; -------------------------------------------------------------------------------- ; @Title: RA8E2 On-Chip Peripherals ; @Props: Released ; @Author: NEJ ; @Changelog: 2025-05-28 NEJ ; @Manufacturer: RENESAS - Renesas Technology, Corp. ; @Doc: Generated (TRACE32, build: 180251.), based on: ; R7FA8E2AF.svd (Ver. 1.0) ; @Core: Cortex-M85 ; @Chip: R7FA8E2AFDCBD ; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; This software is supplied by Renesas Electronics Corporation and is only intended for \n ; use with Renesas products. No other uses are authorized. This software is owned by \n ; Renesas Electronics Corporation and is protected under all applicable laws, including \n ; copyright laws. \n ; \n ; THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING \n ; THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO \n ; WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. \n ; ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT \n ; PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED \n ; COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL \n ; DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE \n ; BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. \n ; \n ; Renesas reserves the right, without notice, to make changes to this software and to \n ; discontinue the availability of this software. By using this software, you agree to \n ; the additional terms and conditions found by accessing the following link: \n ; http://www.renesas.com/disclaimer \n ; \n ; -------------------------------------------------------------------------------- ; $Id: perra8e2.per 19553 2025-05-28 13:14:58Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 tree "Core Registers (Cortex-M85)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x13 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 27. " DISCRITAXIRUW ,Disable critical AXI read under write" "No,Yes" bitfld.long 0x00 15. " DISCRITAXIRUR ,Disable critical AXI read-under-read" "No,Yes" bitfld.long 0x00 14. " EVENTBUSEN ,Enable EVENTBUS output" "Disabled,Enabled" newline bitfld.long 0x00 13. " EVENTBUSEN_S ,Enable Secure-only EVENTBUSEN" "Disabled,Enabled" bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes" bitfld.long 0x00 11. " DISNWAMODE ,Disable no write allocate mode" "No,Yes" newline bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes" line.long 0x04 "CPPWR,Coprocessor Power Control Register" bitfld.long 0x04 23. " SUS11 ,State unknown secure only" "Both states,Secure only" bitfld.long 0x04 22. " SU11 ,State UNKNOWN 11" "Not permitted,Permitted" bitfld.long 0x04 21. " SUS10 ,State unknown secure only" "Both states,Secure only" newline bitfld.long 0x04 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x04 15. " SUS7 ,State unknown secure only" "Both states,Secure only" bitfld.long 0x04 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted" newline bitfld.long 0x04 13. " SUS6 ,State unknown secure only" "Both states,Secure only" bitfld.long 0x04 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x04 11. " SUS5 ,State unknown secure only" "Both states,Secure only" newline bitfld.long 0x04 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x04 9. " SUS4 ,State unknown secure only" "Both states,Secure only" bitfld.long 0x04 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted" newline bitfld.long 0x04 7. " SUS3 ,State unknown secure only" "Both states,Secure only" bitfld.long 0x04 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x04 5. " SUS2 ,State unknown secure only" "Both states,Secure only" newline bitfld.long 0x04 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x04 3. " SUS1 ,State unknown secure only" "Both states,Secure only" bitfld.long 0x04 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted" newline bitfld.long 0x04 1. " SUS0 ,State unknown secure only" "Both states,Secure only" bitfld.long 0x04 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted" line.long 0x08 "SYST_CSR,SysTick Control and Status Register" bitfld.long 0x08 16. " COUNTFLAG ,Counter flag" "Not counted,Counted" bitfld.long 0x08 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x08 1. " TICKINT ,Tick interrupt" "No SysTick,SysTick" newline bitfld.long 0x08 0. " ENABLE ,SysTick enable" "Disabled,Enabled" line.long 0x0C "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x0C 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x10 "SYST_CVR,SysTick Current Value Register" hexmask.long.tbyte 0x10 0.--23. 1. " CURRENT ,Current counter value" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPUID Base Register" abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited" bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15" bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8.1-M w/ Main Extension" newline abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xD23=Cortex-M85" bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control and State Register" setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMI_SET/CLR ,On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSV_SET/CLR ,On writes allows the PendSV exception for the selected security state to be set as pending on reads indicates whether the PendSV for the selected security state exception is pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDST_SET/CLR ,On writes sets the SysTick exception as pending on reads indicates the current state of the exception" "Not pending,Pending" newline bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is secure or non-secure" "Secure,Non-secure" rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled" rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt generated by the NVIC is pending" "Not pending,Pending" newline rhexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt" rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent" rhexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector key" rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian" bitfld.long 0x08 14. " PRIS ,Prioritize secure exceptions" "Disabled,Enabled" newline bitfld.long 0x08 13. " BFHFNMINS ,BusFault HardFault and NMI non-secure enable" "Disabled,Enabled" bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping group priority field bits/subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" bitfld.long 0x08 5. " IESB ,Implicit ESB enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " DIT ,Data Independent Timing" "Not guaranteed,Guaranteed" bitfld.long 0x08 3. " SYSRESETREQS ,System reset request secure only" "Both states,Secure only" bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested" newline bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" newline bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether on an exit from an ISR that returns to the base level of execution priority the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration and Control Register" bitfld.long 0x10 20. " TRD ,Thread reentrancy disabled. Enables checking for exception stack frame integrity signatures on SG instructions" "Disabled,Enabled" bitfld.long 0x10 19. " LOB ,Loop and branch info cache enable" "Disabled,Enabled" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" newline bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored" newline bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise bus faults on handlers running at a requested priority less than 0" "Not ignored,Ignored" bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled" bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled" newline bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled" line.long 0x14 "SHPR1,System Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7 SecureFault" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6 UsageFault" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5 BusFault" newline hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4 MemManage" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11 SVCall" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15 SysTick" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14 PendSV" hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12 DebugMonitor" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending" bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending" bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled" newline bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled" newline bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending" newline bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active" newline bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active" bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active" newline bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active" bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected security state" "Not active,Active" newline bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active" group.byte 0xD28++0x01 line.byte 0x00 "MMFSR,MemManage Fault Register" bitfld.byte 0x00 7. " MMARVALID ,Address valid flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,Stacking access violations" "Not occurred,Occurred" newline bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking access violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data access violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction access violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address valid flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred" newline bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" newline bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x01 line.word 0x00 "UFSR,UsageFault Status Register" eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error" newline eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" eventfld.word 0x00 1. " INVSTATE ,Invalid combination of EPSR and instruction" "No error,Error" newline eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x0F line.long 0x00 "HFSR,HardFault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" eventfld.long 0x04 5. " PMU ,PMU event" "Not occurred,Occurred" eventfld.long 0x04 4. " EXTERNAL ,Eternal event" "Not occurred,Occurred" eventfld.long 0x04 3. " VCATCH ,Vector catch event" "Not occurred,Occurred" newline eventfld.long 0x04 2. " DWTTRAP ,Watchpoint event" "Not occurred,Occurred" eventfld.long 0x04 1. " BKPT ,Breakpoint event" "Not occurred,Occurred" eventfld.long 0x04 0. " HALTED ,Halt or step event" "Not occurred,Occurred" line.long 0x08 "MMFAR,MemManage Fault Address Register" line.long 0x0C "BFAR,BusFault Address Register" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD28))&0x700)==0x700) group.long 0xD3C++0x03 line.long 0x00 "AFSR,Auxiliary Fault Status Register" bitfld.long 0x00 30. " FPOISON ,Fetch fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred" bitfld.long 0x00 29. " FTGU ,Fetch fault caused by TCM gate unit (TGU) security violation" "Not occurred,Occurred" bitfld.long 0x00 28. " FECC ,Fetch fault caused by uncorrectable error correcting code (ECC) error" "Not occurred,Occurred" newline bitfld.long 0x00 27. " FMAXITYPE ,AXI response that caused the fetch fault" "SLVERR,DECERR" bitfld.long 0x00 24. " FMAXI ,Fetch fault on master AXI interface" "Not occurred,Occurred" bitfld.long 0x00 22. " FDTCM ,Fetch fault on data tightly coupled memory (DTCM) interface" "Not occurred,Occurred" newline bitfld.long 0x00 21. " FITCM ,Fetch fault on instruction tightly coupled memory (ITCM) interface" "Not occurred,Occurred" bitfld.long 0x00 19. " PPOISON ,Precise fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred" bitfld.long 0x00 18. " PTGU ,Precise fault caused by TGU security violation" "Not occurred,Occurred" newline bitfld.long 0x00 17. " PECC ,Precise fault caused by uncorrectable ECC error" "Not occurred,Occurred" bitfld.long 0x00 16. " PMAXITYPE ,AXI response that caused the precise fault" "SLVERR,DECERR" bitfld.long 0x00 15. " PIPPB ,Precise fault on internal private peripheral bus (IPPB) interface" "Not occurred,Occurred" newline bitfld.long 0x00 14. " PEPPB ,Precise fault on external private peripheral bus (EPPB) interface" "Not occurred,Occurred" bitfld.long 0x00 13. " PMAXI ,Precise fault on M-AXI interface" "Not occurred,Occurred" bitfld.long 0x00 12. " PPAHB ,Precise fault on peripheral AHB (P-AHB) interface" "Not occurred,Occurred" newline bitfld.long 0x00 11. " PDTCM ,Precise fault on DTCM interface" "Not occurred,Occurred" bitfld.long 0x00 10. " PITCM ,Precise fault on ITCM interface" "Not occurred,Occurred" bitfld.long 0x00 9. " IPOISON ,Imprecise BusFault because of RPOISON" "Not occurred,Occurred" newline bitfld.long 0x00 7. " IECC ,Imprecise fault caused by uncorrectable ECC error" "Not occurred,Occurred" bitfld.long 0x00 6. " IMAXITYPE ,AXI response that caused the imprecise fault" "SLVERR,DECERR" bitfld.long 0x00 4. " IEPPB ,Imprecise fault on EPPB interface" "Not occurred,Occurred" newline bitfld.long 0x00 3. " IMAXI ,Imprecise fault on M-AXI interface" "Not occurred,Occurred" bitfld.long 0x00 2. " IPAHB ,Imprecise fault on P-AHB interface" "Not occurred,Occurred" bitfld.long 0x00 1. " IDTCM ,Imprecise fault on DTCM interface" "Not occurred,Occurred" newline bitfld.long 0x00 0. " IITCM ,Imprecise fault on ITCM interface" "Not occurred,Occurred" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD28))&0x700)==0x600) group.long 0xD3C++0x03 line.long 0x00 "AFSR,Auxiliary Fault Status Register" bitfld.long 0x00 19. " PPOISON ,Precise fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred" bitfld.long 0x00 18. " PTGU ,Precise fault caused by TGU security violation" "Not occurred,Occurred" bitfld.long 0x00 17. " PECC ,Precise fault caused by uncorrectable ECC error" "Not occurred,Occurred" newline bitfld.long 0x00 16. " PMAXITYPE ,AXI response that caused the precise fault" "SLVERR,DECERR" bitfld.long 0x00 15. " PIPPB ,Precise fault on internal private peripheral bus (IPPB) interface" "Not occurred,Occurred" bitfld.long 0x00 14. " PEPPB ,Precise fault on external private peripheral bus (EPPB) interface" "Not occurred,Occurred" newline bitfld.long 0x00 13. " PMAXI ,Precise fault on M-AXI interface" "Not occurred,Occurred" bitfld.long 0x00 12. " PPAHB ,Precise fault on peripheral AHB (P-AHB) interface" "Not occurred,Occurred" bitfld.long 0x00 11. " PDTCM ,Precise fault on DTCM interface" "Not occurred,Occurred" newline bitfld.long 0x00 10. " PITCM ,Precise fault on ITCM interface" "Not occurred,Occurred" bitfld.long 0x00 9. " IPOISON ,Imprecise BusFault because of RPOISON" "Not occurred,Occurred" bitfld.long 0x00 7. " IECC ,Imprecise fault caused by uncorrectable ECC error" "Not occurred,Occurred" newline bitfld.long 0x00 6. " IMAXITYPE ,AXI response that caused the imprecise fault" "SLVERR,DECERR" bitfld.long 0x00 4. " IEPPB ,Imprecise fault on EPPB interface" "Not occurred,Occurred" bitfld.long 0x00 3. " IMAXI ,Imprecise fault on M-AXI interface" "Not occurred,Occurred" newline bitfld.long 0x00 2. " IPAHB ,Imprecise fault on P-AHB interface" "Not occurred,Occurred" bitfld.long 0x00 1. " IDTCM ,Imprecise fault on DTCM interface" "Not occurred,Occurred" bitfld.long 0x00 0. " IITCM ,Imprecise fault on ITCM interface" "Not occurred,Occurred" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD28))&0x700)==0x500) group.long 0xD3C++0x03 line.long 0x00 "AFSR,Auxiliary Fault Status Register" bitfld.long 0x00 30. " FPOISON ,Fetch fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred" bitfld.long 0x00 29. " FTGU ,Fetch fault caused by TCM gate unit (TGU) security violation" "Not occurred,Occurred" bitfld.long 0x00 28. " FECC ,Fetch fault caused by uncorrectable error correcting code (ECC) error" "Not occurred,Occurred" newline bitfld.long 0x00 27. " FMAXITYPE ,AXI response that caused the fetch fault" "SLVERR,DECERR" bitfld.long 0x00 24. " FMAXI ,Fetch fault on master AXI interface" "Not occurred,Occurred" bitfld.long 0x00 22. " FDTCM ,Fetch fault on data tightly coupled memory (DTCM) interface" "Not occurred,Occurred" newline bitfld.long 0x00 21. " FITCM ,Fetch fault on instruction tightly coupled memory (ITCM) interface" "Not occurred,Occurred" bitfld.long 0x00 9. " IPOISON ,Imprecise BusFault because of RPOISON" "Not occurred,Occurred" bitfld.long 0x00 7. " IECC ,Imprecise fault caused by uncorrectable ECC error" "Not occurred,Occurred" newline bitfld.long 0x00 6. " IMAXITYPE ,AXI response that caused the imprecise fault" "SLVERR,DECERR" bitfld.long 0x00 4. " IEPPB ,Imprecise fault on EPPB interface" "Not occurred,Occurred" bitfld.long 0x00 3. " IMAXI ,Imprecise fault on M-AXI interface" "Not occurred,Occurred" newline bitfld.long 0x00 2. " IPAHB ,Imprecise fault on P-AHB interface" "Not occurred,Occurred" bitfld.long 0x00 1. " IDTCM ,Imprecise fault on DTCM interface" "Not occurred,Occurred" bitfld.long 0x00 0. " IITCM ,Imprecise fault on ITCM interface" "Not occurred,Occurred" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD28))&0x700)==0x400) group.long 0xD3C++0x03 line.long 0x00 "AFSR,Auxiliary Fault Status Register" bitfld.long 0x00 9. " IPOISON ,Imprecise BusFault because of RPOISON" "Not occurred,Occurred" bitfld.long 0x00 7. " IECC ,Imprecise fault caused by uncorrectable ECC error" "Not occurred,Occurred" bitfld.long 0x00 6. " IMAXITYPE ,AXI response that caused the imprecise fault" "SLVERR,DECERR" newline bitfld.long 0x00 4. " IEPPB ,Imprecise fault on EPPB interface" "Not occurred,Occurred" bitfld.long 0x00 3. " IMAXI ,Imprecise fault on M-AXI interface" "Not occurred,Occurred" bitfld.long 0x00 2. " IPAHB ,Imprecise fault on P-AHB interface" "Not occurred,Occurred" newline bitfld.long 0x00 1. " IDTCM ,Imprecise fault on DTCM interface" "Not occurred,Occurred" bitfld.long 0x00 0. " IITCM ,Imprecise fault on ITCM interface" "Not occurred,Occurred" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD28))&0x700)==0x300) group.long 0xD3C++0x03 line.long 0x00 "AFSR,Auxiliary Fault Status Register" bitfld.long 0x00 30. " FPOISON ,Fetch fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred" bitfld.long 0x00 29. " FTGU ,Fetch fault caused by TCM gate unit (TGU) security violation" "Not occurred,Occurred" bitfld.long 0x00 28. " FECC ,Fetch fault caused by uncorrectable error correcting code (ECC) error" "Not occurred,Occurred" newline bitfld.long 0x00 27. " FMAXITYPE ,AXI response that caused the fetch fault" "SLVERR,DECERR" bitfld.long 0x00 24. " FMAXI ,Fetch fault on master AXI interface" "Not occurred,Occurred" bitfld.long 0x00 22. " FDTCM ,Fetch fault on data tightly coupled memory (DTCM) interface" "Not occurred,Occurred" newline bitfld.long 0x00 21. " FITCM ,Fetch fault on instruction tightly coupled memory (ITCM) interface" "Not occurred,Occurred" bitfld.long 0x00 19. " PPOISON ,Precise fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred" bitfld.long 0x00 18. " PTGU ,Precise fault caused by TGU security violation" "Not occurred,Occurred" newline bitfld.long 0x00 17. " PECC ,Precise fault caused by uncorrectable ECC error" "Not occurred,Occurred" bitfld.long 0x00 16. " PMAXITYPE ,AXI response that caused the precise fault" "SLVERR,DECERR" bitfld.long 0x00 15. " PIPPB ,Precise fault on internal private peripheral bus (IPPB) interface" "Not occurred,Occurred" newline bitfld.long 0x00 14. " PEPPB ,Precise fault on external private peripheral bus (EPPB) interface" "Not occurred,Occurred" bitfld.long 0x00 13. " PMAXI ,Precise fault on M-AXI interface" "Not occurred,Occurred" bitfld.long 0x00 12. " PPAHB ,Precise fault on peripheral AHB (P-AHB) interface" "Not occurred,Occurred" newline bitfld.long 0x00 11. " PDTCM ,Precise fault on DTCM interface" "Not occurred,Occurred" bitfld.long 0x00 10. " PITCM ,Precise fault on ITCM interface" "Not occurred,Occurred" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD28))&0x700)==0x200) group.long 0xD3C++0x03 line.long 0x00 "AFSR,Auxiliary Fault Status Register" bitfld.long 0x00 19. " PPOISON ,Precise fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred" bitfld.long 0x00 18. " PTGU ,Precise fault caused by TGU security violation" "Not occurred,Occurred" bitfld.long 0x00 17. " PECC ,Precise fault caused by uncorrectable ECC error" "Not occurred,Occurred" newline bitfld.long 0x00 16. " PMAXITYPE ,AXI response that caused the precise fault" "SLVERR,DECERR" bitfld.long 0x00 15. " PIPPB ,Precise fault on internal private peripheral bus (IPPB) interface" "Not occurred,Occurred" bitfld.long 0x00 14. " PEPPB ,Precise fault on external private peripheral bus (EPPB) interface" "Not occurred,Occurred" newline bitfld.long 0x00 13. " PMAXI ,Precise fault on M-AXI interface" "Not occurred,Occurred" bitfld.long 0x00 12. " PPAHB ,Precise fault on peripheral AHB (P-AHB) interface" "Not occurred,Occurred" bitfld.long 0x00 11. " PDTCM ,Precise fault on DTCM interface" "Not occurred,Occurred" newline bitfld.long 0x00 10. " PITCM ,Precise fault on ITCM interface" "Not occurred,Occurred" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD28))&0x700)==0x100) group.long 0xD3C++0x03 line.long 0x00 "AFSR,Auxiliary Fault Status Register" bitfld.long 0x00 30. " FPOISON ,Fetch fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred" bitfld.long 0x00 29. " FTGU ,Fetch fault caused by TCM gate unit (TGU) security violation" "Not occurred,Occurred" bitfld.long 0x00 28. " FECC ,Fetch fault caused by uncorrectable error correcting code (ECC) error" "Not occurred,Occurred" newline bitfld.long 0x00 27. " FMAXITYPE ,AXI response that caused the fetch fault" "SLVERR,DECERR" bitfld.long 0x00 24. " FMAXI ,Fetch fault on master AXI interface" "Not occurred,Occurred" bitfld.long 0x00 22. " FDTCM ,Fetch fault on data tightly coupled memory (DTCM) interface" "Not occurred,Occurred" newline bitfld.long 0x00 21. " FITCM ,Fetch fault on instruction tightly coupled memory (ITCM) interface" "Not occurred,Occurred" else group.long 0xD3C++0x03 line.long 0x00 "AFSR,Auxiliary Fault Status Register" endif group.long 0xD88++0x07 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Denied,Privileged,Reserved,Full" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,Reserved,Full" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,Reserved,Full" newline bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,Reserved,Full" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,Reserved,Full" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,Reserved,Full" newline bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,Reserved,Full" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,Reserved,Full" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,Reserved,Full" newline bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,Reserved,Full" line.long 0x04 "NSACR,Non-secure Access Control Register" bitfld.long 0x04 11. " CP11 ,Enables non-secure access to coprocessor CP11" "Disabled,Enabled" bitfld.long 0x04 10. " CP10 ,Enables non-secure access to coprocessor CP10" "Disabled,Enabled" bitfld.long 0x04 7. " CP7 ,Enables non-secure access to coprocessor CP7" "Disabled,Enabled" newline bitfld.long 0x04 6. " CP6 ,Enables non-secure access to coprocessor CP6" "Disabled,Enabled" bitfld.long 0x04 5. " CP5 ,Enables non-secure access to coprocessor CP5" "Disabled,Enabled" bitfld.long 0x04 4. " CP4 ,Enables non-secure access to coprocessor CP4" "Disabled,Enabled" newline bitfld.long 0x04 3. " CP3 ,Enables non-secure access to coprocessor CP3" "Disabled,Enabled" bitfld.long 0x04 2. " CP2 ,Enables non-secure access to coprocessor CP2" "Disabled,Enabled" bitfld.long 0x04 1. " CP1 ,Enables non-secure access to coprocessor CP1" "Disabled,Enabled" newline bitfld.long 0x04 0. " CP0 ,Enables non-secure access to coprocessor CP0" "Disabled,Enabled" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Triggered Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended" wgroup.long 0x10700++0x03 line.long 0x00 "CFGINFOSEL,Processor Configuration Information Selection Register" rgroup.long 0x10704++0x03 line.long 0x00 "CFGINFORD,Processor Configuration Information Read Data Register" group.long 0x10004++0x03 line.long 0x00 "PFCR,Prefetcher Control Register" bitfld.long 0x00 7. " DIS_NLP ,Disables Next Line Prefetch mode" "No,Yes" bitfld.long 0x00 0. " ENABLE ,Prefetcher enable" "Disabled,Enabled" width 10. tree "Memory System" rgroup.long 0xD78++0x03 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,?..." bitfld.long 0x00 27.--29. " LOUU ,Level of unification uniprocessor" "Not implemented,Level 1,?..." bitfld.long 0x00 24.--26. " LOC ,Level of coherency" "Not implemented,Level 1,?..." newline bitfld.long 0x00 21.--23. " LOUIS ,Level of unification inner shareable" "Not implemented,Level 1,?..." bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..." if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C))&0xE0000000)==0x80000000) rgroup.long 0xD7C++0x03 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,Reserved,Reserved,Reserved,Cache,?..." bitfld.long 0x00 24.--27. " CWG ,Cache write-back granule" "No Cache,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,?..." bitfld.long 0x00 20.--23. " ERG ,Exclusives reservation granule" "Not provided,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,?..." newline bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0xD7C++0x03 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,Reserved,Reserved,Reserved,Cache,?..." endif rgroup.long 0xD80++0x03 line.long 0x00 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. " WT ,Indicates support available for write-through" "Reserved,Supported" bitfld.long 0x00 30. " WB ,Indicates support available for write-back" "Reserved,Supported" bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Reserved,Supported" newline bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Reserved,Supported" hexmask.long.word 0x00 13.--27. 0x20 " NUMSETS ,Indicates the number of sets as (number of sets) - 1" hexmask.long.word 0x00 3.--12. 0x08 " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1" newline bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "Reserved,32 bytes,?..." group.long 0xD84++0x03 line.long 0x00 "CSSELR,Cache Size Selection Register" rbitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,?..." bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data,Instruction" wgroup.long 0xF50++0x03 line.long 0x00 "ICIALLU,I-Cache Invalidate All To PoU" wgroup.long 0xF58++0x1F line.long 0x00 "ICIMVAU,I-Cache Invalidate By MVA To PoU" line.long 0x04 "DCIMVAC,D-Cache Invalidate By MVA To PoC" line.long 0x08 "DCISW,D-Cache Invalidate By Set-Way" hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on" bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on minus 1" "L1,L2,L3,L4,L5,L6,L7,L8" line.long 0x0C "DCCMVAU,D-Cache Clean By MVA To PoU" line.long 0x10 "DCCMVAC,D-Cache Clean By MVA To PoC" line.long 0x14 "DCCSW,D-Cache Clean By Set-Way" hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on" bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on minus" "L1,L2,L3,L4,L5,L6,L7,L8" line.long 0x18 "DCCIMVAC,D-Cache Clean And Invalidate By MVA To PoC" line.long 0x1C "DCCISW,D-Cache Clean And Invalidate By Set-Way" hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on" bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on minus" "L1,L2,L3,L4,L5,L6,L7,L8" group.long 0x10010++0x0B line.long 0x00 "ITCMCR,Instruction TCM Control Register" rbitfld.long 0x00 3.--6. " SZ ,TCM size" "Not implemented,Reserved,Reserved,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB" bitfld.long 0x00 0. " EN ,TCM enable" "Disabled,Enabled" line.long 0x04 "DTCMCR,Data TCM Control Register" rbitfld.long 0x04 3.--6. " SZ ,TCM size" "Not implemented,Reserved,Reserved,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB" bitfld.long 0x04 0. " EN ,TCM enable" "Disabled,Enabled" line.long 0x08 "PAHBCR,P-AHB Control Register" rbitfld.long 0x08 1.--3. " SZ ,P-AHB size" "Disabled,64 MB,128 MB,256 MB,512 MB,?..." bitfld.long 0x08 0. " EN ,P-AHB enable" "Disabled,Enabled" repeat 2. (increment 0x10100 0x04) (increment 0. 1.) group.long $1++0x03 line.long 0x00 "IEBR$2,Instruction Cache Error Bank Register $2" bitfld.long 0x00 30.--31. " SWDEF ,User-defined" "0,1,2,3" bitfld.long 0x00 16. " BANK ,Indicates which RAM bank to use" "Tag,Data" bitfld.long 0x00 15. " LOC_WAY ,Indicates the location in instruction cache RAM (way)" "0,1" newline hexmask.long.word 0x00 5.--14. 0x20 " LOC_INDEX ,Indicates the location in instruction cache RAM (index)" bitfld.long 0x00 2.--4. " LOC_OFFSET ,Indicates the location in instruction cache RAM (offset)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" newline bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" repeat.end repeat 2. (increment 0x10110 0x04) (increment 0. 1.) group.long $1++0x03 line.long 0x00 "DEBR$2,Data Cache Error Bank Register $2" bitfld.long 0x00 30.--31. " SWDEF ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TYPE ,Indicates the error type" "Single-bit,Multi-bit" bitfld.long 0x00 16. " BANK ,Indicates which RAM bank to use" "Tag,Data" newline bitfld.long 0x00 14.--15. " LOC_WAY ,Indicates the location in instruction cache RAM (way)" "0,1,2,3" hexmask.long.word 0x00 5.--13. 0x20 " LOC_INDEX ,Indicates the location in instruction cache RAM (index)" bitfld.long 0x00 2.--4. " LOC_OFFSET ,Indicates the location in instruction cache RAM (offset)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" repeat.end repeat 2. (increment 0x10120 0x04) (increment 0. 1.) group.long $1++0x03 line.long 0x00 "TEBR$2,TCM Error Bank Register $2" bitfld.long 0x00 30.--31. " SWDEF ,User-defined" "0,1,2,3" bitfld.long 0x00 28. " POISON ,Indicates whether a BusFault is generated or not" "Not generated,Generated" bitfld.long 0x00 27. " TYPE ,Indicates the error type" "Single-bit,Multi-bit" newline bitfld.long 0x00 24.--26. " BANK ,Indicates which RAM bank to use" "DTCM0,DTCM1,DTCM2,DTCM3,ITCM,?..." hexmask.long.tbyte 0x00 3.--23. 0x08 " LOCATION ,Indicates the location in data cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" newline bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" repeat.end group.long 0x10000++0x03 line.long 0x00 "MSCR,Memory System Control Register" rbitfld.long 0x00 17. " CPWRDN ,Data and instruction caches powered down or automatic invalidation enable" "Disabled,Enabled" bitfld.long 0x00 16. " DCCLEAN ,Data cache contains any dirty lines" "Contained,Not contained" bitfld.long 0x00 13. " ICACTIVE ,L1 instruction cache is active" "Not active,Active" newline bitfld.long 0x00 12. " DCACTIVE ,L1 data cache is active" "Not active,Active" bitfld.long 0x00 3. " EVECCFAULT ,Enables asynchronous BusFault exceptions when data is lost on evictions" "Disabled,Enabled" bitfld.long 0x00 2. " FORCEWT ,Enables forced write-through in the L1 data cache" "Disabled,Enabled" newline rbitfld.long 0x00 1. " ECCEN ,Indicates whether error correcting code is present and enabled" "Disabled,Enabled" newline rgroup.long 0x10200++0x07 line.long 0x00 "DCADCRR,Direct Cache Access Data Cache Read Register" bitfld.long 0x00 23.--25. " STATUS ,Clean or dirty transient and outer attributes of the cache line" "Clean/transient/unknown,Clean/not transient/unknown,Dirty/not transient/Non-cacheable,Dirty/Not transient/Non-cacheable/W-back/W-allocate,Dirty/not transient/W-back/no W-allocate,Dirty/not transient/W-through/W-allocate,Dirty/Not transient/W-through/no W-allocate,?..." newline bitfld.long 0x00 22. " VALID ,Valid state of the data cache line entry" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--21. 0x01 " TAG ,Tag address" line.long 0x04 "DCAICRR,Direct Cache Access Instruction Cache Read Register" bitfld.long 0x04 21. " VALID ,Valid state of the instruction cache line" "Not valid,Valid" hexmask.long.tbyte 0x04 0.--20. 0x01 " TAG ,Tag address" newline group.long 0x10210++0x07 line.long 0x00 "DCADCLR,Direct Cache Access Location Register" rbitfld.long 0x00 30.--31. " WAY ,Cache way" "0,1,2,3" rhexmask.long.word 0x00 5.--13. 0x20 " SET ,Set index" rbitfld.long 0x00 2.--4. " OFFSET ,Data offset" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 0. " RAMTYPE ,RAM type" "Tag,Data" line.long 0x04 "DCAICLR,Direct Cache Access Location Register" rbitfld.long 0x04 30. " WAY ,Cache way" "0,1" rhexmask.long.word 0x04 5.--14. 0x20 " SET ,Set index" rbitfld.long 0x04 2.--4. " OFFSET ,Data offset" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 0. " RAMTYPE ,RAM type" "Tag,Data" tree.end tree "Feature Registers" rgroup.long 0xD40++0x37 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " RAS ,Identifies which version of the RAS architecture is implemented" "Reserved,Reserved,Version 1,?..." bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" "Reserved,Reserved,2-stack,?..." bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,Reserved,Implemented with state handling,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 28.--31. " UDE ,Unprivileged debug extension" "Not implemented,Implemented,?..." bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug indicates the supported M-profile debug architecture" "Not supported,Reserved,ARMv8-M Debug architecture,?..." line.long 0x0C "ID_AFR0,Auxiliary Feature Register 0" line.long 0x10 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x10 20.--23. " AUXREG ,Indicates the support for auxiliary registers" "Not supported,Supported,?..." bitfld.long 0x10 16.--19. " TCM ,Indicates the support for tightly coupled memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x10 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..." newline bitfld.long 0x10 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" bitfld.long 0x10 4.--7. " PMSASUP ,Indicates support for a PMSA" "Reserved,Reserved,Reserved,Reserved,PMSAv8,?..." line.long 0x14 "ID_MMFR1,Memory Model Feature Register 1" line.long 0x18 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x18 24.--27. " WFISTALL ,Indicates the support for wait for interrupt (WFI) stalling" "Not supported,Supported,?..." line.long 0x1C "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x1C 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..." bitfld.long 0x1C 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..." bitfld.long 0x1C 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..." line.long 0x20 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x20 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Reserved,SDIV/UDIV,?..." bitfld.long 0x20 20.--23. " DEBUG ,Indicates the supported debug instructions" "Reserved,BKPT,?..." bitfld.long 0x20 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x20 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Reserved,CBNZ/CBZ,Reserved,CBNZ/CBZ with looping,?..." bitfld.long 0x20 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Reserved,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x20 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Reserved,CLZ supported,?..." line.long 0x24 "ID_ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x24 24.--27. " INTERWORK ,Indicates the supported interworking instructions" "Reserved,Reserved,BX/BLX,?..." bitfld.long 0x24 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Reserved,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x24 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Reserved,IT,?..." newline bitfld.long 0x24 12.--15. " EXTEND ,Indicates the supported extend instructions" "Reserved,Basic,Extended,?..." line.long 0x28 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x28 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Reserved,Reserved,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x28 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Reserved,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x28 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Reserved,SMULL/SMLAL,Reserved,SMULL/SMLAL/DSP,?..." newline bitfld.long 0x28 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Reserved,Reserved,MUL/MLA/MLS,?..." bitfld.long 0x28 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x28 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Reserved,Reserved,Reserved,PLD/PLI,?..." newline bitfld.long 0x28 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Reserved,Reserved,Load-acquire/Store-release/Exclusive,?..." line.long 0x2C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x2C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Reserved,Supported,?..." bitfld.long 0x2C 20.--23. " T32COPY ,Indicates the supported non flag-setting MOV instructions" "Reserved,Supported,?..." bitfld.long 0x2C 16.--19. " TABBRANCH ,Indicates the supported table branch instructions" "Reserved,TBB/TBH,?..." newline bitfld.long 0x2C 12.--15. " SYNCHPRIM ,Indicates the supported table branch instructions" "Reserved,Supported,?..." bitfld.long 0x2C 8.--11. " SVC ,Indicates the supported SVC instructions" "Reserved,SVC,?..." bitfld.long 0x2C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Reserved,Supported,Reserved,Extended,?..." newline bitfld.long 0x2C 0.--3. " SATURATE ,Indicates the supported saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..." line.long 0x30 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x30 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Reserved,CPS/MRS/MSR,?..." bitfld.long 0x30 20.--23. " SYNCHPRIMFRAC ,Indicate the implemented synchronization primitive instructions" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x30 16.--19. " BARRIER ,Indicates the supported barrier instructions" "Reserved,CSDB/DMB/DSB/ISB/PSSBB/SSBB,?..." newline bitfld.long 0x30 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Reserved,Supported,?..." bitfld.long 0x30 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x30 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Reserved,Reserved,Supported,?..." line.long 0x34 "ID_ISAR5,Instruction Set Attributes Register 5" bitfld.long 0x34 20.--23. " PACBTI ,Pointer authentication algorithm" "Not implemented,QARMA5,Implementation defined,Reserved,QARMA3,?..." tree.end newline rgroup.long 0xFBC++0x03 line.long 0x00 "DDEVARCH,CoreSight Device Architecture Register" hexmask.long.word 0x00 21.--31. 0x20 " ARCHITECT ,Component architect" bitfld.long 0x00 20. " PRESENT ,Register present" "Reserved,Present" bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "M-Profile V3.0,?..." newline bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "Reserved,Reserved,M-Profile V3.0,?..." hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part" rgroup.long 0xFCC++0x03 line.long 0x00 "DDEVTYPE,SCS Device Type Register" bitfld.long 0x00 4.--7. " SUB ,Component sub-type" "Other,?..." bitfld.long 0x00 0.--3. " MAJOR ,CoreSight major type" "Miscellaneous,?..." rgroup.long 0xCFC++0x03 line.long 0x00 "REVIDR,Revision ID Register" width 8. tree "Peripheral Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "DPIDR0,CoreSight Peripheral ID Register 0" hexmask.long.byte 0x00 0.--7. 1. " PART_NUM[7:0] ,Part number bits[7:0]" line.long 0x04 "DPIDR1,CoreSight Peripheral ID Register 1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " PART_NUM[11:8] ,Part number bits[11:8]" line.long 0x08 "DPIDR2,CoreSight Peripheral ID Register 2" hexmask.long.byte 0x08 4.--7. 1. " REVISION ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "DPIDR3,CoreSight Peripheral ID Register 3" hexmask.long.byte 0x0C 4.--7. 1. " REVAND ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x0F line.long 0x00 "DPIDR4,CoreSight Peripheral ID Register 4" hexmask.long.byte 0x00 4.--7. 1. " COUNT ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" line.long 0x04 "DPIDR5,CoreSight Peripheral ID Register 5" line.long 0x08 "DPIDR6,CoreSight Peripheral ID Register 6" line.long 0x0C "DPIDR7,CoreSight Peripheral ID Register 7" rgroup.long 0xFF0++0x0F line.long 0x00 "DCIDR0,CoreSight Component ID Register 0" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "DCIDR1,CoreSight Component ID Register 1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component identification preamble" line.long 0x08 "DCIDR2,CoreSight Component ID Register 2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0C "DCIDR3,CoreSight Component ID Register 3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end width 12. tree "Reliability, Availability, and Serviceability" base (CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))-0x9000) rgroup.long 0x00++0x03 line.long 0x00 "ERRFR0,RAS Error Record Feature" bitfld.long 0x00 8.--9. " UE ,Enable uncorrected error" "Reserved,Enabled,?..." bitfld.long 0x00 0.--1. " ED ,Error reporting and logging" "Reserved,Enabled,?..." hgroup.long 0x08++0x03 hide.long 0x00 "ERRCTRL0,RAS Error Record Control Register 0" group.long 0x10++0x03 line.long 0x00 "ERRSTATUS0,RAS Error Record Primary Status Register" eventfld.long 0x00 31. " AV ,Address valid" "Not valid,Valid" bitfld.long 0x00 30. " V ,Status valid" "Not valid,Valid" eventfld.long 0x00 29. " UE ,Uncorrected errors" "Not detected,Detected" newline eventfld.long 0x00 28. " ER ,BusFault caused by RAS" "Not occurred,Occurred" eventfld.long 0x00 27. " OF ,RAS event has occurred since the last time ERRSTATUS0.V was cleared" "At most one,At least two" eventfld.long 0x00 26. " MV ,Miscellaneous registers valid" "Not valid,Valid" newline bitfld.long 0x00 24.--25. " CE ,Corrected errors" "Not detected,Reserved,Detected,?..." eventfld.long 0x00 23. " DE ,Deferred errors" "No deferred,Deferred" bitfld.long 0x00 20.--21. " UET ,Uncorrectable error type" "UC,Reserved,Reserved,UER" newline hexmask.long.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code" rgroup.long 0x18++0x07 line.long 0x00 "ERRADDR0,RAS Error Record Address Register" line.long 0x04 "ERRADDR20,RAS Error Record Address Register" bitfld.long 0x04 30. " SI ,Security information incorrect" "Reserved,Not valid" bitfld.long 0x04 29. " AI ,Address incorrect" "Valid,Not valid" hgroup.long 0x20++0x03 hide.long 0x00 "ERRMISC00,RAS Error Record Miscellaneous Register 00" rgroup.long 0x24++0x03 line.long 0x00 "ERRMISC10,RAS Error Record Miscellaneous Register 10" bitfld.long 0x00 0.--1. " TYPE ,Indicates the type of RAS event logged" "L1 instruction,L1 data,By processor,S-AHB" hgroup.long 0x28++0x03 hide.long 0x00 "ERRMISC20,RAS Error Record Miscellaneous Register 20" hgroup.long 0x2C++0x03 hide.long 0x00 "ERRMISC30,RAS Error Record Miscellaneous Register 30" hgroup.long 0x30++0x03 hide.long 0x00 "ERRMISC40,RAS Error Record Miscellaneous Register 40" hgroup.long 0x34++0x03 hide.long 0x00 "ERRMISC50,RAS Error Record Miscellaneous Register 50" hgroup.long 0x38++0x03 hide.long 0x00 "ERRMISC60,RAS Error Record Miscellaneous Register 60" hgroup.long 0x3C++0x03 hide.long 0x00 "ERRMISC70,RAS Error Record Miscellaneous Register 70" rgroup.long 0xE00++0x03 line.long 0x00 "ERRGSR0,RAS Fault Group Status Register" bitfld.long 0x00 0. " ERR0 ,Error record 0 valid" "Not valid,Valid" rgroup.long 0xFC8++0x03 line.long 0x00 "ERRDEVID,RAS Error Record Device ID Register" hexmask.long.word 0x00 0.--15. 1. " NUM ,Maximum error record index+1" group.long 0x9F04++0x03 line.long 0x00 "RFSR,RAS Fault Status Register" eventfld.long 0x00 31. " VALID ,Indicates whether the register is valid" "Not valid,Valid" bitfld.long 0x00 16.--30. " IS ,Implementation-defined syndrome" "L1 instruction,L1 data,TCM ECC,?..." bitfld.long 0x00 0.--1. " UET ,Error type" "Uncontainable,Reserved,Reserved,Recoverable" tree.end tree "TCM Security Gate" base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) group.long 0x10500++0x07 line.long 0x00 "ITGU_CTRL,ITGU Control Register" bitfld.long 0x00 1. " DEREN ,Enable slave AHB error response for TGU fault" "Disabled,Enabled" bitfld.long 0x00 0. " DBFEN ,Enable data side BusFault for TGU fault" "Disabled,Enabled" line.long 0x04 "ITGU_CFG,ITGU Configuration Register" bitfld.long 0x04 31. " PRESENT ,This field determines if the TGU is present" "Not present,Present" bitfld.long 0x04 8.--11. " NUMBLKS ,Number of TCM blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " BLKSZ ,TGU block size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 16. (increment 0x10510 0x04) (increment 0. 1.) group.long $1++0x03 line.long 0x00 "ITGU_LUT$2,ITGU Look Up Table Register $2" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" newline bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" newline bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" newline bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" newline bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" newline bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" newline bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" newline bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" repeat.end group.long 0x10500++0x07 line.long 0x00 "DTGU_CTRL,ITGU Control Register" bitfld.long 0x00 1. " DEREN ,Enable slave AHB error response for TGU fault" "Disabled,Enabled" bitfld.long 0x00 0. " DBFEN ,Enable data side BusFault for TGU fault" "Disabled,Enabled" line.long 0x04 "DTGU_CFG,ITGU Configuration Register" bitfld.long 0x04 31. " PRESENT ,This field determines if the TGU is present" "Not present,Present" bitfld.long 0x04 8.--11. " NUMBLKS ,Number of TCM blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " BLKSZ ,TGU block size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 16. (increment 0x10510 0x04) (increment 0. 1.) group.long $1++0x03 line.long 0x00 "DTGU_LUT$2,ITGU Look Up Table Register $2" bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure" newline bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure" newline bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure" newline bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure" newline bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure" newline bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure" newline bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure" newline bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure" bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure" repeat.end tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 13. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" hexmask.long.byte 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..." group.long 0xD94++0x07 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" line.long 0x04 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x04 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x0 group.long 0xD9C++0x07 "Region 0" saveindex 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR0,MPU Region Attribute And Size Register 0" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveindex 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveindex 0xD98 %l 0x0 hide.long 0x00 "MPU_RLAR0,MPU Region Attribute And Size Register 0" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x1 group.long 0xD9C++0x07 "Region 1" saveindex 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR1,MPU Region Attribute And Size Register 1" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveindex 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveindex 0xD98 %l 0x1 hide.long 0x00 "MPU_RLAR1,MPU Region Attribute And Size Register 1" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x2 group.long 0xD9C++0x07 "Region 2" saveindex 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR2,MPU Region Attribute And Size Register 2" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveindex 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveindex 0xD98 %l 0x2 hide.long 0x00 "MPU_RLAR2,MPU Region Attribute And Size Register 2" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x3 group.long 0xD9C++0x07 "Region 3" saveindex 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR3,MPU Region Attribute And Size Register 3" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveindex 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveindex 0xD98 %l 0x3 hide.long 0x00 "MPU_RLAR3,MPU Region Attribute And Size Register 3" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x4 group.long 0xD9C++0x07 "Region 4" saveindex 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR4,MPU Region Attribute And Size Register 4" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveindex 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveindex 0xD98 %l 0x4 hide.long 0x00 "MPU_RLAR4,MPU Region Attribute And Size Register 4" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x5 group.long 0xD9C++0x07 "Region 5" saveindex 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR5,MPU Region Attribute And Size Register 5" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveindex 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveindex 0xD98 %l 0x5 hide.long 0x00 "MPU_RLAR5,MPU Region Attribute And Size Register 5" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x6 group.long 0xD9C++0x07 "Region 6" saveindex 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR6,MPU Region Attribute And Size Register 6" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveindex 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveindex 0xD98 %l 0x6 hide.long 0x00 "MPU_RLAR6,MPU Region Attribute And Size Register 6" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x7 group.long 0xD9C++0x07 "Region 7" saveindex 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR7,MPU Region Attribute And Size Register 7" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveindex 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveindex 0xD98 %l 0x7 hide.long 0x00 "MPU_RLAR7,MPU Region Attribute And Size Register 7" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x8 group.long 0xD9C++0x07 "Region 8" saveindex 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR8,MPU Region Attribute And Size Register 8" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveindex 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveindex 0xD98 %l 0x8 hide.long 0x00 "MPU_RLAR8,MPU Region Attribute And Size Register 8" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x9 group.long 0xD9C++0x07 "Region 9" saveindex 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR9,MPU Region Attribute And Size Register 9" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveindex 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveindex 0xD98 %l 0x9 hide.long 0x00 "MPU_RLAR9,MPU Region Attribute And Size Register 9" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xA group.long 0xD9C++0x07 "Region 10" saveindex 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR10,MPU Region Attribute And Size Register 10" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveindex 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveindex 0xD98 %l 0xA hide.long 0x00 "MPU_RLAR10,MPU Region Attribute And Size Register 10" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xB group.long 0xD9C++0x07 "Region 11" saveindex 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR11,MPU Region Attribute And Size Register 11" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveindex 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveindex 0xD98 %l 0xB hide.long 0x00 "MPU_RLAR11,MPU Region Attribute And Size Register 11" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xC group.long 0xD9C++0x07 "Region 12" saveindex 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR12,MPU Region Attribute And Size Register 12" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveindex 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveindex 0xD98 %l 0xC hide.long 0x00 "MPU_RLAR12,MPU Region Attribute And Size Register 12" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xD group.long 0xD9C++0x07 "Region 13" saveindex 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR13,MPU Region Attribute And Size Register 13" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveindex 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveindex 0xD98 %l 0xD hide.long 0x00 "MPU_RLAR13,MPU Region Attribute And Size Register 13" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xE group.long 0xD9C++0x07 "Region 14" saveindex 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR14,MPU Region Attribute And Size Register 14" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveindex 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveindex 0xD98 %l 0xE hide.long 0x00 "MPU_RLAR14,MPU Region Attribute And Size Register 14" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xF group.long 0xD9C++0x07 "Region 15" saveindex 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR15,MPU Region Attribute And Size Register 15" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveindex 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveindex 0xD98 %l 0xF hide.long 0x00 "MPU_RLAR15,MPU Region Attribute And Size Register 15" endif tree.end newline repeat 3. (increment 0xDA4 0x08)(increment 1. 1.) group.long $1++0x07 line.long 0x00 "MPU_RBAR_A$2,MPU Region Base Address Register Alias $2" hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" newline bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted" line.long 0x04 "MPU_RLAR_A$2,MPU Region Limit Address Register Alias $2" hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted" bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled" repeat.end newline group.long 0xDC0++0x07 line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x00 24.--27. " ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x00 16.--19. " ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x00 8.--11. " ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x00 0.--3. " ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1" bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x04 24.--27. " ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x04 16.--19. " ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x04 8.--11. " ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x04 0.--3. " ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Security Attribution Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 11. group.long 0xDD0++0x03 line.long 0x00 "SAU_CTRL,SAU Control Register" bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or secure" "Secure,Non-secure" bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled" rgroup.long 0xDD4++0x03 line.long 0x00 "SAU_TYPE,SAU Type Register" hexmask.long.byte 0x00 0.--7. 1. " SREGION ,The number of implemented SAU regions" group.long 0xDD8++0x03 line.long 0x00 "SAU_RNR,SAU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR" tree "SAU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x0 group.long 0xDDC++0x07 "Region 0" saveindex 0xDD8 %l 0x0 line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " BADDR ,Base address of the region" line.long 0x04 "SAU_RLAR0,SAU Region Limit Address Register 0" hexmask.long 0x04 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x04 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x04 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 0 (not implemented)" saveindex 0xDD8 %l 0x0 hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0" hgroup.long 0xDE0++0x03 saveindex 0xDD8 %l 0x0 hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x1 group.long 0xDDC++0x07 "Region 1" saveindex 0xDD8 %l 0x1 line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " BADDR ,Base address of the region" line.long 0x04 "SAU_RLAR1,SAU Region Limit Address Register 1" hexmask.long 0x04 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x04 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x04 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 1 (not implemented)" saveindex 0xDD8 %l 0x1 hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1" hgroup.long 0xDE0++0x03 saveindex 0xDD8 %l 0x1 hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x2 group.long 0xDDC++0x07 "Region 2" saveindex 0xDD8 %l 0x2 line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " BADDR ,Base address of the region" line.long 0x04 "SAU_RLAR2,SAU Region Limit Address Register 2" hexmask.long 0x04 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x04 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x04 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 2 (not implemented)" saveindex 0xDD8 %l 0x2 hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2" hgroup.long 0xDE0++0x03 saveindex 0xDD8 %l 0x2 hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x3 group.long 0xDDC++0x07 "Region 3" saveindex 0xDD8 %l 0x3 line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " BADDR ,Base address of the region" line.long 0x04 "SAU_RLAR3,SAU Region Limit Address Register 3" hexmask.long 0x04 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x04 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x04 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 3 (not implemented)" saveindex 0xDD8 %l 0x3 hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3" hgroup.long 0xDE0++0x03 saveindex 0xDD8 %l 0x3 hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x4 group.long 0xDDC++0x07 "Region 4" saveindex 0xDD8 %l 0x4 line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " BADDR ,Base address of the region" line.long 0x04 "SAU_RLAR4,SAU Region Limit Address Register 4" hexmask.long 0x04 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x04 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x04 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 4 (not implemented)" saveindex 0xDD8 %l 0x4 hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4" hgroup.long 0xDE0++0x03 saveindex 0xDD8 %l 0x4 hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x5 group.long 0xDDC++0x07 "Region 5" saveindex 0xDD8 %l 0x5 line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " BADDR ,Base address of the region" line.long 0x04 "SAU_RLAR5,SAU Region Limit Address Register 5" hexmask.long 0x04 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x04 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x04 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 5 (not implemented)" saveindex 0xDD8 %l 0x5 hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5" hgroup.long 0xDE0++0x03 saveindex 0xDD8 %l 0x5 hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x6 group.long 0xDDC++0x07 "Region 6" saveindex 0xDD8 %l 0x6 line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " BADDR ,Base address of the region" line.long 0x04 "SAU_RLAR6,SAU Region Limit Address Register 6" hexmask.long 0x04 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x04 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x04 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 6 (not implemented)" saveindex 0xDD8 %l 0x6 hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6" hgroup.long 0xDE0++0x03 saveindex 0xDD8 %l 0x6 hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x7 group.long 0xDDC++0x07 "Region 7" saveindex 0xDD8 %l 0x7 line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " BADDR ,Base address of the region" line.long 0x04 "SAU_RLAR7,SAU Region Limit Address Register 7" hexmask.long 0x04 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x04 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x04 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 7 (not implemented)" saveindex 0xDD8 %l 0x7 hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7" hgroup.long 0xDE0++0x03 saveindex 0xDD8 %l 0x7 hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7" endif tree.end newline group.long 0xDE4++0x07 line.long 0x00 "SFSR,Secure Fault Status Register" bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred" bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid" bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred" newline bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred" bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred" bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred" bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred" line.long 0x04 "SFAR,Secure Fault Address Register" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Control Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total number of interrupt lines in groups of 32" "0-31,0-63,0-95,0-127,0-159,0-191,0-223,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,?..." wgroup.long 0x10400++0x03 line.long 0x00 "EVENTSPR,Event Set Pending Register" bitfld.long 0x00 2. " EDBGREQ ,External debug request has occurred" "Not occurred,Occurred" bitfld.long 0x00 1. " NMI ,Non-maskable interrupt has occurred" "Not occurred,Occurred" bitfld.long 0x00 0. " EVENT ,RXEV event has occurred" "Not occurred,Occurred" rgroup.long 0x10480++0x03 line.long 0x00 "EVENTMASKA,Wake-Up Event Mask Register" bitfld.long 0x00 2. " EDBGREQ ,Mask for external debug request" "0,1" bitfld.long 0x00 1. " NMI ,Mask for non-maskable interrupt" "Not occurred,Occurred" bitfld.long 0x00 0. " EVENT ,RXEV event has occurred while WFE sleep" "Not occurred,Occurred" repeat 15. (increment 0x10484 0x04) (increment 0. 1.) rgroup.long $1++0x03 line.long 0x00 "EVENTMASK$2,Wake-up Event Mask Register $2" repeat.end width 24. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt set/clear enable bit" "Disabled,Enabled" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) group.long 0x104++0x03 line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x104++0x03 hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) group.long 0x108++0x03 line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x108++0x03 hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) group.long 0x10C++0x03 line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x10C++0x03 hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) group.long 0x110++0x03 line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x110++0x03 hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) group.long 0x114++0x03 line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x114++0x03 hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) group.long 0x118++0x03 line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x118++0x03 hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) group.long 0x11C++0x03 line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x11C++0x03 hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) group.long 0x120++0x03 line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x120++0x03 hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) group.long 0x124++0x03 line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x124++0x03 hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) group.long 0x128++0x03 line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x128++0x03 hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) group.long 0x12C++0x03 line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x12C++0x03 hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) group.long 0x130++0x03 line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x130++0x03 hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) group.long 0x134++0x03 line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x134++0x03 hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) group.long 0x138++0x03 line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt set/clear enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt set/clear enable bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt set/clear enable bit" "Disabled,Enabled" else hgroup.long 0x138++0x03 hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register" endif tree.end width 24. tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt set/clear pending" "Not pending,Pending" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) group.long 0x204++0x03 line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x204++0x03 hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) group.long 0x208++0x03 line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x208++0x03 hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) group.long 0x20C++0x03 line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x20C++0x03 hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) group.long 0x210++0x03 line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x210++0x03 hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) group.long 0x214++0x03 line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x214++0x03 hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) group.long 0x218++0x03 line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x218++0x03 hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) group.long 0x21C++0x03 line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x21C++0x03 hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) group.long 0x220++0x03 line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x220++0x03 hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) group.long 0x224++0x03 line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x224++0x03 hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) group.long 0x228++0x03 line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x228++0x03 hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) group.long 0x22C++0x03 line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x22C++0x03 hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) group.long 0x230++0x03 line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x230++0x03 hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) group.long 0x234++0x03 line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x234++0x03 hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) group.long 0x238++0x03 line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt set/clear pending" "Not pending,Pending" newline setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt set/clear pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt set/clear pending" "Not pending,Pending" else hgroup.long 0x238++0x03 hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register" endif tree.end width 11. tree "Interrupt Active Bit Registers" rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE0,Active Bit Register 0" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 25. " ACTIVE25 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 19. " ACTIVE19 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 13. " ACTIVE13 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 7. " ACTIVE7 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 1. " ACTIVE1 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt active flag" "Not active,Active" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) rgroup.long 0x304++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE63 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE62 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE61 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE60 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE59 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE58 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 25. " ACTIVE57 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE56 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE55 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE54 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE53 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE52 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 19. " ACTIVE51 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE50 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE49 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE48 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE47 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE46 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 13. " ACTIVE45 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE44 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE43 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE42 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE41 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE40 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 7. " ACTIVE39 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE38 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE37 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE36 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE35 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE34 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 1. " ACTIVE33 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE32 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x304++0x03 hide.long 0x00 "ACTIVE1,Active Bit Register 1" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) rgroup.long 0x308++0x03 line.long 0x00 "ACTIVE2,Active Bit Register 2" bitfld.long 0x00 31. " ACTIVE95 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE94 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE93 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE92 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE91 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE90 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 25. " ACTIVE89 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE88 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE87 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE86 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE85 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE84 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 19. " ACTIVE83 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE82 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE81 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE80 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE79 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE78 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 13. " ACTIVE77 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE76 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE75 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE74 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE73 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE72 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 7. " ACTIVE71 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE70 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE69 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE68 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE67 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE66 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 1. " ACTIVE65 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE64 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x308++0x03 hide.long 0x00 "ACTIVE2,Active Bit Register 2" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) rgroup.long 0x30C++0x03 line.long 0x00 "ACTIVE3,Active Bit Register 3" bitfld.long 0x00 31. " ACTIVE127 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE126 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE125 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE124 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE123 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE122 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 25. " ACTIVE121 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE120 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE119 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE118 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE117 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE116 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 19. " ACTIVE115 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE114 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE113 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE112 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE111 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE110 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 13. " ACTIVE109 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE108 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE107 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE106 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE105 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE104 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 7. " ACTIVE103 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE102 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE101 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE100 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE99 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE98 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 1. " ACTIVE97 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE96 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x30C++0x03 hide.long 0x00 "ACTIVE3,Active Bit Register 3" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) rgroup.long 0x310++0x03 line.long 0x00 "ACTIVE4,Active Bit Register 4" bitfld.long 0x00 31. " ACTIVE159 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE158 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE157 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE156 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE155 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE154 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 25. " ACTIVE153 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE152 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE151 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE150 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE149 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE148 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 19. " ACTIVE147 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE146 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE145 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE144 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE143 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE142 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 13. " ACTIVE141 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE140 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE139 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE138 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE137 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE136 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 7. " ACTIVE135 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE134 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE133 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE132 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE131 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE130 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 1. " ACTIVE129 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE128 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x310++0x03 hide.long 0x00 "ACTIVE4,Active Bit Register 4" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) rgroup.long 0x314++0x03 line.long 0x00 "ACTIVE5,Active Bit Register 5" bitfld.long 0x00 31. " ACTIVE191 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE190 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE189 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE188 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE187 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE186 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 25. " ACTIVE185 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE184 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE183 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE182 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE181 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE180 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 19. " ACTIVE179 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE178 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE177 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE176 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE175 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE174 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 13. " ACTIVE173 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE172 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE171 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE170 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE169 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE168 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 7. " ACTIVE167 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE166 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE165 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE164 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE163 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE162 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 1. " ACTIVE161 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE160 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x314++0x03 hide.long 0x00 "ACTIVE5,Active Bit Register 5" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) rgroup.long 0x318++0x03 line.long 0x00 "ACTIVE6,Active Bit Register 6" bitfld.long 0x00 31. " ACTIVE223 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE222 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE221 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE220 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE219 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE218 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 25. " ACTIVE217 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE216 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE215 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE214 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE213 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE212 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 19. " ACTIVE211 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE210 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE209 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE208 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE207 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE206 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 13. " ACTIVE205 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE204 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE203 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE202 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE201 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE200 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 7. " ACTIVE199 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE198 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE197 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE196 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE195 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE194 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 1. " ACTIVE193 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE192 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x318++0x03 hide.long 0x00 "ACTIVE6,Active Bit Register 6" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) rgroup.long 0x31C++0x03 line.long 0x00 "ACTIVE7,Active Bit Register 7" bitfld.long 0x00 31. " ACTIVE255 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE254 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE253 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE252 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE251 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE250 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 25. " ACTIVE249 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE248 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE247 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE246 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE245 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE244 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 19. " ACTIVE243 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE242 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE241 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE240 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE239 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE238 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 13. " ACTIVE237 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE236 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE235 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE234 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE233 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE232 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 7. " ACTIVE231 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE230 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE229 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE228 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE227 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE226 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 1. " ACTIVE225 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE224 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x31C++0x03 hide.long 0x00 "ACTIVE7,Active Bit Register 7" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) rgroup.long 0x320++0x03 line.long 0x00 "ACTIVE8,Active Bit Register 8" bitfld.long 0x00 31. " ACTIVE287 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE286 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE285 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE284 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE283 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE282 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 25. " ACTIVE281 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE280 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE279 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE278 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE277 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE276 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 19. " ACTIVE275 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE274 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE273 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE272 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE271 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE270 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 13. " ACTIVE269 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE268 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE267 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE266 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE265 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE264 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 7. " ACTIVE263 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE262 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE261 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE260 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE259 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE258 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 1. " ACTIVE257 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE256 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x320++0x03 hide.long 0x00 "ACTIVE8,Active Bit Register 8" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) rgroup.long 0x324++0x03 line.long 0x00 "ACTIVE9,Active Bit Register 9" bitfld.long 0x00 31. " ACTIVE319 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE318 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE317 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE316 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE315 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE314 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 25. " ACTIVE313 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE312 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE311 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE310 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE309 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE308 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 19. " ACTIVE307 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE306 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE305 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE304 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE303 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE302 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 13. " ACTIVE301 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE300 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE299 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE298 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE297 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE296 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 7. " ACTIVE295 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE294 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE293 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE292 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE291 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE290 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 1. " ACTIVE289 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE288 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x324++0x03 hide.long 0x00 "ACTIVE9,Active Bit Register 9" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) rgroup.long 0x328++0x03 line.long 0x00 "ACTIVE10,Active Bit Register 10" bitfld.long 0x00 31. " ACTIVE351 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE350 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE349 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE348 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE347 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE346 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 25. " ACTIVE345 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE344 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE343 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE342 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE341 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE340 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 19. " ACTIVE339 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE338 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE337 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE336 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE335 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE334 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 13. " ACTIVE333 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE332 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE331 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE330 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE329 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE328 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 7. " ACTIVE327 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE326 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE325 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE324 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE323 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE322 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 1. " ACTIVE321 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE320 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x328++0x03 hide.long 0x00 "ACTIVE10,Active Bit Register 10" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) rgroup.long 0x32C++0x03 line.long 0x00 "ACTIVE11,Active Bit Register 11" bitfld.long 0x00 31. " ACTIVE383 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE382 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE381 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE380 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE379 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE378 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 25. " ACTIVE377 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE376 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE375 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE374 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE373 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE372 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 19. " ACTIVE371 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE370 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE369 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE368 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE367 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE366 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 13. " ACTIVE365 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE364 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE363 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE362 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE361 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE360 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 7. " ACTIVE359 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE358 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE357 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE356 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE355 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE354 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 1. " ACTIVE353 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE352 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x32C++0x03 hide.long 0x00 "ACTIVE11,Active Bit Register 11" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) rgroup.long 0x330++0x03 line.long 0x00 "ACTIVE12,Active Bit Register 12" bitfld.long 0x00 31. " ACTIVE415 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE414 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE413 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE412 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE411 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE410 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 25. " ACTIVE409 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE408 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE407 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE406 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE405 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE404 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 19. " ACTIVE403 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE402 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE401 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE400 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE399 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE398 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 13. " ACTIVE397 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE396 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE395 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE394 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE393 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE392 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 7. " ACTIVE391 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE390 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE389 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE388 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE387 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE386 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 1. " ACTIVE385 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE384 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x330++0x03 hide.long 0x00 "ACTIVE12,Active Bit Register 12" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) rgroup.long 0x334++0x03 line.long 0x00 "ACTIVE13,Active Bit Register 13" bitfld.long 0x00 31. " ACTIVE447 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE446 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE445 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE444 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE443 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE442 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 25. " ACTIVE441 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE440 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE439 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE438 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE437 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE436 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 19. " ACTIVE435 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE434 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE433 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE432 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE431 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE430 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 13. " ACTIVE429 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE428 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE427 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE426 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE425 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE424 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 7. " ACTIVE423 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE422 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE421 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE420 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE419 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE418 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 1. " ACTIVE417 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE416 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x334++0x03 hide.long 0x00 "ACTIVE13,Active Bit Register 13" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) rgroup.long 0x338++0x03 line.long 0x00 "ACTIVE14,Active Bit Register 14" bitfld.long 0x00 31. " ACTIVE479 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE478 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE477 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE476 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE475 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE474 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 25. " ACTIVE473 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE472 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE471 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE470 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE469 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE468 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 19. " ACTIVE467 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE466 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE465 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE464 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE463 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE462 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 13. " ACTIVE461 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE460 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE459 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE458 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE457 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE456 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 7. " ACTIVE455 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE454 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE453 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE452 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE451 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE450 ,Interrupt active flag" "Not active,Active" newline bitfld.long 0x00 1. " ACTIVE449 ,Interrupt active flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE448 ,Interrupt active flag" "Not active,Active" else hgroup.long 0x338++0x03 hide.long 0x00 "ACTIVE14,Active Bit Register 14" endif tree.end width 13. tree "Interrupt Target Non-Secure Registers" group.long 0x380++0x03 line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0" bitfld.long 0x00 31. " ITNS31 ,Interrupt targets non-secure 31" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS30 ,Interrupt targets non-secure 30" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS29 ,Interrupt targets non-secure 29" "Secure,Non-secure" newline bitfld.long 0x00 28. " ITNS28 ,Interrupt targets non-secure 28" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS27 ,Interrupt targets non-secure 27" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS26 ,Interrupt targets non-secure 26" "Secure,Non-secure" newline bitfld.long 0x00 25. " ITNS25 ,Interrupt targets non-secure 25" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS24 ,Interrupt targets non-secure 24" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS23 ,Interrupt targets non-secure 23" "Secure,Non-secure" newline bitfld.long 0x00 22. " ITNS22 ,Interrupt targets non-secure 22" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS21 ,Interrupt targets non-secure 21" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS20 ,Interrupt targets non-secure 20" "Secure,Non-secure" newline bitfld.long 0x00 19. " ITNS19 ,Interrupt targets non-secure 19" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS18 ,Interrupt targets non-secure 18" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS17 ,Interrupt targets non-secure 17" "Secure,Non-secure" newline bitfld.long 0x00 16. " ITNS16 ,Interrupt targets non-secure 16" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS15 ,Interrupt targets non-secure 15" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS14 ,Interrupt targets non-secure 14" "Secure,Non-secure" newline bitfld.long 0x00 13. " ITNS13 ,Interrupt targets non-secure 13" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS12 ,Interrupt targets non-secure 12" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS11 ,Interrupt targets non-secure 11" "Secure,Non-secure" newline bitfld.long 0x00 10. " ITNS10 ,Interrupt targets non-secure 10" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS9 ,Interrupt targets non-secure 9" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS8 ,Interrupt targets non-secure 8" "Secure,Non-secure" newline bitfld.long 0x00 7. " ITNS7 ,Interrupt targets non-secure 7" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS6 ,Interrupt targets non-secure 6" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS5 ,Interrupt targets non-secure 5" "Secure,Non-secure" newline bitfld.long 0x00 4. " ITNS4 ,Interrupt targets non-secure 4" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS3 ,Interrupt targets non-secure 3" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS2 ,Interrupt targets non-secure 2" "Secure,Non-secure" newline bitfld.long 0x00 1. " ITNS1 ,Interrupt targets non-secure 1" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS0 ,Interrupt targets non-secure 0" "Secure,Non-secure" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) group.long 0x384++0x03 line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1" bitfld.long 0x00 31. " ITNS63 ,Interrupt targets non-secure 63" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS62 ,Interrupt targets non-secure 62" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS61 ,Interrupt targets non-secure 61" "Secure,Non-secure" newline bitfld.long 0x00 28. " ITNS60 ,Interrupt targets non-secure 60" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS59 ,Interrupt targets non-secure 59" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS58 ,Interrupt targets non-secure 58" "Secure,Non-secure" newline bitfld.long 0x00 25. " ITNS57 ,Interrupt targets non-secure 57" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS56 ,Interrupt targets non-secure 56" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS55 ,Interrupt targets non-secure 55" "Secure,Non-secure" newline bitfld.long 0x00 22. " ITNS54 ,Interrupt targets non-secure 54" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS53 ,Interrupt targets non-secure 53" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS52 ,Interrupt targets non-secure 52" "Secure,Non-secure" newline bitfld.long 0x00 19. " ITNS51 ,Interrupt targets non-secure 51" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS50 ,Interrupt targets non-secure 50" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS49 ,Interrupt targets non-secure 49" "Secure,Non-secure" newline bitfld.long 0x00 16. " ITNS48 ,Interrupt targets non-secure 48" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS47 ,Interrupt targets non-secure 47" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS46 ,Interrupt targets non-secure 46" "Secure,Non-secure" newline bitfld.long 0x00 13. " ITNS45 ,Interrupt targets non-secure 45" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS44 ,Interrupt targets non-secure 44" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS43 ,Interrupt targets non-secure 43" "Secure,Non-secure" newline bitfld.long 0x00 10. " ITNS42 ,Interrupt targets non-secure 42" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS41 ,Interrupt targets non-secure 41" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS40 ,Interrupt targets non-secure 40" "Secure,Non-secure" newline bitfld.long 0x00 7. " ITNS39 ,Interrupt targets non-secure 39" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS38 ,Interrupt targets non-secure 38" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS37 ,Interrupt targets non-secure 37" "Secure,Non-secure" newline bitfld.long 0x00 4. " ITNS36 ,Interrupt targets non-secure 36" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS35 ,Interrupt targets non-secure 35" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS34 ,Interrupt targets non-secure 34" "Secure,Non-secure" newline bitfld.long 0x00 1. " ITNS33 ,Interrupt targets non-secure 33" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS32 ,Interrupt targets non-secure 32" "Secure,Non-secure" else hgroup.long 0x384++0x03 hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) group.long 0x388++0x03 line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2" bitfld.long 0x00 31. " ITNS95 ,Interrupt targets non-secure 95" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS94 ,Interrupt targets non-secure 94" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS93 ,Interrupt targets non-secure 93" "Secure,Non-secure" newline bitfld.long 0x00 28. " ITNS92 ,Interrupt targets non-secure 92" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS91 ,Interrupt targets non-secure 91" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS90 ,Interrupt targets non-secure 90" "Secure,Non-secure" newline bitfld.long 0x00 25. " ITNS89 ,Interrupt targets non-secure 89" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS88 ,Interrupt targets non-secure 88" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS87 ,Interrupt targets non-secure 87" "Secure,Non-secure" newline bitfld.long 0x00 22. " ITNS86 ,Interrupt targets non-secure 86" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS85 ,Interrupt targets non-secure 85" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS84 ,Interrupt targets non-secure 84" "Secure,Non-secure" newline bitfld.long 0x00 19. " ITNS83 ,Interrupt targets non-secure 83" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS82 ,Interrupt targets non-secure 82" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS81 ,Interrupt targets non-secure 81" "Secure,Non-secure" newline bitfld.long 0x00 16. " ITNS80 ,Interrupt targets non-secure 80" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS79 ,Interrupt targets non-secure 79" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS78 ,Interrupt targets non-secure 78" "Secure,Non-secure" newline bitfld.long 0x00 13. " ITNS77 ,Interrupt targets non-secure 77" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS76 ,Interrupt targets non-secure 76" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS75 ,Interrupt targets non-secure 75" "Secure,Non-secure" newline bitfld.long 0x00 10. " ITNS74 ,Interrupt targets non-secure 74" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS73 ,Interrupt targets non-secure 73" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS72 ,Interrupt targets non-secure 72" "Secure,Non-secure" newline bitfld.long 0x00 7. " ITNS71 ,Interrupt targets non-secure 71" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS70 ,Interrupt targets non-secure 70" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS69 ,Interrupt targets non-secure 69" "Secure,Non-secure" newline bitfld.long 0x00 4. " ITNS68 ,Interrupt targets non-secure 68" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS67 ,Interrupt targets non-secure 67" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS66 ,Interrupt targets non-secure 66" "Secure,Non-secure" newline bitfld.long 0x00 1. " ITNS65 ,Interrupt targets non-secure 65" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS64 ,Interrupt targets non-secure 64" "Secure,Non-secure" else hgroup.long 0x388++0x03 hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) group.long 0x38C++0x03 line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3" bitfld.long 0x00 31. " ITNS127 ,Interrupt targets non-secure 127" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS126 ,Interrupt targets non-secure 126" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS125 ,Interrupt targets non-secure 125" "Secure,Non-secure" newline bitfld.long 0x00 28. " ITNS124 ,Interrupt targets non-secure 124" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS123 ,Interrupt targets non-secure 123" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS122 ,Interrupt targets non-secure 122" "Secure,Non-secure" newline bitfld.long 0x00 25. " ITNS121 ,Interrupt targets non-secure 121" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS120 ,Interrupt targets non-secure 120" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS119 ,Interrupt targets non-secure 119" "Secure,Non-secure" newline bitfld.long 0x00 22. " ITNS118 ,Interrupt targets non-secure 118" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS117 ,Interrupt targets non-secure 117" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS116 ,Interrupt targets non-secure 116" "Secure,Non-secure" newline bitfld.long 0x00 19. " ITNS115 ,Interrupt targets non-secure 115" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS114 ,Interrupt targets non-secure 114" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS113 ,Interrupt targets non-secure 113" "Secure,Non-secure" newline bitfld.long 0x00 16. " ITNS112 ,Interrupt targets non-secure 112" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS111 ,Interrupt targets non-secure 111" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS110 ,Interrupt targets non-secure 110" "Secure,Non-secure" newline bitfld.long 0x00 13. " ITNS109 ,Interrupt targets non-secure 109" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS108 ,Interrupt targets non-secure 108" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS107 ,Interrupt targets non-secure 107" "Secure,Non-secure" newline bitfld.long 0x00 10. " ITNS106 ,Interrupt targets non-secure 106" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS105 ,Interrupt targets non-secure 105" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS104 ,Interrupt targets non-secure 104" "Secure,Non-secure" newline bitfld.long 0x00 7. " ITNS103 ,Interrupt targets non-secure 103" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS102 ,Interrupt targets non-secure 102" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS101 ,Interrupt targets non-secure 101" "Secure,Non-secure" newline bitfld.long 0x00 4. " ITNS100 ,Interrupt targets non-secure 100" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS99 ,Interrupt targets non-secure 99" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS98 ,Interrupt targets non-secure 98" "Secure,Non-secure" newline bitfld.long 0x00 1. " ITNS97 ,Interrupt targets non-secure 97" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS96 ,Interrupt targets non-secure 96" "Secure,Non-secure" else hgroup.long 0x38C++0x03 hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) group.long 0x390++0x03 line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4" bitfld.long 0x00 31. " ITNS159 ,Interrupt targets non-secure 159" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS158 ,Interrupt targets non-secure 158" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS157 ,Interrupt targets non-secure 157" "Secure,Non-secure" newline bitfld.long 0x00 28. " ITNS156 ,Interrupt targets non-secure 156" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS155 ,Interrupt targets non-secure 155" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS154 ,Interrupt targets non-secure 154" "Secure,Non-secure" newline bitfld.long 0x00 25. " ITNS153 ,Interrupt targets non-secure 153" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS152 ,Interrupt targets non-secure 152" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS151 ,Interrupt targets non-secure 151" "Secure,Non-secure" newline bitfld.long 0x00 22. " ITNS150 ,Interrupt targets non-secure 150" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS149 ,Interrupt targets non-secure 149" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS148 ,Interrupt targets non-secure 148" "Secure,Non-secure" newline bitfld.long 0x00 19. " ITNS147 ,Interrupt targets non-secure 147" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS146 ,Interrupt targets non-secure 146" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS145 ,Interrupt targets non-secure 145" "Secure,Non-secure" newline bitfld.long 0x00 16. " ITNS144 ,Interrupt targets non-secure 144" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS143 ,Interrupt targets non-secure 143" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS142 ,Interrupt targets non-secure 142" "Secure,Non-secure" newline bitfld.long 0x00 13. " ITNS141 ,Interrupt targets non-secure 141" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS140 ,Interrupt targets non-secure 140" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS139 ,Interrupt targets non-secure 139" "Secure,Non-secure" newline bitfld.long 0x00 10. " ITNS138 ,Interrupt targets non-secure 138" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS137 ,Interrupt targets non-secure 137" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS136 ,Interrupt targets non-secure 136" "Secure,Non-secure" newline bitfld.long 0x00 7. " ITNS135 ,Interrupt targets non-secure 135" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS134 ,Interrupt targets non-secure 134" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS133 ,Interrupt targets non-secure 133" "Secure,Non-secure" newline bitfld.long 0x00 4. " ITNS132 ,Interrupt targets non-secure 132" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS131 ,Interrupt targets non-secure 131" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS130 ,Interrupt targets non-secure 130" "Secure,Non-secure" newline bitfld.long 0x00 1. " ITNS129 ,Interrupt targets non-secure 129" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS128 ,Interrupt targets non-secure 128" "Secure,Non-secure" else hgroup.long 0x390++0x03 hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) group.long 0x394++0x03 line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5" bitfld.long 0x00 31. " ITNS191 ,Interrupt targets non-secure 191" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS190 ,Interrupt targets non-secure 190" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS189 ,Interrupt targets non-secure 189" "Secure,Non-secure" newline bitfld.long 0x00 28. " ITNS188 ,Interrupt targets non-secure 188" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS187 ,Interrupt targets non-secure 187" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS186 ,Interrupt targets non-secure 186" "Secure,Non-secure" newline bitfld.long 0x00 25. " ITNS185 ,Interrupt targets non-secure 185" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS184 ,Interrupt targets non-secure 184" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS183 ,Interrupt targets non-secure 183" "Secure,Non-secure" newline bitfld.long 0x00 22. " ITNS182 ,Interrupt targets non-secure 182" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS181 ,Interrupt targets non-secure 181" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS180 ,Interrupt targets non-secure 180" "Secure,Non-secure" newline bitfld.long 0x00 19. " ITNS179 ,Interrupt targets non-secure 179" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS178 ,Interrupt targets non-secure 178" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS177 ,Interrupt targets non-secure 177" "Secure,Non-secure" newline bitfld.long 0x00 16. " ITNS176 ,Interrupt targets non-secure 176" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS175 ,Interrupt targets non-secure 175" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS174 ,Interrupt targets non-secure 174" "Secure,Non-secure" newline bitfld.long 0x00 13. " ITNS173 ,Interrupt targets non-secure 173" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS172 ,Interrupt targets non-secure 172" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS171 ,Interrupt targets non-secure 171" "Secure,Non-secure" newline bitfld.long 0x00 10. " ITNS170 ,Interrupt targets non-secure 170" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS169 ,Interrupt targets non-secure 169" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS168 ,Interrupt targets non-secure 168" "Secure,Non-secure" newline bitfld.long 0x00 7. " ITNS167 ,Interrupt targets non-secure 167" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS166 ,Interrupt targets non-secure 166" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS165 ,Interrupt targets non-secure 165" "Secure,Non-secure" newline bitfld.long 0x00 4. " ITNS164 ,Interrupt targets non-secure 164" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS163 ,Interrupt targets non-secure 163" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS162 ,Interrupt targets non-secure 162" "Secure,Non-secure" newline bitfld.long 0x00 1. " ITNS161 ,Interrupt targets non-secure 161" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS160 ,Interrupt targets non-secure 160" "Secure,Non-secure" else hgroup.long 0x394++0x03 hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) group.long 0x398++0x03 line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6" bitfld.long 0x00 31. " ITNS223 ,Interrupt targets non-secure 223" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS222 ,Interrupt targets non-secure 222" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS221 ,Interrupt targets non-secure 221" "Secure,Non-secure" newline bitfld.long 0x00 28. " ITNS220 ,Interrupt targets non-secure 220" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS219 ,Interrupt targets non-secure 219" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS218 ,Interrupt targets non-secure 218" "Secure,Non-secure" newline bitfld.long 0x00 25. " ITNS217 ,Interrupt targets non-secure 217" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS216 ,Interrupt targets non-secure 216" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS215 ,Interrupt targets non-secure 215" "Secure,Non-secure" newline bitfld.long 0x00 22. " ITNS214 ,Interrupt targets non-secure 214" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS213 ,Interrupt targets non-secure 213" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS212 ,Interrupt targets non-secure 212" "Secure,Non-secure" newline bitfld.long 0x00 19. " ITNS211 ,Interrupt targets non-secure 211" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS210 ,Interrupt targets non-secure 210" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS209 ,Interrupt targets non-secure 209" "Secure,Non-secure" newline bitfld.long 0x00 16. " ITNS208 ,Interrupt targets non-secure 208" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS207 ,Interrupt targets non-secure 207" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS206 ,Interrupt targets non-secure 206" "Secure,Non-secure" newline bitfld.long 0x00 13. " ITNS205 ,Interrupt targets non-secure 205" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS204 ,Interrupt targets non-secure 204" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS203 ,Interrupt targets non-secure 203" "Secure,Non-secure" newline bitfld.long 0x00 10. " ITNS202 ,Interrupt targets non-secure 202" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS201 ,Interrupt targets non-secure 201" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS200 ,Interrupt targets non-secure 200" "Secure,Non-secure" newline bitfld.long 0x00 7. " ITNS199 ,Interrupt targets non-secure 199" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS198 ,Interrupt targets non-secure 198" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS197 ,Interrupt targets non-secure 197" "Secure,Non-secure" newline bitfld.long 0x00 4. " ITNS196 ,Interrupt targets non-secure 196" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS195 ,Interrupt targets non-secure 195" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS194 ,Interrupt targets non-secure 194" "Secure,Non-secure" newline bitfld.long 0x00 1. " ITNS193 ,Interrupt targets non-secure 193" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS192 ,Interrupt targets non-secure 192" "Secure,Non-secure" else hgroup.long 0x398++0x03 hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) group.long 0x39C++0x03 line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7" bitfld.long 0x00 31. " ITNS255 ,Interrupt targets non-secure 255" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS254 ,Interrupt targets non-secure 254" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS253 ,Interrupt targets non-secure 253" "Secure,Non-secure" newline bitfld.long 0x00 28. " ITNS252 ,Interrupt targets non-secure 252" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS251 ,Interrupt targets non-secure 251" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS250 ,Interrupt targets non-secure 250" "Secure,Non-secure" newline bitfld.long 0x00 25. " ITNS249 ,Interrupt targets non-secure 249" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS248 ,Interrupt targets non-secure 248" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS247 ,Interrupt targets non-secure 247" "Secure,Non-secure" newline bitfld.long 0x00 22. " ITNS246 ,Interrupt targets non-secure 246" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS245 ,Interrupt targets non-secure 245" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS244 ,Interrupt targets non-secure 244" "Secure,Non-secure" newline bitfld.long 0x00 19. " ITNS243 ,Interrupt targets non-secure 243" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS242 ,Interrupt targets non-secure 242" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS241 ,Interrupt targets non-secure 241" "Secure,Non-secure" newline bitfld.long 0x00 16. " ITNS240 ,Interrupt targets non-secure 240" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS239 ,Interrupt targets non-secure 239" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS238 ,Interrupt targets non-secure 238" "Secure,Non-secure" newline bitfld.long 0x00 13. " ITNS237 ,Interrupt targets non-secure 237" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS236 ,Interrupt targets non-secure 236" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS235 ,Interrupt targets non-secure 235" "Secure,Non-secure" newline bitfld.long 0x00 10. " ITNS234 ,Interrupt targets non-secure 234" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS233 ,Interrupt targets non-secure 233" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS232 ,Interrupt targets non-secure 232" "Secure,Non-secure" newline bitfld.long 0x00 7. " ITNS231 ,Interrupt targets non-secure 231" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS230 ,Interrupt targets non-secure 230" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS229 ,Interrupt targets non-secure 229" "Secure,Non-secure" newline bitfld.long 0x00 4. " ITNS228 ,Interrupt targets non-secure 228" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS227 ,Interrupt targets non-secure 227" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS226 ,Interrupt targets non-secure 226" "Secure,Non-secure" newline bitfld.long 0x00 1. " ITNS225 ,Interrupt targets non-secure 225" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS224 ,Interrupt targets non-secure 224" "Secure,Non-secure" else hgroup.long 0x39C++0x03 hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) group.long 0x3A0++0x03 line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8" bitfld.long 0x00 31. " ITNS287 ,Interrupt targets non-secure 287" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS286 ,Interrupt targets non-secure 286" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS285 ,Interrupt targets non-secure 285" "Secure,Non-secure" newline bitfld.long 0x00 28. " ITNS284 ,Interrupt targets non-secure 284" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS283 ,Interrupt targets non-secure 283" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS282 ,Interrupt targets non-secure 282" "Secure,Non-secure" newline bitfld.long 0x00 25. " ITNS281 ,Interrupt targets non-secure 281" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS280 ,Interrupt targets non-secure 280" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS279 ,Interrupt targets non-secure 279" "Secure,Non-secure" newline bitfld.long 0x00 22. " ITNS278 ,Interrupt targets non-secure 278" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS277 ,Interrupt targets non-secure 277" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS276 ,Interrupt targets non-secure 276" "Secure,Non-secure" newline bitfld.long 0x00 19. " ITNS275 ,Interrupt targets non-secure 275" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS274 ,Interrupt targets non-secure 274" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS273 ,Interrupt targets non-secure 273" "Secure,Non-secure" newline bitfld.long 0x00 16. " ITNS272 ,Interrupt targets non-secure 272" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS271 ,Interrupt targets non-secure 271" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS270 ,Interrupt targets non-secure 270" "Secure,Non-secure" newline bitfld.long 0x00 13. " ITNS269 ,Interrupt targets non-secure 269" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS268 ,Interrupt targets non-secure 268" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS267 ,Interrupt targets non-secure 267" "Secure,Non-secure" newline bitfld.long 0x00 10. " ITNS266 ,Interrupt targets non-secure 266" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS265 ,Interrupt targets non-secure 265" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS264 ,Interrupt targets non-secure 264" "Secure,Non-secure" newline bitfld.long 0x00 7. " ITNS263 ,Interrupt targets non-secure 263" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS262 ,Interrupt targets non-secure 262" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS261 ,Interrupt targets non-secure 261" "Secure,Non-secure" newline bitfld.long 0x00 4. " ITNS260 ,Interrupt targets non-secure 260" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS259 ,Interrupt targets non-secure 259" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS258 ,Interrupt targets non-secure 258" "Secure,Non-secure" newline bitfld.long 0x00 1. " ITNS257 ,Interrupt targets non-secure 257" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS256 ,Interrupt targets non-secure 256" "Secure,Non-secure" else hgroup.long 0x3A0++0x03 hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) group.long 0x3A4++0x03 line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9" bitfld.long 0x00 31. " ITNS319 ,Interrupt targets non-secure 319" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS318 ,Interrupt targets non-secure 318" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS317 ,Interrupt targets non-secure 317" "Secure,Non-secure" newline bitfld.long 0x00 28. " ITNS316 ,Interrupt targets non-secure 316" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS315 ,Interrupt targets non-secure 315" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS314 ,Interrupt targets non-secure 314" "Secure,Non-secure" newline bitfld.long 0x00 25. " ITNS313 ,Interrupt targets non-secure 313" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS312 ,Interrupt targets non-secure 312" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS311 ,Interrupt targets non-secure 311" "Secure,Non-secure" newline bitfld.long 0x00 22. " ITNS310 ,Interrupt targets non-secure 310" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS309 ,Interrupt targets non-secure 309" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS308 ,Interrupt targets non-secure 308" "Secure,Non-secure" newline bitfld.long 0x00 19. " ITNS307 ,Interrupt targets non-secure 307" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS306 ,Interrupt targets non-secure 306" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS305 ,Interrupt targets non-secure 305" "Secure,Non-secure" newline bitfld.long 0x00 16. " ITNS304 ,Interrupt targets non-secure 304" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS303 ,Interrupt targets non-secure 303" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS302 ,Interrupt targets non-secure 302" "Secure,Non-secure" newline bitfld.long 0x00 13. " ITNS301 ,Interrupt targets non-secure 301" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS300 ,Interrupt targets non-secure 300" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS299 ,Interrupt targets non-secure 299" "Secure,Non-secure" newline bitfld.long 0x00 10. " ITNS298 ,Interrupt targets non-secure 298" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS297 ,Interrupt targets non-secure 297" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS296 ,Interrupt targets non-secure 296" "Secure,Non-secure" newline bitfld.long 0x00 7. " ITNS295 ,Interrupt targets non-secure 295" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS294 ,Interrupt targets non-secure 294" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS293 ,Interrupt targets non-secure 293" "Secure,Non-secure" newline bitfld.long 0x00 4. " ITNS292 ,Interrupt targets non-secure 292" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS291 ,Interrupt targets non-secure 291" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS290 ,Interrupt targets non-secure 290" "Secure,Non-secure" newline bitfld.long 0x00 1. " ITNS289 ,Interrupt targets non-secure 289" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS288 ,Interrupt targets non-secure 288" "Secure,Non-secure" else hgroup.long 0x3A4++0x03 hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) group.long 0x3A8++0x03 line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10" bitfld.long 0x00 31. " ITNS351 ,Interrupt targets non-secure 351" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS350 ,Interrupt targets non-secure 350" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS349 ,Interrupt targets non-secure 349" "Secure,Non-secure" newline bitfld.long 0x00 28. " ITNS348 ,Interrupt targets non-secure 348" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS347 ,Interrupt targets non-secure 347" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS346 ,Interrupt targets non-secure 346" "Secure,Non-secure" newline bitfld.long 0x00 25. " ITNS345 ,Interrupt targets non-secure 345" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS344 ,Interrupt targets non-secure 344" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS343 ,Interrupt targets non-secure 343" "Secure,Non-secure" newline bitfld.long 0x00 22. " ITNS342 ,Interrupt targets non-secure 342" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS341 ,Interrupt targets non-secure 341" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS340 ,Interrupt targets non-secure 340" "Secure,Non-secure" newline bitfld.long 0x00 19. " ITNS339 ,Interrupt targets non-secure 339" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS338 ,Interrupt targets non-secure 338" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS337 ,Interrupt targets non-secure 337" "Secure,Non-secure" newline bitfld.long 0x00 16. " ITNS336 ,Interrupt targets non-secure 336" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS335 ,Interrupt targets non-secure 335" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS334 ,Interrupt targets non-secure 334" "Secure,Non-secure" newline bitfld.long 0x00 13. " ITNS333 ,Interrupt targets non-secure 333" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS332 ,Interrupt targets non-secure 332" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS331 ,Interrupt targets non-secure 331" "Secure,Non-secure" newline bitfld.long 0x00 10. " ITNS330 ,Interrupt targets non-secure 330" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS329 ,Interrupt targets non-secure 329" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS328 ,Interrupt targets non-secure 328" "Secure,Non-secure" newline bitfld.long 0x00 7. " ITNS327 ,Interrupt targets non-secure 327" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS326 ,Interrupt targets non-secure 326" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS325 ,Interrupt targets non-secure 325" "Secure,Non-secure" newline bitfld.long 0x00 4. " ITNS324 ,Interrupt targets non-secure 324" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS323 ,Interrupt targets non-secure 323" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS322 ,Interrupt targets non-secure 322" "Secure,Non-secure" newline bitfld.long 0x00 1. " ITNS321 ,Interrupt targets non-secure 321" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS320 ,Interrupt targets non-secure 320" "Secure,Non-secure" else hgroup.long 0x3A8++0x03 hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) group.long 0x3AC++0x03 line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11" bitfld.long 0x00 31. " ITNS383 ,Interrupt targets non-secure 383" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS382 ,Interrupt targets non-secure 382" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS381 ,Interrupt targets non-secure 381" "Secure,Non-secure" newline bitfld.long 0x00 28. " ITNS380 ,Interrupt targets non-secure 380" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS379 ,Interrupt targets non-secure 379" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS378 ,Interrupt targets non-secure 378" "Secure,Non-secure" newline bitfld.long 0x00 25. " ITNS377 ,Interrupt targets non-secure 377" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS376 ,Interrupt targets non-secure 376" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS375 ,Interrupt targets non-secure 375" "Secure,Non-secure" newline bitfld.long 0x00 22. " ITNS374 ,Interrupt targets non-secure 374" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS373 ,Interrupt targets non-secure 373" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS372 ,Interrupt targets non-secure 372" "Secure,Non-secure" newline bitfld.long 0x00 19. " ITNS371 ,Interrupt targets non-secure 371" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS370 ,Interrupt targets non-secure 370" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS369 ,Interrupt targets non-secure 369" "Secure,Non-secure" newline bitfld.long 0x00 16. " ITNS368 ,Interrupt targets non-secure 368" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS367 ,Interrupt targets non-secure 367" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS366 ,Interrupt targets non-secure 366" "Secure,Non-secure" newline bitfld.long 0x00 13. " ITNS365 ,Interrupt targets non-secure 365" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS364 ,Interrupt targets non-secure 364" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS363 ,Interrupt targets non-secure 363" "Secure,Non-secure" newline bitfld.long 0x00 10. " ITNS362 ,Interrupt targets non-secure 362" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS361 ,Interrupt targets non-secure 361" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS360 ,Interrupt targets non-secure 360" "Secure,Non-secure" newline bitfld.long 0x00 7. " ITNS359 ,Interrupt targets non-secure 359" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS358 ,Interrupt targets non-secure 358" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS357 ,Interrupt targets non-secure 357" "Secure,Non-secure" newline bitfld.long 0x00 4. " ITNS356 ,Interrupt targets non-secure 356" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS355 ,Interrupt targets non-secure 355" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS354 ,Interrupt targets non-secure 354" "Secure,Non-secure" newline bitfld.long 0x00 1. " ITNS353 ,Interrupt targets non-secure 353" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS352 ,Interrupt targets non-secure 352" "Secure,Non-secure" else hgroup.long 0x3AC++0x03 hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) group.long 0x3B0++0x03 line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12" bitfld.long 0x00 31. " ITNS415 ,Interrupt targets non-secure 415" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS414 ,Interrupt targets non-secure 414" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS413 ,Interrupt targets non-secure 413" "Secure,Non-secure" newline bitfld.long 0x00 28. " ITNS412 ,Interrupt targets non-secure 412" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS411 ,Interrupt targets non-secure 411" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS410 ,Interrupt targets non-secure 410" "Secure,Non-secure" newline bitfld.long 0x00 25. " ITNS409 ,Interrupt targets non-secure 409" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS408 ,Interrupt targets non-secure 408" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS407 ,Interrupt targets non-secure 407" "Secure,Non-secure" newline bitfld.long 0x00 22. " ITNS406 ,Interrupt targets non-secure 406" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS405 ,Interrupt targets non-secure 405" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS404 ,Interrupt targets non-secure 404" "Secure,Non-secure" newline bitfld.long 0x00 19. " ITNS403 ,Interrupt targets non-secure 403" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS402 ,Interrupt targets non-secure 402" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS401 ,Interrupt targets non-secure 401" "Secure,Non-secure" newline bitfld.long 0x00 16. " ITNS400 ,Interrupt targets non-secure 400" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS399 ,Interrupt targets non-secure 399" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS398 ,Interrupt targets non-secure 398" "Secure,Non-secure" newline bitfld.long 0x00 13. " ITNS397 ,Interrupt targets non-secure 397" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS396 ,Interrupt targets non-secure 396" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS395 ,Interrupt targets non-secure 395" "Secure,Non-secure" newline bitfld.long 0x00 10. " ITNS394 ,Interrupt targets non-secure 394" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS393 ,Interrupt targets non-secure 393" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS392 ,Interrupt targets non-secure 392" "Secure,Non-secure" newline bitfld.long 0x00 7. " ITNS391 ,Interrupt targets non-secure 391" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS390 ,Interrupt targets non-secure 390" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS389 ,Interrupt targets non-secure 389" "Secure,Non-secure" newline bitfld.long 0x00 4. " ITNS388 ,Interrupt targets non-secure 388" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS387 ,Interrupt targets non-secure 387" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS386 ,Interrupt targets non-secure 386" "Secure,Non-secure" newline bitfld.long 0x00 1. " ITNS385 ,Interrupt targets non-secure 385" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS384 ,Interrupt targets non-secure 384" "Secure,Non-secure" else hgroup.long 0x3B0++0x03 hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) group.long 0x3B4++0x03 line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13" bitfld.long 0x00 31. " ITNS447 ,Interrupt targets non-secure 447" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS446 ,Interrupt targets non-secure 446" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS445 ,Interrupt targets non-secure 445" "Secure,Non-secure" newline bitfld.long 0x00 28. " ITNS444 ,Interrupt targets non-secure 444" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS443 ,Interrupt targets non-secure 443" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS442 ,Interrupt targets non-secure 442" "Secure,Non-secure" newline bitfld.long 0x00 25. " ITNS441 ,Interrupt targets non-secure 441" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS440 ,Interrupt targets non-secure 440" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS439 ,Interrupt targets non-secure 439" "Secure,Non-secure" newline bitfld.long 0x00 22. " ITNS438 ,Interrupt targets non-secure 438" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS437 ,Interrupt targets non-secure 437" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS436 ,Interrupt targets non-secure 436" "Secure,Non-secure" newline bitfld.long 0x00 19. " ITNS435 ,Interrupt targets non-secure 435" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS434 ,Interrupt targets non-secure 434" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS433 ,Interrupt targets non-secure 433" "Secure,Non-secure" newline bitfld.long 0x00 16. " ITNS432 ,Interrupt targets non-secure 432" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS431 ,Interrupt targets non-secure 431" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS430 ,Interrupt targets non-secure 430" "Secure,Non-secure" newline bitfld.long 0x00 13. " ITNS429 ,Interrupt targets non-secure 429" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS428 ,Interrupt targets non-secure 428" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS427 ,Interrupt targets non-secure 427" "Secure,Non-secure" newline bitfld.long 0x00 10. " ITNS426 ,Interrupt targets non-secure 426" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS425 ,Interrupt targets non-secure 425" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS424 ,Interrupt targets non-secure 424" "Secure,Non-secure" newline bitfld.long 0x00 7. " ITNS423 ,Interrupt targets non-secure 423" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS422 ,Interrupt targets non-secure 422" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS421 ,Interrupt targets non-secure 421" "Secure,Non-secure" newline bitfld.long 0x00 4. " ITNS420 ,Interrupt targets non-secure 420" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS419 ,Interrupt targets non-secure 419" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS418 ,Interrupt targets non-secure 418" "Secure,Non-secure" newline bitfld.long 0x00 1. " ITNS417 ,Interrupt targets non-secure 417" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS416 ,Interrupt targets non-secure 416" "Secure,Non-secure" else hgroup.long 0x3B4++0x03 hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) group.long 0x3B8++0x03 line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14" bitfld.long 0x00 31. " ITNS479 ,Interrupt targets non-secure 479" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS478 ,Interrupt targets non-secure 478" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS477 ,Interrupt targets non-secure 477" "Secure,Non-secure" newline bitfld.long 0x00 28. " ITNS476 ,Interrupt targets non-secure 476" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS475 ,Interrupt targets non-secure 475" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS474 ,Interrupt targets non-secure 474" "Secure,Non-secure" newline bitfld.long 0x00 25. " ITNS473 ,Interrupt targets non-secure 473" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS472 ,Interrupt targets non-secure 472" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS471 ,Interrupt targets non-secure 471" "Secure,Non-secure" newline bitfld.long 0x00 22. " ITNS470 ,Interrupt targets non-secure 470" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS469 ,Interrupt targets non-secure 469" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS468 ,Interrupt targets non-secure 468" "Secure,Non-secure" newline bitfld.long 0x00 19. " ITNS467 ,Interrupt targets non-secure 467" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS466 ,Interrupt targets non-secure 466" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS465 ,Interrupt targets non-secure 465" "Secure,Non-secure" newline bitfld.long 0x00 16. " ITNS464 ,Interrupt targets non-secure 464" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS463 ,Interrupt targets non-secure 463" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS462 ,Interrupt targets non-secure 462" "Secure,Non-secure" newline bitfld.long 0x00 13. " ITNS461 ,Interrupt targets non-secure 461" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS460 ,Interrupt targets non-secure 460" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS459 ,Interrupt targets non-secure 459" "Secure,Non-secure" newline bitfld.long 0x00 10. " ITNS458 ,Interrupt targets non-secure 458" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS457 ,Interrupt targets non-secure 457" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS456 ,Interrupt targets non-secure 456" "Secure,Non-secure" newline bitfld.long 0x00 7. " ITNS455 ,Interrupt targets non-secure 455" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS454 ,Interrupt targets non-secure 454" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS453 ,Interrupt targets non-secure 453" "Secure,Non-secure" newline bitfld.long 0x00 4. " ITNS452 ,Interrupt targets non-secure 452" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS451 ,Interrupt targets non-secure 451" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS450 ,Interrupt targets non-secure 450" "Secure,Non-secure" newline bitfld.long 0x00 1. " ITNS449 ,Interrupt targets non-secure 449" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS448 ,Interrupt targets non-secure 448" "Secure,Non-secure" else hgroup.long 0x3B8++0x03 hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14" endif tree.end tree "Interrupt Priority Registers" group.long 0x400++0x03 line.long 0x00 "IPR0 ,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_3 ,Interrupt 3 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_2 ,Interrupt 2 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_1 ,Interrupt 1 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_0 ,Interrupt 0 priority" group.long 0x404++0x03 line.long 0x00 "IPR1 ,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_7 ,Interrupt 7 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_6 ,Interrupt 6 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_5 ,Interrupt 5 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_4 ,Interrupt 4 priority" group.long 0x408++0x03 line.long 0x00 "IPR2 ,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_11 ,Interrupt 11 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_10 ,Interrupt 10 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_9 ,Interrupt 9 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_8 ,Interrupt 8 priority" group.long 0x40C++0x03 line.long 0x00 "IPR3 ,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_15 ,Interrupt 15 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_14 ,Interrupt 14 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_13 ,Interrupt 13 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_12 ,Interrupt 12 priority" group.long 0x410++0x03 line.long 0x00 "IPR4 ,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_19 ,Interrupt 19 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_18 ,Interrupt 18 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_17 ,Interrupt 17 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_16 ,Interrupt 16 priority" group.long 0x414++0x03 line.long 0x00 "IPR5 ,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_23 ,Interrupt 23 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_22 ,Interrupt 22 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_21 ,Interrupt 21 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_20 ,Interrupt 20 priority" group.long 0x418++0x03 line.long 0x00 "IPR6 ,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_27 ,Interrupt 27 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_26 ,Interrupt 26 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_25 ,Interrupt 25 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_24 ,Interrupt 24 priority" group.long 0x41C++0x03 line.long 0x00 "IPR7 ,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_31 ,Interrupt 31 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_30 ,Interrupt 30 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_29 ,Interrupt 29 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_28 ,Interrupt 28 priority" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) group.long 0x420++0x03 line.long 0x00 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_35 ,Interrupt 35 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_34 ,Interrupt 34 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_33 ,Interrupt 33 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_32 ,Interrupt 32 priority" group.long 0x424++0x03 line.long 0x00 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_39 ,Interrupt 39 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_38 ,Interrupt 38 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_37 ,Interrupt 37 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_36 ,Interrupt 36 priority" group.long 0x428++0x03 line.long 0x00 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_43 ,Interrupt 43 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_42 ,Interrupt 42 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_41 ,Interrupt 41 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_40 ,Interrupt 40 priority" group.long 0x42C++0x03 line.long 0x00 "IPR11,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_47 ,Interrupt 47 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_46 ,Interrupt 46 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_45 ,Interrupt 45 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_44 ,Interrupt 44 priority" group.long 0x430++0x03 line.long 0x00 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_51 ,Interrupt 51 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_50 ,Interrupt 50 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_49 ,Interrupt 49 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_48 ,Interrupt 48 priority" group.long 0x434++0x03 line.long 0x00 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_55 ,Interrupt 55 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_54 ,Interrupt 54 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_53 ,Interrupt 53 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_52 ,Interrupt 52 priority" group.long 0x438++0x03 line.long 0x00 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_59 ,Interrupt 59 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_58 ,Interrupt 58 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_57 ,Interrupt 57 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_56 ,Interrupt 56 priority" group.long 0x43C++0x03 line.long 0x00 "IPR15,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_63 ,Interrupt 63 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_62 ,Interrupt 62 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_61 ,Interrupt 61 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_60 ,Interrupt 60 priority" else repeat 8. (increment 0x420 0x04)(increment 8. 1.) hgroup.long $1++0x03 hide.long 0x00 "IPR$2,Interrupt Priority Register" repeat.end endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) group.long 0x440++0x03 line.long 0x00 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_67 ,Interrupt 67 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_66 ,Interrupt 66 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_65 ,Interrupt 65 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_64 ,Interrupt 64 priority" group.long 0x444++0x03 line.long 0x00 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_71 ,Interrupt 71 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_70 ,Interrupt 70 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_69 ,Interrupt 69 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_68 ,Interrupt 68 priority" group.long 0x448++0x03 line.long 0x00 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_75 ,Interrupt 75 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_74 ,Interrupt 74 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_73 ,Interrupt 73 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_72 ,Interrupt 72 priority" group.long 0x44C++0x03 line.long 0x00 "IPR19,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_79 ,Interrupt 79 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_78 ,Interrupt 78 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_77 ,Interrupt 77 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_76 ,Interrupt 76 priority" group.long 0x450++0x03 line.long 0x00 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_83 ,Interrupt 83 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_82 ,Interrupt 82 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_81 ,Interrupt 81 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_80 ,Interrupt 80 priority" group.long 0x454++0x03 line.long 0x00 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_87 ,Interrupt 87 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_86 ,Interrupt 86 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_85 ,Interrupt 85 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_84 ,Interrupt 84 priority" group.long 0x458++0x03 line.long 0x00 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_91 ,Interrupt 91 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_90 ,Interrupt 90 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_89 ,Interrupt 89 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_88 ,Interrupt 88 priority" group.long 0x45C++0x03 line.long 0x00 "IPR23,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_95 ,Interrupt 95 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_94 ,Interrupt 94 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_93 ,Interrupt 93 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_92 ,Interrupt 92 priority" else repeat 8. (increment 0x440 0x04)(increment 16. 1.) hgroup.long $1++0x03 hide.long 0x00 "IPR$2,Interrupt Priority Register" repeat.end endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) group.long 0x460++0x03 line.long 0x00 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_99 ,Interrupt 99 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_98 ,Interrupt 98 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_97 ,Interrupt 97 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_96 ,Interrupt 96 priority" group.long 0x464++0x03 line.long 0x00 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_103 ,Interrupt 103 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_102 ,Interrupt 102 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_101 ,Interrupt 101 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_100 ,Interrupt 100 priority" group.long 0x468++0x03 line.long 0x00 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_107 ,Interrupt 107 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_106 ,Interrupt 106 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_105 ,Interrupt 105 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_104 ,Interrupt 104 priority" group.long 0x46C++0x03 line.long 0x00 "IPR27,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_111 ,Interrupt 111 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_110 ,Interrupt 110 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_109 ,Interrupt 109 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_108 ,Interrupt 108 priority" group.long 0x470++0x03 line.long 0x00 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_115 ,Interrupt 115 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_114 ,Interrupt 114 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_113 ,Interrupt 113 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_112 ,Interrupt 112 priority" group.long 0x474++0x03 line.long 0x00 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_119 ,Interrupt 119 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_118 ,Interrupt 118 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_117 ,Interrupt 117 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_116 ,Interrupt 116 priority" group.long 0x478++0x03 line.long 0x00 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_123 ,Interrupt 123 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_122 ,Interrupt 122 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_121 ,Interrupt 121 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_120 ,Interrupt 120 priority" group.long 0x47C++0x03 line.long 0x00 "IPR31,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_127 ,Interrupt 127 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_126 ,Interrupt 126 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_125 ,Interrupt 125 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_124 ,Interrupt 124 priority" else repeat 8. (increment 0x460 0x04)(increment 24. 1.) hgroup.long $1++0x03 hide.long 0x00 "IPR$2,Interrupt Priority Register" repeat.end endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) group.long 0x480++0x03 line.long 0x00 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_131 ,Interrupt 131 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_130 ,Interrupt 130 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_129 ,Interrupt 129 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_128 ,Interrupt 128 priority" group.long 0x484++0x03 line.long 0x00 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_135 ,Interrupt 135 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_134 ,Interrupt 134 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_133 ,Interrupt 133 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_132 ,Interrupt 132 priority" group.long 0x488++0x03 line.long 0x00 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_139 ,Interrupt 139 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_138 ,Interrupt 138 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_137 ,Interrupt 137 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_136 ,Interrupt 136 priority" group.long 0x48C++0x03 line.long 0x00 "IPR35,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_143 ,Interrupt 143 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_142 ,Interrupt 142 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_141 ,Interrupt 141 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_140 ,Interrupt 140 priority" group.long 0x490++0x03 line.long 0x00 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_147 ,Interrupt 147 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_146 ,Interrupt 146 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_145 ,Interrupt 145 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_144 ,Interrupt 144 priority" group.long 0x494++0x03 line.long 0x00 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_151 ,Interrupt 151 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_150 ,Interrupt 150 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_149 ,Interrupt 149 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_148 ,Interrupt 148 priority" group.long 0x498++0x03 line.long 0x00 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_155 ,Interrupt 155 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_154 ,Interrupt 154 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_153 ,Interrupt 153 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_152 ,Interrupt 152 priority" group.long 0x49C++0x03 line.long 0x00 "IPR39,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_159 ,Interrupt 159 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_158 ,Interrupt 158 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_157 ,Interrupt 157 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_156 ,Interrupt 156 priority" else repeat 8. (increment 0x480 0x04)(increment 32. 1.) hgroup.long $1++0x03 hide.long 0x00 "IPR$2,Interrupt Priority Register" repeat.end endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "IPR40,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_163 ,Interrupt 163 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_162 ,Interrupt 162 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_161 ,Interrupt 161 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_160 ,Interrupt 160 priority" group.long 0x4A4++0x03 line.long 0x00 "IPR41,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_167 ,Interrupt 167 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_166 ,Interrupt 166 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_165 ,Interrupt 165 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_164 ,Interrupt 164 priority" group.long 0x4A8++0x03 line.long 0x00 "IPR42,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_171 ,Interrupt 171 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_170 ,Interrupt 170 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_169 ,Interrupt 169 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_168 ,Interrupt 168 priority" group.long 0x4AC++0x03 line.long 0x00 "IPR43,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_175 ,Interrupt 175 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_174 ,Interrupt 174 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_173 ,Interrupt 173 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_172 ,Interrupt 172 priority" group.long 0x4B0++0x03 line.long 0x00 "IPR44,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_179 ,Interrupt 179 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_178 ,Interrupt 178 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_177 ,Interrupt 177 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_176 ,Interrupt 176 priority" group.long 0x4B4++0x03 line.long 0x00 "IPR45,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_183 ,Interrupt 183 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_182 ,Interrupt 182 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_181 ,Interrupt 181 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_180 ,Interrupt 180 priority" group.long 0x4B8++0x03 line.long 0x00 "IPR46,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_187 ,Interrupt 187 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_186 ,Interrupt 186 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_185 ,Interrupt 185 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_184 ,Interrupt 184 priority" group.long 0x4BC++0x03 line.long 0x00 "IPR47,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_191 ,Interrupt 191 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_190 ,Interrupt 190 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_189 ,Interrupt 189 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_188 ,Interrupt 188 priority" else repeat 8. (increment 0x4A0 0x04)(increment 40. 1.) hgroup.long $1++0x03 hide.long 0x00 "IPR$2,Interrupt Priority Register" repeat.end endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "IPR48,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_195 ,Interrupt 195 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_194 ,Interrupt 194 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_193 ,Interrupt 193 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_192 ,Interrupt 192 priority" group.long 0x4C4++0x03 line.long 0x00 "IPR49,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_199 ,Interrupt 199 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_198 ,Interrupt 198 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_197 ,Interrupt 197 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_196 ,Interrupt 196 priority" group.long 0x4C8++0x03 line.long 0x00 "IPR50,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_203 ,Interrupt 203 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_202 ,Interrupt 202 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_201 ,Interrupt 201 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_200 ,Interrupt 200 priority" group.long 0x4CC++0x03 line.long 0x00 "IPR51,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_207 ,Interrupt 207 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_206 ,Interrupt 206 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_205 ,Interrupt 205 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_204 ,Interrupt 204 priority" group.long 0x4D0++0x03 line.long 0x00 "IPR52,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_211 ,Interrupt 211 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_210 ,Interrupt 210 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_209 ,Interrupt 209 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_208 ,Interrupt 208 priority" group.long 0x4D4++0x03 line.long 0x00 "IPR53,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_215 ,Interrupt 215 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_214 ,Interrupt 214 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_213 ,Interrupt 213 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_212 ,Interrupt 212 priority" group.long 0x4D8++0x03 line.long 0x00 "IPR54,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_219 ,Interrupt 219 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_218 ,Interrupt 218 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_217 ,Interrupt 217 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_216 ,Interrupt 216 priority" group.long 0x4DC++0x03 line.long 0x00 "IPR55,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_223 ,Interrupt 223 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_222 ,Interrupt 222 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_221 ,Interrupt 221 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_220 ,Interrupt 220 priority" else repeat 8. (increment 0x4C0 0x04)(increment 48. 1.) hgroup.long $1++0x03 hide.long 0x00 "IPR$2,Interrupt Priority Register" repeat.end endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "IPR56,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_227 ,Interrupt 227 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_226 ,Interrupt 226 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_225 ,Interrupt 225 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_224 ,Interrupt 224 priority" group.long 0x4E4++0x03 line.long 0x00 "IPR57,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_231 ,Interrupt 231 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_230 ,Interrupt 230 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_229 ,Interrupt 229 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_228 ,Interrupt 228 priority" group.long 0x4E8++0x03 line.long 0x00 "IPR58,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_235 ,Interrupt 235 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_234 ,Interrupt 234 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_233 ,Interrupt 233 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_232 ,Interrupt 232 priority" group.long 0x4EC++0x03 line.long 0x00 "IPR59,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_239 ,Interrupt 239 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_238 ,Interrupt 238 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_237 ,Interrupt 237 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_236 ,Interrupt 236 priority" group.long 0x4F0++0x03 line.long 0x00 "IPR60,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_243 ,Interrupt 243 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_242 ,Interrupt 242 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_241 ,Interrupt 241 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_240 ,Interrupt 240 priority" group.long 0x4F4++0x03 line.long 0x00 "IPR61,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_247 ,Interrupt 247 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_246 ,Interrupt 246 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_245 ,Interrupt 245 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_244 ,Interrupt 244 priority" group.long 0x4F8++0x03 line.long 0x00 "IPR62,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_251 ,Interrupt 251 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_250 ,Interrupt 250 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_249 ,Interrupt 249 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_248 ,Interrupt 248 priority" group.long 0x4FC++0x03 line.long 0x00 "IPR63,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_255 ,Interrupt 255 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_254 ,Interrupt 254 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_253 ,Interrupt 253 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_252 ,Interrupt 252 priority" else repeat 8. (increment 0x4E0 0x04)(increment 56. 1.) hgroup.long $1++0x03 hide.long 0x00 "IPR$2,Interrupt Priority Register" repeat.end endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) group.long 0x500++0x03 line.long 0x00 "IPR64,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_259 ,Interrupt 259 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_258 ,Interrupt 258 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_257 ,Interrupt 257 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_256 ,Interrupt 256 priority" group.long 0x504++0x03 line.long 0x00 "IPR65,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_263 ,Interrupt 263 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_262 ,Interrupt 262 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_261 ,Interrupt 261 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_260 ,Interrupt 260 priority" group.long 0x508++0x03 line.long 0x00 "IPR66,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_267 ,Interrupt 267 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_266 ,Interrupt 266 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_265 ,Interrupt 265 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_264 ,Interrupt 264 priority" group.long 0x50C++0x03 line.long 0x00 "IPR67,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_271 ,Interrupt 271 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_270 ,Interrupt 270 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_269 ,Interrupt 269 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_268 ,Interrupt 268 priority" group.long 0x510++0x03 line.long 0x00 "IPR68,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_275 ,Interrupt 275 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_274 ,Interrupt 274 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_273 ,Interrupt 273 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_272 ,Interrupt 272 priority" group.long 0x514++0x03 line.long 0x00 "IPR69,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_279 ,Interrupt 279 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_278 ,Interrupt 278 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_277 ,Interrupt 277 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_276 ,Interrupt 276 priority" group.long 0x518++0x03 line.long 0x00 "IPR70,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_283 ,Interrupt 283 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_282 ,Interrupt 282 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_281 ,Interrupt 281 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_280 ,Interrupt 280 priority" group.long 0x51C++0x03 line.long 0x00 "IPR71,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_287 ,Interrupt 287 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_286 ,Interrupt 286 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_285 ,Interrupt 285 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_284 ,Interrupt 284 priority" else repeat 8. (increment 0x500 0x04)(increment 64. 1.) hgroup.long $1++0x03 hide.long 0x00 "IPR$2,Interrupt Priority Register" repeat.end endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) group.long 0x520++0x03 line.long 0x00 "IPR72,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_291 ,Interrupt 291 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_290 ,Interrupt 290 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_289 ,Interrupt 289 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_288 ,Interrupt 288 priority" group.long 0x524++0x03 line.long 0x00 "IPR73,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_295 ,Interrupt 295 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_294 ,Interrupt 294 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_293 ,Interrupt 293 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_292 ,Interrupt 292 priority" group.long 0x528++0x03 line.long 0x00 "IPR74,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_299 ,Interrupt 299 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_298 ,Interrupt 298 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_297 ,Interrupt 297 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_296 ,Interrupt 296 priority" group.long 0x52C++0x03 line.long 0x00 "IPR75,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_303 ,Interrupt 303 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_302 ,Interrupt 302 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_301 ,Interrupt 301 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_300 ,Interrupt 300 priority" group.long 0x530++0x03 line.long 0x00 "IPR76,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_307 ,Interrupt 307 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_306 ,Interrupt 306 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_305 ,Interrupt 305 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_304 ,Interrupt 304 priority" group.long 0x534++0x03 line.long 0x00 "IPR77,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_311 ,Interrupt 311 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_310 ,Interrupt 310 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_309 ,Interrupt 309 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_308 ,Interrupt 308 priority" group.long 0x538++0x03 line.long 0x00 "IPR78,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_315 ,Interrupt 315 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_314 ,Interrupt 314 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_313 ,Interrupt 313 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_312 ,Interrupt 312 priority" group.long 0x53C++0x03 line.long 0x00 "IPR79,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_319 ,Interrupt 319 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_318 ,Interrupt 318 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_317 ,Interrupt 317 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_316 ,Interrupt 316 priority" else repeat 8. (increment 0x520 0x04)(increment 72. 1.) hgroup.long $1++0x03 hide.long 0x00 "IPR$2,Interrupt Priority Register" repeat.end endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "IPR80,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_323 ,Interrupt 323 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_322 ,Interrupt 322 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_321 ,Interrupt 321 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_320 ,Interrupt 320 priority" group.long 0x544++0x03 line.long 0x00 "IPR81,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_327 ,Interrupt 327 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_326 ,Interrupt 326 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_325 ,Interrupt 325 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_324 ,Interrupt 324 priority" group.long 0x548++0x03 line.long 0x00 "IPR82,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_331 ,Interrupt 331 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_330 ,Interrupt 330 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_329 ,Interrupt 329 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_328 ,Interrupt 328 priority" group.long 0x54C++0x03 line.long 0x00 "IPR83,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_335 ,Interrupt 335 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_334 ,Interrupt 334 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_333 ,Interrupt 333 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_332 ,Interrupt 332 priority" group.long 0x550++0x03 line.long 0x00 "IPR84,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_339 ,Interrupt 339 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_338 ,Interrupt 338 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_337 ,Interrupt 337 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_336 ,Interrupt 336 priority" group.long 0x554++0x03 line.long 0x00 "IPR85,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_343 ,Interrupt 343 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_342 ,Interrupt 342 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_341 ,Interrupt 341 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_340 ,Interrupt 340 priority" group.long 0x558++0x03 line.long 0x00 "IPR86,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_347 ,Interrupt 347 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_346 ,Interrupt 346 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_345 ,Interrupt 345 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_344 ,Interrupt 344 priority" group.long 0x55C++0x03 line.long 0x00 "IPR87,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_351 ,Interrupt 351 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_350 ,Interrupt 350 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_349 ,Interrupt 349 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_348 ,Interrupt 348 priority" else repeat 8. (increment 0x540 0x04)(increment 80. 1.) hgroup.long $1++0x03 hide.long 0x00 "IPR$2,Interrupt Priority Register" repeat.end endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "IPR88,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_355 ,Interrupt 355 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_354 ,Interrupt 354 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_353 ,Interrupt 353 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_352 ,Interrupt 352 priority" group.long 0x564++0x03 line.long 0x00 "IPR89,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_359 ,Interrupt 359 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_358 ,Interrupt 358 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_357 ,Interrupt 357 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_356 ,Interrupt 356 priority" group.long 0x568++0x03 line.long 0x00 "IPR90,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_363 ,Interrupt 363 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_362 ,Interrupt 362 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_361 ,Interrupt 361 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_360 ,Interrupt 360 priority" group.long 0x56C++0x03 line.long 0x00 "IPR91,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_367 ,Interrupt 367 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_366 ,Interrupt 366 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_365 ,Interrupt 365 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_364 ,Interrupt 364 priority" group.long 0x570++0x03 line.long 0x00 "IPR92,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_371 ,Interrupt 371 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_370 ,Interrupt 370 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_369 ,Interrupt 369 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_368 ,Interrupt 368 priority" group.long 0x574++0x03 line.long 0x00 "IPR93,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_375 ,Interrupt 375 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_374 ,Interrupt 374 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_373 ,Interrupt 373 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_372 ,Interrupt 372 priority" group.long 0x578++0x03 line.long 0x00 "IPR94,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_379 ,Interrupt 379 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_378 ,Interrupt 378 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_377 ,Interrupt 377 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_376 ,Interrupt 376 priority" group.long 0x57C++0x03 line.long 0x00 "IPR95,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_383 ,Interrupt 383 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_382 ,Interrupt 382 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_381 ,Interrupt 381 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_380 ,Interrupt 380 priority" else repeat 8. (increment 0x560 0x04)(increment 88. 1.) hgroup.long $1++0x03 hide.long 0x00 "IPR$2,Interrupt Priority Register" repeat.end endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "IPR96,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_387 ,Interrupt 387 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_386 ,Interrupt 386 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_385 ,Interrupt 385 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_384 ,Interrupt 384 priority" group.long 0x584++0x03 line.long 0x00 "IPR97,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_391 ,Interrupt 391 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_390 ,Interrupt 390 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_389 ,Interrupt 389 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_388 ,Interrupt 388 priority" group.long 0x588++0x03 line.long 0x00 "IPR98,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_395 ,Interrupt 395 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_394 ,Interrupt 394 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_393 ,Interrupt 393 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_392 ,Interrupt 392 priority" group.long 0x58C++0x03 line.long 0x00 "IPR99,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_399 ,Interrupt 399 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_398 ,Interrupt 398 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_397 ,Interrupt 397 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_396 ,Interrupt 396 priority" group.long 0x590++0x03 line.long 0x00 "IPR100,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_403 ,Interrupt 403 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_402 ,Interrupt 402 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_401 ,Interrupt 401 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_400 ,Interrupt 400 priority" group.long 0x594++0x03 line.long 0x00 "IPR101,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_407 ,Interrupt 407 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_406 ,Interrupt 406 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_405 ,Interrupt 405 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_404 ,Interrupt 404 priority" group.long 0x598++0x03 line.long 0x00 "IPR102,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_411 ,Interrupt 411 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_410 ,Interrupt 410 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_409 ,Interrupt 409 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_408 ,Interrupt 408 priority" group.long 0x59C++0x03 line.long 0x00 "IPR103,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_415 ,Interrupt 415 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_414 ,Interrupt 414 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_413 ,Interrupt 413 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_412 ,Interrupt 412 priority" else repeat 8. (increment 0x580 0x04)(increment 96. 1.) hgroup.long $1++0x03 hide.long 0x00 "IPR$2,Interrupt Priority Register" repeat.end endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "IPR104,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_419 ,Interrupt 419 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_418 ,Interrupt 418 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_417 ,Interrupt 417 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_416 ,Interrupt 416 priority" group.long 0x5A4++0x03 line.long 0x00 "IPR105,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_423 ,Interrupt 423 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_422 ,Interrupt 422 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_421 ,Interrupt 421 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_420 ,Interrupt 420 priority" group.long 0x5A8++0x03 line.long 0x00 "IPR106,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_427 ,Interrupt 427 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_426 ,Interrupt 426 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_425 ,Interrupt 425 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_424 ,Interrupt 424 priority" group.long 0x5AC++0x03 line.long 0x00 "IPR107,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_431 ,Interrupt 431 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_430 ,Interrupt 430 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_429 ,Interrupt 429 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_428 ,Interrupt 428 priority" group.long 0x5B0++0x03 line.long 0x00 "IPR108,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_435 ,Interrupt 435 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_434 ,Interrupt 434 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_433 ,Interrupt 433 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_432 ,Interrupt 432 priority" group.long 0x5B4++0x03 line.long 0x00 "IPR109,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_439 ,Interrupt 439 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_438 ,Interrupt 438 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_437 ,Interrupt 437 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_436 ,Interrupt 436 priority" group.long 0x5B8++0x03 line.long 0x00 "IPR110,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_443 ,Interrupt 443 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_442 ,Interrupt 442 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_441 ,Interrupt 441 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_440 ,Interrupt 440 priority" group.long 0x5BC++0x03 line.long 0x00 "IPR111,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_447 ,Interrupt 447 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_446 ,Interrupt 446 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_445 ,Interrupt 445 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_444 ,Interrupt 444 priority" else repeat 8. (increment 0x5A0 0x04)(increment 104. 1.) hgroup.long $1++0x03 hide.long 0x00 "IPR$2,Interrupt Priority Register" repeat.end endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "IPR112,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_451 ,Interrupt 451 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_450 ,Interrupt 450 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_449 ,Interrupt 449 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_448 ,Interrupt 448 priority" group.long 0x5C4++0x03 line.long 0x00 "IPR113,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_455 ,Interrupt 455 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_454 ,Interrupt 454 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_453 ,Interrupt 453 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_452 ,Interrupt 452 priority" group.long 0x5C8++0x03 line.long 0x00 "IPR114,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_459 ,Interrupt 459 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_458 ,Interrupt 458 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_457 ,Interrupt 457 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_456 ,Interrupt 456 priority" group.long 0x5CC++0x03 line.long 0x00 "IPR115,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_463 ,Interrupt 463 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_462 ,Interrupt 462 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_461 ,Interrupt 461 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_460 ,Interrupt 460 priority" group.long 0x5D0++0x03 line.long 0x00 "IPR116,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_467 ,Interrupt 467 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_466 ,Interrupt 466 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_465 ,Interrupt 465 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_464 ,Interrupt 464 priority" group.long 0x5D4++0x03 line.long 0x00 "IPR117,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_471 ,Interrupt 471 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_470 ,Interrupt 470 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_469 ,Interrupt 469 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_468 ,Interrupt 468 priority" group.long 0x5D8++0x03 line.long 0x00 "IPR118,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_475 ,Interrupt 475 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_474 ,Interrupt 474 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_473 ,Interrupt 473 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_472 ,Interrupt 472 priority" group.long 0x5DC++0x03 line.long 0x00 "IPR119,Interrupt Priority Register" hexmask.long.byte 0x00 24.--31. 1. " PRI_479 ,Interrupt 479 priority" hexmask.long.byte 0x00 16.--23. 1. " PRI_478 ,Interrupt 478 priority" hexmask.long.byte 0x00 8.--15. 1. " PRI_477 ,Interrupt 477 priority" hexmask.long.byte 0x00 0.--7. 1. " PRI_476 ,Interrupt 476 priority" else repeat 8. (increment 0x5C0 0x04)(increment 112. 1.) hgroup.long $1++0x03 hide.long 0x00 "IPR$2,Interrupt Priority Register" repeat.end endif tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Floating-Point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writeable from the non-secure state" "Writeable,Write ignored" newline bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled" bitfld.long 0x00 27. " CLRONRETS ,Clear on return secure only" "Both states,Secure only" bitfld.long 0x00 26. " TS ,Treat as secure" "Disabled,Enabled" newline bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the usage fault exception to pending" "Not able,Able" bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" newline bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able" bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" newline bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure" newline bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x08 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" newline bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" bitfld.long 0x08 19. " FZ16 ,Flush-to-zero mode control bit on half-precision data-processing instructions" "Disabled,Enabled" bitfld.long 0x08 16.--18. " LTPSIZE ,Vector element size used when applying low-overhead-loop tail predication to vector instructions" "8-bit,16-bit,32-bit,64-bit,Not applied,?..." rgroup.long 0xF40++0x0B line.long 0x00 "MVFR0,Media And FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" "Not supported,All supported,?..." bitfld.long 0x00 20.--23. " FPSQRT ,Indicates the hardware support for FP square root operations" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" "Not supported,Supported,?..." newline bitfld.long 0x00 8.--11. " FPDP ,Indicates the hardware support for FP double precision operations" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " FPSP ,Indicates the hardware support for FP single-precision operations" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" "Reserved,Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media And FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" "Not supported,Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" "Not supported,Half-single,Half-single/double,?..." bitfld.long 0x04 20.--23. " FP16 ,Floating-point half-precision data processing" "Not supported,Supported,?..." newline bitfld.long 0x04 8.--11. " MVE ,Indicates support for M-profile vector extension" "Not supported,Supported no FP,Supported with FP,?..." bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the default NaN mode" "Not supported,NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the flush-to-zero mode of operation" "Not supported,Fully denormalized,?..." line.long 0x08 "MVFR2,Media And FP Feature Register 2" bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,Reserved,Reserved,Reserved,Supported,?..." width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 13. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 5. " PMU ,Indicates whether a PMU counter overflow event has occurred" "Not occurred,Occurred" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a vector catch" "Not triggered,Triggered" newline eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates that a halt request debug event or step debug event has occurred" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write" hexmask.long.byte 0x00 0.--7. 1. " REGSEL ,Specifies the ARM core register special-purpose register or floating-point extension register" group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x04 23. " MONPRKEY ,Writes to the MON_PEND and MON_REQ fields are ignored" "Not ignored,Ignored" bitfld.long 0x04 21. " UMON_EN ,Unprivileged monitor enable" "Disabled,Enabled" newline rbitfld.long 0x04 20. " SDME ,Indicates whether the DebugMonitor targets the secure or the non-secure state" "Non-secure,Secure" bitfld.long 0x04 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x04 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x04 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x04 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x04 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled" newline bitfld.long 0x04 10. " VC_HARDERR ,Enable halting debug trap on a hard fault exception" "Disabled,Enabled" bitfld.long 0x04 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled" bitfld.long 0x04 8. " VC_BUSERR ,Enable halting debug trap on a bus fault exception" "Disabled,Enabled" newline bitfld.long 0x04 7. " VC_STATERR ,Enable halting debug trap on a usage fault exception caused by a state information error" "Disabled,Enabled" bitfld.long 0x04 6. " VC_CHKERR ,Enable halting debug trap on a usage fault exception caused by a checking error" "Disabled,Enabled" bitfld.long 0x04 5. " VC_NOCPERR ,Enable halting debug trap on a usage fault caused by an access to a Coprocessor" "Disabled,Enabled" newline bitfld.long 0x04 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" bitfld.long 0x04 0. " VC_CORERESET ,Enable reset vector catch" "Disabled,Enabled" group.long 0xE04++0x07 line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register" bitfld.long 0x00 10. " UIDEN ,Unprivileged invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 9. " UIDAPEN ,Unprivileged invasive DAP access enable" "Disabled,Enabled" bitfld.long 0x00 8. " FSDMA ,Force secure debug monitor allowed" "Not allowed,Allowed" newline bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN" bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN" line.long 0x04 "DSCSR,Debug Security Control and Status Register" bitfld.long 0x04 17. " CDSKEY ,CDS write-enable key" "Not ignored,Ignored" bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure" bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure" newline bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled" rgroup.long 0xFB8++0x03 line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 22.--23. " SUNID ,Secure unprivileged non-invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed" bitfld.long 0x00 20.--21. " SUID ,Secure unprivileged invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed" bitfld.long 0x00 18.--19. " NSUNID ,Non-secure unprivileged non-invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed" newline bitfld.long 0x00 16.--17. " NSUID ,Non-secure unprivileged invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed" bitfld.long 0x00 6.--7. " SNID ,Secure non-invasive debug" "Not implemented,Reserved,Implemented/Disabled,Implemented/Enabled" bitfld.long 0x00 4.--5. " SID ,Secure invasive debug" "Not implemented,Reserved,Implemented/Disabled,Implemented/Enabled" newline bitfld.long 0x00 2.--3. " NSNID ,Non-secure non-invasive debug" "Reserved,Reserved,Prohibited,Allowed" bitfld.long 0x00 0.--1. " NSID ,Non-secure invasive debug" "Reserved,Reserved,Prohibited,Allowed" group.long 0x10300++0x07 line.long 0x00 "CPDLPSTATE,Core Power Domain Low Power State Register" bitfld.long 0x00 8.--9. " RLPSTATE ,Power-on state for PDRAMS power domain" "ON,Reserved,Reserved,OFF" bitfld.long 0x00 4.--5. " ELPSTATE ,Type of low-power state for PDEPU" "ON,ON clock off,RET,OFF" bitfld.long 0x00 0.--1. " CLPSTATE ,Type of low-power state for PDCORE" "ON,ON clock off,RET,OFF" line.long 0x04 "DPDLPSTATE,Debug Power Domain Low Power State Register" bitfld.long 0x04 0.--1. " DLPSTATE ,Type of low-power state for PDDEBUG" "ON,ON clock off,Reserved,OFF" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "BreakPoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 12. group.long 0x00++0x03 line.long 0x00 "FP_CTRL,Flash Patch Control Register" rbitfld.long 0x00 28.--31. " REV ,Flash patch breakpoint architecture revision" "Reserved,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "Not implemented,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 1. " KEY ,FP_CTRL write-enable key" "Ignored,Permitted" newline bitfld.long 0x00 0. " ENABLE ,Flash patch unit enable" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "FP_REMAP,Flash Patch Remap" repeat 8. (increment 0x08 0x04) (increment 0. 1.) group.long $1++0x03 line.long 0x00 "FP_COMP$2,Flash Patch Comparator Register $2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between remapping and breakpoint functionality" "Disabled,Enabled" repeat.end rgroup.long 0xFBC++0x03 line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register" hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect" bitfld.long 0x00 20. " PRESENT ,Register present" "Reserved,Present" bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "FPB v2,?..." newline bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "Reserved,FPB v2,?..." hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part" width 10. tree "Peripheral Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "FP_PIDR0,FP Peripheral Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " PART_NUM[7:0] ,Part number bits[7:0]" line.long 0x04 "FP_PIDR1,FP Peripheral Identification Register 1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " PART_NUM[11:8] ,Part number bits[11:8]" line.long 0x08 "FP_PIDR2,FP Peripheral Identification Register 2" hexmask.long.byte 0x08 4.--7. 1. " REVISION ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "FP_PIDR3,FP Peripheral Identification Register 3" hexmask.long.byte 0x0C 4.--7. 1. " REVAND ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "FP_PIDR4,FP Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " COUNT ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "FP_CIDR0,FP Component Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "FP_CIDR1,FP Component Identification Register 1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class" line.long 0x08 "FP_CIDR2,FP Component Identification Register 2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0C "FP_CIDR3,FP Component Identification Register 3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end width 0x0B else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 16. group.long 0x00++0x03 line.long 0x00 "DWT_CTRL,DWT Control Register" bitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "Not supported,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" bitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" newline bitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in secure state" "No,Yes" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow event counter packets generation" "Disabled,Enabled" newline bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the sleep counter overflow event" "Disabled,Enabled" newline bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" newline bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" newline bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x00) group.long 0x04++0x03 line.long 0x00 "DWT_CYCCNT,DWT Cycle Count Register" else rgroup.long 0x04++0x03 line.long 0x00 "DWT_CYCCNT,DWT Cycle Count Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))))&0x1000000)==0x00) group.long 0x08++0x13 line.long 0x00 "DWT_CPICNT,DWT CPI Count Register" hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter" line.long 0x04 "DWT_EXCCNT,DWT Exception Overhead Count Register" hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x08 "DWT_SLEEPCNT,DWT Sleep Count Register" hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep counter" line.long 0x0C "DWT_LSUCNT,DWT LSU Count Register" hexmask.long.byte 0x0C 0.--7. 1. " LSUCNT ,Load-store overhead counter" line.long 0x10 "DWT_FOLDCNT,DWT Folded-instruction Count Register" hexmask.long.byte 0x10 0.--7. 1. " FOLDCNT ,Folded-instruction counter" else rgroup.long 0x08++0x13 line.long 0x00 "DWT_CPICNT,DWT CPI Count Register" line.long 0x04 "DWT_EXCCNT,DWT Exception Overhead Count Register" line.long 0x08 "DWT_SLEEPCNT,DWT Sleep Count Register" line.long 0x0C "DWT_LSUCNT,DWT LSU Count Register" line.long 0x10 "DWT_FOLDCNT,DWT Folded-instruction Count Register" endif rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,DWT Program Counter Sample Register" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08))&0x0E)==0x02) group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " PCVALUE ,PC value" else group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" endif group.long (0x20+0x08)++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0" rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr with value,Cycle counter/data addr/data addr with value,Instruction addr/data addr/data addr with value,Cycle counter/instruction addr/data addr/data addr with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr limit/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data addr with value,Reserved,Data addr/data addr limit/data value/linked data value/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data value/linked data value/data addr with value,?..." newline rbitfld.long 0x00 24. " MATCHED ,Comparator matched" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "1B,2B,4B,?..." bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace data address" newline bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..." if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x0E)==0x02) group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " PCVALUE ,PC value" else group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" endif group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1" rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr with value,Cycle counter/data addr/data addr with value,Instruction addr/data addr/data addr with value,Cycle counter/instruction addr/data addr/data addr with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr limit/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data addr with value,Reserved,Data addr/data addr limit/data value/linked data value/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data value/linked data value/data addr with value,?..." newline rbitfld.long 0x00 24. " MATCHED ,Comparator matched" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "1B,2B,4B,?..." bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace data address" newline bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..." if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0x0C)==0x08) group.long (0x30+0x0C)++0x03 line.long 0x00 "DWT_VMASK1,DWT Comparator Value Mask Register" bitfld.long 0x00 31. " VMASK[31] ,Data value mask 31" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Data value mask 30" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Data value mask 29" "Not masked,Masked" newline bitfld.long 0x00 28. " [28] ,Data value mask 28" "Not masked,Masked" bitfld.long 0x00 27. " [27] ,Data value mask 27" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Data value mask 26" "Not masked,Masked" newline bitfld.long 0x00 25. " [25] ,Data value mask 25" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Data value mask 24" "Not masked,Masked" bitfld.long 0x00 23. " [23] ,Data value mask 23" "Not masked,Masked" newline bitfld.long 0x00 22. " [22] ,Data value mask 22" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Data value mask 21" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Data value mask 20" "Not masked,Masked" newline bitfld.long 0x00 19. " [19] ,Data value mask 19" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Data value mask 18" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Data value mask 17" "Not masked,Masked" newline bitfld.long 0x00 16. " [16] ,Data value mask 16" "Not masked,Masked" bitfld.long 0x00 15. " [15] ,Data value mask 15" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Data value mask 14" "Not masked,Masked" newline bitfld.long 0x00 13. " [13] ,Data value mask 13" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Data value mask 12" "Not masked,Masked" bitfld.long 0x00 11. " [11] ,Data value mask 11" "Not masked,Masked" newline bitfld.long 0x00 10. " [10] ,Data value mask 10" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Data value mask 9" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Data value mask 8" "Not masked,Masked" newline bitfld.long 0x00 7. " [7] ,Data value mask 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Data value mask 6" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Data value mask 5" "Not masked,Masked" newline bitfld.long 0x00 4. " [4] ,Data value mask 4" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,Data value mask 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Data value mask 2" "Not masked,Masked" newline bitfld.long 0x00 1. " [1] ,Data value mask 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Data value mask 0" "Not masked,Masked" else rgroup.long (0x30+0x0C)++0x03 line.long 0x00 "DWT_VMASK1,DWT Comparator Value Mask Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x0E)==0x02) group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " PCVALUE ,PC value" else group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" endif group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2" rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr with value,Cycle counter/data addr/data addr with value,Instruction addr/data addr/data addr with value,Cycle counter/instruction addr/data addr/data addr with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr limit/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data addr with value,Reserved,Data addr/data addr limit/data value/linked data value/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data value/linked data value/data addr with value,?..." newline rbitfld.long 0x00 24. " MATCHED ,Comparator matched" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "1B,2B,4B,?..." bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace data address" newline bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..." if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x0E)==0x02) group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " PCVALUE ,PC value" else group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" endif group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3" rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr with value,Cycle counter/data addr/data addr with value,Instruction addr/data addr/data addr with value,Cycle counter/instruction addr/data addr/data addr with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr limit/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data addr with value,Reserved,Data addr/data addr limit/data value/linked data value/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data value/linked data value/data addr with value,?..." newline rbitfld.long 0x00 24. " MATCHED ,Comparator matched" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "1B,2B,4B,?..." bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace data address" newline bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..." if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0x0C)==0x08) group.long (0x50+0x0C)++0x03 line.long 0x00 "DWT_VMASK3,DWT Comparator Value Mask Register" bitfld.long 0x00 31. " VMASK[31] ,Data value mask 31" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Data value mask 30" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Data value mask 29" "Not masked,Masked" newline bitfld.long 0x00 28. " [28] ,Data value mask 28" "Not masked,Masked" bitfld.long 0x00 27. " [27] ,Data value mask 27" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Data value mask 26" "Not masked,Masked" newline bitfld.long 0x00 25. " [25] ,Data value mask 25" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Data value mask 24" "Not masked,Masked" bitfld.long 0x00 23. " [23] ,Data value mask 23" "Not masked,Masked" newline bitfld.long 0x00 22. " [22] ,Data value mask 22" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Data value mask 21" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Data value mask 20" "Not masked,Masked" newline bitfld.long 0x00 19. " [19] ,Data value mask 19" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Data value mask 18" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Data value mask 17" "Not masked,Masked" newline bitfld.long 0x00 16. " [16] ,Data value mask 16" "Not masked,Masked" bitfld.long 0x00 15. " [15] ,Data value mask 15" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Data value mask 14" "Not masked,Masked" newline bitfld.long 0x00 13. " [13] ,Data value mask 13" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Data value mask 12" "Not masked,Masked" bitfld.long 0x00 11. " [11] ,Data value mask 11" "Not masked,Masked" newline bitfld.long 0x00 10. " [10] ,Data value mask 10" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Data value mask 9" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Data value mask 8" "Not masked,Masked" newline bitfld.long 0x00 7. " [7] ,Data value mask 7" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Data value mask 6" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Data value mask 5" "Not masked,Masked" newline bitfld.long 0x00 4. " [4] ,Data value mask 4" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,Data value mask 3" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Data value mask 2" "Not masked,Masked" newline bitfld.long 0x00 1. " [1] ,Data value mask 1" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Data value mask 0" "Not masked,Masked" else rgroup.long (0x50+0x0C)++0x03 line.long 0x00 "DWT_VMASK3,DWT Comparator Value Mask Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08))&0x0E)==0x02) group.long 0x60++0x03 line.long 0x00 "DWT_COMP4,DWT Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " PCVALUE ,PC value" else group.long 0x60++0x03 line.long 0x00 "DWT_COMP4,DWT Comparator Register 4" endif group.long (0x60+0x08)++0x03 line.long 0x00 "DWT_FUNCTION4,DWT Function Register 4" rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr with value,Cycle counter/data addr/data addr with value,Instruction addr/data addr/data addr with value,Cycle counter/instruction addr/data addr/data addr with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr limit/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data addr with value,Reserved,Data addr/data addr limit/data value/linked data value/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data value/linked data value/data addr with value,?..." newline rbitfld.long 0x00 24. " MATCHED ,Comparator matched" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "1B,2B,4B,?..." bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace data address" newline bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..." if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08))&0x0E)==0x02) group.long 0x70++0x03 line.long 0x00 "DWT_COMP5,DWT Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " PCVALUE ,PC value" else group.long 0x70++0x03 line.long 0x00 "DWT_COMP5,DWT Comparator Register 5" endif group.long (0x70+0x08)++0x03 line.long 0x00 "DWT_FUNCTION5,DWT Function Register 5" rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr with value,Cycle counter/data addr/data addr with value,Instruction addr/data addr/data addr with value,Cycle counter/instruction addr/data addr/data addr with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr limit/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data addr with value,Reserved,Data addr/data addr limit/data value/linked data value/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data value/linked data value/data addr with value,?..." newline rbitfld.long 0x00 24. " MATCHED ,Comparator matched" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "1B,2B,4B,?..." bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace data address" newline bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..." if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08))&0x0E)==0x02) group.long 0x80++0x03 line.long 0x00 "DWT_COMP6,DWT Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " PCVALUE ,PC value" else group.long 0x80++0x03 line.long 0x00 "DWT_COMP6,DWT Comparator Register 6" endif group.long (0x80+0x08)++0x03 line.long 0x00 "DWT_FUNCTION6,DWT Function Register 6" rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr with value,Cycle counter/data addr/data addr with value,Instruction addr/data addr/data addr with value,Cycle counter/instruction addr/data addr/data addr with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr limit/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data addr with value,Reserved,Data addr/data addr limit/data value/linked data value/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data value/linked data value/data addr with value,?..." newline rbitfld.long 0x00 24. " MATCHED ,Comparator matched" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "1B,2B,4B,?..." bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace data address" newline bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..." if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08))&0x0E)==0x02) group.long 0x90++0x03 line.long 0x00 "DWT_COMP7,DWT Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " PCVALUE ,PC value" else group.long 0x90++0x03 line.long 0x00 "DWT_COMP7,DWT Comparator Register 7" endif group.long (0x90+0x08)++0x03 line.long 0x00 "DWT_FUNCTION7,DWT Function Register 7" rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr with value,Cycle counter/data addr/data addr with value,Instruction addr/data addr/data addr with value,Cycle counter/instruction addr/data addr/data addr with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr limit/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data addr with value,Reserved,Data addr/data addr limit/data value/linked data value/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data value/linked data value/data addr with value,?..." newline rbitfld.long 0x00 24. " MATCHED ,Comparator matched" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "1B,2B,4B,?..." bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace data address" newline bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..." rgroup.long 0xFBC++0x03 line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register" hexmask.long.word 0x00 21.--31. 0x20 " ARCHITECT ,Component architect" bitfld.long 0x00 20. " PRESENT ,Register present" "Reserved,Present" bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "DWT v2.0,DWT v2.1,?..." newline bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "Reserved,DWT v2,?..." hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part" rgroup.long 0xFCC++0x03 line.long 0x00 "DWT_DEVTYPE,DWT Device Type Identifier Register" bitfld.long 0x00 4.--7. " SUB ,Sub-type" "Other,?..." bitfld.long 0x00 0.--3. " MAJOR ,Major type" "Miscellaneous,?..." width 11. tree "Peripheral Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "DWT_PIDR0,DWT Peripheral Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " PART_NUM[7:0] ,Part number bits[7:0]" line.long 0x04 "DWT_PIDR1,DWT Peripheral Identification Register 1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " PART_NUM[11:8] ,Part number bits[11:8]" line.long 0x08 "DWT_PIDR2,DWT Peripheral Identification Register 2" hexmask.long.byte 0x08 4.--7. 1. " REVISION ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "DWT_PIDR3,DWT Peripheral Identification Register 3" hexmask.long.byte 0x0C 4.--7. 1. " REVAND ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x0F line.long 0x00 "DWT_PIDR4,DWT Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " COUNT ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" line.long 0x04 "DWT_PIDR5,DWT Peripheral Identification Register 5" line.long 0x08 "DWT_PIDR6,DWT Peripheral Identification Register 6" line.long 0x0C "DWT_PIDR7,DWT Peripheral Identification Register 7" rgroup.long 0xFF0++0x0F line.long 0x00 "DWT_CIDR0,DWT Component Identification Register 0 (Preamble)" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "DWT_CIDR1,DWT Component Identification Register 1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class" line.long 0x08 "DWT_CIDR2,DWT Component Identification Register 2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0C "DWT_CIDR3,DWT Component Identification Register 3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree "Performance Monitoring Unit Extension (PMU)" sif COMPonent.AVAILABLE("BMC") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1)) width 16. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x08) group.long 0x0++0x03 line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x4++0x03 line.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x8++0x03 line.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0xC++0x03 line.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x10++0x03 line.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x14++0x03 line.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x18++0x03 line.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x1C++0x03 line.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x07) group.long 0x0++0x03 line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x4++0x03 line.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x8++0x03 line.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0xC++0x03 line.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x10++0x03 line.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x14++0x03 line.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x18++0x03 line.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" hgroup.long 0x1C++0x03 hide.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x06) group.long 0x0++0x03 line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x4++0x03 line.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x8++0x03 line.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0xC++0x03 line.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x10++0x03 line.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x14++0x03 line.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" hgroup.long 0x18++0x03 hide.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register" hgroup.long 0x1C++0x03 hide.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x05) group.long 0x0++0x03 line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x4++0x03 line.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x8++0x03 line.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0xC++0x03 line.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x10++0x03 line.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" hgroup.long 0x14++0x03 hide.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register" hgroup.long 0x18++0x03 hide.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register" hgroup.long 0x1C++0x03 hide.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x04) group.long 0x0++0x03 line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x4++0x03 line.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x8++0x03 line.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0xC++0x03 line.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" hgroup.long 0x10++0x03 hide.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register" hgroup.long 0x14++0x03 hide.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register" hgroup.long 0x18++0x03 hide.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register" hgroup.long 0x1C++0x03 hide.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x03) group.long 0x0++0x03 line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x4++0x03 line.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x8++0x03 line.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" hgroup.long 0xC++0x03 hide.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register" hgroup.long 0x10++0x03 hide.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register" hgroup.long 0x14++0x03 hide.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register" hgroup.long 0x18++0x03 hide.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register" hgroup.long 0x1C++0x03 hide.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x02) group.long 0x0++0x03 line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" group.long 0x4++0x03 line.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" hgroup.long 0x8++0x03 hide.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register" hgroup.long 0xC++0x03 hide.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register" hgroup.long 0x10++0x03 hide.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register" hgroup.long 0x14++0x03 hide.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register" hgroup.long 0x18++0x03 hide.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register" hgroup.long 0x1C++0x03 hide.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x01) group.long 0x0++0x03 line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter" hgroup.long 0x4++0x03 hide.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register" hgroup.long 0x8++0x03 hide.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register" hgroup.long 0xC++0x03 hide.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register" hgroup.long 0x10++0x03 hide.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register" hgroup.long 0x14++0x03 hide.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register" hgroup.long 0x18++0x03 hide.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register" hgroup.long 0x1C++0x03 hide.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register" else hgroup.long 0x0++0x03 hide.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register" hgroup.long 0x4++0x03 hide.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register" hgroup.long 0x8++0x03 hide.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register" hgroup.long 0xC++0x03 hide.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register" hgroup.long 0x10++0x03 hide.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register" hgroup.long 0x14++0x03 hide.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register" hgroup.long 0x18++0x03 hide.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register" hgroup.long 0x1C++0x03 hide.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register" endif group.long 0x7C++0x03 line.long 0x00 "PMU_CCNTR,Performance Monitoring Unit Cycle Counter Register" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x08) group.long 0x400++0x03 line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x404++0x03 line.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x408++0x03 line.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x40C++0x03 line.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x410++0x03 line.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x414++0x03 line.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x418++0x03 line.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x41C++0x03 line.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x07) group.long 0x400++0x03 line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x404++0x03 line.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x408++0x03 line.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x40C++0x03 line.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x410++0x03 line.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x414++0x03 line.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x418++0x03 line.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" hgroup.long 0x41C++0x03 hide.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x06) group.long 0x400++0x03 line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x404++0x03 line.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x408++0x03 line.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x40C++0x03 line.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x410++0x03 line.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x414++0x03 line.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" hgroup.long 0x418++0x03 hide.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x41C++0x03 hide.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x05) group.long 0x400++0x03 line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x404++0x03 line.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x408++0x03 line.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x40C++0x03 line.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x410++0x03 line.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" hgroup.long 0x414++0x03 hide.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x418++0x03 hide.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x41C++0x03 hide.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x04) group.long 0x400++0x03 line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x404++0x03 line.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x408++0x03 line.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x40C++0x03 line.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" hgroup.long 0x410++0x03 hide.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x414++0x03 hide.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x418++0x03 hide.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x41C++0x03 hide.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x03) group.long 0x400++0x03 line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x404++0x03 line.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x408++0x03 line.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" hgroup.long 0x40C++0x03 hide.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x410++0x03 hide.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x414++0x03 hide.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x418++0x03 hide.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x41C++0x03 hide.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x02) group.long 0x400++0x03 line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" group.long 0x404++0x03 line.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" hgroup.long 0x408++0x03 hide.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x40C++0x03 hide.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x410++0x03 hide.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x414++0x03 hide.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x418++0x03 hide.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x41C++0x03 hide.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x01) group.long 0x400++0x03 line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register" hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number" hgroup.long 0x404++0x03 hide.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x408++0x03 hide.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x40C++0x03 hide.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x410++0x03 hide.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x414++0x03 hide.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x418++0x03 hide.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x41C++0x03 hide.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register" else hgroup.long 0x400++0x03 hide.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x404++0x03 hide.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x408++0x03 hide.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x40C++0x03 hide.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x410++0x03 hide.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x414++0x03 hide.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x418++0x03 hide.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register" hgroup.long 0x41C++0x03 hide.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register" endif rgroup.long 0x47C++0x03 line.long 0x00 "PMU_CCFILTR,Performance Monitoring Unit Cycle Counter Filter Register" group.long 0xC00++0x03 line.long 0x00 "PMU_CNTENSET,Performance Monitoring Unit Count Enable Set Register" bitfld.long 0x00 31. " C ,Cycle counter enable bit" "Disabled,Enabled" bitfld.long 0x00 7. " P7 ,Event counter PMN 7 enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " P6 ,Event counter PMN 6 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 5. " P5 ,Event counter PMN 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,Event counter PMN 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,Event counter PMN 3 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 2. " P2 ,Event counter PMN 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,Event counter PMN 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,Event counter PMN 0 enable bit" "Disabled,Enabled" group.long 0xC20++0x03 line.long 0x00 "PMU_CNTENCLR,Performance Monitoring Unit Count Enable Clear Register" bitfld.long 0x00 31. " C ,Cycle counter enable bit" "Disabled,Enabled" bitfld.long 0x00 7. " P7 ,Event counter PMN 7 enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " P6 ,Event counter PMN 6 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 5. " P5 ,Event counter PMN 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,Event counter PMN 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,Event counter PMN 3 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 2. " P2 ,Event counter PMN 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,Event counter PMN 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,Event counter PMN 0 enable bit" "Disabled,Enabled" group.long 0xC40++0x03 line.long 0x00 "PMU_INTENSET,Performance Monitoring Unit Interrupt Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " P7 ,PMCNT7 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " P6 ,PMCNT6 overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " P5 ,PMCNT5 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMCNT4 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " P2 ,PMCNT2 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMCNT1 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMCNT0 overflow interrupt enable" "Disabled,Enabled" group.long 0xC60++0x03 line.long 0x00 "PMU_INTENCLR,Performance Monitoring Unit Interrupt Enable Clear Register" bitfld.long 0x00 31. " C ,CCNT overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " P7 ,PMCNT7 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " P6 ,PMCNT6 overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " P5 ,PMCNT5 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMCNT4 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMCNT3 overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " P2 ,PMCNT2 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMCNT1 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMCNT0 overflow interrupt enable" "Disabled,Enabled" group.long 0xC80++0x03 line.long 0x00 "PMU_OVSCLR,Performance Monitoring Unit Overflow Flag Status Clear Register" bitfld.long 0x00 31. " C ,PMCCNTR overflow" "No overflow,Overflow" bitfld.long 0x00 7. " P7 ,PMN7 overflow" "No overflow,Overflow" bitfld.long 0x00 6. " P6 ,PMN6 overflow" "No overflow,Overflow" newline bitfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow" bitfld.long 0x00 4. " P4 ,PMN4 overflow" "No overflow,Overflow" bitfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow" newline bitfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow" bitfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow" bitfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow" wgroup.long 0xCA0++0x03 line.long 0x00 "PMU_SWINC,Performance Monitoring Unit Software Increment Register" bitfld.long 0x00 7. " P7 ,PMN7 software increment" "Disabled,Enabled" bitfld.long 0x00 6. " P6 ,PMN6 software increment" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMN5 software increment" "Disabled,Enabled" newline bitfld.long 0x00 4. " P4 ,PMN4 software increment" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMN3 software increment" "Disabled,Enabled" bitfld.long 0x00 2. " P2 ,PMN2 software increment" "Disabled,Enabled" newline bitfld.long 0x00 1. " P1 ,PMN1 software increment" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMN0 software increment" "Disabled,Enabled" group.long 0xCC0++0x03 line.long 0x00 "PMU_OVSSET,Performance Monitoring Unit Overflow Flag Status Set Register" bitfld.long 0x00 31. " C ,PMCCNTR overflow" "No overflow,Overflow" bitfld.long 0x00 7. " P7 ,PMN7 overflow" "No overflow,Overflow" bitfld.long 0x00 6. " P6 ,PMN6 overflow" "No overflow,Overflow" newline bitfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow" bitfld.long 0x00 4. " P4 ,PMN4 overflow" "No overflow,Overflow" bitfld.long 0x00 3. " P3 ,PMN3 Overflow" "No overflow,Overflow" newline bitfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow" bitfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow" bitfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow" rgroup.long 0xE00++0x03 line.long 0x00 "PMU_TYPE,Performance Monitoring Unit Type Register" bitfld.long 0x00 23. " TRO ,Trace-on-overflow support" "Not supported,Supported" bitfld.long 0x00 21. " FZO ,Freeze-on-overflow support" "Not supported,Supported" bitfld.long 0x00 14. " CC ,Dedicated cycle counter" "Disabled,Enabled" newline bitfld.long 0x00 8.--13. " SIZE ,Size of counters" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" hexmask.long.byte 0x00 0.--7. 1. " N ,Number of event counters" group.long 0xE04++0x03 line.long 0x00 "PMU_CTRL,Performance Monitors Unit Control Register" bitfld.long 0x00 11. " TRO ,Trace-on-overflow" "Disabled,Enabled" bitfld.long 0x00 9. " FZO ,Freeze-on-overflow" "Disabled,Enabled" bitfld.long 0x00 5. " DP ,Disable cycle counter in prohibited regions" "No,Yes" newline bitfld.long 0x00 2. " C ,Clock counter reset" "No reset,Reset" bitfld.long 0x00 1. " P ,Event counter reset" "No reset,Reset" bitfld.long 0x00 0. " E ,Counters enable" "Disabled,Enabled" rgroup.long 0xFB8++0x07 line.long 0x00 "PMU_AUTHSTATUS,Performance Monitoring Unit Authentication Status Register" bitfld.long 0x00 22.--23. " SUNID ,Secure unprivileged non-invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed" bitfld.long 0x00 20.--21. " SUID ,Secure unprivileged invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed" bitfld.long 0x00 18.--19. " NSUNID ,Non-secure unprivileged non-invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed" newline bitfld.long 0x00 16.--17. " NSUID ,Non-secure unprivileged invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed" bitfld.long 0x00 6.--7. " SNID ,Secure non-invasive debug" "Not implemented,Reserved,Implemented/Prohibited,Implemented/Allowed" bitfld.long 0x00 4.--5. " SID ,Secure invasive debug" "Not implemented,Reserved,Implemented/Prohibited,Implemented/Allowed" newline bitfld.long 0x00 2.--3. " NSNID ,Non-secure non-invasive debug" "Reserved,Reserved,Prohibited,Allowed" bitfld.long 0x00 0.--1. " NSID ,Non-secure invasive debug" "Reserved,Reserved,Prohibited,Allowed" line.long 0x04 "PMU_DEVARCH,Performance Monitoring Unit Device Architecture Register" hexmask.long.word 0x04 21.--31. 1. " ARCHITECT ,Defines the architect of the component" bitfld.long 0x04 20. " PRESENT ,Defines that the DEVARCH register is present" "Reserved,Present" bitfld.long 0x04 16.--19. " REVISION ,Defines the architecture revision" "Armv8.1-M,?..." newline hexmask.long.word 0x04 0.--15. 1. " ARCHID ,Defines this part to be a ARMv8-M debug component" rgroup.long 0xFCC++0x03 line.long 0x00 "PMU_DEVTYPE,Device Type Register" bitfld.long 0x00 4.--7. " SUB ,Sub-type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " MAJOR ,Major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree "Peripheral Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PMU_PIDR0,PMU Peripheral Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " PART_NUM[7:0] ,Part number bits[7:0]" line.long 0x04 "PMU_PIDR1,PMU Peripheral Identification Register 1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " PART_NUM[11:8] ,Part number bits[11:8]" line.long 0x08 "PMU_PIDR2,PMU Peripheral Identification Register 2" hexmask.long.byte 0x08 4.--7. 1. " REVISION ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PMU_PIDR3,PMU Peripheral Identification Register 3" hexmask.long.byte 0x0C 4.--7. 1. " REVAND ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x0F line.long 0x00 "PMU_PIDR4,PMU Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " COUNT ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" line.long 0x04 "PMU_PIDR5,PMU Peripheral Identification Register 5" line.long 0x08 "PMU_PIDR6,PMU Peripheral Identification Register 6" line.long 0x0C "PMU_PIDR7,PMU Peripheral Identification Register 7" rgroup.long 0xFF0++0x0F line.long 0x00 "PMU_CIDR0,PMU Component Identification Register 0 (Preamble)" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "PMU_CIDR1,PMU Component Identification Register 1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class preamble" line.long 0x08 "PMU_CIDR2,PMU Component Identification Register 2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0C "PMU_CIDR3,PMU Component Identification Register 3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end width 0x0B else newline textline "BMC component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end tree "ACMPHS (High-Speed Analog Comparator)" base ad:0x0 tree "ACMPHS0" base ad:0x40236000 group.byte 0x0++0x0 line.byte 0x0 "CMPCTL,Comparator Control Register" bitfld.byte 0x0 7. "HCMPON,Comparator Operation Control" "0: Stop operation (comparator outputs a low-level..,1: Enable operation (enables input to the.." bitfld.byte 0x0 5.--6. "CDFS,Noise Filter Selection" "0: Do not use noise filter,1: Use noise filter sampling frequency of PCLKB/23,?,?" newline bitfld.byte 0x0 3.--4. "CEG,Selection of Valid Edge (Edge Selector)" "0: Do not detect edge,1: Detect rising edge,?,?" bitfld.byte 0x0 2. "CSTEN,Interrupt Select" "0: Output through the edge selector,1: Output directly" newline bitfld.byte 0x0 1. "COE,Comparator Output Enable" "0: Disable comparator output (output signal is low..,1: Enable comparator output" bitfld.byte 0x0 0. "CINV,Comparator Output Polarity Selection" "0: Do not invert comparator output,1: Invert comparator output" group.byte 0x4++0x0 line.byte 0x0 "CMPSEL0,Comparator Input Select Register" hexmask.byte 0x0 0.--3. 1. "CMPSEL,Comparator Input Selection" group.byte 0x8++0x0 line.byte 0x0 "CMPSEL1,Comparator Reference Voltage Select Register" hexmask.byte 0x0 0.--3. 1. "CRVS,Reference Voltage Selection" rgroup.byte 0xC++0x0 line.byte 0x0 "CMPMON,Comparator Output Monitor Register" bitfld.byte 0x0 0. "COMPMON,Comparator Output Monitor" "0: Comparator output is low,1: Comparator output is high" group.byte 0x10++0x0 line.byte 0x0 "CPIOC,Comparator Output Control Register" bitfld.byte 0x0 7. "VREFEN" "0: Disable internal Vref,1: Enable internal Vref" bitfld.byte 0x0 0. "CPOE,External Pin Output Enable" "0: Output to the comparator external pin is..,1: Output to the comparator external pin is enabled" group.byte 0x40++0x0 line.byte 0x0 "CPINTCTL,Comparator Interrupt Control Register" bitfld.byte 0x0 0. "MSKE,Comparator Interrupt Periodic Mask Enable" "0: Disable interrupt masking (Default),1: Enable interrupt masking by GPT output signal.." group.byte 0x44++0x0 line.byte 0x0 "CPMSKCTL,Comparator Interrupt Mask Control Register" bitfld.byte 0x0 0.--2. "MSKSEL,Comparator Interrupt Periodic Mask Selection" "0: Setting prohibited.,1: Enable interrupt masking by GTIOC1A output signal,?,?,?,?,?,?" tree.end tree "ACMPHS0_NS" base ad:0x50236000 group.byte 0x0++0x0 line.byte 0x0 "CMPCTL,Comparator Control Register" bitfld.byte 0x0 7. "HCMPON,Comparator Operation Control" "0: Stop operation (comparator outputs a low-level..,1: Enable operation (enables input to the.." bitfld.byte 0x0 5.--6. "CDFS,Noise Filter Selection" "0: Do not use noise filter,1: Use noise filter sampling frequency of PCLKB/23,?,?" newline bitfld.byte 0x0 3.--4. "CEG,Selection of Valid Edge (Edge Selector)" "0: Do not detect edge,1: Detect rising edge,?,?" bitfld.byte 0x0 2. "CSTEN,Interrupt Select" "0: Output through the edge selector,1: Output directly" newline bitfld.byte 0x0 1. "COE,Comparator Output Enable" "0: Disable comparator output (output signal is low..,1: Enable comparator output" bitfld.byte 0x0 0. "CINV,Comparator Output Polarity Selection" "0: Do not invert comparator output,1: Invert comparator output" group.byte 0x4++0x0 line.byte 0x0 "CMPSEL0,Comparator Input Select Register" hexmask.byte 0x0 0.--3. 1. "CMPSEL,Comparator Input Selection" group.byte 0x8++0x0 line.byte 0x0 "CMPSEL1,Comparator Reference Voltage Select Register" hexmask.byte 0x0 0.--3. 1. "CRVS,Reference Voltage Selection" rgroup.byte 0xC++0x0 line.byte 0x0 "CMPMON,Comparator Output Monitor Register" bitfld.byte 0x0 0. "COMPMON,Comparator Output Monitor" "0: Comparator output is low,1: Comparator output is high" group.byte 0x10++0x0 line.byte 0x0 "CPIOC,Comparator Output Control Register" bitfld.byte 0x0 7. "VREFEN" "0: Disable internal Vref,1: Enable internal Vref" bitfld.byte 0x0 0. "CPOE,External Pin Output Enable" "0: Output to the comparator external pin is..,1: Output to the comparator external pin is enabled" group.byte 0x40++0x0 line.byte 0x0 "CPINTCTL,Comparator Interrupt Control Register" bitfld.byte 0x0 0. "MSKE,Comparator Interrupt Periodic Mask Enable" "0: Disable interrupt masking (Default),1: Enable interrupt masking by GPT output signal.." group.byte 0x44++0x0 line.byte 0x0 "CPMSKCTL,Comparator Interrupt Mask Control Register" bitfld.byte 0x0 0.--2. "MSKSEL,Comparator Interrupt Periodic Mask Selection" "0: Setting prohibited.,1: Enable interrupt masking by GTIOC1A output signal,?,?,?,?,?,?" tree.end tree "ACMPHS1" base ad:0x40236100 group.byte 0x0++0x0 line.byte 0x0 "CMPCTL,Comparator Control Register" bitfld.byte 0x0 7. "HCMPON,Comparator Operation Control" "0: Stop operation (comparator outputs a low-level..,1: Enable operation (enables input to the.." bitfld.byte 0x0 5.--6. "CDFS,Noise Filter Selection" "0: Do not use noise filter,1: Use noise filter sampling frequency of PCLKB/23,?,?" newline bitfld.byte 0x0 3.--4. "CEG,Selection of Valid Edge (Edge Selector)" "0: Do not detect edge,1: Detect rising edge,?,?" bitfld.byte 0x0 2. "CSTEN,Interrupt Select" "0: Output through the edge selector,1: Output directly" newline bitfld.byte 0x0 1. "COE,Comparator Output Enable" "0: Disable comparator output (output signal is low..,1: Enable comparator output" bitfld.byte 0x0 0. "CINV,Comparator Output Polarity Selection" "0: Do not invert comparator output,1: Invert comparator output" group.byte 0x4++0x0 line.byte 0x0 "CMPSEL0,Comparator Input Select Register" hexmask.byte 0x0 0.--3. 1. "CMPSEL,Comparator Input Selection" group.byte 0x8++0x0 line.byte 0x0 "CMPSEL1,Comparator Reference Voltage Select Register" hexmask.byte 0x0 0.--3. 1. "CRVS,Reference Voltage Selection" rgroup.byte 0xC++0x0 line.byte 0x0 "CMPMON,Comparator Output Monitor Register" bitfld.byte 0x0 0. "COMPMON,Comparator Output Monitor" "0: Comparator output is low,1: Comparator output is high" group.byte 0x10++0x0 line.byte 0x0 "CPIOC,Comparator Output Control Register" bitfld.byte 0x0 7. "VREFEN" "0: Disable internal Vref,1: Enable internal Vref" bitfld.byte 0x0 0. "CPOE,External Pin Output Enable" "0: Output to the comparator external pin is..,1: Output to the comparator external pin is enabled" group.byte 0x40++0x0 line.byte 0x0 "CPINTCTL,Comparator Interrupt Control Register" bitfld.byte 0x0 0. "MSKE,Comparator Interrupt Periodic Mask Enable" "0: Disable interrupt masking (Default),1: Enable interrupt masking by GPT output signal.." group.byte 0x44++0x0 line.byte 0x0 "CPMSKCTL,Comparator Interrupt Mask Control Register" bitfld.byte 0x0 0.--2. "MSKSEL,Comparator Interrupt Periodic Mask Selection" "0: Setting prohibited.,1: Enable interrupt masking by GTIOC1A output signal,?,?,?,?,?,?" tree.end tree "ACMPHS1_NS" base ad:0x50236100 group.byte 0x0++0x0 line.byte 0x0 "CMPCTL,Comparator Control Register" bitfld.byte 0x0 7. "HCMPON,Comparator Operation Control" "0: Stop operation (comparator outputs a low-level..,1: Enable operation (enables input to the.." bitfld.byte 0x0 5.--6. "CDFS,Noise Filter Selection" "0: Do not use noise filter,1: Use noise filter sampling frequency of PCLKB/23,?,?" newline bitfld.byte 0x0 3.--4. "CEG,Selection of Valid Edge (Edge Selector)" "0: Do not detect edge,1: Detect rising edge,?,?" bitfld.byte 0x0 2. "CSTEN,Interrupt Select" "0: Output through the edge selector,1: Output directly" newline bitfld.byte 0x0 1. "COE,Comparator Output Enable" "0: Disable comparator output (output signal is low..,1: Enable comparator output" bitfld.byte 0x0 0. "CINV,Comparator Output Polarity Selection" "0: Do not invert comparator output,1: Invert comparator output" group.byte 0x4++0x0 line.byte 0x0 "CMPSEL0,Comparator Input Select Register" hexmask.byte 0x0 0.--3. 1. "CMPSEL,Comparator Input Selection" group.byte 0x8++0x0 line.byte 0x0 "CMPSEL1,Comparator Reference Voltage Select Register" hexmask.byte 0x0 0.--3. 1. "CRVS,Reference Voltage Selection" rgroup.byte 0xC++0x0 line.byte 0x0 "CMPMON,Comparator Output Monitor Register" bitfld.byte 0x0 0. "COMPMON,Comparator Output Monitor" "0: Comparator output is low,1: Comparator output is high" group.byte 0x10++0x0 line.byte 0x0 "CPIOC,Comparator Output Control Register" bitfld.byte 0x0 7. "VREFEN" "0: Disable internal Vref,1: Enable internal Vref" bitfld.byte 0x0 0. "CPOE,External Pin Output Enable" "0: Output to the comparator external pin is..,1: Output to the comparator external pin is enabled" group.byte 0x40++0x0 line.byte 0x0 "CPINTCTL,Comparator Interrupt Control Register" bitfld.byte 0x0 0. "MSKE,Comparator Interrupt Periodic Mask Enable" "0: Disable interrupt masking (Default),1: Enable interrupt masking by GPT output signal.." group.byte 0x44++0x0 line.byte 0x0 "CPMSKCTL,Comparator Interrupt Mask Control Register" bitfld.byte 0x0 0.--2. "MSKSEL,Comparator Interrupt Periodic Mask Selection" "0: Setting prohibited.,1: Enable interrupt masking by GTIOC1A output signal,?,?,?,?,?,?" tree.end tree.end tree "ADC12 (12-Bit A/D Converter)" base ad:0x0 tree "ADC120" base ad:0x40332000 group.word 0x0++0x1 line.word 0x0 "ADCSR,A/D Control Register" bitfld.word 0x0 15. "ADST,A/D Conversion Start" "0: Stop A/D conversion process.,1: Start A/D conversion process." bitfld.word 0x0 13.--14. "ADCS,Scan Mode Select" "0: Single scan mode,1: Group scan mode,?,?" newline bitfld.word 0x0 9. "TRGE,Trigger Start Enable" "0: Disable A/D conversion to be started by the..,1: Enable A/D conversion to be started by the.." bitfld.word 0x0 8. "EXTRG,Trigger Select" "0: Start A/D conversion by the synchronous trigger..,1: Start A/D conversion by the asynchronous trigger.." newline bitfld.word 0x0 7. "DBLE,Double Trigger Mode Select" "0: Deselect double-trigger mode.,1: Select double-trigger mode." bitfld.word 0x0 6. "GBADIE,Group B Scan End Interrupt and ELC Event Enable" "0: Disable ADC12i_GBADI (i = 0 1) interrupt..,1: Enable ADC12i_GBADI (i = 0 1) interrupt.." newline hexmask.word.byte 0x0 0.--4. 1. "DBLANS,Double Trigger Channel Select" group.word 0x4++0x7 line.word 0x0 "ADANSA0,A/D Channel Select Register A0" bitfld.word 0x0 8. "ANSA08,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x0 7. "ANSA07,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x0 6. "ANSA06,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x0 5. "ANSA05,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x0 4. "ANSA04,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x0 3. "ANSA03,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x0 2. "ANSA02,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x0 1. "ANSA01,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x0 0. "ANSA00,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." line.word 0x2 "ADANSA1,A/D Channel Select Register A1" bitfld.word 0x2 6. "ANSA22,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x2 5. "ANSA21,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x2 4. "ANSA20,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x2 3. "ANSA19,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x2 2. "ANSA18,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x2 1. "ANSA17,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x2 0. "ANSA16,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." line.word 0x4 "ADADS0,A/D-Converted Value Addition/Average Channel Select Register 0" bitfld.word 0x4 8. "ADS08,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x4 7. "ADS07,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x4 6. "ADS06,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x4 5. "ADS05,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x4 4. "ADS04,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x4 3. "ADS03,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x4 2. "ADS02,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x4 1. "ADS01,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x4 0. "ADS00,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." line.word 0x6 "ADADS1,A/D-Converted Value Addition/Average Channel Select Register 1" bitfld.word 0x6 6. "ADS22,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 5. "ADS21,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 4. "ADS20,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 3. "ADS19,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 2. "ADS18,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 1. "ADS17,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 0. "ADS16,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." group.byte 0xC++0x0 line.byte 0x0 "ADADC,A/D-Converted Value Addition/Average Count Select Register" bitfld.byte 0x0 7. "AVEE,Average Mode Select" "0: Enable addition mode,1: Enable average mode" bitfld.byte 0x0 0.--2. "ADC,Addition/Average Count Select" "0: Setting prohibited,1: 2-time conversion (1 addition),?,?,?,?,?,?" group.word 0xE++0x9 line.word 0x0 "ADCER,A/D Control Extended Register" bitfld.word 0x0 15. "ADRFMT,A/D Data Register Format Select" "0: Select right-justified for the A/D data register..,1: Select left-justified for the A/D data register.." bitfld.word 0x0 11. "DIAGM,Self-Diagnosis Enable" "0: Disable ADC12 self-diagnosis,1: Enable ADC12 self-diagnosis" newline bitfld.word 0x0 10. "DIAGLD,Self-Diagnosis Mode Select" "0: Select rotation mode for self-diagnosis voltage,1: Select mixed mode for self-diagnosis voltage" bitfld.word 0x0 8.--9. "DIAGVAL,Self-Diagnosis Conversion Voltage Select" "0: Setting prohibited when self-diagnosis is enabled,1: 0 volts,?,?" newline bitfld.word 0x0 5. "ACE,A/D Data Register Automatic Clearing Enable" "0: Disable automatic clearing,1: Enable automatic clearing" bitfld.word 0x0 1.--2. "ADPRC" "0: 12-bit accuracy,1: 10-bit accuracy,?,?" line.word 0x2 "ADSTRGR,A/D Conversion Start Trigger Select Register" hexmask.word.byte 0x2 8.--13. 1. "TRSA,A/D Conversion Start Trigger Select" hexmask.word.byte 0x2 0.--5. 1. "TRSB,A/D Conversion Start Trigger Select for Group B" line.word 0x4 "ADEXICR,A/D Conversion Extended Input Control Registers" bitfld.word 0x4 11. "OCSB,Internal Reference Voltage A/D Conversion Select for Group B" "0: Disable A/D conversion of internal reference..,1: Enable A/D conversion of internal reference.." bitfld.word 0x4 10. "TSSB,Temperature Sensor Output A/D Conversion Select for Group B" "0: Disable A/D conversion of temperature sensor..,1: Enable A/D conversion of temperature sensor output" newline bitfld.word 0x4 9. "OCSA,Internal Reference Voltage A/D Conversion Select" "0: Disable A/D conversion of internal reference..,1: Enable A/D conversion of internal reference.." bitfld.word 0x4 8. "TSSA,Temperature Sensor Output A/D Conversion Select" "0: Disable A/D conversion of temperature sensor..,1: Enable A/D conversion of temperature sensor output" newline bitfld.word 0x4 1. "OCSAD,Internal Reference Voltage A/D-Converted Value Addition/Average Mode Select" "0: Do not select addition/average mode for internal..,1: Select addition/average mode for internal.." bitfld.word 0x4 0. "TSSAD,Temperature Sensor Output A/D-Converted Value Addition/Average Mode Select" "0: Do not select addition/average mode for..,1: Select addition/average mode for temperature.." line.word 0x6 "ADANSB0,A/D Channel Select Register B0" bitfld.word 0x6 8. "ANSB08,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 7. "ANSB07,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 6. "ANSB06,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 5. "ANSB05,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 4. "ANSB04,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 3. "ANSB03,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 2. "ANSB02,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 1. "ANSB01,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 0. "ANSB00,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." line.word 0x8 "ADANSB1,A/D Channel Select Register B1" bitfld.word 0x8 6. "ANSB22,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x8 5. "ANSB21,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x8 4. "ANSB20,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x8 3. "ANSB19,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x8 2. "ANSB18,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x8 1. "ANSB17,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x8 0. "ANSB16,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." rgroup.word 0x18++0x7 line.word 0x0 "ADDBLDR,A/D Data Duplexing Register" hexmask.word 0x0 0.--15. 1. "ADDBLDR,Converted Value 15 to 0" line.word 0x2 "ADTSDR,A/D Temperature Sensor Data Register" hexmask.word 0x2 0.--15. 1. "ADTSDR,Converted Value 15 to 0" line.word 0x4 "ADOCDR,A/D Internal Reference Voltage Data Register" hexmask.word 0x4 0.--15. 1. "ADOCDR,Converted Value 15 to 0" line.word 0x6 "ADRD,A/D Self-Diagnosis Data Register" bitfld.word 0x6 14.--15. "DIAGST,Self-Diagnosis Status" "0: Self-diagnosis not executed after power-on.,1: Self-diagnosis was executed using the 0 V voltage.,?,?" hexmask.word 0x6 0.--11. 1. "AD,Converted Value 11 to 0" repeat 9. (increment 0x0 0x1)(increment 0x0 0x2) rgroup.word ($2+0x20)++0x1 line.word 0x0 "ADDR$1,A/D Data Registers %s" hexmask.word 0x0 0.--15. 1. "ADDR,Converted Value 15 to 0" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x2) rgroup.word ($2+0x20)++0x1 line.word 0x0 "ADDR$1,A/D Data Registers %s" hexmask.word 0x0 0.--15. 1. "ADDR,Converted Value 15 to 0" repeat.end rgroup.word 0x26++0x1 line.word 0x0 "ADVMDR,A/D VBATT Monitor Data Register" hexmask.word 0x0 0.--15. 1. "ADDR,Converted Value 15 to 0" group.word 0x66++0x1 line.word 0x0 "ADSHCR,A/D Sample and Hold Circuit Control Register" bitfld.word 0x0 8.--9. "SHANS,Channel-Dedicated Sample-and-Hold Circuit Bypass Select" "0: Bypass the circuits,1: Use the circuits,?,?" hexmask.word.byte 0x0 0.--7. 1. "SSTSH,Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting" group.byte 0x7A++0x0 line.byte 0x0 "ADDISCR,A/D Disconnection Detection Control Register" bitfld.byte 0x0 4. "PCHG,Precharge/discharge select" "0: Discharge,1: Precharge" hexmask.byte 0x0 0.--3. 1. "ADNDIS,Disconnection Detection Assist Setting" group.byte 0x7C++0x0 line.byte 0x0 "ADSHMSR,A/D Sample and Hold Operation Mode Selection Register" bitfld.byte 0x0 0. "SHMD,Sampling Operation Selection" "0: Sampling Operation Selection,1: Enable continuous sampling function" group.word 0x80++0x1 line.word 0x0 "ADGSPCR,A/D Group Scan Priority Control Register" bitfld.word 0x0 15. "GBRP,Single Scan Continuous Start" "0: Single scan is not continuously activated.,1: Single scan for the group with the.." bitfld.word 0x0 14. "LGRRS,Enabled only when PGS = 1 and GBRSCN = 1." "0: Start rescanning from the first channel for..,1: Start rescanning from the channel for which A/D.." newline bitfld.word 0x0 1. "GBRSCN,Lower-Priority Group Restart Setting" "0: Disable rescanning of the group that was stopped..,1: Enable rescanning of the group that was stopped.." bitfld.word 0x0 0. "PGS,Group Priority Operation Setting" "0: Operate without group priority control.,1: Operate with group priority control." rgroup.word 0x84++0x3 line.word 0x0 "ADDBLDRA,A/D Data Duplexing Register A" hexmask.word 0x0 0.--15. 1. "ADDBLDR,Converted Value 15 to 0" line.word 0x2 "ADDBLDRB,A/D Data Duplexing Register B" hexmask.word 0x2 0.--15. 1. "ADDBLDR,Converted Value 15 to 0" rgroup.byte 0x8C++0x0 line.byte 0x0 "ADWINMON,A/D Compare Function Window A/B Status Monitor Register" bitfld.byte 0x0 5. "MONCMPB,Comparison Result Monitor B" "0: Window B comparison conditions are not met.,1: Window B comparison conditions are met." bitfld.byte 0x0 4. "MONCMPA,Comparison Result Monitor A" "0: Window A comparison conditions are not met.,1: Window A comparison conditions are met." newline bitfld.byte 0x0 0. "MONCOMB,Combination Result Monitor" "0: Window A/B composite conditions are not met.,1: Window A/B composite conditions are met." group.word 0x90++0x1 line.word 0x0 "ADCMPCR,A/D Compare Function Control Register" bitfld.word 0x0 15. "CMPAIE,Compare A Interrupt Enable" "0: Disable ADC12i_CMPAI (i = 0 1) interrupt when..,1: Enable ADC12i_CMPAI (i = 0 1) interrupt when.." bitfld.word 0x0 14. "WCMPE,Window Function Setting" "0: Disable window function Window A and window B..,1: Enable window function Window A and window B.." newline bitfld.word 0x0 13. "CMPBIE,Compare B Interrupt Enable" "0: Disable ADC12i_CMPBI (i = 0 1) interrupt when..,1: Enable ADC12i_CMPBI (i = 0 1) interrupt when.." bitfld.word 0x0 11. "CMPAE,Compare Window A Operation Enable" "0: Disable compare window A operation. Disable..,1: Enable compare window A operation." newline bitfld.word 0x0 9. "CMPBE,Compare Window B Operation Enable" "0: Disable compare window B operation. Disable..,1: Enable compare window B operation." bitfld.word 0x0 0.--1. "CMPAB,Window A/B Composite Conditions Setting" "0: Output ADC12i_WCMPM (i = 0 1) when window A OR..,1: Output ADC12i_WCMPM (i = 0 1) when window A EXOR..,?,?" group.byte 0x92++0x1 line.byte 0x0 "ADCMPANSER,A/D Compare Function Window A Extended Input Select Register" bitfld.byte 0x0 1. "CMPOCA,Internal Reference Voltage Compare Select" "0: Exclude the internal reference voltage from the..,1: Include the internal reference voltage in the.." bitfld.byte 0x0 0. "CMPTSA,Temperature Sensor Output Compare Select" "0: Exclude the temperature sensor output from the..,1: Include the temperature sensor output in the.." line.byte 0x1 "ADCMPLER,A/D Compare Function Window A Extended Input Comparison Condition Setting Register" bitfld.byte 0x1 1. "CMPLOCA,Compare Window A Internal Reference Voltage Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.byte 0x1 0. "CMPLTSA,Compare Window A Temperature Sensor Output Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." group.word 0x94++0x1 line.word 0x0 "ADCMPANSR0,A/D Compare Function Window A Channel Select Register 0" bitfld.word 0x0 15. "CMPCHA15,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 14. "CMPCHA14,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 13. "CMPCHA13,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 12. "CMPCHA12,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 11. "CMPCHA11,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 10. "CMPCHA10,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 9. "CMPCHA09,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 8. "CMPCHA08,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 7. "CMPCHA07,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 6. "CMPCHA06,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 5. "CMPCHA05,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 4. "CMPCHA04,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 3. "CMPCHA03,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 2. "CMPCHA02,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 1. "CMPCHA01,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 0. "CMPCHA00,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." group.word 0x98++0x1 line.word 0x0 "ADCMPLR0,A/D Compare Function Window A Comparison Condition Setting Register 0" bitfld.word 0x0 15. "CMPLCHA15,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 14. "CMPLCHA14,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 13. "CMPLCHA13,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 12. "CMPLCHA12,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 11. "CMPLCHA11,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 10. "CMPLCHA10,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 9. "CMPLCHA09,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 8. "CMPLCHA08,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 7. "CMPLCHA07,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 6. "CMPLCHA06,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 5. "CMPLCHA05,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 4. "CMPLCHA04,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 3. "CMPLCHA03,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 2. "CMPLCHA02,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 1. "CMPLCHA01,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 0. "CMPLCHA00,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." repeat 2. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0x9C)++0x1 line.word 0x0 "ADCMPDR$1,A/D Compare Function Window A Lower-Side/Upper-Side Level Setting Register" repeat.end group.word 0xA0++0x1 line.word 0x0 "ADCMPSR0,A/D Compare Function Window A Channel Status Register 0" bitfld.word 0x0 15. "CMPSTCHA15,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 14. "CMPSTCHA14,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 13. "CMPSTCHA13,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 12. "CMPSTCHA12,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 11. "CMPSTCHA11,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 10. "CMPSTCHA10,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 9. "CMPSTCHA09,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 8. "CMPSTCHA08,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 7. "CMPSTCHA07,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 6. "CMPSTCHA06,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 5. "CMPSTCHA05,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 4. "CMPSTCHA04,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 3. "CMPSTCHA03,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 2. "CMPSTCHA02,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 1. "CMPSTCHA01,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 0. "CMPSTCHA00,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." group.byte 0xA4++0x0 line.byte 0x0 "ADCMPSER,A/D Compare Function Window A Extended Input Channel Status Register" bitfld.byte 0x0 1. "CMPSTOCA,Compare Window A Internal Reference Voltage Compare Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.byte 0x0 0. "CMPSTTSA,Compare Window A Temperature Sensor Output Compare Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." group.byte 0xA6++0x0 line.byte 0x0 "ADCMPBNSR,A/D Compare Function Window B Channel Select Register" bitfld.byte 0x0 7. "CMPLB,Compare Window B Comparison Condition Setting" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." hexmask.byte 0x0 0.--5. 1. "CMPCHB,Compare Window B Channel Select" group.word 0xA8++0x3 line.word 0x0 "ADWINLLB,A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register" line.word 0x2 "ADWINULB,A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register" group.byte 0xAC++0x0 line.byte 0x0 "ADCMPBSR,A/D Compare Function Window B Status Register" bitfld.byte 0x0 0. "CMPSTB,Compare Window B Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." repeat 16. (increment 0x0 0x1)(increment 0x0 0x2) rgroup.word ($2+0xB0)++0x1 line.word 0x0 "ADBUF$1,A/D Data Buffer Registers %s" hexmask.word 0x0 0.--15. 1. "ADBUF,Converted Value 15 to 0" repeat.end group.byte 0xD0++0x0 line.byte 0x0 "ADBUFEN,A/D Data Buffer Enable Register" bitfld.byte 0x0 0. "BUFEN,Data Buffer Enable" "0: The data buffer is not used.,1: The data buffer is used." group.byte 0xD2++0x0 line.byte 0x0 "ADBUFPTR,A/D Data Buffer Pointer Register" bitfld.byte 0x0 4. "PTROVF,Pointer Overflow Flag" "0: The data buffer pointer has not overflowed.,1: The data buffer pointer has overflowed." hexmask.byte 0x0 0.--3. 1. "BUFPTR,Data Buffer Pointer" group.byte 0xDD++0x2 line.byte 0x0 "ADSSTRL,A/D Sampling State Register" hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting" line.byte 0x1 "ADSSTRT,A/D Sampling State Register" hexmask.byte 0x1 0.--7. 1. "SST,Sampling Time Setting" line.byte 0x2 "ADSSTRO,A/D Sampling State Register" hexmask.byte 0x2 0.--7. 1. "SST,Sampling Time Setting" repeat 9. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0xE0)++0x0 line.byte 0x0 "ADSSTR$1,A/D Sampling State Register" hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting" repeat.end group.byte 0xE3++0x0 line.byte 0x0 "ADSSTRV,A/D Sampling State Register" hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting" repeat 4. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0xEC)++0x0 line.byte 0x0 "ADSSTR$1,A/D Sampling State Register" hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting" repeat.end tree.end tree "ADC120_NS" base ad:0x50332000 group.word 0x0++0x1 line.word 0x0 "ADCSR,A/D Control Register" bitfld.word 0x0 15. "ADST,A/D Conversion Start" "0: Stop A/D conversion process.,1: Start A/D conversion process." bitfld.word 0x0 13.--14. "ADCS,Scan Mode Select" "0: Single scan mode,1: Group scan mode,?,?" newline bitfld.word 0x0 9. "TRGE,Trigger Start Enable" "0: Disable A/D conversion to be started by the..,1: Enable A/D conversion to be started by the.." bitfld.word 0x0 8. "EXTRG,Trigger Select" "0: Start A/D conversion by the synchronous trigger..,1: Start A/D conversion by the asynchronous trigger.." newline bitfld.word 0x0 7. "DBLE,Double Trigger Mode Select" "0: Deselect double-trigger mode.,1: Select double-trigger mode." bitfld.word 0x0 6. "GBADIE,Group B Scan End Interrupt and ELC Event Enable" "0: Disable ADC12i_GBADI (i = 0 1) interrupt..,1: Enable ADC12i_GBADI (i = 0 1) interrupt.." newline hexmask.word.byte 0x0 0.--4. 1. "DBLANS,Double Trigger Channel Select" group.word 0x4++0x7 line.word 0x0 "ADANSA0,A/D Channel Select Register A0" bitfld.word 0x0 8. "ANSA08,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x0 7. "ANSA07,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x0 6. "ANSA06,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x0 5. "ANSA05,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x0 4. "ANSA04,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x0 3. "ANSA03,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x0 2. "ANSA02,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x0 1. "ANSA01,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x0 0. "ANSA00,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." line.word 0x2 "ADANSA1,A/D Channel Select Register A1" bitfld.word 0x2 6. "ANSA22,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x2 5. "ANSA21,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x2 4. "ANSA20,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x2 3. "ANSA19,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x2 2. "ANSA18,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x2 1. "ANSA17,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x2 0. "ANSA16,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." line.word 0x4 "ADADS0,A/D-Converted Value Addition/Average Channel Select Register 0" bitfld.word 0x4 8. "ADS08,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x4 7. "ADS07,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x4 6. "ADS06,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x4 5. "ADS05,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x4 4. "ADS04,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x4 3. "ADS03,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x4 2. "ADS02,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x4 1. "ADS01,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x4 0. "ADS00,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." line.word 0x6 "ADADS1,A/D-Converted Value Addition/Average Channel Select Register 1" bitfld.word 0x6 6. "ADS22,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 5. "ADS21,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 4. "ADS20,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 3. "ADS19,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 2. "ADS18,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 1. "ADS17,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 0. "ADS16,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." group.byte 0xC++0x0 line.byte 0x0 "ADADC,A/D-Converted Value Addition/Average Count Select Register" bitfld.byte 0x0 7. "AVEE,Average Mode Select" "0: Enable addition mode,1: Enable average mode" bitfld.byte 0x0 0.--2. "ADC,Addition/Average Count Select" "0: Setting prohibited,1: 2-time conversion (1 addition),?,?,?,?,?,?" group.word 0xE++0x9 line.word 0x0 "ADCER,A/D Control Extended Register" bitfld.word 0x0 15. "ADRFMT,A/D Data Register Format Select" "0: Select right-justified for the A/D data register..,1: Select left-justified for the A/D data register.." bitfld.word 0x0 11. "DIAGM,Self-Diagnosis Enable" "0: Disable ADC12 self-diagnosis,1: Enable ADC12 self-diagnosis" newline bitfld.word 0x0 10. "DIAGLD,Self-Diagnosis Mode Select" "0: Select rotation mode for self-diagnosis voltage,1: Select mixed mode for self-diagnosis voltage" bitfld.word 0x0 8.--9. "DIAGVAL,Self-Diagnosis Conversion Voltage Select" "0: Setting prohibited when self-diagnosis is enabled,1: 0 volts,?,?" newline bitfld.word 0x0 5. "ACE,A/D Data Register Automatic Clearing Enable" "0: Disable automatic clearing,1: Enable automatic clearing" bitfld.word 0x0 1.--2. "ADPRC" "0: 12-bit accuracy,1: 10-bit accuracy,?,?" line.word 0x2 "ADSTRGR,A/D Conversion Start Trigger Select Register" hexmask.word.byte 0x2 8.--13. 1. "TRSA,A/D Conversion Start Trigger Select" hexmask.word.byte 0x2 0.--5. 1. "TRSB,A/D Conversion Start Trigger Select for Group B" line.word 0x4 "ADEXICR,A/D Conversion Extended Input Control Registers" bitfld.word 0x4 11. "OCSB,Internal Reference Voltage A/D Conversion Select for Group B" "0: Disable A/D conversion of internal reference..,1: Enable A/D conversion of internal reference.." bitfld.word 0x4 10. "TSSB,Temperature Sensor Output A/D Conversion Select for Group B" "0: Disable A/D conversion of temperature sensor..,1: Enable A/D conversion of temperature sensor output" newline bitfld.word 0x4 9. "OCSA,Internal Reference Voltage A/D Conversion Select" "0: Disable A/D conversion of internal reference..,1: Enable A/D conversion of internal reference.." bitfld.word 0x4 8. "TSSA,Temperature Sensor Output A/D Conversion Select" "0: Disable A/D conversion of temperature sensor..,1: Enable A/D conversion of temperature sensor output" newline bitfld.word 0x4 1. "OCSAD,Internal Reference Voltage A/D-Converted Value Addition/Average Mode Select" "0: Do not select addition/average mode for internal..,1: Select addition/average mode for internal.." bitfld.word 0x4 0. "TSSAD,Temperature Sensor Output A/D-Converted Value Addition/Average Mode Select" "0: Do not select addition/average mode for..,1: Select addition/average mode for temperature.." line.word 0x6 "ADANSB0,A/D Channel Select Register B0" bitfld.word 0x6 8. "ANSB08,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 7. "ANSB07,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 6. "ANSB06,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 5. "ANSB05,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 4. "ANSB04,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 3. "ANSB03,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 2. "ANSB02,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 1. "ANSB01,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 0. "ANSB00,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." line.word 0x8 "ADANSB1,A/D Channel Select Register B1" bitfld.word 0x8 6. "ANSB22,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x8 5. "ANSB21,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x8 4. "ANSB20,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x8 3. "ANSB19,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x8 2. "ANSB18,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x8 1. "ANSB17,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x8 0. "ANSB16,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." rgroup.word 0x18++0x7 line.word 0x0 "ADDBLDR,A/D Data Duplexing Register" hexmask.word 0x0 0.--15. 1. "ADDBLDR,Converted Value 15 to 0" line.word 0x2 "ADTSDR,A/D Temperature Sensor Data Register" hexmask.word 0x2 0.--15. 1. "ADTSDR,Converted Value 15 to 0" line.word 0x4 "ADOCDR,A/D Internal Reference Voltage Data Register" hexmask.word 0x4 0.--15. 1. "ADOCDR,Converted Value 15 to 0" line.word 0x6 "ADRD,A/D Self-Diagnosis Data Register" bitfld.word 0x6 14.--15. "DIAGST,Self-Diagnosis Status" "0: Self-diagnosis not executed after power-on.,1: Self-diagnosis was executed using the 0 V voltage.,?,?" hexmask.word 0x6 0.--11. 1. "AD,Converted Value 11 to 0" repeat 9. (increment 0x0 0x1)(increment 0x0 0x2) rgroup.word ($2+0x20)++0x1 line.word 0x0 "ADDR$1,A/D Data Registers %s" hexmask.word 0x0 0.--15. 1. "ADDR,Converted Value 15 to 0" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x2) rgroup.word ($2+0x20)++0x1 line.word 0x0 "ADDR$1,A/D Data Registers %s" hexmask.word 0x0 0.--15. 1. "ADDR,Converted Value 15 to 0" repeat.end rgroup.word 0x26++0x1 line.word 0x0 "ADVMDR,A/D VBATT Monitor Data Register" hexmask.word 0x0 0.--15. 1. "ADDR,Converted Value 15 to 0" group.word 0x66++0x1 line.word 0x0 "ADSHCR,A/D Sample and Hold Circuit Control Register" bitfld.word 0x0 8.--9. "SHANS,Channel-Dedicated Sample-and-Hold Circuit Bypass Select" "0: Bypass the circuits,1: Use the circuits,?,?" hexmask.word.byte 0x0 0.--7. 1. "SSTSH,Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting" group.byte 0x7A++0x0 line.byte 0x0 "ADDISCR,A/D Disconnection Detection Control Register" bitfld.byte 0x0 4. "PCHG,Precharge/discharge select" "0: Discharge,1: Precharge" hexmask.byte 0x0 0.--3. 1. "ADNDIS,Disconnection Detection Assist Setting" group.byte 0x7C++0x0 line.byte 0x0 "ADSHMSR,A/D Sample and Hold Operation Mode Selection Register" bitfld.byte 0x0 0. "SHMD,Sampling Operation Selection" "0: Sampling Operation Selection,1: Enable continuous sampling function" group.word 0x80++0x1 line.word 0x0 "ADGSPCR,A/D Group Scan Priority Control Register" bitfld.word 0x0 15. "GBRP,Single Scan Continuous Start" "0: Single scan is not continuously activated.,1: Single scan for the group with the.." bitfld.word 0x0 14. "LGRRS,Enabled only when PGS = 1 and GBRSCN = 1." "0: Start rescanning from the first channel for..,1: Start rescanning from the channel for which A/D.." newline bitfld.word 0x0 1. "GBRSCN,Lower-Priority Group Restart Setting" "0: Disable rescanning of the group that was stopped..,1: Enable rescanning of the group that was stopped.." bitfld.word 0x0 0. "PGS,Group Priority Operation Setting" "0: Operate without group priority control.,1: Operate with group priority control." rgroup.word 0x84++0x3 line.word 0x0 "ADDBLDRA,A/D Data Duplexing Register A" hexmask.word 0x0 0.--15. 1. "ADDBLDR,Converted Value 15 to 0" line.word 0x2 "ADDBLDRB,A/D Data Duplexing Register B" hexmask.word 0x2 0.--15. 1. "ADDBLDR,Converted Value 15 to 0" rgroup.byte 0x8C++0x0 line.byte 0x0 "ADWINMON,A/D Compare Function Window A/B Status Monitor Register" bitfld.byte 0x0 5. "MONCMPB,Comparison Result Monitor B" "0: Window B comparison conditions are not met.,1: Window B comparison conditions are met." bitfld.byte 0x0 4. "MONCMPA,Comparison Result Monitor A" "0: Window A comparison conditions are not met.,1: Window A comparison conditions are met." newline bitfld.byte 0x0 0. "MONCOMB,Combination Result Monitor" "0: Window A/B composite conditions are not met.,1: Window A/B composite conditions are met." group.word 0x90++0x1 line.word 0x0 "ADCMPCR,A/D Compare Function Control Register" bitfld.word 0x0 15. "CMPAIE,Compare A Interrupt Enable" "0: Disable ADC12i_CMPAI (i = 0 1) interrupt when..,1: Enable ADC12i_CMPAI (i = 0 1) interrupt when.." bitfld.word 0x0 14. "WCMPE,Window Function Setting" "0: Disable window function Window A and window B..,1: Enable window function Window A and window B.." newline bitfld.word 0x0 13. "CMPBIE,Compare B Interrupt Enable" "0: Disable ADC12i_CMPBI (i = 0 1) interrupt when..,1: Enable ADC12i_CMPBI (i = 0 1) interrupt when.." bitfld.word 0x0 11. "CMPAE,Compare Window A Operation Enable" "0: Disable compare window A operation. Disable..,1: Enable compare window A operation." newline bitfld.word 0x0 9. "CMPBE,Compare Window B Operation Enable" "0: Disable compare window B operation. Disable..,1: Enable compare window B operation." bitfld.word 0x0 0.--1. "CMPAB,Window A/B Composite Conditions Setting" "0: Output ADC12i_WCMPM (i = 0 1) when window A OR..,1: Output ADC12i_WCMPM (i = 0 1) when window A EXOR..,?,?" group.byte 0x92++0x1 line.byte 0x0 "ADCMPANSER,A/D Compare Function Window A Extended Input Select Register" bitfld.byte 0x0 1. "CMPOCA,Internal Reference Voltage Compare Select" "0: Exclude the internal reference voltage from the..,1: Include the internal reference voltage in the.." bitfld.byte 0x0 0. "CMPTSA,Temperature Sensor Output Compare Select" "0: Exclude the temperature sensor output from the..,1: Include the temperature sensor output in the.." line.byte 0x1 "ADCMPLER,A/D Compare Function Window A Extended Input Comparison Condition Setting Register" bitfld.byte 0x1 1. "CMPLOCA,Compare Window A Internal Reference Voltage Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.byte 0x1 0. "CMPLTSA,Compare Window A Temperature Sensor Output Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." group.word 0x94++0x1 line.word 0x0 "ADCMPANSR0,A/D Compare Function Window A Channel Select Register 0" bitfld.word 0x0 15. "CMPCHA15,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 14. "CMPCHA14,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 13. "CMPCHA13,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 12. "CMPCHA12,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 11. "CMPCHA11,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 10. "CMPCHA10,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 9. "CMPCHA09,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 8. "CMPCHA08,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 7. "CMPCHA07,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 6. "CMPCHA06,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 5. "CMPCHA05,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 4. "CMPCHA04,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 3. "CMPCHA03,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 2. "CMPCHA02,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 1. "CMPCHA01,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 0. "CMPCHA00,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." group.word 0x98++0x1 line.word 0x0 "ADCMPLR0,A/D Compare Function Window A Comparison Condition Setting Register 0" bitfld.word 0x0 15. "CMPLCHA15,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 14. "CMPLCHA14,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 13. "CMPLCHA13,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 12. "CMPLCHA12,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 11. "CMPLCHA11,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 10. "CMPLCHA10,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 9. "CMPLCHA09,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 8. "CMPLCHA08,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 7. "CMPLCHA07,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 6. "CMPLCHA06,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 5. "CMPLCHA05,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 4. "CMPLCHA04,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 3. "CMPLCHA03,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 2. "CMPLCHA02,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 1. "CMPLCHA01,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 0. "CMPLCHA00,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." repeat 2. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0x9C)++0x1 line.word 0x0 "ADCMPDR$1,A/D Compare Function Window A Lower-Side/Upper-Side Level Setting Register" repeat.end group.word 0xA0++0x1 line.word 0x0 "ADCMPSR0,A/D Compare Function Window A Channel Status Register 0" bitfld.word 0x0 15. "CMPSTCHA15,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 14. "CMPSTCHA14,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 13. "CMPSTCHA13,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 12. "CMPSTCHA12,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 11. "CMPSTCHA11,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 10. "CMPSTCHA10,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 9. "CMPSTCHA09,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 8. "CMPSTCHA08,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 7. "CMPSTCHA07,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 6. "CMPSTCHA06,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 5. "CMPSTCHA05,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 4. "CMPSTCHA04,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 3. "CMPSTCHA03,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 2. "CMPSTCHA02,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 1. "CMPSTCHA01,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 0. "CMPSTCHA00,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." group.byte 0xA4++0x0 line.byte 0x0 "ADCMPSER,A/D Compare Function Window A Extended Input Channel Status Register" bitfld.byte 0x0 1. "CMPSTOCA,Compare Window A Internal Reference Voltage Compare Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.byte 0x0 0. "CMPSTTSA,Compare Window A Temperature Sensor Output Compare Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." group.byte 0xA6++0x0 line.byte 0x0 "ADCMPBNSR,A/D Compare Function Window B Channel Select Register" bitfld.byte 0x0 7. "CMPLB,Compare Window B Comparison Condition Setting" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." hexmask.byte 0x0 0.--5. 1. "CMPCHB,Compare Window B Channel Select" group.word 0xA8++0x3 line.word 0x0 "ADWINLLB,A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register" line.word 0x2 "ADWINULB,A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register" group.byte 0xAC++0x0 line.byte 0x0 "ADCMPBSR,A/D Compare Function Window B Status Register" bitfld.byte 0x0 0. "CMPSTB,Compare Window B Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." repeat 16. (increment 0x0 0x1)(increment 0x0 0x2) rgroup.word ($2+0xB0)++0x1 line.word 0x0 "ADBUF$1,A/D Data Buffer Registers %s" hexmask.word 0x0 0.--15. 1. "ADBUF,Converted Value 15 to 0" repeat.end group.byte 0xD0++0x0 line.byte 0x0 "ADBUFEN,A/D Data Buffer Enable Register" bitfld.byte 0x0 0. "BUFEN,Data Buffer Enable" "0: The data buffer is not used.,1: The data buffer is used." group.byte 0xD2++0x0 line.byte 0x0 "ADBUFPTR,A/D Data Buffer Pointer Register" bitfld.byte 0x0 4. "PTROVF,Pointer Overflow Flag" "0: The data buffer pointer has not overflowed.,1: The data buffer pointer has overflowed." hexmask.byte 0x0 0.--3. 1. "BUFPTR,Data Buffer Pointer" group.byte 0xDD++0x2 line.byte 0x0 "ADSSTRL,A/D Sampling State Register" hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting" line.byte 0x1 "ADSSTRT,A/D Sampling State Register" hexmask.byte 0x1 0.--7. 1. "SST,Sampling Time Setting" line.byte 0x2 "ADSSTRO,A/D Sampling State Register" hexmask.byte 0x2 0.--7. 1. "SST,Sampling Time Setting" repeat 9. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0xE0)++0x0 line.byte 0x0 "ADSSTR$1,A/D Sampling State Register" hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting" repeat.end group.byte 0xE3++0x0 line.byte 0x0 "ADSSTRV,A/D Sampling State Register" hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting" repeat 4. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0xEC)++0x0 line.byte 0x0 "ADSSTR$1,A/D Sampling State Register" hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting" repeat.end tree.end tree "ADC121" base ad:0x40332200 group.word 0x0++0x1 line.word 0x0 "ADCSR,A/D Control Register" bitfld.word 0x0 15. "ADST,A/D Conversion Start" "0: Stop A/D conversion process.,1: Start A/D conversion process." bitfld.word 0x0 13.--14. "ADCS,Scan Mode Select" "0: Single scan mode,1: Group scan mode,?,?" newline bitfld.word 0x0 9. "TRGE,Trigger Start Enable" "0: Disable A/D conversion to be started by the..,1: Enable A/D conversion to be started by the.." bitfld.word 0x0 8. "EXTRG,Trigger Select" "0: Start A/D conversion by the synchronous trigger..,1: Start A/D conversion by the asynchronous trigger.." newline bitfld.word 0x0 7. "DBLE,Double Trigger Mode Select" "0: Deselect double-trigger mode.,1: Select double-trigger mode." bitfld.word 0x0 6. "GBADIE,Group B Scan End Interrupt and ELC Event Enable" "0: Disable ADC12i_GBADI (i = 0 1) interrupt..,1: Enable ADC12i_GBADI (i = 0 1) interrupt.." newline hexmask.word.byte 0x0 0.--4. 1. "DBLANS,Double Trigger Channel Select" group.word 0x4++0x7 line.word 0x0 "ADANSA0,A/D Channel Select Register A0" bitfld.word 0x0 6. "ANSA06,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x0 5. "ANSA05,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x0 4. "ANSA04,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x0 3. "ANSA03,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x0 2. "ANSA02,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x0 1. "ANSA01,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x0 0. "ANSA00,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." line.word 0x2 "ADANSA1,A/D Channel Select Register A1" bitfld.word 0x2 3. "ANSA19,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x2 2. "ANSA18,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x2 1. "ANSA17,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x2 0. "ANSA16,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." line.word 0x4 "ADADS0,A/D-Converted Value Addition/Average Channel Select Register 0" bitfld.word 0x4 6. "ADS06,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x4 5. "ADS05,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x4 4. "ADS04,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x4 3. "ADS03,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x4 2. "ADS02,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x4 1. "ADS01,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x4 0. "ADS00,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." line.word 0x6 "ADADS1,A/D-Converted Value Addition/Average Channel Select Register 1" bitfld.word 0x6 3. "ADS19,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 2. "ADS18,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 1. "ADS17,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 0. "ADS16,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." group.byte 0xC++0x0 line.byte 0x0 "ADADC,A/D-Converted Value Addition/Average Count Select Register" bitfld.byte 0x0 7. "AVEE,Average Mode Select" "0: Enable addition mode,1: Enable average mode" bitfld.byte 0x0 0.--2. "ADC,Addition/Average Count Select" "0: Setting prohibited,1: 2-time conversion (1 addition),?,?,?,?,?,?" group.word 0xE++0x9 line.word 0x0 "ADCER,A/D Control Extended Register" bitfld.word 0x0 15. "ADRFMT,A/D Data Register Format Select" "0: Select right-justified for the A/D data register..,1: Select left-justified for the A/D data register.." bitfld.word 0x0 11. "DIAGM,Self-Diagnosis Enable" "0: Disable ADC12 self-diagnosis,1: Enable ADC12 self-diagnosis" newline bitfld.word 0x0 10. "DIAGLD,Self-Diagnosis Mode Select" "0: Select rotation mode for self-diagnosis voltage,1: Select mixed mode for self-diagnosis voltage" bitfld.word 0x0 8.--9. "DIAGVAL,Self-Diagnosis Conversion Voltage Select" "0: Setting prohibited when self-diagnosis is enabled,1: 0 volts,?,?" newline bitfld.word 0x0 5. "ACE,A/D Data Register Automatic Clearing Enable" "0: Disable automatic clearing,1: Enable automatic clearing" bitfld.word 0x0 1.--2. "ADPRC" "0: 12-bit accuracy,1: 10-bit accuracy,?,?" line.word 0x2 "ADSTRGR,A/D Conversion Start Trigger Select Register" hexmask.word.byte 0x2 8.--13. 1. "TRSA,A/D Conversion Start Trigger Select" hexmask.word.byte 0x2 0.--5. 1. "TRSB,A/D Conversion Start Trigger Select for Group B" line.word 0x4 "ADEXICR,A/D Conversion Extended Input Control Registers" bitfld.word 0x4 11. "OCSB,Internal Reference Voltage A/D Conversion Select for Group B" "0: Disable A/D conversion of internal reference..,1: Enable A/D conversion of internal reference.." bitfld.word 0x4 10. "TSSB,Temperature Sensor Output A/D Conversion Select for Group B" "0: Disable A/D conversion of temperature sensor..,1: Enable A/D conversion of temperature sensor output" newline bitfld.word 0x4 9. "OCSA,Internal Reference Voltage A/D Conversion Select" "0: Disable A/D conversion of internal reference..,1: Enable A/D conversion of internal reference.." bitfld.word 0x4 8. "TSSA,Temperature Sensor Output A/D Conversion Select" "0: Disable A/D conversion of temperature sensor..,1: Enable A/D conversion of temperature sensor output" newline bitfld.word 0x4 1. "OCSAD,Internal Reference Voltage A/D-Converted Value Addition/Average Mode Select" "0: Do not select addition/average mode for internal..,1: Select addition/average mode for internal.." bitfld.word 0x4 0. "TSSAD,Temperature Sensor Output A/D-Converted Value Addition/Average Mode Select" "0: Do not select addition/average mode for..,1: Select addition/average mode for temperature.." line.word 0x6 "ADANSB0,A/D Channel Select Register B0" bitfld.word 0x6 6. "ANSB06,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 5. "ANSB05,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 4. "ANSB04,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 3. "ANSB03,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 2. "ANSB02,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 1. "ANSB01,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 0. "ANSB00,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." line.word 0x8 "ADANSB1,A/D Channel Select Register B1" bitfld.word 0x8 3. "ANSB19,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x8 2. "ANSB18,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x8 1. "ANSB17,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x8 0. "ANSB16,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." rgroup.word 0x18++0x7 line.word 0x0 "ADDBLDR,A/D Data Duplexing Register" hexmask.word 0x0 0.--15. 1. "ADDBLDR,Converted Value 15 to 0" line.word 0x2 "ADTSDR,A/D Temperature Sensor Data Register" hexmask.word 0x2 0.--15. 1. "ADTSDR,Converted Value 15 to 0" line.word 0x4 "ADOCDR,A/D Internal Reference Voltage Data Register" hexmask.word 0x4 0.--15. 1. "ADOCDR,Converted Value 15 to 0" line.word 0x6 "ADRD,A/D Self-Diagnosis Data Register" bitfld.word 0x6 14.--15. "DIAGST,Self-Diagnosis Status" "0: Self-diagnosis not executed after power-on.,1: Self-diagnosis was executed using the 0 V voltage.,?,?" hexmask.word 0x6 0.--11. 1. "AD,Converted Value 11 to 0" repeat 7. (increment 0x0 0x1)(increment 0x0 0x2) rgroup.word ($2+0x20)++0x1 line.word 0x0 "ADDR$1,A/D Data Registers %s" hexmask.word 0x0 0.--15. 1. "ADDR,Converted Value 15 to 0" repeat.end repeat 7. (increment 0x0 0x1)(increment 0x0 0x2) rgroup.word ($2+0x20)++0x1 line.word 0x0 "ADDR$1,A/D Data Registers %s" hexmask.word 0x0 0.--15. 1. "ADDR,Converted Value 15 to 0" repeat.end rgroup.word 0x26++0x1 line.word 0x0 "ADVMDR,A/D VBATT Monitor Data Register" hexmask.word 0x0 0.--15. 1. "ADDR,Converted Value 15 to 0" group.word 0x66++0x1 line.word 0x0 "ADSHCR,A/D Sample and Hold Circuit Control Register" bitfld.word 0x0 8.--9. "SHANS,Channel-Dedicated Sample-and-Hold Circuit Bypass Select" "0: Bypass the circuits,1: Use the circuits,?,?" hexmask.word.byte 0x0 0.--7. 1. "SSTSH,Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting" group.byte 0x7A++0x0 line.byte 0x0 "ADDISCR,A/D Disconnection Detection Control Register" bitfld.byte 0x0 4. "PCHG,Precharge/discharge select" "0: Discharge,1: Precharge" hexmask.byte 0x0 0.--3. 1. "ADNDIS,Disconnection Detection Assist Setting" group.byte 0x7C++0x0 line.byte 0x0 "ADSHMSR,A/D Sample and Hold Operation Mode Selection Register" bitfld.byte 0x0 0. "SHMD,Sampling Operation Selection" "0: Sampling Operation Selection,1: Enable continuous sampling function" group.word 0x80++0x1 line.word 0x0 "ADGSPCR,A/D Group Scan Priority Control Register" bitfld.word 0x0 15. "GBRP,Single Scan Continuous Start" "0: Single scan is not continuously activated.,1: Single scan for the group with the.." bitfld.word 0x0 14. "LGRRS,Enabled only when PGS = 1 and GBRSCN = 1." "0: Start rescanning from the first channel for..,1: Start rescanning from the channel for which A/D.." newline bitfld.word 0x0 1. "GBRSCN,Lower-Priority Group Restart Setting" "0: Disable rescanning of the group that was stopped..,1: Enable rescanning of the group that was stopped.." bitfld.word 0x0 0. "PGS,Group Priority Operation Setting" "0: Operate without group priority control.,1: Operate with group priority control." rgroup.word 0x84++0x3 line.word 0x0 "ADDBLDRA,A/D Data Duplexing Register A" hexmask.word 0x0 0.--15. 1. "ADDBLDR,Converted Value 15 to 0" line.word 0x2 "ADDBLDRB,A/D Data Duplexing Register B" hexmask.word 0x2 0.--15. 1. "ADDBLDR,Converted Value 15 to 0" rgroup.byte 0x8C++0x0 line.byte 0x0 "ADWINMON,A/D Compare Function Window A/B Status Monitor Register" bitfld.byte 0x0 5. "MONCMPB,Comparison Result Monitor B" "0: Window B comparison conditions are not met.,1: Window B comparison conditions are met." bitfld.byte 0x0 4. "MONCMPA,Comparison Result Monitor A" "0: Window A comparison conditions are not met.,1: Window A comparison conditions are met." newline bitfld.byte 0x0 0. "MONCOMB,Combination Result Monitor" "0: Window A/B composite conditions are not met.,1: Window A/B composite conditions are met." group.word 0x90++0x1 line.word 0x0 "ADCMPCR,A/D Compare Function Control Register" bitfld.word 0x0 15. "CMPAIE,Compare A Interrupt Enable" "0: Disable ADC12i_CMPAI (i = 0 1) interrupt when..,1: Enable ADC12i_CMPAI (i = 0 1) interrupt when.." bitfld.word 0x0 14. "WCMPE,Window Function Setting" "0: Disable window function Window A and window B..,1: Enable window function Window A and window B.." newline bitfld.word 0x0 13. "CMPBIE,Compare B Interrupt Enable" "0: Disable ADC12i_CMPBI (i = 0 1) interrupt when..,1: Enable ADC12i_CMPBI (i = 0 1) interrupt when.." bitfld.word 0x0 11. "CMPAE,Compare Window A Operation Enable" "0: Disable compare window A operation. Disable..,1: Enable compare window A operation." newline bitfld.word 0x0 9. "CMPBE,Compare Window B Operation Enable" "0: Disable compare window B operation. Disable..,1: Enable compare window B operation." bitfld.word 0x0 0.--1. "CMPAB,Window A/B Composite Conditions Setting" "0: Output ADC12i_WCMPM (i = 0 1) when window A OR..,1: Output ADC12i_WCMPM (i = 0 1) when window A EXOR..,?,?" group.byte 0x92++0x1 line.byte 0x0 "ADCMPANSER,A/D Compare Function Window A Extended Input Select Register" bitfld.byte 0x0 1. "CMPOCA,Internal Reference Voltage Compare Select" "0: Exclude the internal reference voltage from the..,1: Include the internal reference voltage in the.." bitfld.byte 0x0 0. "CMPTSA,Temperature Sensor Output Compare Select" "0: Exclude the temperature sensor output from the..,1: Include the temperature sensor output in the.." line.byte 0x1 "ADCMPLER,A/D Compare Function Window A Extended Input Comparison Condition Setting Register" bitfld.byte 0x1 1. "CMPLOCA,Compare Window A Internal Reference Voltage Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.byte 0x1 0. "CMPLTSA,Compare Window A Temperature Sensor Output Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." group.word 0x94++0x1 line.word 0x0 "ADCMPANSR0,A/D Compare Function Window A Channel Select Register 0" bitfld.word 0x0 15. "CMPCHA15,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 14. "CMPCHA14,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 13. "CMPCHA13,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 12. "CMPCHA12,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 11. "CMPCHA11,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 10. "CMPCHA10,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 9. "CMPCHA09,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 8. "CMPCHA08,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 7. "CMPCHA07,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 6. "CMPCHA06,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 5. "CMPCHA05,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 4. "CMPCHA04,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 3. "CMPCHA03,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 2. "CMPCHA02,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 1. "CMPCHA01,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 0. "CMPCHA00,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." group.word 0x98++0x1 line.word 0x0 "ADCMPLR0,A/D Compare Function Window A Comparison Condition Setting Register 0" bitfld.word 0x0 15. "CMPLCHA15,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 14. "CMPLCHA14,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 13. "CMPLCHA13,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 12. "CMPLCHA12,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 11. "CMPLCHA11,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 10. "CMPLCHA10,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 9. "CMPLCHA09,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 8. "CMPLCHA08,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 7. "CMPLCHA07,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 6. "CMPLCHA06,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 5. "CMPLCHA05,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 4. "CMPLCHA04,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 3. "CMPLCHA03,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 2. "CMPLCHA02,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 1. "CMPLCHA01,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 0. "CMPLCHA00,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." repeat 2. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0x9C)++0x1 line.word 0x0 "ADCMPDR$1,A/D Compare Function Window A Lower-Side/Upper-Side Level Setting Register" repeat.end group.word 0xA0++0x1 line.word 0x0 "ADCMPSR0,A/D Compare Function Window A Channel Status Register 0" bitfld.word 0x0 15. "CMPSTCHA15,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 14. "CMPSTCHA14,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 13. "CMPSTCHA13,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 12. "CMPSTCHA12,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 11. "CMPSTCHA11,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 10. "CMPSTCHA10,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 9. "CMPSTCHA09,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 8. "CMPSTCHA08,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 7. "CMPSTCHA07,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 6. "CMPSTCHA06,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 5. "CMPSTCHA05,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 4. "CMPSTCHA04,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 3. "CMPSTCHA03,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 2. "CMPSTCHA02,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 1. "CMPSTCHA01,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 0. "CMPSTCHA00,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." group.byte 0xA4++0x0 line.byte 0x0 "ADCMPSER,A/D Compare Function Window A Extended Input Channel Status Register" bitfld.byte 0x0 1. "CMPSTOCA,Compare Window A Internal Reference Voltage Compare Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.byte 0x0 0. "CMPSTTSA,Compare Window A Temperature Sensor Output Compare Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." group.byte 0xA6++0x0 line.byte 0x0 "ADCMPBNSR,A/D Compare Function Window B Channel Select Register" bitfld.byte 0x0 7. "CMPLB,Compare Window B Comparison Condition Setting" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." hexmask.byte 0x0 0.--5. 1. "CMPCHB,Compare Window B Channel Select" group.word 0xA8++0x3 line.word 0x0 "ADWINLLB,A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register" line.word 0x2 "ADWINULB,A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register" group.byte 0xAC++0x0 line.byte 0x0 "ADCMPBSR,A/D Compare Function Window B Status Register" bitfld.byte 0x0 0. "CMPSTB,Compare Window B Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." repeat 16. (increment 0x0 0x1)(increment 0x0 0x2) rgroup.word ($2+0xB0)++0x1 line.word 0x0 "ADBUF$1,A/D Data Buffer Registers %s" hexmask.word 0x0 0.--15. 1. "ADBUF,Converted Value 15 to 0" repeat.end group.byte 0xD0++0x0 line.byte 0x0 "ADBUFEN,A/D Data Buffer Enable Register" bitfld.byte 0x0 0. "BUFEN,Data Buffer Enable" "0: The data buffer is not used.,1: The data buffer is used." group.byte 0xD2++0x0 line.byte 0x0 "ADBUFPTR,A/D Data Buffer Pointer Register" bitfld.byte 0x0 4. "PTROVF,Pointer Overflow Flag" "0: The data buffer pointer has not overflowed.,1: The data buffer pointer has overflowed." hexmask.byte 0x0 0.--3. 1. "BUFPTR,Data Buffer Pointer" group.byte 0xDD++0x2 line.byte 0x0 "ADSSTRL,A/D Sampling State Register" hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting" line.byte 0x1 "ADSSTRT,A/D Sampling State Register" hexmask.byte 0x1 0.--7. 1. "SST,Sampling Time Setting" line.byte 0x2 "ADSSTRO,A/D Sampling State Register" hexmask.byte 0x2 0.--7. 1. "SST,Sampling Time Setting" repeat 7. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0xE0)++0x0 line.byte 0x0 "ADSSTR$1,A/D Sampling State Register" hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting" repeat.end group.byte 0xE3++0x0 line.byte 0x0 "ADSSTRV,A/D Sampling State Register" hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting" tree.end tree "ADC121_NS" base ad:0x50332200 group.word 0x0++0x1 line.word 0x0 "ADCSR,A/D Control Register" bitfld.word 0x0 15. "ADST,A/D Conversion Start" "0: Stop A/D conversion process.,1: Start A/D conversion process." bitfld.word 0x0 13.--14. "ADCS,Scan Mode Select" "0: Single scan mode,1: Group scan mode,?,?" newline bitfld.word 0x0 9. "TRGE,Trigger Start Enable" "0: Disable A/D conversion to be started by the..,1: Enable A/D conversion to be started by the.." bitfld.word 0x0 8. "EXTRG,Trigger Select" "0: Start A/D conversion by the synchronous trigger..,1: Start A/D conversion by the asynchronous trigger.." newline bitfld.word 0x0 7. "DBLE,Double Trigger Mode Select" "0: Deselect double-trigger mode.,1: Select double-trigger mode." bitfld.word 0x0 6. "GBADIE,Group B Scan End Interrupt and ELC Event Enable" "0: Disable ADC12i_GBADI (i = 0 1) interrupt..,1: Enable ADC12i_GBADI (i = 0 1) interrupt.." newline hexmask.word.byte 0x0 0.--4. 1. "DBLANS,Double Trigger Channel Select" group.word 0x4++0x7 line.word 0x0 "ADANSA0,A/D Channel Select Register A0" bitfld.word 0x0 6. "ANSA06,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x0 5. "ANSA05,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x0 4. "ANSA04,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x0 3. "ANSA03,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x0 2. "ANSA02,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x0 1. "ANSA01,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x0 0. "ANSA00,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." line.word 0x2 "ADANSA1,A/D Channel Select Register A1" bitfld.word 0x2 3. "ANSA19,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x2 2. "ANSA18,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x2 1. "ANSA17,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x2 0. "ANSA16,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." line.word 0x4 "ADADS0,A/D-Converted Value Addition/Average Channel Select Register 0" bitfld.word 0x4 6. "ADS06,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x4 5. "ADS05,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x4 4. "ADS04,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x4 3. "ADS03,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x4 2. "ADS02,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x4 1. "ADS01,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x4 0. "ADS00,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." line.word 0x6 "ADADS1,A/D-Converted Value Addition/Average Channel Select Register 1" bitfld.word 0x6 3. "ADS19,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 2. "ADS18,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 1. "ADS17,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 0. "ADS16,A/D Conversion Channels Select/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel." group.byte 0xC++0x0 line.byte 0x0 "ADADC,A/D-Converted Value Addition/Average Count Select Register" bitfld.byte 0x0 7. "AVEE,Average Mode Select" "0: Enable addition mode,1: Enable average mode" bitfld.byte 0x0 0.--2. "ADC,Addition/Average Count Select" "0: Setting prohibited,1: 2-time conversion (1 addition),?,?,?,?,?,?" group.word 0xE++0x9 line.word 0x0 "ADCER,A/D Control Extended Register" bitfld.word 0x0 15. "ADRFMT,A/D Data Register Format Select" "0: Select right-justified for the A/D data register..,1: Select left-justified for the A/D data register.." bitfld.word 0x0 11. "DIAGM,Self-Diagnosis Enable" "0: Disable ADC12 self-diagnosis,1: Enable ADC12 self-diagnosis" newline bitfld.word 0x0 10. "DIAGLD,Self-Diagnosis Mode Select" "0: Select rotation mode for self-diagnosis voltage,1: Select mixed mode for self-diagnosis voltage" bitfld.word 0x0 8.--9. "DIAGVAL,Self-Diagnosis Conversion Voltage Select" "0: Setting prohibited when self-diagnosis is enabled,1: 0 volts,?,?" newline bitfld.word 0x0 5. "ACE,A/D Data Register Automatic Clearing Enable" "0: Disable automatic clearing,1: Enable automatic clearing" bitfld.word 0x0 1.--2. "ADPRC" "0: 12-bit accuracy,1: 10-bit accuracy,?,?" line.word 0x2 "ADSTRGR,A/D Conversion Start Trigger Select Register" hexmask.word.byte 0x2 8.--13. 1. "TRSA,A/D Conversion Start Trigger Select" hexmask.word.byte 0x2 0.--5. 1. "TRSB,A/D Conversion Start Trigger Select for Group B" line.word 0x4 "ADEXICR,A/D Conversion Extended Input Control Registers" bitfld.word 0x4 11. "OCSB,Internal Reference Voltage A/D Conversion Select for Group B" "0: Disable A/D conversion of internal reference..,1: Enable A/D conversion of internal reference.." bitfld.word 0x4 10. "TSSB,Temperature Sensor Output A/D Conversion Select for Group B" "0: Disable A/D conversion of temperature sensor..,1: Enable A/D conversion of temperature sensor output" newline bitfld.word 0x4 9. "OCSA,Internal Reference Voltage A/D Conversion Select" "0: Disable A/D conversion of internal reference..,1: Enable A/D conversion of internal reference.." bitfld.word 0x4 8. "TSSA,Temperature Sensor Output A/D Conversion Select" "0: Disable A/D conversion of temperature sensor..,1: Enable A/D conversion of temperature sensor output" newline bitfld.word 0x4 1. "OCSAD,Internal Reference Voltage A/D-Converted Value Addition/Average Mode Select" "0: Do not select addition/average mode for internal..,1: Select addition/average mode for internal.." bitfld.word 0x4 0. "TSSAD,Temperature Sensor Output A/D-Converted Value Addition/Average Mode Select" "0: Do not select addition/average mode for..,1: Select addition/average mode for temperature.." line.word 0x6 "ADANSB0,A/D Channel Select Register B0" bitfld.word 0x6 6. "ANSB06,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 5. "ANSB05,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 4. "ANSB04,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 3. "ANSB03,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 2. "ANSB02,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x6 1. "ANSB01,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x6 0. "ANSB00,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." line.word 0x8 "ADANSB1,A/D Channel Select Register B1" bitfld.word 0x8 3. "ANSB19,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x8 2. "ANSB18,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." newline bitfld.word 0x8 1. "ANSB17,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." bitfld.word 0x8 0. "ANSB16,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel." rgroup.word 0x18++0x7 line.word 0x0 "ADDBLDR,A/D Data Duplexing Register" hexmask.word 0x0 0.--15. 1. "ADDBLDR,Converted Value 15 to 0" line.word 0x2 "ADTSDR,A/D Temperature Sensor Data Register" hexmask.word 0x2 0.--15. 1. "ADTSDR,Converted Value 15 to 0" line.word 0x4 "ADOCDR,A/D Internal Reference Voltage Data Register" hexmask.word 0x4 0.--15. 1. "ADOCDR,Converted Value 15 to 0" line.word 0x6 "ADRD,A/D Self-Diagnosis Data Register" bitfld.word 0x6 14.--15. "DIAGST,Self-Diagnosis Status" "0: Self-diagnosis not executed after power-on.,1: Self-diagnosis was executed using the 0 V voltage.,?,?" hexmask.word 0x6 0.--11. 1. "AD,Converted Value 11 to 0" repeat 7. (increment 0x0 0x1)(increment 0x0 0x2) rgroup.word ($2+0x20)++0x1 line.word 0x0 "ADDR$1,A/D Data Registers %s" hexmask.word 0x0 0.--15. 1. "ADDR,Converted Value 15 to 0" repeat.end repeat 7. (increment 0x0 0x1)(increment 0x0 0x2) rgroup.word ($2+0x20)++0x1 line.word 0x0 "ADDR$1,A/D Data Registers %s" hexmask.word 0x0 0.--15. 1. "ADDR,Converted Value 15 to 0" repeat.end rgroup.word 0x26++0x1 line.word 0x0 "ADVMDR,A/D VBATT Monitor Data Register" hexmask.word 0x0 0.--15. 1. "ADDR,Converted Value 15 to 0" group.word 0x66++0x1 line.word 0x0 "ADSHCR,A/D Sample and Hold Circuit Control Register" bitfld.word 0x0 8.--9. "SHANS,Channel-Dedicated Sample-and-Hold Circuit Bypass Select" "0: Bypass the circuits,1: Use the circuits,?,?" hexmask.word.byte 0x0 0.--7. 1. "SSTSH,Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting" group.byte 0x7A++0x0 line.byte 0x0 "ADDISCR,A/D Disconnection Detection Control Register" bitfld.byte 0x0 4. "PCHG,Precharge/discharge select" "0: Discharge,1: Precharge" hexmask.byte 0x0 0.--3. 1. "ADNDIS,Disconnection Detection Assist Setting" group.byte 0x7C++0x0 line.byte 0x0 "ADSHMSR,A/D Sample and Hold Operation Mode Selection Register" bitfld.byte 0x0 0. "SHMD,Sampling Operation Selection" "0: Sampling Operation Selection,1: Enable continuous sampling function" group.word 0x80++0x1 line.word 0x0 "ADGSPCR,A/D Group Scan Priority Control Register" bitfld.word 0x0 15. "GBRP,Single Scan Continuous Start" "0: Single scan is not continuously activated.,1: Single scan for the group with the.." bitfld.word 0x0 14. "LGRRS,Enabled only when PGS = 1 and GBRSCN = 1." "0: Start rescanning from the first channel for..,1: Start rescanning from the channel for which A/D.." newline bitfld.word 0x0 1. "GBRSCN,Lower-Priority Group Restart Setting" "0: Disable rescanning of the group that was stopped..,1: Enable rescanning of the group that was stopped.." bitfld.word 0x0 0. "PGS,Group Priority Operation Setting" "0: Operate without group priority control.,1: Operate with group priority control." rgroup.word 0x84++0x3 line.word 0x0 "ADDBLDRA,A/D Data Duplexing Register A" hexmask.word 0x0 0.--15. 1. "ADDBLDR,Converted Value 15 to 0" line.word 0x2 "ADDBLDRB,A/D Data Duplexing Register B" hexmask.word 0x2 0.--15. 1. "ADDBLDR,Converted Value 15 to 0" rgroup.byte 0x8C++0x0 line.byte 0x0 "ADWINMON,A/D Compare Function Window A/B Status Monitor Register" bitfld.byte 0x0 5. "MONCMPB,Comparison Result Monitor B" "0: Window B comparison conditions are not met.,1: Window B comparison conditions are met." bitfld.byte 0x0 4. "MONCMPA,Comparison Result Monitor A" "0: Window A comparison conditions are not met.,1: Window A comparison conditions are met." newline bitfld.byte 0x0 0. "MONCOMB,Combination Result Monitor" "0: Window A/B composite conditions are not met.,1: Window A/B composite conditions are met." group.word 0x90++0x1 line.word 0x0 "ADCMPCR,A/D Compare Function Control Register" bitfld.word 0x0 15. "CMPAIE,Compare A Interrupt Enable" "0: Disable ADC12i_CMPAI (i = 0 1) interrupt when..,1: Enable ADC12i_CMPAI (i = 0 1) interrupt when.." bitfld.word 0x0 14. "WCMPE,Window Function Setting" "0: Disable window function Window A and window B..,1: Enable window function Window A and window B.." newline bitfld.word 0x0 13. "CMPBIE,Compare B Interrupt Enable" "0: Disable ADC12i_CMPBI (i = 0 1) interrupt when..,1: Enable ADC12i_CMPBI (i = 0 1) interrupt when.." bitfld.word 0x0 11. "CMPAE,Compare Window A Operation Enable" "0: Disable compare window A operation. Disable..,1: Enable compare window A operation." newline bitfld.word 0x0 9. "CMPBE,Compare Window B Operation Enable" "0: Disable compare window B operation. Disable..,1: Enable compare window B operation." bitfld.word 0x0 0.--1. "CMPAB,Window A/B Composite Conditions Setting" "0: Output ADC12i_WCMPM (i = 0 1) when window A OR..,1: Output ADC12i_WCMPM (i = 0 1) when window A EXOR..,?,?" group.byte 0x92++0x1 line.byte 0x0 "ADCMPANSER,A/D Compare Function Window A Extended Input Select Register" bitfld.byte 0x0 1. "CMPOCA,Internal Reference Voltage Compare Select" "0: Exclude the internal reference voltage from the..,1: Include the internal reference voltage in the.." bitfld.byte 0x0 0. "CMPTSA,Temperature Sensor Output Compare Select" "0: Exclude the temperature sensor output from the..,1: Include the temperature sensor output in the.." line.byte 0x1 "ADCMPLER,A/D Compare Function Window A Extended Input Comparison Condition Setting Register" bitfld.byte 0x1 1. "CMPLOCA,Compare Window A Internal Reference Voltage Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.byte 0x1 0. "CMPLTSA,Compare Window A Temperature Sensor Output Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." group.word 0x94++0x1 line.word 0x0 "ADCMPANSR0,A/D Compare Function Window A Channel Select Register 0" bitfld.word 0x0 15. "CMPCHA15,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 14. "CMPCHA14,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 13. "CMPCHA13,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 12. "CMPCHA12,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 11. "CMPCHA11,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 10. "CMPCHA10,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 9. "CMPCHA09,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 8. "CMPCHA08,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 7. "CMPCHA07,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 6. "CMPCHA06,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 5. "CMPCHA05,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 4. "CMPCHA04,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 3. "CMPCHA03,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 2. "CMPCHA02,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." newline bitfld.word 0x0 1. "CMPCHA01,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." bitfld.word 0x0 0. "CMPCHA00,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.." group.word 0x98++0x1 line.word 0x0 "ADCMPLR0,A/D Compare Function Window A Comparison Condition Setting Register 0" bitfld.word 0x0 15. "CMPLCHA15,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 14. "CMPLCHA14,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 13. "CMPLCHA13,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 12. "CMPLCHA12,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 11. "CMPLCHA11,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 10. "CMPLCHA10,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 9. "CMPLCHA09,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 8. "CMPLCHA08,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 7. "CMPLCHA07,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 6. "CMPLCHA06,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 5. "CMPLCHA05,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 4. "CMPLCHA04,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 3. "CMPLCHA03,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 2. "CMPLCHA02,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." newline bitfld.word 0x0 1. "CMPLCHA01,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." bitfld.word 0x0 0. "CMPLCHA00,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." repeat 2. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0x9C)++0x1 line.word 0x0 "ADCMPDR$1,A/D Compare Function Window A Lower-Side/Upper-Side Level Setting Register" repeat.end group.word 0xA0++0x1 line.word 0x0 "ADCMPSR0,A/D Compare Function Window A Channel Status Register 0" bitfld.word 0x0 15. "CMPSTCHA15,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 14. "CMPSTCHA14,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 13. "CMPSTCHA13,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 12. "CMPSTCHA12,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 11. "CMPSTCHA11,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 10. "CMPSTCHA10,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 9. "CMPSTCHA09,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 8. "CMPSTCHA08,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 7. "CMPSTCHA07,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 6. "CMPSTCHA06,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 5. "CMPSTCHA05,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 4. "CMPSTCHA04,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 3. "CMPSTCHA03,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 2. "CMPSTCHA02,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0x0 1. "CMPSTCHA01,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0x0 0. "CMPSTCHA00,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." group.byte 0xA4++0x0 line.byte 0x0 "ADCMPSER,A/D Compare Function Window A Extended Input Channel Status Register" bitfld.byte 0x0 1. "CMPSTOCA,Compare Window A Internal Reference Voltage Compare Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.byte 0x0 0. "CMPSTTSA,Compare Window A Temperature Sensor Output Compare Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." group.byte 0xA6++0x0 line.byte 0x0 "ADCMPBNSR,A/D Compare Function Window B Channel Select Register" bitfld.byte 0x0 7. "CMPLB,Compare Window B Comparison Condition Setting" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.." hexmask.byte 0x0 0.--5. 1. "CMPCHB,Compare Window B Channel Select" group.word 0xA8++0x3 line.word 0x0 "ADWINLLB,A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register" line.word 0x2 "ADWINULB,A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register" group.byte 0xAC++0x0 line.byte 0x0 "ADCMPBSR,A/D Compare Function Window B Status Register" bitfld.byte 0x0 0. "CMPSTB,Compare Window B Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met." repeat 16. (increment 0x0 0x1)(increment 0x0 0x2) rgroup.word ($2+0xB0)++0x1 line.word 0x0 "ADBUF$1,A/D Data Buffer Registers %s" hexmask.word 0x0 0.--15. 1. "ADBUF,Converted Value 15 to 0" repeat.end group.byte 0xD0++0x0 line.byte 0x0 "ADBUFEN,A/D Data Buffer Enable Register" bitfld.byte 0x0 0. "BUFEN,Data Buffer Enable" "0: The data buffer is not used.,1: The data buffer is used." group.byte 0xD2++0x0 line.byte 0x0 "ADBUFPTR,A/D Data Buffer Pointer Register" bitfld.byte 0x0 4. "PTROVF,Pointer Overflow Flag" "0: The data buffer pointer has not overflowed.,1: The data buffer pointer has overflowed." hexmask.byte 0x0 0.--3. 1. "BUFPTR,Data Buffer Pointer" group.byte 0xDD++0x2 line.byte 0x0 "ADSSTRL,A/D Sampling State Register" hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting" line.byte 0x1 "ADSSTRT,A/D Sampling State Register" hexmask.byte 0x1 0.--7. 1. "SST,Sampling Time Setting" line.byte 0x2 "ADSSTRO,A/D Sampling State Register" hexmask.byte 0x2 0.--7. 1. "SST,Sampling Time Setting" repeat 7. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0xE0)++0x0 line.byte 0x0 "ADSSTR$1,A/D Sampling State Register" hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting" repeat.end group.byte 0xE3++0x0 line.byte 0x0 "ADSSTRV,A/D Sampling State Register" hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting" tree.end tree.end tree "AGT (Low Power Asynchronous General Purpose Timer)" base ad:0x0 tree "AGT0" base ad:0x40221000 group.word 0x0++0x5 line.word 0x0 "AGT,AGT Counter Register" line.word 0x2 "AGTCMA,AGT Compare Match A Register" line.word 0x4 "AGTCMB,AGT Compare Match B Register" group.byte 0x8++0x2 line.byte 0x0 "AGTCR,AGT Control Register" bitfld.byte 0x0 7. "TCMBF,Compare Match B Flag" "0: No match,1: Match" bitfld.byte 0x0 6. "TCMAF,Compare Match A Flag" "0: No match,1: Match" newline bitfld.byte 0x0 5. "TUNDF,Underflow Flag" "0: No underflow,1: Underflow" bitfld.byte 0x0 4. "TEDGF,Active Edge Judgment Flag" "0: No active edge received,1: Active edge received" newline bitfld.byte 0x0 2. "TSTOP,AGT Count Forced Stop" "0: Writing is invalid,1: The count is forcibly stopped" rbitfld.byte 0x0 1. "TCSTF,AGT Count Status Flag" "0: Count stopped,1: Count in progress" newline bitfld.byte 0x0 0. "TSTART,AGT Count Start" "0: Count stops,1: Count starts" line.byte 0x1 "AGTMR1,AGT Mode Register 1" bitfld.byte 0x1 4.--6. "TCK,Count Source" "0: Setting prohibited,1: PCLKB/8,?,?,?,?,?,?" bitfld.byte 0x1 3. "TEDGPL,Edge Polarity" "0: Single-edge,1: Both-edge" newline bitfld.byte 0x1 0.--2. "TMOD,Operating Mode" "0: Setting prohibited,1: Pulse output mode,?,?,?,?,?,?" line.byte 0x2 "AGTMR2,AGT Mode Register 2" bitfld.byte 0x2 7. "LPM,Low Power Mode" "0: Normal mode,1: Low power mode" bitfld.byte 0x2 0.--2. "CKS,AGTLCLK or AGTSCLK Count Source Clock Frequency Division Ratio" "0: 1/1,1: 1/2,?,?,?,?,?,?" group.byte 0xC++0x3 line.byte 0x0 "AGTIOC,AGT I/O Control Register" bitfld.byte 0x0 6.--7. "TIOGT,Count Control" "0: Setting prohibited,1: Event is counted during polarity period..,?,?" bitfld.byte 0x0 4.--5. "TIPF,Input Filter" "0: No filter,1: Filter sampled at PCLKB,?,?" newline bitfld.byte 0x0 2. "TOE,AGTOn pin Output Enable" "0: AGTOn pin output disabled,1: AGTOn pin output enabled" bitfld.byte 0x0 0. "TEDGSEL,I/O Polarity Switch" "0,1" line.byte 0x1 "AGTISR,AGT Event Pin Select Register" bitfld.byte 0x1 2. "EEPS,AGTEEn Polarity Selection" "0: An event is counted during the low-level period,1: An event is counted during the high-level period" line.byte 0x2 "AGTCMSR,AGT Compare Match Function Select Register" bitfld.byte 0x2 6. "TOPOLB,AGTOBn Pin Polarity Select" "0: AGTOBn pin output is started on low. i.e. normal..,1: AGTOBn pin output is started on high. i.e." bitfld.byte 0x2 5. "TOEB,AGTOBn Pin Output Enable" "0: AGTOBn pin output disabled,1: AGTOBn pin output enabled" newline bitfld.byte 0x2 4. "TCMEB,AGT Compare Match B Register Enable" "0: Compare match B register disabled,1: Compare match B register enabled" bitfld.byte 0x2 2. "TOPOLA,AGTOAn Pin Polarity Select" "0: AGTOAn pin output is started on low. i.e. normal..,1: AGTOAn pin output is started on high. i.e." newline bitfld.byte 0x2 1. "TOEA,AGTOAn Pin Output Enable" "0: AGTOAn pin output disabled,1: AGTOAn pin output enabled" bitfld.byte 0x2 0. "TCMEA,AGT Compare Match A Register Enable" "0: AGT Compare match A register disabled,1: AGT Compare match A register enabled" line.byte 0x3 "AGTIOSEL,AGT Pin Select Register" bitfld.byte 0x3 4. "TIES,AGTIOn Pin Input Enable" "0: External event input is disabled during Software..,1: External event input is enabled during Software.." tree.end tree "AGT0_NS" base ad:0x50221000 group.word 0x0++0x5 line.word 0x0 "AGT,AGT Counter Register" line.word 0x2 "AGTCMA,AGT Compare Match A Register" line.word 0x4 "AGTCMB,AGT Compare Match B Register" group.byte 0x8++0x2 line.byte 0x0 "AGTCR,AGT Control Register" bitfld.byte 0x0 7. "TCMBF,Compare Match B Flag" "0: No match,1: Match" bitfld.byte 0x0 6. "TCMAF,Compare Match A Flag" "0: No match,1: Match" newline bitfld.byte 0x0 5. "TUNDF,Underflow Flag" "0: No underflow,1: Underflow" bitfld.byte 0x0 4. "TEDGF,Active Edge Judgment Flag" "0: No active edge received,1: Active edge received" newline bitfld.byte 0x0 2. "TSTOP,AGT Count Forced Stop" "0: Writing is invalid,1: The count is forcibly stopped" rbitfld.byte 0x0 1. "TCSTF,AGT Count Status Flag" "0: Count stopped,1: Count in progress" newline bitfld.byte 0x0 0. "TSTART,AGT Count Start" "0: Count stops,1: Count starts" line.byte 0x1 "AGTMR1,AGT Mode Register 1" bitfld.byte 0x1 4.--6. "TCK,Count Source" "0: Setting prohibited,1: PCLKB/8,?,?,?,?,?,?" bitfld.byte 0x1 3. "TEDGPL,Edge Polarity" "0: Single-edge,1: Both-edge" newline bitfld.byte 0x1 0.--2. "TMOD,Operating Mode" "0: Setting prohibited,1: Pulse output mode,?,?,?,?,?,?" line.byte 0x2 "AGTMR2,AGT Mode Register 2" bitfld.byte 0x2 7. "LPM,Low Power Mode" "0: Normal mode,1: Low power mode" bitfld.byte 0x2 0.--2. "CKS,AGTLCLK or AGTSCLK Count Source Clock Frequency Division Ratio" "0: 1/1,1: 1/2,?,?,?,?,?,?" group.byte 0xC++0x3 line.byte 0x0 "AGTIOC,AGT I/O Control Register" bitfld.byte 0x0 6.--7. "TIOGT,Count Control" "0: Setting prohibited,1: Event is counted during polarity period..,?,?" bitfld.byte 0x0 4.--5. "TIPF,Input Filter" "0: No filter,1: Filter sampled at PCLKB,?,?" newline bitfld.byte 0x0 2. "TOE,AGTOn pin Output Enable" "0: AGTOn pin output disabled,1: AGTOn pin output enabled" bitfld.byte 0x0 0. "TEDGSEL,I/O Polarity Switch" "0,1" line.byte 0x1 "AGTISR,AGT Event Pin Select Register" bitfld.byte 0x1 2. "EEPS,AGTEEn Polarity Selection" "0: An event is counted during the low-level period,1: An event is counted during the high-level period" line.byte 0x2 "AGTCMSR,AGT Compare Match Function Select Register" bitfld.byte 0x2 6. "TOPOLB,AGTOBn Pin Polarity Select" "0: AGTOBn pin output is started on low. i.e. normal..,1: AGTOBn pin output is started on high. i.e." bitfld.byte 0x2 5. "TOEB,AGTOBn Pin Output Enable" "0: AGTOBn pin output disabled,1: AGTOBn pin output enabled" newline bitfld.byte 0x2 4. "TCMEB,AGT Compare Match B Register Enable" "0: Compare match B register disabled,1: Compare match B register enabled" bitfld.byte 0x2 2. "TOPOLA,AGTOAn Pin Polarity Select" "0: AGTOAn pin output is started on low. i.e. normal..,1: AGTOAn pin output is started on high. i.e." newline bitfld.byte 0x2 1. "TOEA,AGTOAn Pin Output Enable" "0: AGTOAn pin output disabled,1: AGTOAn pin output enabled" bitfld.byte 0x2 0. "TCMEA,AGT Compare Match A Register Enable" "0: AGT Compare match A register disabled,1: AGT Compare match A register enabled" line.byte 0x3 "AGTIOSEL,AGT Pin Select Register" bitfld.byte 0x3 4. "TIES,AGTIOn Pin Input Enable" "0: External event input is disabled during Software..,1: External event input is enabled during Software.." tree.end tree "AGT1" base ad:0x40221100 group.word 0x0++0x5 line.word 0x0 "AGT,AGT Counter Register" line.word 0x2 "AGTCMA,AGT Compare Match A Register" line.word 0x4 "AGTCMB,AGT Compare Match B Register" group.byte 0x8++0x2 line.byte 0x0 "AGTCR,AGT Control Register" bitfld.byte 0x0 7. "TCMBF,Compare Match B Flag" "0: No match,1: Match" bitfld.byte 0x0 6. "TCMAF,Compare Match A Flag" "0: No match,1: Match" newline bitfld.byte 0x0 5. "TUNDF,Underflow Flag" "0: No underflow,1: Underflow" bitfld.byte 0x0 4. "TEDGF,Active Edge Judgment Flag" "0: No active edge received,1: Active edge received" newline bitfld.byte 0x0 2. "TSTOP,AGT Count Forced Stop" "0: Writing is invalid,1: The count is forcibly stopped" rbitfld.byte 0x0 1. "TCSTF,AGT Count Status Flag" "0: Count stopped,1: Count in progress" newline bitfld.byte 0x0 0. "TSTART,AGT Count Start" "0: Count stops,1: Count starts" line.byte 0x1 "AGTMR1,AGT Mode Register 1" bitfld.byte 0x1 4.--6. "TCK,Count Source" "0: Setting prohibited,1: PCLKB/8,?,?,?,?,?,?" bitfld.byte 0x1 3. "TEDGPL,Edge Polarity" "0: Single-edge,1: Both-edge" newline bitfld.byte 0x1 0.--2. "TMOD,Operating Mode" "0: Setting prohibited,1: Pulse output mode,?,?,?,?,?,?" line.byte 0x2 "AGTMR2,AGT Mode Register 2" bitfld.byte 0x2 7. "LPM,Low Power Mode" "0: Normal mode,1: Low power mode" bitfld.byte 0x2 0.--2. "CKS,AGTLCLK or AGTSCLK Count Source Clock Frequency Division Ratio" "0: 1/1,1: 1/2,?,?,?,?,?,?" group.byte 0xC++0x3 line.byte 0x0 "AGTIOC,AGT I/O Control Register" bitfld.byte 0x0 6.--7. "TIOGT,Count Control" "0: Setting prohibited,1: Event is counted during polarity period..,?,?" bitfld.byte 0x0 4.--5. "TIPF,Input Filter" "0: No filter,1: Filter sampled at PCLKB,?,?" newline bitfld.byte 0x0 2. "TOE,AGTOn pin Output Enable" "0: AGTOn pin output disabled,1: AGTOn pin output enabled" bitfld.byte 0x0 0. "TEDGSEL,I/O Polarity Switch" "0,1" line.byte 0x1 "AGTISR,AGT Event Pin Select Register" bitfld.byte 0x1 2. "EEPS,AGTEEn Polarity Selection" "0: An event is counted during the low-level period,1: An event is counted during the high-level period" line.byte 0x2 "AGTCMSR,AGT Compare Match Function Select Register" bitfld.byte 0x2 6. "TOPOLB,AGTOBn Pin Polarity Select" "0: AGTOBn pin output is started on low. i.e. normal..,1: AGTOBn pin output is started on high. i.e." bitfld.byte 0x2 5. "TOEB,AGTOBn Pin Output Enable" "0: AGTOBn pin output disabled,1: AGTOBn pin output enabled" newline bitfld.byte 0x2 4. "TCMEB,AGT Compare Match B Register Enable" "0: Compare match B register disabled,1: Compare match B register enabled" bitfld.byte 0x2 2. "TOPOLA,AGTOAn Pin Polarity Select" "0: AGTOAn pin output is started on low. i.e. normal..,1: AGTOAn pin output is started on high. i.e." newline bitfld.byte 0x2 1. "TOEA,AGTOAn Pin Output Enable" "0: AGTOAn pin output disabled,1: AGTOAn pin output enabled" bitfld.byte 0x2 0. "TCMEA,AGT Compare Match A Register Enable" "0: AGT Compare match A register disabled,1: AGT Compare match A register enabled" line.byte 0x3 "AGTIOSEL,AGT Pin Select Register" bitfld.byte 0x3 4. "TIES,AGTIOn Pin Input Enable" "0: External event input is disabled during Software..,1: External event input is enabled during Software.." tree.end tree "AGT1_NS" base ad:0x50221100 group.word 0x0++0x5 line.word 0x0 "AGT,AGT Counter Register" line.word 0x2 "AGTCMA,AGT Compare Match A Register" line.word 0x4 "AGTCMB,AGT Compare Match B Register" group.byte 0x8++0x2 line.byte 0x0 "AGTCR,AGT Control Register" bitfld.byte 0x0 7. "TCMBF,Compare Match B Flag" "0: No match,1: Match" bitfld.byte 0x0 6. "TCMAF,Compare Match A Flag" "0: No match,1: Match" newline bitfld.byte 0x0 5. "TUNDF,Underflow Flag" "0: No underflow,1: Underflow" bitfld.byte 0x0 4. "TEDGF,Active Edge Judgment Flag" "0: No active edge received,1: Active edge received" newline bitfld.byte 0x0 2. "TSTOP,AGT Count Forced Stop" "0: Writing is invalid,1: The count is forcibly stopped" rbitfld.byte 0x0 1. "TCSTF,AGT Count Status Flag" "0: Count stopped,1: Count in progress" newline bitfld.byte 0x0 0. "TSTART,AGT Count Start" "0: Count stops,1: Count starts" line.byte 0x1 "AGTMR1,AGT Mode Register 1" bitfld.byte 0x1 4.--6. "TCK,Count Source" "0: Setting prohibited,1: PCLKB/8,?,?,?,?,?,?" bitfld.byte 0x1 3. "TEDGPL,Edge Polarity" "0: Single-edge,1: Both-edge" newline bitfld.byte 0x1 0.--2. "TMOD,Operating Mode" "0: Setting prohibited,1: Pulse output mode,?,?,?,?,?,?" line.byte 0x2 "AGTMR2,AGT Mode Register 2" bitfld.byte 0x2 7. "LPM,Low Power Mode" "0: Normal mode,1: Low power mode" bitfld.byte 0x2 0.--2. "CKS,AGTLCLK or AGTSCLK Count Source Clock Frequency Division Ratio" "0: 1/1,1: 1/2,?,?,?,?,?,?" group.byte 0xC++0x3 line.byte 0x0 "AGTIOC,AGT I/O Control Register" bitfld.byte 0x0 6.--7. "TIOGT,Count Control" "0: Setting prohibited,1: Event is counted during polarity period..,?,?" bitfld.byte 0x0 4.--5. "TIPF,Input Filter" "0: No filter,1: Filter sampled at PCLKB,?,?" newline bitfld.byte 0x0 2. "TOE,AGTOn pin Output Enable" "0: AGTOn pin output disabled,1: AGTOn pin output enabled" bitfld.byte 0x0 0. "TEDGSEL,I/O Polarity Switch" "0,1" line.byte 0x1 "AGTISR,AGT Event Pin Select Register" bitfld.byte 0x1 2. "EEPS,AGTEEn Polarity Selection" "0: An event is counted during the low-level period,1: An event is counted during the high-level period" line.byte 0x2 "AGTCMSR,AGT Compare Match Function Select Register" bitfld.byte 0x2 6. "TOPOLB,AGTOBn Pin Polarity Select" "0: AGTOBn pin output is started on low. i.e. normal..,1: AGTOBn pin output is started on high. i.e." bitfld.byte 0x2 5. "TOEB,AGTOBn Pin Output Enable" "0: AGTOBn pin output disabled,1: AGTOBn pin output enabled" newline bitfld.byte 0x2 4. "TCMEB,AGT Compare Match B Register Enable" "0: Compare match B register disabled,1: Compare match B register enabled" bitfld.byte 0x2 2. "TOPOLA,AGTOAn Pin Polarity Select" "0: AGTOAn pin output is started on low. i.e. normal..,1: AGTOAn pin output is started on high. i.e." newline bitfld.byte 0x2 1. "TOEA,AGTOAn Pin Output Enable" "0: AGTOAn pin output disabled,1: AGTOAn pin output enabled" bitfld.byte 0x2 0. "TCMEA,AGT Compare Match A Register Enable" "0: AGT Compare match A register disabled,1: AGT Compare match A register enabled" line.byte 0x3 "AGTIOSEL,AGT Pin Select Register" bitfld.byte 0x3 4. "TIES,AGTIOn Pin Input Enable" "0: External event input is disabled during Software..,1: External event input is enabled during Software.." tree.end tree.end tree "BUS (Bus Control)" base ad:0x0 tree "BUS" base ad:0x40003000 repeat 8. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0x2)++0x1 line.word 0x0 "CS$1MOD,CS%s Mode Register (n = 0 to 7)" bitfld.word 0x0 15. "PRMOD,Page Read Access Mode Select" "0: Normal access compatible mode,1: External data read continuous assertion mode" bitfld.word 0x0 9. "PWENB,Page Write Access Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 8. "PRENB,Page Read Access Enable" "0: Disabled,1: Enabled" bitfld.word 0x0 3. "EWENB,External Wait Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 0. "WRMOD,Write Access Mode Select" "0: Byte strobe mode,1: Single-write strobe mode" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x4)++0x3 line.long 0x0 "CS$1WCR1,CS%s Wait Control Register 1 (n = 0 to 7)" hexmask.long.byte 0x0 24.--28. 1. "CSRWAIT,Normal Read Cycle Wait Select" hexmask.long.byte 0x0 16.--20. 1. "CSWWAIT,Normal Write Cycle Wait Select" newline bitfld.long 0x0 8.--10. "CSPRWAIT,Page Read Cycle Wait Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "CSPWWAIT,Page Write Cycle Wait Select" "0,1,2,3,4,5,6,7" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x8)++0x3 line.long 0x0 "CS$1WCR2,CS%s Wait Control Register 2 (n = 0 to 7)" bitfld.long 0x0 28.--30. "CSON,CS Assert Wait Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "WDON,Write Data Output Wait Select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "WRON,WR Assert Wait Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "RDON,RD Assert Wait Select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--13. "AWAIT,Address Cycle Wait Select" "0,1,2,3" bitfld.long 0x0 8.--10. "WDOFF,Write Data Output Extension Cycle Select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "CSWOFF,Write Access CS Extension Cycle Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "CSROFF,Read Access CS Extension Cycle Select" "0,1,2,3,4,5,6,7" repeat.end group.word 0x802++0x1 line.word 0x0 "CS0CR,CS0 Control Register" bitfld.word 0x0 12. "MPXEN,Address/Data Multiplexed I/O Interface Select" "0: Separate bus interface is selected for area n.,1: Address/data multiplexed I/O interface is.." bitfld.word 0x0 8. "EMODE,Endian Mode" "0: Little endian,1: Big endian" newline bitfld.word 0x0 4.--5. "BSIZE,External Bus Width Select" "0: Setting prohibited,?,?,?" bitfld.word 0x0 0. "EXENB,Operation Enable" "0: Disable operation,1: Enable operation" repeat 8. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0x80A)++0x1 line.word 0x0 "CS$1REC,CS%s Recovery Cycle Register (n = 0 to 7)" hexmask.word.byte 0x0 8.--11. 1. "WRCV,Write Recovery" hexmask.word.byte 0x0 0.--3. 1. "RRCV,Read Recovery" repeat.end repeat 7. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0x812)++0x1 line.word 0x0 "CS$1CR,CS%s Control Register" bitfld.word 0x0 12. "MPXEN,Address/Data Multiplexed I/O Interface Select" "0: Separate bus interface is selected for area n.,1: Address/data multiplexed I/O interface is.." bitfld.word 0x0 8. "EMODE,Endian Mode" "0: Little endian,1: Big endian" newline bitfld.word 0x0 4.--5. "BSIZE,External Bus Width Select" "0: Setting prohibited,?,?,?" bitfld.word 0x0 0. "EXENB,Operation Enable" "0: Disable operation,1: Enable operation" repeat.end group.word 0x880++0x1 line.word 0x0 "CSRECEN,CS Recovery Cycle Insertion Enable Register" bitfld.word 0x0 15. "RCVENM7,Multiplexed Bus Recovery Cycle Insertion Enable 7" "0: Disabled,1: Enabled" bitfld.word 0x0 14. "RCVENM6,Multiplexed Bus Recovery Cycle Insertion Enable 6" "0: Disabled,1: Enabled" newline bitfld.word 0x0 13. "RCVENM5,Multiplexed Bus Recovery Cycle Insertion Enable 5" "0: Disabled,1: Enabled" bitfld.word 0x0 12. "RCVENM4,Multiplexed Bus Recovery Cycle Insertion Enable 4" "0: Disabled,1: Enabled" newline bitfld.word 0x0 11. "RCVENM3,Multiplexed Bus Recovery Cycle Insertion Enable 3" "0: Disabled,1: Enabled" bitfld.word 0x0 10. "RCVENM2,Multiplexed Bus Recovery Cycle Insertion Enable 2" "0: Disabled,1: Enabled" newline bitfld.word 0x0 9. "RCVENM1,Multiplexed Bus Recovery Cycle Insertion Enable 1" "0: Disabled,1: Enabled" bitfld.word 0x0 8. "RCVENM0,Multiplexed Bus Recovery Cycle Insertion Enable 0" "0: Disabled,1: Enabled" newline bitfld.word 0x0 7. "RCVEN7,Separate Bus Recovery Cycle Insertion Enable 7" "0: Disabled,1: Enabled" bitfld.word 0x0 6. "RCVEN6,Separate Bus Recovery Cycle Insertion Enable 6" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "RCVEN5,Separate Bus Recovery Cycle Insertion Enable 5" "0: Disabled,1: Enabled" bitfld.word 0x0 4. "RCVEN4,Separate Bus Recovery Cycle Insertion Enable 4" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "RCVEN3,Separate Bus Recovery Cycle Insertion Enable 3" "0: Disabled,1: Enabled" bitfld.word 0x0 2. "RCVEN2,Separate Bus Recovery Cycle Insertion Enable 2" "0: Disabled,1: Enabled" newline bitfld.word 0x0 1. "RCVEN1,Separate Bus Recovery Cycle Insertion Enable 1" "0: Disabled,1: Enabled" bitfld.word 0x0 0. "RCVEN0,Separate Bus Recovery Cycle Insertion Enable 0" "0: Disabled,1: Enabled" group.byte 0xC00++0x2 line.byte 0x0 "SDCCR,SDC Control Register" bitfld.byte 0x0 4.--5. "BSIZE,SDRAM Bus Width Select" "0: Setting prohibited,?,?,?" bitfld.byte 0x0 0. "EXENB,Operation Enable" "0: Disable,1: Enable" line.byte 0x1 "SDCMOD,SDC Mode Register" bitfld.byte 0x1 0. "EMODE,Endian Mode" "0: Endian order of SDRAM address space is the same..,1: Endian order of SDRAM address space is not the.." line.byte 0x2 "SDAMOD,SDRAM Access Mode Register" bitfld.byte 0x2 0. "BE,Continuous Access Enable" "0: Continuous access is disabled,1: Continuous access is enabled" group.byte 0xC10++0x0 line.byte 0x0 "SDSELF,SDRAM Self-Refresh Control Register" bitfld.byte 0x0 0. "SFEN,SDRAM Self-Refresh Enable" "0: Disable,1: Enable" group.word 0xC14++0x1 line.word 0x0 "SDRFCR,SDRAM Refresh Control Register" hexmask.word.byte 0x0 12.--15. 1. "REFW,Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count Setting" hexmask.word 0x0 0.--11. 1. "RFC,Auto-Refresh Request Interval Setting" group.byte 0xC16++0x0 line.byte 0x0 "SDRFEN,SDRAM Auto-Refresh Control Register" bitfld.byte 0x0 0. "RFEN,Auto-Refresh Operation Enable" "0: Disable,1: Enable" group.byte 0xC20++0x0 line.byte 0x0 "SDICR,SDRAM Initialization Sequence Control Register" bitfld.byte 0x0 0. "INIRQ,Initialization Sequence Start" "0: Invalid,1: Start initialization sequence" group.word 0xC24++0x1 line.word 0x0 "SDIR,SDRAM Initialization Register" bitfld.word 0x0 8.--10. "PRC,Initialization Precharge Cycle Count" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 4.--7. 1. "ARFC,Initialization Auto-Refresh Count" newline hexmask.word.byte 0x0 0.--3. 1. "ARFI,Initialization Auto-Refresh Interval" group.byte 0xC40++0x0 line.byte 0x0 "SDADR,SDRAM Address Register" bitfld.byte 0x0 0.--1. "MXC,Address Multiplex Select" "0: 8-bit shift,1: 9-bit shift,?,?" group.long 0xC44++0x3 line.long 0x0 "SDTR,SDRAM Timing Register" bitfld.long 0x0 16.--18. "RAI,Row Active Interval" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "RCD,Row Column Latency" "0: 1 cycle,1: 2 cycles,?,?" newline bitfld.long 0x0 9.--11. "RP,Row Precharge Interval" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "WR,Write Recovery Interval" "0: 1 cycle,1: 2 cycles" newline bitfld.long 0x0 0.--2. "CL,SDRAMC Column Latency" "0,1,2,3,4,5,6,7" group.word 0xC48++0x1 line.word 0x0 "SDMOD,SDRAM Mode Register" hexmask.word 0x0 0.--14. 1. "MR,Mode Register Setting" rgroup.byte 0xC50++0x0 line.byte 0x0 "SDSR,SDRAM Status Register" bitfld.byte 0x0 4. "SRFST,Self-Refresh Transition/Recovery Status" "0: Transition/recovery not in progress,1: Transition/recovery in progress" bitfld.byte 0x0 3. "INIST,Initialization Status" "0: Initialization sequence not in progress,1: Initialization sequence in progress" newline bitfld.byte 0x0 0. "MRSST,Mode Register Setting Status" "0: Mode register setting not in progress,1: Mode register setting in progress" group.word 0x1000++0x1 line.word 0x0 "BUSOAD,BUS Operation After Detection Register" bitfld.word 0x0 2. "BWERROAD,Bufferable write error operation after detection" "0,1" bitfld.word 0x0 1. "SLERROAD,Slave bus error operation after detection" "0,1" newline bitfld.word 0x0 0. "ILERROAD,Illegal address access error operation after detection" "0,1" group.word 0x1004++0x1 line.word 0x0 "BUSOADPT,BUS Operation After Detection Protect Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: BUSOAD register writing is possible.,1: BUSOAD register writing is protected. Read is.." group.word 0x1010++0x1 line.word 0x0 "MSAOAD,Master Security Attribution Operation After Detection Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "OAD,Operation after detection" "0: NMI,1: Reset" group.word 0x1014++0x1 line.word 0x0 "MSAPT,Master Security Attribution Protect Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: MSAOAD register writing is possible.,1: MSAOAD register writing is protected. Read is.." group.long 0x1100++0x3 line.long 0x0 "BUSMABT,Bus Master Arbitration Control Register" bitfld.long 0x0 0. "ARBS,Arbitration Select for GDSSBI" "0: Fixed priority,1: Round-robin" group.long 0x1200++0x3 line.long 0x0 "BUSSABT1FHBI,Bus Slave Arbitration Control Register 1(x = FHBI. S0BI. S1BI)" bitfld.long 0x0 0.--1. "ARBS,Arbitration Select for " "0: Fixed priority,1: Setting prohibited,?,?" group.long 0x1210++0x3 line.long 0x0 "BUSSABT0FLBI,Bus Slave Arbitration Control Register 0" bitfld.long 0x0 0. "ARBS,Arbitration Select for " "0: Fixed priority,1: Round-robin" group.long 0x1218++0x3 line.long 0x0 "BUSSABT1S0BI,Bus Slave Arbitration Control Register 1(x = FHBI. S0BI. S1BI)" bitfld.long 0x0 0.--1. "ARBS,Arbitration Select for " "0: Fixed priority,1: Setting prohibited,?,?" group.long 0x1220++0x3 line.long 0x0 "BUSSABT1S1BI,Bus Slave Arbitration Control Register 1(x = FHBI. S0BI. S1BI)" bitfld.long 0x0 0.--1. "ARBS,Arbitration Select for " "0: Fixed priority,1: Setting prohibited,?,?" group.long 0x1248++0x3 line.long 0x0 "BUSSABT0STBYSBI,Bus Slave Arbitration Control Register 0" bitfld.long 0x0 0. "ARBS,Arbitration Select for " "0: Fixed priority,1: Round-robin" group.long 0x1250++0x3 line.long 0x0 "BUSSABT0ECBI,Bus Slave Arbitration Control Register 0" bitfld.long 0x0 0. "ARBS,Arbitration Select for " "0: Fixed priority,1: Round-robin" group.long 0x1258++0x3 line.long 0x0 "BUSSABT0EOBI,Bus Slave Arbitration Control Register 0" bitfld.long 0x0 0. "ARBS,Arbitration Select for " "0: Fixed priority,1: Round-robin" group.long 0x1260++0x3 line.long 0x0 "BUSSABT0PBBI,Bus Slave Arbitration Control Register 0" bitfld.long 0x0 0. "ARBS,Arbitration Select for " "0: Fixed priority,1: Round-robin" group.long 0x1268++0x3 line.long 0x0 "BUSSABT0PABI,Bus Slave Arbitration Control Register 0" bitfld.long 0x0 0. "ARBS,Arbitration Select for " "0: Fixed priority,1: Round-robin" group.long 0x1270++0x3 line.long 0x0 "BUSSABT0PIBI,Bus Slave Arbitration Control Register 0" bitfld.long 0x0 0. "ARBS,Arbitration Select for " "0: Fixed priority,1: Round-robin" group.long 0x1278++0x3 line.long 0x0 "BUSSABT0PSBI,Bus Slave Arbitration Control Register 0" bitfld.long 0x0 0. "ARBS,Arbitration Select for " "0: Fixed priority,1: Round-robin" group.long 0x1300++0x3 line.long 0x0 "BUSDIVBYP,Bus Divider Bypass Register" bitfld.long 0x0 16. "CPU0SBPE,Divider for CPUSAHBI bypass enable" "0: Disable,1: Enable" bitfld.long 0x0 3. "GDSSBPE,Divider for GDSSBI bypass enable" "0: Disable,1: Enable" rgroup.long 0x1800++0x3 line.long 0x0 "BUS4ERRADD,BUS Error Address Register (n = 4)" hexmask.long 0x0 0.--31. 1. "BERAD,Bus Error Address" rgroup.byte 0x1804++0x0 line.byte 0x0 "BUS4ERRRW,BUS Error Read Write (n = 4)" bitfld.byte 0x0 0. "RWSTAT,Error access Read/Write Status" "0: Read access,1: Write access" repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.long ($2+0x1820)++0x3 line.long 0x0 "BUS$1ERRADD,BUS Error Address Register (n = 6 to 9)" hexmask.long 0x0 0.--31. 1. "BERAD,Bus Error Address" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x1824)++0x0 line.byte 0x0 "BUS$1ERRRW,BUS Error Read Write (n = 6 to 9)" bitfld.byte 0x0 0. "RWSTAT,Error access Read/Write Status" "0: Read access,1: Write access" repeat.end rgroup.long 0x1900++0x3 line.long 0x0 "BMSA4ERRADD,Bus Master Security Attribution Unit Error Address" hexmask.long 0x0 0.--31. 1. "MSERAD,Bus Master Security Attribution Unit Error Address" rgroup.byte 0x1904++0x0 line.byte 0x0 "BMSA4ERRRW,BUS Master Security Attribution Unit Error Read Write (n = 4)" bitfld.byte 0x0 0. "MSARWSTAT,Master Security Attribution Unit error access Read/Write Status" "0: Read access,1: Write access" repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.long ($2+0x1920)++0x3 line.long 0x0 "BMSA$1ERRADD,Bus Master Security Attribution Unit Error Address" hexmask.long 0x0 0.--31. 1. "MSERAD,Bus Master Security Attribution Unit Error Address" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x1924)++0x0 line.byte 0x0 "BMSA$1ERRRW,BUS Master Security Attribution Unit Error Read Write (n = 6 to 9)" bitfld.byte 0x0 0. "MSARWSTAT,Master Security Attribution Unit error access Read/Write Status" "0: Read access,1: Write access" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x1A00)++0x0 line.byte 0x0 "BUS$1ERRSTAT,BUS Error Status Register" bitfld.byte 0x0 5. "MSERRSTAT,Master Security Attribution Unit Error Status" "0: No error occurred,1: Error occurred" bitfld.byte 0x0 4. "ILERRSTAT,Illegal Address Access Error Status" "0: No error occurred,1: Error occurred" newline bitfld.byte 0x0 3. "MMERRSTAT,Master MPU Error Status" "0: No error occurred,1: Error occurred" bitfld.byte 0x0 0. "SLERRSTAT,Slave Bus Error Status" "0: No error occurred,1: Error occurred" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) group.byte ($2+0x1A08)++0x0 line.byte 0x0 "BUS$1ERRCLR,BUS Error Clear Register" bitfld.byte 0x0 5. "MSERRCLR,Master Security Attribution Unit Error Clear" "0,1" bitfld.byte 0x0 4. "ILERRCLR,Illegal Address Access Error Clear" "0,1" newline bitfld.byte 0x0 3. "MMERRCLR,Master MPU Error Clear" "0,1" bitfld.byte 0x0 0. "SLERRCLR,Slave Bus Error Clear" "0,1" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x1A50)++0x0 line.byte 0x0 "BUS$1ERRSTAT,BUS Error Status Register" bitfld.byte 0x0 5. "MSERRSTAT,Master Security Attribution Unit Error Status" "0: No error occurred,1: Error occurred" bitfld.byte 0x0 4. "ILERRSTAT,Illegal Address Access Error Status" "0: No error occurred,1: Error occurred" newline bitfld.byte 0x0 3. "MMERRSTAT,Master MPU Error Status" "0: No error occurred,1: Error occurred" bitfld.byte 0x0 0. "SLERRSTAT,Slave Bus Error Status" "0: No error occurred,1: Error occurred" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) group.byte ($2+0x1A58)++0x0 line.byte 0x0 "BUS$1ERRCLR,BUS Error Clear Register" bitfld.byte 0x0 5. "MSERRCLR,Master Security Attribution Unit Error Clear" "0,1" bitfld.byte 0x0 4. "ILERRCLR,Illegal Address Access Error Clear" "0,1" newline bitfld.byte 0x0 3. "MMERRCLR,Master MPU Error Clear" "0,1" bitfld.byte 0x0 0. "SLERRCLR,Slave Bus Error Clear" "0,1" repeat.end rgroup.long 0x1B00++0x3 line.long 0x0 "MBWERRSTAT,Master Bufferable Write Error Status Register" bitfld.long 0x0 23. "MBWERR23,Master Bufferable Write Error" "0: No bufferable write error in Master #23,1: Bufferable write error occurs in Master #23" bitfld.long 0x0 20. "MBWERR20,Master Bufferable Write Error" "0: No bufferable write error in Master #20,1: Bufferable write error occurs in Master #20" newline bitfld.long 0x0 19. "MBWERR19,Master Bufferable Write Error" "0: No bufferable write error in Master #19,1: Bufferable write error occurs in Master #19" bitfld.long 0x0 18. "MBWERR18,Master Bufferable Write Error" "0: No bufferable write error in Master #18,1: Bufferable write error occurs in Master #18" newline bitfld.long 0x0 17. "MBWERR17,Master Bufferable Write Error" "0: No bufferable write error in Master #17,1: Bufferable write error occurs in Master #17" bitfld.long 0x0 8. "MBWERR8,Master Bufferable Write Error" "0: No bufferable write error in Master #8,1: Bufferable write error occurs in Master #8" newline bitfld.long 0x0 1. "MBWERR1,Master Bufferable Write Error" "0: No bufferable write error in Master #1,1: Bufferable write error occurs in Master #1" bitfld.long 0x0 0. "MBWERR0,Master Bufferable Write Error" "0: No bufferable write error in Master #0,1: Bufferable write error occurs in Master #0" group.long 0x1B08++0x3 line.long 0x0 "MBWERRCLR,Master Bufferable Write Error Clear Register" bitfld.long 0x0 23. "MBWECLR23,Master Bufferable Write Error Clear" "0,1" bitfld.long 0x0 20. "MBWECLR20,Master Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 19. "MBWECLR19,Master Bufferable Write Error Clear" "0,1" bitfld.long 0x0 18. "MBWECLR18,Master Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 17. "MBWECLR17,Master Bufferable Write Error Clear" "0,1" bitfld.long 0x0 8. "MBWECLR8,Master Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 1. "MBWECLR1,Master Bufferable Write Error Clear" "0,1" bitfld.long 0x0 0. "MBWECLR0,Master Bufferable Write Error Clear" "0,1" rgroup.long 0x1B20++0x3 line.long 0x0 "SBWERRSTAT,Slave Bufferable Write Error Status Register" bitfld.long 0x0 12. "SBWERR12,Slave Bufferable Write Error" "0: No bufferable write error in Slave #12,1: Bufferable write error occurs in Slave #12" bitfld.long 0x0 11. "SBWERR11,Slave Bufferable Write Error" "0: No bufferable write error in Slave #11,1: Bufferable write error occurs in Slave #11" newline bitfld.long 0x0 10. "SBWERR10,Slave Bufferable Write Error" "0: No bufferable write error in Slave #10,1: Bufferable write error occurs in Slave #10" bitfld.long 0x0 9. "SBWERR9,Slave Bufferable Write Error" "0: No bufferable write error in Slave #9,1: Bufferable write error occurs in Slave #9" newline bitfld.long 0x0 8. "SBWERR8,Slave Bufferable Write Error" "0: No bufferable write error in Slave #8,1: Bufferable write error occurs in Slave #8" bitfld.long 0x0 7. "SBWERR7,Slave Bufferable Write Error" "0: No bufferable write error in Slave #7,1: Bufferable write error occurs in Slave #7" newline bitfld.long 0x0 6. "SBWERR6,Slave Bufferable Write Error" "0: No bufferable write error in Slave #6,1: Bufferable write error occurs in Slave #6" bitfld.long 0x0 5. "SBWERR5,Slave Bufferable Write Error" "0: No bufferable write error in Slave #5,1: Bufferable write error occurs in Slave #5" newline bitfld.long 0x0 4. "SBWERR4,Slave Bufferable Write Error" "0: No bufferable write error in Slave #4,1: Bufferable write error occurs in Slave #4" bitfld.long 0x0 3. "SBWERR3,Slave Bufferable Write Error" "0: No bufferable write error in Slave #3,1: Bufferable write error occurs in Slave #3" newline bitfld.long 0x0 2. "SBWERR2,Slave Bufferable Write Error" "0: No bufferable write error in Slave #2,1: Bufferable write error occurs in Slave #2" bitfld.long 0x0 1. "SBWERR1,Slave Bufferable Write Error" "0: No bufferable write error in Slave #1,1: Bufferable write error occurs in Slave #1" newline bitfld.long 0x0 0. "SBWERR0,Slave Bufferable Write Error" "0: No bufferable write error in Slave #0,1: Bufferable write error occurs in Slave #0" group.long 0x1B28++0x3 line.long 0x0 "SBWERRCLR,Slave Bufferable Write Error Clear Register" bitfld.long 0x0 12. "SBWECLR12,Slave Bufferable Write Error Clear" "0,1" bitfld.long 0x0 11. "SBWECLR11,Slave Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 10. "SBWECLR10,Slave Bufferable Write Error Clear" "0,1" bitfld.long 0x0 9. "SBWECLR9,Slave Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 8. "SBWECLR8,Slave Bufferable Write Error Clear" "0,1" bitfld.long 0x0 7. "SBWECLR7,Slave Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 6. "SBWECLR6,Slave Bufferable Write Error Clear" "0,1" bitfld.long 0x0 5. "SBWECLR5,Slave Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 4. "SBWECLR4,Slave Bufferable Write Error Clear" "0,1" bitfld.long 0x0 3. "SBWECLR3,Slave Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 2. "SBWECLR2,Slave Bufferable Write Error Clear" "0,1" bitfld.long 0x0 1. "SBWECLR1,Slave Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 0. "SBWECLR0,Slave Bufferable Write Error Clear" "0,1" tree.end tree "BUS_NS" base ad:0x50003000 repeat 8. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0x2)++0x1 line.word 0x0 "CS$1MOD,CS%s Mode Register (n = 0 to 7)" bitfld.word 0x0 15. "PRMOD,Page Read Access Mode Select" "0: Normal access compatible mode,1: External data read continuous assertion mode" bitfld.word 0x0 9. "PWENB,Page Write Access Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 8. "PRENB,Page Read Access Enable" "0: Disabled,1: Enabled" bitfld.word 0x0 3. "EWENB,External Wait Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 0. "WRMOD,Write Access Mode Select" "0: Byte strobe mode,1: Single-write strobe mode" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x4)++0x3 line.long 0x0 "CS$1WCR1,CS%s Wait Control Register 1 (n = 0 to 7)" hexmask.long.byte 0x0 24.--28. 1. "CSRWAIT,Normal Read Cycle Wait Select" hexmask.long.byte 0x0 16.--20. 1. "CSWWAIT,Normal Write Cycle Wait Select" newline bitfld.long 0x0 8.--10. "CSPRWAIT,Page Read Cycle Wait Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "CSPWWAIT,Page Write Cycle Wait Select" "0,1,2,3,4,5,6,7" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x8)++0x3 line.long 0x0 "CS$1WCR2,CS%s Wait Control Register 2 (n = 0 to 7)" bitfld.long 0x0 28.--30. "CSON,CS Assert Wait Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "WDON,Write Data Output Wait Select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "WRON,WR Assert Wait Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "RDON,RD Assert Wait Select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--13. "AWAIT,Address Cycle Wait Select" "0,1,2,3" bitfld.long 0x0 8.--10. "WDOFF,Write Data Output Extension Cycle Select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "CSWOFF,Write Access CS Extension Cycle Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "CSROFF,Read Access CS Extension Cycle Select" "0,1,2,3,4,5,6,7" repeat.end group.word 0x802++0x1 line.word 0x0 "CS0CR,CS0 Control Register" bitfld.word 0x0 12. "MPXEN,Address/Data Multiplexed I/O Interface Select" "0: Separate bus interface is selected for area n.,1: Address/data multiplexed I/O interface is.." bitfld.word 0x0 8. "EMODE,Endian Mode" "0: Little endian,1: Big endian" newline bitfld.word 0x0 4.--5. "BSIZE,External Bus Width Select" "0: Setting prohibited,?,?,?" bitfld.word 0x0 0. "EXENB,Operation Enable" "0: Disable operation,1: Enable operation" repeat 8. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0x80A)++0x1 line.word 0x0 "CS$1REC,CS%s Recovery Cycle Register (n = 0 to 7)" hexmask.word.byte 0x0 8.--11. 1. "WRCV,Write Recovery" hexmask.word.byte 0x0 0.--3. 1. "RRCV,Read Recovery" repeat.end repeat 7. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0x812)++0x1 line.word 0x0 "CS$1CR,CS%s Control Register" bitfld.word 0x0 12. "MPXEN,Address/Data Multiplexed I/O Interface Select" "0: Separate bus interface is selected for area n.,1: Address/data multiplexed I/O interface is.." bitfld.word 0x0 8. "EMODE,Endian Mode" "0: Little endian,1: Big endian" newline bitfld.word 0x0 4.--5. "BSIZE,External Bus Width Select" "0: Setting prohibited,?,?,?" bitfld.word 0x0 0. "EXENB,Operation Enable" "0: Disable operation,1: Enable operation" repeat.end group.word 0x880++0x1 line.word 0x0 "CSRECEN,CS Recovery Cycle Insertion Enable Register" bitfld.word 0x0 15. "RCVENM7,Multiplexed Bus Recovery Cycle Insertion Enable 7" "0: Disabled,1: Enabled" bitfld.word 0x0 14. "RCVENM6,Multiplexed Bus Recovery Cycle Insertion Enable 6" "0: Disabled,1: Enabled" newline bitfld.word 0x0 13. "RCVENM5,Multiplexed Bus Recovery Cycle Insertion Enable 5" "0: Disabled,1: Enabled" bitfld.word 0x0 12. "RCVENM4,Multiplexed Bus Recovery Cycle Insertion Enable 4" "0: Disabled,1: Enabled" newline bitfld.word 0x0 11. "RCVENM3,Multiplexed Bus Recovery Cycle Insertion Enable 3" "0: Disabled,1: Enabled" bitfld.word 0x0 10. "RCVENM2,Multiplexed Bus Recovery Cycle Insertion Enable 2" "0: Disabled,1: Enabled" newline bitfld.word 0x0 9. "RCVENM1,Multiplexed Bus Recovery Cycle Insertion Enable 1" "0: Disabled,1: Enabled" bitfld.word 0x0 8. "RCVENM0,Multiplexed Bus Recovery Cycle Insertion Enable 0" "0: Disabled,1: Enabled" newline bitfld.word 0x0 7. "RCVEN7,Separate Bus Recovery Cycle Insertion Enable 7" "0: Disabled,1: Enabled" bitfld.word 0x0 6. "RCVEN6,Separate Bus Recovery Cycle Insertion Enable 6" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "RCVEN5,Separate Bus Recovery Cycle Insertion Enable 5" "0: Disabled,1: Enabled" bitfld.word 0x0 4. "RCVEN4,Separate Bus Recovery Cycle Insertion Enable 4" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "RCVEN3,Separate Bus Recovery Cycle Insertion Enable 3" "0: Disabled,1: Enabled" bitfld.word 0x0 2. "RCVEN2,Separate Bus Recovery Cycle Insertion Enable 2" "0: Disabled,1: Enabled" newline bitfld.word 0x0 1. "RCVEN1,Separate Bus Recovery Cycle Insertion Enable 1" "0: Disabled,1: Enabled" bitfld.word 0x0 0. "RCVEN0,Separate Bus Recovery Cycle Insertion Enable 0" "0: Disabled,1: Enabled" group.byte 0xC00++0x2 line.byte 0x0 "SDCCR,SDC Control Register" bitfld.byte 0x0 4.--5. "BSIZE,SDRAM Bus Width Select" "0: Setting prohibited,?,?,?" bitfld.byte 0x0 0. "EXENB,Operation Enable" "0: Disable,1: Enable" line.byte 0x1 "SDCMOD,SDC Mode Register" bitfld.byte 0x1 0. "EMODE,Endian Mode" "0: Endian order of SDRAM address space is the same..,1: Endian order of SDRAM address space is not the.." line.byte 0x2 "SDAMOD,SDRAM Access Mode Register" bitfld.byte 0x2 0. "BE,Continuous Access Enable" "0: Continuous access is disabled,1: Continuous access is enabled" group.byte 0xC10++0x0 line.byte 0x0 "SDSELF,SDRAM Self-Refresh Control Register" bitfld.byte 0x0 0. "SFEN,SDRAM Self-Refresh Enable" "0: Disable,1: Enable" group.word 0xC14++0x1 line.word 0x0 "SDRFCR,SDRAM Refresh Control Register" hexmask.word.byte 0x0 12.--15. 1. "REFW,Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count Setting" hexmask.word 0x0 0.--11. 1. "RFC,Auto-Refresh Request Interval Setting" group.byte 0xC16++0x0 line.byte 0x0 "SDRFEN,SDRAM Auto-Refresh Control Register" bitfld.byte 0x0 0. "RFEN,Auto-Refresh Operation Enable" "0: Disable,1: Enable" group.byte 0xC20++0x0 line.byte 0x0 "SDICR,SDRAM Initialization Sequence Control Register" bitfld.byte 0x0 0. "INIRQ,Initialization Sequence Start" "0: Invalid,1: Start initialization sequence" group.word 0xC24++0x1 line.word 0x0 "SDIR,SDRAM Initialization Register" bitfld.word 0x0 8.--10. "PRC,Initialization Precharge Cycle Count" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 4.--7. 1. "ARFC,Initialization Auto-Refresh Count" newline hexmask.word.byte 0x0 0.--3. 1. "ARFI,Initialization Auto-Refresh Interval" group.byte 0xC40++0x0 line.byte 0x0 "SDADR,SDRAM Address Register" bitfld.byte 0x0 0.--1. "MXC,Address Multiplex Select" "0: 8-bit shift,1: 9-bit shift,?,?" group.long 0xC44++0x3 line.long 0x0 "SDTR,SDRAM Timing Register" bitfld.long 0x0 16.--18. "RAI,Row Active Interval" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "RCD,Row Column Latency" "0: 1 cycle,1: 2 cycles,?,?" newline bitfld.long 0x0 9.--11. "RP,Row Precharge Interval" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "WR,Write Recovery Interval" "0: 1 cycle,1: 2 cycles" newline bitfld.long 0x0 0.--2. "CL,SDRAMC Column Latency" "0,1,2,3,4,5,6,7" group.word 0xC48++0x1 line.word 0x0 "SDMOD,SDRAM Mode Register" hexmask.word 0x0 0.--14. 1. "MR,Mode Register Setting" rgroup.byte 0xC50++0x0 line.byte 0x0 "SDSR,SDRAM Status Register" bitfld.byte 0x0 4. "SRFST,Self-Refresh Transition/Recovery Status" "0: Transition/recovery not in progress,1: Transition/recovery in progress" bitfld.byte 0x0 3. "INIST,Initialization Status" "0: Initialization sequence not in progress,1: Initialization sequence in progress" newline bitfld.byte 0x0 0. "MRSST,Mode Register Setting Status" "0: Mode register setting not in progress,1: Mode register setting in progress" group.word 0x1000++0x1 line.word 0x0 "BUSOAD,BUS Operation After Detection Register" bitfld.word 0x0 2. "BWERROAD,Bufferable write error operation after detection" "0,1" bitfld.word 0x0 1. "SLERROAD,Slave bus error operation after detection" "0,1" newline bitfld.word 0x0 0. "ILERROAD,Illegal address access error operation after detection" "0,1" group.word 0x1004++0x1 line.word 0x0 "BUSOADPT,BUS Operation After Detection Protect Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: BUSOAD register writing is possible.,1: BUSOAD register writing is protected. Read is.." group.long 0x1100++0x3 line.long 0x0 "BUSMABT,Bus Master Arbitration Control Register" bitfld.long 0x0 0. "ARBS,Arbitration Select for GDSSBI" "0: Fixed priority,1: Round-robin" group.long 0x1200++0x3 line.long 0x0 "BUSSABT1FHBI,Bus Slave Arbitration Control Register 1(x = FHBI. S0BI. S1BI)" bitfld.long 0x0 0.--1. "ARBS,Arbitration Select for " "0: Fixed priority,1: Setting prohibited,?,?" group.long 0x1210++0x3 line.long 0x0 "BUSSABT0FLBI,Bus Slave Arbitration Control Register 0" bitfld.long 0x0 0. "ARBS,Arbitration Select for " "0: Fixed priority,1: Round-robin" group.long 0x1218++0x3 line.long 0x0 "BUSSABT1S0BI,Bus Slave Arbitration Control Register 1(x = FHBI. S0BI. S1BI)" bitfld.long 0x0 0.--1. "ARBS,Arbitration Select for " "0: Fixed priority,1: Setting prohibited,?,?" group.long 0x1220++0x3 line.long 0x0 "BUSSABT1S1BI,Bus Slave Arbitration Control Register 1(x = FHBI. S0BI. S1BI)" bitfld.long 0x0 0.--1. "ARBS,Arbitration Select for " "0: Fixed priority,1: Setting prohibited,?,?" group.long 0x1248++0x3 line.long 0x0 "BUSSABT0STBYSBI,Bus Slave Arbitration Control Register 0" bitfld.long 0x0 0. "ARBS,Arbitration Select for " "0: Fixed priority,1: Round-robin" group.long 0x1250++0x3 line.long 0x0 "BUSSABT0ECBI,Bus Slave Arbitration Control Register 0" bitfld.long 0x0 0. "ARBS,Arbitration Select for " "0: Fixed priority,1: Round-robin" group.long 0x1258++0x3 line.long 0x0 "BUSSABT0EOBI,Bus Slave Arbitration Control Register 0" bitfld.long 0x0 0. "ARBS,Arbitration Select for " "0: Fixed priority,1: Round-robin" group.long 0x1260++0x3 line.long 0x0 "BUSSABT0PBBI,Bus Slave Arbitration Control Register 0" bitfld.long 0x0 0. "ARBS,Arbitration Select for " "0: Fixed priority,1: Round-robin" group.long 0x1268++0x3 line.long 0x0 "BUSSABT0PABI,Bus Slave Arbitration Control Register 0" bitfld.long 0x0 0. "ARBS,Arbitration Select for " "0: Fixed priority,1: Round-robin" group.long 0x1270++0x3 line.long 0x0 "BUSSABT0PIBI,Bus Slave Arbitration Control Register 0" bitfld.long 0x0 0. "ARBS,Arbitration Select for " "0: Fixed priority,1: Round-robin" group.long 0x1278++0x3 line.long 0x0 "BUSSABT0PSBI,Bus Slave Arbitration Control Register 0" bitfld.long 0x0 0. "ARBS,Arbitration Select for " "0: Fixed priority,1: Round-robin" group.long 0x1300++0x3 line.long 0x0 "BUSDIVBYP,Bus Divider Bypass Register" bitfld.long 0x0 16. "CPU0SBPE,Divider for CPUSAHBI bypass enable" "0: Disable,1: Enable" bitfld.long 0x0 3. "GDSSBPE,Divider for GDSSBI bypass enable" "0: Disable,1: Enable" rgroup.long 0x1800++0x3 line.long 0x0 "BUS4ERRADD,BUS Error Address Register (n = 4)" hexmask.long 0x0 0.--31. 1. "BERAD,Bus Error Address" rgroup.byte 0x1804++0x0 line.byte 0x0 "BUS4ERRRW,BUS Error Read Write (n = 4)" bitfld.byte 0x0 0. "RWSTAT,Error access Read/Write Status" "0: Read access,1: Write access" repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.long ($2+0x1820)++0x3 line.long 0x0 "BUS$1ERRADD,BUS Error Address Register (n = 6 to 9)" hexmask.long 0x0 0.--31. 1. "BERAD,Bus Error Address" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x1824)++0x0 line.byte 0x0 "BUS$1ERRRW,BUS Error Read Write (n = 6 to 9)" bitfld.byte 0x0 0. "RWSTAT,Error access Read/Write Status" "0: Read access,1: Write access" repeat.end rgroup.long 0x1900++0x3 line.long 0x0 "BMSA4ERRADD,Bus Master Security Attribution Unit Error Address" hexmask.long 0x0 0.--31. 1. "MSERAD,Bus Master Security Attribution Unit Error Address" rgroup.byte 0x1904++0x0 line.byte 0x0 "BMSA4ERRRW,BUS Master Security Attribution Unit Error Read Write (n = 4)" bitfld.byte 0x0 0. "MSARWSTAT,Master Security Attribution Unit error access Read/Write Status" "0: Read access,1: Write access" repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.long ($2+0x1920)++0x3 line.long 0x0 "BMSA$1ERRADD,Bus Master Security Attribution Unit Error Address" hexmask.long 0x0 0.--31. 1. "MSERAD,Bus Master Security Attribution Unit Error Address" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x1924)++0x0 line.byte 0x0 "BMSA$1ERRRW,BUS Master Security Attribution Unit Error Read Write (n = 6 to 9)" bitfld.byte 0x0 0. "MSARWSTAT,Master Security Attribution Unit error access Read/Write Status" "0: Read access,1: Write access" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x1A00)++0x0 line.byte 0x0 "BUS$1ERRSTAT,BUS Error Status Register" bitfld.byte 0x0 5. "MSERRSTAT,Master Security Attribution Unit Error Status" "0: No error occurred,1: Error occurred" bitfld.byte 0x0 4. "ILERRSTAT,Illegal Address Access Error Status" "0: No error occurred,1: Error occurred" newline bitfld.byte 0x0 3. "MMERRSTAT,Master MPU Error Status" "0: No error occurred,1: Error occurred" bitfld.byte 0x0 0. "SLERRSTAT,Slave Bus Error Status" "0: No error occurred,1: Error occurred" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) group.byte ($2+0x1A08)++0x0 line.byte 0x0 "BUS$1ERRCLR,BUS Error Clear Register" bitfld.byte 0x0 5. "MSERRCLR,Master Security Attribution Unit Error Clear" "0,1" bitfld.byte 0x0 4. "ILERRCLR,Illegal Address Access Error Clear" "0,1" newline bitfld.byte 0x0 3. "MMERRCLR,Master MPU Error Clear" "0,1" bitfld.byte 0x0 0. "SLERRCLR,Slave Bus Error Clear" "0,1" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x1A50)++0x0 line.byte 0x0 "BUS$1ERRSTAT,BUS Error Status Register" bitfld.byte 0x0 5. "MSERRSTAT,Master Security Attribution Unit Error Status" "0: No error occurred,1: Error occurred" bitfld.byte 0x0 4. "ILERRSTAT,Illegal Address Access Error Status" "0: No error occurred,1: Error occurred" newline bitfld.byte 0x0 3. "MMERRSTAT,Master MPU Error Status" "0: No error occurred,1: Error occurred" bitfld.byte 0x0 0. "SLERRSTAT,Slave Bus Error Status" "0: No error occurred,1: Error occurred" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) group.byte ($2+0x1A58)++0x0 line.byte 0x0 "BUS$1ERRCLR,BUS Error Clear Register" bitfld.byte 0x0 5. "MSERRCLR,Master Security Attribution Unit Error Clear" "0,1" bitfld.byte 0x0 4. "ILERRCLR,Illegal Address Access Error Clear" "0,1" newline bitfld.byte 0x0 3. "MMERRCLR,Master MPU Error Clear" "0,1" bitfld.byte 0x0 0. "SLERRCLR,Slave Bus Error Clear" "0,1" repeat.end rgroup.long 0x1B00++0x3 line.long 0x0 "MBWERRSTAT,Master Bufferable Write Error Status Register" bitfld.long 0x0 23. "MBWERR23,Master Bufferable Write Error" "0: No bufferable write error in Master #23,1: Bufferable write error occurs in Master #23" bitfld.long 0x0 20. "MBWERR20,Master Bufferable Write Error" "0: No bufferable write error in Master #20,1: Bufferable write error occurs in Master #20" newline bitfld.long 0x0 19. "MBWERR19,Master Bufferable Write Error" "0: No bufferable write error in Master #19,1: Bufferable write error occurs in Master #19" bitfld.long 0x0 18. "MBWERR18,Master Bufferable Write Error" "0: No bufferable write error in Master #18,1: Bufferable write error occurs in Master #18" newline bitfld.long 0x0 17. "MBWERR17,Master Bufferable Write Error" "0: No bufferable write error in Master #17,1: Bufferable write error occurs in Master #17" bitfld.long 0x0 8. "MBWERR8,Master Bufferable Write Error" "0: No bufferable write error in Master #8,1: Bufferable write error occurs in Master #8" newline bitfld.long 0x0 1. "MBWERR1,Master Bufferable Write Error" "0: No bufferable write error in Master #1,1: Bufferable write error occurs in Master #1" bitfld.long 0x0 0. "MBWERR0,Master Bufferable Write Error" "0: No bufferable write error in Master #0,1: Bufferable write error occurs in Master #0" group.long 0x1B08++0x3 line.long 0x0 "MBWERRCLR,Master Bufferable Write Error Clear Register" bitfld.long 0x0 23. "MBWECLR23,Master Bufferable Write Error Clear" "0,1" bitfld.long 0x0 20. "MBWECLR20,Master Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 19. "MBWECLR19,Master Bufferable Write Error Clear" "0,1" bitfld.long 0x0 18. "MBWECLR18,Master Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 17. "MBWECLR17,Master Bufferable Write Error Clear" "0,1" bitfld.long 0x0 8. "MBWECLR8,Master Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 1. "MBWECLR1,Master Bufferable Write Error Clear" "0,1" bitfld.long 0x0 0. "MBWECLR0,Master Bufferable Write Error Clear" "0,1" rgroup.long 0x1B20++0x3 line.long 0x0 "SBWERRSTAT,Slave Bufferable Write Error Status Register" bitfld.long 0x0 12. "SBWERR12,Slave Bufferable Write Error" "0: No bufferable write error in Slave #12,1: Bufferable write error occurs in Slave #12" bitfld.long 0x0 11. "SBWERR11,Slave Bufferable Write Error" "0: No bufferable write error in Slave #11,1: Bufferable write error occurs in Slave #11" newline bitfld.long 0x0 10. "SBWERR10,Slave Bufferable Write Error" "0: No bufferable write error in Slave #10,1: Bufferable write error occurs in Slave #10" bitfld.long 0x0 9. "SBWERR9,Slave Bufferable Write Error" "0: No bufferable write error in Slave #9,1: Bufferable write error occurs in Slave #9" newline bitfld.long 0x0 8. "SBWERR8,Slave Bufferable Write Error" "0: No bufferable write error in Slave #8,1: Bufferable write error occurs in Slave #8" bitfld.long 0x0 7. "SBWERR7,Slave Bufferable Write Error" "0: No bufferable write error in Slave #7,1: Bufferable write error occurs in Slave #7" newline bitfld.long 0x0 6. "SBWERR6,Slave Bufferable Write Error" "0: No bufferable write error in Slave #6,1: Bufferable write error occurs in Slave #6" bitfld.long 0x0 5. "SBWERR5,Slave Bufferable Write Error" "0: No bufferable write error in Slave #5,1: Bufferable write error occurs in Slave #5" newline bitfld.long 0x0 4. "SBWERR4,Slave Bufferable Write Error" "0: No bufferable write error in Slave #4,1: Bufferable write error occurs in Slave #4" bitfld.long 0x0 3. "SBWERR3,Slave Bufferable Write Error" "0: No bufferable write error in Slave #3,1: Bufferable write error occurs in Slave #3" newline bitfld.long 0x0 2. "SBWERR2,Slave Bufferable Write Error" "0: No bufferable write error in Slave #2,1: Bufferable write error occurs in Slave #2" bitfld.long 0x0 1. "SBWERR1,Slave Bufferable Write Error" "0: No bufferable write error in Slave #1,1: Bufferable write error occurs in Slave #1" newline bitfld.long 0x0 0. "SBWERR0,Slave Bufferable Write Error" "0: No bufferable write error in Slave #0,1: Bufferable write error occurs in Slave #0" group.long 0x1B28++0x3 line.long 0x0 "SBWERRCLR,Slave Bufferable Write Error Clear Register" bitfld.long 0x0 12. "SBWECLR12,Slave Bufferable Write Error Clear" "0,1" bitfld.long 0x0 11. "SBWECLR11,Slave Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 10. "SBWECLR10,Slave Bufferable Write Error Clear" "0,1" bitfld.long 0x0 9. "SBWECLR9,Slave Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 8. "SBWECLR8,Slave Bufferable Write Error Clear" "0,1" bitfld.long 0x0 7. "SBWECLR7,Slave Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 6. "SBWECLR6,Slave Bufferable Write Error Clear" "0,1" bitfld.long 0x0 5. "SBWECLR5,Slave Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 4. "SBWECLR4,Slave Bufferable Write Error Clear" "0,1" bitfld.long 0x0 3. "SBWECLR3,Slave Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 2. "SBWECLR2,Slave Bufferable Write Error Clear" "0,1" bitfld.long 0x0 1. "SBWECLR1,Slave Bufferable Write Error Clear" "0,1" newline bitfld.long 0x0 0. "SBWECLR0,Slave Bufferable Write Error Clear" "0,1" tree.end tree.end tree "CAC (Clock Frequency Accuracy Measurement Circuit)" base ad:0x0 tree "CAC" base ad:0x40202400 group.byte 0x0++0x3 line.byte 0x0 "CACR0,CAC Control Register 0" bitfld.byte 0x0 0. "CFME,Clock Frequency Measurement Enable" "0: Disable,1: Enable" line.byte 0x1 "CACR1,CAC Control Register 1" bitfld.byte 0x1 6.--7. "EDGES,Valid Edge Select" "0: Rising edge,1: Falling edge,?,?" bitfld.byte 0x1 4.--5. "TCSS,Timer Count Clock Source Select" "0: No division,1: x 1/4 clock,?,?" newline bitfld.byte 0x1 1.--3. "FMCS,Measurement Target Clock Select" "0: Main clock oscillator (CACMCLK),1: Sub-clock oscillator (CACSCLK),?,?,?,?,?,?" bitfld.byte 0x1 0. "CACREFE,CACREF Pin Input Enable" "0: Disable,1: Enable" line.byte 0x2 "CACR2,CAC Control Register 2" bitfld.byte 0x2 6.--7. "DFS,Digital Filter Select" "0: Disable digital filtering,1: Use sampling clock for the digital filter as the..,?,?" bitfld.byte 0x2 4.--5. "RCDS,Measurement Reference Clock Frequency Division Ratio Select" "0: x 1/32 clock,1: x 1/128 clock,?,?" newline bitfld.byte 0x2 1.--3. "RSCS,Measurement Reference Clock Select" "0: Main clock oscillator (CACMCLK),1: Sub-clock oscillator (CACSCLK),?,?,?,?,?,?" bitfld.byte 0x2 0. "RPS,Reference Signal Select" "0: CACREF pin input,1: Internal clock (internally generated signal)" line.byte 0x3 "CAICR,CAC Interrupt Control Register" bitfld.byte 0x3 6. "OVFFCL,OVFF Clear" "0: No effect,1: The CASTR.OVFF flag is cleared." bitfld.byte 0x3 5. "MENDFCL,MENDF Clear" "0: No effect,1: The CASTR.MENDF flag is cleared" newline bitfld.byte 0x3 4. "FERRFCL,FERRF Clear" "0: No effect,1: The CASTR.FERRF flag is cleared" bitfld.byte 0x3 2. "OVFIE,Overflow Interrupt Request Enable" "0: Disable,1: Enable" newline bitfld.byte 0x3 1. "MENDIE,Measurement End Interrupt Request Enable" "0: Disable,1: Enable" bitfld.byte 0x3 0. "FERRIE,Frequency Error Interrupt Request Enable" "0: Disable,1: Enable" rgroup.byte 0x4++0x0 line.byte 0x0 "CASTR,CAC Status Register" bitfld.byte 0x0 2. "OVFF,Overflow Flag" "0: Counter has not overflowed,1: Counter overflowed" bitfld.byte 0x0 1. "MENDF,Measurement End Flag" "0: Measurement is in progress,1: Measurement ended" newline bitfld.byte 0x0 0. "FERRF,Frequency Error Flag" "0: Clock frequency is within the allowable range,1: Clock frequency has deviated beyond the.." group.word 0x6++0x3 line.word 0x0 "CAULVR,CAC Upper-Limit Value Setting Register" line.word 0x2 "CALLVR,CAC Lower-Limit Value Setting Register" rgroup.word 0xA++0x1 line.word 0x0 "CACNTBR,CAC Counter Buffer Register" tree.end tree "CAC_NS" base ad:0x50202400 group.byte 0x0++0x3 line.byte 0x0 "CACR0,CAC Control Register 0" bitfld.byte 0x0 0. "CFME,Clock Frequency Measurement Enable" "0: Disable,1: Enable" line.byte 0x1 "CACR1,CAC Control Register 1" bitfld.byte 0x1 6.--7. "EDGES,Valid Edge Select" "0: Rising edge,1: Falling edge,?,?" bitfld.byte 0x1 4.--5. "TCSS,Timer Count Clock Source Select" "0: No division,1: x 1/4 clock,?,?" newline bitfld.byte 0x1 1.--3. "FMCS,Measurement Target Clock Select" "0: Main clock oscillator (CACMCLK),1: Sub-clock oscillator (CACSCLK),?,?,?,?,?,?" bitfld.byte 0x1 0. "CACREFE,CACREF Pin Input Enable" "0: Disable,1: Enable" line.byte 0x2 "CACR2,CAC Control Register 2" bitfld.byte 0x2 6.--7. "DFS,Digital Filter Select" "0: Disable digital filtering,1: Use sampling clock for the digital filter as the..,?,?" bitfld.byte 0x2 4.--5. "RCDS,Measurement Reference Clock Frequency Division Ratio Select" "0: x 1/32 clock,1: x 1/128 clock,?,?" newline bitfld.byte 0x2 1.--3. "RSCS,Measurement Reference Clock Select" "0: Main clock oscillator (CACMCLK),1: Sub-clock oscillator (CACSCLK),?,?,?,?,?,?" bitfld.byte 0x2 0. "RPS,Reference Signal Select" "0: CACREF pin input,1: Internal clock (internally generated signal)" line.byte 0x3 "CAICR,CAC Interrupt Control Register" bitfld.byte 0x3 6. "OVFFCL,OVFF Clear" "0: No effect,1: The CASTR.OVFF flag is cleared." bitfld.byte 0x3 5. "MENDFCL,MENDF Clear" "0: No effect,1: The CASTR.MENDF flag is cleared" newline bitfld.byte 0x3 4. "FERRFCL,FERRF Clear" "0: No effect,1: The CASTR.FERRF flag is cleared" bitfld.byte 0x3 2. "OVFIE,Overflow Interrupt Request Enable" "0: Disable,1: Enable" newline bitfld.byte 0x3 1. "MENDIE,Measurement End Interrupt Request Enable" "0: Disable,1: Enable" bitfld.byte 0x3 0. "FERRIE,Frequency Error Interrupt Request Enable" "0: Disable,1: Enable" rgroup.byte 0x4++0x0 line.byte 0x0 "CASTR,CAC Status Register" bitfld.byte 0x0 2. "OVFF,Overflow Flag" "0: Counter has not overflowed,1: Counter overflowed" bitfld.byte 0x0 1. "MENDF,Measurement End Flag" "0: Measurement is in progress,1: Measurement ended" newline bitfld.byte 0x0 0. "FERRF,Frequency Error Flag" "0: Clock frequency is within the allowable range,1: Clock frequency has deviated beyond the.." group.word 0x6++0x3 line.word 0x0 "CAULVR,CAC Upper-Limit Value Setting Register" line.word 0x2 "CALLVR,CAC Lower-Limit Value Setting Register" rgroup.word 0xA++0x1 line.word 0x0 "CACNTBR,CAC Counter Buffer Register" tree.end tree.end tree "CANFD (CAN with Flexible Data-rate)" base ad:0x0 tree "CANFD0" base ad:0x40380000 group.long 0x0++0xF line.long 0x0 "CFDC0NCFG,Nominal Bitrate Configuration Register" hexmask.long.byte 0x0 25.--31. 1. "NTSEG2,Timing Segment 2" hexmask.long.byte 0x0 17.--24. 1. "NTSEG1,Timing Segment 1" newline hexmask.long.byte 0x0 10.--16. 1. "NSJW,Resynchronization Jump Width" hexmask.long.word 0x0 0.--9. 1. "NBRP,Channel Nominal Baud Rate Prescaler" line.long 0x4 "CFDC0CTR,Control Register" bitfld.long 0x4 31. "ROM,Restricted Operation Mode" "0: Restricted operation mode disabled,1: Restricted operation mode enabled" bitfld.long 0x4 30. "BFT,Bit Flip Test" "0: First data bit of reception stream not inverted,1: First data bit of reception stream inverted" newline bitfld.long 0x4 25.--26. "CTMS,Channel Test Mode Select" "0: Basic test mode,1: Listen-only mode,?,?" bitfld.long 0x4 24. "CTME,Channel Test Mode Enable" "0: Channel test mode disabled,1: Channel test mode enabled" newline bitfld.long 0x4 23. "ERRD,Channel Error Display" "0: Only the first set of error codes displayed,1: Accumulated error codes displayed" bitfld.long 0x4 21.--22. "BOM,Channel Bus-Off Mode" "0: Normal mode (comply with ISO 11898-1),1: Entry to Halt mode automatically at bus-off start,?,?" newline bitfld.long 0x4 19. "TDCVFIE,Transceiver Delay Compensation Violation Interrupt Enable" "0: Transceiver delay compensation violation..,1: Transceiver delay compensation violation.." bitfld.long 0x4 18. "SOCOIE,Successful Occurrence Counter Overflow Interrupt Enable" "0: Successful occurrence counter overflow interrupt..,1: Successful occurrence counter overflow interrupt.." newline bitfld.long 0x4 17. "EOCOIE,Error Occurrence Counter Overflow Interrupt Enable" "0: Error occurrence counter overflow interrupt..,1: Error occurrence counter overflow interrupt.." bitfld.long 0x4 16. "TAIE,Transmission Abort Interrupt Enable" "0: TX abort interrupt disabled,1: TX abort interrupt enabled" newline bitfld.long 0x4 15. "ALIE,Arbitration Lost Interrupt Enable" "0: Arbitration lost interrupt disabled,1: Arbitration lost interrupt enabled" bitfld.long 0x4 14. "BLIE,Bus Lock Interrupt Enable" "0: Bus lock interrupt disabled,1: Bus lock interrupt enabled" newline bitfld.long 0x4 13. "OLIE,Overload Interrupt Enable" "0: Overload interrupt disabled,1: Overload interrupt enabled" bitfld.long 0x4 12. "BORIE,Bus-Off Recovery Interrupt Enable" "0: Bus-off recovery interrupt disabled,1: Bus-off recovery interrupt enabled" newline bitfld.long 0x4 11. "BOEIE,Bus-Off Entry Interrupt Enable" "0: Bus-off entry interrupt disabled,1: Bus-off entry interrupt enabled" bitfld.long 0x4 10. "EPIE,Error Passive Interrupt Enable" "0: Error passive interrupt disabled,1: Error passive interrupt enabled" newline bitfld.long 0x4 9. "EWIE,Error Warning Interrupt Enable" "0: Error warning interrupt disabled,1: Error warning interrupt enabled" bitfld.long 0x4 8. "BEIE,Bus Error Interrupt Enable" "0: Bus error interrupt disabled,1: Bus error interrupt enabled" newline bitfld.long 0x4 3. "RTBO,Return from Bus-Off" "0: Channel is not forced to return from bus-off,1: Channel is forced to return from bus-off" bitfld.long 0x4 2. "CSLPR,Channel Sleep Request" "0: Channel sleep request disabled,1: Channel sleep request enabled" newline bitfld.long 0x4 0.--1. "CHMDC,Channel Mode Control" "0: Channel operation mode request,1: Channel reset request,?,?" line.long 0x8 "CFDC0STS,Status Register" hexmask.long.byte 0x8 24.--31. 1. "TEC,Transmission Error Count" hexmask.long.byte 0x8 16.--23. 1. "REC,Reception Error Count" newline bitfld.long 0x8 8. "ESIF,Error State Indication Flag" "0: No CANFD message has been received when the ESI..,1: At least one CANFD message was received when the.." rbitfld.long 0x8 7. "COMSTS,Channel Communication Status" "0: Channel is not ready for communication,1: Channel is ready for communication" newline rbitfld.long 0x8 6. "RECSTS,Channel Receive Status" "0: Channel is not receiving,1: Channel is receiving" rbitfld.long 0x8 5. "TRMSTS,Channel Transmit Status" "0: Channel is not transmitting,1: Channel is transmitting" newline rbitfld.long 0x8 4. "BOSTS,Channel Bus-Off Status" "0: Channel not in bus-off state,1: Channel in bus-off state" rbitfld.long 0x8 3. "EPSTS,Channel Error Passive Status" "0: Channel not in error passive state,1: Channel in error passive state" newline rbitfld.long 0x8 2. "CSLPSTS,Channel Sleep Status" "0: Channel not in Sleep mode,1: Channel in Sleep mode" rbitfld.long 0x8 1. "CHLTSTS,Channel Halt Status" "0: Channel not in Halt mode,1: Channel in Halt mode" newline rbitfld.long 0x8 0. "CRSTSTS,Channel Reset Status" "0: Channel not in Reset mode,1: Channel in Reset mode" line.long 0xC "CFDC0ERFL,Error Flag Register" hexmask.long.word 0xC 16.--30. 1. "CRCREG,CRC Register value" bitfld.long 0xC 14. "ADERR,Acknowledge Delimiter Error" "0: Channel acknowledge delimiter error not detected,1: Channel acknowledge delimiter error detected" newline bitfld.long 0xC 13. "B0ERR,Bit 0 Error" "0: Channel bit 0 error not detected,1: Channel bit 0 error detected" bitfld.long 0xC 12. "B1ERR,Bit 1 Error" "0: Channel bit 1 error not detected,1: Channel bit 1 error detected" newline bitfld.long 0xC 11. "CERR,CRC Error" "0: Channel CRC error not detected,1: Channel CRC error detected" bitfld.long 0xC 10. "AERR,Acknowledge Error" "0: Channel acknowledge error not detected,1: Channel acknowledge error detected" newline bitfld.long 0xC 9. "FERR,Form Error" "0: Channel form error not detected,1: Channel form error detected" bitfld.long 0xC 8. "SERR,Stuff Error" "0: Channel stuff error not detected,1: Channel stuff error detected" newline bitfld.long 0xC 7. "ALF,Arbitration Lost Flag" "0: Channel arbitration lost not detected,1: Channel arbitration lost detected" bitfld.long 0xC 6. "BLF,Bus Lock Flag" "0: Channel bus lock not detected,1: Channel bus lock detected" newline bitfld.long 0xC 5. "OVLF,Overload Flag" "0: Channel overload not detected,1: Channel overload detected" bitfld.long 0xC 4. "BORF,Bus-Off Recovery Flag" "0: Channel bus-off recovery not detected,1: Channel bus-off recovery detected" newline bitfld.long 0xC 3. "BOEF,Bus-Off Entry Flag" "0: Channel bus-off entry not detected,1: Channel bus-off entry detected" bitfld.long 0xC 2. "EPF,Error Passive Flag" "0: Channel error passive not detected,1: Channel error passive detected" newline bitfld.long 0xC 1. "EWF,Error Warning Flag" "0: Channel error warning not detected,1: Channel error warning detected" bitfld.long 0xC 0. "BEF,Bus Error Flag" "0: Channel bus error not detected,1: Channel bus error detected" group.long 0x14++0x7 line.long 0x0 "CFDGCFG,Global Configuration Register" hexmask.long.word 0x0 16.--31. 1. "ITRCP,Interval Timer Reference Clock Prescaler" bitfld.long 0x0 12. "TSSS,Timestamp Source Select" "0: Source clock for timestamp counter is peripheral..,1: Source clock for timestamp counter is bit time.." newline hexmask.long.byte 0x0 8.--11. 1. "TSP,Timestamp Prescaler" bitfld.long 0x0 5. "CMPOC,CANFD Message Payload Overflow Configuration" "0: Message is rejected,1: Message payload is cut to fit to configured.." newline bitfld.long 0x0 4. "DCS,Data Link Controller Clock Select" "0: CANFD core clock (CANFDCLK),1: External oscillator clock (CANMCLK)" bitfld.long 0x0 3. "MME,Mirror Mode Enable" "0: Mirror mode disabled,1: Mirror mode enabled" newline bitfld.long 0x0 2. "DRE,DLC Replacement Enable" "0: DLC replacement disabled,1: DLC replacement enabled" bitfld.long 0x0 1. "DCE,DLC Check Enable" "0: DLC check disabled,1: DLC check enabled" newline bitfld.long 0x0 0. "TPRI,Transmission Priority" "0: ID priority,1: Message buffer number priority" line.long 0x4 "CFDGCTR,Global Control Register" bitfld.long 0x4 16. "TSRST,Timestamp Reset" "0: Timestamp not reset,1: Timestamp reset" bitfld.long 0x4 11. "CMPOFIE,CANFD Message Payload Overflow Flag Interrupt Enable" "0: CANFD message payload overflow flag interrupt..,1: CANFD message payload overflow flag interrupt.." newline bitfld.long 0x4 10. "THLEIE,TX History List Entry Lost Interrupt Enable" "0: TX history list entry lost interrupt disabled,1: TX history list entry lost interrupt enabled" bitfld.long 0x4 9. "MEIE,Message Lost Error Interrupt Enable" "0: Message lost error interrupt disabled,1: Message lost error interrupt enabled" newline bitfld.long 0x4 8. "DEIE,DLC Check Interrupt Enable" "0: DLC check interrupt disabled,1: DLC check interrupt enabled" bitfld.long 0x4 2. "GSLPR,Global Sleep Request" "0: Global sleep request disabled,1: Global sleep request enabled" newline bitfld.long 0x4 0.--1. "GMDC,Global Mode Control" "0: Global operation mode request,1: Global reset mode request,?,?" rgroup.long 0x1C++0x3 line.long 0x0 "CFDGSTS,Global Status Register" bitfld.long 0x0 3. "GRAMINIT,Global RAM Initialization" "0: RAM initialization is complete,1: RAM initialization is ongoing" bitfld.long 0x0 2. "GSLPSTS,Global Sleep Status" "0: Not in Sleep mode,1: In Sleep mode" newline bitfld.long 0x0 1. "GHLTSTS,Global Halt Status" "0: Not in Halt mode,1: In Halt mode" bitfld.long 0x0 0. "GRSTSTS,Global Reset Status" "0: Not in Reset mode,1: In Reset mode" group.long 0x20++0x3 line.long 0x0 "CFDGERFL,Global Error Flag Register" bitfld.long 0x0 16. "EEF0,ECC Error Flag" "0: ECC error not detected during TX-SCAN,1: ECC error detected during TX-SCAN" bitfld.long 0x0 3. "CMPOF,CANFD Message Payload Overflow Flag" "0: CANFD message payload overflow not detected,1: CANFD message payload overflow detected" newline rbitfld.long 0x0 2. "THLES,TX History List Entry Lost Error Status" "0: TX history list entry lost error not detected,1: TX history list entry lost error detected" rbitfld.long 0x0 1. "MES,Message Lost Error Status" "0: Message lost error not detected,1: Message lost error detected" newline bitfld.long 0x0 0. "DEF,DLC Error Flag" "0: DLC error not detected,1: DLC error detected" rgroup.long 0x24++0x3 line.long 0x0 "CFDGTSC,Global Timestamp Counter Register" hexmask.long.word 0x0 0.--15. 1. "TS,Timestamp value" group.long 0x28++0xB line.long 0x0 "CFDGAFLECTR,Global Acceptance Filter List Entry Control Register" bitfld.long 0x0 8. "AFLDAE,Acceptance Filter List Data Access Enable" "0: Acceptance Filter List data access disabled,1: Acceptance Filter List data access enabled" line.long 0x4 "CFDGAFLCFG,Global Acceptance Filter List Configuration Register" hexmask.long.byte 0x4 16.--20. 1. "RNC0,Rule Number" line.long 0x8 "CFDRMNB,RX Message Buffer Number Register" bitfld.long 0x8 8.--10. "RMPLS,Reception Message Buffer Payload Data Size" "0: 8 bytes,1: 12 bytes,?,?,?,?,?,?" hexmask.long.byte 0x8 0.--4. 1. "NRXMB,Number of RX Message Buffers" group.word 0x34++0x1 line.word 0x0 "CFDRMND,RX Message Buffer New Data Register" hexmask.word 0x0 0.--15. 1. "RMNS,RX Message Buffer New Data Status" group.word 0x38++0x1 line.word 0x0 "CFDRMIEC,RX Message Buffer Interrupt Enable Configuration Register" hexmask.word 0x0 0.--15. 1. "RMIE,RX Message Buffer Interrupt Enable" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x3C)++0x3 line.long 0x0 "CFDRFCC$1,RX FIFO Configuration/Control Registers %s" bitfld.long 0x0 13.--15. "RFIGCV,RX FIFO Interrupt Generation Counter Value" "0: Interrupt generated when FIFO is 1/8th full,1: Interrupt generated when FIFO is 1/4th full,?,?,?,?,?,?" bitfld.long 0x0 12. "RFIM,RX FIFO Interrupt Mode" "0: Interrupt generated when RX FIFO counter reaches..,1: Interrupt generated at the end of every received.." newline bitfld.long 0x0 8.--10. "RFDC,RX FIFO Depth Configuration" "0: FIFO Depth = 0 message,1: FIFO Depth = 4 messages,?,?,?,?,?,?" bitfld.long 0x0 4.--6. "RFPLS,Rx FIFO Payload Data Size Configuration" "0: 8 bytes,1: 12 bytes,?,?,?,?,?,?" newline bitfld.long 0x0 1. "RFIE,RX FIFO Interrupt Enable" "0: FIFO interrupt generation disabled,1: FIFO interrupt generation enabled" bitfld.long 0x0 0. "RFE,RX FIFO Enable" "0: FIFO disabled,1: FIFO enabled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x44)++0x3 line.long 0x0 "CFDRFSTS$1,RX FIFO Status Registers %s" hexmask.long.byte 0x0 8.--13. 1. "RFMC,RX FIFO Message Count" bitfld.long 0x0 3. "RFIF,RX FIFO Interrupt Flag" "0: FIFO interrupt condition not satisfied,1: FIFO interrupt condition satisfied" newline bitfld.long 0x0 2. "RFMLT,RX FIFO Message Lost" "0: No message lost in FIFO,1: FIFO message lost" rbitfld.long 0x0 1. "RFFLL,RX FIFO Full" "0: FIFO not full,1: FIFO full" newline rbitfld.long 0x0 0. "RFEMP,RX FIFO Empty" "0: FIFO not empty,1: FIFO empty" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x4C)++0x3 line.long 0x0 "CFDRFPCTR$1,RX FIFO Pointer Control Registers %s" hexmask.long.byte 0x0 0.--7. 1. "RFPC,RX FIFO Pointer Control" repeat.end group.long 0x54++0x7 line.long 0x0 "CFDCFCC,Common FIFO Configuration/Control Register" hexmask.long.byte 0x0 24.--31. 1. "CFITT,Common FIFO Interval Transmission Time" bitfld.long 0x0 21.--23. "CFDC,Common FIFO Depth Configuration" "0: FIFO Depth = 0 message,1: FIFO Depth = 4 messages,?,?,?,?,?,?" newline bitfld.long 0x0 16.--17. "CFTML,Common FIFO TX Message Buffer Link" "0,1,2,3" bitfld.long 0x0 13.--15. "CFIGCV,Common FIFO Interrupt Generation Counter Value" "0: Interrupt generated when FIFO is 1/8th full,1: Interrupt generated when FIFO is 1/4th full,?,?,?,?,?,?" newline bitfld.long 0x0 12. "CFIM,Common FIFO Interrupt Mode" "0: RX FIFO mode: RX interrupt generated when Common..,1: RX FIFO mode: RX interrupt generated at the end.." bitfld.long 0x0 11. "CFITR,Common FIFO Interval Timer Resolution" "0: Reference clock period × 1,1: Reference clock period × 10" newline bitfld.long 0x0 10. "CFITSS,Common FIFO Interval Timer Source Select" "0: Reference clock (× 1 / × 10 period),1: Bit time clock of related channel (FIFO is.." bitfld.long 0x0 8. "CFM,Common FIFO Mode" "0: RX FIFO mode,1: TX FIFO mode" newline bitfld.long 0x0 4.--6. "CFPLS,Common FIFO Payload Data Size Configuration" "0: 8 bytes,1: 12 bytes,?,?,?,?,?,?" bitfld.long 0x0 2. "CFTXIE,Common FIFO TX Interrupt Enable" "0: FIFO interrupt generation disabled for Frame TX,1: FIFO interrupt generation enabled for Frame TX" newline bitfld.long 0x0 1. "CFRXIE,Common FIFO RX Interrupt Enable" "0: FIFO interrupt generation disabled for Frame RX,1: FIFO interrupt generation enabled for Frame RX" bitfld.long 0x0 0. "CFE,Common FIFO Enable" "0: FIFO disabled,1: FIFO enabled" line.long 0x4 "CFDCFSTS,Common FIFO Status Register" hexmask.long.byte 0x4 8.--13. 1. "CFMC,Common FIFO Message Count" bitfld.long 0x4 4. "CFTXIF,Common TX FIFO Interrupt Flag" "0: FIFO interrupt condition not satisfied after..,1: FIFO Interrupt condition satisfied after frame.." newline bitfld.long 0x4 3. "CFRXIF,Common RX FIFO Interrupt Flag" "0: FIFO interrupt condition not satisfied after..,1: FIFO interrupt condition satisfied after frame.." bitfld.long 0x4 2. "CFMLT,Common FIFO Message Lost" "0: Number of message lost in FIFO,1: FIFO message lost" newline rbitfld.long 0x4 1. "CFFLL,Common FIFO Full" "0: FIFO not full,1: FIFO full" rbitfld.long 0x4 0. "CFEMP,Common FIFO Empty" "0: FIFO not empty,1: FIFO empty" wgroup.long 0x5C++0x3 line.long 0x0 "CFDCFPCTR,Common FIFO Pointer Control Register" hexmask.long.byte 0x0 0.--7. 1. "CFPC,Common FIFO Pointer Control" rgroup.long 0x60++0xF line.long 0x0 "CFDFESTS,FIFO Empty Status Register" bitfld.long 0x0 8. "CFEMP,Common FIFO Empty Status" "0: Corresponding FIFO not empty,1: Corresponding FIFO empty" bitfld.long 0x0 0.--1. "RFXEMP,RX FIFO Empty Status" "0: Corresponding FIFO not empty,1: Corresponding FIFO empty,?,?" line.long 0x4 "CFDFFSTS,FIFO Full Status Register" bitfld.long 0x4 8. "CFFLL,Common FIF0 Full Status" "0: Corresponding FIFO not full,1: Corresponding FIFO full" bitfld.long 0x4 0.--1. "RFXFLL,RX FIF0 Full Status" "0: Corresponding FIFO not full,1: Corresponding FIFO full,?,?" line.long 0x8 "CFDFMSTS,FIFO Message Lost Status Register" bitfld.long 0x8 8. "CFMLT,Common FIFO Message Lost Status" "0: Corresponding FIFO Message Lost flag not set,1: Corresponding FIFO Message Lost flag set" bitfld.long 0x8 0.--1. "RFXMLT,RX FIFO Message Lost Status" "0: Corresponding FIFO Message Lost flag not set,1: Corresponding FIFO Message Lost flag set,?,?" line.long 0xC "CFDRFISTS,RX FIFO Interrupt Flag Status Register" bitfld.long 0xC 0.--1. "RFXIF,RX FIFO[x] Interrupt Flag Status" "0: Corresponding RX FIFO Interrupt flag not set,1: Corresponding RX FIFO Interrupt flag set,?,?" repeat 4. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x70)++0x0 line.byte 0x0 "CFDTMC$1,TX Message Buffer Control Registers %s" bitfld.byte 0x0 2. "TMOM,TX Message Buffer One-shot Mode" "0: TX message buffer not configured in one-shot mode,1: TX message buffer configured in one-shot mode" bitfld.byte 0x0 1. "TMTAR,TX Message Buffer Transmission Abort Request" "0: TX message buffer transmission request abort not..,1: TX message buffer transmission request abort.." newline bitfld.byte 0x0 0. "TMTR,TX Message Buffer Transmission Request" "0: TX Message buffer transmission not requested,1: TX message buffer transmission requested" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x74)++0x0 line.byte 0x0 "CFDTMSTS$1,TX Message Buffer Status Registers %s" rbitfld.byte 0x0 4. "TMTARM,TX Message Buffer Transmission Abort Request Mirrored" "0: TX message buffer transmission request abort not..,1: TX message buffer transmission request abort.." rbitfld.byte 0x0 3. "TMTRM,TX Message Buffer Transmission Request Mirrored" "0: TX message buffer transmission not requested,1: TX message buffer transmission requested" newline bitfld.byte 0x0 1.--2. "TMTRF,TX Message Buffer Transmission Result Flag" "0: No result,1: Transmission aborted from the TX message buffer,?,?" rbitfld.byte 0x0 0. "TMTSTS,TX Message Buffer Transmission Status" "0: No on-going transmission,1: On-going transmission" repeat.end rgroup.long 0x78++0xF line.long 0x0 "CFDTMTRSTS,TX Message Buffer Transmission Request Status Register" hexmask.long.byte 0x0 0.--3. 1. "CFDTMTRSTS,TX Message Buffer Transmission Request Status" line.long 0x4 "CFDTMTARSTS,TX Message Buffer Transmission Abort Request Status Register" hexmask.long.byte 0x4 0.--3. 1. "CFDTMTARSTS,TX Message Buffer Transmission Abort Request Status" line.long 0x8 "CFDTMTCSTS,TX Message Buffer Transmission Completion Status Register" hexmask.long.byte 0x8 0.--3. 1. "CFDTMTCSTS,TX Message Buffer Transmission Completion Status" line.long 0xC "CFDTMTASTS,TX Message Buffer Transmission Abort Status Register" hexmask.long.byte 0xC 0.--3. 1. "CFDTMTASTS,TX Message Buffer Transmission Abort Status" group.long 0x88++0xB line.long 0x0 "CFDTMIEC,TX Message Buffer Interrupt Enable Configuration Register" hexmask.long.byte 0x0 0.--3. 1. "TMIEg,TX Message Buffer Interrupt Enable" line.long 0x4 "CFDTXQCC,TX Queue Configuration/Control Register" bitfld.long 0x4 8.--9. "TXQDC,TX Queue Depth Configuration" "0: 0 messages,1: Reserved,?,?" bitfld.long 0x4 7. "TXQIM,TX Queue Interrupt Mode" "0: When the last message is successfully transmitted,1: At every successful transmission" newline bitfld.long 0x4 5. "TXQTXIE,TX Queue TX Interrupt Enable" "0: TX Queue TX interrupt disabled,1: TX Queue TX interrupt enabled" bitfld.long 0x4 0. "TXQE,TX Queue Enable" "0: TX Queue disabled,1: TX Queue enabled" line.long 0x8 "CFDTXQSTS,TX Queue Status Register" rbitfld.long 0x8 8.--10. "TXQMC,TX Queue Message Count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 2. "TXQTXIF,TX Queue TX Interrupt Flag" "0: TX Queue interrupt condition not satisfied after..,1: TX Queue interrupt condition satisfied after a.." newline rbitfld.long 0x8 1. "TXQFLL,TX Queue Full" "0: TX Queue not full,1: TX Queue full" rbitfld.long 0x8 0. "TXQEMP,TX Queue Empty" "0: TX Queue not empty,1: TX Queue empty" wgroup.long 0x94++0x3 line.long 0x0 "CFDTXQPCTR,TX Queue Pointer Control Register" hexmask.long.byte 0x0 0.--7. 1. "TXQPC,TX Queue Pointer Control" group.long 0x98++0x7 line.long 0x0 "CFDTHLCC,TX History List Configuration/Control Register" bitfld.long 0x0 10. "THLDTE,TX History List Dedicated TX Enable" "0: TX FIFO + TX Queue,1: Flat TX MB + TX FIFO + TX Queue" bitfld.long 0x0 9. "THLIM,TX History List Interrupt Mode" "0: Interrupt generated if TX History List level..,1: Interrupt generated for every successfully.." newline bitfld.long 0x0 8. "THLIE,TX History List Interrupt Enable" "0: TX History List Interrupt disabled,1: TX History List Interrupt enabled" bitfld.long 0x0 0. "THLE,TX History List Enable" "0: TX History List disabled,1: TX History List enabled" line.long 0x4 "CFDTHLSTS,TX History List Status Register" hexmask.long.byte 0x4 8.--11. 1. "THLMC,TX History List Message Count" bitfld.long 0x4 3. "THLIF,TX History List Interrupt Flag" "0: TX History List interrupt condition not satisfied,1: TX History List interrupt condition satisfied" newline bitfld.long 0x4 2. "THLELT,TX History List Entry Lost" "0: No entry lost in TX History List,1: TX History List entry Lost" rbitfld.long 0x4 1. "THLFLL,TX History List Full" "0: TX History List not full,1: TX History List full" newline rbitfld.long 0x4 0. "THLEMP,TX History List Empty" "0: TX History List not empty,1: TX History List empty" wgroup.long 0xA0++0x3 line.long 0x0 "CFDTHLPCTR,TX History List Pointer Control Register" hexmask.long.byte 0x0 0.--7. 1. "THLPC,TX History List Pointer Control" rgroup.long 0xA4++0x3 line.long 0x0 "CFDGTINTSTS,Global TX Interrupt Status Register" bitfld.long 0x0 4. "THIF0,TX History List Interrupt" "0: Channel n TX History List Interrupt flag not set,1: Channel n TX History List Interrupt flag set" bitfld.long 0x0 3. "CFTIF0,COM FIFO TX Mode Interrupt Flag" "0: Channel n COM FIFO TX Mode Interrupt flag not set,1: Channel n COM FIFO TX Mode Interrupt flag set" newline bitfld.long 0x0 2. "TQIF0,TX Queue Interrupt Flag" "0: Channel n TX Queue Interrupt flag not set,1: Channel n TX Queue Interrupt flag set" bitfld.long 0x0 1. "TAI0,TX Abort Interrupt Flag" "0: Channel n TX Abort Interrupt flag not set,1: Channel n TX Abort Interrupt flag set" newline bitfld.long 0x0 0. "TSIF0,TX Successful Interrupt Flag" "0: Channel n TX Successful Interrupt flag not set,1: Channel n TX Successful Interrupt flag set" group.long 0xA8++0xB line.long 0x0 "CFDGTSTCFG,Global Test Configuration Register" hexmask.long.byte 0x0 16.--19. 1. "RTMPS,RAM Test Mode Page Select" line.long 0x4 "CFDGTSTCTR,Global Test Control Register" bitfld.long 0x4 2. "RTME,RAM Test Mode Enable" "0: RAM test mode disabled,1: RAM test mode enabled" line.long 0x8 "CFDGFDCFG,Global FD Configuration Register" bitfld.long 0x8 8.--9. "TSCCFG,Timestamp Capture Configuration" "0: Timestamp capture at the sample point of SOF..,1: Timestamp capture at frame valid indication,?,?" bitfld.long 0x8 0. "RPED,RES Bit Protocol Exception Disable" "0: Protocol exception event detection enabled,1: Protocol exception event detection disabled" wgroup.long 0xB8++0x3 line.long 0x0 "CFDGLOCKK,Global Lock Key Register" hexmask.long.word 0x0 0.--15. 1. "LOCK,Lock Key" group.long 0xC0++0xB line.long 0x0 "CFDGAFLIGNENT,Global AFL Ignore Entry Register" hexmask.long.byte 0x0 0.--3. 1. "IRN,Ignore Rule Number" line.long 0x4 "CFDGAFLIGNCTR,Global AFL Ignore Control Register" hexmask.long.byte 0x4 8.--15. 1. "KEY,Key Code" bitfld.long 0x4 0. "IREN,Ignore Rule Enable" "0: AFL entry number is not ignored,1: AFL entry number is ignored" line.long 0x8 "CFDCDTCT,DMA Transfer Control Register" bitfld.long 0x8 8. "CFDMAE,DMA Transfer Enable for Common FIFO 0" "0: DMA transfer request disabled,1: DMA transfer request enabled" bitfld.long 0x8 1. "RFDMAE1,DMA Transfer Enable for RXFIFO 1" "0: DMA transfer request disabled,1: DMA transfer request enabled" newline bitfld.long 0x8 0. "RFDMAE0,DMA Transfer Enable for RXFIFO 0" "0: DMA transfer request disabled,1: DMA transfer request enabled" rgroup.long 0xCC++0x3 line.long 0x0 "CFDCDTSTS,DMA Transfer Status Register" bitfld.long 0x0 8. "CFDMASTS,DMA Transfer Status only for Common FIFO" "0: DMA transfer stopped,1: DMA transfer on going" bitfld.long 0x0 1. "RFDMASTS1,DMA Transfer Status for RX FIFO 1" "0: DMA transfer stopped,1: DMA transfer on going" newline bitfld.long 0x0 0. "RFDMASTS0,DMA Transfer Status for RX FIFO 0" "0: DMA transfer stopped,1: DMA transfer on going" group.long 0xD8++0x3 line.long 0x0 "CFDGRSTC,Global SW reset Register" hexmask.long.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.long 0x0 0. "SRST,SW Reset" "0: Normal state,1: SW reset state" group.long 0x100++0xF line.long 0x0 "CFDC0DCFG,Data Bitrate Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "DSJW,Resynchronization Jump Width" hexmask.long.byte 0x0 16.--19. 1. "DTSEG2,Timing Segment 2" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Timing Segment 1" hexmask.long.byte 0x0 0.--7. 1. "DBRP,Channel Data Baud Rate Prescaler" line.long 0x4 "CFDC0FDCFG,CANFD Configuration Register" bitfld.long 0x4 30. "CLOE,Classical CAN Enable" "0: Classical CAN mode disabled,1: Classical CAN mode enabled" bitfld.long 0x4 29. "REFE,RX Edge Filter Enable" "0: RX edge filter disabled,1: RX edge filter enabled" newline bitfld.long 0x4 28. "FDOE,FD-Only Enable" "0: FD-only mode disabled,1: FD-only mode enabled" hexmask.long.byte 0x4 16.--23. 1. "TDCO,Transceiver Delay Compensation Offset" newline bitfld.long 0x4 10. "ESIC,Error State Indication Configuration" "0: The ESI bit in the frame represents the error..,1: The ESI bit in the frame represents the error.." bitfld.long 0x4 9. "TDCE,Transceiver Delay Compensation Enable" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled" newline bitfld.long 0x4 8. "TDCOC,Transceiver Delay Compensation Offset Configuration" "0: Measured + offset,1: Offset-only" bitfld.long 0x4 0.--2. "EOCCFG,Error Occurrence Counter Configuration" "0: All transmitter or receiver CAN frames,1: All transmitter CAN frames,?,?,?,?,?,?" line.long 0x8 "CFDC0FDCTR,CANFD Control Register" bitfld.long 0x8 1. "SOCCLR,Successful Occurrence Counter Clear" "0: No successful occurrence counter clear,1: Clear successful occurrence counter" bitfld.long 0x8 0. "EOCCLR,Error Occurrence Counter Clear" "0: No error occurrence counter clear,1: Clear error occurrence counter" line.long 0xC "CFDC0FDSTS,CANFD Status Register" hexmask.long.byte 0xC 24.--31. 1. "SOC,Successful occurrence counter" hexmask.long.byte 0xC 16.--23. 1. "EOC,Error Occurrence Counter" newline bitfld.long 0xC 15. "TDCVF,Transceiver Delay Compensation Violation Flag" "0: Transceiver delay compensation violation has not..,1: Transceiver delay compensation violation has.." bitfld.long 0xC 9. "SOCO,Successful Occurrence Counter Overflow" "0: Successful occurrence counter has not overflowed,1: Successful occurrence counter has overflowed" newline bitfld.long 0xC 8. "EOCO,Error Occurrence Counter Overflow" "0: Error occurrence counter has not overflowed,1: Error occurrence counter has overflowed" hexmask.long.byte 0xC 0.--7. 1. "TDCR,Transceiver Delay Compensation Result" rgroup.long 0x110++0x3 line.long 0x0 "CFDC0FDCRC,CANFD CRC Register" hexmask.long.byte 0x0 24.--27. 1. "SCNT,Stuff bit count" hexmask.long.tbyte 0x0 0.--20. 1. "CRCREG,CRC Register value" repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x120)++0x3 line.long 0x0 "CFDGAFLID$1,Global Acceptance Filter List ID Registers" bitfld.long 0x0 31. "GAFLIDE,Global Acceptance Filter List Entry IDE Field" "0: Standard identifier of rule entry ID is valid..,1: Extended identifier of rule entry ID is valid.." bitfld.long 0x0 30. "GAFLRTR,Global Acceptance Filter List Entry RTR Field" "0: Data frame,1: Remote frame" newline bitfld.long 0x0 29. "GAFLLB,Global Acceptance Filter List Entry Loopback Configuration" "0: Global Acceptance Filter List entry ID for..,1: Global Acceptance Filter List entry ID for.." hexmask.long 0x0 0.--28. 1. "GAFLID,Global Acceptance Filter List Entry ID Field" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x124)++0x3 line.long 0x0 "CFDGAFLM$1,Global Acceptance Filter List Mask Registers" bitfld.long 0x0 31. "GAFLIDEM,Global Acceptance Filter List IDE Mask" "0: IDE bit is not used for ID matching,1: IDE bit is used for ID matching" bitfld.long 0x0 30. "GAFLRTRM,Global Acceptance Filter List Entry RTR Mask" "0: RTR bit is not used for ID matching,1: RTR bit is used for ID matching" newline bitfld.long 0x0 29. "GAFLIFL1,Global Acceptance Filter List Information Label 1" "0,1" hexmask.long 0x0 0.--28. 1. "GAFLIDM,Global Acceptance Filter List ID Mask Field" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x128)++0x3 line.long 0x0 "CFDGAFLP0$1,Global Acceptance Filter List Pointer 0 Registers" hexmask.long.word 0x0 16.--31. 1. "GAFLPTR,Global Acceptance Filter List Pointer" bitfld.long 0x0 15. "GAFLRMV,Global Acceptance Filter List RX Message Buffer Valid" "0: Single message buffer direction pointer is invalid,1: Single message buffer direction pointer is valid" newline hexmask.long.byte 0x0 8.--12. 1. "GAFLRMDP,Global Acceptance Filter List RX Message Buffer Direction Pointer" bitfld.long 0x0 7. "GAFLIFL0,Global Acceptance Filter List Information Label 0" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "GAFLDLC,Global Acceptance Filter List DLC Field" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x12C)++0x3 line.long 0x0 "CFDGAFLP1$1,Global Acceptance Filter List Pointer 1 Registers" bitfld.long 0x0 8. "GAFLFDP8,Global Acceptance Filter List FIFO Direction Pointer" "0: Disable Common FIFO as target for reception,1: Enable Common FIFO as target for reception" bitfld.long 0x0 1. "GAFLFDP1,Global Acceptance Filter List FIFO Direction Pointer" "0: Disable RX FIFO 1 as target for reception,1: Enable RX FIFO 1 as target for reception" newline bitfld.long 0x0 0. "GAFLFDP0,Global Acceptance Filter List FIFO Direction Pointer" "0: Disable RX FIFO 0 as target for reception,1: Enable RX FIFO 0 as target for reception" repeat.end repeat 64. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x280)++0x3 line.long 0x0 "CFDRPGACC$1,RAM Test Page Access Registers %s" hexmask.long 0x0 0.--31. 1. "RDTA,RAM Data Test Access" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x520)++0x3 line.long 0x0 "CFDRFID$1,RX FIFO Access ID Register %s" bitfld.long 0x0 31. "RFIDE,RX FIFO Buffer IDE bit" "0: STD-ID has been received,1: EXT-ID has been received" bitfld.long 0x0 30. "RFRTR,RX FIFO Buffer RTR bit" "0: Data frame,1: Remote frame" newline hexmask.long 0x0 0.--28. 1. "RFID,RX FIFO Buffer ID Field" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x524)++0x3 line.long 0x0 "CFDRFPTR$1,RX FIFO Access Pointer Register %s" hexmask.long.byte 0x0 28.--31. 1. "RFDLC,RX FIFO Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RFTS,RX FIFO Timestamp Value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x528)++0x3 line.long 0x0 "CFDRFFDSTS$1,RX FIFO Access CANFD Status Register %s" hexmask.long.word 0x0 16.--31. 1. "CFDRFPTR,RX FIFO Buffer Pointer Field" bitfld.long 0x0 8.--9. "RFIFL,RX FIFO Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RFFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RFBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RFESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x52C)++0x3 line.long 0x0 "CFDRFDF$1_0,RX FIFO Access Data Field 0 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x530)++0x3 line.long 0x0 "CFDRFDF$1_1,RX FIFO Access Data Field 1 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x534)++0x3 line.long 0x0 "CFDRFDF$1_2,RX FIFO Access Data Field 2 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x538)++0x3 line.long 0x0 "CFDRFDF$1_3,RX FIFO Access Data Field 3 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x53C)++0x3 line.long 0x0 "CFDRFDF$1_4,RX FIFO Access Data Field 4 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x540)++0x3 line.long 0x0 "CFDRFDF$1_5,RX FIFO Access Data Field 5 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x544)++0x3 line.long 0x0 "CFDRFDF$1_6,RX FIFO Access Data Field 6 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x548)++0x3 line.long 0x0 "CFDRFDF$1_7,RX FIFO Access Data Field 7 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x54C)++0x3 line.long 0x0 "CFDRFDF$1_8,RX FIFO Access Data Field 8 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x550)++0x3 line.long 0x0 "CFDRFDF$1_9,RX FIFO Access Data Field 9 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x554)++0x3 line.long 0x0 "CFDRFDF$1_10,RX FIFO Access Data Field 10 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x558)++0x3 line.long 0x0 "CFDRFDF$1_11,RX FIFO Access Data Field 11 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x55C)++0x3 line.long 0x0 "CFDRFDF$1_12,RX FIFO Access Data Field 12 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x560)++0x3 line.long 0x0 "CFDRFDF$1_13,RX FIFO Access Data Field 13 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x564)++0x3 line.long 0x0 "CFDRFDF$1_14,RX FIFO Access Data Field 14 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x568)++0x3 line.long 0x0 "CFDRFDF$1_15,RX FIFO Access Data Field 15 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end group.long 0x5B8++0xB line.long 0x0 "CFDCFID,Common FIFO Access ID Register" bitfld.long 0x0 31. "CFIDE,Common FIFO Buffer IDE Bit" "0: STD-ID will be transmitted or has been received,1: EXT-ID will be transmitted or has been received" bitfld.long 0x0 30. "CFRTR,Common FIFO Buffer RTR Bit" "0: Data Frame,1: Remote Frame" newline bitfld.long 0x0 29. "THLEN,THL Entry enable" "0: Entry will not be stored in THL after successful..,1: Entry will be stored in THL after successful TX." hexmask.long 0x0 0.--28. 1. "CFID,Common FIFO Buffer ID Field" line.long 0x4 "CFDCFPTR,Common FIFO Access Pointer Register" hexmask.long.byte 0x4 28.--31. 1. "CFDLC,Common FIFO Buffer DLC Field" hexmask.long.word 0x4 0.--15. 1. "CFTS,Common FIFO Timestamp Value" line.long 0x8 "CFDCFFDCSTS,Common FIFO Access CANFD Control/Status Register" hexmask.long.word 0x8 16.--31. 1. "CFPTR,Common FIFO Buffer Pointer Field" bitfld.long 0x8 8.--9. "CFIFL,COMMON FIFO Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x8 2. "CFFDF,CAN FD Format bit" "0: Non CANFD frame received or to transmit,1: CANFD frame received or to transmit" bitfld.long 0x8 1. "CFBRS,Bit Rate Switch bit" "0: CANFD frame received or to transmit with no bit..,1: CANFD frame received or to transmit with bit.." newline bitfld.long 0x8 0. "CFESI,Error State Indicator bit" "0: CANFD frame received or to transmit by error..,1: CANFD frame received or to transmit by error.." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5C4)++0x3 line.long 0x0 "CFDCFDF$1,Common FIFO Access Data Field %s Registers" hexmask.long.byte 0x0 24.--31. 1. "CFDB_HH,Common FIFO Buffer Data Bytes ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "CFDB_HL,Common FIFO Buffer Data Bytes ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "CFDB_LH,Common FIFO Buffer Data Bytes ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "CFDB_LL,Common FIFO Buffer Data Bytes (p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x604)++0x3 line.long 0x0 "CFDTMID$1,TX Message Buffer ID Registers" bitfld.long 0x0 31. "TMIDE,TX Message Buffer IDE bit" "0: STD-ID is transmitted,1: EXT-ID is transmitted" bitfld.long 0x0 30. "TMRTR,TX Message Buffer RTR bit" "0: Data frame,1: Remote frame" newline bitfld.long 0x0 29. "THLEN,Tx History List Entry" "0: Entry not stored in THL after successful TX,1: Entry stored in THL after successful TX" hexmask.long 0x0 0.--28. 1. "TMID,TX Message Buffer ID Field" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x608)++0x3 line.long 0x0 "CFDTMPTR$1,TX Message Buffer Pointer Register" hexmask.long.byte 0x0 28.--31. 1. "TMDLC,TX Message Buffer DLC Field" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x60C)++0x3 line.long 0x0 "CFDTMFDCTR$1,TX Message Buffer CANFD Control Register" hexmask.long.word 0x0 16.--31. 1. "TMPTR,TX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "TMIFL,TX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "TMFDF,CAN FD Format bit" "0: Non CANFD frame to transmit,1: CANFD frame to transmit" bitfld.long 0x0 1. "TMBRS,Bit Rate Switch bit" "0: CANFD frame to transmit with no bit rate switch,1: CANFD frame to transmit with bit rate switch" newline bitfld.long 0x0 0. "TMESI,Error State Indicator bit" "0: CANFD frame to transmit by error active node,1: CANFD frame to transmit by error passive node" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x610)++0x3 line.long 0x0 "CFDTMDF$1_0,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x614)++0x3 line.long 0x0 "CFDTMDF$1_1,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x618)++0x3 line.long 0x0 "CFDTMDF$1_2,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x61C)++0x3 line.long 0x0 "CFDTMDF$1_3,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x620)++0x3 line.long 0x0 "CFDTMDF$1_4,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x624)++0x3 line.long 0x0 "CFDTMDF$1_5,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x628)++0x3 line.long 0x0 "CFDTMDF$1_6,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x62C)++0x3 line.long 0x0 "CFDTMDF$1_7,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x630)++0x3 line.long 0x0 "CFDTMDF$1_8,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x634)++0x3 line.long 0x0 "CFDTMDF$1_9,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x638)++0x3 line.long 0x0 "CFDTMDF$1_10,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x63C)++0x3 line.long 0x0 "CFDTMDF$1_11,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x640)++0x3 line.long 0x0 "CFDTMDF$1_12,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x644)++0x3 line.long 0x0 "CFDTMDF$1_13,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x648)++0x3 line.long 0x0 "CFDTMDF$1_14,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x64C)++0x3 line.long 0x0 "CFDTMDF$1_15,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end rgroup.long 0x740++0x7 line.long 0x0 "CFDTHLACC0,TX History List Access Register 0" hexmask.long.word 0x0 16.--31. 1. "TMTS,Transmit Timestamp" bitfld.long 0x0 3.--4. "BN,Buffer Number" "0,1,2,3" newline bitfld.long 0x0 0.--2. "BT,Buffer Type" "?,1: Flat TX message buffer,?,?,?,?,?,?" line.long 0x4 "CFDTHLACC1,TX History List Access Register 1" bitfld.long 0x4 16.--17. "TIFL,Transmit Information Label" "0,1,2,3" hexmask.long.word 0x4 0.--15. 1. "TID,Transmit ID" repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x920)++0x3 line.long 0x0 "CFDRMID$1,RX Message Buffer ID Registers" bitfld.long 0x0 31. "RMIDE,RX Message Buffer IDE Bit" "0: STD-ID is stored,1: EXT-ID is stored" bitfld.long 0x0 30. "RMRTR,RX Message Buffer RTR Bit" "0: Data frame,1: Remote frame" newline hexmask.long 0x0 0.--28. 1. "RMID,RX Message Buffer ID Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x924)++0x3 line.long 0x0 "CFDRMPTR$1,RX Message Buffer Pointer Registers" hexmask.long.byte 0x0 28.--31. 1. "RMDLC,RX Message Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RMTS,RX Message Buffer Timestamp Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x928)++0x3 line.long 0x0 "CFDRMFDSTS$1,RX Message Buffer CANFD Status Registers" hexmask.long.word 0x0 16.--31. 1. "RMPTR,RX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "RMIFL,RX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RMFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RMBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RMESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x92C)++0x3 line.long 0x0 "CFDRMDF$1_0,RX Message Buffer Data Field 0 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x930)++0x3 line.long 0x0 "CFDRMDF$1_1,RX Message Buffer Data Field 1 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x934)++0x3 line.long 0x0 "CFDRMDF$1_2,RX Message Buffer Data Field 2 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x938)++0x3 line.long 0x0 "CFDRMDF$1_3,RX Message Buffer Data Field 3 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x93C)++0x3 line.long 0x0 "CFDRMDF$1_4,RX Message Buffer Data Field 4 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x940)++0x3 line.long 0x0 "CFDRMDF$1_5,RX Message Buffer Data Field 5 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x944)++0x3 line.long 0x0 "CFDRMDF$1_6,RX Message Buffer Data Field 6 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x948)++0x3 line.long 0x0 "CFDRMDF$1_7,RX Message Buffer Data Field 7 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x94C)++0x3 line.long 0x0 "CFDRMDF$1_8,RX Message Buffer Data Field 8 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x950)++0x3 line.long 0x0 "CFDRMDF$1_9,RX Message Buffer Data Field 9 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x954)++0x3 line.long 0x0 "CFDRMDF$1_10,RX Message Buffer Data Field 10 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x958)++0x3 line.long 0x0 "CFDRMDF$1_11,RX Message Buffer Data Field 11 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x95C)++0x3 line.long 0x0 "CFDRMDF$1_12,RX Message Buffer Data Field 12 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x960)++0x3 line.long 0x0 "CFDRMDF$1_13,RX Message Buffer Data Field 13 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x964)++0x3 line.long 0x0 "CFDRMDF$1_14,RX Message Buffer Data Field 14 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x968)++0x3 line.long 0x0 "CFDRMDF$1_15,RX Message Buffer Data Field 15 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD20)++0x3 line.long 0x0 "CFDRMID$1,RX Message Buffer ID Registers" bitfld.long 0x0 31. "RMIDE,RX Message Buffer IDE Bit" "0: STD-ID is stored,1: EXT-ID is stored" bitfld.long 0x0 30. "RMRTR,RX Message Buffer RTR Bit" "0: Data frame,1: Remote frame" newline hexmask.long 0x0 0.--28. 1. "RMID,RX Message Buffer ID Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD24)++0x3 line.long 0x0 "CFDRMPTR$1,RX Message Buffer Pointer Registers" hexmask.long.byte 0x0 28.--31. 1. "RMDLC,RX Message Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RMTS,RX Message Buffer Timestamp Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD28)++0x3 line.long 0x0 "CFDRMFDSTS$1,RX Message Buffer CANFD Status Registers" hexmask.long.word 0x0 16.--31. 1. "RMPTR,RX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "RMIFL,RX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RMFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RMBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RMESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD2C)++0x3 line.long 0x0 "CFDRMDF$1_0,RX Message Buffer Data Field 0 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD30)++0x3 line.long 0x0 "CFDRMDF$1_1,RX Message Buffer Data Field 1 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD34)++0x3 line.long 0x0 "CFDRMDF$1_2,RX Message Buffer Data Field 2 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD38)++0x3 line.long 0x0 "CFDRMDF$1_3,RX Message Buffer Data Field 3 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD3C)++0x3 line.long 0x0 "CFDRMDF$1_4,RX Message Buffer Data Field 4 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD40)++0x3 line.long 0x0 "CFDRMDF$1_5,RX Message Buffer Data Field 5 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD44)++0x3 line.long 0x0 "CFDRMDF$1_6,RX Message Buffer Data Field 6 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD48)++0x3 line.long 0x0 "CFDRMDF$1_7,RX Message Buffer Data Field 7 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD4C)++0x3 line.long 0x0 "CFDRMDF$1_8,RX Message Buffer Data Field 8 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD50)++0x3 line.long 0x0 "CFDRMDF$1_9,RX Message Buffer Data Field 9 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD54)++0x3 line.long 0x0 "CFDRMDF$1_10,RX Message Buffer Data Field 10 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD58)++0x3 line.long 0x0 "CFDRMDF$1_11,RX Message Buffer Data Field 11 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD5C)++0x3 line.long 0x0 "CFDRMDF$1_12,RX Message Buffer Data Field 12 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD60)++0x3 line.long 0x0 "CFDRMDF$1_13,RX Message Buffer Data Field 13 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD64)++0x3 line.long 0x0 "CFDRMDF$1_14,RX Message Buffer Data Field 14 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD68)++0x3 line.long 0x0 "CFDRMDF$1_15,RX Message Buffer Data Field 15 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1124)++0x3 line.long 0x0 "CFDRMPTR$1,RX Message Buffer Pointer Registers" hexmask.long.byte 0x0 28.--31. 1. "RMDLC,RX Message Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RMTS,RX Message Buffer Timestamp Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1128)++0x3 line.long 0x0 "CFDRMFDSTS$1,RX Message Buffer CANFD Status Registers" hexmask.long.word 0x0 16.--31. 1. "RMPTR,RX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "RMIFL,RX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RMFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RMBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RMESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x112C)++0x3 line.long 0x0 "CFDRMDF$1_0,RX Message Buffer Data Field 0 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1130)++0x3 line.long 0x0 "CFDRMDF$1_1,RX Message Buffer Data Field 1 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1134)++0x3 line.long 0x0 "CFDRMDF$1_2,RX Message Buffer Data Field 2 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1138)++0x3 line.long 0x0 "CFDRMDF$1_3,RX Message Buffer Data Field 3 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x113C)++0x3 line.long 0x0 "CFDRMDF$1_4,RX Message Buffer Data Field 4 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1140)++0x3 line.long 0x0 "CFDRMDF$1_5,RX Message Buffer Data Field 5 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1144)++0x3 line.long 0x0 "CFDRMDF$1_6,RX Message Buffer Data Field 6 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1148)++0x3 line.long 0x0 "CFDRMDF$1_7,RX Message Buffer Data Field 7 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x114C)++0x3 line.long 0x0 "CFDRMDF$1_8,RX Message Buffer Data Field 8 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1150)++0x3 line.long 0x0 "CFDRMDF$1_9,RX Message Buffer Data Field 9 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1154)++0x3 line.long 0x0 "CFDRMDF$1_10,RX Message Buffer Data Field 10 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1158)++0x3 line.long 0x0 "CFDRMDF$1_11,RX Message Buffer Data Field 11 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x115C)++0x3 line.long 0x0 "CFDRMDF$1_12,RX Message Buffer Data Field 12 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1160)++0x3 line.long 0x0 "CFDRMDF$1_13,RX Message Buffer Data Field 13 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1164)++0x3 line.long 0x0 "CFDRMDF$1_14,RX Message Buffer Data Field 14 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1168)++0x3 line.long 0x0 "CFDRMDF$1_15,RX Message Buffer Data Field 15 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1524)++0x3 line.long 0x0 "CFDRMPTR$1,RX Message Buffer Pointer Registers" hexmask.long.byte 0x0 28.--31. 1. "RMDLC,RX Message Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RMTS,RX Message Buffer Timestamp Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1528)++0x3 line.long 0x0 "CFDRMFDSTS$1,RX Message Buffer CANFD Status Registers" hexmask.long.word 0x0 16.--31. 1. "RMPTR,RX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "RMIFL,RX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RMFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RMBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RMESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x152C)++0x3 line.long 0x0 "CFDRMDF$1_0,RX Message Buffer Data Field 0 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1530)++0x3 line.long 0x0 "CFDRMDF$1_1,RX Message Buffer Data Field 1 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1534)++0x3 line.long 0x0 "CFDRMDF$1_2,RX Message Buffer Data Field 2 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1538)++0x3 line.long 0x0 "CFDRMDF$1_3,RX Message Buffer Data Field 3 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x153C)++0x3 line.long 0x0 "CFDRMDF$1_4,RX Message Buffer Data Field 4 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1540)++0x3 line.long 0x0 "CFDRMDF$1_5,RX Message Buffer Data Field 5 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1544)++0x3 line.long 0x0 "CFDRMDF$1_6,RX Message Buffer Data Field 6 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1548)++0x3 line.long 0x0 "CFDRMDF$1_7,RX Message Buffer Data Field 7 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x154C)++0x3 line.long 0x0 "CFDRMDF$1_8,RX Message Buffer Data Field 8 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1550)++0x3 line.long 0x0 "CFDRMDF$1_9,RX Message Buffer Data Field 9 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1554)++0x3 line.long 0x0 "CFDRMDF$1_10,RX Message Buffer Data Field 10 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1558)++0x3 line.long 0x0 "CFDRMDF$1_11,RX Message Buffer Data Field 11 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x155C)++0x3 line.long 0x0 "CFDRMDF$1_12,RX Message Buffer Data Field 12 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1560)++0x3 line.long 0x0 "CFDRMDF$1_13,RX Message Buffer Data Field 13 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1564)++0x3 line.long 0x0 "CFDRMDF$1_14,RX Message Buffer Data Field 14 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1568)++0x3 line.long 0x0 "CFDRMDF$1_15,RX Message Buffer Data Field 15 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end tree.end tree "CANFD0_NS" base ad:0x50380000 group.long 0x0++0xF line.long 0x0 "CFDC0NCFG,Nominal Bitrate Configuration Register" hexmask.long.byte 0x0 25.--31. 1. "NTSEG2,Timing Segment 2" hexmask.long.byte 0x0 17.--24. 1. "NTSEG1,Timing Segment 1" newline hexmask.long.byte 0x0 10.--16. 1. "NSJW,Resynchronization Jump Width" hexmask.long.word 0x0 0.--9. 1. "NBRP,Channel Nominal Baud Rate Prescaler" line.long 0x4 "CFDC0CTR,Control Register" bitfld.long 0x4 31. "ROM,Restricted Operation Mode" "0: Restricted operation mode disabled,1: Restricted operation mode enabled" bitfld.long 0x4 30. "BFT,Bit Flip Test" "0: First data bit of reception stream not inverted,1: First data bit of reception stream inverted" newline bitfld.long 0x4 25.--26. "CTMS,Channel Test Mode Select" "0: Basic test mode,1: Listen-only mode,?,?" bitfld.long 0x4 24. "CTME,Channel Test Mode Enable" "0: Channel test mode disabled,1: Channel test mode enabled" newline bitfld.long 0x4 23. "ERRD,Channel Error Display" "0: Only the first set of error codes displayed,1: Accumulated error codes displayed" bitfld.long 0x4 21.--22. "BOM,Channel Bus-Off Mode" "0: Normal mode (comply with ISO 11898-1),1: Entry to Halt mode automatically at bus-off start,?,?" newline bitfld.long 0x4 19. "TDCVFIE,Transceiver Delay Compensation Violation Interrupt Enable" "0: Transceiver delay compensation violation..,1: Transceiver delay compensation violation.." bitfld.long 0x4 18. "SOCOIE,Successful Occurrence Counter Overflow Interrupt Enable" "0: Successful occurrence counter overflow interrupt..,1: Successful occurrence counter overflow interrupt.." newline bitfld.long 0x4 17. "EOCOIE,Error Occurrence Counter Overflow Interrupt Enable" "0: Error occurrence counter overflow interrupt..,1: Error occurrence counter overflow interrupt.." bitfld.long 0x4 16. "TAIE,Transmission Abort Interrupt Enable" "0: TX abort interrupt disabled,1: TX abort interrupt enabled" newline bitfld.long 0x4 15. "ALIE,Arbitration Lost Interrupt Enable" "0: Arbitration lost interrupt disabled,1: Arbitration lost interrupt enabled" bitfld.long 0x4 14. "BLIE,Bus Lock Interrupt Enable" "0: Bus lock interrupt disabled,1: Bus lock interrupt enabled" newline bitfld.long 0x4 13. "OLIE,Overload Interrupt Enable" "0: Overload interrupt disabled,1: Overload interrupt enabled" bitfld.long 0x4 12. "BORIE,Bus-Off Recovery Interrupt Enable" "0: Bus-off recovery interrupt disabled,1: Bus-off recovery interrupt enabled" newline bitfld.long 0x4 11. "BOEIE,Bus-Off Entry Interrupt Enable" "0: Bus-off entry interrupt disabled,1: Bus-off entry interrupt enabled" bitfld.long 0x4 10. "EPIE,Error Passive Interrupt Enable" "0: Error passive interrupt disabled,1: Error passive interrupt enabled" newline bitfld.long 0x4 9. "EWIE,Error Warning Interrupt Enable" "0: Error warning interrupt disabled,1: Error warning interrupt enabled" bitfld.long 0x4 8. "BEIE,Bus Error Interrupt Enable" "0: Bus error interrupt disabled,1: Bus error interrupt enabled" newline bitfld.long 0x4 3. "RTBO,Return from Bus-Off" "0: Channel is not forced to return from bus-off,1: Channel is forced to return from bus-off" bitfld.long 0x4 2. "CSLPR,Channel Sleep Request" "0: Channel sleep request disabled,1: Channel sleep request enabled" newline bitfld.long 0x4 0.--1. "CHMDC,Channel Mode Control" "0: Channel operation mode request,1: Channel reset request,?,?" line.long 0x8 "CFDC0STS,Status Register" hexmask.long.byte 0x8 24.--31. 1. "TEC,Transmission Error Count" hexmask.long.byte 0x8 16.--23. 1. "REC,Reception Error Count" newline bitfld.long 0x8 8. "ESIF,Error State Indication Flag" "0: No CANFD message has been received when the ESI..,1: At least one CANFD message was received when the.." rbitfld.long 0x8 7. "COMSTS,Channel Communication Status" "0: Channel is not ready for communication,1: Channel is ready for communication" newline rbitfld.long 0x8 6. "RECSTS,Channel Receive Status" "0: Channel is not receiving,1: Channel is receiving" rbitfld.long 0x8 5. "TRMSTS,Channel Transmit Status" "0: Channel is not transmitting,1: Channel is transmitting" newline rbitfld.long 0x8 4. "BOSTS,Channel Bus-Off Status" "0: Channel not in bus-off state,1: Channel in bus-off state" rbitfld.long 0x8 3. "EPSTS,Channel Error Passive Status" "0: Channel not in error passive state,1: Channel in error passive state" newline rbitfld.long 0x8 2. "CSLPSTS,Channel Sleep Status" "0: Channel not in Sleep mode,1: Channel in Sleep mode" rbitfld.long 0x8 1. "CHLTSTS,Channel Halt Status" "0: Channel not in Halt mode,1: Channel in Halt mode" newline rbitfld.long 0x8 0. "CRSTSTS,Channel Reset Status" "0: Channel not in Reset mode,1: Channel in Reset mode" line.long 0xC "CFDC0ERFL,Error Flag Register" hexmask.long.word 0xC 16.--30. 1. "CRCREG,CRC Register value" bitfld.long 0xC 14. "ADERR,Acknowledge Delimiter Error" "0: Channel acknowledge delimiter error not detected,1: Channel acknowledge delimiter error detected" newline bitfld.long 0xC 13. "B0ERR,Bit 0 Error" "0: Channel bit 0 error not detected,1: Channel bit 0 error detected" bitfld.long 0xC 12. "B1ERR,Bit 1 Error" "0: Channel bit 1 error not detected,1: Channel bit 1 error detected" newline bitfld.long 0xC 11. "CERR,CRC Error" "0: Channel CRC error not detected,1: Channel CRC error detected" bitfld.long 0xC 10. "AERR,Acknowledge Error" "0: Channel acknowledge error not detected,1: Channel acknowledge error detected" newline bitfld.long 0xC 9. "FERR,Form Error" "0: Channel form error not detected,1: Channel form error detected" bitfld.long 0xC 8. "SERR,Stuff Error" "0: Channel stuff error not detected,1: Channel stuff error detected" newline bitfld.long 0xC 7. "ALF,Arbitration Lost Flag" "0: Channel arbitration lost not detected,1: Channel arbitration lost detected" bitfld.long 0xC 6. "BLF,Bus Lock Flag" "0: Channel bus lock not detected,1: Channel bus lock detected" newline bitfld.long 0xC 5. "OVLF,Overload Flag" "0: Channel overload not detected,1: Channel overload detected" bitfld.long 0xC 4. "BORF,Bus-Off Recovery Flag" "0: Channel bus-off recovery not detected,1: Channel bus-off recovery detected" newline bitfld.long 0xC 3. "BOEF,Bus-Off Entry Flag" "0: Channel bus-off entry not detected,1: Channel bus-off entry detected" bitfld.long 0xC 2. "EPF,Error Passive Flag" "0: Channel error passive not detected,1: Channel error passive detected" newline bitfld.long 0xC 1. "EWF,Error Warning Flag" "0: Channel error warning not detected,1: Channel error warning detected" bitfld.long 0xC 0. "BEF,Bus Error Flag" "0: Channel bus error not detected,1: Channel bus error detected" group.long 0x14++0x7 line.long 0x0 "CFDGCFG,Global Configuration Register" hexmask.long.word 0x0 16.--31. 1. "ITRCP,Interval Timer Reference Clock Prescaler" bitfld.long 0x0 12. "TSSS,Timestamp Source Select" "0: Source clock for timestamp counter is peripheral..,1: Source clock for timestamp counter is bit time.." newline hexmask.long.byte 0x0 8.--11. 1. "TSP,Timestamp Prescaler" bitfld.long 0x0 5. "CMPOC,CANFD Message Payload Overflow Configuration" "0: Message is rejected,1: Message payload is cut to fit to configured.." newline bitfld.long 0x0 4. "DCS,Data Link Controller Clock Select" "0: CANFD core clock (CANFDCLK),1: External oscillator clock (CANMCLK)" bitfld.long 0x0 3. "MME,Mirror Mode Enable" "0: Mirror mode disabled,1: Mirror mode enabled" newline bitfld.long 0x0 2. "DRE,DLC Replacement Enable" "0: DLC replacement disabled,1: DLC replacement enabled" bitfld.long 0x0 1. "DCE,DLC Check Enable" "0: DLC check disabled,1: DLC check enabled" newline bitfld.long 0x0 0. "TPRI,Transmission Priority" "0: ID priority,1: Message buffer number priority" line.long 0x4 "CFDGCTR,Global Control Register" bitfld.long 0x4 16. "TSRST,Timestamp Reset" "0: Timestamp not reset,1: Timestamp reset" bitfld.long 0x4 11. "CMPOFIE,CANFD Message Payload Overflow Flag Interrupt Enable" "0: CANFD message payload overflow flag interrupt..,1: CANFD message payload overflow flag interrupt.." newline bitfld.long 0x4 10. "THLEIE,TX History List Entry Lost Interrupt Enable" "0: TX history list entry lost interrupt disabled,1: TX history list entry lost interrupt enabled" bitfld.long 0x4 9. "MEIE,Message Lost Error Interrupt Enable" "0: Message lost error interrupt disabled,1: Message lost error interrupt enabled" newline bitfld.long 0x4 8. "DEIE,DLC Check Interrupt Enable" "0: DLC check interrupt disabled,1: DLC check interrupt enabled" bitfld.long 0x4 2. "GSLPR,Global Sleep Request" "0: Global sleep request disabled,1: Global sleep request enabled" newline bitfld.long 0x4 0.--1. "GMDC,Global Mode Control" "0: Global operation mode request,1: Global reset mode request,?,?" rgroup.long 0x1C++0x3 line.long 0x0 "CFDGSTS,Global Status Register" bitfld.long 0x0 3. "GRAMINIT,Global RAM Initialization" "0: RAM initialization is complete,1: RAM initialization is ongoing" bitfld.long 0x0 2. "GSLPSTS,Global Sleep Status" "0: Not in Sleep mode,1: In Sleep mode" newline bitfld.long 0x0 1. "GHLTSTS,Global Halt Status" "0: Not in Halt mode,1: In Halt mode" bitfld.long 0x0 0. "GRSTSTS,Global Reset Status" "0: Not in Reset mode,1: In Reset mode" group.long 0x20++0x3 line.long 0x0 "CFDGERFL,Global Error Flag Register" bitfld.long 0x0 16. "EEF0,ECC Error Flag" "0: ECC error not detected during TX-SCAN,1: ECC error detected during TX-SCAN" bitfld.long 0x0 3. "CMPOF,CANFD Message Payload Overflow Flag" "0: CANFD message payload overflow not detected,1: CANFD message payload overflow detected" newline rbitfld.long 0x0 2. "THLES,TX History List Entry Lost Error Status" "0: TX history list entry lost error not detected,1: TX history list entry lost error detected" rbitfld.long 0x0 1. "MES,Message Lost Error Status" "0: Message lost error not detected,1: Message lost error detected" newline bitfld.long 0x0 0. "DEF,DLC Error Flag" "0: DLC error not detected,1: DLC error detected" rgroup.long 0x24++0x3 line.long 0x0 "CFDGTSC,Global Timestamp Counter Register" hexmask.long.word 0x0 0.--15. 1. "TS,Timestamp value" group.long 0x28++0xB line.long 0x0 "CFDGAFLECTR,Global Acceptance Filter List Entry Control Register" bitfld.long 0x0 8. "AFLDAE,Acceptance Filter List Data Access Enable" "0: Acceptance Filter List data access disabled,1: Acceptance Filter List data access enabled" line.long 0x4 "CFDGAFLCFG,Global Acceptance Filter List Configuration Register" hexmask.long.byte 0x4 16.--20. 1. "RNC0,Rule Number" line.long 0x8 "CFDRMNB,RX Message Buffer Number Register" bitfld.long 0x8 8.--10. "RMPLS,Reception Message Buffer Payload Data Size" "0: 8 bytes,1: 12 bytes,?,?,?,?,?,?" hexmask.long.byte 0x8 0.--4. 1. "NRXMB,Number of RX Message Buffers" group.word 0x34++0x1 line.word 0x0 "CFDRMND,RX Message Buffer New Data Register" hexmask.word 0x0 0.--15. 1. "RMNS,RX Message Buffer New Data Status" group.word 0x38++0x1 line.word 0x0 "CFDRMIEC,RX Message Buffer Interrupt Enable Configuration Register" hexmask.word 0x0 0.--15. 1. "RMIE,RX Message Buffer Interrupt Enable" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x3C)++0x3 line.long 0x0 "CFDRFCC$1,RX FIFO Configuration/Control Registers %s" bitfld.long 0x0 13.--15. "RFIGCV,RX FIFO Interrupt Generation Counter Value" "0: Interrupt generated when FIFO is 1/8th full,1: Interrupt generated when FIFO is 1/4th full,?,?,?,?,?,?" bitfld.long 0x0 12. "RFIM,RX FIFO Interrupt Mode" "0: Interrupt generated when RX FIFO counter reaches..,1: Interrupt generated at the end of every received.." newline bitfld.long 0x0 8.--10. "RFDC,RX FIFO Depth Configuration" "0: FIFO Depth = 0 message,1: FIFO Depth = 4 messages,?,?,?,?,?,?" bitfld.long 0x0 4.--6. "RFPLS,Rx FIFO Payload Data Size Configuration" "0: 8 bytes,1: 12 bytes,?,?,?,?,?,?" newline bitfld.long 0x0 1. "RFIE,RX FIFO Interrupt Enable" "0: FIFO interrupt generation disabled,1: FIFO interrupt generation enabled" bitfld.long 0x0 0. "RFE,RX FIFO Enable" "0: FIFO disabled,1: FIFO enabled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x44)++0x3 line.long 0x0 "CFDRFSTS$1,RX FIFO Status Registers %s" hexmask.long.byte 0x0 8.--13. 1. "RFMC,RX FIFO Message Count" bitfld.long 0x0 3. "RFIF,RX FIFO Interrupt Flag" "0: FIFO interrupt condition not satisfied,1: FIFO interrupt condition satisfied" newline bitfld.long 0x0 2. "RFMLT,RX FIFO Message Lost" "0: No message lost in FIFO,1: FIFO message lost" rbitfld.long 0x0 1. "RFFLL,RX FIFO Full" "0: FIFO not full,1: FIFO full" newline rbitfld.long 0x0 0. "RFEMP,RX FIFO Empty" "0: FIFO not empty,1: FIFO empty" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x4C)++0x3 line.long 0x0 "CFDRFPCTR$1,RX FIFO Pointer Control Registers %s" hexmask.long.byte 0x0 0.--7. 1. "RFPC,RX FIFO Pointer Control" repeat.end group.long 0x54++0x7 line.long 0x0 "CFDCFCC,Common FIFO Configuration/Control Register" hexmask.long.byte 0x0 24.--31. 1. "CFITT,Common FIFO Interval Transmission Time" bitfld.long 0x0 21.--23. "CFDC,Common FIFO Depth Configuration" "0: FIFO Depth = 0 message,1: FIFO Depth = 4 messages,?,?,?,?,?,?" newline bitfld.long 0x0 16.--17. "CFTML,Common FIFO TX Message Buffer Link" "0,1,2,3" bitfld.long 0x0 13.--15. "CFIGCV,Common FIFO Interrupt Generation Counter Value" "0: Interrupt generated when FIFO is 1/8th full,1: Interrupt generated when FIFO is 1/4th full,?,?,?,?,?,?" newline bitfld.long 0x0 12. "CFIM,Common FIFO Interrupt Mode" "0: RX FIFO mode: RX interrupt generated when Common..,1: RX FIFO mode: RX interrupt generated at the end.." bitfld.long 0x0 11. "CFITR,Common FIFO Interval Timer Resolution" "0: Reference clock period × 1,1: Reference clock period × 10" newline bitfld.long 0x0 10. "CFITSS,Common FIFO Interval Timer Source Select" "0: Reference clock (× 1 / × 10 period),1: Bit time clock of related channel (FIFO is.." bitfld.long 0x0 8. "CFM,Common FIFO Mode" "0: RX FIFO mode,1: TX FIFO mode" newline bitfld.long 0x0 4.--6. "CFPLS,Common FIFO Payload Data Size Configuration" "0: 8 bytes,1: 12 bytes,?,?,?,?,?,?" bitfld.long 0x0 2. "CFTXIE,Common FIFO TX Interrupt Enable" "0: FIFO interrupt generation disabled for Frame TX,1: FIFO interrupt generation enabled for Frame TX" newline bitfld.long 0x0 1. "CFRXIE,Common FIFO RX Interrupt Enable" "0: FIFO interrupt generation disabled for Frame RX,1: FIFO interrupt generation enabled for Frame RX" bitfld.long 0x0 0. "CFE,Common FIFO Enable" "0: FIFO disabled,1: FIFO enabled" line.long 0x4 "CFDCFSTS,Common FIFO Status Register" hexmask.long.byte 0x4 8.--13. 1. "CFMC,Common FIFO Message Count" bitfld.long 0x4 4. "CFTXIF,Common TX FIFO Interrupt Flag" "0: FIFO interrupt condition not satisfied after..,1: FIFO Interrupt condition satisfied after frame.." newline bitfld.long 0x4 3. "CFRXIF,Common RX FIFO Interrupt Flag" "0: FIFO interrupt condition not satisfied after..,1: FIFO interrupt condition satisfied after frame.." bitfld.long 0x4 2. "CFMLT,Common FIFO Message Lost" "0: Number of message lost in FIFO,1: FIFO message lost" newline rbitfld.long 0x4 1. "CFFLL,Common FIFO Full" "0: FIFO not full,1: FIFO full" rbitfld.long 0x4 0. "CFEMP,Common FIFO Empty" "0: FIFO not empty,1: FIFO empty" wgroup.long 0x5C++0x3 line.long 0x0 "CFDCFPCTR,Common FIFO Pointer Control Register" hexmask.long.byte 0x0 0.--7. 1. "CFPC,Common FIFO Pointer Control" rgroup.long 0x60++0xF line.long 0x0 "CFDFESTS,FIFO Empty Status Register" bitfld.long 0x0 8. "CFEMP,Common FIFO Empty Status" "0: Corresponding FIFO not empty,1: Corresponding FIFO empty" bitfld.long 0x0 0.--1. "RFXEMP,RX FIFO Empty Status" "0: Corresponding FIFO not empty,1: Corresponding FIFO empty,?,?" line.long 0x4 "CFDFFSTS,FIFO Full Status Register" bitfld.long 0x4 8. "CFFLL,Common FIF0 Full Status" "0: Corresponding FIFO not full,1: Corresponding FIFO full" bitfld.long 0x4 0.--1. "RFXFLL,RX FIF0 Full Status" "0: Corresponding FIFO not full,1: Corresponding FIFO full,?,?" line.long 0x8 "CFDFMSTS,FIFO Message Lost Status Register" bitfld.long 0x8 8. "CFMLT,Common FIFO Message Lost Status" "0: Corresponding FIFO Message Lost flag not set,1: Corresponding FIFO Message Lost flag set" bitfld.long 0x8 0.--1. "RFXMLT,RX FIFO Message Lost Status" "0: Corresponding FIFO Message Lost flag not set,1: Corresponding FIFO Message Lost flag set,?,?" line.long 0xC "CFDRFISTS,RX FIFO Interrupt Flag Status Register" bitfld.long 0xC 0.--1. "RFXIF,RX FIFO[x] Interrupt Flag Status" "0: Corresponding RX FIFO Interrupt flag not set,1: Corresponding RX FIFO Interrupt flag set,?,?" repeat 4. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x70)++0x0 line.byte 0x0 "CFDTMC$1,TX Message Buffer Control Registers %s" bitfld.byte 0x0 2. "TMOM,TX Message Buffer One-shot Mode" "0: TX message buffer not configured in one-shot mode,1: TX message buffer configured in one-shot mode" bitfld.byte 0x0 1. "TMTAR,TX Message Buffer Transmission Abort Request" "0: TX message buffer transmission request abort not..,1: TX message buffer transmission request abort.." newline bitfld.byte 0x0 0. "TMTR,TX Message Buffer Transmission Request" "0: TX Message buffer transmission not requested,1: TX message buffer transmission requested" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x74)++0x0 line.byte 0x0 "CFDTMSTS$1,TX Message Buffer Status Registers %s" rbitfld.byte 0x0 4. "TMTARM,TX Message Buffer Transmission Abort Request Mirrored" "0: TX message buffer transmission request abort not..,1: TX message buffer transmission request abort.." rbitfld.byte 0x0 3. "TMTRM,TX Message Buffer Transmission Request Mirrored" "0: TX message buffer transmission not requested,1: TX message buffer transmission requested" newline bitfld.byte 0x0 1.--2. "TMTRF,TX Message Buffer Transmission Result Flag" "0: No result,1: Transmission aborted from the TX message buffer,?,?" rbitfld.byte 0x0 0. "TMTSTS,TX Message Buffer Transmission Status" "0: No on-going transmission,1: On-going transmission" repeat.end rgroup.long 0x78++0xF line.long 0x0 "CFDTMTRSTS,TX Message Buffer Transmission Request Status Register" hexmask.long.byte 0x0 0.--3. 1. "CFDTMTRSTS,TX Message Buffer Transmission Request Status" line.long 0x4 "CFDTMTARSTS,TX Message Buffer Transmission Abort Request Status Register" hexmask.long.byte 0x4 0.--3. 1. "CFDTMTARSTS,TX Message Buffer Transmission Abort Request Status" line.long 0x8 "CFDTMTCSTS,TX Message Buffer Transmission Completion Status Register" hexmask.long.byte 0x8 0.--3. 1. "CFDTMTCSTS,TX Message Buffer Transmission Completion Status" line.long 0xC "CFDTMTASTS,TX Message Buffer Transmission Abort Status Register" hexmask.long.byte 0xC 0.--3. 1. "CFDTMTASTS,TX Message Buffer Transmission Abort Status" group.long 0x88++0xB line.long 0x0 "CFDTMIEC,TX Message Buffer Interrupt Enable Configuration Register" hexmask.long.byte 0x0 0.--3. 1. "TMIEg,TX Message Buffer Interrupt Enable" line.long 0x4 "CFDTXQCC,TX Queue Configuration/Control Register" bitfld.long 0x4 8.--9. "TXQDC,TX Queue Depth Configuration" "0: 0 messages,1: Reserved,?,?" bitfld.long 0x4 7. "TXQIM,TX Queue Interrupt Mode" "0: When the last message is successfully transmitted,1: At every successful transmission" newline bitfld.long 0x4 5. "TXQTXIE,TX Queue TX Interrupt Enable" "0: TX Queue TX interrupt disabled,1: TX Queue TX interrupt enabled" bitfld.long 0x4 0. "TXQE,TX Queue Enable" "0: TX Queue disabled,1: TX Queue enabled" line.long 0x8 "CFDTXQSTS,TX Queue Status Register" rbitfld.long 0x8 8.--10. "TXQMC,TX Queue Message Count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 2. "TXQTXIF,TX Queue TX Interrupt Flag" "0: TX Queue interrupt condition not satisfied after..,1: TX Queue interrupt condition satisfied after a.." newline rbitfld.long 0x8 1. "TXQFLL,TX Queue Full" "0: TX Queue not full,1: TX Queue full" rbitfld.long 0x8 0. "TXQEMP,TX Queue Empty" "0: TX Queue not empty,1: TX Queue empty" wgroup.long 0x94++0x3 line.long 0x0 "CFDTXQPCTR,TX Queue Pointer Control Register" hexmask.long.byte 0x0 0.--7. 1. "TXQPC,TX Queue Pointer Control" group.long 0x98++0x7 line.long 0x0 "CFDTHLCC,TX History List Configuration/Control Register" bitfld.long 0x0 10. "THLDTE,TX History List Dedicated TX Enable" "0: TX FIFO + TX Queue,1: Flat TX MB + TX FIFO + TX Queue" bitfld.long 0x0 9. "THLIM,TX History List Interrupt Mode" "0: Interrupt generated if TX History List level..,1: Interrupt generated for every successfully.." newline bitfld.long 0x0 8. "THLIE,TX History List Interrupt Enable" "0: TX History List Interrupt disabled,1: TX History List Interrupt enabled" bitfld.long 0x0 0. "THLE,TX History List Enable" "0: TX History List disabled,1: TX History List enabled" line.long 0x4 "CFDTHLSTS,TX History List Status Register" hexmask.long.byte 0x4 8.--11. 1. "THLMC,TX History List Message Count" bitfld.long 0x4 3. "THLIF,TX History List Interrupt Flag" "0: TX History List interrupt condition not satisfied,1: TX History List interrupt condition satisfied" newline bitfld.long 0x4 2. "THLELT,TX History List Entry Lost" "0: No entry lost in TX History List,1: TX History List entry Lost" rbitfld.long 0x4 1. "THLFLL,TX History List Full" "0: TX History List not full,1: TX History List full" newline rbitfld.long 0x4 0. "THLEMP,TX History List Empty" "0: TX History List not empty,1: TX History List empty" wgroup.long 0xA0++0x3 line.long 0x0 "CFDTHLPCTR,TX History List Pointer Control Register" hexmask.long.byte 0x0 0.--7. 1. "THLPC,TX History List Pointer Control" rgroup.long 0xA4++0x3 line.long 0x0 "CFDGTINTSTS,Global TX Interrupt Status Register" bitfld.long 0x0 4. "THIF0,TX History List Interrupt" "0: Channel n TX History List Interrupt flag not set,1: Channel n TX History List Interrupt flag set" bitfld.long 0x0 3. "CFTIF0,COM FIFO TX Mode Interrupt Flag" "0: Channel n COM FIFO TX Mode Interrupt flag not set,1: Channel n COM FIFO TX Mode Interrupt flag set" newline bitfld.long 0x0 2. "TQIF0,TX Queue Interrupt Flag" "0: Channel n TX Queue Interrupt flag not set,1: Channel n TX Queue Interrupt flag set" bitfld.long 0x0 1. "TAI0,TX Abort Interrupt Flag" "0: Channel n TX Abort Interrupt flag not set,1: Channel n TX Abort Interrupt flag set" newline bitfld.long 0x0 0. "TSIF0,TX Successful Interrupt Flag" "0: Channel n TX Successful Interrupt flag not set,1: Channel n TX Successful Interrupt flag set" group.long 0xA8++0xB line.long 0x0 "CFDGTSTCFG,Global Test Configuration Register" hexmask.long.byte 0x0 16.--19. 1. "RTMPS,RAM Test Mode Page Select" line.long 0x4 "CFDGTSTCTR,Global Test Control Register" bitfld.long 0x4 2. "RTME,RAM Test Mode Enable" "0: RAM test mode disabled,1: RAM test mode enabled" line.long 0x8 "CFDGFDCFG,Global FD Configuration Register" bitfld.long 0x8 8.--9. "TSCCFG,Timestamp Capture Configuration" "0: Timestamp capture at the sample point of SOF..,1: Timestamp capture at frame valid indication,?,?" bitfld.long 0x8 0. "RPED,RES Bit Protocol Exception Disable" "0: Protocol exception event detection enabled,1: Protocol exception event detection disabled" wgroup.long 0xB8++0x3 line.long 0x0 "CFDGLOCKK,Global Lock Key Register" hexmask.long.word 0x0 0.--15. 1. "LOCK,Lock Key" group.long 0xC0++0xB line.long 0x0 "CFDGAFLIGNENT,Global AFL Ignore Entry Register" hexmask.long.byte 0x0 0.--3. 1. "IRN,Ignore Rule Number" line.long 0x4 "CFDGAFLIGNCTR,Global AFL Ignore Control Register" hexmask.long.byte 0x4 8.--15. 1. "KEY,Key Code" bitfld.long 0x4 0. "IREN,Ignore Rule Enable" "0: AFL entry number is not ignored,1: AFL entry number is ignored" line.long 0x8 "CFDCDTCT,DMA Transfer Control Register" bitfld.long 0x8 8. "CFDMAE,DMA Transfer Enable for Common FIFO 0" "0: DMA transfer request disabled,1: DMA transfer request enabled" bitfld.long 0x8 1. "RFDMAE1,DMA Transfer Enable for RXFIFO 1" "0: DMA transfer request disabled,1: DMA transfer request enabled" newline bitfld.long 0x8 0. "RFDMAE0,DMA Transfer Enable for RXFIFO 0" "0: DMA transfer request disabled,1: DMA transfer request enabled" rgroup.long 0xCC++0x3 line.long 0x0 "CFDCDTSTS,DMA Transfer Status Register" bitfld.long 0x0 8. "CFDMASTS,DMA Transfer Status only for Common FIFO" "0: DMA transfer stopped,1: DMA transfer on going" bitfld.long 0x0 1. "RFDMASTS1,DMA Transfer Status for RX FIFO 1" "0: DMA transfer stopped,1: DMA transfer on going" newline bitfld.long 0x0 0. "RFDMASTS0,DMA Transfer Status for RX FIFO 0" "0: DMA transfer stopped,1: DMA transfer on going" group.long 0xD8++0x3 line.long 0x0 "CFDGRSTC,Global SW reset Register" hexmask.long.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.long 0x0 0. "SRST,SW Reset" "0: Normal state,1: SW reset state" group.long 0x100++0xF line.long 0x0 "CFDC0DCFG,Data Bitrate Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "DSJW,Resynchronization Jump Width" hexmask.long.byte 0x0 16.--19. 1. "DTSEG2,Timing Segment 2" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Timing Segment 1" hexmask.long.byte 0x0 0.--7. 1. "DBRP,Channel Data Baud Rate Prescaler" line.long 0x4 "CFDC0FDCFG,CANFD Configuration Register" bitfld.long 0x4 30. "CLOE,Classical CAN Enable" "0: Classical CAN mode disabled,1: Classical CAN mode enabled" bitfld.long 0x4 29. "REFE,RX Edge Filter Enable" "0: RX edge filter disabled,1: RX edge filter enabled" newline bitfld.long 0x4 28. "FDOE,FD-Only Enable" "0: FD-only mode disabled,1: FD-only mode enabled" hexmask.long.byte 0x4 16.--23. 1. "TDCO,Transceiver Delay Compensation Offset" newline bitfld.long 0x4 10. "ESIC,Error State Indication Configuration" "0: The ESI bit in the frame represents the error..,1: The ESI bit in the frame represents the error.." bitfld.long 0x4 9. "TDCE,Transceiver Delay Compensation Enable" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled" newline bitfld.long 0x4 8. "TDCOC,Transceiver Delay Compensation Offset Configuration" "0: Measured + offset,1: Offset-only" bitfld.long 0x4 0.--2. "EOCCFG,Error Occurrence Counter Configuration" "0: All transmitter or receiver CAN frames,1: All transmitter CAN frames,?,?,?,?,?,?" line.long 0x8 "CFDC0FDCTR,CANFD Control Register" bitfld.long 0x8 1. "SOCCLR,Successful Occurrence Counter Clear" "0: No successful occurrence counter clear,1: Clear successful occurrence counter" bitfld.long 0x8 0. "EOCCLR,Error Occurrence Counter Clear" "0: No error occurrence counter clear,1: Clear error occurrence counter" line.long 0xC "CFDC0FDSTS,CANFD Status Register" hexmask.long.byte 0xC 24.--31. 1. "SOC,Successful occurrence counter" hexmask.long.byte 0xC 16.--23. 1. "EOC,Error Occurrence Counter" newline bitfld.long 0xC 15. "TDCVF,Transceiver Delay Compensation Violation Flag" "0: Transceiver delay compensation violation has not..,1: Transceiver delay compensation violation has.." bitfld.long 0xC 9. "SOCO,Successful Occurrence Counter Overflow" "0: Successful occurrence counter has not overflowed,1: Successful occurrence counter has overflowed" newline bitfld.long 0xC 8. "EOCO,Error Occurrence Counter Overflow" "0: Error occurrence counter has not overflowed,1: Error occurrence counter has overflowed" hexmask.long.byte 0xC 0.--7. 1. "TDCR,Transceiver Delay Compensation Result" rgroup.long 0x110++0x3 line.long 0x0 "CFDC0FDCRC,CANFD CRC Register" hexmask.long.byte 0x0 24.--27. 1. "SCNT,Stuff bit count" hexmask.long.tbyte 0x0 0.--20. 1. "CRCREG,CRC Register value" repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x120)++0x3 line.long 0x0 "CFDGAFLID$1,Global Acceptance Filter List ID Registers" bitfld.long 0x0 31. "GAFLIDE,Global Acceptance Filter List Entry IDE Field" "0: Standard identifier of rule entry ID is valid..,1: Extended identifier of rule entry ID is valid.." bitfld.long 0x0 30. "GAFLRTR,Global Acceptance Filter List Entry RTR Field" "0: Data frame,1: Remote frame" newline bitfld.long 0x0 29. "GAFLLB,Global Acceptance Filter List Entry Loopback Configuration" "0: Global Acceptance Filter List entry ID for..,1: Global Acceptance Filter List entry ID for.." hexmask.long 0x0 0.--28. 1. "GAFLID,Global Acceptance Filter List Entry ID Field" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x124)++0x3 line.long 0x0 "CFDGAFLM$1,Global Acceptance Filter List Mask Registers" bitfld.long 0x0 31. "GAFLIDEM,Global Acceptance Filter List IDE Mask" "0: IDE bit is not used for ID matching,1: IDE bit is used for ID matching" bitfld.long 0x0 30. "GAFLRTRM,Global Acceptance Filter List Entry RTR Mask" "0: RTR bit is not used for ID matching,1: RTR bit is used for ID matching" newline bitfld.long 0x0 29. "GAFLIFL1,Global Acceptance Filter List Information Label 1" "0,1" hexmask.long 0x0 0.--28. 1. "GAFLIDM,Global Acceptance Filter List ID Mask Field" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x128)++0x3 line.long 0x0 "CFDGAFLP0$1,Global Acceptance Filter List Pointer 0 Registers" hexmask.long.word 0x0 16.--31. 1. "GAFLPTR,Global Acceptance Filter List Pointer" bitfld.long 0x0 15. "GAFLRMV,Global Acceptance Filter List RX Message Buffer Valid" "0: Single message buffer direction pointer is invalid,1: Single message buffer direction pointer is valid" newline hexmask.long.byte 0x0 8.--12. 1. "GAFLRMDP,Global Acceptance Filter List RX Message Buffer Direction Pointer" bitfld.long 0x0 7. "GAFLIFL0,Global Acceptance Filter List Information Label 0" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "GAFLDLC,Global Acceptance Filter List DLC Field" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x12C)++0x3 line.long 0x0 "CFDGAFLP1$1,Global Acceptance Filter List Pointer 1 Registers" bitfld.long 0x0 8. "GAFLFDP8,Global Acceptance Filter List FIFO Direction Pointer" "0: Disable Common FIFO as target for reception,1: Enable Common FIFO as target for reception" bitfld.long 0x0 1. "GAFLFDP1,Global Acceptance Filter List FIFO Direction Pointer" "0: Disable RX FIFO 1 as target for reception,1: Enable RX FIFO 1 as target for reception" newline bitfld.long 0x0 0. "GAFLFDP0,Global Acceptance Filter List FIFO Direction Pointer" "0: Disable RX FIFO 0 as target for reception,1: Enable RX FIFO 0 as target for reception" repeat.end repeat 64. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x280)++0x3 line.long 0x0 "CFDRPGACC$1,RAM Test Page Access Registers %s" hexmask.long 0x0 0.--31. 1. "RDTA,RAM Data Test Access" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x520)++0x3 line.long 0x0 "CFDRFID$1,RX FIFO Access ID Register %s" bitfld.long 0x0 31. "RFIDE,RX FIFO Buffer IDE bit" "0: STD-ID has been received,1: EXT-ID has been received" bitfld.long 0x0 30. "RFRTR,RX FIFO Buffer RTR bit" "0: Data frame,1: Remote frame" newline hexmask.long 0x0 0.--28. 1. "RFID,RX FIFO Buffer ID Field" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x524)++0x3 line.long 0x0 "CFDRFPTR$1,RX FIFO Access Pointer Register %s" hexmask.long.byte 0x0 28.--31. 1. "RFDLC,RX FIFO Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RFTS,RX FIFO Timestamp Value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x528)++0x3 line.long 0x0 "CFDRFFDSTS$1,RX FIFO Access CANFD Status Register %s" hexmask.long.word 0x0 16.--31. 1. "CFDRFPTR,RX FIFO Buffer Pointer Field" bitfld.long 0x0 8.--9. "RFIFL,RX FIFO Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RFFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RFBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RFESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x52C)++0x3 line.long 0x0 "CFDRFDF$1_0,RX FIFO Access Data Field 0 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x530)++0x3 line.long 0x0 "CFDRFDF$1_1,RX FIFO Access Data Field 1 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x534)++0x3 line.long 0x0 "CFDRFDF$1_2,RX FIFO Access Data Field 2 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x538)++0x3 line.long 0x0 "CFDRFDF$1_3,RX FIFO Access Data Field 3 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x53C)++0x3 line.long 0x0 "CFDRFDF$1_4,RX FIFO Access Data Field 4 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x540)++0x3 line.long 0x0 "CFDRFDF$1_5,RX FIFO Access Data Field 5 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x544)++0x3 line.long 0x0 "CFDRFDF$1_6,RX FIFO Access Data Field 6 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x548)++0x3 line.long 0x0 "CFDRFDF$1_7,RX FIFO Access Data Field 7 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x54C)++0x3 line.long 0x0 "CFDRFDF$1_8,RX FIFO Access Data Field 8 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x550)++0x3 line.long 0x0 "CFDRFDF$1_9,RX FIFO Access Data Field 9 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x554)++0x3 line.long 0x0 "CFDRFDF$1_10,RX FIFO Access Data Field 10 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x558)++0x3 line.long 0x0 "CFDRFDF$1_11,RX FIFO Access Data Field 11 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x55C)++0x3 line.long 0x0 "CFDRFDF$1_12,RX FIFO Access Data Field 12 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x560)++0x3 line.long 0x0 "CFDRFDF$1_13,RX FIFO Access Data Field 13 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x564)++0x3 line.long 0x0 "CFDRFDF$1_14,RX FIFO Access Data Field 14 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x568)++0x3 line.long 0x0 "CFDRFDF$1_15,RX FIFO Access Data Field 15 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end group.long 0x5B8++0xB line.long 0x0 "CFDCFID,Common FIFO Access ID Register" bitfld.long 0x0 31. "CFIDE,Common FIFO Buffer IDE Bit" "0: STD-ID will be transmitted or has been received,1: EXT-ID will be transmitted or has been received" bitfld.long 0x0 30. "CFRTR,Common FIFO Buffer RTR Bit" "0: Data Frame,1: Remote Frame" newline bitfld.long 0x0 29. "THLEN,THL Entry enable" "0: Entry will not be stored in THL after successful..,1: Entry will be stored in THL after successful TX." hexmask.long 0x0 0.--28. 1. "CFID,Common FIFO Buffer ID Field" line.long 0x4 "CFDCFPTR,Common FIFO Access Pointer Register" hexmask.long.byte 0x4 28.--31. 1. "CFDLC,Common FIFO Buffer DLC Field" hexmask.long.word 0x4 0.--15. 1. "CFTS,Common FIFO Timestamp Value" line.long 0x8 "CFDCFFDCSTS,Common FIFO Access CANFD Control/Status Register" hexmask.long.word 0x8 16.--31. 1. "CFPTR,Common FIFO Buffer Pointer Field" bitfld.long 0x8 8.--9. "CFIFL,COMMON FIFO Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x8 2. "CFFDF,CAN FD Format bit" "0: Non CANFD frame received or to transmit,1: CANFD frame received or to transmit" bitfld.long 0x8 1. "CFBRS,Bit Rate Switch bit" "0: CANFD frame received or to transmit with no bit..,1: CANFD frame received or to transmit with bit.." newline bitfld.long 0x8 0. "CFESI,Error State Indicator bit" "0: CANFD frame received or to transmit by error..,1: CANFD frame received or to transmit by error.." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5C4)++0x3 line.long 0x0 "CFDCFDF$1,Common FIFO Access Data Field %s Registers" hexmask.long.byte 0x0 24.--31. 1. "CFDB_HH,Common FIFO Buffer Data Bytes ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "CFDB_HL,Common FIFO Buffer Data Bytes ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "CFDB_LH,Common FIFO Buffer Data Bytes ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "CFDB_LL,Common FIFO Buffer Data Bytes (p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x604)++0x3 line.long 0x0 "CFDTMID$1,TX Message Buffer ID Registers" bitfld.long 0x0 31. "TMIDE,TX Message Buffer IDE bit" "0: STD-ID is transmitted,1: EXT-ID is transmitted" bitfld.long 0x0 30. "TMRTR,TX Message Buffer RTR bit" "0: Data frame,1: Remote frame" newline bitfld.long 0x0 29. "THLEN,Tx History List Entry" "0: Entry not stored in THL after successful TX,1: Entry stored in THL after successful TX" hexmask.long 0x0 0.--28. 1. "TMID,TX Message Buffer ID Field" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x608)++0x3 line.long 0x0 "CFDTMPTR$1,TX Message Buffer Pointer Register" hexmask.long.byte 0x0 28.--31. 1. "TMDLC,TX Message Buffer DLC Field" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x60C)++0x3 line.long 0x0 "CFDTMFDCTR$1,TX Message Buffer CANFD Control Register" hexmask.long.word 0x0 16.--31. 1. "TMPTR,TX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "TMIFL,TX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "TMFDF,CAN FD Format bit" "0: Non CANFD frame to transmit,1: CANFD frame to transmit" bitfld.long 0x0 1. "TMBRS,Bit Rate Switch bit" "0: CANFD frame to transmit with no bit rate switch,1: CANFD frame to transmit with bit rate switch" newline bitfld.long 0x0 0. "TMESI,Error State Indicator bit" "0: CANFD frame to transmit by error active node,1: CANFD frame to transmit by error passive node" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x610)++0x3 line.long 0x0 "CFDTMDF$1_0,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x614)++0x3 line.long 0x0 "CFDTMDF$1_1,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x618)++0x3 line.long 0x0 "CFDTMDF$1_2,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x61C)++0x3 line.long 0x0 "CFDTMDF$1_3,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x620)++0x3 line.long 0x0 "CFDTMDF$1_4,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x624)++0x3 line.long 0x0 "CFDTMDF$1_5,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x628)++0x3 line.long 0x0 "CFDTMDF$1_6,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x62C)++0x3 line.long 0x0 "CFDTMDF$1_7,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x630)++0x3 line.long 0x0 "CFDTMDF$1_8,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x634)++0x3 line.long 0x0 "CFDTMDF$1_9,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x638)++0x3 line.long 0x0 "CFDTMDF$1_10,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x63C)++0x3 line.long 0x0 "CFDTMDF$1_11,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x640)++0x3 line.long 0x0 "CFDTMDF$1_12,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x644)++0x3 line.long 0x0 "CFDTMDF$1_13,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x648)++0x3 line.long 0x0 "CFDTMDF$1_14,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x64C)++0x3 line.long 0x0 "CFDTMDF$1_15,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end rgroup.long 0x740++0x7 line.long 0x0 "CFDTHLACC0,TX History List Access Register 0" hexmask.long.word 0x0 16.--31. 1. "TMTS,Transmit Timestamp" bitfld.long 0x0 3.--4. "BN,Buffer Number" "0,1,2,3" newline bitfld.long 0x0 0.--2. "BT,Buffer Type" "?,1: Flat TX message buffer,?,?,?,?,?,?" line.long 0x4 "CFDTHLACC1,TX History List Access Register 1" bitfld.long 0x4 16.--17. "TIFL,Transmit Information Label" "0,1,2,3" hexmask.long.word 0x4 0.--15. 1. "TID,Transmit ID" repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x920)++0x3 line.long 0x0 "CFDRMID$1,RX Message Buffer ID Registers" bitfld.long 0x0 31. "RMIDE,RX Message Buffer IDE Bit" "0: STD-ID is stored,1: EXT-ID is stored" bitfld.long 0x0 30. "RMRTR,RX Message Buffer RTR Bit" "0: Data frame,1: Remote frame" newline hexmask.long 0x0 0.--28. 1. "RMID,RX Message Buffer ID Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x924)++0x3 line.long 0x0 "CFDRMPTR$1,RX Message Buffer Pointer Registers" hexmask.long.byte 0x0 28.--31. 1. "RMDLC,RX Message Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RMTS,RX Message Buffer Timestamp Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x928)++0x3 line.long 0x0 "CFDRMFDSTS$1,RX Message Buffer CANFD Status Registers" hexmask.long.word 0x0 16.--31. 1. "RMPTR,RX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "RMIFL,RX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RMFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RMBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RMESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x92C)++0x3 line.long 0x0 "CFDRMDF$1_0,RX Message Buffer Data Field 0 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x930)++0x3 line.long 0x0 "CFDRMDF$1_1,RX Message Buffer Data Field 1 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x934)++0x3 line.long 0x0 "CFDRMDF$1_2,RX Message Buffer Data Field 2 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x938)++0x3 line.long 0x0 "CFDRMDF$1_3,RX Message Buffer Data Field 3 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x93C)++0x3 line.long 0x0 "CFDRMDF$1_4,RX Message Buffer Data Field 4 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x940)++0x3 line.long 0x0 "CFDRMDF$1_5,RX Message Buffer Data Field 5 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x944)++0x3 line.long 0x0 "CFDRMDF$1_6,RX Message Buffer Data Field 6 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x948)++0x3 line.long 0x0 "CFDRMDF$1_7,RX Message Buffer Data Field 7 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x94C)++0x3 line.long 0x0 "CFDRMDF$1_8,RX Message Buffer Data Field 8 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x950)++0x3 line.long 0x0 "CFDRMDF$1_9,RX Message Buffer Data Field 9 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x954)++0x3 line.long 0x0 "CFDRMDF$1_10,RX Message Buffer Data Field 10 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x958)++0x3 line.long 0x0 "CFDRMDF$1_11,RX Message Buffer Data Field 11 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x95C)++0x3 line.long 0x0 "CFDRMDF$1_12,RX Message Buffer Data Field 12 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x960)++0x3 line.long 0x0 "CFDRMDF$1_13,RX Message Buffer Data Field 13 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x964)++0x3 line.long 0x0 "CFDRMDF$1_14,RX Message Buffer Data Field 14 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x968)++0x3 line.long 0x0 "CFDRMDF$1_15,RX Message Buffer Data Field 15 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD20)++0x3 line.long 0x0 "CFDRMID$1,RX Message Buffer ID Registers" bitfld.long 0x0 31. "RMIDE,RX Message Buffer IDE Bit" "0: STD-ID is stored,1: EXT-ID is stored" bitfld.long 0x0 30. "RMRTR,RX Message Buffer RTR Bit" "0: Data frame,1: Remote frame" newline hexmask.long 0x0 0.--28. 1. "RMID,RX Message Buffer ID Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD24)++0x3 line.long 0x0 "CFDRMPTR$1,RX Message Buffer Pointer Registers" hexmask.long.byte 0x0 28.--31. 1. "RMDLC,RX Message Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RMTS,RX Message Buffer Timestamp Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD28)++0x3 line.long 0x0 "CFDRMFDSTS$1,RX Message Buffer CANFD Status Registers" hexmask.long.word 0x0 16.--31. 1. "RMPTR,RX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "RMIFL,RX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RMFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RMBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RMESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD2C)++0x3 line.long 0x0 "CFDRMDF$1_0,RX Message Buffer Data Field 0 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD30)++0x3 line.long 0x0 "CFDRMDF$1_1,RX Message Buffer Data Field 1 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD34)++0x3 line.long 0x0 "CFDRMDF$1_2,RX Message Buffer Data Field 2 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD38)++0x3 line.long 0x0 "CFDRMDF$1_3,RX Message Buffer Data Field 3 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD3C)++0x3 line.long 0x0 "CFDRMDF$1_4,RX Message Buffer Data Field 4 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD40)++0x3 line.long 0x0 "CFDRMDF$1_5,RX Message Buffer Data Field 5 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD44)++0x3 line.long 0x0 "CFDRMDF$1_6,RX Message Buffer Data Field 6 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD48)++0x3 line.long 0x0 "CFDRMDF$1_7,RX Message Buffer Data Field 7 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD4C)++0x3 line.long 0x0 "CFDRMDF$1_8,RX Message Buffer Data Field 8 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD50)++0x3 line.long 0x0 "CFDRMDF$1_9,RX Message Buffer Data Field 9 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD54)++0x3 line.long 0x0 "CFDRMDF$1_10,RX Message Buffer Data Field 10 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD58)++0x3 line.long 0x0 "CFDRMDF$1_11,RX Message Buffer Data Field 11 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD5C)++0x3 line.long 0x0 "CFDRMDF$1_12,RX Message Buffer Data Field 12 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD60)++0x3 line.long 0x0 "CFDRMDF$1_13,RX Message Buffer Data Field 13 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD64)++0x3 line.long 0x0 "CFDRMDF$1_14,RX Message Buffer Data Field 14 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD68)++0x3 line.long 0x0 "CFDRMDF$1_15,RX Message Buffer Data Field 15 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1124)++0x3 line.long 0x0 "CFDRMPTR$1,RX Message Buffer Pointer Registers" hexmask.long.byte 0x0 28.--31. 1. "RMDLC,RX Message Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RMTS,RX Message Buffer Timestamp Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1128)++0x3 line.long 0x0 "CFDRMFDSTS$1,RX Message Buffer CANFD Status Registers" hexmask.long.word 0x0 16.--31. 1. "RMPTR,RX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "RMIFL,RX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RMFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RMBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RMESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x112C)++0x3 line.long 0x0 "CFDRMDF$1_0,RX Message Buffer Data Field 0 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1130)++0x3 line.long 0x0 "CFDRMDF$1_1,RX Message Buffer Data Field 1 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1134)++0x3 line.long 0x0 "CFDRMDF$1_2,RX Message Buffer Data Field 2 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1138)++0x3 line.long 0x0 "CFDRMDF$1_3,RX Message Buffer Data Field 3 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x113C)++0x3 line.long 0x0 "CFDRMDF$1_4,RX Message Buffer Data Field 4 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1140)++0x3 line.long 0x0 "CFDRMDF$1_5,RX Message Buffer Data Field 5 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1144)++0x3 line.long 0x0 "CFDRMDF$1_6,RX Message Buffer Data Field 6 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1148)++0x3 line.long 0x0 "CFDRMDF$1_7,RX Message Buffer Data Field 7 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x114C)++0x3 line.long 0x0 "CFDRMDF$1_8,RX Message Buffer Data Field 8 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1150)++0x3 line.long 0x0 "CFDRMDF$1_9,RX Message Buffer Data Field 9 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1154)++0x3 line.long 0x0 "CFDRMDF$1_10,RX Message Buffer Data Field 10 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1158)++0x3 line.long 0x0 "CFDRMDF$1_11,RX Message Buffer Data Field 11 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x115C)++0x3 line.long 0x0 "CFDRMDF$1_12,RX Message Buffer Data Field 12 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1160)++0x3 line.long 0x0 "CFDRMDF$1_13,RX Message Buffer Data Field 13 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1164)++0x3 line.long 0x0 "CFDRMDF$1_14,RX Message Buffer Data Field 14 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1168)++0x3 line.long 0x0 "CFDRMDF$1_15,RX Message Buffer Data Field 15 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1524)++0x3 line.long 0x0 "CFDRMPTR$1,RX Message Buffer Pointer Registers" hexmask.long.byte 0x0 28.--31. 1. "RMDLC,RX Message Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RMTS,RX Message Buffer Timestamp Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1528)++0x3 line.long 0x0 "CFDRMFDSTS$1,RX Message Buffer CANFD Status Registers" hexmask.long.word 0x0 16.--31. 1. "RMPTR,RX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "RMIFL,RX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RMFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RMBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RMESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x152C)++0x3 line.long 0x0 "CFDRMDF$1_0,RX Message Buffer Data Field 0 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1530)++0x3 line.long 0x0 "CFDRMDF$1_1,RX Message Buffer Data Field 1 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1534)++0x3 line.long 0x0 "CFDRMDF$1_2,RX Message Buffer Data Field 2 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1538)++0x3 line.long 0x0 "CFDRMDF$1_3,RX Message Buffer Data Field 3 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x153C)++0x3 line.long 0x0 "CFDRMDF$1_4,RX Message Buffer Data Field 4 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1540)++0x3 line.long 0x0 "CFDRMDF$1_5,RX Message Buffer Data Field 5 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1544)++0x3 line.long 0x0 "CFDRMDF$1_6,RX Message Buffer Data Field 6 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1548)++0x3 line.long 0x0 "CFDRMDF$1_7,RX Message Buffer Data Field 7 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x154C)++0x3 line.long 0x0 "CFDRMDF$1_8,RX Message Buffer Data Field 8 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1550)++0x3 line.long 0x0 "CFDRMDF$1_9,RX Message Buffer Data Field 9 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1554)++0x3 line.long 0x0 "CFDRMDF$1_10,RX Message Buffer Data Field 10 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1558)++0x3 line.long 0x0 "CFDRMDF$1_11,RX Message Buffer Data Field 11 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x155C)++0x3 line.long 0x0 "CFDRMDF$1_12,RX Message Buffer Data Field 12 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1560)++0x3 line.long 0x0 "CFDRMDF$1_13,RX Message Buffer Data Field 13 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1564)++0x3 line.long 0x0 "CFDRMDF$1_14,RX Message Buffer Data Field 14 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1568)++0x3 line.long 0x0 "CFDRMDF$1_15,RX Message Buffer Data Field 15 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end tree.end tree "CANFD1" base ad:0x40382000 group.long 0x0++0xF line.long 0x0 "CFDC0NCFG,Nominal Bitrate Configuration Register" hexmask.long.byte 0x0 25.--31. 1. "NTSEG2,Timing Segment 2" hexmask.long.byte 0x0 17.--24. 1. "NTSEG1,Timing Segment 1" newline hexmask.long.byte 0x0 10.--16. 1. "NSJW,Resynchronization Jump Width" hexmask.long.word 0x0 0.--9. 1. "NBRP,Channel Nominal Baud Rate Prescaler" line.long 0x4 "CFDC0CTR,Control Register" bitfld.long 0x4 31. "ROM,Restricted Operation Mode" "0: Restricted operation mode disabled,1: Restricted operation mode enabled" bitfld.long 0x4 30. "BFT,Bit Flip Test" "0: First data bit of reception stream not inverted,1: First data bit of reception stream inverted" newline bitfld.long 0x4 25.--26. "CTMS,Channel Test Mode Select" "0: Basic test mode,1: Listen-only mode,?,?" bitfld.long 0x4 24. "CTME,Channel Test Mode Enable" "0: Channel test mode disabled,1: Channel test mode enabled" newline bitfld.long 0x4 23. "ERRD,Channel Error Display" "0: Only the first set of error codes displayed,1: Accumulated error codes displayed" bitfld.long 0x4 21.--22. "BOM,Channel Bus-Off Mode" "0: Normal mode (comply with ISO 11898-1),1: Entry to Halt mode automatically at bus-off start,?,?" newline bitfld.long 0x4 19. "TDCVFIE,Transceiver Delay Compensation Violation Interrupt Enable" "0: Transceiver delay compensation violation..,1: Transceiver delay compensation violation.." bitfld.long 0x4 18. "SOCOIE,Successful Occurrence Counter Overflow Interrupt Enable" "0: Successful occurrence counter overflow interrupt..,1: Successful occurrence counter overflow interrupt.." newline bitfld.long 0x4 17. "EOCOIE,Error Occurrence Counter Overflow Interrupt Enable" "0: Error occurrence counter overflow interrupt..,1: Error occurrence counter overflow interrupt.." bitfld.long 0x4 16. "TAIE,Transmission Abort Interrupt Enable" "0: TX abort interrupt disabled,1: TX abort interrupt enabled" newline bitfld.long 0x4 15. "ALIE,Arbitration Lost Interrupt Enable" "0: Arbitration lost interrupt disabled,1: Arbitration lost interrupt enabled" bitfld.long 0x4 14. "BLIE,Bus Lock Interrupt Enable" "0: Bus lock interrupt disabled,1: Bus lock interrupt enabled" newline bitfld.long 0x4 13. "OLIE,Overload Interrupt Enable" "0: Overload interrupt disabled,1: Overload interrupt enabled" bitfld.long 0x4 12. "BORIE,Bus-Off Recovery Interrupt Enable" "0: Bus-off recovery interrupt disabled,1: Bus-off recovery interrupt enabled" newline bitfld.long 0x4 11. "BOEIE,Bus-Off Entry Interrupt Enable" "0: Bus-off entry interrupt disabled,1: Bus-off entry interrupt enabled" bitfld.long 0x4 10. "EPIE,Error Passive Interrupt Enable" "0: Error passive interrupt disabled,1: Error passive interrupt enabled" newline bitfld.long 0x4 9. "EWIE,Error Warning Interrupt Enable" "0: Error warning interrupt disabled,1: Error warning interrupt enabled" bitfld.long 0x4 8. "BEIE,Bus Error Interrupt Enable" "0: Bus error interrupt disabled,1: Bus error interrupt enabled" newline bitfld.long 0x4 3. "RTBO,Return from Bus-Off" "0: Channel is not forced to return from bus-off,1: Channel is forced to return from bus-off" bitfld.long 0x4 2. "CSLPR,Channel Sleep Request" "0: Channel sleep request disabled,1: Channel sleep request enabled" newline bitfld.long 0x4 0.--1. "CHMDC,Channel Mode Control" "0: Channel operation mode request,1: Channel reset request,?,?" line.long 0x8 "CFDC0STS,Status Register" hexmask.long.byte 0x8 24.--31. 1. "TEC,Transmission Error Count" hexmask.long.byte 0x8 16.--23. 1. "REC,Reception Error Count" newline bitfld.long 0x8 8. "ESIF,Error State Indication Flag" "0: No CANFD message has been received when the ESI..,1: At least one CANFD message was received when the.." rbitfld.long 0x8 7. "COMSTS,Channel Communication Status" "0: Channel is not ready for communication,1: Channel is ready for communication" newline rbitfld.long 0x8 6. "RECSTS,Channel Receive Status" "0: Channel is not receiving,1: Channel is receiving" rbitfld.long 0x8 5. "TRMSTS,Channel Transmit Status" "0: Channel is not transmitting,1: Channel is transmitting" newline rbitfld.long 0x8 4. "BOSTS,Channel Bus-Off Status" "0: Channel not in bus-off state,1: Channel in bus-off state" rbitfld.long 0x8 3. "EPSTS,Channel Error Passive Status" "0: Channel not in error passive state,1: Channel in error passive state" newline rbitfld.long 0x8 2. "CSLPSTS,Channel Sleep Status" "0: Channel not in Sleep mode,1: Channel in Sleep mode" rbitfld.long 0x8 1. "CHLTSTS,Channel Halt Status" "0: Channel not in Halt mode,1: Channel in Halt mode" newline rbitfld.long 0x8 0. "CRSTSTS,Channel Reset Status" "0: Channel not in Reset mode,1: Channel in Reset mode" line.long 0xC "CFDC0ERFL,Error Flag Register" hexmask.long.word 0xC 16.--30. 1. "CRCREG,CRC Register value" bitfld.long 0xC 14. "ADERR,Acknowledge Delimiter Error" "0: Channel acknowledge delimiter error not detected,1: Channel acknowledge delimiter error detected" newline bitfld.long 0xC 13. "B0ERR,Bit 0 Error" "0: Channel bit 0 error not detected,1: Channel bit 0 error detected" bitfld.long 0xC 12. "B1ERR,Bit 1 Error" "0: Channel bit 1 error not detected,1: Channel bit 1 error detected" newline bitfld.long 0xC 11. "CERR,CRC Error" "0: Channel CRC error not detected,1: Channel CRC error detected" bitfld.long 0xC 10. "AERR,Acknowledge Error" "0: Channel acknowledge error not detected,1: Channel acknowledge error detected" newline bitfld.long 0xC 9. "FERR,Form Error" "0: Channel form error not detected,1: Channel form error detected" bitfld.long 0xC 8. "SERR,Stuff Error" "0: Channel stuff error not detected,1: Channel stuff error detected" newline bitfld.long 0xC 7. "ALF,Arbitration Lost Flag" "0: Channel arbitration lost not detected,1: Channel arbitration lost detected" bitfld.long 0xC 6. "BLF,Bus Lock Flag" "0: Channel bus lock not detected,1: Channel bus lock detected" newline bitfld.long 0xC 5. "OVLF,Overload Flag" "0: Channel overload not detected,1: Channel overload detected" bitfld.long 0xC 4. "BORF,Bus-Off Recovery Flag" "0: Channel bus-off recovery not detected,1: Channel bus-off recovery detected" newline bitfld.long 0xC 3. "BOEF,Bus-Off Entry Flag" "0: Channel bus-off entry not detected,1: Channel bus-off entry detected" bitfld.long 0xC 2. "EPF,Error Passive Flag" "0: Channel error passive not detected,1: Channel error passive detected" newline bitfld.long 0xC 1. "EWF,Error Warning Flag" "0: Channel error warning not detected,1: Channel error warning detected" bitfld.long 0xC 0. "BEF,Bus Error Flag" "0: Channel bus error not detected,1: Channel bus error detected" group.long 0x14++0x7 line.long 0x0 "CFDGCFG,Global Configuration Register" hexmask.long.word 0x0 16.--31. 1. "ITRCP,Interval Timer Reference Clock Prescaler" bitfld.long 0x0 12. "TSSS,Timestamp Source Select" "0: Source clock for timestamp counter is peripheral..,1: Source clock for timestamp counter is bit time.." newline hexmask.long.byte 0x0 8.--11. 1. "TSP,Timestamp Prescaler" bitfld.long 0x0 5. "CMPOC,CANFD Message Payload Overflow Configuration" "0: Message is rejected,1: Message payload is cut to fit to configured.." newline bitfld.long 0x0 4. "DCS,Data Link Controller Clock Select" "0: CANFD core clock (CANFDCLK),1: External oscillator clock (CANMCLK)" bitfld.long 0x0 3. "MME,Mirror Mode Enable" "0: Mirror mode disabled,1: Mirror mode enabled" newline bitfld.long 0x0 2. "DRE,DLC Replacement Enable" "0: DLC replacement disabled,1: DLC replacement enabled" bitfld.long 0x0 1. "DCE,DLC Check Enable" "0: DLC check disabled,1: DLC check enabled" newline bitfld.long 0x0 0. "TPRI,Transmission Priority" "0: ID priority,1: Message buffer number priority" line.long 0x4 "CFDGCTR,Global Control Register" bitfld.long 0x4 16. "TSRST,Timestamp Reset" "0: Timestamp not reset,1: Timestamp reset" bitfld.long 0x4 11. "CMPOFIE,CANFD Message Payload Overflow Flag Interrupt Enable" "0: CANFD message payload overflow flag interrupt..,1: CANFD message payload overflow flag interrupt.." newline bitfld.long 0x4 10. "THLEIE,TX History List Entry Lost Interrupt Enable" "0: TX history list entry lost interrupt disabled,1: TX history list entry lost interrupt enabled" bitfld.long 0x4 9. "MEIE,Message Lost Error Interrupt Enable" "0: Message lost error interrupt disabled,1: Message lost error interrupt enabled" newline bitfld.long 0x4 8. "DEIE,DLC Check Interrupt Enable" "0: DLC check interrupt disabled,1: DLC check interrupt enabled" bitfld.long 0x4 2. "GSLPR,Global Sleep Request" "0: Global sleep request disabled,1: Global sleep request enabled" newline bitfld.long 0x4 0.--1. "GMDC,Global Mode Control" "0: Global operation mode request,1: Global reset mode request,?,?" rgroup.long 0x1C++0x3 line.long 0x0 "CFDGSTS,Global Status Register" bitfld.long 0x0 3. "GRAMINIT,Global RAM Initialization" "0: RAM initialization is complete,1: RAM initialization is ongoing" bitfld.long 0x0 2. "GSLPSTS,Global Sleep Status" "0: Not in Sleep mode,1: In Sleep mode" newline bitfld.long 0x0 1. "GHLTSTS,Global Halt Status" "0: Not in Halt mode,1: In Halt mode" bitfld.long 0x0 0. "GRSTSTS,Global Reset Status" "0: Not in Reset mode,1: In Reset mode" group.long 0x20++0x3 line.long 0x0 "CFDGERFL,Global Error Flag Register" bitfld.long 0x0 16. "EEF0,ECC Error Flag" "0: ECC error not detected during TX-SCAN,1: ECC error detected during TX-SCAN" bitfld.long 0x0 3. "CMPOF,CANFD Message Payload Overflow Flag" "0: CANFD message payload overflow not detected,1: CANFD message payload overflow detected" newline rbitfld.long 0x0 2. "THLES,TX History List Entry Lost Error Status" "0: TX history list entry lost error not detected,1: TX history list entry lost error detected" rbitfld.long 0x0 1. "MES,Message Lost Error Status" "0: Message lost error not detected,1: Message lost error detected" newline bitfld.long 0x0 0. "DEF,DLC Error Flag" "0: DLC error not detected,1: DLC error detected" rgroup.long 0x24++0x3 line.long 0x0 "CFDGTSC,Global Timestamp Counter Register" hexmask.long.word 0x0 0.--15. 1. "TS,Timestamp value" group.long 0x28++0xB line.long 0x0 "CFDGAFLECTR,Global Acceptance Filter List Entry Control Register" bitfld.long 0x0 8. "AFLDAE,Acceptance Filter List Data Access Enable" "0: Acceptance Filter List data access disabled,1: Acceptance Filter List data access enabled" line.long 0x4 "CFDGAFLCFG,Global Acceptance Filter List Configuration Register" hexmask.long.byte 0x4 16.--20. 1. "RNC0,Rule Number" line.long 0x8 "CFDRMNB,RX Message Buffer Number Register" bitfld.long 0x8 8.--10. "RMPLS,Reception Message Buffer Payload Data Size" "0: 8 bytes,1: 12 bytes,?,?,?,?,?,?" hexmask.long.byte 0x8 0.--4. 1. "NRXMB,Number of RX Message Buffers" group.word 0x34++0x1 line.word 0x0 "CFDRMND,RX Message Buffer New Data Register" hexmask.word 0x0 0.--15. 1. "RMNS,RX Message Buffer New Data Status" group.word 0x38++0x1 line.word 0x0 "CFDRMIEC,RX Message Buffer Interrupt Enable Configuration Register" hexmask.word 0x0 0.--15. 1. "RMIE,RX Message Buffer Interrupt Enable" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x3C)++0x3 line.long 0x0 "CFDRFCC$1,RX FIFO Configuration/Control Registers %s" bitfld.long 0x0 13.--15. "RFIGCV,RX FIFO Interrupt Generation Counter Value" "0: Interrupt generated when FIFO is 1/8th full,1: Interrupt generated when FIFO is 1/4th full,?,?,?,?,?,?" bitfld.long 0x0 12. "RFIM,RX FIFO Interrupt Mode" "0: Interrupt generated when RX FIFO counter reaches..,1: Interrupt generated at the end of every received.." newline bitfld.long 0x0 8.--10. "RFDC,RX FIFO Depth Configuration" "0: FIFO Depth = 0 message,1: FIFO Depth = 4 messages,?,?,?,?,?,?" bitfld.long 0x0 4.--6. "RFPLS,Rx FIFO Payload Data Size Configuration" "0: 8 bytes,1: 12 bytes,?,?,?,?,?,?" newline bitfld.long 0x0 1. "RFIE,RX FIFO Interrupt Enable" "0: FIFO interrupt generation disabled,1: FIFO interrupt generation enabled" bitfld.long 0x0 0. "RFE,RX FIFO Enable" "0: FIFO disabled,1: FIFO enabled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x44)++0x3 line.long 0x0 "CFDRFSTS$1,RX FIFO Status Registers %s" hexmask.long.byte 0x0 8.--13. 1. "RFMC,RX FIFO Message Count" bitfld.long 0x0 3. "RFIF,RX FIFO Interrupt Flag" "0: FIFO interrupt condition not satisfied,1: FIFO interrupt condition satisfied" newline bitfld.long 0x0 2. "RFMLT,RX FIFO Message Lost" "0: No message lost in FIFO,1: FIFO message lost" rbitfld.long 0x0 1. "RFFLL,RX FIFO Full" "0: FIFO not full,1: FIFO full" newline rbitfld.long 0x0 0. "RFEMP,RX FIFO Empty" "0: FIFO not empty,1: FIFO empty" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x4C)++0x3 line.long 0x0 "CFDRFPCTR$1,RX FIFO Pointer Control Registers %s" hexmask.long.byte 0x0 0.--7. 1. "RFPC,RX FIFO Pointer Control" repeat.end group.long 0x54++0x7 line.long 0x0 "CFDCFCC,Common FIFO Configuration/Control Register" hexmask.long.byte 0x0 24.--31. 1. "CFITT,Common FIFO Interval Transmission Time" bitfld.long 0x0 21.--23. "CFDC,Common FIFO Depth Configuration" "0: FIFO Depth = 0 message,1: FIFO Depth = 4 messages,?,?,?,?,?,?" newline bitfld.long 0x0 16.--17. "CFTML,Common FIFO TX Message Buffer Link" "0,1,2,3" bitfld.long 0x0 13.--15. "CFIGCV,Common FIFO Interrupt Generation Counter Value" "0: Interrupt generated when FIFO is 1/8th full,1: Interrupt generated when FIFO is 1/4th full,?,?,?,?,?,?" newline bitfld.long 0x0 12. "CFIM,Common FIFO Interrupt Mode" "0: RX FIFO mode: RX interrupt generated when Common..,1: RX FIFO mode: RX interrupt generated at the end.." bitfld.long 0x0 11. "CFITR,Common FIFO Interval Timer Resolution" "0: Reference clock period × 1,1: Reference clock period × 10" newline bitfld.long 0x0 10. "CFITSS,Common FIFO Interval Timer Source Select" "0: Reference clock (× 1 / × 10 period),1: Bit time clock of related channel (FIFO is.." bitfld.long 0x0 8. "CFM,Common FIFO Mode" "0: RX FIFO mode,1: TX FIFO mode" newline bitfld.long 0x0 4.--6. "CFPLS,Common FIFO Payload Data Size Configuration" "0: 8 bytes,1: 12 bytes,?,?,?,?,?,?" bitfld.long 0x0 2. "CFTXIE,Common FIFO TX Interrupt Enable" "0: FIFO interrupt generation disabled for Frame TX,1: FIFO interrupt generation enabled for Frame TX" newline bitfld.long 0x0 1. "CFRXIE,Common FIFO RX Interrupt Enable" "0: FIFO interrupt generation disabled for Frame RX,1: FIFO interrupt generation enabled for Frame RX" bitfld.long 0x0 0. "CFE,Common FIFO Enable" "0: FIFO disabled,1: FIFO enabled" line.long 0x4 "CFDCFSTS,Common FIFO Status Register" hexmask.long.byte 0x4 8.--13. 1. "CFMC,Common FIFO Message Count" bitfld.long 0x4 4. "CFTXIF,Common TX FIFO Interrupt Flag" "0: FIFO interrupt condition not satisfied after..,1: FIFO Interrupt condition satisfied after frame.." newline bitfld.long 0x4 3. "CFRXIF,Common RX FIFO Interrupt Flag" "0: FIFO interrupt condition not satisfied after..,1: FIFO interrupt condition satisfied after frame.." bitfld.long 0x4 2. "CFMLT,Common FIFO Message Lost" "0: Number of message lost in FIFO,1: FIFO message lost" newline rbitfld.long 0x4 1. "CFFLL,Common FIFO Full" "0: FIFO not full,1: FIFO full" rbitfld.long 0x4 0. "CFEMP,Common FIFO Empty" "0: FIFO not empty,1: FIFO empty" wgroup.long 0x5C++0x3 line.long 0x0 "CFDCFPCTR,Common FIFO Pointer Control Register" hexmask.long.byte 0x0 0.--7. 1. "CFPC,Common FIFO Pointer Control" rgroup.long 0x60++0xF line.long 0x0 "CFDFESTS,FIFO Empty Status Register" bitfld.long 0x0 8. "CFEMP,Common FIFO Empty Status" "0: Corresponding FIFO not empty,1: Corresponding FIFO empty" bitfld.long 0x0 0.--1. "RFXEMP,RX FIFO Empty Status" "0: Corresponding FIFO not empty,1: Corresponding FIFO empty,?,?" line.long 0x4 "CFDFFSTS,FIFO Full Status Register" bitfld.long 0x4 8. "CFFLL,Common FIF0 Full Status" "0: Corresponding FIFO not full,1: Corresponding FIFO full" bitfld.long 0x4 0.--1. "RFXFLL,RX FIF0 Full Status" "0: Corresponding FIFO not full,1: Corresponding FIFO full,?,?" line.long 0x8 "CFDFMSTS,FIFO Message Lost Status Register" bitfld.long 0x8 8. "CFMLT,Common FIFO Message Lost Status" "0: Corresponding FIFO Message Lost flag not set,1: Corresponding FIFO Message Lost flag set" bitfld.long 0x8 0.--1. "RFXMLT,RX FIFO Message Lost Status" "0: Corresponding FIFO Message Lost flag not set,1: Corresponding FIFO Message Lost flag set,?,?" line.long 0xC "CFDRFISTS,RX FIFO Interrupt Flag Status Register" bitfld.long 0xC 0.--1. "RFXIF,RX FIFO[x] Interrupt Flag Status" "0: Corresponding RX FIFO Interrupt flag not set,1: Corresponding RX FIFO Interrupt flag set,?,?" repeat 4. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x70)++0x0 line.byte 0x0 "CFDTMC$1,TX Message Buffer Control Registers %s" bitfld.byte 0x0 2. "TMOM,TX Message Buffer One-shot Mode" "0: TX message buffer not configured in one-shot mode,1: TX message buffer configured in one-shot mode" bitfld.byte 0x0 1. "TMTAR,TX Message Buffer Transmission Abort Request" "0: TX message buffer transmission request abort not..,1: TX message buffer transmission request abort.." newline bitfld.byte 0x0 0. "TMTR,TX Message Buffer Transmission Request" "0: TX Message buffer transmission not requested,1: TX message buffer transmission requested" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x74)++0x0 line.byte 0x0 "CFDTMSTS$1,TX Message Buffer Status Registers %s" rbitfld.byte 0x0 4. "TMTARM,TX Message Buffer Transmission Abort Request Mirrored" "0: TX message buffer transmission request abort not..,1: TX message buffer transmission request abort.." rbitfld.byte 0x0 3. "TMTRM,TX Message Buffer Transmission Request Mirrored" "0: TX message buffer transmission not requested,1: TX message buffer transmission requested" newline bitfld.byte 0x0 1.--2. "TMTRF,TX Message Buffer Transmission Result Flag" "0: No result,1: Transmission aborted from the TX message buffer,?,?" rbitfld.byte 0x0 0. "TMTSTS,TX Message Buffer Transmission Status" "0: No on-going transmission,1: On-going transmission" repeat.end rgroup.long 0x78++0xF line.long 0x0 "CFDTMTRSTS,TX Message Buffer Transmission Request Status Register" hexmask.long.byte 0x0 0.--3. 1. "CFDTMTRSTS,TX Message Buffer Transmission Request Status" line.long 0x4 "CFDTMTARSTS,TX Message Buffer Transmission Abort Request Status Register" hexmask.long.byte 0x4 0.--3. 1. "CFDTMTARSTS,TX Message Buffer Transmission Abort Request Status" line.long 0x8 "CFDTMTCSTS,TX Message Buffer Transmission Completion Status Register" hexmask.long.byte 0x8 0.--3. 1. "CFDTMTCSTS,TX Message Buffer Transmission Completion Status" line.long 0xC "CFDTMTASTS,TX Message Buffer Transmission Abort Status Register" hexmask.long.byte 0xC 0.--3. 1. "CFDTMTASTS,TX Message Buffer Transmission Abort Status" group.long 0x88++0xB line.long 0x0 "CFDTMIEC,TX Message Buffer Interrupt Enable Configuration Register" hexmask.long.byte 0x0 0.--3. 1. "TMIEg,TX Message Buffer Interrupt Enable" line.long 0x4 "CFDTXQCC,TX Queue Configuration/Control Register" bitfld.long 0x4 8.--9. "TXQDC,TX Queue Depth Configuration" "0: 0 messages,1: Reserved,?,?" bitfld.long 0x4 7. "TXQIM,TX Queue Interrupt Mode" "0: When the last message is successfully transmitted,1: At every successful transmission" newline bitfld.long 0x4 5. "TXQTXIE,TX Queue TX Interrupt Enable" "0: TX Queue TX interrupt disabled,1: TX Queue TX interrupt enabled" bitfld.long 0x4 0. "TXQE,TX Queue Enable" "0: TX Queue disabled,1: TX Queue enabled" line.long 0x8 "CFDTXQSTS,TX Queue Status Register" rbitfld.long 0x8 8.--10. "TXQMC,TX Queue Message Count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 2. "TXQTXIF,TX Queue TX Interrupt Flag" "0: TX Queue interrupt condition not satisfied after..,1: TX Queue interrupt condition satisfied after a.." newline rbitfld.long 0x8 1. "TXQFLL,TX Queue Full" "0: TX Queue not full,1: TX Queue full" rbitfld.long 0x8 0. "TXQEMP,TX Queue Empty" "0: TX Queue not empty,1: TX Queue empty" wgroup.long 0x94++0x3 line.long 0x0 "CFDTXQPCTR,TX Queue Pointer Control Register" hexmask.long.byte 0x0 0.--7. 1. "TXQPC,TX Queue Pointer Control" group.long 0x98++0x7 line.long 0x0 "CFDTHLCC,TX History List Configuration/Control Register" bitfld.long 0x0 10. "THLDTE,TX History List Dedicated TX Enable" "0: TX FIFO + TX Queue,1: Flat TX MB + TX FIFO + TX Queue" bitfld.long 0x0 9. "THLIM,TX History List Interrupt Mode" "0: Interrupt generated if TX History List level..,1: Interrupt generated for every successfully.." newline bitfld.long 0x0 8. "THLIE,TX History List Interrupt Enable" "0: TX History List Interrupt disabled,1: TX History List Interrupt enabled" bitfld.long 0x0 0. "THLE,TX History List Enable" "0: TX History List disabled,1: TX History List enabled" line.long 0x4 "CFDTHLSTS,TX History List Status Register" hexmask.long.byte 0x4 8.--11. 1. "THLMC,TX History List Message Count" bitfld.long 0x4 3. "THLIF,TX History List Interrupt Flag" "0: TX History List interrupt condition not satisfied,1: TX History List interrupt condition satisfied" newline bitfld.long 0x4 2. "THLELT,TX History List Entry Lost" "0: No entry lost in TX History List,1: TX History List entry Lost" rbitfld.long 0x4 1. "THLFLL,TX History List Full" "0: TX History List not full,1: TX History List full" newline rbitfld.long 0x4 0. "THLEMP,TX History List Empty" "0: TX History List not empty,1: TX History List empty" wgroup.long 0xA0++0x3 line.long 0x0 "CFDTHLPCTR,TX History List Pointer Control Register" hexmask.long.byte 0x0 0.--7. 1. "THLPC,TX History List Pointer Control" rgroup.long 0xA4++0x3 line.long 0x0 "CFDGTINTSTS,Global TX Interrupt Status Register" bitfld.long 0x0 4. "THIF0,TX History List Interrupt" "0: Channel n TX History List Interrupt flag not set,1: Channel n TX History List Interrupt flag set" bitfld.long 0x0 3. "CFTIF0,COM FIFO TX Mode Interrupt Flag" "0: Channel n COM FIFO TX Mode Interrupt flag not set,1: Channel n COM FIFO TX Mode Interrupt flag set" newline bitfld.long 0x0 2. "TQIF0,TX Queue Interrupt Flag" "0: Channel n TX Queue Interrupt flag not set,1: Channel n TX Queue Interrupt flag set" bitfld.long 0x0 1. "TAI0,TX Abort Interrupt Flag" "0: Channel n TX Abort Interrupt flag not set,1: Channel n TX Abort Interrupt flag set" newline bitfld.long 0x0 0. "TSIF0,TX Successful Interrupt Flag" "0: Channel n TX Successful Interrupt flag not set,1: Channel n TX Successful Interrupt flag set" group.long 0xA8++0xB line.long 0x0 "CFDGTSTCFG,Global Test Configuration Register" hexmask.long.byte 0x0 16.--19. 1. "RTMPS,RAM Test Mode Page Select" line.long 0x4 "CFDGTSTCTR,Global Test Control Register" bitfld.long 0x4 2. "RTME,RAM Test Mode Enable" "0: RAM test mode disabled,1: RAM test mode enabled" line.long 0x8 "CFDGFDCFG,Global FD Configuration Register" bitfld.long 0x8 8.--9. "TSCCFG,Timestamp Capture Configuration" "0: Timestamp capture at the sample point of SOF..,1: Timestamp capture at frame valid indication,?,?" bitfld.long 0x8 0. "RPED,RES Bit Protocol Exception Disable" "0: Protocol exception event detection enabled,1: Protocol exception event detection disabled" wgroup.long 0xB8++0x3 line.long 0x0 "CFDGLOCKK,Global Lock Key Register" hexmask.long.word 0x0 0.--15. 1. "LOCK,Lock Key" group.long 0xC0++0xB line.long 0x0 "CFDGAFLIGNENT,Global AFL Ignore Entry Register" hexmask.long.byte 0x0 0.--3. 1. "IRN,Ignore Rule Number" line.long 0x4 "CFDGAFLIGNCTR,Global AFL Ignore Control Register" hexmask.long.byte 0x4 8.--15. 1. "KEY,Key Code" bitfld.long 0x4 0. "IREN,Ignore Rule Enable" "0: AFL entry number is not ignored,1: AFL entry number is ignored" line.long 0x8 "CFDCDTCT,DMA Transfer Control Register" bitfld.long 0x8 8. "CFDMAE,DMA Transfer Enable for Common FIFO 0" "0: DMA transfer request disabled,1: DMA transfer request enabled" bitfld.long 0x8 1. "RFDMAE1,DMA Transfer Enable for RXFIFO 1" "0: DMA transfer request disabled,1: DMA transfer request enabled" newline bitfld.long 0x8 0. "RFDMAE0,DMA Transfer Enable for RXFIFO 0" "0: DMA transfer request disabled,1: DMA transfer request enabled" rgroup.long 0xCC++0x3 line.long 0x0 "CFDCDTSTS,DMA Transfer Status Register" bitfld.long 0x0 8. "CFDMASTS,DMA Transfer Status only for Common FIFO" "0: DMA transfer stopped,1: DMA transfer on going" bitfld.long 0x0 1. "RFDMASTS1,DMA Transfer Status for RX FIFO 1" "0: DMA transfer stopped,1: DMA transfer on going" newline bitfld.long 0x0 0. "RFDMASTS0,DMA Transfer Status for RX FIFO 0" "0: DMA transfer stopped,1: DMA transfer on going" group.long 0xD8++0x3 line.long 0x0 "CFDGRSTC,Global SW reset Register" hexmask.long.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.long 0x0 0. "SRST,SW Reset" "0: Normal state,1: SW reset state" group.long 0x100++0xF line.long 0x0 "CFDC0DCFG,Data Bitrate Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "DSJW,Resynchronization Jump Width" hexmask.long.byte 0x0 16.--19. 1. "DTSEG2,Timing Segment 2" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Timing Segment 1" hexmask.long.byte 0x0 0.--7. 1. "DBRP,Channel Data Baud Rate Prescaler" line.long 0x4 "CFDC0FDCFG,CANFD Configuration Register" bitfld.long 0x4 30. "CLOE,Classical CAN Enable" "0: Classical CAN mode disabled,1: Classical CAN mode enabled" bitfld.long 0x4 29. "REFE,RX Edge Filter Enable" "0: RX edge filter disabled,1: RX edge filter enabled" newline bitfld.long 0x4 28. "FDOE,FD-Only Enable" "0: FD-only mode disabled,1: FD-only mode enabled" hexmask.long.byte 0x4 16.--23. 1. "TDCO,Transceiver Delay Compensation Offset" newline bitfld.long 0x4 10. "ESIC,Error State Indication Configuration" "0: The ESI bit in the frame represents the error..,1: The ESI bit in the frame represents the error.." bitfld.long 0x4 9. "TDCE,Transceiver Delay Compensation Enable" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled" newline bitfld.long 0x4 8. "TDCOC,Transceiver Delay Compensation Offset Configuration" "0: Measured + offset,1: Offset-only" bitfld.long 0x4 0.--2. "EOCCFG,Error Occurrence Counter Configuration" "0: All transmitter or receiver CAN frames,1: All transmitter CAN frames,?,?,?,?,?,?" line.long 0x8 "CFDC0FDCTR,CANFD Control Register" bitfld.long 0x8 1. "SOCCLR,Successful Occurrence Counter Clear" "0: No successful occurrence counter clear,1: Clear successful occurrence counter" bitfld.long 0x8 0. "EOCCLR,Error Occurrence Counter Clear" "0: No error occurrence counter clear,1: Clear error occurrence counter" line.long 0xC "CFDC0FDSTS,CANFD Status Register" hexmask.long.byte 0xC 24.--31. 1. "SOC,Successful occurrence counter" hexmask.long.byte 0xC 16.--23. 1. "EOC,Error Occurrence Counter" newline bitfld.long 0xC 15. "TDCVF,Transceiver Delay Compensation Violation Flag" "0: Transceiver delay compensation violation has not..,1: Transceiver delay compensation violation has.." bitfld.long 0xC 9. "SOCO,Successful Occurrence Counter Overflow" "0: Successful occurrence counter has not overflowed,1: Successful occurrence counter has overflowed" newline bitfld.long 0xC 8. "EOCO,Error Occurrence Counter Overflow" "0: Error occurrence counter has not overflowed,1: Error occurrence counter has overflowed" hexmask.long.byte 0xC 0.--7. 1. "TDCR,Transceiver Delay Compensation Result" rgroup.long 0x110++0x3 line.long 0x0 "CFDC0FDCRC,CANFD CRC Register" hexmask.long.byte 0x0 24.--27. 1. "SCNT,Stuff bit count" hexmask.long.tbyte 0x0 0.--20. 1. "CRCREG,CRC Register value" repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x120)++0x3 line.long 0x0 "CFDGAFLID$1,Global Acceptance Filter List ID Registers" bitfld.long 0x0 31. "GAFLIDE,Global Acceptance Filter List Entry IDE Field" "0: Standard identifier of rule entry ID is valid..,1: Extended identifier of rule entry ID is valid.." bitfld.long 0x0 30. "GAFLRTR,Global Acceptance Filter List Entry RTR Field" "0: Data frame,1: Remote frame" newline bitfld.long 0x0 29. "GAFLLB,Global Acceptance Filter List Entry Loopback Configuration" "0: Global Acceptance Filter List entry ID for..,1: Global Acceptance Filter List entry ID for.." hexmask.long 0x0 0.--28. 1. "GAFLID,Global Acceptance Filter List Entry ID Field" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x124)++0x3 line.long 0x0 "CFDGAFLM$1,Global Acceptance Filter List Mask Registers" bitfld.long 0x0 31. "GAFLIDEM,Global Acceptance Filter List IDE Mask" "0: IDE bit is not used for ID matching,1: IDE bit is used for ID matching" bitfld.long 0x0 30. "GAFLRTRM,Global Acceptance Filter List Entry RTR Mask" "0: RTR bit is not used for ID matching,1: RTR bit is used for ID matching" newline bitfld.long 0x0 29. "GAFLIFL1,Global Acceptance Filter List Information Label 1" "0,1" hexmask.long 0x0 0.--28. 1. "GAFLIDM,Global Acceptance Filter List ID Mask Field" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x128)++0x3 line.long 0x0 "CFDGAFLP0$1,Global Acceptance Filter List Pointer 0 Registers" hexmask.long.word 0x0 16.--31. 1. "GAFLPTR,Global Acceptance Filter List Pointer" bitfld.long 0x0 15. "GAFLRMV,Global Acceptance Filter List RX Message Buffer Valid" "0: Single message buffer direction pointer is invalid,1: Single message buffer direction pointer is valid" newline hexmask.long.byte 0x0 8.--12. 1. "GAFLRMDP,Global Acceptance Filter List RX Message Buffer Direction Pointer" bitfld.long 0x0 7. "GAFLIFL0,Global Acceptance Filter List Information Label 0" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "GAFLDLC,Global Acceptance Filter List DLC Field" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x12C)++0x3 line.long 0x0 "CFDGAFLP1$1,Global Acceptance Filter List Pointer 1 Registers" bitfld.long 0x0 8. "GAFLFDP8,Global Acceptance Filter List FIFO Direction Pointer" "0: Disable Common FIFO as target for reception,1: Enable Common FIFO as target for reception" bitfld.long 0x0 1. "GAFLFDP1,Global Acceptance Filter List FIFO Direction Pointer" "0: Disable RX FIFO 1 as target for reception,1: Enable RX FIFO 1 as target for reception" newline bitfld.long 0x0 0. "GAFLFDP0,Global Acceptance Filter List FIFO Direction Pointer" "0: Disable RX FIFO 0 as target for reception,1: Enable RX FIFO 0 as target for reception" repeat.end repeat 64. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x280)++0x3 line.long 0x0 "CFDRPGACC$1,RAM Test Page Access Registers %s" hexmask.long 0x0 0.--31. 1. "RDTA,RAM Data Test Access" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x520)++0x3 line.long 0x0 "CFDRFID$1,RX FIFO Access ID Register %s" bitfld.long 0x0 31. "RFIDE,RX FIFO Buffer IDE bit" "0: STD-ID has been received,1: EXT-ID has been received" bitfld.long 0x0 30. "RFRTR,RX FIFO Buffer RTR bit" "0: Data frame,1: Remote frame" newline hexmask.long 0x0 0.--28. 1. "RFID,RX FIFO Buffer ID Field" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x524)++0x3 line.long 0x0 "CFDRFPTR$1,RX FIFO Access Pointer Register %s" hexmask.long.byte 0x0 28.--31. 1. "RFDLC,RX FIFO Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RFTS,RX FIFO Timestamp Value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x528)++0x3 line.long 0x0 "CFDRFFDSTS$1,RX FIFO Access CANFD Status Register %s" hexmask.long.word 0x0 16.--31. 1. "CFDRFPTR,RX FIFO Buffer Pointer Field" bitfld.long 0x0 8.--9. "RFIFL,RX FIFO Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RFFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RFBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RFESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x52C)++0x3 line.long 0x0 "CFDRFDF$1_0,RX FIFO Access Data Field 0 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x530)++0x3 line.long 0x0 "CFDRFDF$1_1,RX FIFO Access Data Field 1 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x534)++0x3 line.long 0x0 "CFDRFDF$1_2,RX FIFO Access Data Field 2 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x538)++0x3 line.long 0x0 "CFDRFDF$1_3,RX FIFO Access Data Field 3 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x53C)++0x3 line.long 0x0 "CFDRFDF$1_4,RX FIFO Access Data Field 4 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x540)++0x3 line.long 0x0 "CFDRFDF$1_5,RX FIFO Access Data Field 5 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x544)++0x3 line.long 0x0 "CFDRFDF$1_6,RX FIFO Access Data Field 6 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x548)++0x3 line.long 0x0 "CFDRFDF$1_7,RX FIFO Access Data Field 7 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x54C)++0x3 line.long 0x0 "CFDRFDF$1_8,RX FIFO Access Data Field 8 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x550)++0x3 line.long 0x0 "CFDRFDF$1_9,RX FIFO Access Data Field 9 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x554)++0x3 line.long 0x0 "CFDRFDF$1_10,RX FIFO Access Data Field 10 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x558)++0x3 line.long 0x0 "CFDRFDF$1_11,RX FIFO Access Data Field 11 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x55C)++0x3 line.long 0x0 "CFDRFDF$1_12,RX FIFO Access Data Field 12 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x560)++0x3 line.long 0x0 "CFDRFDF$1_13,RX FIFO Access Data Field 13 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x564)++0x3 line.long 0x0 "CFDRFDF$1_14,RX FIFO Access Data Field 14 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x568)++0x3 line.long 0x0 "CFDRFDF$1_15,RX FIFO Access Data Field 15 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end group.long 0x5B8++0xB line.long 0x0 "CFDCFID,Common FIFO Access ID Register" bitfld.long 0x0 31. "CFIDE,Common FIFO Buffer IDE Bit" "0: STD-ID will be transmitted or has been received,1: EXT-ID will be transmitted or has been received" bitfld.long 0x0 30. "CFRTR,Common FIFO Buffer RTR Bit" "0: Data Frame,1: Remote Frame" newline bitfld.long 0x0 29. "THLEN,THL Entry enable" "0: Entry will not be stored in THL after successful..,1: Entry will be stored in THL after successful TX." hexmask.long 0x0 0.--28. 1. "CFID,Common FIFO Buffer ID Field" line.long 0x4 "CFDCFPTR,Common FIFO Access Pointer Register" hexmask.long.byte 0x4 28.--31. 1. "CFDLC,Common FIFO Buffer DLC Field" hexmask.long.word 0x4 0.--15. 1. "CFTS,Common FIFO Timestamp Value" line.long 0x8 "CFDCFFDCSTS,Common FIFO Access CANFD Control/Status Register" hexmask.long.word 0x8 16.--31. 1. "CFPTR,Common FIFO Buffer Pointer Field" bitfld.long 0x8 8.--9. "CFIFL,COMMON FIFO Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x8 2. "CFFDF,CAN FD Format bit" "0: Non CANFD frame received or to transmit,1: CANFD frame received or to transmit" bitfld.long 0x8 1. "CFBRS,Bit Rate Switch bit" "0: CANFD frame received or to transmit with no bit..,1: CANFD frame received or to transmit with bit.." newline bitfld.long 0x8 0. "CFESI,Error State Indicator bit" "0: CANFD frame received or to transmit by error..,1: CANFD frame received or to transmit by error.." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5C4)++0x3 line.long 0x0 "CFDCFDF$1,Common FIFO Access Data Field %s Registers" hexmask.long.byte 0x0 24.--31. 1. "CFDB_HH,Common FIFO Buffer Data Bytes ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "CFDB_HL,Common FIFO Buffer Data Bytes ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "CFDB_LH,Common FIFO Buffer Data Bytes ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "CFDB_LL,Common FIFO Buffer Data Bytes (p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x604)++0x3 line.long 0x0 "CFDTMID$1,TX Message Buffer ID Registers" bitfld.long 0x0 31. "TMIDE,TX Message Buffer IDE bit" "0: STD-ID is transmitted,1: EXT-ID is transmitted" bitfld.long 0x0 30. "TMRTR,TX Message Buffer RTR bit" "0: Data frame,1: Remote frame" newline bitfld.long 0x0 29. "THLEN,Tx History List Entry" "0: Entry not stored in THL after successful TX,1: Entry stored in THL after successful TX" hexmask.long 0x0 0.--28. 1. "TMID,TX Message Buffer ID Field" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x608)++0x3 line.long 0x0 "CFDTMPTR$1,TX Message Buffer Pointer Register" hexmask.long.byte 0x0 28.--31. 1. "TMDLC,TX Message Buffer DLC Field" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x60C)++0x3 line.long 0x0 "CFDTMFDCTR$1,TX Message Buffer CANFD Control Register" hexmask.long.word 0x0 16.--31. 1. "TMPTR,TX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "TMIFL,TX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "TMFDF,CAN FD Format bit" "0: Non CANFD frame to transmit,1: CANFD frame to transmit" bitfld.long 0x0 1. "TMBRS,Bit Rate Switch bit" "0: CANFD frame to transmit with no bit rate switch,1: CANFD frame to transmit with bit rate switch" newline bitfld.long 0x0 0. "TMESI,Error State Indicator bit" "0: CANFD frame to transmit by error active node,1: CANFD frame to transmit by error passive node" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x610)++0x3 line.long 0x0 "CFDTMDF$1_0,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x614)++0x3 line.long 0x0 "CFDTMDF$1_1,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x618)++0x3 line.long 0x0 "CFDTMDF$1_2,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x61C)++0x3 line.long 0x0 "CFDTMDF$1_3,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x620)++0x3 line.long 0x0 "CFDTMDF$1_4,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x624)++0x3 line.long 0x0 "CFDTMDF$1_5,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x628)++0x3 line.long 0x0 "CFDTMDF$1_6,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x62C)++0x3 line.long 0x0 "CFDTMDF$1_7,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x630)++0x3 line.long 0x0 "CFDTMDF$1_8,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x634)++0x3 line.long 0x0 "CFDTMDF$1_9,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x638)++0x3 line.long 0x0 "CFDTMDF$1_10,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x63C)++0x3 line.long 0x0 "CFDTMDF$1_11,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x640)++0x3 line.long 0x0 "CFDTMDF$1_12,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x644)++0x3 line.long 0x0 "CFDTMDF$1_13,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x648)++0x3 line.long 0x0 "CFDTMDF$1_14,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x64C)++0x3 line.long 0x0 "CFDTMDF$1_15,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end rgroup.long 0x740++0x7 line.long 0x0 "CFDTHLACC0,TX History List Access Register 0" hexmask.long.word 0x0 16.--31. 1. "TMTS,Transmit Timestamp" bitfld.long 0x0 3.--4. "BN,Buffer Number" "0,1,2,3" newline bitfld.long 0x0 0.--2. "BT,Buffer Type" "?,1: Flat TX message buffer,?,?,?,?,?,?" line.long 0x4 "CFDTHLACC1,TX History List Access Register 1" bitfld.long 0x4 16.--17. "TIFL,Transmit Information Label" "0,1,2,3" hexmask.long.word 0x4 0.--15. 1. "TID,Transmit ID" repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x920)++0x3 line.long 0x0 "CFDRMID$1,RX Message Buffer ID Registers" bitfld.long 0x0 31. "RMIDE,RX Message Buffer IDE Bit" "0: STD-ID is stored,1: EXT-ID is stored" bitfld.long 0x0 30. "RMRTR,RX Message Buffer RTR Bit" "0: Data frame,1: Remote frame" newline hexmask.long 0x0 0.--28. 1. "RMID,RX Message Buffer ID Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x924)++0x3 line.long 0x0 "CFDRMPTR$1,RX Message Buffer Pointer Registers" hexmask.long.byte 0x0 28.--31. 1. "RMDLC,RX Message Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RMTS,RX Message Buffer Timestamp Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x928)++0x3 line.long 0x0 "CFDRMFDSTS$1,RX Message Buffer CANFD Status Registers" hexmask.long.word 0x0 16.--31. 1. "RMPTR,RX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "RMIFL,RX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RMFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RMBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RMESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x92C)++0x3 line.long 0x0 "CFDRMDF$1_0,RX Message Buffer Data Field 0 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x930)++0x3 line.long 0x0 "CFDRMDF$1_1,RX Message Buffer Data Field 1 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x934)++0x3 line.long 0x0 "CFDRMDF$1_2,RX Message Buffer Data Field 2 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x938)++0x3 line.long 0x0 "CFDRMDF$1_3,RX Message Buffer Data Field 3 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x93C)++0x3 line.long 0x0 "CFDRMDF$1_4,RX Message Buffer Data Field 4 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x940)++0x3 line.long 0x0 "CFDRMDF$1_5,RX Message Buffer Data Field 5 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x944)++0x3 line.long 0x0 "CFDRMDF$1_6,RX Message Buffer Data Field 6 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x948)++0x3 line.long 0x0 "CFDRMDF$1_7,RX Message Buffer Data Field 7 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x94C)++0x3 line.long 0x0 "CFDRMDF$1_8,RX Message Buffer Data Field 8 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x950)++0x3 line.long 0x0 "CFDRMDF$1_9,RX Message Buffer Data Field 9 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x954)++0x3 line.long 0x0 "CFDRMDF$1_10,RX Message Buffer Data Field 10 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x958)++0x3 line.long 0x0 "CFDRMDF$1_11,RX Message Buffer Data Field 11 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x95C)++0x3 line.long 0x0 "CFDRMDF$1_12,RX Message Buffer Data Field 12 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x960)++0x3 line.long 0x0 "CFDRMDF$1_13,RX Message Buffer Data Field 13 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x964)++0x3 line.long 0x0 "CFDRMDF$1_14,RX Message Buffer Data Field 14 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x968)++0x3 line.long 0x0 "CFDRMDF$1_15,RX Message Buffer Data Field 15 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD20)++0x3 line.long 0x0 "CFDRMID$1,RX Message Buffer ID Registers" bitfld.long 0x0 31. "RMIDE,RX Message Buffer IDE Bit" "0: STD-ID is stored,1: EXT-ID is stored" bitfld.long 0x0 30. "RMRTR,RX Message Buffer RTR Bit" "0: Data frame,1: Remote frame" newline hexmask.long 0x0 0.--28. 1. "RMID,RX Message Buffer ID Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD24)++0x3 line.long 0x0 "CFDRMPTR$1,RX Message Buffer Pointer Registers" hexmask.long.byte 0x0 28.--31. 1. "RMDLC,RX Message Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RMTS,RX Message Buffer Timestamp Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD28)++0x3 line.long 0x0 "CFDRMFDSTS$1,RX Message Buffer CANFD Status Registers" hexmask.long.word 0x0 16.--31. 1. "RMPTR,RX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "RMIFL,RX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RMFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RMBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RMESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD2C)++0x3 line.long 0x0 "CFDRMDF$1_0,RX Message Buffer Data Field 0 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD30)++0x3 line.long 0x0 "CFDRMDF$1_1,RX Message Buffer Data Field 1 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD34)++0x3 line.long 0x0 "CFDRMDF$1_2,RX Message Buffer Data Field 2 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD38)++0x3 line.long 0x0 "CFDRMDF$1_3,RX Message Buffer Data Field 3 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD3C)++0x3 line.long 0x0 "CFDRMDF$1_4,RX Message Buffer Data Field 4 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD40)++0x3 line.long 0x0 "CFDRMDF$1_5,RX Message Buffer Data Field 5 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD44)++0x3 line.long 0x0 "CFDRMDF$1_6,RX Message Buffer Data Field 6 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD48)++0x3 line.long 0x0 "CFDRMDF$1_7,RX Message Buffer Data Field 7 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD4C)++0x3 line.long 0x0 "CFDRMDF$1_8,RX Message Buffer Data Field 8 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD50)++0x3 line.long 0x0 "CFDRMDF$1_9,RX Message Buffer Data Field 9 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD54)++0x3 line.long 0x0 "CFDRMDF$1_10,RX Message Buffer Data Field 10 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD58)++0x3 line.long 0x0 "CFDRMDF$1_11,RX Message Buffer Data Field 11 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD5C)++0x3 line.long 0x0 "CFDRMDF$1_12,RX Message Buffer Data Field 12 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD60)++0x3 line.long 0x0 "CFDRMDF$1_13,RX Message Buffer Data Field 13 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD64)++0x3 line.long 0x0 "CFDRMDF$1_14,RX Message Buffer Data Field 14 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD68)++0x3 line.long 0x0 "CFDRMDF$1_15,RX Message Buffer Data Field 15 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1124)++0x3 line.long 0x0 "CFDRMPTR$1,RX Message Buffer Pointer Registers" hexmask.long.byte 0x0 28.--31. 1. "RMDLC,RX Message Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RMTS,RX Message Buffer Timestamp Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1128)++0x3 line.long 0x0 "CFDRMFDSTS$1,RX Message Buffer CANFD Status Registers" hexmask.long.word 0x0 16.--31. 1. "RMPTR,RX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "RMIFL,RX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RMFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RMBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RMESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x112C)++0x3 line.long 0x0 "CFDRMDF$1_0,RX Message Buffer Data Field 0 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1130)++0x3 line.long 0x0 "CFDRMDF$1_1,RX Message Buffer Data Field 1 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1134)++0x3 line.long 0x0 "CFDRMDF$1_2,RX Message Buffer Data Field 2 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1138)++0x3 line.long 0x0 "CFDRMDF$1_3,RX Message Buffer Data Field 3 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x113C)++0x3 line.long 0x0 "CFDRMDF$1_4,RX Message Buffer Data Field 4 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1140)++0x3 line.long 0x0 "CFDRMDF$1_5,RX Message Buffer Data Field 5 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1144)++0x3 line.long 0x0 "CFDRMDF$1_6,RX Message Buffer Data Field 6 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1148)++0x3 line.long 0x0 "CFDRMDF$1_7,RX Message Buffer Data Field 7 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x114C)++0x3 line.long 0x0 "CFDRMDF$1_8,RX Message Buffer Data Field 8 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1150)++0x3 line.long 0x0 "CFDRMDF$1_9,RX Message Buffer Data Field 9 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1154)++0x3 line.long 0x0 "CFDRMDF$1_10,RX Message Buffer Data Field 10 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1158)++0x3 line.long 0x0 "CFDRMDF$1_11,RX Message Buffer Data Field 11 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x115C)++0x3 line.long 0x0 "CFDRMDF$1_12,RX Message Buffer Data Field 12 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1160)++0x3 line.long 0x0 "CFDRMDF$1_13,RX Message Buffer Data Field 13 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1164)++0x3 line.long 0x0 "CFDRMDF$1_14,RX Message Buffer Data Field 14 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1168)++0x3 line.long 0x0 "CFDRMDF$1_15,RX Message Buffer Data Field 15 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1524)++0x3 line.long 0x0 "CFDRMPTR$1,RX Message Buffer Pointer Registers" hexmask.long.byte 0x0 28.--31. 1. "RMDLC,RX Message Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RMTS,RX Message Buffer Timestamp Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1528)++0x3 line.long 0x0 "CFDRMFDSTS$1,RX Message Buffer CANFD Status Registers" hexmask.long.word 0x0 16.--31. 1. "RMPTR,RX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "RMIFL,RX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RMFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RMBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RMESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x152C)++0x3 line.long 0x0 "CFDRMDF$1_0,RX Message Buffer Data Field 0 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1530)++0x3 line.long 0x0 "CFDRMDF$1_1,RX Message Buffer Data Field 1 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1534)++0x3 line.long 0x0 "CFDRMDF$1_2,RX Message Buffer Data Field 2 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1538)++0x3 line.long 0x0 "CFDRMDF$1_3,RX Message Buffer Data Field 3 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x153C)++0x3 line.long 0x0 "CFDRMDF$1_4,RX Message Buffer Data Field 4 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1540)++0x3 line.long 0x0 "CFDRMDF$1_5,RX Message Buffer Data Field 5 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1544)++0x3 line.long 0x0 "CFDRMDF$1_6,RX Message Buffer Data Field 6 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1548)++0x3 line.long 0x0 "CFDRMDF$1_7,RX Message Buffer Data Field 7 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x154C)++0x3 line.long 0x0 "CFDRMDF$1_8,RX Message Buffer Data Field 8 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1550)++0x3 line.long 0x0 "CFDRMDF$1_9,RX Message Buffer Data Field 9 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1554)++0x3 line.long 0x0 "CFDRMDF$1_10,RX Message Buffer Data Field 10 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1558)++0x3 line.long 0x0 "CFDRMDF$1_11,RX Message Buffer Data Field 11 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x155C)++0x3 line.long 0x0 "CFDRMDF$1_12,RX Message Buffer Data Field 12 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1560)++0x3 line.long 0x0 "CFDRMDF$1_13,RX Message Buffer Data Field 13 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1564)++0x3 line.long 0x0 "CFDRMDF$1_14,RX Message Buffer Data Field 14 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1568)++0x3 line.long 0x0 "CFDRMDF$1_15,RX Message Buffer Data Field 15 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end tree.end tree "CANFD1_NS" base ad:0x50382000 group.long 0x0++0xF line.long 0x0 "CFDC0NCFG,Nominal Bitrate Configuration Register" hexmask.long.byte 0x0 25.--31. 1. "NTSEG2,Timing Segment 2" hexmask.long.byte 0x0 17.--24. 1. "NTSEG1,Timing Segment 1" newline hexmask.long.byte 0x0 10.--16. 1. "NSJW,Resynchronization Jump Width" hexmask.long.word 0x0 0.--9. 1. "NBRP,Channel Nominal Baud Rate Prescaler" line.long 0x4 "CFDC0CTR,Control Register" bitfld.long 0x4 31. "ROM,Restricted Operation Mode" "0: Restricted operation mode disabled,1: Restricted operation mode enabled" bitfld.long 0x4 30. "BFT,Bit Flip Test" "0: First data bit of reception stream not inverted,1: First data bit of reception stream inverted" newline bitfld.long 0x4 25.--26. "CTMS,Channel Test Mode Select" "0: Basic test mode,1: Listen-only mode,?,?" bitfld.long 0x4 24. "CTME,Channel Test Mode Enable" "0: Channel test mode disabled,1: Channel test mode enabled" newline bitfld.long 0x4 23. "ERRD,Channel Error Display" "0: Only the first set of error codes displayed,1: Accumulated error codes displayed" bitfld.long 0x4 21.--22. "BOM,Channel Bus-Off Mode" "0: Normal mode (comply with ISO 11898-1),1: Entry to Halt mode automatically at bus-off start,?,?" newline bitfld.long 0x4 19. "TDCVFIE,Transceiver Delay Compensation Violation Interrupt Enable" "0: Transceiver delay compensation violation..,1: Transceiver delay compensation violation.." bitfld.long 0x4 18. "SOCOIE,Successful Occurrence Counter Overflow Interrupt Enable" "0: Successful occurrence counter overflow interrupt..,1: Successful occurrence counter overflow interrupt.." newline bitfld.long 0x4 17. "EOCOIE,Error Occurrence Counter Overflow Interrupt Enable" "0: Error occurrence counter overflow interrupt..,1: Error occurrence counter overflow interrupt.." bitfld.long 0x4 16. "TAIE,Transmission Abort Interrupt Enable" "0: TX abort interrupt disabled,1: TX abort interrupt enabled" newline bitfld.long 0x4 15. "ALIE,Arbitration Lost Interrupt Enable" "0: Arbitration lost interrupt disabled,1: Arbitration lost interrupt enabled" bitfld.long 0x4 14. "BLIE,Bus Lock Interrupt Enable" "0: Bus lock interrupt disabled,1: Bus lock interrupt enabled" newline bitfld.long 0x4 13. "OLIE,Overload Interrupt Enable" "0: Overload interrupt disabled,1: Overload interrupt enabled" bitfld.long 0x4 12. "BORIE,Bus-Off Recovery Interrupt Enable" "0: Bus-off recovery interrupt disabled,1: Bus-off recovery interrupt enabled" newline bitfld.long 0x4 11. "BOEIE,Bus-Off Entry Interrupt Enable" "0: Bus-off entry interrupt disabled,1: Bus-off entry interrupt enabled" bitfld.long 0x4 10. "EPIE,Error Passive Interrupt Enable" "0: Error passive interrupt disabled,1: Error passive interrupt enabled" newline bitfld.long 0x4 9. "EWIE,Error Warning Interrupt Enable" "0: Error warning interrupt disabled,1: Error warning interrupt enabled" bitfld.long 0x4 8. "BEIE,Bus Error Interrupt Enable" "0: Bus error interrupt disabled,1: Bus error interrupt enabled" newline bitfld.long 0x4 3. "RTBO,Return from Bus-Off" "0: Channel is not forced to return from bus-off,1: Channel is forced to return from bus-off" bitfld.long 0x4 2. "CSLPR,Channel Sleep Request" "0: Channel sleep request disabled,1: Channel sleep request enabled" newline bitfld.long 0x4 0.--1. "CHMDC,Channel Mode Control" "0: Channel operation mode request,1: Channel reset request,?,?" line.long 0x8 "CFDC0STS,Status Register" hexmask.long.byte 0x8 24.--31. 1. "TEC,Transmission Error Count" hexmask.long.byte 0x8 16.--23. 1. "REC,Reception Error Count" newline bitfld.long 0x8 8. "ESIF,Error State Indication Flag" "0: No CANFD message has been received when the ESI..,1: At least one CANFD message was received when the.." rbitfld.long 0x8 7. "COMSTS,Channel Communication Status" "0: Channel is not ready for communication,1: Channel is ready for communication" newline rbitfld.long 0x8 6. "RECSTS,Channel Receive Status" "0: Channel is not receiving,1: Channel is receiving" rbitfld.long 0x8 5. "TRMSTS,Channel Transmit Status" "0: Channel is not transmitting,1: Channel is transmitting" newline rbitfld.long 0x8 4. "BOSTS,Channel Bus-Off Status" "0: Channel not in bus-off state,1: Channel in bus-off state" rbitfld.long 0x8 3. "EPSTS,Channel Error Passive Status" "0: Channel not in error passive state,1: Channel in error passive state" newline rbitfld.long 0x8 2. "CSLPSTS,Channel Sleep Status" "0: Channel not in Sleep mode,1: Channel in Sleep mode" rbitfld.long 0x8 1. "CHLTSTS,Channel Halt Status" "0: Channel not in Halt mode,1: Channel in Halt mode" newline rbitfld.long 0x8 0. "CRSTSTS,Channel Reset Status" "0: Channel not in Reset mode,1: Channel in Reset mode" line.long 0xC "CFDC0ERFL,Error Flag Register" hexmask.long.word 0xC 16.--30. 1. "CRCREG,CRC Register value" bitfld.long 0xC 14. "ADERR,Acknowledge Delimiter Error" "0: Channel acknowledge delimiter error not detected,1: Channel acknowledge delimiter error detected" newline bitfld.long 0xC 13. "B0ERR,Bit 0 Error" "0: Channel bit 0 error not detected,1: Channel bit 0 error detected" bitfld.long 0xC 12. "B1ERR,Bit 1 Error" "0: Channel bit 1 error not detected,1: Channel bit 1 error detected" newline bitfld.long 0xC 11. "CERR,CRC Error" "0: Channel CRC error not detected,1: Channel CRC error detected" bitfld.long 0xC 10. "AERR,Acknowledge Error" "0: Channel acknowledge error not detected,1: Channel acknowledge error detected" newline bitfld.long 0xC 9. "FERR,Form Error" "0: Channel form error not detected,1: Channel form error detected" bitfld.long 0xC 8. "SERR,Stuff Error" "0: Channel stuff error not detected,1: Channel stuff error detected" newline bitfld.long 0xC 7. "ALF,Arbitration Lost Flag" "0: Channel arbitration lost not detected,1: Channel arbitration lost detected" bitfld.long 0xC 6. "BLF,Bus Lock Flag" "0: Channel bus lock not detected,1: Channel bus lock detected" newline bitfld.long 0xC 5. "OVLF,Overload Flag" "0: Channel overload not detected,1: Channel overload detected" bitfld.long 0xC 4. "BORF,Bus-Off Recovery Flag" "0: Channel bus-off recovery not detected,1: Channel bus-off recovery detected" newline bitfld.long 0xC 3. "BOEF,Bus-Off Entry Flag" "0: Channel bus-off entry not detected,1: Channel bus-off entry detected" bitfld.long 0xC 2. "EPF,Error Passive Flag" "0: Channel error passive not detected,1: Channel error passive detected" newline bitfld.long 0xC 1. "EWF,Error Warning Flag" "0: Channel error warning not detected,1: Channel error warning detected" bitfld.long 0xC 0. "BEF,Bus Error Flag" "0: Channel bus error not detected,1: Channel bus error detected" group.long 0x14++0x7 line.long 0x0 "CFDGCFG,Global Configuration Register" hexmask.long.word 0x0 16.--31. 1. "ITRCP,Interval Timer Reference Clock Prescaler" bitfld.long 0x0 12. "TSSS,Timestamp Source Select" "0: Source clock for timestamp counter is peripheral..,1: Source clock for timestamp counter is bit time.." newline hexmask.long.byte 0x0 8.--11. 1. "TSP,Timestamp Prescaler" bitfld.long 0x0 5. "CMPOC,CANFD Message Payload Overflow Configuration" "0: Message is rejected,1: Message payload is cut to fit to configured.." newline bitfld.long 0x0 4. "DCS,Data Link Controller Clock Select" "0: CANFD core clock (CANFDCLK),1: External oscillator clock (CANMCLK)" bitfld.long 0x0 3. "MME,Mirror Mode Enable" "0: Mirror mode disabled,1: Mirror mode enabled" newline bitfld.long 0x0 2. "DRE,DLC Replacement Enable" "0: DLC replacement disabled,1: DLC replacement enabled" bitfld.long 0x0 1. "DCE,DLC Check Enable" "0: DLC check disabled,1: DLC check enabled" newline bitfld.long 0x0 0. "TPRI,Transmission Priority" "0: ID priority,1: Message buffer number priority" line.long 0x4 "CFDGCTR,Global Control Register" bitfld.long 0x4 16. "TSRST,Timestamp Reset" "0: Timestamp not reset,1: Timestamp reset" bitfld.long 0x4 11. "CMPOFIE,CANFD Message Payload Overflow Flag Interrupt Enable" "0: CANFD message payload overflow flag interrupt..,1: CANFD message payload overflow flag interrupt.." newline bitfld.long 0x4 10. "THLEIE,TX History List Entry Lost Interrupt Enable" "0: TX history list entry lost interrupt disabled,1: TX history list entry lost interrupt enabled" bitfld.long 0x4 9. "MEIE,Message Lost Error Interrupt Enable" "0: Message lost error interrupt disabled,1: Message lost error interrupt enabled" newline bitfld.long 0x4 8. "DEIE,DLC Check Interrupt Enable" "0: DLC check interrupt disabled,1: DLC check interrupt enabled" bitfld.long 0x4 2. "GSLPR,Global Sleep Request" "0: Global sleep request disabled,1: Global sleep request enabled" newline bitfld.long 0x4 0.--1. "GMDC,Global Mode Control" "0: Global operation mode request,1: Global reset mode request,?,?" rgroup.long 0x1C++0x3 line.long 0x0 "CFDGSTS,Global Status Register" bitfld.long 0x0 3. "GRAMINIT,Global RAM Initialization" "0: RAM initialization is complete,1: RAM initialization is ongoing" bitfld.long 0x0 2. "GSLPSTS,Global Sleep Status" "0: Not in Sleep mode,1: In Sleep mode" newline bitfld.long 0x0 1. "GHLTSTS,Global Halt Status" "0: Not in Halt mode,1: In Halt mode" bitfld.long 0x0 0. "GRSTSTS,Global Reset Status" "0: Not in Reset mode,1: In Reset mode" group.long 0x20++0x3 line.long 0x0 "CFDGERFL,Global Error Flag Register" bitfld.long 0x0 16. "EEF0,ECC Error Flag" "0: ECC error not detected during TX-SCAN,1: ECC error detected during TX-SCAN" bitfld.long 0x0 3. "CMPOF,CANFD Message Payload Overflow Flag" "0: CANFD message payload overflow not detected,1: CANFD message payload overflow detected" newline rbitfld.long 0x0 2. "THLES,TX History List Entry Lost Error Status" "0: TX history list entry lost error not detected,1: TX history list entry lost error detected" rbitfld.long 0x0 1. "MES,Message Lost Error Status" "0: Message lost error not detected,1: Message lost error detected" newline bitfld.long 0x0 0. "DEF,DLC Error Flag" "0: DLC error not detected,1: DLC error detected" rgroup.long 0x24++0x3 line.long 0x0 "CFDGTSC,Global Timestamp Counter Register" hexmask.long.word 0x0 0.--15. 1. "TS,Timestamp value" group.long 0x28++0xB line.long 0x0 "CFDGAFLECTR,Global Acceptance Filter List Entry Control Register" bitfld.long 0x0 8. "AFLDAE,Acceptance Filter List Data Access Enable" "0: Acceptance Filter List data access disabled,1: Acceptance Filter List data access enabled" line.long 0x4 "CFDGAFLCFG,Global Acceptance Filter List Configuration Register" hexmask.long.byte 0x4 16.--20. 1. "RNC0,Rule Number" line.long 0x8 "CFDRMNB,RX Message Buffer Number Register" bitfld.long 0x8 8.--10. "RMPLS,Reception Message Buffer Payload Data Size" "0: 8 bytes,1: 12 bytes,?,?,?,?,?,?" hexmask.long.byte 0x8 0.--4. 1. "NRXMB,Number of RX Message Buffers" group.word 0x34++0x1 line.word 0x0 "CFDRMND,RX Message Buffer New Data Register" hexmask.word 0x0 0.--15. 1. "RMNS,RX Message Buffer New Data Status" group.word 0x38++0x1 line.word 0x0 "CFDRMIEC,RX Message Buffer Interrupt Enable Configuration Register" hexmask.word 0x0 0.--15. 1. "RMIE,RX Message Buffer Interrupt Enable" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x3C)++0x3 line.long 0x0 "CFDRFCC$1,RX FIFO Configuration/Control Registers %s" bitfld.long 0x0 13.--15. "RFIGCV,RX FIFO Interrupt Generation Counter Value" "0: Interrupt generated when FIFO is 1/8th full,1: Interrupt generated when FIFO is 1/4th full,?,?,?,?,?,?" bitfld.long 0x0 12. "RFIM,RX FIFO Interrupt Mode" "0: Interrupt generated when RX FIFO counter reaches..,1: Interrupt generated at the end of every received.." newline bitfld.long 0x0 8.--10. "RFDC,RX FIFO Depth Configuration" "0: FIFO Depth = 0 message,1: FIFO Depth = 4 messages,?,?,?,?,?,?" bitfld.long 0x0 4.--6. "RFPLS,Rx FIFO Payload Data Size Configuration" "0: 8 bytes,1: 12 bytes,?,?,?,?,?,?" newline bitfld.long 0x0 1. "RFIE,RX FIFO Interrupt Enable" "0: FIFO interrupt generation disabled,1: FIFO interrupt generation enabled" bitfld.long 0x0 0. "RFE,RX FIFO Enable" "0: FIFO disabled,1: FIFO enabled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x44)++0x3 line.long 0x0 "CFDRFSTS$1,RX FIFO Status Registers %s" hexmask.long.byte 0x0 8.--13. 1. "RFMC,RX FIFO Message Count" bitfld.long 0x0 3. "RFIF,RX FIFO Interrupt Flag" "0: FIFO interrupt condition not satisfied,1: FIFO interrupt condition satisfied" newline bitfld.long 0x0 2. "RFMLT,RX FIFO Message Lost" "0: No message lost in FIFO,1: FIFO message lost" rbitfld.long 0x0 1. "RFFLL,RX FIFO Full" "0: FIFO not full,1: FIFO full" newline rbitfld.long 0x0 0. "RFEMP,RX FIFO Empty" "0: FIFO not empty,1: FIFO empty" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x4C)++0x3 line.long 0x0 "CFDRFPCTR$1,RX FIFO Pointer Control Registers %s" hexmask.long.byte 0x0 0.--7. 1. "RFPC,RX FIFO Pointer Control" repeat.end group.long 0x54++0x7 line.long 0x0 "CFDCFCC,Common FIFO Configuration/Control Register" hexmask.long.byte 0x0 24.--31. 1. "CFITT,Common FIFO Interval Transmission Time" bitfld.long 0x0 21.--23. "CFDC,Common FIFO Depth Configuration" "0: FIFO Depth = 0 message,1: FIFO Depth = 4 messages,?,?,?,?,?,?" newline bitfld.long 0x0 16.--17. "CFTML,Common FIFO TX Message Buffer Link" "0,1,2,3" bitfld.long 0x0 13.--15. "CFIGCV,Common FIFO Interrupt Generation Counter Value" "0: Interrupt generated when FIFO is 1/8th full,1: Interrupt generated when FIFO is 1/4th full,?,?,?,?,?,?" newline bitfld.long 0x0 12. "CFIM,Common FIFO Interrupt Mode" "0: RX FIFO mode: RX interrupt generated when Common..,1: RX FIFO mode: RX interrupt generated at the end.." bitfld.long 0x0 11. "CFITR,Common FIFO Interval Timer Resolution" "0: Reference clock period × 1,1: Reference clock period × 10" newline bitfld.long 0x0 10. "CFITSS,Common FIFO Interval Timer Source Select" "0: Reference clock (× 1 / × 10 period),1: Bit time clock of related channel (FIFO is.." bitfld.long 0x0 8. "CFM,Common FIFO Mode" "0: RX FIFO mode,1: TX FIFO mode" newline bitfld.long 0x0 4.--6. "CFPLS,Common FIFO Payload Data Size Configuration" "0: 8 bytes,1: 12 bytes,?,?,?,?,?,?" bitfld.long 0x0 2. "CFTXIE,Common FIFO TX Interrupt Enable" "0: FIFO interrupt generation disabled for Frame TX,1: FIFO interrupt generation enabled for Frame TX" newline bitfld.long 0x0 1. "CFRXIE,Common FIFO RX Interrupt Enable" "0: FIFO interrupt generation disabled for Frame RX,1: FIFO interrupt generation enabled for Frame RX" bitfld.long 0x0 0. "CFE,Common FIFO Enable" "0: FIFO disabled,1: FIFO enabled" line.long 0x4 "CFDCFSTS,Common FIFO Status Register" hexmask.long.byte 0x4 8.--13. 1. "CFMC,Common FIFO Message Count" bitfld.long 0x4 4. "CFTXIF,Common TX FIFO Interrupt Flag" "0: FIFO interrupt condition not satisfied after..,1: FIFO Interrupt condition satisfied after frame.." newline bitfld.long 0x4 3. "CFRXIF,Common RX FIFO Interrupt Flag" "0: FIFO interrupt condition not satisfied after..,1: FIFO interrupt condition satisfied after frame.." bitfld.long 0x4 2. "CFMLT,Common FIFO Message Lost" "0: Number of message lost in FIFO,1: FIFO message lost" newline rbitfld.long 0x4 1. "CFFLL,Common FIFO Full" "0: FIFO not full,1: FIFO full" rbitfld.long 0x4 0. "CFEMP,Common FIFO Empty" "0: FIFO not empty,1: FIFO empty" wgroup.long 0x5C++0x3 line.long 0x0 "CFDCFPCTR,Common FIFO Pointer Control Register" hexmask.long.byte 0x0 0.--7. 1. "CFPC,Common FIFO Pointer Control" rgroup.long 0x60++0xF line.long 0x0 "CFDFESTS,FIFO Empty Status Register" bitfld.long 0x0 8. "CFEMP,Common FIFO Empty Status" "0: Corresponding FIFO not empty,1: Corresponding FIFO empty" bitfld.long 0x0 0.--1. "RFXEMP,RX FIFO Empty Status" "0: Corresponding FIFO not empty,1: Corresponding FIFO empty,?,?" line.long 0x4 "CFDFFSTS,FIFO Full Status Register" bitfld.long 0x4 8. "CFFLL,Common FIF0 Full Status" "0: Corresponding FIFO not full,1: Corresponding FIFO full" bitfld.long 0x4 0.--1. "RFXFLL,RX FIF0 Full Status" "0: Corresponding FIFO not full,1: Corresponding FIFO full,?,?" line.long 0x8 "CFDFMSTS,FIFO Message Lost Status Register" bitfld.long 0x8 8. "CFMLT,Common FIFO Message Lost Status" "0: Corresponding FIFO Message Lost flag not set,1: Corresponding FIFO Message Lost flag set" bitfld.long 0x8 0.--1. "RFXMLT,RX FIFO Message Lost Status" "0: Corresponding FIFO Message Lost flag not set,1: Corresponding FIFO Message Lost flag set,?,?" line.long 0xC "CFDRFISTS,RX FIFO Interrupt Flag Status Register" bitfld.long 0xC 0.--1. "RFXIF,RX FIFO[x] Interrupt Flag Status" "0: Corresponding RX FIFO Interrupt flag not set,1: Corresponding RX FIFO Interrupt flag set,?,?" repeat 4. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x70)++0x0 line.byte 0x0 "CFDTMC$1,TX Message Buffer Control Registers %s" bitfld.byte 0x0 2. "TMOM,TX Message Buffer One-shot Mode" "0: TX message buffer not configured in one-shot mode,1: TX message buffer configured in one-shot mode" bitfld.byte 0x0 1. "TMTAR,TX Message Buffer Transmission Abort Request" "0: TX message buffer transmission request abort not..,1: TX message buffer transmission request abort.." newline bitfld.byte 0x0 0. "TMTR,TX Message Buffer Transmission Request" "0: TX Message buffer transmission not requested,1: TX message buffer transmission requested" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x74)++0x0 line.byte 0x0 "CFDTMSTS$1,TX Message Buffer Status Registers %s" rbitfld.byte 0x0 4. "TMTARM,TX Message Buffer Transmission Abort Request Mirrored" "0: TX message buffer transmission request abort not..,1: TX message buffer transmission request abort.." rbitfld.byte 0x0 3. "TMTRM,TX Message Buffer Transmission Request Mirrored" "0: TX message buffer transmission not requested,1: TX message buffer transmission requested" newline bitfld.byte 0x0 1.--2. "TMTRF,TX Message Buffer Transmission Result Flag" "0: No result,1: Transmission aborted from the TX message buffer,?,?" rbitfld.byte 0x0 0. "TMTSTS,TX Message Buffer Transmission Status" "0: No on-going transmission,1: On-going transmission" repeat.end rgroup.long 0x78++0xF line.long 0x0 "CFDTMTRSTS,TX Message Buffer Transmission Request Status Register" hexmask.long.byte 0x0 0.--3. 1. "CFDTMTRSTS,TX Message Buffer Transmission Request Status" line.long 0x4 "CFDTMTARSTS,TX Message Buffer Transmission Abort Request Status Register" hexmask.long.byte 0x4 0.--3. 1. "CFDTMTARSTS,TX Message Buffer Transmission Abort Request Status" line.long 0x8 "CFDTMTCSTS,TX Message Buffer Transmission Completion Status Register" hexmask.long.byte 0x8 0.--3. 1. "CFDTMTCSTS,TX Message Buffer Transmission Completion Status" line.long 0xC "CFDTMTASTS,TX Message Buffer Transmission Abort Status Register" hexmask.long.byte 0xC 0.--3. 1. "CFDTMTASTS,TX Message Buffer Transmission Abort Status" group.long 0x88++0xB line.long 0x0 "CFDTMIEC,TX Message Buffer Interrupt Enable Configuration Register" hexmask.long.byte 0x0 0.--3. 1. "TMIEg,TX Message Buffer Interrupt Enable" line.long 0x4 "CFDTXQCC,TX Queue Configuration/Control Register" bitfld.long 0x4 8.--9. "TXQDC,TX Queue Depth Configuration" "0: 0 messages,1: Reserved,?,?" bitfld.long 0x4 7. "TXQIM,TX Queue Interrupt Mode" "0: When the last message is successfully transmitted,1: At every successful transmission" newline bitfld.long 0x4 5. "TXQTXIE,TX Queue TX Interrupt Enable" "0: TX Queue TX interrupt disabled,1: TX Queue TX interrupt enabled" bitfld.long 0x4 0. "TXQE,TX Queue Enable" "0: TX Queue disabled,1: TX Queue enabled" line.long 0x8 "CFDTXQSTS,TX Queue Status Register" rbitfld.long 0x8 8.--10. "TXQMC,TX Queue Message Count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 2. "TXQTXIF,TX Queue TX Interrupt Flag" "0: TX Queue interrupt condition not satisfied after..,1: TX Queue interrupt condition satisfied after a.." newline rbitfld.long 0x8 1. "TXQFLL,TX Queue Full" "0: TX Queue not full,1: TX Queue full" rbitfld.long 0x8 0. "TXQEMP,TX Queue Empty" "0: TX Queue not empty,1: TX Queue empty" wgroup.long 0x94++0x3 line.long 0x0 "CFDTXQPCTR,TX Queue Pointer Control Register" hexmask.long.byte 0x0 0.--7. 1. "TXQPC,TX Queue Pointer Control" group.long 0x98++0x7 line.long 0x0 "CFDTHLCC,TX History List Configuration/Control Register" bitfld.long 0x0 10. "THLDTE,TX History List Dedicated TX Enable" "0: TX FIFO + TX Queue,1: Flat TX MB + TX FIFO + TX Queue" bitfld.long 0x0 9. "THLIM,TX History List Interrupt Mode" "0: Interrupt generated if TX History List level..,1: Interrupt generated for every successfully.." newline bitfld.long 0x0 8. "THLIE,TX History List Interrupt Enable" "0: TX History List Interrupt disabled,1: TX History List Interrupt enabled" bitfld.long 0x0 0. "THLE,TX History List Enable" "0: TX History List disabled,1: TX History List enabled" line.long 0x4 "CFDTHLSTS,TX History List Status Register" hexmask.long.byte 0x4 8.--11. 1. "THLMC,TX History List Message Count" bitfld.long 0x4 3. "THLIF,TX History List Interrupt Flag" "0: TX History List interrupt condition not satisfied,1: TX History List interrupt condition satisfied" newline bitfld.long 0x4 2. "THLELT,TX History List Entry Lost" "0: No entry lost in TX History List,1: TX History List entry Lost" rbitfld.long 0x4 1. "THLFLL,TX History List Full" "0: TX History List not full,1: TX History List full" newline rbitfld.long 0x4 0. "THLEMP,TX History List Empty" "0: TX History List not empty,1: TX History List empty" wgroup.long 0xA0++0x3 line.long 0x0 "CFDTHLPCTR,TX History List Pointer Control Register" hexmask.long.byte 0x0 0.--7. 1. "THLPC,TX History List Pointer Control" rgroup.long 0xA4++0x3 line.long 0x0 "CFDGTINTSTS,Global TX Interrupt Status Register" bitfld.long 0x0 4. "THIF0,TX History List Interrupt" "0: Channel n TX History List Interrupt flag not set,1: Channel n TX History List Interrupt flag set" bitfld.long 0x0 3. "CFTIF0,COM FIFO TX Mode Interrupt Flag" "0: Channel n COM FIFO TX Mode Interrupt flag not set,1: Channel n COM FIFO TX Mode Interrupt flag set" newline bitfld.long 0x0 2. "TQIF0,TX Queue Interrupt Flag" "0: Channel n TX Queue Interrupt flag not set,1: Channel n TX Queue Interrupt flag set" bitfld.long 0x0 1. "TAI0,TX Abort Interrupt Flag" "0: Channel n TX Abort Interrupt flag not set,1: Channel n TX Abort Interrupt flag set" newline bitfld.long 0x0 0. "TSIF0,TX Successful Interrupt Flag" "0: Channel n TX Successful Interrupt flag not set,1: Channel n TX Successful Interrupt flag set" group.long 0xA8++0xB line.long 0x0 "CFDGTSTCFG,Global Test Configuration Register" hexmask.long.byte 0x0 16.--19. 1. "RTMPS,RAM Test Mode Page Select" line.long 0x4 "CFDGTSTCTR,Global Test Control Register" bitfld.long 0x4 2. "RTME,RAM Test Mode Enable" "0: RAM test mode disabled,1: RAM test mode enabled" line.long 0x8 "CFDGFDCFG,Global FD Configuration Register" bitfld.long 0x8 8.--9. "TSCCFG,Timestamp Capture Configuration" "0: Timestamp capture at the sample point of SOF..,1: Timestamp capture at frame valid indication,?,?" bitfld.long 0x8 0. "RPED,RES Bit Protocol Exception Disable" "0: Protocol exception event detection enabled,1: Protocol exception event detection disabled" wgroup.long 0xB8++0x3 line.long 0x0 "CFDGLOCKK,Global Lock Key Register" hexmask.long.word 0x0 0.--15. 1. "LOCK,Lock Key" group.long 0xC0++0xB line.long 0x0 "CFDGAFLIGNENT,Global AFL Ignore Entry Register" hexmask.long.byte 0x0 0.--3. 1. "IRN,Ignore Rule Number" line.long 0x4 "CFDGAFLIGNCTR,Global AFL Ignore Control Register" hexmask.long.byte 0x4 8.--15. 1. "KEY,Key Code" bitfld.long 0x4 0. "IREN,Ignore Rule Enable" "0: AFL entry number is not ignored,1: AFL entry number is ignored" line.long 0x8 "CFDCDTCT,DMA Transfer Control Register" bitfld.long 0x8 8. "CFDMAE,DMA Transfer Enable for Common FIFO 0" "0: DMA transfer request disabled,1: DMA transfer request enabled" bitfld.long 0x8 1. "RFDMAE1,DMA Transfer Enable for RXFIFO 1" "0: DMA transfer request disabled,1: DMA transfer request enabled" newline bitfld.long 0x8 0. "RFDMAE0,DMA Transfer Enable for RXFIFO 0" "0: DMA transfer request disabled,1: DMA transfer request enabled" rgroup.long 0xCC++0x3 line.long 0x0 "CFDCDTSTS,DMA Transfer Status Register" bitfld.long 0x0 8. "CFDMASTS,DMA Transfer Status only for Common FIFO" "0: DMA transfer stopped,1: DMA transfer on going" bitfld.long 0x0 1. "RFDMASTS1,DMA Transfer Status for RX FIFO 1" "0: DMA transfer stopped,1: DMA transfer on going" newline bitfld.long 0x0 0. "RFDMASTS0,DMA Transfer Status for RX FIFO 0" "0: DMA transfer stopped,1: DMA transfer on going" group.long 0xD8++0x3 line.long 0x0 "CFDGRSTC,Global SW reset Register" hexmask.long.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.long 0x0 0. "SRST,SW Reset" "0: Normal state,1: SW reset state" group.long 0x100++0xF line.long 0x0 "CFDC0DCFG,Data Bitrate Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "DSJW,Resynchronization Jump Width" hexmask.long.byte 0x0 16.--19. 1. "DTSEG2,Timing Segment 2" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Timing Segment 1" hexmask.long.byte 0x0 0.--7. 1. "DBRP,Channel Data Baud Rate Prescaler" line.long 0x4 "CFDC0FDCFG,CANFD Configuration Register" bitfld.long 0x4 30. "CLOE,Classical CAN Enable" "0: Classical CAN mode disabled,1: Classical CAN mode enabled" bitfld.long 0x4 29. "REFE,RX Edge Filter Enable" "0: RX edge filter disabled,1: RX edge filter enabled" newline bitfld.long 0x4 28. "FDOE,FD-Only Enable" "0: FD-only mode disabled,1: FD-only mode enabled" hexmask.long.byte 0x4 16.--23. 1. "TDCO,Transceiver Delay Compensation Offset" newline bitfld.long 0x4 10. "ESIC,Error State Indication Configuration" "0: The ESI bit in the frame represents the error..,1: The ESI bit in the frame represents the error.." bitfld.long 0x4 9. "TDCE,Transceiver Delay Compensation Enable" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled" newline bitfld.long 0x4 8. "TDCOC,Transceiver Delay Compensation Offset Configuration" "0: Measured + offset,1: Offset-only" bitfld.long 0x4 0.--2. "EOCCFG,Error Occurrence Counter Configuration" "0: All transmitter or receiver CAN frames,1: All transmitter CAN frames,?,?,?,?,?,?" line.long 0x8 "CFDC0FDCTR,CANFD Control Register" bitfld.long 0x8 1. "SOCCLR,Successful Occurrence Counter Clear" "0: No successful occurrence counter clear,1: Clear successful occurrence counter" bitfld.long 0x8 0. "EOCCLR,Error Occurrence Counter Clear" "0: No error occurrence counter clear,1: Clear error occurrence counter" line.long 0xC "CFDC0FDSTS,CANFD Status Register" hexmask.long.byte 0xC 24.--31. 1. "SOC,Successful occurrence counter" hexmask.long.byte 0xC 16.--23. 1. "EOC,Error Occurrence Counter" newline bitfld.long 0xC 15. "TDCVF,Transceiver Delay Compensation Violation Flag" "0: Transceiver delay compensation violation has not..,1: Transceiver delay compensation violation has.." bitfld.long 0xC 9. "SOCO,Successful Occurrence Counter Overflow" "0: Successful occurrence counter has not overflowed,1: Successful occurrence counter has overflowed" newline bitfld.long 0xC 8. "EOCO,Error Occurrence Counter Overflow" "0: Error occurrence counter has not overflowed,1: Error occurrence counter has overflowed" hexmask.long.byte 0xC 0.--7. 1. "TDCR,Transceiver Delay Compensation Result" rgroup.long 0x110++0x3 line.long 0x0 "CFDC0FDCRC,CANFD CRC Register" hexmask.long.byte 0x0 24.--27. 1. "SCNT,Stuff bit count" hexmask.long.tbyte 0x0 0.--20. 1. "CRCREG,CRC Register value" repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x120)++0x3 line.long 0x0 "CFDGAFLID$1,Global Acceptance Filter List ID Registers" bitfld.long 0x0 31. "GAFLIDE,Global Acceptance Filter List Entry IDE Field" "0: Standard identifier of rule entry ID is valid..,1: Extended identifier of rule entry ID is valid.." bitfld.long 0x0 30. "GAFLRTR,Global Acceptance Filter List Entry RTR Field" "0: Data frame,1: Remote frame" newline bitfld.long 0x0 29. "GAFLLB,Global Acceptance Filter List Entry Loopback Configuration" "0: Global Acceptance Filter List entry ID for..,1: Global Acceptance Filter List entry ID for.." hexmask.long 0x0 0.--28. 1. "GAFLID,Global Acceptance Filter List Entry ID Field" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x124)++0x3 line.long 0x0 "CFDGAFLM$1,Global Acceptance Filter List Mask Registers" bitfld.long 0x0 31. "GAFLIDEM,Global Acceptance Filter List IDE Mask" "0: IDE bit is not used for ID matching,1: IDE bit is used for ID matching" bitfld.long 0x0 30. "GAFLRTRM,Global Acceptance Filter List Entry RTR Mask" "0: RTR bit is not used for ID matching,1: RTR bit is used for ID matching" newline bitfld.long 0x0 29. "GAFLIFL1,Global Acceptance Filter List Information Label 1" "0,1" hexmask.long 0x0 0.--28. 1. "GAFLIDM,Global Acceptance Filter List ID Mask Field" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x128)++0x3 line.long 0x0 "CFDGAFLP0$1,Global Acceptance Filter List Pointer 0 Registers" hexmask.long.word 0x0 16.--31. 1. "GAFLPTR,Global Acceptance Filter List Pointer" bitfld.long 0x0 15. "GAFLRMV,Global Acceptance Filter List RX Message Buffer Valid" "0: Single message buffer direction pointer is invalid,1: Single message buffer direction pointer is valid" newline hexmask.long.byte 0x0 8.--12. 1. "GAFLRMDP,Global Acceptance Filter List RX Message Buffer Direction Pointer" bitfld.long 0x0 7. "GAFLIFL0,Global Acceptance Filter List Information Label 0" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "GAFLDLC,Global Acceptance Filter List DLC Field" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x12C)++0x3 line.long 0x0 "CFDGAFLP1$1,Global Acceptance Filter List Pointer 1 Registers" bitfld.long 0x0 8. "GAFLFDP8,Global Acceptance Filter List FIFO Direction Pointer" "0: Disable Common FIFO as target for reception,1: Enable Common FIFO as target for reception" bitfld.long 0x0 1. "GAFLFDP1,Global Acceptance Filter List FIFO Direction Pointer" "0: Disable RX FIFO 1 as target for reception,1: Enable RX FIFO 1 as target for reception" newline bitfld.long 0x0 0. "GAFLFDP0,Global Acceptance Filter List FIFO Direction Pointer" "0: Disable RX FIFO 0 as target for reception,1: Enable RX FIFO 0 as target for reception" repeat.end repeat 64. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x280)++0x3 line.long 0x0 "CFDRPGACC$1,RAM Test Page Access Registers %s" hexmask.long 0x0 0.--31. 1. "RDTA,RAM Data Test Access" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x520)++0x3 line.long 0x0 "CFDRFID$1,RX FIFO Access ID Register %s" bitfld.long 0x0 31. "RFIDE,RX FIFO Buffer IDE bit" "0: STD-ID has been received,1: EXT-ID has been received" bitfld.long 0x0 30. "RFRTR,RX FIFO Buffer RTR bit" "0: Data frame,1: Remote frame" newline hexmask.long 0x0 0.--28. 1. "RFID,RX FIFO Buffer ID Field" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x524)++0x3 line.long 0x0 "CFDRFPTR$1,RX FIFO Access Pointer Register %s" hexmask.long.byte 0x0 28.--31. 1. "RFDLC,RX FIFO Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RFTS,RX FIFO Timestamp Value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x528)++0x3 line.long 0x0 "CFDRFFDSTS$1,RX FIFO Access CANFD Status Register %s" hexmask.long.word 0x0 16.--31. 1. "CFDRFPTR,RX FIFO Buffer Pointer Field" bitfld.long 0x0 8.--9. "RFIFL,RX FIFO Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RFFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RFBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RFESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x52C)++0x3 line.long 0x0 "CFDRFDF$1_0,RX FIFO Access Data Field 0 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x530)++0x3 line.long 0x0 "CFDRFDF$1_1,RX FIFO Access Data Field 1 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x534)++0x3 line.long 0x0 "CFDRFDF$1_2,RX FIFO Access Data Field 2 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x538)++0x3 line.long 0x0 "CFDRFDF$1_3,RX FIFO Access Data Field 3 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x53C)++0x3 line.long 0x0 "CFDRFDF$1_4,RX FIFO Access Data Field 4 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x540)++0x3 line.long 0x0 "CFDRFDF$1_5,RX FIFO Access Data Field 5 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x544)++0x3 line.long 0x0 "CFDRFDF$1_6,RX FIFO Access Data Field 6 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x548)++0x3 line.long 0x0 "CFDRFDF$1_7,RX FIFO Access Data Field 7 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x54C)++0x3 line.long 0x0 "CFDRFDF$1_8,RX FIFO Access Data Field 8 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x550)++0x3 line.long 0x0 "CFDRFDF$1_9,RX FIFO Access Data Field 9 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x554)++0x3 line.long 0x0 "CFDRFDF$1_10,RX FIFO Access Data Field 10 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x558)++0x3 line.long 0x0 "CFDRFDF$1_11,RX FIFO Access Data Field 11 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x55C)++0x3 line.long 0x0 "CFDRFDF$1_12,RX FIFO Access Data Field 12 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x560)++0x3 line.long 0x0 "CFDRFDF$1_13,RX FIFO Access Data Field 13 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x564)++0x3 line.long 0x0 "CFDRFDF$1_14,RX FIFO Access Data Field 14 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x568)++0x3 line.long 0x0 "CFDRFDF$1_15,RX FIFO Access Data Field 15 Register %s" hexmask.long.byte 0x0 24.--31. 1. "RFDB_HH,RX FIFO Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RFDB_HL,RX FIFO Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RFDB_LH,RX FIFO Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RFDB_LL,RX FIFO Buffer Data Byte (p × 4)" repeat.end group.long 0x5B8++0xB line.long 0x0 "CFDCFID,Common FIFO Access ID Register" bitfld.long 0x0 31. "CFIDE,Common FIFO Buffer IDE Bit" "0: STD-ID will be transmitted or has been received,1: EXT-ID will be transmitted or has been received" bitfld.long 0x0 30. "CFRTR,Common FIFO Buffer RTR Bit" "0: Data Frame,1: Remote Frame" newline bitfld.long 0x0 29. "THLEN,THL Entry enable" "0: Entry will not be stored in THL after successful..,1: Entry will be stored in THL after successful TX." hexmask.long 0x0 0.--28. 1. "CFID,Common FIFO Buffer ID Field" line.long 0x4 "CFDCFPTR,Common FIFO Access Pointer Register" hexmask.long.byte 0x4 28.--31. 1. "CFDLC,Common FIFO Buffer DLC Field" hexmask.long.word 0x4 0.--15. 1. "CFTS,Common FIFO Timestamp Value" line.long 0x8 "CFDCFFDCSTS,Common FIFO Access CANFD Control/Status Register" hexmask.long.word 0x8 16.--31. 1. "CFPTR,Common FIFO Buffer Pointer Field" bitfld.long 0x8 8.--9. "CFIFL,COMMON FIFO Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x8 2. "CFFDF,CAN FD Format bit" "0: Non CANFD frame received or to transmit,1: CANFD frame received or to transmit" bitfld.long 0x8 1. "CFBRS,Bit Rate Switch bit" "0: CANFD frame received or to transmit with no bit..,1: CANFD frame received or to transmit with bit.." newline bitfld.long 0x8 0. "CFESI,Error State Indicator bit" "0: CANFD frame received or to transmit by error..,1: CANFD frame received or to transmit by error.." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5C4)++0x3 line.long 0x0 "CFDCFDF$1,Common FIFO Access Data Field %s Registers" hexmask.long.byte 0x0 24.--31. 1. "CFDB_HH,Common FIFO Buffer Data Bytes ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "CFDB_HL,Common FIFO Buffer Data Bytes ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "CFDB_LH,Common FIFO Buffer Data Bytes ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "CFDB_LL,Common FIFO Buffer Data Bytes (p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x604)++0x3 line.long 0x0 "CFDTMID$1,TX Message Buffer ID Registers" bitfld.long 0x0 31. "TMIDE,TX Message Buffer IDE bit" "0: STD-ID is transmitted,1: EXT-ID is transmitted" bitfld.long 0x0 30. "TMRTR,TX Message Buffer RTR bit" "0: Data frame,1: Remote frame" newline bitfld.long 0x0 29. "THLEN,Tx History List Entry" "0: Entry not stored in THL after successful TX,1: Entry stored in THL after successful TX" hexmask.long 0x0 0.--28. 1. "TMID,TX Message Buffer ID Field" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x608)++0x3 line.long 0x0 "CFDTMPTR$1,TX Message Buffer Pointer Register" hexmask.long.byte 0x0 28.--31. 1. "TMDLC,TX Message Buffer DLC Field" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x60C)++0x3 line.long 0x0 "CFDTMFDCTR$1,TX Message Buffer CANFD Control Register" hexmask.long.word 0x0 16.--31. 1. "TMPTR,TX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "TMIFL,TX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "TMFDF,CAN FD Format bit" "0: Non CANFD frame to transmit,1: CANFD frame to transmit" bitfld.long 0x0 1. "TMBRS,Bit Rate Switch bit" "0: CANFD frame to transmit with no bit rate switch,1: CANFD frame to transmit with bit rate switch" newline bitfld.long 0x0 0. "TMESI,Error State Indicator bit" "0: CANFD frame to transmit by error active node,1: CANFD frame to transmit by error passive node" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x610)++0x3 line.long 0x0 "CFDTMDF$1_0,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x614)++0x3 line.long 0x0 "CFDTMDF$1_1,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x618)++0x3 line.long 0x0 "CFDTMDF$1_2,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x61C)++0x3 line.long 0x0 "CFDTMDF$1_3,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x620)++0x3 line.long 0x0 "CFDTMDF$1_4,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x624)++0x3 line.long 0x0 "CFDTMDF$1_5,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x628)++0x3 line.long 0x0 "CFDTMDF$1_6,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x62C)++0x3 line.long 0x0 "CFDTMDF$1_7,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x630)++0x3 line.long 0x0 "CFDTMDF$1_8,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x634)++0x3 line.long 0x0 "CFDTMDF$1_9,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x638)++0x3 line.long 0x0 "CFDTMDF$1_10,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x63C)++0x3 line.long 0x0 "CFDTMDF$1_11,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x640)++0x3 line.long 0x0 "CFDTMDF$1_12,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x644)++0x3 line.long 0x0 "CFDTMDF$1_13,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x648)++0x3 line.long 0x0 "CFDTMDF$1_14,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4C) group.long ($2+0x64C)++0x3 line.long 0x0 "CFDTMDF$1_15,TX Message Buffer Data Field Register" hexmask.long.byte 0x0 24.--31. 1. "TMDB_HH,TX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "TMDB_HL,TX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "TMDB_LH,TX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "TMDB_LL,TX Message Buffer Data Byte ((p × 4)" repeat.end rgroup.long 0x740++0x7 line.long 0x0 "CFDTHLACC0,TX History List Access Register 0" hexmask.long.word 0x0 16.--31. 1. "TMTS,Transmit Timestamp" bitfld.long 0x0 3.--4. "BN,Buffer Number" "0,1,2,3" newline bitfld.long 0x0 0.--2. "BT,Buffer Type" "?,1: Flat TX message buffer,?,?,?,?,?,?" line.long 0x4 "CFDTHLACC1,TX History List Access Register 1" bitfld.long 0x4 16.--17. "TIFL,Transmit Information Label" "0,1,2,3" hexmask.long.word 0x4 0.--15. 1. "TID,Transmit ID" repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x920)++0x3 line.long 0x0 "CFDRMID$1,RX Message Buffer ID Registers" bitfld.long 0x0 31. "RMIDE,RX Message Buffer IDE Bit" "0: STD-ID is stored,1: EXT-ID is stored" bitfld.long 0x0 30. "RMRTR,RX Message Buffer RTR Bit" "0: Data frame,1: Remote frame" newline hexmask.long 0x0 0.--28. 1. "RMID,RX Message Buffer ID Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x924)++0x3 line.long 0x0 "CFDRMPTR$1,RX Message Buffer Pointer Registers" hexmask.long.byte 0x0 28.--31. 1. "RMDLC,RX Message Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RMTS,RX Message Buffer Timestamp Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x928)++0x3 line.long 0x0 "CFDRMFDSTS$1,RX Message Buffer CANFD Status Registers" hexmask.long.word 0x0 16.--31. 1. "RMPTR,RX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "RMIFL,RX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RMFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RMBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RMESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x92C)++0x3 line.long 0x0 "CFDRMDF$1_0,RX Message Buffer Data Field 0 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x930)++0x3 line.long 0x0 "CFDRMDF$1_1,RX Message Buffer Data Field 1 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x934)++0x3 line.long 0x0 "CFDRMDF$1_2,RX Message Buffer Data Field 2 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x938)++0x3 line.long 0x0 "CFDRMDF$1_3,RX Message Buffer Data Field 3 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x93C)++0x3 line.long 0x0 "CFDRMDF$1_4,RX Message Buffer Data Field 4 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x940)++0x3 line.long 0x0 "CFDRMDF$1_5,RX Message Buffer Data Field 5 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x944)++0x3 line.long 0x0 "CFDRMDF$1_6,RX Message Buffer Data Field 6 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x948)++0x3 line.long 0x0 "CFDRMDF$1_7,RX Message Buffer Data Field 7 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x94C)++0x3 line.long 0x0 "CFDRMDF$1_8,RX Message Buffer Data Field 8 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x950)++0x3 line.long 0x0 "CFDRMDF$1_9,RX Message Buffer Data Field 9 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x954)++0x3 line.long 0x0 "CFDRMDF$1_10,RX Message Buffer Data Field 10 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x958)++0x3 line.long 0x0 "CFDRMDF$1_11,RX Message Buffer Data Field 11 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x95C)++0x3 line.long 0x0 "CFDRMDF$1_12,RX Message Buffer Data Field 12 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x960)++0x3 line.long 0x0 "CFDRMDF$1_13,RX Message Buffer Data Field 13 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x964)++0x3 line.long 0x0 "CFDRMDF$1_14,RX Message Buffer Data Field 14 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x968)++0x3 line.long 0x0 "CFDRMDF$1_15,RX Message Buffer Data Field 15 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD20)++0x3 line.long 0x0 "CFDRMID$1,RX Message Buffer ID Registers" bitfld.long 0x0 31. "RMIDE,RX Message Buffer IDE Bit" "0: STD-ID is stored,1: EXT-ID is stored" bitfld.long 0x0 30. "RMRTR,RX Message Buffer RTR Bit" "0: Data frame,1: Remote frame" newline hexmask.long 0x0 0.--28. 1. "RMID,RX Message Buffer ID Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD24)++0x3 line.long 0x0 "CFDRMPTR$1,RX Message Buffer Pointer Registers" hexmask.long.byte 0x0 28.--31. 1. "RMDLC,RX Message Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RMTS,RX Message Buffer Timestamp Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD28)++0x3 line.long 0x0 "CFDRMFDSTS$1,RX Message Buffer CANFD Status Registers" hexmask.long.word 0x0 16.--31. 1. "RMPTR,RX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "RMIFL,RX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RMFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RMBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RMESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD2C)++0x3 line.long 0x0 "CFDRMDF$1_0,RX Message Buffer Data Field 0 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD30)++0x3 line.long 0x0 "CFDRMDF$1_1,RX Message Buffer Data Field 1 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD34)++0x3 line.long 0x0 "CFDRMDF$1_2,RX Message Buffer Data Field 2 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD38)++0x3 line.long 0x0 "CFDRMDF$1_3,RX Message Buffer Data Field 3 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD3C)++0x3 line.long 0x0 "CFDRMDF$1_4,RX Message Buffer Data Field 4 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD40)++0x3 line.long 0x0 "CFDRMDF$1_5,RX Message Buffer Data Field 5 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD44)++0x3 line.long 0x0 "CFDRMDF$1_6,RX Message Buffer Data Field 6 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD48)++0x3 line.long 0x0 "CFDRMDF$1_7,RX Message Buffer Data Field 7 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD4C)++0x3 line.long 0x0 "CFDRMDF$1_8,RX Message Buffer Data Field 8 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD50)++0x3 line.long 0x0 "CFDRMDF$1_9,RX Message Buffer Data Field 9 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD54)++0x3 line.long 0x0 "CFDRMDF$1_10,RX Message Buffer Data Field 10 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD58)++0x3 line.long 0x0 "CFDRMDF$1_11,RX Message Buffer Data Field 11 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD5C)++0x3 line.long 0x0 "CFDRMDF$1_12,RX Message Buffer Data Field 12 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD60)++0x3 line.long 0x0 "CFDRMDF$1_13,RX Message Buffer Data Field 13 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD64)++0x3 line.long 0x0 "CFDRMDF$1_14,RX Message Buffer Data Field 14 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0xD68)++0x3 line.long 0x0 "CFDRMDF$1_15,RX Message Buffer Data Field 15 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1124)++0x3 line.long 0x0 "CFDRMPTR$1,RX Message Buffer Pointer Registers" hexmask.long.byte 0x0 28.--31. 1. "RMDLC,RX Message Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RMTS,RX Message Buffer Timestamp Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1128)++0x3 line.long 0x0 "CFDRMFDSTS$1,RX Message Buffer CANFD Status Registers" hexmask.long.word 0x0 16.--31. 1. "RMPTR,RX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "RMIFL,RX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RMFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RMBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RMESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x112C)++0x3 line.long 0x0 "CFDRMDF$1_0,RX Message Buffer Data Field 0 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1130)++0x3 line.long 0x0 "CFDRMDF$1_1,RX Message Buffer Data Field 1 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1134)++0x3 line.long 0x0 "CFDRMDF$1_2,RX Message Buffer Data Field 2 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1138)++0x3 line.long 0x0 "CFDRMDF$1_3,RX Message Buffer Data Field 3 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x113C)++0x3 line.long 0x0 "CFDRMDF$1_4,RX Message Buffer Data Field 4 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1140)++0x3 line.long 0x0 "CFDRMDF$1_5,RX Message Buffer Data Field 5 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1144)++0x3 line.long 0x0 "CFDRMDF$1_6,RX Message Buffer Data Field 6 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1148)++0x3 line.long 0x0 "CFDRMDF$1_7,RX Message Buffer Data Field 7 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x114C)++0x3 line.long 0x0 "CFDRMDF$1_8,RX Message Buffer Data Field 8 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1150)++0x3 line.long 0x0 "CFDRMDF$1_9,RX Message Buffer Data Field 9 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1154)++0x3 line.long 0x0 "CFDRMDF$1_10,RX Message Buffer Data Field 10 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1158)++0x3 line.long 0x0 "CFDRMDF$1_11,RX Message Buffer Data Field 11 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x115C)++0x3 line.long 0x0 "CFDRMDF$1_12,RX Message Buffer Data Field 12 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1160)++0x3 line.long 0x0 "CFDRMDF$1_13,RX Message Buffer Data Field 13 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1164)++0x3 line.long 0x0 "CFDRMDF$1_14,RX Message Buffer Data Field 14 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1168)++0x3 line.long 0x0 "CFDRMDF$1_15,RX Message Buffer Data Field 15 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1524)++0x3 line.long 0x0 "CFDRMPTR$1,RX Message Buffer Pointer Registers" hexmask.long.byte 0x0 28.--31. 1. "RMDLC,RX Message Buffer DLC Field" hexmask.long.word 0x0 0.--15. 1. "RMTS,RX Message Buffer Timestamp Field" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1528)++0x3 line.long 0x0 "CFDRMFDSTS$1,RX Message Buffer CANFD Status Registers" hexmask.long.word 0x0 16.--31. 1. "RMPTR,RX Message Buffer Pointer Field" bitfld.long 0x0 8.--9. "RMIFL,RX Message Buffer Information Label Field" "0,1,2,3" newline bitfld.long 0x0 2. "RMFDF,CAN FD Format bit" "0: Non CANFD frame received,1: CANFD frame received" bitfld.long 0x0 1. "RMBRS,Bit Rate Switch bit" "0: CANFD frame received with no bit rate switch,1: CANFD frame received with bit rate switch" newline bitfld.long 0x0 0. "RMESI,Error State Indicator bit" "0: CANFD frame received from error active node,1: CANFD frame received from error passive node" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x152C)++0x3 line.long 0x0 "CFDRMDF$1_0,RX Message Buffer Data Field 0 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1530)++0x3 line.long 0x0 "CFDRMDF$1_1,RX Message Buffer Data Field 1 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1534)++0x3 line.long 0x0 "CFDRMDF$1_2,RX Message Buffer Data Field 2 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1538)++0x3 line.long 0x0 "CFDRMDF$1_3,RX Message Buffer Data Field 3 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x153C)++0x3 line.long 0x0 "CFDRMDF$1_4,RX Message Buffer Data Field 4 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1540)++0x3 line.long 0x0 "CFDRMDF$1_5,RX Message Buffer Data Field 5 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1544)++0x3 line.long 0x0 "CFDRMDF$1_6,RX Message Buffer Data Field 6 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1548)++0x3 line.long 0x0 "CFDRMDF$1_7,RX Message Buffer Data Field 7 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x154C)++0x3 line.long 0x0 "CFDRMDF$1_8,RX Message Buffer Data Field 8 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1550)++0x3 line.long 0x0 "CFDRMDF$1_9,RX Message Buffer Data Field 9 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1554)++0x3 line.long 0x0 "CFDRMDF$1_10,RX Message Buffer Data Field 10 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1558)++0x3 line.long 0x0 "CFDRMDF$1_11,RX Message Buffer Data Field 11 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x155C)++0x3 line.long 0x0 "CFDRMDF$1_12,RX Message Buffer Data Field 12 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1560)++0x3 line.long 0x0 "CFDRMDF$1_13,RX Message Buffer Data Field 13 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1564)++0x3 line.long 0x0 "CFDRMDF$1_14,RX Message Buffer Data Field 14 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4C) rgroup.long ($2+0x1568)++0x3 line.long 0x0 "CFDRMDF$1_15,RX Message Buffer Data Field 15 Registers" hexmask.long.byte 0x0 24.--31. 1. "RMDB_HH,RX Message Buffer Data Byte ((p × 4) + 3)" hexmask.long.byte 0x0 16.--23. 1. "RMDB_HL,RX Message Buffer Data Byte ((p × 4) + 2)" newline hexmask.long.byte 0x0 8.--15. 1. "RMDB_LH,RX Message Buffer Data Byte ((p × 4) + 1)" hexmask.long.byte 0x0 0.--7. 1. "RMDB_LL,RX Message Buffer Data Byte (p × 4)" repeat.end tree.end tree.end tree "CNECC (CANFD ECC)" base ad:0x0 tree "ECCMB0" base ad:0x4036F200 group.long 0x0++0x3 line.long 0x0 "EC710CTL,ECC Control Register" rbitfld.long 0x0 17. "ECDEDF0,ECC Dual Bit Error Address Detection Flag" "0: There is no bit error in EC710EAD0 after reset..,1: Address captured in EC710EAD0 shows that 2-bit.." rbitfld.long 0x0 16. "ECSEDF0,ECC Single bit Error Address Detection Flag" "0: There is no bit error in EC710EAD0 after reset..,1: Address captured in EC710EAD0 shows that 1-bit.." newline bitfld.long 0x0 14.--15. "EMCA,Access Control to ECC Mode Select bit" "0,1,2,3" rbitfld.long 0x0 11. "ECOVFF,ECC Overflow Detection Flag" "0: No effect,1: ECC overflow detection flag" newline bitfld.long 0x0 10. "ECER2C,2-bit ECC Error Detection Flag Clear" "0: No effect,1: Clear 2-bit ECC error detection flag" bitfld.long 0x0 9. "ECER1C,Accumulating ECC Error Detection and Correction Flag Clear" "0: No effect,1: Clear accumulating ECC error detection and.." newline bitfld.long 0x0 6. "ECERVF,ECC Error Judgment Enable Flag" "0: Error judgment disable,1: Error judgment enable" bitfld.long 0x0 5. "EC1ECP,ECC 1-bit Error Correction Permission" "0: At 1-bit error detection the error correction is..,1: At 1-bit error detection the error correction is.." newline bitfld.long 0x0 4. "EC2EDIC,ECC 2-bit Error Detection Interrupt Control" "0: Disable 2-bit error detection interrupt request,1: Enable 2-bit error detection interrupt request" bitfld.long 0x0 3. "EC1EDIC,ECC 1-bit Error Detection Interrupt Control" "0: Disable 1-bit error detection interrupt request,1: Enable 1-bit error detection interrupt request" newline rbitfld.long 0x0 2. "ECER2F,2-bit ECC Error Detection Flag" "0: After clearing this bit 2-bit error has not..,1: 2-bit error has occurred" rbitfld.long 0x0 1. "ECER1F,ECC Error Detection and Correction Flag" "0: After clearing this bit 1-bit error correction..,1: 1-bit error has occurred" newline rbitfld.long 0x0 0. "ECEMF,ECC Error Message Flag" "0: There is no bit error in present RAM output data,1: There is bit error in present RAM output data" group.word 0x4++0x1 line.word 0x0 "EC710TMC,ECC Test Mode Control Register" bitfld.word 0x0 14.--15. "ETMA,ECC Test Mode Bit Access Control" "0,1,2,3" bitfld.word 0x0 7. "ECTMCE,ECC Test Mode Control Enable" "0: The access to test mode register and bit is..,1: The access to test mode register and bit is.." newline bitfld.word 0x0 1. "ECDCS,ECC Decode Input Select" "0: Input lower 32 bits of RAM output data to data..,1: Input ECEDB31-0 in EC710TED register to data.." group.long 0xC++0x3 line.long 0x0 "EC710TED,ECC Test Substitute Data Register" hexmask.long 0x0 0.--31. 1. "ECEDB,ECC Test Substitute Data" rgroup.long 0x10++0x3 line.long 0x0 "EC710EAD0,ECC Error Address Register" hexmask.long.word 0x0 0.--9. 1. "ECEAD,ECC Error Address" tree.end tree "ECCMB0_NS" base ad:0x5036F200 group.long 0x0++0x3 line.long 0x0 "EC710CTL,ECC Control Register" rbitfld.long 0x0 17. "ECDEDF0,ECC Dual Bit Error Address Detection Flag" "0: There is no bit error in EC710EAD0 after reset..,1: Address captured in EC710EAD0 shows that 2-bit.." rbitfld.long 0x0 16. "ECSEDF0,ECC Single bit Error Address Detection Flag" "0: There is no bit error in EC710EAD0 after reset..,1: Address captured in EC710EAD0 shows that 1-bit.." newline bitfld.long 0x0 14.--15. "EMCA,Access Control to ECC Mode Select bit" "0,1,2,3" rbitfld.long 0x0 11. "ECOVFF,ECC Overflow Detection Flag" "0: No effect,1: ECC overflow detection flag" newline bitfld.long 0x0 10. "ECER2C,2-bit ECC Error Detection Flag Clear" "0: No effect,1: Clear 2-bit ECC error detection flag" bitfld.long 0x0 9. "ECER1C,Accumulating ECC Error Detection and Correction Flag Clear" "0: No effect,1: Clear accumulating ECC error detection and.." newline bitfld.long 0x0 6. "ECERVF,ECC Error Judgment Enable Flag" "0: Error judgment disable,1: Error judgment enable" bitfld.long 0x0 5. "EC1ECP,ECC 1-bit Error Correction Permission" "0: At 1-bit error detection the error correction is..,1: At 1-bit error detection the error correction is.." newline bitfld.long 0x0 4. "EC2EDIC,ECC 2-bit Error Detection Interrupt Control" "0: Disable 2-bit error detection interrupt request,1: Enable 2-bit error detection interrupt request" bitfld.long 0x0 3. "EC1EDIC,ECC 1-bit Error Detection Interrupt Control" "0: Disable 1-bit error detection interrupt request,1: Enable 1-bit error detection interrupt request" newline rbitfld.long 0x0 2. "ECER2F,2-bit ECC Error Detection Flag" "0: After clearing this bit 2-bit error has not..,1: 2-bit error has occurred" rbitfld.long 0x0 1. "ECER1F,ECC Error Detection and Correction Flag" "0: After clearing this bit 1-bit error correction..,1: 1-bit error has occurred" newline rbitfld.long 0x0 0. "ECEMF,ECC Error Message Flag" "0: There is no bit error in present RAM output data,1: There is bit error in present RAM output data" group.word 0x4++0x1 line.word 0x0 "EC710TMC,ECC Test Mode Control Register" bitfld.word 0x0 14.--15. "ETMA,ECC Test Mode Bit Access Control" "0,1,2,3" bitfld.word 0x0 7. "ECTMCE,ECC Test Mode Control Enable" "0: The access to test mode register and bit is..,1: The access to test mode register and bit is.." newline bitfld.word 0x0 1. "ECDCS,ECC Decode Input Select" "0: Input lower 32 bits of RAM output data to data..,1: Input ECEDB31-0 in EC710TED register to data.." group.long 0xC++0x3 line.long 0x0 "EC710TED,ECC Test Substitute Data Register" hexmask.long 0x0 0.--31. 1. "ECEDB,ECC Test Substitute Data" rgroup.long 0x10++0x3 line.long 0x0 "EC710EAD0,ECC Error Address Register" hexmask.long.word 0x0 0.--9. 1. "ECEAD,ECC Error Address" tree.end tree "ECCMB1" base ad:0x4036F300 group.long 0x0++0x3 line.long 0x0 "EC710CTL,ECC Control Register" rbitfld.long 0x0 17. "ECDEDF0,ECC Dual Bit Error Address Detection Flag" "0: There is no bit error in EC710EAD0 after reset..,1: Address captured in EC710EAD0 shows that 2-bit.." rbitfld.long 0x0 16. "ECSEDF0,ECC Single bit Error Address Detection Flag" "0: There is no bit error in EC710EAD0 after reset..,1: Address captured in EC710EAD0 shows that 1-bit.." newline bitfld.long 0x0 14.--15. "EMCA,Access Control to ECC Mode Select bit" "0,1,2,3" rbitfld.long 0x0 11. "ECOVFF,ECC Overflow Detection Flag" "0: No effect,1: ECC overflow detection flag" newline bitfld.long 0x0 10. "ECER2C,2-bit ECC Error Detection Flag Clear" "0: No effect,1: Clear 2-bit ECC error detection flag" bitfld.long 0x0 9. "ECER1C,Accumulating ECC Error Detection and Correction Flag Clear" "0: No effect,1: Clear accumulating ECC error detection and.." newline bitfld.long 0x0 6. "ECERVF,ECC Error Judgment Enable Flag" "0: Error judgment disable,1: Error judgment enable" bitfld.long 0x0 5. "EC1ECP,ECC 1-bit Error Correction Permission" "0: At 1-bit error detection the error correction is..,1: At 1-bit error detection the error correction is.." newline bitfld.long 0x0 4. "EC2EDIC,ECC 2-bit Error Detection Interrupt Control" "0: Disable 2-bit error detection interrupt request,1: Enable 2-bit error detection interrupt request" bitfld.long 0x0 3. "EC1EDIC,ECC 1-bit Error Detection Interrupt Control" "0: Disable 1-bit error detection interrupt request,1: Enable 1-bit error detection interrupt request" newline rbitfld.long 0x0 2. "ECER2F,2-bit ECC Error Detection Flag" "0: After clearing this bit 2-bit error has not..,1: 2-bit error has occurred" rbitfld.long 0x0 1. "ECER1F,ECC Error Detection and Correction Flag" "0: After clearing this bit 1-bit error correction..,1: 1-bit error has occurred" newline rbitfld.long 0x0 0. "ECEMF,ECC Error Message Flag" "0: There is no bit error in present RAM output data,1: There is bit error in present RAM output data" group.word 0x4++0x1 line.word 0x0 "EC710TMC,ECC Test Mode Control Register" bitfld.word 0x0 14.--15. "ETMA,ECC Test Mode Bit Access Control" "0,1,2,3" bitfld.word 0x0 7. "ECTMCE,ECC Test Mode Control Enable" "0: The access to test mode register and bit is..,1: The access to test mode register and bit is.." newline bitfld.word 0x0 1. "ECDCS,ECC Decode Input Select" "0: Input lower 32 bits of RAM output data to data..,1: Input ECEDB31-0 in EC710TED register to data.." group.long 0xC++0x3 line.long 0x0 "EC710TED,ECC Test Substitute Data Register" hexmask.long 0x0 0.--31. 1. "ECEDB,ECC Test Substitute Data" rgroup.long 0x10++0x3 line.long 0x0 "EC710EAD0,ECC Error Address Register" hexmask.long.word 0x0 0.--9. 1. "ECEAD,ECC Error Address" tree.end tree "ECCMB1_NS" base ad:0x5036F300 group.long 0x0++0x3 line.long 0x0 "EC710CTL,ECC Control Register" rbitfld.long 0x0 17. "ECDEDF0,ECC Dual Bit Error Address Detection Flag" "0: There is no bit error in EC710EAD0 after reset..,1: Address captured in EC710EAD0 shows that 2-bit.." rbitfld.long 0x0 16. "ECSEDF0,ECC Single bit Error Address Detection Flag" "0: There is no bit error in EC710EAD0 after reset..,1: Address captured in EC710EAD0 shows that 1-bit.." newline bitfld.long 0x0 14.--15. "EMCA,Access Control to ECC Mode Select bit" "0,1,2,3" rbitfld.long 0x0 11. "ECOVFF,ECC Overflow Detection Flag" "0: No effect,1: ECC overflow detection flag" newline bitfld.long 0x0 10. "ECER2C,2-bit ECC Error Detection Flag Clear" "0: No effect,1: Clear 2-bit ECC error detection flag" bitfld.long 0x0 9. "ECER1C,Accumulating ECC Error Detection and Correction Flag Clear" "0: No effect,1: Clear accumulating ECC error detection and.." newline bitfld.long 0x0 6. "ECERVF,ECC Error Judgment Enable Flag" "0: Error judgment disable,1: Error judgment enable" bitfld.long 0x0 5. "EC1ECP,ECC 1-bit Error Correction Permission" "0: At 1-bit error detection the error correction is..,1: At 1-bit error detection the error correction is.." newline bitfld.long 0x0 4. "EC2EDIC,ECC 2-bit Error Detection Interrupt Control" "0: Disable 2-bit error detection interrupt request,1: Enable 2-bit error detection interrupt request" bitfld.long 0x0 3. "EC1EDIC,ECC 1-bit Error Detection Interrupt Control" "0: Disable 1-bit error detection interrupt request,1: Enable 1-bit error detection interrupt request" newline rbitfld.long 0x0 2. "ECER2F,2-bit ECC Error Detection Flag" "0: After clearing this bit 2-bit error has not..,1: 2-bit error has occurred" rbitfld.long 0x0 1. "ECER1F,ECC Error Detection and Correction Flag" "0: After clearing this bit 1-bit error correction..,1: 1-bit error has occurred" newline rbitfld.long 0x0 0. "ECEMF,ECC Error Message Flag" "0: There is no bit error in present RAM output data,1: There is bit error in present RAM output data" group.word 0x4++0x1 line.word 0x0 "EC710TMC,ECC Test Mode Control Register" bitfld.word 0x0 14.--15. "ETMA,ECC Test Mode Bit Access Control" "0,1,2,3" bitfld.word 0x0 7. "ECTMCE,ECC Test Mode Control Enable" "0: The access to test mode register and bit is..,1: The access to test mode register and bit is.." newline bitfld.word 0x0 1. "ECDCS,ECC Decode Input Select" "0: Input lower 32 bits of RAM output data to data..,1: Input ECEDB31-0 in EC710TED register to data.." group.long 0xC++0x3 line.long 0x0 "EC710TED,ECC Test Substitute Data Register" hexmask.long 0x0 0.--31. 1. "ECEDB,ECC Test Substitute Data" rgroup.long 0x10++0x3 line.long 0x0 "EC710EAD0,ECC Error Address Register" hexmask.long.word 0x0 0.--9. 1. "ECEAD,ECC Error Address" tree.end tree.end tree "CPSCU (CPU System Security Control Unit)" base ad:0x0 tree "CPSCU" base ad:0x40008000 group.long 0x10++0x3 line.long 0x0 "SRAMSAR,SRAM Security Attribution Register" bitfld.long 0x0 8. "SRAMWTSA,SRAMWTSC Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 7. "STBRAMSA,Standby SRAM Register Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 1. "SRAMSA1,SRAM1 Register Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 0. "SRAMSA0,SRAM0 Register Security Attribution" "0: Secure,1: Non-secure" group.long 0x30++0x7 line.long 0x0 "DTCSAR,DTC Controller Security Attribution Register" bitfld.long 0x0 0. "DTCSTSA,DTC Security Attribution" "0: Secure.,1: Non-secure." line.long 0x4 "DMACSAR,DMAC Controller Security Attribution Register" bitfld.long 0x4 0. "DMASTSA,DMAST Security Attribution" "0: Secure,1: Non-secure" group.long 0x40++0x7 line.long 0x0 "ICUSARA,Interrupt Controller Unit Security Attribution Register A" bitfld.long 0x0 15. "SAIRQCR15,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 14. "SAIRQCR14,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 13. "SAIRQCR13,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 12. "SAIRQCR12,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" newline bitfld.long 0x0 11. "SAIRQCR11,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 10. "SAIRQCR10,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 9. "SAIRQCR09,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 8. "SAIRQCR08,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" newline bitfld.long 0x0 7. "SAIRQCR07,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 6. "SAIRQCR06,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 5. "SAIRQCR05,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 4. "SAIRQCR04,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" newline bitfld.long 0x0 3. "SAIRQCR03,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 2. "SAIRQCR02,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 1. "SAIRQCR01,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 0. "SAIRQCR00,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" line.long 0x4 "ICUSARB,Interrupt Controller Unit Security Attribution Register B" bitfld.long 0x4 0. "SANMI,Security attributes of registers for nonmaskable interrupt" "0: Secure,1: Non-secure" group.long 0x50++0x7 line.long 0x0 "ICUSARE,Interrupt Controller Unit Security Attribution Register E" bitfld.long 0x0 31. "SAIIC0WUP,Security attributes of registers for WUPEN0.b31" "0: Secure,1: Non-secure" bitfld.long 0x0 30. "SAAGT1CBWUP,Security attributes of registers for WUPEN0.b30" "0: Secure,1: Non-secure" bitfld.long 0x0 29. "SAAGT1CAWUP,Security attributes of registers for WUPEN0.b29" "0: Secure,1: Non-secure" bitfld.long 0x0 28. "SAAGT1UDWUP,Security attributes of registers for WUPEN0.b28" "0: Secure,1: Non-secure" newline bitfld.long 0x0 27. "SAUSBFS0WUP,Security attributes of registers for WUPEN0.b27" "0: Secure,1: Non-secure" bitfld.long 0x0 25. "SARTCPRDWUP,Security attributes of registers for WUPEN0.b25" "0: Secure,1: Non-secure" bitfld.long 0x0 24. "SARTCALMWUP,Security attributes of registers for WUPEN0.b24" "0: Secure,1: Non-secure" bitfld.long 0x0 20. "SAVBATTWUP,Security attributes of registers for WUPEN0.b20" "0: Secure,1: Non-secure" newline bitfld.long 0x0 19. "SAPVD2WUP,Security attributes of registers for WUPEN0.b19" "0: Secure,1: Non-secure" bitfld.long 0x0 18. "SAPVD1WUP,Security attributes of registers for WUPEN0.b18" "0: Secure,1: Non-secure" bitfld.long 0x0 16. "SAIWDTWUP,Security attributes of registers for WUPEN0.b16" "0: Secure,1: Non-secure" line.long 0x4 "ICUSARF,Interrupt Controller Unit Security Attribution Register F" bitfld.long 0x4 14. "SAULP1BWUP,Security attributes of registers for WUPEN1.b14" "0: Secure,1: Non-secure" bitfld.long 0x4 13. "SAULP1AWUP,Security attributes of registers for WUPEN1.b13" "0: Secure,1: Non-secure" bitfld.long 0x4 12. "SAULP1UWUP,Security attributes of registers for WUPEN1.b12" "0: Secure,1: Non-secure" bitfld.long 0x4 10. "SAULP0BWUP,Security attributes of registers for WUPEN1.b10" "0: Secure,1: Non-secure" newline bitfld.long 0x4 9. "SAULP0AWUP,Security attributes of registers for WUPEN1.b9" "0: Secure,1: Non-secure" bitfld.long 0x4 8. "SAULP0UWUP,Security attributes of registers for WUPEN1.b8" "0: Secure,1: Non-secure" bitfld.long 0x4 3. "SACOMPHS0WUP,Security attributes of registers for WUPEN1.b3" "0: Secure,1: Non-secure" group.long 0x70++0xB line.long 0x0 "ICUSARG,Interrupt Controller Unit Security Attribution Register G" bitfld.long 0x0 31. "SAIELSR31,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 30. "SAIELSR30,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 29. "SAIELSR29,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 28. "SAIELSR28,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" newline bitfld.long 0x0 27. "SAIELSR27,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 26. "SAIELSR26,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 25. "SAIELSR25,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 24. "SAIELSR24,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" newline bitfld.long 0x0 23. "SAIELSR23,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 22. "SAIELSR22,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 21. "SAIELSR21,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 20. "SAIELSR20,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" newline bitfld.long 0x0 19. "SAIELSR19,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 18. "SAIELSR18,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 17. "SAIELSR17,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 16. "SAIELSR16,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" newline bitfld.long 0x0 15. "SAIELSR15,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 14. "SAIELSR14,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 13. "SAIELSR13,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 12. "SAIELSR12,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" newline bitfld.long 0x0 11. "SAIELSR11,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 10. "SAIELSR10,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 9. "SAIELSR09,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 8. "SAIELSR08,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" newline bitfld.long 0x0 7. "SAIELSR07,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 6. "SAIELSR06,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 5. "SAIELSR05,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 4. "SAIELSR04,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" newline bitfld.long 0x0 3. "SAIELSR03,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 2. "SAIELSR02,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 1. "SAIELSR01,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 0. "SAIELSR00,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" line.long 0x4 "ICUSARH,Interrupt Controller Unit Security Attribution Register H" bitfld.long 0x4 31. "SAIELSR63,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 30. "SAIELSR62,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 29. "SAIELSR61,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 28. "SAIELSR60,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" newline bitfld.long 0x4 27. "SAIELSR59,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 26. "SAIELSR58,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 25. "SAIELSR57,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 24. "SAIELSR56,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" newline bitfld.long 0x4 23. "SAIELSR55,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 22. "SAIELSR54,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 21. "SAIELSR53,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 20. "SAIELSR52,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" newline bitfld.long 0x4 19. "SAIELSR51,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 18. "SAIELSR50,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 17. "SAIELSR49,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 16. "SAIELSR48,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" newline bitfld.long 0x4 15. "SAIELSR47,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 14. "SAIELSR46,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 13. "SAIELSR45,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 12. "SAIELSR44,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" newline bitfld.long 0x4 11. "SAIELSR43,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 10. "SAIELSR42,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 9. "SAIELSR41,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 8. "SAIELSR40,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" newline bitfld.long 0x4 7. "SAIELSR39,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 6. "SAIELSR38,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 5. "SAIELSR37,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 4. "SAIELSR36,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" newline bitfld.long 0x4 3. "SAIELSR35,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 2. "SAIELSR34,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 1. "SAIELSR33,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 0. "SAIELSR32,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" line.long 0x8 "ICUSARI,Interrupt Controller Unit Security Attribution Register I" bitfld.long 0x8 31. "SAIELSR95,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 30. "SAIELSR94,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 29. "SAIELSR93,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 28. "SAIELSR92,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" newline bitfld.long 0x8 27. "SAIELSR91,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 26. "SAIELSR90,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 25. "SAIELSR89,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 24. "SAIELSR88,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" newline bitfld.long 0x8 23. "SAIELSR87,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 22. "SAIELSR86,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 21. "SAIELSR85,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 20. "SAIELSR84,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" newline bitfld.long 0x8 19. "SAIELSR83,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 18. "SAIELSR82,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 17. "SAIELSR81,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 16. "SAIELSR80,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" newline bitfld.long 0x8 15. "SAIELSR79,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 14. "SAIELSR78,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 13. "SAIELSR77,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 12. "SAIELSR76,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" newline bitfld.long 0x8 11. "SAIELSR75,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 10. "SAIELSR74,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 9. "SAIELSR73,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 8. "SAIELSR72,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" newline bitfld.long 0x8 7. "SAIELSR71,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 6. "SAIELSR70,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 5. "SAIELSR69,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 4. "SAIELSR68,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" newline bitfld.long 0x8 3. "SAIELSR67,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 2. "SAIELSR66,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 1. "SAIELSR65,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 0. "SAIELSR64,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" group.long 0x100++0x7 line.long 0x0 "BUSSARA,Bus Security Attribution Register A" bitfld.long 0x0 0. "BUSSA0,Bus Security Attribution A0" "0: Secure,1: Non-secure" line.long 0x4 "BUSSARB,Bus Security Attribution Register B" bitfld.long 0x4 0. "BUSSB0,Bus Security Attribution B0" "0: Secure,1: Non-secure" group.long 0x110++0x7 line.long 0x0 "BUSSARC,Bus Security Attribution Register C" bitfld.long 0x0 0. "BUSSC0,Bus Security Attribution C0" "0: Secure,1: Non-secure" line.long 0x4 "BUSPARC,Bus Privileged Attribution Register C" bitfld.long 0x4 0. "BUSPA0,External bus controller privilege attribution" "0: Privileged,1: Unprivileged" group.long 0x130++0x7 line.long 0x0 "MMPUSARA,Master Memory Protection Unit Security Attribution Register A" hexmask.long.byte 0x0 0.--7. 1. "MMPUASAn,MMPUA Security Attribution n (n = 0 to 7)" line.long 0x4 "MMPUSARB,Master Memory Protection Unit Security Attribution Register B" bitfld.long 0x4 8. "MMPUBSA8,MMPUB Security Attribution 8" "0: Secure,1: Non-secure" bitfld.long 0x4 0. "MMPUBSA0,MMPUB Security Attribution 0" "0: Secure,1: Non-secure" group.long 0x170++0x3 line.long 0x0 "CPUSAR,CPU Security Attribution Register" bitfld.long 0x0 0. "CPUSA0,CPU Control Registers Security Attribution" "0: Secure,1: Non-secure" group.long 0x180++0x3 line.long 0x0 "DEBUGSAR,Debug Security Attribution Register" bitfld.long 0x0 0. "DBGSA0,Debug Resources Security Attribution 0" "0: Secure,1: Non-secure" group.long 0x1A0++0x3 line.long 0x0 "DMACCHSAR,DMA channel Security Attribution Register" bitfld.long 0x0 7. "SADMAC7,Security attributes of output and registers for DMAC channel" "0: Secure,1: Non-secure" bitfld.long 0x0 6. "SADMAC6,Security attributes of output and registers for DMAC channel" "0: Secure,1: Non-secure" bitfld.long 0x0 5. "SADMAC5,Security attributes of output and registers for DMAC channel" "0: Secure,1: Non-secure" bitfld.long 0x0 4. "SADMAC4,Security attributes of output and registers for DMAC channel" "0: Secure,1: Non-secure" newline bitfld.long 0x0 3. "SADMAC3,Security attributes of output and registers for DMAC channel" "0: Secure,1: Non-secure" bitfld.long 0x0 2. "SADMAC2,Security attributes of output and registers for DMAC channel" "0: Secure,1: Non-secure" bitfld.long 0x0 1. "SADMAC1,Security attributes of output and registers for DMAC channel" "0: Secure,1: Non-secure" bitfld.long 0x0 0. "SADMAC0,Security attributes of output and registers for DMAC channel" "0: Secure,1: Non-secure" group.long 0x1F0++0x3 line.long 0x0 "DMACCHPAR,DMA channel Privilege Attribution Register" bitfld.long 0x0 7. "PADMAC7,Privilege attributes of outputs and registers for DMAC channel" "0: Privileged.,1: Unprivileged." bitfld.long 0x0 6. "PADMAC6,Privilege attributes of outputs and registers for DMAC channel" "0: Privileged.,1: Unprivileged." bitfld.long 0x0 5. "PADMAC5,Privilege attributes of outputs and registers for DMAC channel" "0: Privileged.,1: Unprivileged." bitfld.long 0x0 4. "PADMAC4,Privilege attributes of outputs and registers for DMAC channel" "0: Privileged.,1: Unprivileged." newline bitfld.long 0x0 3. "PADMAC3,Privilege attributes of outputs and registers for DMAC channel" "0: Privileged.,1: Unprivileged." bitfld.long 0x0 2. "PADMAC2,Privilege attributes of outputs and registers for DMAC channel" "0: Privileged.,1: Unprivileged." bitfld.long 0x0 1. "PADMAC1,Privilege attributes of outputs and registers for DMAC channel" "0: Privileged.,1: Unprivileged." bitfld.long 0x0 0. "PADMAC0,Privilege attributes of outputs and registers for DMAC channel" "0: Privileged.,1: Unprivileged." repeat 3. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x400)++0x3 line.long 0x0 "SRAMSABAR$1,SRAM Error Address Register" repeat.end group.long 0x420++0x3 line.long 0x0 "STBRAMSABAR,Standby SRAM Security Attribute Boundary Address Register" group.long 0x494++0x3 line.long 0x0 "STBRAMPABAR_S,Standby SRAM Privilege Attribute Boundary Address Register for Secure" group.long 0x600++0x3 line.long 0x0 "TEVTRCR,Trusted Event Route Control Register" bitfld.long 0x0 0. "TEVTE,Trusted Event Route Control Register for IELSRn DELSRn and ELCSRn" "0: Disable,1: Enable" tree.end tree "CPSCU_NS" base ad:0x50008000 group.long 0x10++0x3 line.long 0x0 "SRAMSAR,SRAM Security Attribution Register" bitfld.long 0x0 8. "SRAMWTSA,SRAMWTSC Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 7. "STBRAMSA,Standby SRAM Register Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 1. "SRAMSA1,SRAM1 Register Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 0. "SRAMSA0,SRAM0 Register Security Attribution" "0: Secure,1: Non-secure" group.long 0x30++0x7 line.long 0x0 "DTCSAR,DTC Controller Security Attribution Register" bitfld.long 0x0 0. "DTCSTSA,DTC Security Attribution" "0: Secure.,1: Non-secure." line.long 0x4 "DMACSAR,DMAC Controller Security Attribution Register" bitfld.long 0x4 0. "DMASTSA,DMAST Security Attribution" "0: Secure,1: Non-secure" group.long 0x40++0x7 line.long 0x0 "ICUSARA,Interrupt Controller Unit Security Attribution Register A" bitfld.long 0x0 15. "SAIRQCR15,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 14. "SAIRQCR14,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 13. "SAIRQCR13,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 12. "SAIRQCR12,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" newline bitfld.long 0x0 11. "SAIRQCR11,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 10. "SAIRQCR10,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 9. "SAIRQCR09,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 8. "SAIRQCR08,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" newline bitfld.long 0x0 7. "SAIRQCR07,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 6. "SAIRQCR06,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 5. "SAIRQCR05,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 4. "SAIRQCR04,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" newline bitfld.long 0x0 3. "SAIRQCR03,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 2. "SAIRQCR02,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 1. "SAIRQCR01,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" bitfld.long 0x0 0. "SAIRQCR00,Security attributes of registers for the IRQCRn register" "0: Secure,1: Non-secure" line.long 0x4 "ICUSARB,Interrupt Controller Unit Security Attribution Register B" bitfld.long 0x4 0. "SANMI,Security attributes of registers for nonmaskable interrupt" "0: Secure,1: Non-secure" group.long 0x50++0x7 line.long 0x0 "ICUSARE,Interrupt Controller Unit Security Attribution Register E" bitfld.long 0x0 31. "SAIIC0WUP,Security attributes of registers for WUPEN0.b31" "0: Secure,1: Non-secure" bitfld.long 0x0 30. "SAAGT1CBWUP,Security attributes of registers for WUPEN0.b30" "0: Secure,1: Non-secure" bitfld.long 0x0 29. "SAAGT1CAWUP,Security attributes of registers for WUPEN0.b29" "0: Secure,1: Non-secure" bitfld.long 0x0 28. "SAAGT1UDWUP,Security attributes of registers for WUPEN0.b28" "0: Secure,1: Non-secure" newline bitfld.long 0x0 27. "SAUSBFS0WUP,Security attributes of registers for WUPEN0.b27" "0: Secure,1: Non-secure" bitfld.long 0x0 25. "SARTCPRDWUP,Security attributes of registers for WUPEN0.b25" "0: Secure,1: Non-secure" bitfld.long 0x0 24. "SARTCALMWUP,Security attributes of registers for WUPEN0.b24" "0: Secure,1: Non-secure" bitfld.long 0x0 20. "SAVBATTWUP,Security attributes of registers for WUPEN0.b20" "0: Secure,1: Non-secure" newline bitfld.long 0x0 19. "SAPVD2WUP,Security attributes of registers for WUPEN0.b19" "0: Secure,1: Non-secure" bitfld.long 0x0 18. "SAPVD1WUP,Security attributes of registers for WUPEN0.b18" "0: Secure,1: Non-secure" bitfld.long 0x0 16. "SAIWDTWUP,Security attributes of registers for WUPEN0.b16" "0: Secure,1: Non-secure" line.long 0x4 "ICUSARF,Interrupt Controller Unit Security Attribution Register F" bitfld.long 0x4 14. "SAULP1BWUP,Security attributes of registers for WUPEN1.b14" "0: Secure,1: Non-secure" bitfld.long 0x4 13. "SAULP1AWUP,Security attributes of registers for WUPEN1.b13" "0: Secure,1: Non-secure" bitfld.long 0x4 12. "SAULP1UWUP,Security attributes of registers for WUPEN1.b12" "0: Secure,1: Non-secure" bitfld.long 0x4 10. "SAULP0BWUP,Security attributes of registers for WUPEN1.b10" "0: Secure,1: Non-secure" newline bitfld.long 0x4 9. "SAULP0AWUP,Security attributes of registers for WUPEN1.b9" "0: Secure,1: Non-secure" bitfld.long 0x4 8. "SAULP0UWUP,Security attributes of registers for WUPEN1.b8" "0: Secure,1: Non-secure" bitfld.long 0x4 3. "SACOMPHS0WUP,Security attributes of registers for WUPEN1.b3" "0: Secure,1: Non-secure" group.long 0x70++0xB line.long 0x0 "ICUSARG,Interrupt Controller Unit Security Attribution Register G" bitfld.long 0x0 31. "SAIELSR31,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 30. "SAIELSR30,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 29. "SAIELSR29,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 28. "SAIELSR28,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" newline bitfld.long 0x0 27. "SAIELSR27,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 26. "SAIELSR26,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 25. "SAIELSR25,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 24. "SAIELSR24,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" newline bitfld.long 0x0 23. "SAIELSR23,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 22. "SAIELSR22,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 21. "SAIELSR21,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 20. "SAIELSR20,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" newline bitfld.long 0x0 19. "SAIELSR19,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 18. "SAIELSR18,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 17. "SAIELSR17,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 16. "SAIELSR16,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" newline bitfld.long 0x0 15. "SAIELSR15,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 14. "SAIELSR14,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 13. "SAIELSR13,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 12. "SAIELSR12,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" newline bitfld.long 0x0 11. "SAIELSR11,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 10. "SAIELSR10,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 9. "SAIELSR09,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 8. "SAIELSR08,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" newline bitfld.long 0x0 7. "SAIELSR07,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 6. "SAIELSR06,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 5. "SAIELSR05,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 4. "SAIELSR04,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" newline bitfld.long 0x0 3. "SAIELSR03,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 2. "SAIELSR02,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 1. "SAIELSR01,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" bitfld.long 0x0 0. "SAIELSR00,Security attributes of registers for IELSR31 to IELSR0" "0: Secure,1: Non-secure" line.long 0x4 "ICUSARH,Interrupt Controller Unit Security Attribution Register H" bitfld.long 0x4 31. "SAIELSR63,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 30. "SAIELSR62,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 29. "SAIELSR61,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 28. "SAIELSR60,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" newline bitfld.long 0x4 27. "SAIELSR59,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 26. "SAIELSR58,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 25. "SAIELSR57,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 24. "SAIELSR56,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" newline bitfld.long 0x4 23. "SAIELSR55,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 22. "SAIELSR54,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 21. "SAIELSR53,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 20. "SAIELSR52,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" newline bitfld.long 0x4 19. "SAIELSR51,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 18. "SAIELSR50,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 17. "SAIELSR49,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 16. "SAIELSR48,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" newline bitfld.long 0x4 15. "SAIELSR47,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 14. "SAIELSR46,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 13. "SAIELSR45,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 12. "SAIELSR44,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" newline bitfld.long 0x4 11. "SAIELSR43,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 10. "SAIELSR42,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 9. "SAIELSR41,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 8. "SAIELSR40,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" newline bitfld.long 0x4 7. "SAIELSR39,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 6. "SAIELSR38,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 5. "SAIELSR37,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 4. "SAIELSR36,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" newline bitfld.long 0x4 3. "SAIELSR35,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 2. "SAIELSR34,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 1. "SAIELSR33,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" bitfld.long 0x4 0. "SAIELSR32,Security attributes of registers for IELSR63 to IELSR32" "0: Secure,1: Non-secure" line.long 0x8 "ICUSARI,Interrupt Controller Unit Security Attribution Register I" bitfld.long 0x8 31. "SAIELSR95,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 30. "SAIELSR94,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 29. "SAIELSR93,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 28. "SAIELSR92,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" newline bitfld.long 0x8 27. "SAIELSR91,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 26. "SAIELSR90,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 25. "SAIELSR89,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 24. "SAIELSR88,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" newline bitfld.long 0x8 23. "SAIELSR87,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 22. "SAIELSR86,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 21. "SAIELSR85,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 20. "SAIELSR84,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" newline bitfld.long 0x8 19. "SAIELSR83,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 18. "SAIELSR82,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 17. "SAIELSR81,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 16. "SAIELSR80,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" newline bitfld.long 0x8 15. "SAIELSR79,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 14. "SAIELSR78,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 13. "SAIELSR77,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 12. "SAIELSR76,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" newline bitfld.long 0x8 11. "SAIELSR75,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 10. "SAIELSR74,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 9. "SAIELSR73,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 8. "SAIELSR72,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" newline bitfld.long 0x8 7. "SAIELSR71,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 6. "SAIELSR70,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 5. "SAIELSR69,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 4. "SAIELSR68,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" newline bitfld.long 0x8 3. "SAIELSR67,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 2. "SAIELSR66,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 1. "SAIELSR65,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" bitfld.long 0x8 0. "SAIELSR64,Security attributes of registers for IELSR95 to IELSR64" "0: Secure,1: Non-secure" group.long 0x100++0x7 line.long 0x0 "BUSSARA,Bus Security Attribution Register A" bitfld.long 0x0 0. "BUSSA0,Bus Security Attribution A0" "0: Secure,1: Non-secure" line.long 0x4 "BUSSARB,Bus Security Attribution Register B" bitfld.long 0x4 0. "BUSSB0,Bus Security Attribution B0" "0: Secure,1: Non-secure" group.long 0x110++0x7 line.long 0x0 "BUSSARC,Bus Security Attribution Register C" bitfld.long 0x0 0. "BUSSC0,Bus Security Attribution C0" "0: Secure,1: Non-secure" line.long 0x4 "BUSPARC,Bus Privileged Attribution Register C" bitfld.long 0x4 0. "BUSPA0,External bus controller privilege attribution" "0: Privileged,1: Unprivileged" group.long 0x130++0x7 line.long 0x0 "MMPUSARA,Master Memory Protection Unit Security Attribution Register A" hexmask.long.byte 0x0 0.--7. 1. "MMPUASAn,MMPUA Security Attribution n (n = 0 to 7)" line.long 0x4 "MMPUSARB,Master Memory Protection Unit Security Attribution Register B" bitfld.long 0x4 8. "MMPUBSA8,MMPUB Security Attribution 8" "0: Secure,1: Non-secure" bitfld.long 0x4 0. "MMPUBSA0,MMPUB Security Attribution 0" "0: Secure,1: Non-secure" group.long 0x170++0x3 line.long 0x0 "CPUSAR,CPU Security Attribution Register" bitfld.long 0x0 0. "CPUSA0,CPU Control Registers Security Attribution" "0: Secure,1: Non-secure" group.long 0x180++0x3 line.long 0x0 "DEBUGSAR,Debug Security Attribution Register" bitfld.long 0x0 0. "DBGSA0,Debug Resources Security Attribution 0" "0: Secure,1: Non-secure" group.long 0x1A0++0x3 line.long 0x0 "DMACCHSAR,DMA channel Security Attribution Register" bitfld.long 0x0 7. "SADMAC7,Security attributes of output and registers for DMAC channel" "0: Secure,1: Non-secure" bitfld.long 0x0 6. "SADMAC6,Security attributes of output and registers for DMAC channel" "0: Secure,1: Non-secure" bitfld.long 0x0 5. "SADMAC5,Security attributes of output and registers for DMAC channel" "0: Secure,1: Non-secure" bitfld.long 0x0 4. "SADMAC4,Security attributes of output and registers for DMAC channel" "0: Secure,1: Non-secure" newline bitfld.long 0x0 3. "SADMAC3,Security attributes of output and registers for DMAC channel" "0: Secure,1: Non-secure" bitfld.long 0x0 2. "SADMAC2,Security attributes of output and registers for DMAC channel" "0: Secure,1: Non-secure" bitfld.long 0x0 1. "SADMAC1,Security attributes of output and registers for DMAC channel" "0: Secure,1: Non-secure" bitfld.long 0x0 0. "SADMAC0,Security attributes of output and registers for DMAC channel" "0: Secure,1: Non-secure" group.long 0x1F0++0x3 line.long 0x0 "DMACCHPAR,DMA channel Privilege Attribution Register" bitfld.long 0x0 7. "PADMAC7,Privilege attributes of outputs and registers for DMAC channel" "0: Privileged.,1: Unprivileged." bitfld.long 0x0 6. "PADMAC6,Privilege attributes of outputs and registers for DMAC channel" "0: Privileged.,1: Unprivileged." bitfld.long 0x0 5. "PADMAC5,Privilege attributes of outputs and registers for DMAC channel" "0: Privileged.,1: Unprivileged." bitfld.long 0x0 4. "PADMAC4,Privilege attributes of outputs and registers for DMAC channel" "0: Privileged.,1: Unprivileged." newline bitfld.long 0x0 3. "PADMAC3,Privilege attributes of outputs and registers for DMAC channel" "0: Privileged.,1: Unprivileged." bitfld.long 0x0 2. "PADMAC2,Privilege attributes of outputs and registers for DMAC channel" "0: Privileged.,1: Unprivileged." bitfld.long 0x0 1. "PADMAC1,Privilege attributes of outputs and registers for DMAC channel" "0: Privileged.,1: Unprivileged." bitfld.long 0x0 0. "PADMAC0,Privilege attributes of outputs and registers for DMAC channel" "0: Privileged.,1: Unprivileged." repeat 3. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x400)++0x3 line.long 0x0 "SRAMSABAR$1,SRAM Error Address Register" repeat.end group.long 0x420++0x3 line.long 0x0 "STBRAMSABAR,Standby SRAM Security Attribute Boundary Address Register" group.long 0x490++0x3 line.long 0x0 "STBRAMPABAR_NS,Standby SRAM Privilege Attribute Boundary Address Register for Non-secure" group.long 0x600++0x3 line.long 0x0 "TEVTRCR,Trusted Event Route Control Register" bitfld.long 0x0 0. "TEVTE,Trusted Event Route Control Register for IELSRn DELSRn and ELCSRn" "0: Disable,1: Enable" tree.end tree.end tree "CPU (CPU Registers)" base ad:0x0 tree "CPU_CTRL" base ad:0x4000F000 group.byte 0x30++0x0 line.byte 0x0 "CPULCKUPCR,CPU Lockup Control Register" bitfld.byte 0x0 0. "OAD,Operation after detection of CPU lockup" "0: Non-maskable Interrupt,1: CPU Lockup reset" group.byte 0x400++0x0 line.byte 0x0 "CPULOCKCR,CPU Function Lock Control Register" bitfld.byte 0x0 5. "LCKDCAIC" "0,1" bitfld.byte 0x0 4. "LCKDTGU,Disable writes to registers that are associated with the DTCM interface security gating from software or from a debug agent connected to the processor:" "0,1" bitfld.byte 0x0 3. "LCKITGU,Disable writes to registers that are associated with the ITCM interface security gating from software or from a debug agent connected to the processor:" "0,1" bitfld.byte 0x0 2. "LCKSAU,Disable writes to registers that are associated with the SAU region from software or from a debug agent connected to the processor:" "0,1" bitfld.byte 0x0 1. "LCKSMPU,Disable writes to registers that are associated with the Secure MPU region from software or from a debug agent connected to the processor:" "0,1" bitfld.byte 0x0 0. "LCKSVTAIR,Disable writes to the following secure registers from software or from a debug agent that is connected to the processor:" "0,1" group.word 0x840++0x1 line.word 0x0 "CPUCRPT,CPU Control Register Protection Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,The KEY[7:0] bits enable or disable writing to the PROTECT bit." bitfld.word 0x0 0. "PROTECT,Protection of register" "0: Writing to CPULCKUPCR register is permitted.,1: Writing to CPULCKUPCR register is not permitted." tree.end tree "CPU_CTRL_NS" base ad:0x5000F000 group.byte 0x30++0x0 line.byte 0x0 "CPULCKUPCR,CPU Lockup Control Register" bitfld.byte 0x0 0. "OAD,Operation after detection of CPU lockup" "0: Non-maskable Interrupt,1: CPU Lockup reset" group.byte 0x500++0x0 line.byte 0x0 "CPULOCKCRNS,CPU Non-secure Function Lock Control Register" bitfld.byte 0x0 1. "LCKNSMPU,Disable writes to registers that are associated with the Non-secure MPU region from software or from a debug agent connected to the processor:" "0,1" bitfld.byte 0x0 0. "LCKNSVTOR" "0,1" group.word 0x840++0x1 line.word 0x0 "CPUCRPT,CPU Control Register Protection Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,The KEY[7:0] bits enable or disable writing to the PROTECT bit." bitfld.word 0x0 0. "PROTECT,Protection of register" "0: Writing to CPULCKUPCR register is permitted.,1: Writing to CPULCKUPCR register is not permitted." tree.end tree "CPU_DBG" base ad:0x4001B000 rgroup.long 0x0++0x3 line.long 0x0 "DBGSTR,Debug Status Register" bitfld.long 0x0 29. "CDBGPWRUPACK,Debug power-up acknowledge" "0: Debug power-up request is not acknowledged,1: Debug power-up request is acknowledged" bitfld.long 0x0 28. "CDBGPWRUPREQ,Debug power-up request" "0: OCD is not requesting debug power-up,1: OCD is requesting debug power-up" group.long 0x10++0x3 line.long 0x0 "DBGSTOPCR,Debug Stop Control Register" bitfld.long 0x0 24. "DBGSTOP_RER" "0: Enable SRAM parity error reset/interrupt,1: Mask SRAM parity error reset/interrupt" bitfld.long 0x0 17. "DBGSTOP_PVD,Mask bit for PVDn (n = 1 2) reset/interrupt" "0: Enable PVDn (n = 1 2) reset/interrupt,1: Mask PVDn (n = 1 2) reset/interrupt" newline bitfld.long 0x0 1. "DBGSTOP_WDT0,Mask bit for WDT reset/interrupt in the OCD run mode" "0: Enable WDT reset/interrupt,1: Mask WDT reset/interrupt and stop WDT counter" bitfld.long 0x0 0. "DBGSTOP_IWDT,Mask bit for IWDT reset/interrupt in the OCD run mode" "0: Enable IWDT reset/interrupt,1: Mask IWDT reset/interrupt and stop IWDT counter" group.long 0x20++0x7 line.long 0x0 "DBGAUTH0,Debug Authentication Control Register 0" bitfld.long 0x0 31. "SWDBG,Software control of debug function" "0: Disabled,1: Enabled" bitfld.long 0x0 16. "DEVICEEN,APB-AP (AP1) authentication" "0: Disabled,1: Enabled" newline bitfld.long 0x0 8. "DBGENAP,CPU AHB-AP (AP0) debug enable" "0: Disabled,1: Enabled" bitfld.long 0x0 4. "NIDEN0,CPU non-invasive debug enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "DBGEN0,CPU invasive debug enable" "0: Disabled,1: Enabled" line.long 0x4 "DBGAUTH1,Debug Authentication Control Register 1" bitfld.long 0x4 8. "SPIDENAP,CPU AHB-AP (AP0) debug enable" "0: Disabled,1: Enabled" group.long 0x30++0x3 line.long 0x0 "TRPORTCR,Trace Port Control Register" bitfld.long 0x0 2.--3. "DRV,Port Drive Capability Control indicates trace port buffer speed:" "0: Low-drive,1: Middle-drive,?,?" bitfld.long 0x0 0. "OE,Data Out Enable bit indicates whether Trace Clock Trace Data and SWO outputs are enabled." "0: Output disabled,1: Output enabled" group.long 0x40++0x3 line.long 0x0 "CACHEDBGCR,Cache Debug Control Register" bitfld.long 0x0 0. "L1RSTDIS,Disable L1 cache automatic invalidation" "0: Enable automatic invalidation of the L1 cache,1: Disable automatic invalidation of the L1 cache" group.long 0x300++0x3 line.long 0x0 "DBGMOCOEN,MOCO Enable Request Register for Debug" bitfld.long 0x0 0. "MOCOEN,MOCO enable request" "0: No request MOCO enable,1: Request MOCO enable" group.long 0x310++0x3 line.long 0x0 "DBGFCLKSEL,Flash Sequencer Clock Select Register for Debug" bitfld.long 0x0 0. "FCLKSEL,Flash sequencer clock select" "0: FCLK,1: MOCO" tree.end tree "CPU_DBG_NS" base ad:0x5001B000 rgroup.long 0x0++0x3 line.long 0x0 "DBGSTR,Debug Status Register" bitfld.long 0x0 29. "CDBGPWRUPACK,Debug power-up acknowledge" "0: Debug power-up request is not acknowledged,1: Debug power-up request is acknowledged" bitfld.long 0x0 28. "CDBGPWRUPREQ,Debug power-up request" "0: OCD is not requesting debug power-up,1: OCD is requesting debug power-up" group.long 0x10++0x3 line.long 0x0 "DBGSTOPCR,Debug Stop Control Register" bitfld.long 0x0 24. "DBGSTOP_RER" "0: Enable SRAM parity error reset/interrupt,1: Mask SRAM parity error reset/interrupt" bitfld.long 0x0 17. "DBGSTOP_PVD,Mask bit for PVDn (n = 1 2) reset/interrupt" "0: Enable PVDn (n = 1 2) reset/interrupt,1: Mask PVDn (n = 1 2) reset/interrupt" newline bitfld.long 0x0 1. "DBGSTOP_WDT0,Mask bit for WDT reset/interrupt in the OCD run mode" "0: Enable WDT reset/interrupt,1: Mask WDT reset/interrupt and stop WDT counter" bitfld.long 0x0 0. "DBGSTOP_IWDT,Mask bit for IWDT reset/interrupt in the OCD run mode" "0: Enable IWDT reset/interrupt,1: Mask IWDT reset/interrupt and stop IWDT counter" group.long 0x20++0x3 line.long 0x0 "DBGAUTH0,Debug Authentication Control Register 0" bitfld.long 0x0 31. "SWDBG,Software control of debug function" "0: Disabled,1: Enabled" bitfld.long 0x0 16. "DEVICEEN,APB-AP (AP1) authentication" "0: Disabled,1: Enabled" newline bitfld.long 0x0 8. "DBGENAP,CPU AHB-AP (AP0) debug enable" "0: Disabled,1: Enabled" bitfld.long 0x0 4. "NIDEN0,CPU non-invasive debug enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "DBGEN0,CPU invasive debug enable" "0: Disabled,1: Enabled" group.long 0x30++0x3 line.long 0x0 "TRPORTCR,Trace Port Control Register" bitfld.long 0x0 2.--3. "DRV,Port Drive Capability Control indicates trace port buffer speed:" "0: Low-drive,1: Middle-drive,?,?" bitfld.long 0x0 0. "OE,Data Out Enable bit indicates whether Trace Clock Trace Data and SWO outputs are enabled." "0: Output disabled,1: Output enabled" group.long 0x300++0x3 line.long 0x0 "DBGMOCOEN,MOCO Enable Request Register for Debug" bitfld.long 0x0 0. "MOCOEN,MOCO enable request" "0: No request MOCO enable,1: Request MOCO enable" group.long 0x310++0x3 line.long 0x0 "DBGFCLKSEL,Flash Sequencer Clock Select Register for Debug" bitfld.long 0x0 0. "FCLKSEL,Flash sequencer clock select" "0: FCLK,1: MOCO" tree.end tree.end tree "CRC (Cyclic Redundancy Check)" base ad:0x0 tree "CRC" base ad:0x40310000 group.byte 0x0++0x1 line.byte 0x0 "CRCCR0,CRC Control Register 0" bitfld.byte 0x0 7. "DORCLR,CRCDOR/CRCDOR_HA/CRCDOR_BY Register Clear" "0: No effect,1: Clear the CRCDOR/CRCDOR_HA/CRCDOR_BY register" bitfld.byte 0x0 6. "LMS,CRC Calculation Switching" "0: Generate CRC code for LSB-first communication,1: Generate CRC code for MSB-first communication" newline bitfld.byte 0x0 0.--2. "GPS,CRC Generating Polynomial Switching" "0: No calculation is executed,1: 8-bit CRC-8 (X8 + X2 + X + 1),?,?,?,?,?,?" line.byte 0x1 "CRCCR1,CRC Control Register 1" bitfld.byte 0x1 7. "CRCSEN,Snoop Enable" "0: Disabled,1: Enabled" bitfld.byte 0x1 6. "CRCSWR,Snoop-On-Write/Read Switch" "0: Snoop-on-read,1: Snoop-on-write" group.long 0x4++0x3 line.long 0x0 "CRCDIR,CRC Data Input Register" group.byte 0x4++0x0 line.byte 0x0 "CRCDIR_BY,CRC Data Input Register" group.long 0x8++0x3 line.long 0x0 "CRCDOR,CRC Data Output Register" group.word 0x8++0x1 line.word 0x0 "CRCDOR_HA,CRC Data Output Register" group.byte 0x8++0x0 line.byte 0x0 "CRCDOR_BY,CRC Data Output Register" group.word 0xC++0x1 line.word 0x0 "CRCSAR,Snoop Address Register" hexmask.word 0x0 0.--13. 1. "CRCSA,Register Snoop Address" tree.end tree "CRC_NS" base ad:0x50310000 group.byte 0x0++0x1 line.byte 0x0 "CRCCR0,CRC Control Register 0" bitfld.byte 0x0 7. "DORCLR,CRCDOR/CRCDOR_HA/CRCDOR_BY Register Clear" "0: No effect,1: Clear the CRCDOR/CRCDOR_HA/CRCDOR_BY register" bitfld.byte 0x0 6. "LMS,CRC Calculation Switching" "0: Generate CRC code for LSB-first communication,1: Generate CRC code for MSB-first communication" newline bitfld.byte 0x0 0.--2. "GPS,CRC Generating Polynomial Switching" "0: No calculation is executed,1: 8-bit CRC-8 (X8 + X2 + X + 1),?,?,?,?,?,?" line.byte 0x1 "CRCCR1,CRC Control Register 1" bitfld.byte 0x1 7. "CRCSEN,Snoop Enable" "0: Disabled,1: Enabled" bitfld.byte 0x1 6. "CRCSWR,Snoop-On-Write/Read Switch" "0: Snoop-on-read,1: Snoop-on-write" group.long 0x4++0x3 line.long 0x0 "CRCDIR,CRC Data Input Register" group.byte 0x4++0x0 line.byte 0x0 "CRCDIR_BY,CRC Data Input Register" group.long 0x8++0x3 line.long 0x0 "CRCDOR,CRC Data Output Register" group.word 0x8++0x1 line.word 0x0 "CRCDOR_HA,CRC Data Output Register" group.byte 0x8++0x0 line.byte 0x0 "CRCDOR_BY,CRC Data Output Register" group.word 0xC++0x1 line.word 0x0 "CRCSAR,Snoop Address Register" hexmask.word 0x0 0.--13. 1. "CRCSA,Register Snoop Address" tree.end tree.end tree "DAC12 (12-Bit D/A Converter)" base ad:0x0 tree "DAC12" base ad:0x40333000 group.word 0x0++0x1 line.word 0x0 "DADR0,D/A Data Register 0" group.byte 0x4++0x2 line.byte 0x0 "DACR,D/A Control Register" bitfld.byte 0x0 6. "DAOE0,D/A Output Enable 0" "0: Disable analog output of channel 0 (DA0),1: Enable D/A conversion of channel 0 (DA0)" line.byte 0x1 "DADPR,DADRn Format Select Register" bitfld.byte 0x1 7. "DPSEL,DADRn Format Select" "0: Right-justified format,1: Left-justified format" line.byte 0x2 "DAADSCR,D/A A/D Synchronous Start Control Register" bitfld.byte 0x2 7. "DAADST,D/A A/D Synchronous Conversion" "0: Do not synchronize DAC12 with ADC12 (unit 1)..,1: Synchronize DAC12 with ADC12 (unit 1) operation.." group.byte 0x8++0x0 line.byte 0x0 "DAAMPCR,D/A Output Amplifier Control Register" bitfld.byte 0x0 6. "DAAMP0,Amplifier Control 0" "0: Do not use channel 0 output amplifier,1: Use channel 0 output amplifier" group.byte 0x1C++0x0 line.byte 0x0 "DAASWCR,D/A Amplifier Stabilization Wait Control Register" bitfld.byte 0x0 6. "DAASW0,D/A Amplifier Stabilization Wait 0 and D/A internal output control" "0: For output to external pin: Amplifier..,1: For output to external pin: Amplifier.." group.byte 0x10C0++0x0 line.byte 0x0 "DAADUSR,D/A A/D Synchronous Unit Select Register" bitfld.byte 0x0 1. "AMADSEL1,A/D Unit 1 Select" "0: Do not select unit 1,1: Select unit 1" tree.end tree "DAC12_NS" base ad:0x50333000 group.word 0x0++0x1 line.word 0x0 "DADR0,D/A Data Register 0" group.byte 0x4++0x2 line.byte 0x0 "DACR,D/A Control Register" bitfld.byte 0x0 6. "DAOE0,D/A Output Enable 0" "0: Disable analog output of channel 0 (DA0),1: Enable D/A conversion of channel 0 (DA0)" line.byte 0x1 "DADPR,DADRn Format Select Register" bitfld.byte 0x1 7. "DPSEL,DADRn Format Select" "0: Right-justified format,1: Left-justified format" line.byte 0x2 "DAADSCR,D/A A/D Synchronous Start Control Register" bitfld.byte 0x2 7. "DAADST,D/A A/D Synchronous Conversion" "0: Do not synchronize DAC12 with ADC12 (unit 1)..,1: Synchronize DAC12 with ADC12 (unit 1) operation.." group.byte 0x8++0x0 line.byte 0x0 "DAAMPCR,D/A Output Amplifier Control Register" bitfld.byte 0x0 6. "DAAMP0,Amplifier Control 0" "0: Do not use channel 0 output amplifier,1: Use channel 0 output amplifier" group.byte 0x1C++0x0 line.byte 0x0 "DAASWCR,D/A Amplifier Stabilization Wait Control Register" bitfld.byte 0x0 6. "DAASW0,D/A Amplifier Stabilization Wait 0 and D/A internal output control" "0: For output to external pin: Amplifier..,1: For output to external pin: Amplifier.." group.byte 0x10C0++0x0 line.byte 0x0 "DAADUSR,D/A A/D Synchronous Unit Select Register" bitfld.byte 0x0 1. "AMADSEL1,A/D Unit 1 Select" "0: Do not select unit 1,1: Select unit 1" tree.end tree.end tree "DMA (DMAC Module Activation)" base ad:0x0 tree "DMA0" base ad:0x4000A800 group.byte 0x0++0x0 line.byte 0x0 "DMAST,DMA Module Activation Register" bitfld.byte 0x0 0. "DMST,DMAC Operation Enable" "0: DMAC activation is disabled.,1: DMAC activation is enabled." group.long 0x40++0x3 line.long 0x0 "DMECHR,DMAC Error Channel Register" bitfld.long 0x0 16. "DMESTA,DMAC Error Status" "0: No DMA transfer error occurred,1: DMA transfer error occurred" rbitfld.long 0x0 8. "DMECHSAM,DMAC Error channel Security Attribution Monitor" "0: secure channel,1: non-secure channel" rbitfld.long 0x0 0.--2. "DMECH,DMAC Error channel" "0,1,2,3,4,5,6,7" repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "DELSR$1,DMAC Event Link Setting Register %s" bitfld.long 0x0 16. "IR,DMAC Activation Request Status flag" "0: No DMAC activation request occurred.,1: DMAC activation request occurred." hexmask.long.word 0x0 0.--8. 1. "DELS,DMAC Event Link Select" repeat.end tree.end tree "DMA0_NS" base ad:0x5000A800 group.byte 0x0++0x0 line.byte 0x0 "DMAST,DMA Module Activation Register" bitfld.byte 0x0 0. "DMST,DMAC Operation Enable" "0: DMAC activation is disabled.,1: DMAC activation is enabled." group.long 0x40++0x3 line.long 0x0 "DMECHR,DMAC Error Channel Register" bitfld.long 0x0 16. "DMESTA,DMAC Error Status" "0: No DMA transfer error occurred,1: DMA transfer error occurred" rbitfld.long 0x0 8. "DMECHSAM,DMAC Error channel Security Attribution Monitor" "0: secure channel,1: non-secure channel" rbitfld.long 0x0 0.--2. "DMECH,DMAC Error channel" "0,1,2,3,4,5,6,7" repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "DELSR$1,DMAC Event Link Setting Register %s" bitfld.long 0x0 16. "IR,DMAC Activation Request Status flag" "0: No DMAC activation request occurred.,1: DMAC activation request occurred." hexmask.long.word 0x0 0.--8. 1. "DELS,DMAC Event Link Select" repeat.end tree.end tree "DMAC00" base ad:0x4000A000 group.long 0x0++0xF line.long 0x0 "DMSAR,DMA Source Address Register" line.long 0x4 "DMDAR,DMA Destination Address Register" line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" line.long 0xC "DMCRB,DMA Block Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "DMCRBH,Specifies the number of block repeat or repeat-block transfer operations." hexmask.long.word 0xC 0.--15. 1. "DMCRBL,Functions as a number of block repeat or repeat-block transfer counter." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10. "TKP,Transfer Keeping" "0: Transfer is stopped by completion of specified..,1: Transfer is not stopped by completion of.." bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software request,1: Hardware request,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disables the transfer end interrupt request.,1: Enables the transfer end interrupt request." bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disables the transfer escape end interrupt..,1: Enables the transfer escape end interrupt request." newline bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disables the repeat size end interrupt request.,1: Enables the repeat size end interrupt request." bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." newline bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Source address is fixed.,1: Offset addition.,?,?" bitfld.word 0x0 13. "SADR,Source Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area" bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Destination address is fixed.,1: Offset addition.,?,?" newline bitfld.word 0x0 5. "DADR,Destination Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area" group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disables DMA transfer.,1: Enables DMA transfer." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMAC Active Flag" "0: DMAC is in the idle state.,1: DMAC is operating." bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: A transfer end interrupt has not been generated.,1: A transfer end interrupt has been generated." newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: A transfer escape end interrupt has not been..,1: A transfer escape end interrupt has been.." group.long 0x20++0xF line.long 0x0 "DMSRR,DMA Source Reload Address Register" line.long 0x4 "DMDRR,DMA Destination Reload Address Register" line.long 0x8 "DMSBS,DMA Source Buffer Size Register" hexmask.long.word 0x8 16.--31. 1. "DMSBSH,Specifies the repeat-area size in repeat-block transfer mode" hexmask.long.word 0x8 0.--15. 1. "DMSBSL,Functions as data transfer counter in repeat-block transfer mode" line.long 0xC "DMDBS,DMA Destination Buffer Size Register" hexmask.long.word 0xC 16.--31. 1. "DMDBSH,Specifies the repeat-area size in repeat-block transfer mode." hexmask.long.word 0xC 0.--15. 1. "DMDBSL,Functions as data transfer counter in repeat-block transfer mode." group.byte 0x30++0x0 line.byte 0x0 "DMBWR,DMA Bufferable Write Enable Register" bitfld.byte 0x0 0. "BWE,Bufferable Write Enable" "0: Disables Bufferable Write,1: Enables Bufferable Write" tree.end tree "DMAC00_NS" base ad:0x5000A000 group.long 0x0++0xF line.long 0x0 "DMSAR,DMA Source Address Register" line.long 0x4 "DMDAR,DMA Destination Address Register" line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" line.long 0xC "DMCRB,DMA Block Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "DMCRBH,Specifies the number of block repeat or repeat-block transfer operations." hexmask.long.word 0xC 0.--15. 1. "DMCRBL,Functions as a number of block repeat or repeat-block transfer counter." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10. "TKP,Transfer Keeping" "0: Transfer is stopped by completion of specified..,1: Transfer is not stopped by completion of.." bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software request,1: Hardware request,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disables the transfer end interrupt request.,1: Enables the transfer end interrupt request." bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disables the transfer escape end interrupt..,1: Enables the transfer escape end interrupt request." newline bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disables the repeat size end interrupt request.,1: Enables the repeat size end interrupt request." bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." newline bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Source address is fixed.,1: Offset addition.,?,?" bitfld.word 0x0 13. "SADR,Source Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area" bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Destination address is fixed.,1: Offset addition.,?,?" newline bitfld.word 0x0 5. "DADR,Destination Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area" group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disables DMA transfer.,1: Enables DMA transfer." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMAC Active Flag" "0: DMAC is in the idle state.,1: DMAC is operating." bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: A transfer end interrupt has not been generated.,1: A transfer end interrupt has been generated." newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: A transfer escape end interrupt has not been..,1: A transfer escape end interrupt has been.." group.long 0x20++0xF line.long 0x0 "DMSRR,DMA Source Reload Address Register" line.long 0x4 "DMDRR,DMA Destination Reload Address Register" line.long 0x8 "DMSBS,DMA Source Buffer Size Register" hexmask.long.word 0x8 16.--31. 1. "DMSBSH,Specifies the repeat-area size in repeat-block transfer mode" hexmask.long.word 0x8 0.--15. 1. "DMSBSL,Functions as data transfer counter in repeat-block transfer mode" line.long 0xC "DMDBS,DMA Destination Buffer Size Register" hexmask.long.word 0xC 16.--31. 1. "DMDBSH,Specifies the repeat-area size in repeat-block transfer mode." hexmask.long.word 0xC 0.--15. 1. "DMDBSL,Functions as data transfer counter in repeat-block transfer mode." group.byte 0x30++0x0 line.byte 0x0 "DMBWR,DMA Bufferable Write Enable Register" bitfld.byte 0x0 0. "BWE,Bufferable Write Enable" "0: Disables Bufferable Write,1: Enables Bufferable Write" tree.end tree "DMAC01" base ad:0x4000A040 group.long 0x0++0xF line.long 0x0 "DMSAR,DMA Source Address Register" line.long 0x4 "DMDAR,DMA Destination Address Register" line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" line.long 0xC "DMCRB,DMA Block Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "DMCRBH,Specifies the number of block repeat or repeat-block transfer operations." hexmask.long.word 0xC 0.--15. 1. "DMCRBL,Functions as a number of block repeat or repeat-block transfer counter." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10. "TKP,Transfer Keeping" "0: Transfer is stopped by completion of specified..,1: Transfer is not stopped by completion of.." bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software request,1: Hardware request,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disables the transfer end interrupt request.,1: Enables the transfer end interrupt request." bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disables the transfer escape end interrupt..,1: Enables the transfer escape end interrupt request." newline bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disables the repeat size end interrupt request.,1: Enables the repeat size end interrupt request." bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." newline bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Source address is fixed.,1: Offset addition.,?,?" bitfld.word 0x0 13. "SADR,Source Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area" bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Destination address is fixed.,1: Offset addition.,?,?" newline bitfld.word 0x0 5. "DADR,Destination Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area" group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disables DMA transfer.,1: Enables DMA transfer." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMAC Active Flag" "0: DMAC is in the idle state.,1: DMAC is operating." bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: A transfer end interrupt has not been generated.,1: A transfer end interrupt has been generated." newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: A transfer escape end interrupt has not been..,1: A transfer escape end interrupt has been.." group.long 0x20++0xF line.long 0x0 "DMSRR,DMA Source Reload Address Register" line.long 0x4 "DMDRR,DMA Destination Reload Address Register" line.long 0x8 "DMSBS,DMA Source Buffer Size Register" hexmask.long.word 0x8 16.--31. 1. "DMSBSH,Specifies the repeat-area size in repeat-block transfer mode" hexmask.long.word 0x8 0.--15. 1. "DMSBSL,Functions as data transfer counter in repeat-block transfer mode" line.long 0xC "DMDBS,DMA Destination Buffer Size Register" hexmask.long.word 0xC 16.--31. 1. "DMDBSH,Specifies the repeat-area size in repeat-block transfer mode." hexmask.long.word 0xC 0.--15. 1. "DMDBSL,Functions as data transfer counter in repeat-block transfer mode." group.byte 0x30++0x0 line.byte 0x0 "DMBWR,DMA Bufferable Write Enable Register" bitfld.byte 0x0 0. "BWE,Bufferable Write Enable" "0: Disables Bufferable Write,1: Enables Bufferable Write" tree.end tree "DMAC01_NS" base ad:0x5000A040 group.long 0x0++0xF line.long 0x0 "DMSAR,DMA Source Address Register" line.long 0x4 "DMDAR,DMA Destination Address Register" line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" line.long 0xC "DMCRB,DMA Block Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "DMCRBH,Specifies the number of block repeat or repeat-block transfer operations." hexmask.long.word 0xC 0.--15. 1. "DMCRBL,Functions as a number of block repeat or repeat-block transfer counter." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10. "TKP,Transfer Keeping" "0: Transfer is stopped by completion of specified..,1: Transfer is not stopped by completion of.." bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software request,1: Hardware request,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disables the transfer end interrupt request.,1: Enables the transfer end interrupt request." bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disables the transfer escape end interrupt..,1: Enables the transfer escape end interrupt request." newline bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disables the repeat size end interrupt request.,1: Enables the repeat size end interrupt request." bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." newline bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Source address is fixed.,1: Offset addition.,?,?" bitfld.word 0x0 13. "SADR,Source Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area" bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Destination address is fixed.,1: Offset addition.,?,?" newline bitfld.word 0x0 5. "DADR,Destination Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area" group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disables DMA transfer.,1: Enables DMA transfer." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMAC Active Flag" "0: DMAC is in the idle state.,1: DMAC is operating." bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: A transfer end interrupt has not been generated.,1: A transfer end interrupt has been generated." newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: A transfer escape end interrupt has not been..,1: A transfer escape end interrupt has been.." group.long 0x20++0xF line.long 0x0 "DMSRR,DMA Source Reload Address Register" line.long 0x4 "DMDRR,DMA Destination Reload Address Register" line.long 0x8 "DMSBS,DMA Source Buffer Size Register" hexmask.long.word 0x8 16.--31. 1. "DMSBSH,Specifies the repeat-area size in repeat-block transfer mode" hexmask.long.word 0x8 0.--15. 1. "DMSBSL,Functions as data transfer counter in repeat-block transfer mode" line.long 0xC "DMDBS,DMA Destination Buffer Size Register" hexmask.long.word 0xC 16.--31. 1. "DMDBSH,Specifies the repeat-area size in repeat-block transfer mode." hexmask.long.word 0xC 0.--15. 1. "DMDBSL,Functions as data transfer counter in repeat-block transfer mode." group.byte 0x30++0x0 line.byte 0x0 "DMBWR,DMA Bufferable Write Enable Register" bitfld.byte 0x0 0. "BWE,Bufferable Write Enable" "0: Disables Bufferable Write,1: Enables Bufferable Write" tree.end tree "DMAC02" base ad:0x4000A080 group.long 0x0++0xF line.long 0x0 "DMSAR,DMA Source Address Register" line.long 0x4 "DMDAR,DMA Destination Address Register" line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" line.long 0xC "DMCRB,DMA Block Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "DMCRBH,Specifies the number of block repeat or repeat-block transfer operations." hexmask.long.word 0xC 0.--15. 1. "DMCRBL,Functions as a number of block repeat or repeat-block transfer counter." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10. "TKP,Transfer Keeping" "0: Transfer is stopped by completion of specified..,1: Transfer is not stopped by completion of.." bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software request,1: Hardware request,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disables the transfer end interrupt request.,1: Enables the transfer end interrupt request." bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disables the transfer escape end interrupt..,1: Enables the transfer escape end interrupt request." newline bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disables the repeat size end interrupt request.,1: Enables the repeat size end interrupt request." bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." newline bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Source address is fixed.,1: Offset addition.,?,?" bitfld.word 0x0 13. "SADR,Source Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area" bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Destination address is fixed.,1: Offset addition.,?,?" newline bitfld.word 0x0 5. "DADR,Destination Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area" group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disables DMA transfer.,1: Enables DMA transfer." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMAC Active Flag" "0: DMAC is in the idle state.,1: DMAC is operating." bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: A transfer end interrupt has not been generated.,1: A transfer end interrupt has been generated." newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: A transfer escape end interrupt has not been..,1: A transfer escape end interrupt has been.." group.long 0x20++0xF line.long 0x0 "DMSRR,DMA Source Reload Address Register" line.long 0x4 "DMDRR,DMA Destination Reload Address Register" line.long 0x8 "DMSBS,DMA Source Buffer Size Register" hexmask.long.word 0x8 16.--31. 1. "DMSBSH,Specifies the repeat-area size in repeat-block transfer mode" hexmask.long.word 0x8 0.--15. 1. "DMSBSL,Functions as data transfer counter in repeat-block transfer mode" line.long 0xC "DMDBS,DMA Destination Buffer Size Register" hexmask.long.word 0xC 16.--31. 1. "DMDBSH,Specifies the repeat-area size in repeat-block transfer mode." hexmask.long.word 0xC 0.--15. 1. "DMDBSL,Functions as data transfer counter in repeat-block transfer mode." group.byte 0x30++0x0 line.byte 0x0 "DMBWR,DMA Bufferable Write Enable Register" bitfld.byte 0x0 0. "BWE,Bufferable Write Enable" "0: Disables Bufferable Write,1: Enables Bufferable Write" tree.end tree "DMAC02_NS" base ad:0x5000A080 group.long 0x0++0xF line.long 0x0 "DMSAR,DMA Source Address Register" line.long 0x4 "DMDAR,DMA Destination Address Register" line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" line.long 0xC "DMCRB,DMA Block Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "DMCRBH,Specifies the number of block repeat or repeat-block transfer operations." hexmask.long.word 0xC 0.--15. 1. "DMCRBL,Functions as a number of block repeat or repeat-block transfer counter." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10. "TKP,Transfer Keeping" "0: Transfer is stopped by completion of specified..,1: Transfer is not stopped by completion of.." bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software request,1: Hardware request,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disables the transfer end interrupt request.,1: Enables the transfer end interrupt request." bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disables the transfer escape end interrupt..,1: Enables the transfer escape end interrupt request." newline bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disables the repeat size end interrupt request.,1: Enables the repeat size end interrupt request." bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." newline bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Source address is fixed.,1: Offset addition.,?,?" bitfld.word 0x0 13. "SADR,Source Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area" bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Destination address is fixed.,1: Offset addition.,?,?" newline bitfld.word 0x0 5. "DADR,Destination Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area" group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disables DMA transfer.,1: Enables DMA transfer." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMAC Active Flag" "0: DMAC is in the idle state.,1: DMAC is operating." bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: A transfer end interrupt has not been generated.,1: A transfer end interrupt has been generated." newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: A transfer escape end interrupt has not been..,1: A transfer escape end interrupt has been.." group.long 0x20++0xF line.long 0x0 "DMSRR,DMA Source Reload Address Register" line.long 0x4 "DMDRR,DMA Destination Reload Address Register" line.long 0x8 "DMSBS,DMA Source Buffer Size Register" hexmask.long.word 0x8 16.--31. 1. "DMSBSH,Specifies the repeat-area size in repeat-block transfer mode" hexmask.long.word 0x8 0.--15. 1. "DMSBSL,Functions as data transfer counter in repeat-block transfer mode" line.long 0xC "DMDBS,DMA Destination Buffer Size Register" hexmask.long.word 0xC 16.--31. 1. "DMDBSH,Specifies the repeat-area size in repeat-block transfer mode." hexmask.long.word 0xC 0.--15. 1. "DMDBSL,Functions as data transfer counter in repeat-block transfer mode." group.byte 0x30++0x0 line.byte 0x0 "DMBWR,DMA Bufferable Write Enable Register" bitfld.byte 0x0 0. "BWE,Bufferable Write Enable" "0: Disables Bufferable Write,1: Enables Bufferable Write" tree.end tree "DMAC03" base ad:0x4000A0C0 group.long 0x0++0xF line.long 0x0 "DMSAR,DMA Source Address Register" line.long 0x4 "DMDAR,DMA Destination Address Register" line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" line.long 0xC "DMCRB,DMA Block Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "DMCRBH,Specifies the number of block repeat or repeat-block transfer operations." hexmask.long.word 0xC 0.--15. 1. "DMCRBL,Functions as a number of block repeat or repeat-block transfer counter." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10. "TKP,Transfer Keeping" "0: Transfer is stopped by completion of specified..,1: Transfer is not stopped by completion of.." bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software request,1: Hardware request,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disables the transfer end interrupt request.,1: Enables the transfer end interrupt request." bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disables the transfer escape end interrupt..,1: Enables the transfer escape end interrupt request." newline bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disables the repeat size end interrupt request.,1: Enables the repeat size end interrupt request." bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." newline bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Source address is fixed.,1: Offset addition.,?,?" bitfld.word 0x0 13. "SADR,Source Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area" bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Destination address is fixed.,1: Offset addition.,?,?" newline bitfld.word 0x0 5. "DADR,Destination Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area" group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disables DMA transfer.,1: Enables DMA transfer." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMAC Active Flag" "0: DMAC is in the idle state.,1: DMAC is operating." bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: A transfer end interrupt has not been generated.,1: A transfer end interrupt has been generated." newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: A transfer escape end interrupt has not been..,1: A transfer escape end interrupt has been.." group.long 0x20++0xF line.long 0x0 "DMSRR,DMA Source Reload Address Register" line.long 0x4 "DMDRR,DMA Destination Reload Address Register" line.long 0x8 "DMSBS,DMA Source Buffer Size Register" hexmask.long.word 0x8 16.--31. 1. "DMSBSH,Specifies the repeat-area size in repeat-block transfer mode" hexmask.long.word 0x8 0.--15. 1. "DMSBSL,Functions as data transfer counter in repeat-block transfer mode" line.long 0xC "DMDBS,DMA Destination Buffer Size Register" hexmask.long.word 0xC 16.--31. 1. "DMDBSH,Specifies the repeat-area size in repeat-block transfer mode." hexmask.long.word 0xC 0.--15. 1. "DMDBSL,Functions as data transfer counter in repeat-block transfer mode." group.byte 0x30++0x0 line.byte 0x0 "DMBWR,DMA Bufferable Write Enable Register" bitfld.byte 0x0 0. "BWE,Bufferable Write Enable" "0: Disables Bufferable Write,1: Enables Bufferable Write" tree.end tree "DMAC03_NS" base ad:0x5000A0C0 group.long 0x0++0xF line.long 0x0 "DMSAR,DMA Source Address Register" line.long 0x4 "DMDAR,DMA Destination Address Register" line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" line.long 0xC "DMCRB,DMA Block Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "DMCRBH,Specifies the number of block repeat or repeat-block transfer operations." hexmask.long.word 0xC 0.--15. 1. "DMCRBL,Functions as a number of block repeat or repeat-block transfer counter." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10. "TKP,Transfer Keeping" "0: Transfer is stopped by completion of specified..,1: Transfer is not stopped by completion of.." bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software request,1: Hardware request,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disables the transfer end interrupt request.,1: Enables the transfer end interrupt request." bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disables the transfer escape end interrupt..,1: Enables the transfer escape end interrupt request." newline bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disables the repeat size end interrupt request.,1: Enables the repeat size end interrupt request." bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." newline bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Source address is fixed.,1: Offset addition.,?,?" bitfld.word 0x0 13. "SADR,Source Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area" bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Destination address is fixed.,1: Offset addition.,?,?" newline bitfld.word 0x0 5. "DADR,Destination Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area" group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disables DMA transfer.,1: Enables DMA transfer." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMAC Active Flag" "0: DMAC is in the idle state.,1: DMAC is operating." bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: A transfer end interrupt has not been generated.,1: A transfer end interrupt has been generated." newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: A transfer escape end interrupt has not been..,1: A transfer escape end interrupt has been.." group.long 0x20++0xF line.long 0x0 "DMSRR,DMA Source Reload Address Register" line.long 0x4 "DMDRR,DMA Destination Reload Address Register" line.long 0x8 "DMSBS,DMA Source Buffer Size Register" hexmask.long.word 0x8 16.--31. 1. "DMSBSH,Specifies the repeat-area size in repeat-block transfer mode" hexmask.long.word 0x8 0.--15. 1. "DMSBSL,Functions as data transfer counter in repeat-block transfer mode" line.long 0xC "DMDBS,DMA Destination Buffer Size Register" hexmask.long.word 0xC 16.--31. 1. "DMDBSH,Specifies the repeat-area size in repeat-block transfer mode." hexmask.long.word 0xC 0.--15. 1. "DMDBSL,Functions as data transfer counter in repeat-block transfer mode." group.byte 0x30++0x0 line.byte 0x0 "DMBWR,DMA Bufferable Write Enable Register" bitfld.byte 0x0 0. "BWE,Bufferable Write Enable" "0: Disables Bufferable Write,1: Enables Bufferable Write" tree.end tree "DMAC04" base ad:0x4000A100 group.long 0x0++0xF line.long 0x0 "DMSAR,DMA Source Address Register" line.long 0x4 "DMDAR,DMA Destination Address Register" line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" line.long 0xC "DMCRB,DMA Block Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "DMCRBH,Specifies the number of block repeat or repeat-block transfer operations." hexmask.long.word 0xC 0.--15. 1. "DMCRBL,Functions as a number of block repeat or repeat-block transfer counter." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10. "TKP,Transfer Keeping" "0: Transfer is stopped by completion of specified..,1: Transfer is not stopped by completion of.." bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software request,1: Hardware request,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disables the transfer end interrupt request.,1: Enables the transfer end interrupt request." bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disables the transfer escape end interrupt..,1: Enables the transfer escape end interrupt request." newline bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disables the repeat size end interrupt request.,1: Enables the repeat size end interrupt request." bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." newline bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Source address is fixed.,1: Offset addition.,?,?" bitfld.word 0x0 13. "SADR,Source Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area" bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Destination address is fixed.,1: Offset addition.,?,?" newline bitfld.word 0x0 5. "DADR,Destination Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area" group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disables DMA transfer.,1: Enables DMA transfer." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMAC Active Flag" "0: DMAC is in the idle state.,1: DMAC is operating." bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: A transfer end interrupt has not been generated.,1: A transfer end interrupt has been generated." newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: A transfer escape end interrupt has not been..,1: A transfer escape end interrupt has been.." group.long 0x20++0xF line.long 0x0 "DMSRR,DMA Source Reload Address Register" line.long 0x4 "DMDRR,DMA Destination Reload Address Register" line.long 0x8 "DMSBS,DMA Source Buffer Size Register" hexmask.long.word 0x8 16.--31. 1. "DMSBSH,Specifies the repeat-area size in repeat-block transfer mode" hexmask.long.word 0x8 0.--15. 1. "DMSBSL,Functions as data transfer counter in repeat-block transfer mode" line.long 0xC "DMDBS,DMA Destination Buffer Size Register" hexmask.long.word 0xC 16.--31. 1. "DMDBSH,Specifies the repeat-area size in repeat-block transfer mode." hexmask.long.word 0xC 0.--15. 1. "DMDBSL,Functions as data transfer counter in repeat-block transfer mode." group.byte 0x30++0x0 line.byte 0x0 "DMBWR,DMA Bufferable Write Enable Register" bitfld.byte 0x0 0. "BWE,Bufferable Write Enable" "0: Disables Bufferable Write,1: Enables Bufferable Write" tree.end tree "DMAC04_NS" base ad:0x5000A100 group.long 0x0++0xF line.long 0x0 "DMSAR,DMA Source Address Register" line.long 0x4 "DMDAR,DMA Destination Address Register" line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" line.long 0xC "DMCRB,DMA Block Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "DMCRBH,Specifies the number of block repeat or repeat-block transfer operations." hexmask.long.word 0xC 0.--15. 1. "DMCRBL,Functions as a number of block repeat or repeat-block transfer counter." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10. "TKP,Transfer Keeping" "0: Transfer is stopped by completion of specified..,1: Transfer is not stopped by completion of.." bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software request,1: Hardware request,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disables the transfer end interrupt request.,1: Enables the transfer end interrupt request." bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disables the transfer escape end interrupt..,1: Enables the transfer escape end interrupt request." newline bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disables the repeat size end interrupt request.,1: Enables the repeat size end interrupt request." bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." newline bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Source address is fixed.,1: Offset addition.,?,?" bitfld.word 0x0 13. "SADR,Source Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area" bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Destination address is fixed.,1: Offset addition.,?,?" newline bitfld.word 0x0 5. "DADR,Destination Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area" group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disables DMA transfer.,1: Enables DMA transfer." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMAC Active Flag" "0: DMAC is in the idle state.,1: DMAC is operating." bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: A transfer end interrupt has not been generated.,1: A transfer end interrupt has been generated." newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: A transfer escape end interrupt has not been..,1: A transfer escape end interrupt has been.." group.long 0x20++0xF line.long 0x0 "DMSRR,DMA Source Reload Address Register" line.long 0x4 "DMDRR,DMA Destination Reload Address Register" line.long 0x8 "DMSBS,DMA Source Buffer Size Register" hexmask.long.word 0x8 16.--31. 1. "DMSBSH,Specifies the repeat-area size in repeat-block transfer mode" hexmask.long.word 0x8 0.--15. 1. "DMSBSL,Functions as data transfer counter in repeat-block transfer mode" line.long 0xC "DMDBS,DMA Destination Buffer Size Register" hexmask.long.word 0xC 16.--31. 1. "DMDBSH,Specifies the repeat-area size in repeat-block transfer mode." hexmask.long.word 0xC 0.--15. 1. "DMDBSL,Functions as data transfer counter in repeat-block transfer mode." group.byte 0x30++0x0 line.byte 0x0 "DMBWR,DMA Bufferable Write Enable Register" bitfld.byte 0x0 0. "BWE,Bufferable Write Enable" "0: Disables Bufferable Write,1: Enables Bufferable Write" tree.end tree "DMAC05" base ad:0x4000A140 group.long 0x0++0xF line.long 0x0 "DMSAR,DMA Source Address Register" line.long 0x4 "DMDAR,DMA Destination Address Register" line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" line.long 0xC "DMCRB,DMA Block Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "DMCRBH,Specifies the number of block repeat or repeat-block transfer operations." hexmask.long.word 0xC 0.--15. 1. "DMCRBL,Functions as a number of block repeat or repeat-block transfer counter." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10. "TKP,Transfer Keeping" "0: Transfer is stopped by completion of specified..,1: Transfer is not stopped by completion of.." bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software request,1: Hardware request,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disables the transfer end interrupt request.,1: Enables the transfer end interrupt request." bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disables the transfer escape end interrupt..,1: Enables the transfer escape end interrupt request." newline bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disables the repeat size end interrupt request.,1: Enables the repeat size end interrupt request." bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." newline bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Source address is fixed.,1: Offset addition.,?,?" bitfld.word 0x0 13. "SADR,Source Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area" bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Destination address is fixed.,1: Offset addition.,?,?" newline bitfld.word 0x0 5. "DADR,Destination Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area" group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disables DMA transfer.,1: Enables DMA transfer." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMAC Active Flag" "0: DMAC is in the idle state.,1: DMAC is operating." bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: A transfer end interrupt has not been generated.,1: A transfer end interrupt has been generated." newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: A transfer escape end interrupt has not been..,1: A transfer escape end interrupt has been.." group.long 0x20++0xF line.long 0x0 "DMSRR,DMA Source Reload Address Register" line.long 0x4 "DMDRR,DMA Destination Reload Address Register" line.long 0x8 "DMSBS,DMA Source Buffer Size Register" hexmask.long.word 0x8 16.--31. 1. "DMSBSH,Specifies the repeat-area size in repeat-block transfer mode" hexmask.long.word 0x8 0.--15. 1. "DMSBSL,Functions as data transfer counter in repeat-block transfer mode" line.long 0xC "DMDBS,DMA Destination Buffer Size Register" hexmask.long.word 0xC 16.--31. 1. "DMDBSH,Specifies the repeat-area size in repeat-block transfer mode." hexmask.long.word 0xC 0.--15. 1. "DMDBSL,Functions as data transfer counter in repeat-block transfer mode." group.byte 0x30++0x0 line.byte 0x0 "DMBWR,DMA Bufferable Write Enable Register" bitfld.byte 0x0 0. "BWE,Bufferable Write Enable" "0: Disables Bufferable Write,1: Enables Bufferable Write" tree.end tree "DMAC05_NS" base ad:0x5000A140 group.long 0x0++0xF line.long 0x0 "DMSAR,DMA Source Address Register" line.long 0x4 "DMDAR,DMA Destination Address Register" line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" line.long 0xC "DMCRB,DMA Block Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "DMCRBH,Specifies the number of block repeat or repeat-block transfer operations." hexmask.long.word 0xC 0.--15. 1. "DMCRBL,Functions as a number of block repeat or repeat-block transfer counter." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10. "TKP,Transfer Keeping" "0: Transfer is stopped by completion of specified..,1: Transfer is not stopped by completion of.." bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software request,1: Hardware request,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disables the transfer end interrupt request.,1: Enables the transfer end interrupt request." bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disables the transfer escape end interrupt..,1: Enables the transfer escape end interrupt request." newline bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disables the repeat size end interrupt request.,1: Enables the repeat size end interrupt request." bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." newline bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Source address is fixed.,1: Offset addition.,?,?" bitfld.word 0x0 13. "SADR,Source Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area" bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Destination address is fixed.,1: Offset addition.,?,?" newline bitfld.word 0x0 5. "DADR,Destination Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area" group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disables DMA transfer.,1: Enables DMA transfer." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMAC Active Flag" "0: DMAC is in the idle state.,1: DMAC is operating." bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: A transfer end interrupt has not been generated.,1: A transfer end interrupt has been generated." newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: A transfer escape end interrupt has not been..,1: A transfer escape end interrupt has been.." group.long 0x20++0xF line.long 0x0 "DMSRR,DMA Source Reload Address Register" line.long 0x4 "DMDRR,DMA Destination Reload Address Register" line.long 0x8 "DMSBS,DMA Source Buffer Size Register" hexmask.long.word 0x8 16.--31. 1. "DMSBSH,Specifies the repeat-area size in repeat-block transfer mode" hexmask.long.word 0x8 0.--15. 1. "DMSBSL,Functions as data transfer counter in repeat-block transfer mode" line.long 0xC "DMDBS,DMA Destination Buffer Size Register" hexmask.long.word 0xC 16.--31. 1. "DMDBSH,Specifies the repeat-area size in repeat-block transfer mode." hexmask.long.word 0xC 0.--15. 1. "DMDBSL,Functions as data transfer counter in repeat-block transfer mode." group.byte 0x30++0x0 line.byte 0x0 "DMBWR,DMA Bufferable Write Enable Register" bitfld.byte 0x0 0. "BWE,Bufferable Write Enable" "0: Disables Bufferable Write,1: Enables Bufferable Write" tree.end tree "DMAC06" base ad:0x4000A180 group.long 0x0++0xF line.long 0x0 "DMSAR,DMA Source Address Register" line.long 0x4 "DMDAR,DMA Destination Address Register" line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" line.long 0xC "DMCRB,DMA Block Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "DMCRBH,Specifies the number of block repeat or repeat-block transfer operations." hexmask.long.word 0xC 0.--15. 1. "DMCRBL,Functions as a number of block repeat or repeat-block transfer counter." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10. "TKP,Transfer Keeping" "0: Transfer is stopped by completion of specified..,1: Transfer is not stopped by completion of.." bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software request,1: Hardware request,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disables the transfer end interrupt request.,1: Enables the transfer end interrupt request." bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disables the transfer escape end interrupt..,1: Enables the transfer escape end interrupt request." newline bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disables the repeat size end interrupt request.,1: Enables the repeat size end interrupt request." bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." newline bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Source address is fixed.,1: Offset addition.,?,?" bitfld.word 0x0 13. "SADR,Source Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area" bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Destination address is fixed.,1: Offset addition.,?,?" newline bitfld.word 0x0 5. "DADR,Destination Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area" group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disables DMA transfer.,1: Enables DMA transfer." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMAC Active Flag" "0: DMAC is in the idle state.,1: DMAC is operating." bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: A transfer end interrupt has not been generated.,1: A transfer end interrupt has been generated." newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: A transfer escape end interrupt has not been..,1: A transfer escape end interrupt has been.." group.long 0x20++0xF line.long 0x0 "DMSRR,DMA Source Reload Address Register" line.long 0x4 "DMDRR,DMA Destination Reload Address Register" line.long 0x8 "DMSBS,DMA Source Buffer Size Register" hexmask.long.word 0x8 16.--31. 1. "DMSBSH,Specifies the repeat-area size in repeat-block transfer mode" hexmask.long.word 0x8 0.--15. 1. "DMSBSL,Functions as data transfer counter in repeat-block transfer mode" line.long 0xC "DMDBS,DMA Destination Buffer Size Register" hexmask.long.word 0xC 16.--31. 1. "DMDBSH,Specifies the repeat-area size in repeat-block transfer mode." hexmask.long.word 0xC 0.--15. 1. "DMDBSL,Functions as data transfer counter in repeat-block transfer mode." group.byte 0x30++0x0 line.byte 0x0 "DMBWR,DMA Bufferable Write Enable Register" bitfld.byte 0x0 0. "BWE,Bufferable Write Enable" "0: Disables Bufferable Write,1: Enables Bufferable Write" tree.end tree "DMAC06_NS" base ad:0x5000A180 group.long 0x0++0xF line.long 0x0 "DMSAR,DMA Source Address Register" line.long 0x4 "DMDAR,DMA Destination Address Register" line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" line.long 0xC "DMCRB,DMA Block Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "DMCRBH,Specifies the number of block repeat or repeat-block transfer operations." hexmask.long.word 0xC 0.--15. 1. "DMCRBL,Functions as a number of block repeat or repeat-block transfer counter." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10. "TKP,Transfer Keeping" "0: Transfer is stopped by completion of specified..,1: Transfer is not stopped by completion of.." bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software request,1: Hardware request,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disables the transfer end interrupt request.,1: Enables the transfer end interrupt request." bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disables the transfer escape end interrupt..,1: Enables the transfer escape end interrupt request." newline bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disables the repeat size end interrupt request.,1: Enables the repeat size end interrupt request." bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." newline bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Source address is fixed.,1: Offset addition.,?,?" bitfld.word 0x0 13. "SADR,Source Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area" bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Destination address is fixed.,1: Offset addition.,?,?" newline bitfld.word 0x0 5. "DADR,Destination Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area" group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disables DMA transfer.,1: Enables DMA transfer." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMAC Active Flag" "0: DMAC is in the idle state.,1: DMAC is operating." bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: A transfer end interrupt has not been generated.,1: A transfer end interrupt has been generated." newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: A transfer escape end interrupt has not been..,1: A transfer escape end interrupt has been.." group.long 0x20++0xF line.long 0x0 "DMSRR,DMA Source Reload Address Register" line.long 0x4 "DMDRR,DMA Destination Reload Address Register" line.long 0x8 "DMSBS,DMA Source Buffer Size Register" hexmask.long.word 0x8 16.--31. 1. "DMSBSH,Specifies the repeat-area size in repeat-block transfer mode" hexmask.long.word 0x8 0.--15. 1. "DMSBSL,Functions as data transfer counter in repeat-block transfer mode" line.long 0xC "DMDBS,DMA Destination Buffer Size Register" hexmask.long.word 0xC 16.--31. 1. "DMDBSH,Specifies the repeat-area size in repeat-block transfer mode." hexmask.long.word 0xC 0.--15. 1. "DMDBSL,Functions as data transfer counter in repeat-block transfer mode." group.byte 0x30++0x0 line.byte 0x0 "DMBWR,DMA Bufferable Write Enable Register" bitfld.byte 0x0 0. "BWE,Bufferable Write Enable" "0: Disables Bufferable Write,1: Enables Bufferable Write" tree.end tree "DMAC07" base ad:0x4000A1C0 group.long 0x0++0xF line.long 0x0 "DMSAR,DMA Source Address Register" line.long 0x4 "DMDAR,DMA Destination Address Register" line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" line.long 0xC "DMCRB,DMA Block Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "DMCRBH,Specifies the number of block repeat or repeat-block transfer operations." hexmask.long.word 0xC 0.--15. 1. "DMCRBL,Functions as a number of block repeat or repeat-block transfer counter." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10. "TKP,Transfer Keeping" "0: Transfer is stopped by completion of specified..,1: Transfer is not stopped by completion of.." bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software request,1: Hardware request,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disables the transfer end interrupt request.,1: Enables the transfer end interrupt request." bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disables the transfer escape end interrupt..,1: Enables the transfer escape end interrupt request." newline bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disables the repeat size end interrupt request.,1: Enables the repeat size end interrupt request." bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." newline bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Source address is fixed.,1: Offset addition.,?,?" bitfld.word 0x0 13. "SADR,Source Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area" bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Destination address is fixed.,1: Offset addition.,?,?" newline bitfld.word 0x0 5. "DADR,Destination Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area" group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disables DMA transfer.,1: Enables DMA transfer." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMAC Active Flag" "0: DMAC is in the idle state.,1: DMAC is operating." bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: A transfer end interrupt has not been generated.,1: A transfer end interrupt has been generated." newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: A transfer escape end interrupt has not been..,1: A transfer escape end interrupt has been.." group.long 0x20++0xF line.long 0x0 "DMSRR,DMA Source Reload Address Register" line.long 0x4 "DMDRR,DMA Destination Reload Address Register" line.long 0x8 "DMSBS,DMA Source Buffer Size Register" hexmask.long.word 0x8 16.--31. 1. "DMSBSH,Specifies the repeat-area size in repeat-block transfer mode" hexmask.long.word 0x8 0.--15. 1. "DMSBSL,Functions as data transfer counter in repeat-block transfer mode" line.long 0xC "DMDBS,DMA Destination Buffer Size Register" hexmask.long.word 0xC 16.--31. 1. "DMDBSH,Specifies the repeat-area size in repeat-block transfer mode." hexmask.long.word 0xC 0.--15. 1. "DMDBSL,Functions as data transfer counter in repeat-block transfer mode." group.byte 0x30++0x0 line.byte 0x0 "DMBWR,DMA Bufferable Write Enable Register" bitfld.byte 0x0 0. "BWE,Bufferable Write Enable" "0: Disables Bufferable Write,1: Enables Bufferable Write" tree.end tree "DMAC07_NS" base ad:0x5000A1C0 group.long 0x0++0xF line.long 0x0 "DMSAR,DMA Source Address Register" line.long 0x4 "DMDAR,DMA Destination Address Register" line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" line.long 0xC "DMCRB,DMA Block Transfer Count Register" hexmask.long.word 0xC 16.--31. 1. "DMCRBH,Specifies the number of block repeat or repeat-block transfer operations." hexmask.long.word 0xC 0.--15. 1. "DMCRBL,Functions as a number of block repeat or repeat-block transfer counter." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10. "TKP,Transfer Keeping" "0: Transfer is stopped by completion of specified..,1: Transfer is not stopped by completion of.." bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software request,1: Hardware request,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disables the transfer end interrupt request.,1: Enables the transfer end interrupt request." bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disables the transfer escape end interrupt..,1: Enables the transfer escape end interrupt request." newline bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disables the repeat size end interrupt request.,1: Enables the repeat size end interrupt request." bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." newline bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disables an interrupt request for an extended..,1: Enables an interrupt request for an extended.." group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Source address is fixed.,1: Offset addition.,?,?" bitfld.word 0x0 13. "SADR,Source Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area" bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Destination address is fixed.,1: Offset addition.,?,?" newline bitfld.word 0x0 5. "DADR,Destination Address Update Select After Reload" "0: Only reloading.,1: Add index after reloading." hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area" group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disables DMA transfer.,1: Enables DMA transfer." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMAC Active Flag" "0: DMAC is in the idle state.,1: DMAC is operating." bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: A transfer end interrupt has not been generated.,1: A transfer end interrupt has been generated." newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: A transfer escape end interrupt has not been..,1: A transfer escape end interrupt has been.." group.long 0x20++0xF line.long 0x0 "DMSRR,DMA Source Reload Address Register" line.long 0x4 "DMDRR,DMA Destination Reload Address Register" line.long 0x8 "DMSBS,DMA Source Buffer Size Register" hexmask.long.word 0x8 16.--31. 1. "DMSBSH,Specifies the repeat-area size in repeat-block transfer mode" hexmask.long.word 0x8 0.--15. 1. "DMSBSL,Functions as data transfer counter in repeat-block transfer mode" line.long 0xC "DMDBS,DMA Destination Buffer Size Register" hexmask.long.word 0xC 16.--31. 1. "DMDBSH,Specifies the repeat-area size in repeat-block transfer mode." hexmask.long.word 0xC 0.--15. 1. "DMDBSL,Functions as data transfer counter in repeat-block transfer mode." group.byte 0x30++0x0 line.byte 0x0 "DMBWR,DMA Bufferable Write Enable Register" bitfld.byte 0x0 0. "BWE,Bufferable Write Enable" "0: Disables Bufferable Write,1: Enables Bufferable Write" tree.end tree.end tree "DOC (Data Operation Circuit)" base ad:0x0 tree "DOC_B" base ad:0x40311000 group.byte 0x0++0x0 line.byte 0x0 "DOCR,DOC Control Register" bitfld.byte 0x0 4.--6. "DCSEL,Detection Condition Select" "0: Setting prohibited,1: Match (DODSR0 = DODIR),?,?,?,?,?,?" bitfld.byte 0x0 3. "DOBW,Data Operation Bit Width Select" "0: 16-bit,1: 32-bit" bitfld.byte 0x0 0.--1. "OMS,Operating Mode Select" "0: Data comparison mode,1: Data addition mode,?,?" rgroup.byte 0x4++0x0 line.byte 0x0 "DOSR,DOC Flag Status Register" bitfld.byte 0x0 0. "DOPCF,Data Operation Circuit Flag" "0,1" wgroup.byte 0x8++0x0 line.byte 0x0 "DOSCR,DOC Flag Status Clear Register" bitfld.byte 0x0 0. "DOPCFCL,DOPCF Clear" "0: Maintains the DOPCF flag state.,1: Clears the DOPCF flag." group.long 0xC++0xB line.long 0x0 "DODIR,DOC Data Input Register" line.long 0x4 "DODSR0,DOC Data Setting Register 0" line.long 0x8 "DODSR1,DOC Data Setting Register 1" tree.end tree "DOC_B_NS" base ad:0x50311000 group.byte 0x0++0x0 line.byte 0x0 "DOCR,DOC Control Register" bitfld.byte 0x0 4.--6. "DCSEL,Detection Condition Select" "0: Setting prohibited,1: Match (DODSR0 = DODIR),?,?,?,?,?,?" bitfld.byte 0x0 3. "DOBW,Data Operation Bit Width Select" "0: 16-bit,1: 32-bit" bitfld.byte 0x0 0.--1. "OMS,Operating Mode Select" "0: Data comparison mode,1: Data addition mode,?,?" rgroup.byte 0x4++0x0 line.byte 0x0 "DOSR,DOC Flag Status Register" bitfld.byte 0x0 0. "DOPCF,Data Operation Circuit Flag" "0,1" wgroup.byte 0x8++0x0 line.byte 0x0 "DOSCR,DOC Flag Status Clear Register" bitfld.byte 0x0 0. "DOPCFCL,DOPCF Clear" "0: Maintains the DOPCF flag state.,1: Clears the DOPCF flag." group.long 0xC++0xB line.long 0x0 "DODIR,DOC Data Input Register" line.long 0x4 "DODSR0,DOC Data Setting Register 0" line.long 0x8 "DODSR1,DOC Data Setting Register 1" tree.end tree.end tree "DRW (2D Drawing Engine)" base ad:0x0 tree "DRW" base ad:0x40344000 wgroup.long 0x0++0x3 line.long 0x0 "CONTROL,Geometry Control Register" bitfld.long 0x0 23. "SPANSTORE,Spanstore" "0: Disable,1: Enable. Next line span start is always equal to.." bitfld.long 0x0 22. "SPANABORT,Spanabort" "0: Disable,1: Enable." newline bitfld.long 0x0 21. "UNIONCD,Combine Outputs C and D as Union" "0: Select minimum/intersect between limiters C and D,1: Select maximum/union between limiters C and D." bitfld.long 0x0 20. "UNIONAB,Combine Outputs A and B as Union" "0: Select minimum/intersect between limiters A and B.,1: Select maximum/union between limiters A and B." newline bitfld.long 0x0 19. "UNION56,Combine Limiters 5 and 6 as Union" "0: Select minimum/intersect between limiters 5 and 6,1: Select maximum/union between limiters 5 and 6." bitfld.long 0x0 18. "UNION34,Combine Limiters 3 and 4 as Union" "0: Select minimum/intersect between limiters 3 and 4,1: Select maximum/union between limiters 3 and 4." newline bitfld.long 0x0 17. "UNION12,Combine Limiters 1 and 2 as Union" "0: Select minimum/intersect between limiters 1 and 2,1: Select maximum/union between limiters 1 and 2." bitfld.long 0x0 16. "BAND2ENABLE,Enable Band Post Process for Limiter 2" "0: Disable,1: Enable." newline bitfld.long 0x0 15. "BAND1ENABLE,Enable Band Post Process for Limiter 1" "0: Disable,1: Enable." bitfld.long 0x0 14. "LIM6THRESHOLD,Enable Limiter 6 Threshold Mode" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "LIM5THRESHOLD,Enable Limiter 5 Threshold Mode" "0: Disable,1: Enable" bitfld.long 0x0 12. "LIM4THRESHOLD,Enable Limiter 4 Threshold Mode" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "LIM3THRESHOLD,Enable Limiter 3 Threshold Mode" "0: Disable,1: Enable" bitfld.long 0x0 10. "LIM2THRESHOLD,Enable Limiter 2 Threshold Mode" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "LIM1THRESHOLD,Enable Limiter 1 Threshold Mode" "0: Disable,1: Enable" bitfld.long 0x0 8. "QUAD3ENABLE,Enable Quadratic Coupling of Limiters 5 and 6" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "QUAD2ENABLE,Enable Quadratic Coupling of Limiters 3 and 4" "0: Disable,1: Enable" bitfld.long 0x0 6. "QUAD1ENABLE,Enable Quadratic Coupling of Limiters 1 and 2" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "LIM6ENABLE,Enable Limiter 6" "0: Disable,1: Enable" bitfld.long 0x0 4. "LIM5ENABLE,Enable Limiter 5" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "LIM4ENABLE,Enable Limiter 4" "0: Disable,1: Enable" bitfld.long 0x0 2. "LIM3ENABLE,Enable Limiter 3" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "LIM2ENABLE,Enable Limiter 2" "0: Disable,1: Enable" bitfld.long 0x0 0. "LIM1ENABLE,Enable Limiter 1" "0: Disable,1: Enable" rgroup.long 0x0++0x3 line.long 0x0 "STATUS,Status Control Register" bitfld.long 0x0 10. "BUSERRMDL,Display List Bus Error Interrupt Triggered" "0: No display list bus error occurred or interrupt..,1: Display list bus error interrupt triggered." bitfld.long 0x0 9. "BUSERRMTXMRL,Texture Bus Error Interrupt Triggered" "0: No texture bus error occurred or interrupt..,1: Texture bus error interrupt triggered." newline bitfld.long 0x0 8. "BUSERRMFB,Framebuffer Bus Error Interrupt Triggered" "0: No framebuffer bus error occurred or interrupt..,1: Framebuffer bus error interrupt triggered." bitfld.long 0x0 6. "BUSIRQ,Bus Error Interrupt Triggered" "0: No bus error occurred or interrupt disabled,1: Bus error interrupt triggered." newline bitfld.long 0x0 5. "DLISTIRQ,Display List Interrupt Triggered" "0: Display list not finished or interrupt disabled,1: Display list finished interrupt triggered." bitfld.long 0x0 4. "ENUMIRQ,Enumeration Interrupt Triggered" "0: Enumeration not finished or interrupt disabled,1: Enumeration finished interrupt triggered." newline bitfld.long 0x0 3. "DLISTACTIVE,Display List Reader Status" "0: Display list reader is idle,1: Display list reader is busy and no direct write.." bitfld.long 0x0 2. "CACHEDIRTY,Framebuffer Cache Status" "0: Framebuffer cache is not dirty,1: Framebuffer cache is dirty and frame should not.." newline bitfld.long 0x0 1. "BUSYWRITE,Framebuffer Writeback Status" "0: Framebuffer writeback finished,1: Framebuffer writeback busy framebuffer type.." bitfld.long 0x0 0. "BUSYENUM,Enumeration Unit Status" "0: Enumeration unit idle,1: Enumeration unit is busy new primitive cannot be.." wgroup.long 0x4++0x3 line.long 0x0 "CONTROL2,Surface Control Register" bitfld.long 0x0 30.--31. "RLEPIXELWIDTH,Texel Width for RLE Unit" "0: 1 byte per texel,1: 2 bytes per texel,?,?" bitfld.long 0x0 29. "BDIA,Blend Destination Factor Inverted in Alpha Channel" "0: Use blend factor as specified through BDFA,1: Invert destination blend factor (1-x)." newline bitfld.long 0x0 28. "BSIA,Blend Source Factor Inverted in Alpha Channel" "0: Use blend factor as specified through BSFA,1: Invert blend source factor (1-x)." bitfld.long 0x0 27. "CLUTFORMAT,CLUT Format" "0: Format CLUT as ARGB (8888),1: Format CLUT as RGB (565)." newline bitfld.long 0x0 26. "COLKEYENABLE,Color Keying Enable" "0: Disable color keying,1: Enable color keying." bitfld.long 0x0 25. "CLUTENABLE,CLUT Enable" "0: Disable CLUT,1: Enable CLUT" newline bitfld.long 0x0 24. "RLEENABLE,RLE Enable" "0: Disable RLE,1: Enable RLE." bitfld.long 0x0 22.--23. "WRITEALPHA,Writeback Alpha Source for Framebuffer" "0: (USEACB = 0) Use alpha from color 2 (USEACB = 0)..,1: (USEACB = 0) Use source alpha (pixel coverage)..,?,?" newline bitfld.long 0x0 20.--21. "WRITEFORMAT,Writeback Framebuffer Format" "0,1,2,3" bitfld.long 0x0 18.--19. "READFORMAT_L,Texture Format Descriptor" "0,1,2,3" newline bitfld.long 0x0 17. "TEXTUREFILTERY,Linear Filtering on Texture V Axis" "0: No filtering on texture V axis,1: Linear filtering on texture V axis." bitfld.long 0x0 16. "TEXTUREFILTERX,Linear Filtering on Texture U Axis" "0: No filtering on texture U axis,1: Linear filtering on texture U axis." newline bitfld.long 0x0 15. "TEXTURECLAMPY,Calculating V Limiter Outside Used Texture" "0: Texture wrap mode: Integer part of the..,1: Texture clamp mode: Texture color at the border.." bitfld.long 0x0 14. "TEXTURECLAMPX,Calculating U Limiter Outside Used Texture" "0: Texture wrap mode: Integer part of the..,1: Texture clamp mode: Texture color at the border.." newline bitfld.long 0x0 13. "BC2,Blend color 2" "0: Use pixel from framebuffer as destination (DST),1: Use color 2 as destination (DST)." bitfld.long 0x0 12. "BDI,Blend Destination Factor Inverted" "0: Use blend factor as specified through BDF,1: Invert blend destination factor (1-x)." newline bitfld.long 0x0 11. "BSI,Blend Source Factor Inverted" "0: Use blend factor as specified through BSF,1: Invert blend source factor (1-x)." bitfld.long 0x0 10. "BDF,Blend Destination Factor" "0: Use 1.0 as blend destination factor,1: Use alpha as blend destination factor." newline bitfld.long 0x0 9. "BSF,Blend Source Factor" "0: Use 1.0 as blend source factor,1: Use alpha as blend source factor." bitfld.long 0x0 8. "WRITEFORMAT2,Writeback Framebuffer Format" "0,1" newline bitfld.long 0x0 7. "BDFA,Blend Destination Factor for Alpha Channel" "0: Use 1.0 as blend destination factor for alpha..,1: Use alpha as blend destination factor for alpha.." bitfld.long 0x0 6. "BSFA,Blend Source Factor for Alpha Channel" "0: Use 1.0 as blend source factor for alpha channel,1: Use alpha as blend source factor for alpha.." newline bitfld.long 0x0 4.--5. "READFORMAT_H,Texture Format Descriptor" "0,1,2,3" bitfld.long 0x0 3. "USEACB,Alpha Blend Mode" "0: Use WRITEALPHA[1:0] mode,1: Use full alpha channel blending mode." newline bitfld.long 0x0 2. "PATTERNSOURCEL5,Limiter 5 Enable for Pattern Index" "0,1" bitfld.long 0x0 1. "TEXTUREENABLE,Texture Enable for Pixel Source" "0: Disable texture,1: Enable texture." newline bitfld.long 0x0 0. "PATTERNENABLE,Pattern Color Enable for Pixel Source" "0: Disable pattern,1: Enable pattern." rgroup.long 0x4++0x3 line.long 0x0 "HWREVISION,Hardware Version and Feature Set ID Register" bitfld.long 0x0 27. "ACBLEND,Alpha Channel Blending Available" "0: Full alpha channel blending is not available,1: Full alpha channel blending is available" bitfld.long 0x0 25. "COLORKEY,Color Key Available" "0: No color key,1: Color key is available" newline bitfld.long 0x0 24. "TEXCLUT256,Texture CLUT size" "0: Texture CLUT size is 16 entries,1: Texture CLUT size is 256 entries" bitfld.long 0x0 23. "RLEUNIT,RLE Unit Available" "0: No RLE unit,1: RLE unit is available" newline bitfld.long 0x0 21. "TEXCLUT,Texture CLUT Available" "0: No texture CLUT,1: Texture CLUT is available" bitfld.long 0x0 20. "PERFCOUNT,Two Performance Counter Available" "0: No performance counter,1: Tow performance counters available" newline bitfld.long 0x0 19. "TXCACHE,Texture Cache Available" "0: No texture cache,1: Texture cache is available" bitfld.long 0x0 18. "FBCACHE,Framebuffer Cache Available" "0: No framebuffer cache,1: Framebuffer cache is available" newline bitfld.long 0x0 17. "DLR,Display List Reader Available" "0: No display list reader,1: Display list reader is available" hexmask.long.word 0x0 0.--11. 1. "REV,Revision Number of DRW is stored." repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x10)++0x3 line.long 0x0 "L$1START,Limiter %s Start Value Register (n = 1 to 6)" hexmask.long 0x0 0.--31. 1. "LSTART,Start Value of the nth Limiter" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x28)++0x3 line.long 0x0 "L$1XADD,Limiter %s X-Axis Increment Register(n = 1 to 6)" hexmask.long 0x0 0.--31. 1. "LXADD,X-Axis Increment" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x40)++0x3 line.long 0x0 "L$1YADD,Limiter %s Y-Axis Increment Register(n = 1 to 6)" hexmask.long 0x0 0.--31. 1. "LYADD,Y-Axis Increment" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x58)++0x3 line.long 0x0 "L$1BAND,Limiter m Band Width Parameter Register(n = 1. 2)" hexmask.long 0x0 0.--31. 1. "LBAND,Limiter m Band Width Parameter" repeat.end wgroup.long 0x64++0x7 line.long 0x0 "COLOR1,Base Color Register" hexmask.long.byte 0x0 24.--31. 1. "COLOR1A,Alpha Channel of Color 1" hexmask.long.byte 0x0 16.--23. 1. "COLOR1R,Red Channel of Color 1" newline hexmask.long.byte 0x0 8.--15. 1. "COLOR1G,Green Channel of Color 1" hexmask.long.byte 0x0 0.--7. 1. "COLOR1B,Blue Channel of Color 1" line.long 0x4 "COLOR2,Secondary Color Register" hexmask.long.byte 0x4 24.--31. 1. "COLOR2A,Alpha Channel of Color 2" hexmask.long.byte 0x4 16.--23. 1. "COLOR2R,Red Channel of Color 2" newline hexmask.long.byte 0x4 8.--15. 1. "COLOR2G,Green Channel of Color 2" hexmask.long.byte 0x4 0.--7. 1. "COLOR2B,Blue Channel of Color 2" wgroup.long 0x74++0xF line.long 0x0 "PATTERN,Pattern Register" hexmask.long.byte 0x0 0.--7. 1. "PATTERN,Bitmap of the Pattern" line.long 0x4 "SIZE,Bounding Box Dimension Register" hexmask.long.word 0x4 16.--31. 1. "SIZEY,Bounding Box Height" hexmask.long.word 0x4 0.--15. 1. "SIZEX,Bounding Box Width" line.long 0x8 "PITCH,Framebuffer Pitch And Spanstore Delay Register" hexmask.long.word 0x8 16.--31. 1. "SSD,Spanstore Delay" hexmask.long.word 0x8 0.--15. 1. "PITCH,Pitch of the Framebuffer" line.long 0xC "ORIGIN,Framebuffer Base Address Register" hexmask.long 0xC 0.--31. 1. "ORIGIN,Address of the First Pixel in Framebuffer" wgroup.long 0x90++0x1F line.long 0x0 "LUSTART,U Limiter Start Value Register" hexmask.long 0x0 0.--31. 1. "LUSTART,U Limiter Start Value" line.long 0x4 "LUXADD,U Limiter X-Axis Increment Register" hexmask.long 0x4 0.--31. 1. "LUXADD,U Limiter X-Axis Increment" line.long 0x8 "LUYADD,U Limiter Y-Axis Increment Register" hexmask.long 0x8 0.--31. 1. "LUYADD,U Limiter Y-Axis Increment" line.long 0xC "LVSTARTI,V Limiter Start Value Integer Part Register" bitfld.long 0xC 0. "LVSTARTI,V Limiter Start Value Integer Part" "0,1" line.long 0x10 "LVSTARTF,V Limiter Start Value Fractional Part Register" hexmask.long.word 0x10 0.--15. 1. "LVSTARTF,V Limiter Start Value Fractional Part" line.long 0x14 "LVXADDI,V Limiter X-Axis Increment Integer Part Register" hexmask.long 0x14 0.--31. 1. "LVXADDI,V Limiter X-Axis Increment Integer Part" line.long 0x18 "LVYADDI,V Limiter Y-Axis Increment Integer Part Register" hexmask.long 0x18 0.--31. 1. "LVYADDI,V Limiter Y-Axis Increment Integer Part" line.long 0x1C "LVYXADDF,V Limiter Increment Fractional Parts Register" hexmask.long.word 0x1C 16.--31. 1. "LVYADDF,V Limiter Y-Axis Increment Fractional Part" hexmask.long.word 0x1C 0.--15. 1. "LVXADDF,V Limiter X-Axis Increment Fractional Part" wgroup.long 0xB4++0x17 line.long 0x0 "TEXPITCH,Texels Per Texture Line Register" hexmask.long 0x0 0.--31. 1. "TEXPITCH,Texels Per Texture Line" line.long 0x4 "TEXMASK,Texture Size or Texture Address Mask Register" hexmask.long.tbyte 0x4 11.--31. 1. "TEXVMASK,V Mask in Texture Mode" hexmask.long.word 0x4 0.--10. 1. "TEXUMASK,U Mask in Texture Mode" line.long 0x8 "TEXORIGIN,Texture Base Address Register" hexmask.long 0x8 0.--31. 1. "TEXORIGIN,Texture Base Address" line.long 0xC "IRQCTL,Interrupt Control Register" bitfld.long 0xC 5. "BUSIRQCLR,Clear BUSIRQ" "0: Do not clear BUSIRQ bus error interrupt,1: Clear BUSIRQ bus error interrupt." bitfld.long 0xC 4. "BUSIRQEN,BUSIRQ Interrupt Mask Enable" "0: Disable (mask) BUSIRQ bus error interrupt,1: Enable (unmask) BUSIRQ bus error interrupt." newline bitfld.long 0xC 3. "DLISTIRQCLR,Clear DLISTIRQ" "0: Do not clear DLISTIRQ display list interrupt,1: Clear DLISTIRQ display list interrupt." bitfld.long 0xC 2. "ENUMIRQCLR,Clear ENUMIRQ" "0: Do not clear ENUMIRQ enumeration interrupt,1: Clear ENUMIRQ enumeration interrupt." newline bitfld.long 0xC 1. "DLISTIRQEN,DLISTIRQ Interrupt Mask Enable" "0: Disable (mask) DLISTIRQ display list interrupt,1: Enable (unmask) DLISTIRQ display list interrupt." bitfld.long 0xC 0. "ENUMIRQEN,ENUMIRQ Interrupt Mask Enable" "0: Disable (mask) ENUMIRQ enumeration interrupt,1: Enable (unmask) ENUMIRQ enumeration interrupt." line.long 0x10 "CACHECTL,Cache Control Register" bitfld.long 0x10 3. "CFLUSHTX,Flush Texture Cache" "0: Do not flush the texture cache,1: Flush the texture cache." bitfld.long 0x10 2. "CENABLETX,Texture Cache Enable" "0: Disable the texture cache,1: Enable the texture cache." newline bitfld.long 0x10 1. "CFLUSHFX,Flush Framebuffer Cache" "0: Do not flush the framebuffer cache,1: Flush the framebuffer cache." bitfld.long 0x10 0. "CENABLEFX,Framebuffer Cache Enable" "0: Disable the framebuffer cache,1: Enable the framebuffer cache." line.long 0x14 "DLISTSTART,Display List Start Address Register" hexmask.long 0x14 0.--31. 1. "DLISTSTART,Display List Start Address" group.long 0xCC++0x3 line.long 0x0 "PERFCOUNT1,Performance Counter 1" hexmask.long 0x0 0.--31. 1. "PERFCOUNT,Performance Counter k Value" group.long 0xCC++0x3 line.long 0x0 "PERFCOUNT2,Performance Counter 2" hexmask.long 0x0 0.--31. 1. "PERFCOUNT,Performance Counter k Value" wgroup.long 0xD4++0x3 line.long 0x0 "PERFTRIGGER,Performance Counters Control Register" hexmask.long.word 0x0 16.--31. 1. "PERFTRIGGER2,Trigger of Performance Counter 2" hexmask.long.word 0x0 0.--15. 1. "PERFTRIGGER1,Trigger of Performance Counter 1" wgroup.long 0xDC++0xF line.long 0x0 "TEXCLADDR,CLUT Start Address Register" hexmask.long.byte 0x0 0.--7. 1. "CLADDR,Texture CLUT Start Address" line.long 0x4 "TEXCLDATA,CLUT Data Register" hexmask.long 0x4 0.--31. 1. "CLDATA,Texture CLUT Data" line.long 0x8 "TEXCLOFFSET,CLUT Offset Register" hexmask.long.byte 0x8 0.--7. 1. "CLOFFSET,Texture CLUT Offset" line.long 0xC "COLKEY,Color Key Register" hexmask.long.byte 0xC 16.--23. 1. "COLKEYR,Red Channel of Color Key" hexmask.long.byte 0xC 8.--15. 1. "COLKEYG,Green Channel of Color Key" newline hexmask.long.byte 0xC 0.--7. 1. "COLKEYB,Blue Channel of Color Key" tree.end tree "DRW_NS" base ad:0x50344000 wgroup.long 0x0++0x3 line.long 0x0 "CONTROL,Geometry Control Register" bitfld.long 0x0 23. "SPANSTORE,Spanstore" "0: Disable,1: Enable. Next line span start is always equal to.." bitfld.long 0x0 22. "SPANABORT,Spanabort" "0: Disable,1: Enable." newline bitfld.long 0x0 21. "UNIONCD,Combine Outputs C and D as Union" "0: Select minimum/intersect between limiters C and D,1: Select maximum/union between limiters C and D." bitfld.long 0x0 20. "UNIONAB,Combine Outputs A and B as Union" "0: Select minimum/intersect between limiters A and B.,1: Select maximum/union between limiters A and B." newline bitfld.long 0x0 19. "UNION56,Combine Limiters 5 and 6 as Union" "0: Select minimum/intersect between limiters 5 and 6,1: Select maximum/union between limiters 5 and 6." bitfld.long 0x0 18. "UNION34,Combine Limiters 3 and 4 as Union" "0: Select minimum/intersect between limiters 3 and 4,1: Select maximum/union between limiters 3 and 4." newline bitfld.long 0x0 17. "UNION12,Combine Limiters 1 and 2 as Union" "0: Select minimum/intersect between limiters 1 and 2,1: Select maximum/union between limiters 1 and 2." bitfld.long 0x0 16. "BAND2ENABLE,Enable Band Post Process for Limiter 2" "0: Disable,1: Enable." newline bitfld.long 0x0 15. "BAND1ENABLE,Enable Band Post Process for Limiter 1" "0: Disable,1: Enable." bitfld.long 0x0 14. "LIM6THRESHOLD,Enable Limiter 6 Threshold Mode" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "LIM5THRESHOLD,Enable Limiter 5 Threshold Mode" "0: Disable,1: Enable" bitfld.long 0x0 12. "LIM4THRESHOLD,Enable Limiter 4 Threshold Mode" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "LIM3THRESHOLD,Enable Limiter 3 Threshold Mode" "0: Disable,1: Enable" bitfld.long 0x0 10. "LIM2THRESHOLD,Enable Limiter 2 Threshold Mode" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "LIM1THRESHOLD,Enable Limiter 1 Threshold Mode" "0: Disable,1: Enable" bitfld.long 0x0 8. "QUAD3ENABLE,Enable Quadratic Coupling of Limiters 5 and 6" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "QUAD2ENABLE,Enable Quadratic Coupling of Limiters 3 and 4" "0: Disable,1: Enable" bitfld.long 0x0 6. "QUAD1ENABLE,Enable Quadratic Coupling of Limiters 1 and 2" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "LIM6ENABLE,Enable Limiter 6" "0: Disable,1: Enable" bitfld.long 0x0 4. "LIM5ENABLE,Enable Limiter 5" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "LIM4ENABLE,Enable Limiter 4" "0: Disable,1: Enable" bitfld.long 0x0 2. "LIM3ENABLE,Enable Limiter 3" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "LIM2ENABLE,Enable Limiter 2" "0: Disable,1: Enable" bitfld.long 0x0 0. "LIM1ENABLE,Enable Limiter 1" "0: Disable,1: Enable" rgroup.long 0x0++0x3 line.long 0x0 "STATUS,Status Control Register" bitfld.long 0x0 10. "BUSERRMDL,Display List Bus Error Interrupt Triggered" "0: No display list bus error occurred or interrupt..,1: Display list bus error interrupt triggered." bitfld.long 0x0 9. "BUSERRMTXMRL,Texture Bus Error Interrupt Triggered" "0: No texture bus error occurred or interrupt..,1: Texture bus error interrupt triggered." newline bitfld.long 0x0 8. "BUSERRMFB,Framebuffer Bus Error Interrupt Triggered" "0: No framebuffer bus error occurred or interrupt..,1: Framebuffer bus error interrupt triggered." bitfld.long 0x0 6. "BUSIRQ,Bus Error Interrupt Triggered" "0: No bus error occurred or interrupt disabled,1: Bus error interrupt triggered." newline bitfld.long 0x0 5. "DLISTIRQ,Display List Interrupt Triggered" "0: Display list not finished or interrupt disabled,1: Display list finished interrupt triggered." bitfld.long 0x0 4. "ENUMIRQ,Enumeration Interrupt Triggered" "0: Enumeration not finished or interrupt disabled,1: Enumeration finished interrupt triggered." newline bitfld.long 0x0 3. "DLISTACTIVE,Display List Reader Status" "0: Display list reader is idle,1: Display list reader is busy and no direct write.." bitfld.long 0x0 2. "CACHEDIRTY,Framebuffer Cache Status" "0: Framebuffer cache is not dirty,1: Framebuffer cache is dirty and frame should not.." newline bitfld.long 0x0 1. "BUSYWRITE,Framebuffer Writeback Status" "0: Framebuffer writeback finished,1: Framebuffer writeback busy framebuffer type.." bitfld.long 0x0 0. "BUSYENUM,Enumeration Unit Status" "0: Enumeration unit idle,1: Enumeration unit is busy new primitive cannot be.." wgroup.long 0x4++0x3 line.long 0x0 "CONTROL2,Surface Control Register" bitfld.long 0x0 30.--31. "RLEPIXELWIDTH,Texel Width for RLE Unit" "0: 1 byte per texel,1: 2 bytes per texel,?,?" bitfld.long 0x0 29. "BDIA,Blend Destination Factor Inverted in Alpha Channel" "0: Use blend factor as specified through BDFA,1: Invert destination blend factor (1-x)." newline bitfld.long 0x0 28. "BSIA,Blend Source Factor Inverted in Alpha Channel" "0: Use blend factor as specified through BSFA,1: Invert blend source factor (1-x)." bitfld.long 0x0 27. "CLUTFORMAT,CLUT Format" "0: Format CLUT as ARGB (8888),1: Format CLUT as RGB (565)." newline bitfld.long 0x0 26. "COLKEYENABLE,Color Keying Enable" "0: Disable color keying,1: Enable color keying." bitfld.long 0x0 25. "CLUTENABLE,CLUT Enable" "0: Disable CLUT,1: Enable CLUT" newline bitfld.long 0x0 24. "RLEENABLE,RLE Enable" "0: Disable RLE,1: Enable RLE." bitfld.long 0x0 22.--23. "WRITEALPHA,Writeback Alpha Source for Framebuffer" "0: (USEACB = 0) Use alpha from color 2 (USEACB = 0)..,1: (USEACB = 0) Use source alpha (pixel coverage)..,?,?" newline bitfld.long 0x0 20.--21. "WRITEFORMAT,Writeback Framebuffer Format" "0,1,2,3" bitfld.long 0x0 18.--19. "READFORMAT_L,Texture Format Descriptor" "0,1,2,3" newline bitfld.long 0x0 17. "TEXTUREFILTERY,Linear Filtering on Texture V Axis" "0: No filtering on texture V axis,1: Linear filtering on texture V axis." bitfld.long 0x0 16. "TEXTUREFILTERX,Linear Filtering on Texture U Axis" "0: No filtering on texture U axis,1: Linear filtering on texture U axis." newline bitfld.long 0x0 15. "TEXTURECLAMPY,Calculating V Limiter Outside Used Texture" "0: Texture wrap mode: Integer part of the..,1: Texture clamp mode: Texture color at the border.." bitfld.long 0x0 14. "TEXTURECLAMPX,Calculating U Limiter Outside Used Texture" "0: Texture wrap mode: Integer part of the..,1: Texture clamp mode: Texture color at the border.." newline bitfld.long 0x0 13. "BC2,Blend color 2" "0: Use pixel from framebuffer as destination (DST),1: Use color 2 as destination (DST)." bitfld.long 0x0 12. "BDI,Blend Destination Factor Inverted" "0: Use blend factor as specified through BDF,1: Invert blend destination factor (1-x)." newline bitfld.long 0x0 11. "BSI,Blend Source Factor Inverted" "0: Use blend factor as specified through BSF,1: Invert blend source factor (1-x)." bitfld.long 0x0 10. "BDF,Blend Destination Factor" "0: Use 1.0 as blend destination factor,1: Use alpha as blend destination factor." newline bitfld.long 0x0 9. "BSF,Blend Source Factor" "0: Use 1.0 as blend source factor,1: Use alpha as blend source factor." bitfld.long 0x0 8. "WRITEFORMAT2,Writeback Framebuffer Format" "0,1" newline bitfld.long 0x0 7. "BDFA,Blend Destination Factor for Alpha Channel" "0: Use 1.0 as blend destination factor for alpha..,1: Use alpha as blend destination factor for alpha.." bitfld.long 0x0 6. "BSFA,Blend Source Factor for Alpha Channel" "0: Use 1.0 as blend source factor for alpha channel,1: Use alpha as blend source factor for alpha.." newline bitfld.long 0x0 4.--5. "READFORMAT_H,Texture Format Descriptor" "0,1,2,3" bitfld.long 0x0 3. "USEACB,Alpha Blend Mode" "0: Use WRITEALPHA[1:0] mode,1: Use full alpha channel blending mode." newline bitfld.long 0x0 2. "PATTERNSOURCEL5,Limiter 5 Enable for Pattern Index" "0,1" bitfld.long 0x0 1. "TEXTUREENABLE,Texture Enable for Pixel Source" "0: Disable texture,1: Enable texture." newline bitfld.long 0x0 0. "PATTERNENABLE,Pattern Color Enable for Pixel Source" "0: Disable pattern,1: Enable pattern." rgroup.long 0x4++0x3 line.long 0x0 "HWREVISION,Hardware Version and Feature Set ID Register" bitfld.long 0x0 27. "ACBLEND,Alpha Channel Blending Available" "0: Full alpha channel blending is not available,1: Full alpha channel blending is available" bitfld.long 0x0 25. "COLORKEY,Color Key Available" "0: No color key,1: Color key is available" newline bitfld.long 0x0 24. "TEXCLUT256,Texture CLUT size" "0: Texture CLUT size is 16 entries,1: Texture CLUT size is 256 entries" bitfld.long 0x0 23. "RLEUNIT,RLE Unit Available" "0: No RLE unit,1: RLE unit is available" newline bitfld.long 0x0 21. "TEXCLUT,Texture CLUT Available" "0: No texture CLUT,1: Texture CLUT is available" bitfld.long 0x0 20. "PERFCOUNT,Two Performance Counter Available" "0: No performance counter,1: Tow performance counters available" newline bitfld.long 0x0 19. "TXCACHE,Texture Cache Available" "0: No texture cache,1: Texture cache is available" bitfld.long 0x0 18. "FBCACHE,Framebuffer Cache Available" "0: No framebuffer cache,1: Framebuffer cache is available" newline bitfld.long 0x0 17. "DLR,Display List Reader Available" "0: No display list reader,1: Display list reader is available" hexmask.long.word 0x0 0.--11. 1. "REV,Revision Number of DRW is stored." repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x10)++0x3 line.long 0x0 "L$1START,Limiter %s Start Value Register (n = 1 to 6)" hexmask.long 0x0 0.--31. 1. "LSTART,Start Value of the nth Limiter" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x28)++0x3 line.long 0x0 "L$1XADD,Limiter %s X-Axis Increment Register(n = 1 to 6)" hexmask.long 0x0 0.--31. 1. "LXADD,X-Axis Increment" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x40)++0x3 line.long 0x0 "L$1YADD,Limiter %s Y-Axis Increment Register(n = 1 to 6)" hexmask.long 0x0 0.--31. 1. "LYADD,Y-Axis Increment" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x58)++0x3 line.long 0x0 "L$1BAND,Limiter m Band Width Parameter Register(n = 1. 2)" hexmask.long 0x0 0.--31. 1. "LBAND,Limiter m Band Width Parameter" repeat.end wgroup.long 0x64++0x7 line.long 0x0 "COLOR1,Base Color Register" hexmask.long.byte 0x0 24.--31. 1. "COLOR1A,Alpha Channel of Color 1" hexmask.long.byte 0x0 16.--23. 1. "COLOR1R,Red Channel of Color 1" newline hexmask.long.byte 0x0 8.--15. 1. "COLOR1G,Green Channel of Color 1" hexmask.long.byte 0x0 0.--7. 1. "COLOR1B,Blue Channel of Color 1" line.long 0x4 "COLOR2,Secondary Color Register" hexmask.long.byte 0x4 24.--31. 1. "COLOR2A,Alpha Channel of Color 2" hexmask.long.byte 0x4 16.--23. 1. "COLOR2R,Red Channel of Color 2" newline hexmask.long.byte 0x4 8.--15. 1. "COLOR2G,Green Channel of Color 2" hexmask.long.byte 0x4 0.--7. 1. "COLOR2B,Blue Channel of Color 2" wgroup.long 0x74++0xF line.long 0x0 "PATTERN,Pattern Register" hexmask.long.byte 0x0 0.--7. 1. "PATTERN,Bitmap of the Pattern" line.long 0x4 "SIZE,Bounding Box Dimension Register" hexmask.long.word 0x4 16.--31. 1. "SIZEY,Bounding Box Height" hexmask.long.word 0x4 0.--15. 1. "SIZEX,Bounding Box Width" line.long 0x8 "PITCH,Framebuffer Pitch And Spanstore Delay Register" hexmask.long.word 0x8 16.--31. 1. "SSD,Spanstore Delay" hexmask.long.word 0x8 0.--15. 1. "PITCH,Pitch of the Framebuffer" line.long 0xC "ORIGIN,Framebuffer Base Address Register" hexmask.long 0xC 0.--31. 1. "ORIGIN,Address of the First Pixel in Framebuffer" wgroup.long 0x90++0x1F line.long 0x0 "LUSTART,U Limiter Start Value Register" hexmask.long 0x0 0.--31. 1. "LUSTART,U Limiter Start Value" line.long 0x4 "LUXADD,U Limiter X-Axis Increment Register" hexmask.long 0x4 0.--31. 1. "LUXADD,U Limiter X-Axis Increment" line.long 0x8 "LUYADD,U Limiter Y-Axis Increment Register" hexmask.long 0x8 0.--31. 1. "LUYADD,U Limiter Y-Axis Increment" line.long 0xC "LVSTARTI,V Limiter Start Value Integer Part Register" bitfld.long 0xC 0. "LVSTARTI,V Limiter Start Value Integer Part" "0,1" line.long 0x10 "LVSTARTF,V Limiter Start Value Fractional Part Register" hexmask.long.word 0x10 0.--15. 1. "LVSTARTF,V Limiter Start Value Fractional Part" line.long 0x14 "LVXADDI,V Limiter X-Axis Increment Integer Part Register" hexmask.long 0x14 0.--31. 1. "LVXADDI,V Limiter X-Axis Increment Integer Part" line.long 0x18 "LVYADDI,V Limiter Y-Axis Increment Integer Part Register" hexmask.long 0x18 0.--31. 1. "LVYADDI,V Limiter Y-Axis Increment Integer Part" line.long 0x1C "LVYXADDF,V Limiter Increment Fractional Parts Register" hexmask.long.word 0x1C 16.--31. 1. "LVYADDF,V Limiter Y-Axis Increment Fractional Part" hexmask.long.word 0x1C 0.--15. 1. "LVXADDF,V Limiter X-Axis Increment Fractional Part" wgroup.long 0xB4++0x17 line.long 0x0 "TEXPITCH,Texels Per Texture Line Register" hexmask.long 0x0 0.--31. 1. "TEXPITCH,Texels Per Texture Line" line.long 0x4 "TEXMASK,Texture Size or Texture Address Mask Register" hexmask.long.tbyte 0x4 11.--31. 1. "TEXVMASK,V Mask in Texture Mode" hexmask.long.word 0x4 0.--10. 1. "TEXUMASK,U Mask in Texture Mode" line.long 0x8 "TEXORIGIN,Texture Base Address Register" hexmask.long 0x8 0.--31. 1. "TEXORIGIN,Texture Base Address" line.long 0xC "IRQCTL,Interrupt Control Register" bitfld.long 0xC 5. "BUSIRQCLR,Clear BUSIRQ" "0: Do not clear BUSIRQ bus error interrupt,1: Clear BUSIRQ bus error interrupt." bitfld.long 0xC 4. "BUSIRQEN,BUSIRQ Interrupt Mask Enable" "0: Disable (mask) BUSIRQ bus error interrupt,1: Enable (unmask) BUSIRQ bus error interrupt." newline bitfld.long 0xC 3. "DLISTIRQCLR,Clear DLISTIRQ" "0: Do not clear DLISTIRQ display list interrupt,1: Clear DLISTIRQ display list interrupt." bitfld.long 0xC 2. "ENUMIRQCLR,Clear ENUMIRQ" "0: Do not clear ENUMIRQ enumeration interrupt,1: Clear ENUMIRQ enumeration interrupt." newline bitfld.long 0xC 1. "DLISTIRQEN,DLISTIRQ Interrupt Mask Enable" "0: Disable (mask) DLISTIRQ display list interrupt,1: Enable (unmask) DLISTIRQ display list interrupt." bitfld.long 0xC 0. "ENUMIRQEN,ENUMIRQ Interrupt Mask Enable" "0: Disable (mask) ENUMIRQ enumeration interrupt,1: Enable (unmask) ENUMIRQ enumeration interrupt." line.long 0x10 "CACHECTL,Cache Control Register" bitfld.long 0x10 3. "CFLUSHTX,Flush Texture Cache" "0: Do not flush the texture cache,1: Flush the texture cache." bitfld.long 0x10 2. "CENABLETX,Texture Cache Enable" "0: Disable the texture cache,1: Enable the texture cache." newline bitfld.long 0x10 1. "CFLUSHFX,Flush Framebuffer Cache" "0: Do not flush the framebuffer cache,1: Flush the framebuffer cache." bitfld.long 0x10 0. "CENABLEFX,Framebuffer Cache Enable" "0: Disable the framebuffer cache,1: Enable the framebuffer cache." line.long 0x14 "DLISTSTART,Display List Start Address Register" hexmask.long 0x14 0.--31. 1. "DLISTSTART,Display List Start Address" group.long 0xCC++0x3 line.long 0x0 "PERFCOUNT1,Performance Counter 1" hexmask.long 0x0 0.--31. 1. "PERFCOUNT,Performance Counter k Value" group.long 0xCC++0x3 line.long 0x0 "PERFCOUNT2,Performance Counter 2" hexmask.long 0x0 0.--31. 1. "PERFCOUNT,Performance Counter k Value" wgroup.long 0xD4++0x3 line.long 0x0 "PERFTRIGGER,Performance Counters Control Register" hexmask.long.word 0x0 16.--31. 1. "PERFTRIGGER2,Trigger of Performance Counter 2" hexmask.long.word 0x0 0.--15. 1. "PERFTRIGGER1,Trigger of Performance Counter 1" wgroup.long 0xDC++0xF line.long 0x0 "TEXCLADDR,CLUT Start Address Register" hexmask.long.byte 0x0 0.--7. 1. "CLADDR,Texture CLUT Start Address" line.long 0x4 "TEXCLDATA,CLUT Data Register" hexmask.long 0x4 0.--31. 1. "CLDATA,Texture CLUT Data" line.long 0x8 "TEXCLOFFSET,CLUT Offset Register" hexmask.long.byte 0x8 0.--7. 1. "CLOFFSET,Texture CLUT Offset" line.long 0xC "COLKEY,Color Key Register" hexmask.long.byte 0xC 16.--23. 1. "COLKEYR,Red Channel of Color Key" hexmask.long.byte 0xC 8.--15. 1. "COLKEYG,Green Channel of Color Key" newline hexmask.long.byte 0xC 0.--7. 1. "COLKEYB,Blue Channel of Color Key" tree.end tree.end tree "DTC (Data Transfer Controller)" base ad:0x0 tree "DTC0" base ad:0x4000AC00 group.byte 0xC++0x0 line.byte 0x0 "DTCST,DTC Module Start Register" bitfld.byte 0x0 0. "DTCST,DTC Module Start" "0: DTC module stopped,1: DTC module started" rgroup.word 0xE++0x1 line.word 0x0 "DTCSTS,DTC Status Register" bitfld.word 0x0 15. "ACT,DTC Active Flag" "0: DTC transfer operation is not in progress.,1: DTC transfer operation is in progress." hexmask.word.byte 0x0 0.--7. 1. "VECN,DTC-Activating Vector Number Monitoring" group.byte 0x10++0x0 line.byte 0x0 "DTCCR_SEC,DTC Control Register for Secure Region" bitfld.byte 0x0 4. "RRSS,DTC Transfer Information Read Skip Enable for Secure" "0: Transfer information read is not skipped.,1: Transfer information read is skipped when vector.." group.long 0x14++0x3 line.long 0x0 "DTCVBR_SEC,DTC Vector Base Register for Secure Region" group.long 0x20++0x3 line.long 0x0 "DTEVR,DTC Error Vector Register" bitfld.long 0x0 16. "DTESTA,DTC Error Status Flag" "0: No DTC transfer error occurred,1: DTC transfer error occurred" rbitfld.long 0x0 8. "DTEVSAM,DTC Error Vector Number SA Monitor" "0: Secure vector number,1: Non-secure vector number" hexmask.long.byte 0x0 0.--7. 1. "DTEV,DTC Error Vector Number" tree.end tree "DTC0_NS" base ad:0x5000AC00 group.byte 0x0++0x0 line.byte 0x0 "DTCCR,DTC Control Register" bitfld.byte 0x0 4. "RRS,DTC Transfer Information Read Skip Enable for Non-secure" "0: Transfer information read is not skipped,1: Transfer information read is skipped when vector.." group.long 0x4++0x3 line.long 0x0 "DTCVBR,DTC Vector Base Register" group.byte 0xC++0x0 line.byte 0x0 "DTCST,DTC Module Start Register" bitfld.byte 0x0 0. "DTCST,DTC Module Start" "0: DTC module stopped,1: DTC module started" rgroup.word 0xE++0x1 line.word 0x0 "DTCSTS,DTC Status Register" bitfld.word 0x0 15. "ACT,DTC Active Flag" "0: DTC transfer operation is not in progress.,1: DTC transfer operation is in progress." hexmask.word.byte 0x0 0.--7. 1. "VECN,DTC-Activating Vector Number Monitoring" group.long 0x20++0x3 line.long 0x0 "DTEVR,DTC Error Vector Register" bitfld.long 0x0 16. "DTESTA,DTC Error Status Flag" "0: No DTC transfer error occurred,1: DTC transfer error occurred" rbitfld.long 0x0 8. "DTEVSAM,DTC Error Vector Number SA Monitor" "0: Secure vector number,1: Non-secure vector number" hexmask.long.byte 0x0 0.--7. 1. "DTEV,DTC Error Vector Number" tree.end tree.end tree "ELC (Event Link Controller)" base ad:0x0 tree "ELC" base ad:0x40201000 group.byte 0x0++0x0 line.byte 0x0 "ELCR,Event Link Controller Register" bitfld.byte 0x0 7. "ELCON,All Event Link Enable" "0: ELC function is disabled.,1: ELC function is enabled." repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x4)++0x0 line.byte 0x0 "ELSEGR$1,Event Link Software Event Generation Register %s" bitfld.byte 0x0 7. "WI,ELSEGR Register Write Disable" "0: Write to ELSEGR register enabled.,1: Write to ELSEGR register disabled." bitfld.byte 0x0 6. "WE,SEG Bit Write Enable" "0: Write to SEG bit disabled.,1: Write to SEG bit enabled." bitfld.byte 0x0 0. "SEG,Software Event Generation" "0: Normal operation,1: Software event is generated." repeat.end repeat 18. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x20)++0x1 line.word 0x0 "ELSR$1,Event Link Setting Registern" hexmask.word 0x0 0.--8. 1. "ELS,Event Link Select" repeat.end group.word 0x98++0x1 line.word 0x0 "ELSR30,Event Link Setting Register30" hexmask.word 0x0 0.--8. 1. "ELS,Event Link Select" group.long 0xE0++0x7 line.long 0x0 "ELCSARA,Event Link Controller Security Attribution Register A" bitfld.long 0x0 2. "ELSEGR1,Event Link Software Event Generation Register 1 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 1. "ELSEGR0,Event Link Software Event Generation Register 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 0. "ELCR,Event Link Controller Register Security Attribution" "0: Secure,1: Non-secure" line.long 0x4 "ELCSARB,Event Link Controller Security Attribution Register B" hexmask.long.tbyte 0x4 0.--17. 1. "ELSR,Event Link Setting Register n Security Attribution" group.long 0xF0++0x7 line.long 0x0 "ELCPARA,Event Link Controller Privilege Attribution Register A" bitfld.long 0x0 2. "ELSEGR1,Event Link Software Event Generation Register 1 Privilege Attribution" "0: Privileged,1: Unprivileged" bitfld.long 0x0 1. "ELSEGR0,Event Link Software Event Generation Register 0 Privilege Attribution" "0: Privileged,1: Unprivileged" bitfld.long 0x0 0. "ELCR,Event Link Controller Register Privilege Attribution" "0: Privileged,1: Unprivileged" line.long 0x4 "ELCPARB,Event Link Controller Privilege Attribution Register B" hexmask.long.tbyte 0x4 0.--17. 1. "ELSR,Event Link Setting Register n Privilege Attribution" tree.end tree "ELC_NS" base ad:0x50201000 group.byte 0x0++0x0 line.byte 0x0 "ELCR,Event Link Controller Register" bitfld.byte 0x0 7. "ELCON,All Event Link Enable" "0: ELC function is disabled.,1: ELC function is enabled." repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x4)++0x0 line.byte 0x0 "ELSEGR$1,Event Link Software Event Generation Register %s" bitfld.byte 0x0 7. "WI,ELSEGR Register Write Disable" "0: Write to ELSEGR register enabled.,1: Write to ELSEGR register disabled." bitfld.byte 0x0 6. "WE,SEG Bit Write Enable" "0: Write to SEG bit disabled.,1: Write to SEG bit enabled." bitfld.byte 0x0 0. "SEG,Software Event Generation" "0: Normal operation,1: Software event is generated." repeat.end repeat 18. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x20)++0x1 line.word 0x0 "ELSR$1,Event Link Setting Registern" hexmask.word 0x0 0.--8. 1. "ELS,Event Link Select" repeat.end group.word 0x98++0x1 line.word 0x0 "ELSR30,Event Link Setting Register30" hexmask.word 0x0 0.--8. 1. "ELS,Event Link Select" group.long 0xE0++0x7 line.long 0x0 "ELCSARA,Event Link Controller Security Attribution Register A" bitfld.long 0x0 2. "ELSEGR1,Event Link Software Event Generation Register 1 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 1. "ELSEGR0,Event Link Software Event Generation Register 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 0. "ELCR,Event Link Controller Register Security Attribution" "0: Secure,1: Non-secure" line.long 0x4 "ELCSARB,Event Link Controller Security Attribution Register B" hexmask.long.tbyte 0x4 0.--17. 1. "ELSR,Event Link Setting Register n Security Attribution" group.long 0xF0++0x7 line.long 0x0 "ELCPARA,Event Link Controller Privilege Attribution Register A" bitfld.long 0x0 2. "ELSEGR1,Event Link Software Event Generation Register 1 Privilege Attribution" "0: Privileged,1: Unprivileged" bitfld.long 0x0 1. "ELSEGR0,Event Link Software Event Generation Register 0 Privilege Attribution" "0: Privileged,1: Unprivileged" bitfld.long 0x0 0. "ELCR,Event Link Controller Register Privilege Attribution" "0: Privileged,1: Unprivileged" line.long 0x4 "ELCPARB,Event Link Controller Privilege Attribution Register B" hexmask.long.tbyte 0x4 0.--17. 1. "ELSR,Event Link Setting Register n Privilege Attribution" tree.end tree.end tree "FLASH (Flash Memory)" base ad:0x0 tree "FACI (Flash Application Command Interface)" tree "FACI" base ad:0x4011E000 group.byte 0x10++0x0 line.byte 0x0 "FASTAT,Flash Access Status Register" bitfld.byte 0x0 7. "CFAE,Code Flash Memory Access Violation Flag" "0: No code flash memory access violation has occurred,1: A code flash memory access violation has occurred." rbitfld.byte 0x0 4. "CMDLK,Command Lock Flag" "0: The flash sequencer is not in the command-locked..,1: The flash sequencer is in the command-locked.." newline bitfld.byte 0x0 3. "DFAE,Data Flash Memory Access Violation Flag" "0: No data flash memory access violation has occurred,1: A data flash memory access violation has occurred." group.byte 0x14++0x0 line.byte 0x0 "FAEINT,Flash Access Error Interrupt Enable Register" bitfld.byte 0x0 7. "CFAEIE,Code Flash Memory Access Violation Interrupt Enable" "0: Generation of an FIFERR interrupt request is..,1: Generation of an FIFERR interrupt request is.." bitfld.byte 0x0 4. "CMDLKIE,Command Lock Interrupt Enable" "0: Generation of an FIFERR interrupt request is..,1: Generation of an FIFERR interrupt request is.." newline bitfld.byte 0x0 3. "DFAEIE,Data Flash Memory Access Violation Interrupt Enable" "0: Generation of an FIFERR interrupt request is..,1: Generation of an FIFERR interrupt request is.." group.byte 0x18++0x0 line.byte 0x0 "FRDYIE,Flash Ready Interrupt Enable Register" bitfld.byte 0x0 0. "FRDYIE,Flash Ready Interrupt Enable" "0: Generation of an FRDY interrupt request is..,1: Generation of an FRDY interrupt request is.." group.long 0x30++0x7 line.long 0x0 "FSADDR,FACI Command Start Address Register" line.long 0x4 "FEADDR,FACI Command End Address Register" hexmask.long 0x4 0.--31. 1. "FEADDR,End Address for FACI Command Processing" group.word 0x44++0x1 line.word 0x0 "FMEPROT,Flash P/E Mode Entry Protection Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "CEPROT,Code Flash P/E Mode Entry Protection" "0: FENTRYC bit is not protected,1: FENTRYC bit is protected." group.byte 0x48++0x0 line.byte 0x0 "FCNTSELR,Flash Counter Select Register" bitfld.byte 0x0 0.--2. "CNTSEL,Counter Select" "0,1,2,3,4,5,6,7" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x4C)++0x3 line.long 0x0 "FCNTDATAR$1,Flash Counter Data Register %s" hexmask.long 0x0 0.--31. 1. "CNTRDAT,Counter Read Data" repeat.end group.word 0x78++0x1 line.word 0x0 "FBPROT0,Flash Block Protection Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "BPCN0,Block Protection for Non-secure Cancel" "0: Block protection is enabled,1: Block protection is disabled." group.word 0x7C++0x1 line.word 0x0 "FBPROT1,Flash Block Protection for Secure Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "BPCN1,Block Protection for Secure Cancel" "0: Block protection is enabled,1: Block protection is disabled." rgroup.long 0x80++0x3 line.long 0x0 "FSTATR,Flash Status Register" bitfld.long 0x0 23. "ILGCOMERR,Illegal Command Error" "0: An illegal FACI command error has not been..,1: An illegal FACI command error has been detected." bitfld.long 0x0 22. "FESETERR,FENTRY Setting Error" "0: A setting error in the FENTRYR register has not..,1: A setting error in the FENTRYR register has been.." newline bitfld.long 0x0 21. "SECERR,Security Error" "0: A write protection error against MSUASMON.FSPR..,1: A write protection error against MSUASMON.FSPR.." bitfld.long 0x0 20. "OTERR,Other Error" "0: An error has not been detected.,1: An error has been detected." newline bitfld.long 0x0 19. "TZFERR,TrustZone Filter Error" "0: A TrustZone filter error has not been detected.,1: A TrustZone filter error has been detected." bitfld.long 0x0 15. "FRDY,Flash Ready Flag" "0: Program Block Erase Multi Block Erase P/E..,1: None of the above is in progress." newline bitfld.long 0x0 14. "ILGLERR,Illegal Command Error Flag" "0: The flash sequencer has not detected an illegal..,1: The flash sequencer has detected an illegal FACI.." bitfld.long 0x0 13. "ERSERR,Erasure Error Flag" "0: Erasure has completed successfully,1: An error has occurred during erasure." newline bitfld.long 0x0 12. "PRGERR,Programming Error Flag" "0: Programming has completed successfully,1: An error has occurred during programming." bitfld.long 0x0 11. "SUSRDY,Suspend Ready Flag" "0: The flash sequencer cannot receive P/E suspend..,1: The flash sequencer can receive P/E suspend.." newline bitfld.long 0x0 10. "DBFULL,Data Buffer Full Flag" "0: The data buffer is empty,1: The data buffer is full." bitfld.long 0x0 9. "ERSSPD,Erasure Suspend Status Flag" "0: The flash sequencer is not in the erasure..,1: The flash sequencer is in the erasure suspension.." newline bitfld.long 0x0 8. "PRGSPD,Programming Suspend Status Flag" "0: The flash sequencer is not in the programming..,1: The flash sequencer is in the programming.." bitfld.long 0x0 6. "FLWEERR,Flash Write/Erase Protect Error Flag" "0: An error has not occurred,1: An error has occurred." group.word 0x84++0x1 line.word 0x0 "FENTRYR,Flash P/E Mode Entry Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 7. "FENTRYD,Data Flash P/E Mode Entry" "0: Data flash is in read mode,1: Data flash is in P/E mode." newline bitfld.word 0x0 0. "FENTRYC,Code Flash P/E Mode Entry" "0: Code flash is in read mode,1: Code flash is in P/E mode." group.word 0x8C++0x1 line.word 0x0 "FSUINITR,Flash Sequencer Setup Initialization Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "SUINIT,Set-Up Initialization" "0: The FSADDR FEADDR FBPROT0 FBPROT1 FENTRYR FBCCNT..,1: The FSADDR FEADDR FBPROT0 FBRPOT1 FENTRYR FBCCNT.." rgroup.word 0xA0++0x1 line.word 0x0 "FCMDR,FACI Command Register" hexmask.word.byte 0x0 8.--15. 1. "CMDR,Command Flag" hexmask.word.byte 0x0 0.--7. 1. "PCMDR,Pre-command Flag" group.byte 0xD0++0x0 line.byte 0x0 "FBCCNT,Blank Check Control Register" bitfld.byte 0x0 0. "BCDIR,Blank Check Direction" "0: Blank checking is executed from the lower..,1: Blank checking is executed from the higher.." rgroup.byte 0xD4++0x0 line.byte 0x0 "FBCSTAT,Blank Check Status Register" bitfld.byte 0x0 0. "BCST,Blank Check Status Flag" "0: The target area is in the non-programmed state..,1: The target area has been programmed with 0s or 1s." rgroup.long 0xD8++0x7 line.long 0x0 "FPSADDR,Data Flash Programming Start Address Register" hexmask.long.tbyte 0x0 0.--16. 1. "PSADR,Programmed Area Start Address" line.long 0x4 "FSUASMON,Flash Startup Area Select Monitor Register" bitfld.long 0x4 31. "BTFLG,Flag of Startup Area Select for Boot Swap" "0: The startup area is the alternate block (block 1),1: The startup area is the default block (block 0)." bitfld.long 0x4 15. "FSPR,Protection Programming Flag to set Boot Flag and Startup Area Control" "0: Protected state,1: Non-protected state." group.word 0xE0++0x1 line.word 0x0 "FCPSR,Flash Sequencer Processing Switching Register" bitfld.word 0x0 0. "ESUSPMD,Erasure Suspend Mode" "0: Suspension priority mode,1: Erasure priority mode." group.word 0xE4++0x1 line.word 0x0 "FPCKAR,Flash Sequencer Processing Clock Notification Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" hexmask.word.byte 0x0 0.--7. 1. "PCKA,Flash Sequencer Operating Clock Notification" group.word 0xE8++0x1 line.word 0x0 "FSUACR,Flash Startup Area Control Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0.--1. "SAS,Startup Area Select" "0: Startup area is selected by BTFLG bit,1: Startup area is selected by BTFLG bit,?,?" tree.end tree "FACI_NS" base ad:0x5011E000 group.byte 0x10++0x0 line.byte 0x0 "FASTAT,Flash Access Status Register" bitfld.byte 0x0 7. "CFAE,Code Flash Memory Access Violation Flag" "0: No code flash memory access violation has occurred,1: A code flash memory access violation has occurred." rbitfld.byte 0x0 4. "CMDLK,Command Lock Flag" "0: The flash sequencer is not in the command-locked..,1: The flash sequencer is in the command-locked.." newline bitfld.byte 0x0 3. "DFAE,Data Flash Memory Access Violation Flag" "0: No data flash memory access violation has occurred,1: A data flash memory access violation has occurred." group.byte 0x14++0x0 line.byte 0x0 "FAEINT,Flash Access Error Interrupt Enable Register" bitfld.byte 0x0 7. "CFAEIE,Code Flash Memory Access Violation Interrupt Enable" "0: Generation of an FIFERR interrupt request is..,1: Generation of an FIFERR interrupt request is.." bitfld.byte 0x0 4. "CMDLKIE,Command Lock Interrupt Enable" "0: Generation of an FIFERR interrupt request is..,1: Generation of an FIFERR interrupt request is.." newline bitfld.byte 0x0 3. "DFAEIE,Data Flash Memory Access Violation Interrupt Enable" "0: Generation of an FIFERR interrupt request is..,1: Generation of an FIFERR interrupt request is.." group.byte 0x18++0x0 line.byte 0x0 "FRDYIE,Flash Ready Interrupt Enable Register" bitfld.byte 0x0 0. "FRDYIE,Flash Ready Interrupt Enable" "0: Generation of an FRDY interrupt request is..,1: Generation of an FRDY interrupt request is.." group.long 0x30++0x7 line.long 0x0 "FSADDR,FACI Command Start Address Register" hexmask.long 0x0 0.--31. 1. "FSADDR,Start Address for FACI Command Processing" line.long 0x4 "FEADDR,FACI Command End Address Register" hexmask.long 0x4 0.--31. 1. "FEADDR,End Address for FACI Command Processing" group.word 0x78++0x1 line.word 0x0 "FBPROT0,Flash Block Protection Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "BPCN0,Block Protection for Non-secure Cancel" "0: Block protection is enabled,1: Block protection is disabled." rgroup.long 0x80++0x3 line.long 0x0 "FSTATR,Flash Status Register" bitfld.long 0x0 23. "ILGCOMERR,Illegal Command Error" "0: An illegal FACI command error has not been..,1: An illegal FACI command error has been detected." bitfld.long 0x0 22. "FESETERR,FENTRY Setting Error" "0: A setting error in the FENTRYR register has not..,1: A setting error in the FENTRYR register has been.." newline bitfld.long 0x0 21. "SECERR,Security Error" "0: A write protection error against MSUASMON.FSPR..,1: A write protection error against MSUASMON.FSPR.." bitfld.long 0x0 20. "OTERR,Other Error" "0: An error has not been detected.,1: An error has been detected." newline bitfld.long 0x0 19. "TZFERR,TrustZone Filter Error" "0: A TrustZone filter error has not been detected.,1: A TrustZone filter error has been detected." bitfld.long 0x0 15. "FRDY,Flash Ready Flag" "0: Program Block Erase Multi Block Erase P/E..,1: None of the above is in progress." newline bitfld.long 0x0 14. "ILGLERR,Illegal Command Error Flag" "0: The flash sequencer has not detected an illegal..,1: The flash sequencer has detected an illegal FACI.." bitfld.long 0x0 13. "ERSERR,Erasure Error Flag" "0: Erasure has completed successfully,1: An error has occurred during erasure." newline bitfld.long 0x0 12. "PRGERR,Programming Error Flag" "0: Programming has completed successfully,1: An error has occurred during programming." bitfld.long 0x0 11. "SUSRDY,Suspend Ready Flag" "0: The flash sequencer cannot receive P/E suspend..,1: The flash sequencer can receive P/E suspend.." newline bitfld.long 0x0 10. "DBFULL,Data Buffer Full Flag" "0: The data buffer is empty,1: The data buffer is full." bitfld.long 0x0 9. "ERSSPD,Erasure Suspend Status Flag" "0: The flash sequencer is not in the erasure..,1: The flash sequencer is in the erasure suspension.." newline bitfld.long 0x0 8. "PRGSPD,Programming Suspend Status Flag" "0: The flash sequencer is not in the programming..,1: The flash sequencer is in the programming.." bitfld.long 0x0 6. "FLWEERR,Flash Write/Erase Protect Error Flag" "0: An error has not occurred,1: An error has occurred." group.word 0x84++0x1 line.word 0x0 "FENTRYR,Flash P/E Mode Entry Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 7. "FENTRYD,Data Flash P/E Mode Entry" "0: Data flash is in read mode,1: Data flash is in P/E mode." newline bitfld.word 0x0 0. "FENTRYC,Code Flash P/E Mode Entry" "0: Code flash is in read mode,1: Code flash is in P/E mode." group.word 0x8C++0x1 line.word 0x0 "FSUINITR,Flash Sequencer Setup Initialization Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "SUINIT,Set-Up Initialization" "0: The FSADDR FEADDR FBPROT0 FBPROT1 FENTRYR FBCCNT..,1: The FSADDR FEADDR FBPROT0 FBRPOT1 FENTRYR FBCCNT.." rgroup.word 0xA0++0x1 line.word 0x0 "FCMDR,FACI Command Register" hexmask.word.byte 0x0 8.--15. 1. "CMDR,Command Flag" hexmask.word.byte 0x0 0.--7. 1. "PCMDR,Pre-command Flag" group.byte 0xD0++0x0 line.byte 0x0 "FBCCNT,Blank Check Control Register" bitfld.byte 0x0 0. "BCDIR,Blank Check Direction" "0: Blank checking is executed from the lower..,1: Blank checking is executed from the higher.." rgroup.byte 0xD4++0x0 line.byte 0x0 "FBCSTAT,Blank Check Status Register" bitfld.byte 0x0 0. "BCST,Blank Check Status Flag" "0: The target area is in the non-programmed state..,1: The target area has been programmed with 0s or 1s." rgroup.long 0xD8++0x7 line.long 0x0 "FPSADDR,Data Flash Programming Start Address Register" hexmask.long.tbyte 0x0 0.--16. 1. "PSADR,Programmed Area Start Address" line.long 0x4 "FSUASMON,Flash Startup Area Select Monitor Register" bitfld.long 0x4 31. "BTFLG,Flag of Startup Area Select for Boot Swap" "0: The startup area is the alternate block (block 1),1: The startup area is the default block (block 0)." bitfld.long 0x4 15. "FSPR,Protection Programming Flag to set Boot Flag and Startup Area Control" "0: Protected state,1: Non-protected state." group.word 0xE0++0x1 line.word 0x0 "FCPSR,Flash Sequencer Processing Switching Register" bitfld.word 0x0 0. "ESUSPMD,Erasure Suspend Mode" "0: Suspension priority mode,1: Erasure priority mode." group.word 0xE4++0x1 line.word 0x0 "FPCKAR,Flash Sequencer Processing Clock Notification Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" hexmask.word.byte 0x0 0.--7. 1. "PCKA,Flash Sequencer Operating Clock Notification" tree.end tree.end tree "FCACHE (Flash Cache)" tree "FCACHE" base ad:0x4001C100 group.word 0x0++0x1 line.word 0x0 "FCACHEE,Flash Cache Enable Register" bitfld.word 0x0 0. "FCACHEEN,Flash Cache Enable" "0: FCACHE is disabled,1: FCACHE is enabled" group.word 0x4++0x1 line.word 0x0 "FCACHEIV,Flash Cache Invalidate Register" bitfld.word 0x0 0. "FCACHEIV,Flash Cache Invalidate" "0: Read: Do not invalidate. Write: The setting is..,1: Invalidate FCACHE is invalidated." group.byte 0x1C++0x0 line.byte 0x0 "FLWT,Flash Wait Cycle Register" bitfld.byte 0x0 0.--2. "FLWT,Flash Wait Cycle" "0,1,2,3,4,5,6,7" group.word 0x40++0x1 line.word 0x0 "FSAR,Flash Security Attribution Register" bitfld.word 0x0 10. "FACICMRSA,FACI command Registers Security Attribution" "0: Secure,1: Non-secure" bitfld.word 0x0 9. "FACICMISA,FACI command Issuing Security Attribution" "0: Secure,1: Non-secure" bitfld.word 0x0 8. "FCKMHZSA,FCKMHZ Security Attribution" "0: Secure,1: Non-secure" bitfld.word 0x0 1. "FCACHESA,FCHACHEEN Security Attribution" "0: Secure,1: Non-secure" newline bitfld.word 0x0 0. "FLWTSA,FLWT Security Attribution" "0: Secure,1: Non-secure" tree.end tree "FCACHE_NS" base ad:0x5001C100 group.word 0x0++0x1 line.word 0x0 "FCACHEE,Flash Cache Enable Register" bitfld.word 0x0 0. "FCACHEEN,Flash Cache Enable" "0: FCACHE is disabled,1: FCACHE is enabled" group.word 0x4++0x1 line.word 0x0 "FCACHEIV,Flash Cache Invalidate Register" bitfld.word 0x0 0. "FCACHEIV,Flash Cache Invalidate" "0: Read: Do not invalidate. Write: The setting is..,1: Invalidate FCACHE is invalidated." group.byte 0x1C++0x0 line.byte 0x0 "FLWT,Flash Wait Cycle Register" bitfld.byte 0x0 0.--2. "FLWT,Flash Wait Cycle" "0,1,2,3,4,5,6,7" group.word 0x40++0x1 line.word 0x0 "FSAR,Flash Security Attribution Register" bitfld.word 0x0 10. "FACICMRSA,FACI command Registers Security Attribution" "0: Secure,1: Non-secure" bitfld.word 0x0 9. "FACICMISA,FACI command Issuing Security Attribution" "0: Secure,1: Non-secure" bitfld.word 0x0 8. "FCKMHZSA,FCKMHZ Security Attribution" "0: Secure,1: Non-secure" bitfld.word 0x0 1. "FCACHESA,FCHACHEEN Security Attribution" "0: Secure,1: Non-secure" newline bitfld.word 0x0 0. "FLWTSA,FLWT Security Attribution" "0: Secure,1: Non-secure" tree.end tree.end tree "FLAD (Data Flash)" tree "FLAD" base ad:0x4011C000 group.byte 0x40++0x0 line.byte 0x0 "FCKMHZ,Data Flash Access Frequency Register" hexmask.byte 0x0 0.--7. 1. "FCKMHZ,Data Flash Access Frequency Register" tree.end tree "FLAD_NS" base ad:0x5011C000 group.byte 0x40++0x0 line.byte 0x0 "FCKMHZ,Data Flash Access Frequency Register" hexmask.byte 0x0 0.--7. 1. "FCKMHZ,Data Flash Access Frequency Register" tree.end tree.end tree.end tree "GLCDC (Graphics LCD Controller)" base ad:0x0 tree "GLCDC" base ad:0x40342000 repeat 256. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "GR1_CLUT0$1,Color Palette" hexmask.long.byte 0x0 24.--31. 1. "A,Alpha blending value of color palette n plane for graphics m plane. Unsigned 8-bit integer." hexmask.long.byte 0x0 16.--23. 1. "R,R value of color palette n plane for graphics m plane. Unsigned 8-bit integer." newline hexmask.long.byte 0x0 8.--15. 1. "G,G value of color palette n plane for graphics m plane. Unsigned 8-bit integer." hexmask.long.byte 0x0 0.--7. 1. "B,B value of color palette n plane for graphics m plane. Unsigned 8-bit integer." repeat.end repeat 256. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x400)++0x3 line.long 0x0 "GR1_CLUT1$1,Color Palette" hexmask.long.byte 0x0 24.--31. 1. "A,Alpha blending value of color palette n plane for graphics m plane. Unsigned 8-bit integer." hexmask.long.byte 0x0 16.--23. 1. "R,R value of color palette n plane for graphics m plane. Unsigned 8-bit integer." newline hexmask.long.byte 0x0 8.--15. 1. "G,G value of color palette n plane for graphics m plane. Unsigned 8-bit integer." hexmask.long.byte 0x0 0.--7. 1. "B,B value of color palette n plane for graphics m plane. Unsigned 8-bit integer." repeat.end repeat 256. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x800)++0x3 line.long 0x0 "GR2_CLUT0$1,Color Palette" hexmask.long.byte 0x0 24.--31. 1. "A,Alpha blending value of color palette n plane for graphics m plane. Unsigned 8-bit integer." hexmask.long.byte 0x0 16.--23. 1. "R,R value of color palette n plane for graphics m plane. Unsigned 8-bit integer." newline hexmask.long.byte 0x0 8.--15. 1. "G,G value of color palette n plane for graphics m plane. Unsigned 8-bit integer." hexmask.long.byte 0x0 0.--7. 1. "B,B value of color palette n plane for graphics m plane. Unsigned 8-bit integer." repeat.end repeat 256. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC00)++0x3 line.long 0x0 "GR2_CLUT1$1,Color Palette" hexmask.long.byte 0x0 24.--31. 1. "A,Alpha blending value of color palette n plane for graphics m plane. Unsigned 8-bit integer." hexmask.long.byte 0x0 16.--23. 1. "R,R value of color palette n plane for graphics m plane. Unsigned 8-bit integer." newline hexmask.long.byte 0x0 8.--15. 1. "G,G value of color palette n plane for graphics m plane. Unsigned 8-bit integer." hexmask.long.byte 0x0 0.--7. 1. "B,B value of color palette n plane for graphics m plane. Unsigned 8-bit integer." repeat.end group.long 0x1000++0x17 line.long 0x0 "BG_EN,Background Plane Setting Operation Control Register" bitfld.long 0x0 16. "SWRST,Software Reset Control" "0: Place entire module in software reset state,1: Release entire module from software reset state" bitfld.long 0x0 8. "VEN,Control of GLCDC Internal Register Value Reflection to Internal Operations" "0: Disable GLCDC register values from being..,1: Enable GLCDC register values to be reflected in.." newline bitfld.long 0x0 0. "EN,Background Plane Operation Enable" "0: Disable background plane operation,1: Enable background plane operation" line.long 0x4 "BG_PERI,Background Plane Setting Free-Running Period Register" hexmask.long.word 0x4 16.--26. 1. "FV,Background Plane Vertical Synchronization Signal Period" hexmask.long.word 0x4 0.--10. 1. "FH,Background Plane Horizontal Synchronization Signal Period" line.long 0x8 "BG_SYNC,Background Plane Setting Synchronization Position Register" hexmask.long.byte 0x8 16.--19. 1. "VP,Background Plane Vertical Synchronization Assertion Position" hexmask.long.byte 0x8 0.--3. 1. "HP,Background Plane Horizontal Synchronization Signal Assertion Position" line.long 0xC "BG_VSIZE,Background Plane Setting Full Image Vertical Size Register" hexmask.long.word 0xC 16.--26. 1. "VP,Background Plane Vertical Valid Pixel Start Position" hexmask.long.word 0xC 0.--10. 1. "VW,Background Plane Vertical Valid Pixel Width" line.long 0x10 "BG_HSIZE,Background Plane Setting Full Image Horizontal Size Register" hexmask.long.word 0x10 16.--26. 1. "HP,Background Plane Horizontal Valid Pixel Start Position" hexmask.long.word 0x10 0.--10. 1. "HW,Background Plane Horizontal Valid Pixel Width" line.long 0x14 "BG_BGC,Background Plane Setting Background Color Register" hexmask.long.byte 0x14 16.--23. 1. "R,Background Plane Valid Pixel Area R Value" hexmask.long.byte 0x14 8.--15. 1. "G,Background Plane Valid Pixel Area G Value" newline hexmask.long.byte 0x14 0.--7. 1. "B,Background Plane Valid Pixel Area B Value" rgroup.long 0x1018++0x3 line.long 0x0 "BG_MON,Background Plane Setting Status Monitor Register" bitfld.long 0x0 16. "SWRST,Entire Module SW Reset State Monitor" "0: Entire module is in software reset state,1: Entire module is released from software reset.." bitfld.long 0x0 8. "VEN,Entire Module Internal Operation Reflection Control Signal Monitor" "0: Signal for controlling reflection of the..,1: Signal for controlling reflection of the.." newline bitfld.long 0x0 0. "EN,Background Plane Operation Monitor" "0: Operation is stopped,1: Operation is in progress" repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1100)++0x3 line.long 0x0 "GR$1_VEN,Graphics %s Register Update Control Register" bitfld.long 0x0 0. "PVEN,This bit is cleared to 0 by an internal source." "0: Disable reflection of register values to..,1: Enable reflection of register values to internal.." repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1104)++0x3 line.long 0x0 "GR$1_FLMRD,Graphics %s Frame Buffer Read Control Register" bitfld.long 0x0 0. "RENB,Graphics Data Read Enable" "0: Disable reading,1: Enable reading" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1108)++0x3 line.long 0x0 "GR$1_FLM1,Graphics %s Frame Buffer Control Register 1" bitfld.long 0x0 0.--1. "BSTMD,Burst Transfer Control for Graphics Data Access" "0: Setting prohibited,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x110C)++0x3 line.long 0x0 "GR$1_FLM2,Graphics %s Frame Buffer Control Register 2" hexmask.long 0x0 0.--31. 1. "BASE,Base Address for Accessing Graphics Data" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1110)++0x3 line.long 0x0 "GR$1_FLM3,Graphics %s Frame Buffer Control Register 3" hexmask.long.word 0x0 16.--31. 1. "LNOFF,Macro Line Offset Address for Accessing Graphics Data" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1118)++0x3 line.long 0x0 "GR$1_FLM5,Graphics %s Frame Buffer Control Register 5" hexmask.long.word 0x0 16.--26. 1. "LNNUM,Number of Lines Per Frame for Accessing Graphics Data" hexmask.long.word 0x0 0.--15. 1. "DATANUM,Number of Data Transfer Times Per Line for Accessing Graphics Data" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x111C)++0x3 line.long 0x0 "GR$1_FLM6,Graphics %s Frame Buffer Control Register 6" bitfld.long 0x0 28.--30. "FORMAT,Data Format for Accessing Graphics Data" "0: RGB565 (16 bits/pixel),1: RGB888 (32 bits/pixel 8 bits on the MSB side are..,?,?,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1120)++0x3 line.long 0x0 "GR$1_AB1,Graphics %s Alpha Blending Control Register 1" bitfld.long 0x0 12. "ARCON,Rectangular Area Alpha Blending Control" "0: Turn blending off,1: Turn blending on" bitfld.long 0x0 8. "ARCDISPON,Image Area Border Display Control for Rectangular Area Alpha Blending" "0: Turn display off,1: Turn display on" newline bitfld.long 0x0 4. "GRCDISPON,Graphics Image Area Border Display Control" "0: Turn display off,1: Turn display on" bitfld.long 0x0 0.--1. "DISPSEL,Graphics Display Plane Control" "0: Background color display (value set in the..,1: Lower-layer graphics display,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1124)++0x3 line.long 0x0 "GR$1_AB2,Graphics %s Alpha Blending Control Register 2" hexmask.long.word 0x0 16.--26. 1. "GRCVS,Vertical Start Position of Graphics Image Area" hexmask.long.word 0x0 0.--10. 1. "GRCVW,Vertical Width of Graphics Image Area" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1128)++0x3 line.long 0x0 "GR$1_AB3,Graphics %s Alpha Blending Control Register 3" hexmask.long.word 0x0 16.--26. 1. "GRCHS,Horizontal Start Position of Graphics Image Area" hexmask.long.word 0x0 0.--10. 1. "GRCHW,Horizontal Width of Graphics Image Area" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x112C)++0x3 line.long 0x0 "GR$1_AB4,Graphics %s Alpha Blending Control Register 4" hexmask.long.word 0x0 16.--26. 1. "ARCVS,Vertical Start Position of Rectangular Area Alpha Blending Image Area" hexmask.long.word 0x0 0.--10. 1. "ARCVW,Vertical Width of Rectangular Area Alpha Blending Image Area" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1130)++0x3 line.long 0x0 "GR$1_AB5,Graphics %s Alpha Blending Control Register 5" hexmask.long.word 0x0 16.--26. 1. "ARCHS,Horizontal Start Position of Rectangular Area Alpha Blending Image Area" hexmask.long.word 0x0 0.--10. 1. "ARCHW,Horizontal Width of Rectangular Area Alpha Blending Image Area" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1134)++0x3 line.long 0x0 "GR$1_AB6,Graphics %s Alpha Blending Control Register 6" hexmask.long.word 0x0 16.--24. 1. "ARCCOEF,Alpha Coefficient for Alpha Blending in Rectangular Area" hexmask.long.byte 0x0 0.--7. 1. "ARCRATE,Frame Rate for Alpha Blending in Rectangular Area" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1138)++0x3 line.long 0x0 "GR$1_AB7,Graphics %s Alpha Blending Control Register 7" hexmask.long.byte 0x0 16.--23. 1. "ARCDEF,Initial Alpha Value for Alpha Blending in Rectangular Area" bitfld.long 0x0 0. "CKON,RGB-Index Chroma-Key Processing Control" "0: Disable chroma-key processing,1: Enable chroma-key processing" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x113C)++0x3 line.long 0x0 "GR$1_AB8,Graphics %s Alpha Blending Control Register 8" hexmask.long.byte 0x0 16.--23. 1. "CKKG,G Signal for RGB-Index Chroma-Key Processing" hexmask.long.byte 0x0 8.--15. 1. "CKKB,B Signal for RGB-Index Chroma-Key Processing" newline hexmask.long.byte 0x0 0.--7. 1. "CKKR,R Signal for RGB-Index Chroma-Key Processing" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1140)++0x3 line.long 0x0 "GR$1_AB9,Graphics %s Alpha Blending Control Register 9" hexmask.long.byte 0x0 24.--31. 1. "CKA,A Value after RGB-Index Chroma-Key Processing Replacement" hexmask.long.byte 0x0 16.--23. 1. "CKG,G Value after RGB-Index Chroma-Key Processing Replacement" newline hexmask.long.byte 0x0 8.--15. 1. "CKB,B Value after RGB-Index Chroma-Key Processing Replacement" hexmask.long.byte 0x0 0.--7. 1. "CKR,R Value after RGB-Index Chroma-Key Processing Replacement" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x114C)++0x3 line.long 0x0 "GR$1_BASE,Graphics %s Background Color Control Register" hexmask.long.byte 0x0 16.--23. 1. "G,Background Color G Value" hexmask.long.byte 0x0 8.--15. 1. "B,Background Color B Value" newline hexmask.long.byte 0x0 0.--7. 1. "R,Background Color R Value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1150)++0x3 line.long 0x0 "GR$1_CLUTINT,Graphics %s CLUT Table Interrupt Control Register" bitfld.long 0x0 16. "SEL,CLUT Table Control" "0: Select CLUT table 0,1: Select CLUT table 1" hexmask.long.word 0x0 0.--10. 1. "LINE,Number of Detection Lines" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) rgroup.long ($2+0x1154)++0x3 line.long 0x0 "GR$1_MON,Graphics %s Status Monitor Register" bitfld.long 0x0 16. "UNDFLST,Underflow Status Monitor" "0: No underflow occurred in internal operations,1: Underflow occurred in internal operations" bitfld.long 0x0 0. "ARCST,Status Monitor for Alpha Blending in Rectangular Area" "0: Fade-in/fade-out not in progress,1: Fade-in/fade-out in progress" repeat.end group.long 0x1300++0x3B line.long 0x0 "GAMG_LATCH,Gamma G Register Update Control Register" bitfld.long 0x0 0. "VEN,Control of Gamma Correction × Module Register Value Reflection to Internal Operations" "0: Disable reflection of register values to..,1: Enable reflection of register values to internal.." line.long 0x4 "GAM_SW,Gamma Correction Block Function Switch Register" bitfld.long 0x4 0. "GAMON,Gamma Correction On/Off Control" "0: Turn off gamma correction,1: Turn on gamma correction" line.long 0x8 "GAMG_LUT1,Gamma G Correction Block Table Setting Register 1" hexmask.long.word 0x8 16.--26. 1. "GAIN00,Gain Value of Area 0" hexmask.long.word 0x8 0.--10. 1. "GAIN01,Gain Value of Area 1" line.long 0xC "GAMG_LUT2,Gamma G Correction Block Table Setting Register 2" hexmask.long.word 0xC 16.--26. 1. "GAIN02,Gain Value of Area 2" hexmask.long.word 0xC 0.--10. 1. "GAIN03,Gain Value of Area 3" line.long 0x10 "GAMG_LUT3,Gamma G Correction Block Table Setting Register 3" hexmask.long.word 0x10 16.--26. 1. "GAIN04,Gain Value of Area 4" hexmask.long.word 0x10 0.--10. 1. "GAIN05,Gain Value of Area 5" line.long 0x14 "GAMG_LUT4,Gamma G Correction Block Table Setting Register 4" hexmask.long.word 0x14 16.--26. 1. "GAIN06,Gain Value of Area 6" hexmask.long.word 0x14 0.--10. 1. "GAIN07,Gain Value of Area 7" line.long 0x18 "GAMG_LUT5,Gamma G Correction Block Table Setting Register 5" hexmask.long.word 0x18 16.--26. 1. "GAIN08,Gain Value of Area 8" hexmask.long.word 0x18 0.--10. 1. "GAIN09,Gain Value of Area 9" line.long 0x1C "GAMG_LUT6,Gamma G Correction Block Table Setting Register 6" hexmask.long.word 0x1C 16.--26. 1. "GAIN10,Gain Value of Area 10" hexmask.long.word 0x1C 0.--10. 1. "GAIN11,Gain Value of Area 11" line.long 0x20 "GAMG_LUT7,Gamma G Correction Block Table Setting Register 7" hexmask.long.word 0x20 16.--26. 1. "GAIN12,Gain Value of Area 12" hexmask.long.word 0x20 0.--10. 1. "GAIN13,Gain Value of Area 13" line.long 0x24 "GAMG_LUT8,Gamma G Correction Block Table Setting Register 8" hexmask.long.word 0x24 16.--26. 1. "GAIN14,Gain Value of Area 14" hexmask.long.word 0x24 0.--10. 1. "GAIN15,Gain Value of Area 15" line.long 0x28 "GAMG_AREA1,Gamma G Correction Block Area Setting Register 1" hexmask.long.word 0x28 20.--29. 1. "TH01,Start Threshold of Area 1" hexmask.long.word 0x28 10.--19. 1. "TH02,Start Threshold of Area 2" newline hexmask.long.word 0x28 0.--9. 1. "TH03,Start Threshold of Area 3" line.long 0x2C "GAMG_AREA2,Gamma G Correction Block Area Setting Register 2" hexmask.long.word 0x2C 20.--29. 1. "TH04,Start Threshold of Area 4" hexmask.long.word 0x2C 10.--19. 1. "TH05,Start Threshold of Area 5" newline hexmask.long.word 0x2C 0.--9. 1. "TH06,Start Threshold of Area 6" line.long 0x30 "GAMG_AREA3,Gamma G Correction Block Area Setting Register 3" hexmask.long.word 0x30 20.--29. 1. "TH07,Start Threshold of Area 7" hexmask.long.word 0x30 10.--19. 1. "TH08,Start Threshold of Area 8" newline hexmask.long.word 0x30 0.--9. 1. "TH09,Start Threshold of Area 9" line.long 0x34 "GAMG_AREA4,Gamma G Correction Block Area Setting Register 4" hexmask.long.word 0x34 20.--29. 1. "TH10,Start Threshold of Area 10" hexmask.long.word 0x34 10.--19. 1. "TH11,Start Threshold of Area 11" newline hexmask.long.word 0x34 0.--9. 1. "TH12,Start Threshold of Area 12" line.long 0x38 "GAMG_AREA5,Gamma G Correction Block Area Setting Register 5" hexmask.long.word 0x38 20.--29. 1. "TH13,Start Threshold of Area 13" hexmask.long.word 0x38 10.--19. 1. "TH14,Start Threshold of Area 14" newline hexmask.long.word 0x38 0.--9. 1. "TH15,Start Threshold of Area 15" group.long 0x1340++0x3 line.long 0x0 "GAMB_LATCH,Gamma B Register Update Control Register" bitfld.long 0x0 0. "VEN,Control of Gamma Correction × Module Register Value Reflection to Internal Operations" "0: Disable reflection of register values to..,1: Enable reflection of register values to internal.." group.long 0x1348++0x33 line.long 0x0 "GAMB_LUT1,Gamma B Correction Block Table Setting Register 1" hexmask.long.word 0x0 16.--26. 1. "GAIN00,Gain Value of Area 0" hexmask.long.word 0x0 0.--10. 1. "GAIN01,Gain Value of Area 1" line.long 0x4 "GAMB_LUT2,Gamma B Correction Block Table Setting Register 2" hexmask.long.word 0x4 16.--26. 1. "GAIN02,Gain Value of Area 2" hexmask.long.word 0x4 0.--10. 1. "GAIN03,Gain Value of Area 3" line.long 0x8 "GAMB_LUT3,Gamma B Correction Block Table Setting Register 3" hexmask.long.word 0x8 16.--26. 1. "GAIN04,Gain Value of Area 4" hexmask.long.word 0x8 0.--10. 1. "GAIN05,Gain Value of Area 5" line.long 0xC "GAMB_LUT4,Gamma B Correction Block Table Setting Register 4" hexmask.long.word 0xC 16.--26. 1. "GAIN06,Gain Value of Area 6" hexmask.long.word 0xC 0.--10. 1. "GAIN07,Gain Value of Area 7" line.long 0x10 "GAMB_LUT5,Gamma B Correction Block Table Setting Register 5" hexmask.long.word 0x10 16.--26. 1. "GAIN08,Gain Value of Area 8" hexmask.long.word 0x10 0.--10. 1. "GAIN09,Gain Value of Area 9" line.long 0x14 "GAMB_LUT6,Gamma B Correction Block Table Setting Register 6" hexmask.long.word 0x14 16.--26. 1. "GAIN10,Gain Value of Area 10" hexmask.long.word 0x14 0.--10. 1. "GAIN11,Gain Value of Area 11" line.long 0x18 "GAMB_LUT7,Gamma B Correction Block Table Setting Register 7" hexmask.long.word 0x18 16.--26. 1. "GAIN12,Gain Value of Area 12" hexmask.long.word 0x18 0.--10. 1. "GAIN13,Gain Value of Area 13" line.long 0x1C "GAMB_LUT8,Gamma B Correction Block Table Setting Register 8" hexmask.long.word 0x1C 16.--26. 1. "GAIN14,Gain Value of Area 14" hexmask.long.word 0x1C 0.--10. 1. "GAIN15,Gain Value of Area 15" line.long 0x20 "GAMB_AREA1,Gamma B Correction Block Area Setting Register 1" hexmask.long.word 0x20 20.--29. 1. "TH01,Start Threshold of Area 1" hexmask.long.word 0x20 10.--19. 1. "TH02,Start Threshold of Area 2" newline hexmask.long.word 0x20 0.--9. 1. "TH03,Start Threshold of Area 3" line.long 0x24 "GAMB_AREA2,Gamma B Correction Block Area Setting Register 2" hexmask.long.word 0x24 20.--29. 1. "TH04,Start Threshold of Area 4" hexmask.long.word 0x24 10.--19. 1. "TH05,Start Threshold of Area 5" newline hexmask.long.word 0x24 0.--9. 1. "TH06,Start Threshold of Area 6" line.long 0x28 "GAMB_AREA3,Gamma B Correction Block Area Setting Register 3" hexmask.long.word 0x28 20.--29. 1. "TH07,Start Threshold of Area 7" hexmask.long.word 0x28 10.--19. 1. "TH08,Start Threshold of Area 8" newline hexmask.long.word 0x28 0.--9. 1. "TH09,Start Threshold of Area 9" line.long 0x2C "GAMB_AREA4,Gamma B Correction Block Area Setting Register 4" hexmask.long.word 0x2C 20.--29. 1. "TH10,Start Threshold of Area 10" hexmask.long.word 0x2C 10.--19. 1. "TH11,Start Threshold of Area 11" newline hexmask.long.word 0x2C 0.--9. 1. "TH12,Start Threshold of Area 12" line.long 0x30 "GAMB_AREA5,Gamma B Correction Block Area Setting Register 5" hexmask.long.word 0x30 20.--29. 1. "TH13,Start Threshold of Area 13" hexmask.long.word 0x30 10.--19. 1. "TH14,Start Threshold of Area 14" newline hexmask.long.word 0x30 0.--9. 1. "TH15,Start Threshold of Area 15" group.long 0x1380++0x3 line.long 0x0 "GAMR_LATCH,Gamma R Register Update Control Register" bitfld.long 0x0 0. "VEN,Control of Gamma Correction × Module Register Value Reflection to Internal Operations" "0: Disable reflection of register values to..,1: Enable reflection of register values to internal.." group.long 0x1388++0x33 line.long 0x0 "GAMR_LUT1,Gamma R Correction Block Table Setting Register 1" hexmask.long.word 0x0 16.--26. 1. "GAIN00,Gain Value of Area 0" hexmask.long.word 0x0 0.--10. 1. "GAIN01,Gain Value of Area 1" line.long 0x4 "GAMR_LUT2,Gamma R Correction Block Table Setting Register 2" hexmask.long.word 0x4 16.--26. 1. "GAIN02,Gain Value of Area 2" hexmask.long.word 0x4 0.--10. 1. "GAIN03,Gain Value of Area 3" line.long 0x8 "GAMR_LUT3,Gamma R Correction Block Table Setting Register 3" hexmask.long.word 0x8 16.--26. 1. "GAIN04,Gain Value of Area 4" hexmask.long.word 0x8 0.--10. 1. "GAIN05,Gain Value of Area 5" line.long 0xC "GAMR_LUT4,Gamma R Correction Block Table Setting Register 4" hexmask.long.word 0xC 16.--26. 1. "GAIN06,Gain Value of Area 6" hexmask.long.word 0xC 0.--10. 1. "GAIN07,Gain Value of Area 7" line.long 0x10 "GAMR_LUT5,Gamma R Correction Block Table Setting Register 5" hexmask.long.word 0x10 16.--26. 1. "GAIN08,Gain Value of Area 8" hexmask.long.word 0x10 0.--10. 1. "GAIN09,Gain Value of Area 9" line.long 0x14 "GAMR_LUT6,Gamma R Correction Block Table Setting Register 6" hexmask.long.word 0x14 16.--26. 1. "GAIN10,Gain Value of Area 10" hexmask.long.word 0x14 0.--10. 1. "GAIN11,Gain Value of Area 11" line.long 0x18 "GAMR_LUT7,Gamma R Correction Block Table Setting Register 7" hexmask.long.word 0x18 16.--26. 1. "GAIN12,Gain Value of Area 12" hexmask.long.word 0x18 0.--10. 1. "GAIN13,Gain Value of Area 13" line.long 0x1C "GAMR_LUT8,Gamma R Correction Block Table Setting Register 8" hexmask.long.word 0x1C 16.--26. 1. "GAIN14,Gain Value of Area 14" hexmask.long.word 0x1C 0.--10. 1. "GAIN15,Gain Value of Area 15" line.long 0x20 "GAMR_AREA1,Gamma R Correction Block Area Setting Register 1" hexmask.long.word 0x20 20.--29. 1. "TH01,Start Threshold of Area 1" hexmask.long.word 0x20 10.--19. 1. "TH02,Start Threshold of Area 2" newline hexmask.long.word 0x20 0.--9. 1. "TH03,Start Threshold of Area 3" line.long 0x24 "GAMR_AREA2,Gamma R Correction Block Area Setting Register 2" hexmask.long.word 0x24 20.--29. 1. "TH04,Start Threshold of Area 4" hexmask.long.word 0x24 10.--19. 1. "TH05,Start Threshold of Area 5" newline hexmask.long.word 0x24 0.--9. 1. "TH06,Start Threshold of Area 6" line.long 0x28 "GAMR_AREA3,Gamma R Correction Block Area Setting Register 3" hexmask.long.word 0x28 20.--29. 1. "TH07,Start Threshold of Area 7" hexmask.long.word 0x28 10.--19. 1. "TH08,Start Threshold of Area 8" newline hexmask.long.word 0x28 0.--9. 1. "TH09,Start Threshold of Area 9" line.long 0x2C "GAMR_AREA4,Gamma R Correction Block Area Setting Register 4" hexmask.long.word 0x2C 20.--29. 1. "TH10,Start Threshold of Area 10" hexmask.long.word 0x2C 10.--19. 1. "TH11,Start Threshold of Area 11" newline hexmask.long.word 0x2C 0.--9. 1. "TH12,Start Threshold of Area 12" line.long 0x30 "GAMR_AREA5,Gamma R Correction Block Area Setting Register 5" hexmask.long.word 0x30 20.--29. 1. "TH13,Start Threshold of Area 13" hexmask.long.word 0x30 10.--19. 1. "TH14,Start Threshold of Area 14" newline hexmask.long.word 0x30 0.--9. 1. "TH15,Start Threshold of Area 15" group.long 0x13C0++0x17 line.long 0x0 "OUT_VLATCH,Output Control Block Register Update Control Register" bitfld.long 0x0 0. "VEN,Control of Output Control Module Register Value Reflection to Internal Operations" "0: Disable reflection of register values to..,1: Enable reflection of register values to internal.." line.long 0x4 "OUT_SET,Output Control Block Output Interface Register" bitfld.long 0x4 28. "ENDIANON,Bit Endian Control" "0: Descending order (little endian),1: Ascending order (big endian)" bitfld.long 0x4 24. "SWAPON,Pixel Order Control" "0: RGB order,1: BGR order" newline bitfld.long 0x4 12.--13. "FORMAT,Output Format Select" "0: RGB888 — select RGB888 as dither output format,1: RGB666 — select RGB666 as dither output format,?,?" bitfld.long 0x4 8.--9. "FRQSEL,Clock Frequency Division Control" "0: No frequency division parallel RGB,1: Setting prohibited,?,?" newline bitfld.long 0x4 4. "DIRSEL,Scan Direction Select of Serial RGB Format" "0: Forward scan,1: Reverse scan" bitfld.long 0x4 0.--1. "PHASE,Data Output Delay Control in Serial RGB Format" "0: 0 cycle,1: 1 cycle,?,?" line.long 0x8 "OUT_BRIGHT1,Output Control Block Brightness Correction Register 1" hexmask.long.word 0x8 0.--9. 1. "BRTG,Brightness Adjustment of G Signal" line.long 0xC "OUT_BRIGHT2,Output Control Block Brightness Correction Register 2" hexmask.long.word 0xC 16.--25. 1. "BRTB,Brightness Adjustment of B Signal" hexmask.long.word 0xC 0.--9. 1. "BRTR,Brightness Adjustment of R Signal" line.long 0x10 "OUT_CONTRAST,Output Control Block Contrast Correction Register" hexmask.long.byte 0x10 16.--23. 1. "CONTG,Contrast Adjustment of G Signal" hexmask.long.byte 0x10 8.--15. 1. "CONTB,Contrast Adjustment of B Signal" newline hexmask.long.byte 0x10 0.--7. 1. "CONTR,Contrast Adjustment of R Signal" line.long 0x14 "OUT_PDTHA,Output Control Block Panel Dither Correction Register" bitfld.long 0x14 20.--21. "SEL,Operation Mode" "0: Truncate,1: Round-off,?,?" bitfld.long 0x14 16.--17. "FORM,Output Format Select" "0: RGB888; select RGB888 or serial RGB as output..,1: RGB666; select RGB666 as output interface format,?,?" newline bitfld.long 0x14 12.--13. "PA,Pattern Value (A) of 2×2 Pattern Dither" "0,1,2,3" bitfld.long 0x14 8.--9. "PB,Pattern Value (B) of 2×2 Pattern Dither" "0,1,2,3" newline bitfld.long 0x14 4.--5. "PC,Pattern Value (C) of 2×2 Pattern Dither" "0,1,2,3" bitfld.long 0x14 0.--1. "PD,Pattern Value (D) of 2×2 Pattern Dither" "0,1,2,3" group.long 0x13E4++0x3 line.long 0x0 "OUT_CLKPHASE,Output Control Block Output Phase Control Register" bitfld.long 0x0 12. "FRONTGAM,Correction Control" "0: Process brightness/contrast correction followed..,1: Process gamma correction followed by.." bitfld.long 0x0 8. "LCDEDGE,LCD_DATA Output Phase Control" "0: Synchronize output with rising edge of LCD_CLK,1: Synchronize output with falling edge of LCD_CLK" newline bitfld.long 0x0 6. "TCON0EDGE,LCD_TCON0 Output Phase Control" "0: Synchronize output with rising edge of LCD_CLK,1: Synchronize output with falling edge of LCD_CLK" bitfld.long 0x0 5. "TCON1EDGE,LCD_TCON1 Output Phase Control" "0: Synchronize output with rising edge of LCD_CLK,1: Synchronize output with falling edge of LCD_CLK" newline bitfld.long 0x0 4. "TCON2EDGE,LCD_TCON2 Output Phase Control" "0: Synchronize output with rising edge of LCD_CLK,1: Synchronize output with falling edge of LCD_CLK" bitfld.long 0x0 3. "TCON3EDGE,LCD_TCON3 Output Phase Control" "0: Synchronize output with rising edge of LCD_CLK,1: Synchronize output with falling edge of LCD_CLK" group.long 0x1404++0x27 line.long 0x0 "TCON_TIM,TCON Reference Timing Setting Register" hexmask.long.word 0x0 16.--26. 1. "HALF,Vertical Synchronization Signal Generation Change Timing" hexmask.long.word 0x0 0.--10. 1. "OFFSET,Horizontal Synchronization Signal Generation Reference Timing" line.long 0x4 "TCON_STVA1,TCON Vertical Timing Setting Register x1" hexmask.long.word 0x4 16.--26. 1. "VS,Vertical Synchronization Signal STVx1 First Change Timing" hexmask.long.word 0x4 0.--10. 1. "VW,Vertical Synchronization Signal STVx1 Second Change Timing" line.long 0x8 "TCON_STVA2,TCON Vertical Timing Setting Register x2" bitfld.long 0x8 4. "INV,Vertical Synchronization Signal STVx Polarity Inversion Control" "0: Do not invert,1: Invert" bitfld.long 0x8 0.--2. "SEL,Output Signal Select Control for LCD_TCON0/LCD_TCON1 Pin" "0: STVA,1: STVB,?,?,?,?,?,?" line.long 0xC "TCON_STVB1,TCON Vertical Timing Setting Register x1" hexmask.long.word 0xC 16.--26. 1. "VS,Vertical Synchronization Signal STVx1 First Change Timing" hexmask.long.word 0xC 0.--10. 1. "VW,Vertical Synchronization Signal STVx1 Second Change Timing" line.long 0x10 "TCON_STVB2,TCON Vertical Timing Setting Register x2" bitfld.long 0x10 4. "INV,Vertical Synchronization Signal STVx Polarity Inversion Control" "0: Do not invert,1: Invert" bitfld.long 0x10 0.--2. "SEL,Output Signal Select Control for LCD_TCON0/LCD_TCON1 Pin" "0: STVA,1: STVB,?,?,?,?,?,?" line.long 0x14 "TCON_STHA1,TCON Horizontal Timing Setting Register x1" hexmask.long.word 0x14 16.--26. 1. "HS,Horizontal Synchronization Signal STHx1 First Change Timing" hexmask.long.word 0x14 0.--10. 1. "HW,Horizontal Synchronization Signal STHx1 Second Change Timing" line.long 0x18 "TCON_STHA2,TCON Horizontal Timing Setting Register x2" bitfld.long 0x18 8. "HSSEL,Horizontal Synchronization Signal STHx Reference Timing Control" "0: Select input horizontal synchronization signal..,1: Select offset specified in TCON_TIM.OFFSET[10:0].." bitfld.long 0x18 4. "INV,Horizontal Synchronization Signal STHx Polarity Inversion Control" "0: Do not invert,1: Invert" newline bitfld.long 0x18 0.--2. "SEL,Output Signal Select Control for LCD_TCON2/LCD_TCON3 Pin" "0: STVA,1: STVB,?,?,?,?,?,?" line.long 0x1C "TCON_STHB1,TCON Horizontal Timing Setting Register x1" hexmask.long.word 0x1C 16.--26. 1. "HS,Horizontal Synchronization Signal STHx1 First Change Timing" hexmask.long.word 0x1C 0.--10. 1. "HW,Horizontal Synchronization Signal STHx1 Second Change Timing" line.long 0x20 "TCON_STHB2,TCON Horizontal Timing Setting Register x2" bitfld.long 0x20 8. "HSSEL,Horizontal Synchronization Signal STHx Reference Timing Control" "0: Select input horizontal synchronization signal..,1: Select offset specified in TCON_TIM.OFFSET[10:0].." bitfld.long 0x20 4. "INV,Horizontal Synchronization Signal STHx Polarity Inversion Control" "0: Do not invert,1: Invert" newline bitfld.long 0x20 0.--2. "SEL,Output Signal Select Control for LCD_TCON2/LCD_TCON3 Pin" "0: STVA,1: STVB,?,?,?,?,?,?" line.long 0x24 "TCON_DE,TCON Data Enable Polarity Setting Register" bitfld.long 0x24 0. "INV,Data Enable Signal DE Polarity Inversion Control" "0: Do not invert,1: Invert" group.long 0x1440++0xB line.long 0x0 "SYSCNT_DTCTEN,System Control Block State Detection Control Register" bitfld.long 0x0 2. "L2UNDFDTC,Graphics 2 Underflow Detection Control" "0: Disable detection of graphics 2 underflow,1: Enable detection of graphics 2 underflow" bitfld.long 0x0 1. "L1UNDFDTC,Graphics 1 Underflow Detection Control" "0: Disable detection of graphics 1 underflow,1: Enable detection of graphics 1 underflow" newline bitfld.long 0x0 0. "VPOSDTC,Specified Line Detection Control" "0: Disable detection of specified line,1: Enable detection of specified line" line.long 0x4 "SYSCNT_INTEN,System Control Block Interrupt Request Enable Control Register" bitfld.long 0x4 2. "L2UNDFINTEN,Interrupt Request Signal GLCDC_L2UNDF Enable Control" "0: Disable GLCDC_L2UNDF output,1: Enable GLCDC_L2UNDF output" bitfld.long 0x4 1. "L1UNDFINTEN,Interrupt Request Signal GLCDC_L1UNDF Enable Control" "0: Disable GLCDC_L1UNDF output,1: Enable GLCDC_L1UNDF output" newline bitfld.long 0x4 0. "VPOSINTEN,Interrupt Request Signal GLCDC_VPOS Enable Control" "0: Disable GLCDC_VPOS output,1: Enable GLCDC_VPOS output" line.long 0x8 "SYSCNT_STCLR,System Control Block Status Clear Register" bitfld.long 0x8 2. "L2UNDFCLR,Graphics 2 Underflow Detection Flag Clear" "0: No operation,1: Clears the graphics 2 underflow detection flag" bitfld.long 0x8 1. "L1UNDFCLR,Graphics 1 Underflow Detection Flag Clear" "0: No operation,1: Clear the graphics 1 underflow detection flag" newline bitfld.long 0x8 0. "VPOSCLR,Graphics 2 Specified Line Detection Flag Clear" "0: No operation,1: Clear the graphics 2 specified line detection flag" rgroup.long 0x144C++0x3 line.long 0x0 "SYSCNT_STMON,System Control Block Status Monitor Register" bitfld.long 0x0 2. "L2UNDF,Graphics 2 Underflow Detection Flag" "0: No underflow detected in graphics 2,1: Underflow detected in graphics 2" bitfld.long 0x0 1. "L1UNDF,Graphics 1 Underflow Detection Flag" "0: No underflow detected in graphics 1,1: Underflow detected in graphics 1" newline bitfld.long 0x0 0. "VPOS,Graphics 2 Specified Line Detection Flag" "0: Specified line notification not detected in..,1: Specified line notification detected in graphics 2" group.long 0x1450++0x3 line.long 0x0 "SYSCNT_PANEL_CLK,System Control Block Version and Panel Clock Control Register" hexmask.long.word 0x0 16.--31. 1. "VER,Version Information" bitfld.long 0x0 12. "PIXSEL,Pixel Clock Select Control" "0: Select no frequency division parallel RGB,1: Select quarter frequency serial RGB This setting.." newline bitfld.long 0x0 8. "CLKSEL,Panel Clock Supply Source Control" "0: Select external clock (LCD_EXTCLK),1: Select LCDCLK" bitfld.long 0x0 6. "CLKEN,Panel Clock Output Enable Control" "0: Disable panel clock output,1: Enable panel clock output Before changing the.." newline hexmask.long.byte 0x0 0.--5. 1. "DCDR,Clock Division Ratio Setting Control" tree.end tree "GLCDC_NS" base ad:0x50342000 repeat 256. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "GR1_CLUT0$1,Color Palette" hexmask.long.byte 0x0 24.--31. 1. "A,Alpha blending value of color palette n plane for graphics m plane. Unsigned 8-bit integer." hexmask.long.byte 0x0 16.--23. 1. "R,R value of color palette n plane for graphics m plane. Unsigned 8-bit integer." newline hexmask.long.byte 0x0 8.--15. 1. "G,G value of color palette n plane for graphics m plane. Unsigned 8-bit integer." hexmask.long.byte 0x0 0.--7. 1. "B,B value of color palette n plane for graphics m plane. Unsigned 8-bit integer." repeat.end repeat 256. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x400)++0x3 line.long 0x0 "GR1_CLUT1$1,Color Palette" hexmask.long.byte 0x0 24.--31. 1. "A,Alpha blending value of color palette n plane for graphics m plane. Unsigned 8-bit integer." hexmask.long.byte 0x0 16.--23. 1. "R,R value of color palette n plane for graphics m plane. Unsigned 8-bit integer." newline hexmask.long.byte 0x0 8.--15. 1. "G,G value of color palette n plane for graphics m plane. Unsigned 8-bit integer." hexmask.long.byte 0x0 0.--7. 1. "B,B value of color palette n plane for graphics m plane. Unsigned 8-bit integer." repeat.end repeat 256. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x800)++0x3 line.long 0x0 "GR2_CLUT0$1,Color Palette" hexmask.long.byte 0x0 24.--31. 1. "A,Alpha blending value of color palette n plane for graphics m plane. Unsigned 8-bit integer." hexmask.long.byte 0x0 16.--23. 1. "R,R value of color palette n plane for graphics m plane. Unsigned 8-bit integer." newline hexmask.long.byte 0x0 8.--15. 1. "G,G value of color palette n plane for graphics m plane. Unsigned 8-bit integer." hexmask.long.byte 0x0 0.--7. 1. "B,B value of color palette n plane for graphics m plane. Unsigned 8-bit integer." repeat.end repeat 256. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC00)++0x3 line.long 0x0 "GR2_CLUT1$1,Color Palette" hexmask.long.byte 0x0 24.--31. 1. "A,Alpha blending value of color palette n plane for graphics m plane. Unsigned 8-bit integer." hexmask.long.byte 0x0 16.--23. 1. "R,R value of color palette n plane for graphics m plane. Unsigned 8-bit integer." newline hexmask.long.byte 0x0 8.--15. 1. "G,G value of color palette n plane for graphics m plane. Unsigned 8-bit integer." hexmask.long.byte 0x0 0.--7. 1. "B,B value of color palette n plane for graphics m plane. Unsigned 8-bit integer." repeat.end group.long 0x1000++0x17 line.long 0x0 "BG_EN,Background Plane Setting Operation Control Register" bitfld.long 0x0 16. "SWRST,Software Reset Control" "0: Place entire module in software reset state,1: Release entire module from software reset state" bitfld.long 0x0 8. "VEN,Control of GLCDC Internal Register Value Reflection to Internal Operations" "0: Disable GLCDC register values from being..,1: Enable GLCDC register values to be reflected in.." newline bitfld.long 0x0 0. "EN,Background Plane Operation Enable" "0: Disable background plane operation,1: Enable background plane operation" line.long 0x4 "BG_PERI,Background Plane Setting Free-Running Period Register" hexmask.long.word 0x4 16.--26. 1. "FV,Background Plane Vertical Synchronization Signal Period" hexmask.long.word 0x4 0.--10. 1. "FH,Background Plane Horizontal Synchronization Signal Period" line.long 0x8 "BG_SYNC,Background Plane Setting Synchronization Position Register" hexmask.long.byte 0x8 16.--19. 1. "VP,Background Plane Vertical Synchronization Assertion Position" hexmask.long.byte 0x8 0.--3. 1. "HP,Background Plane Horizontal Synchronization Signal Assertion Position" line.long 0xC "BG_VSIZE,Background Plane Setting Full Image Vertical Size Register" hexmask.long.word 0xC 16.--26. 1. "VP,Background Plane Vertical Valid Pixel Start Position" hexmask.long.word 0xC 0.--10. 1. "VW,Background Plane Vertical Valid Pixel Width" line.long 0x10 "BG_HSIZE,Background Plane Setting Full Image Horizontal Size Register" hexmask.long.word 0x10 16.--26. 1. "HP,Background Plane Horizontal Valid Pixel Start Position" hexmask.long.word 0x10 0.--10. 1. "HW,Background Plane Horizontal Valid Pixel Width" line.long 0x14 "BG_BGC,Background Plane Setting Background Color Register" hexmask.long.byte 0x14 16.--23. 1. "R,Background Plane Valid Pixel Area R Value" hexmask.long.byte 0x14 8.--15. 1. "G,Background Plane Valid Pixel Area G Value" newline hexmask.long.byte 0x14 0.--7. 1. "B,Background Plane Valid Pixel Area B Value" rgroup.long 0x1018++0x3 line.long 0x0 "BG_MON,Background Plane Setting Status Monitor Register" bitfld.long 0x0 16. "SWRST,Entire Module SW Reset State Monitor" "0: Entire module is in software reset state,1: Entire module is released from software reset.." bitfld.long 0x0 8. "VEN,Entire Module Internal Operation Reflection Control Signal Monitor" "0: Signal for controlling reflection of the..,1: Signal for controlling reflection of the.." newline bitfld.long 0x0 0. "EN,Background Plane Operation Monitor" "0: Operation is stopped,1: Operation is in progress" repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1100)++0x3 line.long 0x0 "GR$1_VEN,Graphics %s Register Update Control Register" bitfld.long 0x0 0. "PVEN,This bit is cleared to 0 by an internal source." "0: Disable reflection of register values to..,1: Enable reflection of register values to internal.." repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1104)++0x3 line.long 0x0 "GR$1_FLMRD,Graphics %s Frame Buffer Read Control Register" bitfld.long 0x0 0. "RENB,Graphics Data Read Enable" "0: Disable reading,1: Enable reading" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1108)++0x3 line.long 0x0 "GR$1_FLM1,Graphics %s Frame Buffer Control Register 1" bitfld.long 0x0 0.--1. "BSTMD,Burst Transfer Control for Graphics Data Access" "0: Setting prohibited,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x110C)++0x3 line.long 0x0 "GR$1_FLM2,Graphics %s Frame Buffer Control Register 2" hexmask.long 0x0 0.--31. 1. "BASE,Base Address for Accessing Graphics Data" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1110)++0x3 line.long 0x0 "GR$1_FLM3,Graphics %s Frame Buffer Control Register 3" hexmask.long.word 0x0 16.--31. 1. "LNOFF,Macro Line Offset Address for Accessing Graphics Data" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1118)++0x3 line.long 0x0 "GR$1_FLM5,Graphics %s Frame Buffer Control Register 5" hexmask.long.word 0x0 16.--26. 1. "LNNUM,Number of Lines Per Frame for Accessing Graphics Data" hexmask.long.word 0x0 0.--15. 1. "DATANUM,Number of Data Transfer Times Per Line for Accessing Graphics Data" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x111C)++0x3 line.long 0x0 "GR$1_FLM6,Graphics %s Frame Buffer Control Register 6" bitfld.long 0x0 28.--30. "FORMAT,Data Format for Accessing Graphics Data" "0: RGB565 (16 bits/pixel),1: RGB888 (32 bits/pixel 8 bits on the MSB side are..,?,?,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1120)++0x3 line.long 0x0 "GR$1_AB1,Graphics %s Alpha Blending Control Register 1" bitfld.long 0x0 12. "ARCON,Rectangular Area Alpha Blending Control" "0: Turn blending off,1: Turn blending on" bitfld.long 0x0 8. "ARCDISPON,Image Area Border Display Control for Rectangular Area Alpha Blending" "0: Turn display off,1: Turn display on" newline bitfld.long 0x0 4. "GRCDISPON,Graphics Image Area Border Display Control" "0: Turn display off,1: Turn display on" bitfld.long 0x0 0.--1. "DISPSEL,Graphics Display Plane Control" "0: Background color display (value set in the..,1: Lower-layer graphics display,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1124)++0x3 line.long 0x0 "GR$1_AB2,Graphics %s Alpha Blending Control Register 2" hexmask.long.word 0x0 16.--26. 1. "GRCVS,Vertical Start Position of Graphics Image Area" hexmask.long.word 0x0 0.--10. 1. "GRCVW,Vertical Width of Graphics Image Area" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1128)++0x3 line.long 0x0 "GR$1_AB3,Graphics %s Alpha Blending Control Register 3" hexmask.long.word 0x0 16.--26. 1. "GRCHS,Horizontal Start Position of Graphics Image Area" hexmask.long.word 0x0 0.--10. 1. "GRCHW,Horizontal Width of Graphics Image Area" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x112C)++0x3 line.long 0x0 "GR$1_AB4,Graphics %s Alpha Blending Control Register 4" hexmask.long.word 0x0 16.--26. 1. "ARCVS,Vertical Start Position of Rectangular Area Alpha Blending Image Area" hexmask.long.word 0x0 0.--10. 1. "ARCVW,Vertical Width of Rectangular Area Alpha Blending Image Area" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1130)++0x3 line.long 0x0 "GR$1_AB5,Graphics %s Alpha Blending Control Register 5" hexmask.long.word 0x0 16.--26. 1. "ARCHS,Horizontal Start Position of Rectangular Area Alpha Blending Image Area" hexmask.long.word 0x0 0.--10. 1. "ARCHW,Horizontal Width of Rectangular Area Alpha Blending Image Area" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1134)++0x3 line.long 0x0 "GR$1_AB6,Graphics %s Alpha Blending Control Register 6" hexmask.long.word 0x0 16.--24. 1. "ARCCOEF,Alpha Coefficient for Alpha Blending in Rectangular Area" hexmask.long.byte 0x0 0.--7. 1. "ARCRATE,Frame Rate for Alpha Blending in Rectangular Area" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1138)++0x3 line.long 0x0 "GR$1_AB7,Graphics %s Alpha Blending Control Register 7" hexmask.long.byte 0x0 16.--23. 1. "ARCDEF,Initial Alpha Value for Alpha Blending in Rectangular Area" bitfld.long 0x0 0. "CKON,RGB-Index Chroma-Key Processing Control" "0: Disable chroma-key processing,1: Enable chroma-key processing" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x113C)++0x3 line.long 0x0 "GR$1_AB8,Graphics %s Alpha Blending Control Register 8" hexmask.long.byte 0x0 16.--23. 1. "CKKG,G Signal for RGB-Index Chroma-Key Processing" hexmask.long.byte 0x0 8.--15. 1. "CKKB,B Signal for RGB-Index Chroma-Key Processing" newline hexmask.long.byte 0x0 0.--7. 1. "CKKR,R Signal for RGB-Index Chroma-Key Processing" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1140)++0x3 line.long 0x0 "GR$1_AB9,Graphics %s Alpha Blending Control Register 9" hexmask.long.byte 0x0 24.--31. 1. "CKA,A Value after RGB-Index Chroma-Key Processing Replacement" hexmask.long.byte 0x0 16.--23. 1. "CKG,G Value after RGB-Index Chroma-Key Processing Replacement" newline hexmask.long.byte 0x0 8.--15. 1. "CKB,B Value after RGB-Index Chroma-Key Processing Replacement" hexmask.long.byte 0x0 0.--7. 1. "CKR,R Value after RGB-Index Chroma-Key Processing Replacement" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x114C)++0x3 line.long 0x0 "GR$1_BASE,Graphics %s Background Color Control Register" hexmask.long.byte 0x0 16.--23. 1. "G,Background Color G Value" hexmask.long.byte 0x0 8.--15. 1. "B,Background Color B Value" newline hexmask.long.byte 0x0 0.--7. 1. "R,Background Color R Value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2+0x1150)++0x3 line.long 0x0 "GR$1_CLUTINT,Graphics %s CLUT Table Interrupt Control Register" bitfld.long 0x0 16. "SEL,CLUT Table Control" "0: Select CLUT table 0,1: Select CLUT table 1" hexmask.long.word 0x0 0.--10. 1. "LINE,Number of Detection Lines" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) rgroup.long ($2+0x1154)++0x3 line.long 0x0 "GR$1_MON,Graphics %s Status Monitor Register" bitfld.long 0x0 16. "UNDFLST,Underflow Status Monitor" "0: No underflow occurred in internal operations,1: Underflow occurred in internal operations" bitfld.long 0x0 0. "ARCST,Status Monitor for Alpha Blending in Rectangular Area" "0: Fade-in/fade-out not in progress,1: Fade-in/fade-out in progress" repeat.end group.long 0x1300++0x3B line.long 0x0 "GAMG_LATCH,Gamma G Register Update Control Register" bitfld.long 0x0 0. "VEN,Control of Gamma Correction × Module Register Value Reflection to Internal Operations" "0: Disable reflection of register values to..,1: Enable reflection of register values to internal.." line.long 0x4 "GAM_SW,Gamma Correction Block Function Switch Register" bitfld.long 0x4 0. "GAMON,Gamma Correction On/Off Control" "0: Turn off gamma correction,1: Turn on gamma correction" line.long 0x8 "GAMG_LUT1,Gamma G Correction Block Table Setting Register 1" hexmask.long.word 0x8 16.--26. 1. "GAIN00,Gain Value of Area 0" hexmask.long.word 0x8 0.--10. 1. "GAIN01,Gain Value of Area 1" line.long 0xC "GAMG_LUT2,Gamma G Correction Block Table Setting Register 2" hexmask.long.word 0xC 16.--26. 1. "GAIN02,Gain Value of Area 2" hexmask.long.word 0xC 0.--10. 1. "GAIN03,Gain Value of Area 3" line.long 0x10 "GAMG_LUT3,Gamma G Correction Block Table Setting Register 3" hexmask.long.word 0x10 16.--26. 1. "GAIN04,Gain Value of Area 4" hexmask.long.word 0x10 0.--10. 1. "GAIN05,Gain Value of Area 5" line.long 0x14 "GAMG_LUT4,Gamma G Correction Block Table Setting Register 4" hexmask.long.word 0x14 16.--26. 1. "GAIN06,Gain Value of Area 6" hexmask.long.word 0x14 0.--10. 1. "GAIN07,Gain Value of Area 7" line.long 0x18 "GAMG_LUT5,Gamma G Correction Block Table Setting Register 5" hexmask.long.word 0x18 16.--26. 1. "GAIN08,Gain Value of Area 8" hexmask.long.word 0x18 0.--10. 1. "GAIN09,Gain Value of Area 9" line.long 0x1C "GAMG_LUT6,Gamma G Correction Block Table Setting Register 6" hexmask.long.word 0x1C 16.--26. 1. "GAIN10,Gain Value of Area 10" hexmask.long.word 0x1C 0.--10. 1. "GAIN11,Gain Value of Area 11" line.long 0x20 "GAMG_LUT7,Gamma G Correction Block Table Setting Register 7" hexmask.long.word 0x20 16.--26. 1. "GAIN12,Gain Value of Area 12" hexmask.long.word 0x20 0.--10. 1. "GAIN13,Gain Value of Area 13" line.long 0x24 "GAMG_LUT8,Gamma G Correction Block Table Setting Register 8" hexmask.long.word 0x24 16.--26. 1. "GAIN14,Gain Value of Area 14" hexmask.long.word 0x24 0.--10. 1. "GAIN15,Gain Value of Area 15" line.long 0x28 "GAMG_AREA1,Gamma G Correction Block Area Setting Register 1" hexmask.long.word 0x28 20.--29. 1. "TH01,Start Threshold of Area 1" hexmask.long.word 0x28 10.--19. 1. "TH02,Start Threshold of Area 2" newline hexmask.long.word 0x28 0.--9. 1. "TH03,Start Threshold of Area 3" line.long 0x2C "GAMG_AREA2,Gamma G Correction Block Area Setting Register 2" hexmask.long.word 0x2C 20.--29. 1. "TH04,Start Threshold of Area 4" hexmask.long.word 0x2C 10.--19. 1. "TH05,Start Threshold of Area 5" newline hexmask.long.word 0x2C 0.--9. 1. "TH06,Start Threshold of Area 6" line.long 0x30 "GAMG_AREA3,Gamma G Correction Block Area Setting Register 3" hexmask.long.word 0x30 20.--29. 1. "TH07,Start Threshold of Area 7" hexmask.long.word 0x30 10.--19. 1. "TH08,Start Threshold of Area 8" newline hexmask.long.word 0x30 0.--9. 1. "TH09,Start Threshold of Area 9" line.long 0x34 "GAMG_AREA4,Gamma G Correction Block Area Setting Register 4" hexmask.long.word 0x34 20.--29. 1. "TH10,Start Threshold of Area 10" hexmask.long.word 0x34 10.--19. 1. "TH11,Start Threshold of Area 11" newline hexmask.long.word 0x34 0.--9. 1. "TH12,Start Threshold of Area 12" line.long 0x38 "GAMG_AREA5,Gamma G Correction Block Area Setting Register 5" hexmask.long.word 0x38 20.--29. 1. "TH13,Start Threshold of Area 13" hexmask.long.word 0x38 10.--19. 1. "TH14,Start Threshold of Area 14" newline hexmask.long.word 0x38 0.--9. 1. "TH15,Start Threshold of Area 15" group.long 0x1340++0x3 line.long 0x0 "GAMB_LATCH,Gamma B Register Update Control Register" bitfld.long 0x0 0. "VEN,Control of Gamma Correction × Module Register Value Reflection to Internal Operations" "0: Disable reflection of register values to..,1: Enable reflection of register values to internal.." group.long 0x1348++0x33 line.long 0x0 "GAMB_LUT1,Gamma B Correction Block Table Setting Register 1" hexmask.long.word 0x0 16.--26. 1. "GAIN00,Gain Value of Area 0" hexmask.long.word 0x0 0.--10. 1. "GAIN01,Gain Value of Area 1" line.long 0x4 "GAMB_LUT2,Gamma B Correction Block Table Setting Register 2" hexmask.long.word 0x4 16.--26. 1. "GAIN02,Gain Value of Area 2" hexmask.long.word 0x4 0.--10. 1. "GAIN03,Gain Value of Area 3" line.long 0x8 "GAMB_LUT3,Gamma B Correction Block Table Setting Register 3" hexmask.long.word 0x8 16.--26. 1. "GAIN04,Gain Value of Area 4" hexmask.long.word 0x8 0.--10. 1. "GAIN05,Gain Value of Area 5" line.long 0xC "GAMB_LUT4,Gamma B Correction Block Table Setting Register 4" hexmask.long.word 0xC 16.--26. 1. "GAIN06,Gain Value of Area 6" hexmask.long.word 0xC 0.--10. 1. "GAIN07,Gain Value of Area 7" line.long 0x10 "GAMB_LUT5,Gamma B Correction Block Table Setting Register 5" hexmask.long.word 0x10 16.--26. 1. "GAIN08,Gain Value of Area 8" hexmask.long.word 0x10 0.--10. 1. "GAIN09,Gain Value of Area 9" line.long 0x14 "GAMB_LUT6,Gamma B Correction Block Table Setting Register 6" hexmask.long.word 0x14 16.--26. 1. "GAIN10,Gain Value of Area 10" hexmask.long.word 0x14 0.--10. 1. "GAIN11,Gain Value of Area 11" line.long 0x18 "GAMB_LUT7,Gamma B Correction Block Table Setting Register 7" hexmask.long.word 0x18 16.--26. 1. "GAIN12,Gain Value of Area 12" hexmask.long.word 0x18 0.--10. 1. "GAIN13,Gain Value of Area 13" line.long 0x1C "GAMB_LUT8,Gamma B Correction Block Table Setting Register 8" hexmask.long.word 0x1C 16.--26. 1. "GAIN14,Gain Value of Area 14" hexmask.long.word 0x1C 0.--10. 1. "GAIN15,Gain Value of Area 15" line.long 0x20 "GAMB_AREA1,Gamma B Correction Block Area Setting Register 1" hexmask.long.word 0x20 20.--29. 1. "TH01,Start Threshold of Area 1" hexmask.long.word 0x20 10.--19. 1. "TH02,Start Threshold of Area 2" newline hexmask.long.word 0x20 0.--9. 1. "TH03,Start Threshold of Area 3" line.long 0x24 "GAMB_AREA2,Gamma B Correction Block Area Setting Register 2" hexmask.long.word 0x24 20.--29. 1. "TH04,Start Threshold of Area 4" hexmask.long.word 0x24 10.--19. 1. "TH05,Start Threshold of Area 5" newline hexmask.long.word 0x24 0.--9. 1. "TH06,Start Threshold of Area 6" line.long 0x28 "GAMB_AREA3,Gamma B Correction Block Area Setting Register 3" hexmask.long.word 0x28 20.--29. 1. "TH07,Start Threshold of Area 7" hexmask.long.word 0x28 10.--19. 1. "TH08,Start Threshold of Area 8" newline hexmask.long.word 0x28 0.--9. 1. "TH09,Start Threshold of Area 9" line.long 0x2C "GAMB_AREA4,Gamma B Correction Block Area Setting Register 4" hexmask.long.word 0x2C 20.--29. 1. "TH10,Start Threshold of Area 10" hexmask.long.word 0x2C 10.--19. 1. "TH11,Start Threshold of Area 11" newline hexmask.long.word 0x2C 0.--9. 1. "TH12,Start Threshold of Area 12" line.long 0x30 "GAMB_AREA5,Gamma B Correction Block Area Setting Register 5" hexmask.long.word 0x30 20.--29. 1. "TH13,Start Threshold of Area 13" hexmask.long.word 0x30 10.--19. 1. "TH14,Start Threshold of Area 14" newline hexmask.long.word 0x30 0.--9. 1. "TH15,Start Threshold of Area 15" group.long 0x1380++0x3 line.long 0x0 "GAMR_LATCH,Gamma R Register Update Control Register" bitfld.long 0x0 0. "VEN,Control of Gamma Correction × Module Register Value Reflection to Internal Operations" "0: Disable reflection of register values to..,1: Enable reflection of register values to internal.." group.long 0x1388++0x33 line.long 0x0 "GAMR_LUT1,Gamma R Correction Block Table Setting Register 1" hexmask.long.word 0x0 16.--26. 1. "GAIN00,Gain Value of Area 0" hexmask.long.word 0x0 0.--10. 1. "GAIN01,Gain Value of Area 1" line.long 0x4 "GAMR_LUT2,Gamma R Correction Block Table Setting Register 2" hexmask.long.word 0x4 16.--26. 1. "GAIN02,Gain Value of Area 2" hexmask.long.word 0x4 0.--10. 1. "GAIN03,Gain Value of Area 3" line.long 0x8 "GAMR_LUT3,Gamma R Correction Block Table Setting Register 3" hexmask.long.word 0x8 16.--26. 1. "GAIN04,Gain Value of Area 4" hexmask.long.word 0x8 0.--10. 1. "GAIN05,Gain Value of Area 5" line.long 0xC "GAMR_LUT4,Gamma R Correction Block Table Setting Register 4" hexmask.long.word 0xC 16.--26. 1. "GAIN06,Gain Value of Area 6" hexmask.long.word 0xC 0.--10. 1. "GAIN07,Gain Value of Area 7" line.long 0x10 "GAMR_LUT5,Gamma R Correction Block Table Setting Register 5" hexmask.long.word 0x10 16.--26. 1. "GAIN08,Gain Value of Area 8" hexmask.long.word 0x10 0.--10. 1. "GAIN09,Gain Value of Area 9" line.long 0x14 "GAMR_LUT6,Gamma R Correction Block Table Setting Register 6" hexmask.long.word 0x14 16.--26. 1. "GAIN10,Gain Value of Area 10" hexmask.long.word 0x14 0.--10. 1. "GAIN11,Gain Value of Area 11" line.long 0x18 "GAMR_LUT7,Gamma R Correction Block Table Setting Register 7" hexmask.long.word 0x18 16.--26. 1. "GAIN12,Gain Value of Area 12" hexmask.long.word 0x18 0.--10. 1. "GAIN13,Gain Value of Area 13" line.long 0x1C "GAMR_LUT8,Gamma R Correction Block Table Setting Register 8" hexmask.long.word 0x1C 16.--26. 1. "GAIN14,Gain Value of Area 14" hexmask.long.word 0x1C 0.--10. 1. "GAIN15,Gain Value of Area 15" line.long 0x20 "GAMR_AREA1,Gamma R Correction Block Area Setting Register 1" hexmask.long.word 0x20 20.--29. 1. "TH01,Start Threshold of Area 1" hexmask.long.word 0x20 10.--19. 1. "TH02,Start Threshold of Area 2" newline hexmask.long.word 0x20 0.--9. 1. "TH03,Start Threshold of Area 3" line.long 0x24 "GAMR_AREA2,Gamma R Correction Block Area Setting Register 2" hexmask.long.word 0x24 20.--29. 1. "TH04,Start Threshold of Area 4" hexmask.long.word 0x24 10.--19. 1. "TH05,Start Threshold of Area 5" newline hexmask.long.word 0x24 0.--9. 1. "TH06,Start Threshold of Area 6" line.long 0x28 "GAMR_AREA3,Gamma R Correction Block Area Setting Register 3" hexmask.long.word 0x28 20.--29. 1. "TH07,Start Threshold of Area 7" hexmask.long.word 0x28 10.--19. 1. "TH08,Start Threshold of Area 8" newline hexmask.long.word 0x28 0.--9. 1. "TH09,Start Threshold of Area 9" line.long 0x2C "GAMR_AREA4,Gamma R Correction Block Area Setting Register 4" hexmask.long.word 0x2C 20.--29. 1. "TH10,Start Threshold of Area 10" hexmask.long.word 0x2C 10.--19. 1. "TH11,Start Threshold of Area 11" newline hexmask.long.word 0x2C 0.--9. 1. "TH12,Start Threshold of Area 12" line.long 0x30 "GAMR_AREA5,Gamma R Correction Block Area Setting Register 5" hexmask.long.word 0x30 20.--29. 1. "TH13,Start Threshold of Area 13" hexmask.long.word 0x30 10.--19. 1. "TH14,Start Threshold of Area 14" newline hexmask.long.word 0x30 0.--9. 1. "TH15,Start Threshold of Area 15" group.long 0x13C0++0x17 line.long 0x0 "OUT_VLATCH,Output Control Block Register Update Control Register" bitfld.long 0x0 0. "VEN,Control of Output Control Module Register Value Reflection to Internal Operations" "0: Disable reflection of register values to..,1: Enable reflection of register values to internal.." line.long 0x4 "OUT_SET,Output Control Block Output Interface Register" bitfld.long 0x4 28. "ENDIANON,Bit Endian Control" "0: Descending order (little endian),1: Ascending order (big endian)" bitfld.long 0x4 24. "SWAPON,Pixel Order Control" "0: RGB order,1: BGR order" newline bitfld.long 0x4 12.--13. "FORMAT,Output Format Select" "0: RGB888 — select RGB888 as dither output format,1: RGB666 — select RGB666 as dither output format,?,?" bitfld.long 0x4 8.--9. "FRQSEL,Clock Frequency Division Control" "0: No frequency division parallel RGB,1: Setting prohibited,?,?" newline bitfld.long 0x4 4. "DIRSEL,Scan Direction Select of Serial RGB Format" "0: Forward scan,1: Reverse scan" bitfld.long 0x4 0.--1. "PHASE,Data Output Delay Control in Serial RGB Format" "0: 0 cycle,1: 1 cycle,?,?" line.long 0x8 "OUT_BRIGHT1,Output Control Block Brightness Correction Register 1" hexmask.long.word 0x8 0.--9. 1. "BRTG,Brightness Adjustment of G Signal" line.long 0xC "OUT_BRIGHT2,Output Control Block Brightness Correction Register 2" hexmask.long.word 0xC 16.--25. 1. "BRTB,Brightness Adjustment of B Signal" hexmask.long.word 0xC 0.--9. 1. "BRTR,Brightness Adjustment of R Signal" line.long 0x10 "OUT_CONTRAST,Output Control Block Contrast Correction Register" hexmask.long.byte 0x10 16.--23. 1. "CONTG,Contrast Adjustment of G Signal" hexmask.long.byte 0x10 8.--15. 1. "CONTB,Contrast Adjustment of B Signal" newline hexmask.long.byte 0x10 0.--7. 1. "CONTR,Contrast Adjustment of R Signal" line.long 0x14 "OUT_PDTHA,Output Control Block Panel Dither Correction Register" bitfld.long 0x14 20.--21. "SEL,Operation Mode" "0: Truncate,1: Round-off,?,?" bitfld.long 0x14 16.--17. "FORM,Output Format Select" "0: RGB888; select RGB888 or serial RGB as output..,1: RGB666; select RGB666 as output interface format,?,?" newline bitfld.long 0x14 12.--13. "PA,Pattern Value (A) of 2×2 Pattern Dither" "0,1,2,3" bitfld.long 0x14 8.--9. "PB,Pattern Value (B) of 2×2 Pattern Dither" "0,1,2,3" newline bitfld.long 0x14 4.--5. "PC,Pattern Value (C) of 2×2 Pattern Dither" "0,1,2,3" bitfld.long 0x14 0.--1. "PD,Pattern Value (D) of 2×2 Pattern Dither" "0,1,2,3" group.long 0x13E4++0x3 line.long 0x0 "OUT_CLKPHASE,Output Control Block Output Phase Control Register" bitfld.long 0x0 12. "FRONTGAM,Correction Control" "0: Process brightness/contrast correction followed..,1: Process gamma correction followed by.." bitfld.long 0x0 8. "LCDEDGE,LCD_DATA Output Phase Control" "0: Synchronize output with rising edge of LCD_CLK,1: Synchronize output with falling edge of LCD_CLK" newline bitfld.long 0x0 6. "TCON0EDGE,LCD_TCON0 Output Phase Control" "0: Synchronize output with rising edge of LCD_CLK,1: Synchronize output with falling edge of LCD_CLK" bitfld.long 0x0 5. "TCON1EDGE,LCD_TCON1 Output Phase Control" "0: Synchronize output with rising edge of LCD_CLK,1: Synchronize output with falling edge of LCD_CLK" newline bitfld.long 0x0 4. "TCON2EDGE,LCD_TCON2 Output Phase Control" "0: Synchronize output with rising edge of LCD_CLK,1: Synchronize output with falling edge of LCD_CLK" bitfld.long 0x0 3. "TCON3EDGE,LCD_TCON3 Output Phase Control" "0: Synchronize output with rising edge of LCD_CLK,1: Synchronize output with falling edge of LCD_CLK" group.long 0x1404++0x27 line.long 0x0 "TCON_TIM,TCON Reference Timing Setting Register" hexmask.long.word 0x0 16.--26. 1. "HALF,Vertical Synchronization Signal Generation Change Timing" hexmask.long.word 0x0 0.--10. 1. "OFFSET,Horizontal Synchronization Signal Generation Reference Timing" line.long 0x4 "TCON_STVA1,TCON Vertical Timing Setting Register x1" hexmask.long.word 0x4 16.--26. 1. "VS,Vertical Synchronization Signal STVx1 First Change Timing" hexmask.long.word 0x4 0.--10. 1. "VW,Vertical Synchronization Signal STVx1 Second Change Timing" line.long 0x8 "TCON_STVA2,TCON Vertical Timing Setting Register x2" bitfld.long 0x8 4. "INV,Vertical Synchronization Signal STVx Polarity Inversion Control" "0: Do not invert,1: Invert" bitfld.long 0x8 0.--2. "SEL,Output Signal Select Control for LCD_TCON0/LCD_TCON1 Pin" "0: STVA,1: STVB,?,?,?,?,?,?" line.long 0xC "TCON_STVB1,TCON Vertical Timing Setting Register x1" hexmask.long.word 0xC 16.--26. 1. "VS,Vertical Synchronization Signal STVx1 First Change Timing" hexmask.long.word 0xC 0.--10. 1. "VW,Vertical Synchronization Signal STVx1 Second Change Timing" line.long 0x10 "TCON_STVB2,TCON Vertical Timing Setting Register x2" bitfld.long 0x10 4. "INV,Vertical Synchronization Signal STVx Polarity Inversion Control" "0: Do not invert,1: Invert" bitfld.long 0x10 0.--2. "SEL,Output Signal Select Control for LCD_TCON0/LCD_TCON1 Pin" "0: STVA,1: STVB,?,?,?,?,?,?" line.long 0x14 "TCON_STHA1,TCON Horizontal Timing Setting Register x1" hexmask.long.word 0x14 16.--26. 1. "HS,Horizontal Synchronization Signal STHx1 First Change Timing" hexmask.long.word 0x14 0.--10. 1. "HW,Horizontal Synchronization Signal STHx1 Second Change Timing" line.long 0x18 "TCON_STHA2,TCON Horizontal Timing Setting Register x2" bitfld.long 0x18 8. "HSSEL,Horizontal Synchronization Signal STHx Reference Timing Control" "0: Select input horizontal synchronization signal..,1: Select offset specified in TCON_TIM.OFFSET[10:0].." bitfld.long 0x18 4. "INV,Horizontal Synchronization Signal STHx Polarity Inversion Control" "0: Do not invert,1: Invert" newline bitfld.long 0x18 0.--2. "SEL,Output Signal Select Control for LCD_TCON2/LCD_TCON3 Pin" "0: STVA,1: STVB,?,?,?,?,?,?" line.long 0x1C "TCON_STHB1,TCON Horizontal Timing Setting Register x1" hexmask.long.word 0x1C 16.--26. 1. "HS,Horizontal Synchronization Signal STHx1 First Change Timing" hexmask.long.word 0x1C 0.--10. 1. "HW,Horizontal Synchronization Signal STHx1 Second Change Timing" line.long 0x20 "TCON_STHB2,TCON Horizontal Timing Setting Register x2" bitfld.long 0x20 8. "HSSEL,Horizontal Synchronization Signal STHx Reference Timing Control" "0: Select input horizontal synchronization signal..,1: Select offset specified in TCON_TIM.OFFSET[10:0].." bitfld.long 0x20 4. "INV,Horizontal Synchronization Signal STHx Polarity Inversion Control" "0: Do not invert,1: Invert" newline bitfld.long 0x20 0.--2. "SEL,Output Signal Select Control for LCD_TCON2/LCD_TCON3 Pin" "0: STVA,1: STVB,?,?,?,?,?,?" line.long 0x24 "TCON_DE,TCON Data Enable Polarity Setting Register" bitfld.long 0x24 0. "INV,Data Enable Signal DE Polarity Inversion Control" "0: Do not invert,1: Invert" group.long 0x1440++0xB line.long 0x0 "SYSCNT_DTCTEN,System Control Block State Detection Control Register" bitfld.long 0x0 2. "L2UNDFDTC,Graphics 2 Underflow Detection Control" "0: Disable detection of graphics 2 underflow,1: Enable detection of graphics 2 underflow" bitfld.long 0x0 1. "L1UNDFDTC,Graphics 1 Underflow Detection Control" "0: Disable detection of graphics 1 underflow,1: Enable detection of graphics 1 underflow" newline bitfld.long 0x0 0. "VPOSDTC,Specified Line Detection Control" "0: Disable detection of specified line,1: Enable detection of specified line" line.long 0x4 "SYSCNT_INTEN,System Control Block Interrupt Request Enable Control Register" bitfld.long 0x4 2. "L2UNDFINTEN,Interrupt Request Signal GLCDC_L2UNDF Enable Control" "0: Disable GLCDC_L2UNDF output,1: Enable GLCDC_L2UNDF output" bitfld.long 0x4 1. "L1UNDFINTEN,Interrupt Request Signal GLCDC_L1UNDF Enable Control" "0: Disable GLCDC_L1UNDF output,1: Enable GLCDC_L1UNDF output" newline bitfld.long 0x4 0. "VPOSINTEN,Interrupt Request Signal GLCDC_VPOS Enable Control" "0: Disable GLCDC_VPOS output,1: Enable GLCDC_VPOS output" line.long 0x8 "SYSCNT_STCLR,System Control Block Status Clear Register" bitfld.long 0x8 2. "L2UNDFCLR,Graphics 2 Underflow Detection Flag Clear" "0: No operation,1: Clears the graphics 2 underflow detection flag" bitfld.long 0x8 1. "L1UNDFCLR,Graphics 1 Underflow Detection Flag Clear" "0: No operation,1: Clear the graphics 1 underflow detection flag" newline bitfld.long 0x8 0. "VPOSCLR,Graphics 2 Specified Line Detection Flag Clear" "0: No operation,1: Clear the graphics 2 specified line detection flag" rgroup.long 0x144C++0x3 line.long 0x0 "SYSCNT_STMON,System Control Block Status Monitor Register" bitfld.long 0x0 2. "L2UNDF,Graphics 2 Underflow Detection Flag" "0: No underflow detected in graphics 2,1: Underflow detected in graphics 2" bitfld.long 0x0 1. "L1UNDF,Graphics 1 Underflow Detection Flag" "0: No underflow detected in graphics 1,1: Underflow detected in graphics 1" newline bitfld.long 0x0 0. "VPOS,Graphics 2 Specified Line Detection Flag" "0: Specified line notification not detected in..,1: Specified line notification detected in graphics 2" group.long 0x1450++0x3 line.long 0x0 "SYSCNT_PANEL_CLK,System Control Block Version and Panel Clock Control Register" hexmask.long.word 0x0 16.--31. 1. "VER,Version Information" bitfld.long 0x0 12. "PIXSEL,Pixel Clock Select Control" "0: Select no frequency division parallel RGB,1: Select quarter frequency serial RGB This setting.." newline bitfld.long 0x0 8. "CLKSEL,Panel Clock Supply Source Control" "0: Select external clock (LCD_EXTCLK),1: Select LCDCLK" bitfld.long 0x0 6. "CLKEN,Panel Clock Output Enable Control" "0: Disable panel clock output,1: Enable panel clock output Before changing the.." newline hexmask.long.byte 0x0 0.--5. 1. "DCDR,Clock Division Ratio Setting Control" tree.end tree.end tree "GPT (General PWM Timer)" base ad:0x0 tree "GPT16 (General PWM 16-bit Timer)" tree "GPT168" base ad:0x40322800 group.long 0x4++0x7 line.long 0x0 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x0 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x0 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x0 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x0 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x0 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x4 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x4 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x4 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x4 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x4 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x4 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x1F line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" group.long 0x38++0x3 line.long 0x0 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x0 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x0 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x0 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" group.long 0x70++0x17 line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x3 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" tree.end tree "GPT168_NS" base ad:0x50322800 group.long 0x4++0x7 line.long 0x0 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x0 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x0 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x0 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x0 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x0 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x4 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x4 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x4 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x4 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x4 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x4 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x1F line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" group.long 0x38++0x3 line.long 0x0 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x0 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x0 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x0 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" group.long 0x70++0x17 line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x3 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" tree.end tree "GPT169" base ad:0x40322900 group.long 0x4++0x7 line.long 0x0 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x0 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x0 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x0 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x0 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x0 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x4 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x4 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x4 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x4 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x4 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x4 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x1F line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" group.long 0x38++0x3 line.long 0x0 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x0 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x0 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x0 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" group.long 0x70++0x17 line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x3 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" tree.end tree "GPT169_NS" base ad:0x50322900 group.long 0x4++0x7 line.long 0x0 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x0 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x0 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x0 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x0 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x0 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x0 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x4 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x4 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x4 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x4 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x4 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x4 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x4 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x1F line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" group.long 0x38++0x3 line.long 0x0 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x0 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x0 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x0 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" group.long 0x70++0x17 line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x3 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" tree.end tree "GPT1610" base ad:0x40322A00 group.long 0x0++0x3 line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" group.long 0x30++0x7 line.long 0x0 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x0 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x0 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x0 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x0 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x0 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x0 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x0 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x0 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x4 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x4 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x4 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x4 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x4 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x4 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x4 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x4 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x4 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x4 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x4 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x4 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x4 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x4 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x4 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" group.long 0x3C++0x7 line.long 0x0 "GTST,General PWM Timer Status Register" bitfld.long 0x0 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x0 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x0 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x0 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x0 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x0 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x0 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x0 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x0 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x0 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x0 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x0 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x0 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x0 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x0 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x0 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x0 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x4 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x4 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x4 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x4 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x4 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x4 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x4 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x4 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x4 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x4 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x4 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x4 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xBC++0x3 line.long 0x0 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x0 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x0 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x0 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT1610_NS" base ad:0x50322A00 group.long 0x0++0x3 line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" group.long 0x30++0x7 line.long 0x0 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x0 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x0 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x0 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x0 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x0 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x0 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x0 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x0 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x4 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x4 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x4 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x4 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x4 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x4 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x4 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x4 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x4 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x4 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x4 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x4 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x4 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x4 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x4 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" group.long 0x3C++0x7 line.long 0x0 "GTST,General PWM Timer Status Register" bitfld.long 0x0 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x0 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x0 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x0 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x0 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x0 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x0 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x0 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x0 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x0 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x0 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x0 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x0 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x0 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x0 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x0 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x0 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x4 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x4 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x4 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x4 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x4 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x4 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x4 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x4 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x4 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x4 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x4 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x4 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xBC++0x3 line.long 0x0 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x0 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x0 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x0 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT1611" base ad:0x40322B00 group.long 0x0++0x3 line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" group.long 0x30++0x7 line.long 0x0 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x0 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x0 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x0 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x0 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x0 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x0 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x0 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x0 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x4 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x4 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x4 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x4 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x4 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x4 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x4 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x4 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x4 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x4 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x4 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x4 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x4 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x4 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x4 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" group.long 0x3C++0x7 line.long 0x0 "GTST,General PWM Timer Status Register" bitfld.long 0x0 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x0 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x0 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x0 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x0 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x0 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x0 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x0 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x0 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x0 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x0 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x0 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x0 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x0 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x0 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x0 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x0 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x4 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x4 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x4 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x4 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x4 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x4 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x4 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x4 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x4 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x4 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x4 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x4 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xBC++0x3 line.long 0x0 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x0 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x0 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x0 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT1611_NS" base ad:0x50322B00 group.long 0x0++0x3 line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" group.long 0x30++0x7 line.long 0x0 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x0 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x0 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x0 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x0 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x0 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x0 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x0 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x0 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x4 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x4 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x4 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x4 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x4 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x4 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x4 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x4 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x4 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x4 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x4 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x4 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x4 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x4 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x4 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" group.long 0x3C++0x7 line.long 0x0 "GTST,General PWM Timer Status Register" bitfld.long 0x0 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x0 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x0 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x0 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x0 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x0 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x0 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x0 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x0 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x0 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x0 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x0 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x0 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x0 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x0 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x0 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x0 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x4 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x4 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x4 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x4 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x4 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x4 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x4 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x4 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x4 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x4 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x4 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x4 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xBC++0x3 line.long 0x0 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x0 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x0 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x0 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT1612" base ad:0x40322C00 group.long 0x0++0x3 line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" group.long 0x30++0x7 line.long 0x0 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x0 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x0 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x0 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x0 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x0 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x0 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x0 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x0 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x4 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x4 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x4 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x4 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x4 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x4 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x4 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x4 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x4 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x4 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x4 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x4 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x4 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x4 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x4 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" group.long 0x3C++0x7 line.long 0x0 "GTST,General PWM Timer Status Register" bitfld.long 0x0 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x0 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x0 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x0 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x0 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x0 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x0 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x0 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x0 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x0 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x0 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x0 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x0 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x0 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x0 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x0 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x0 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x4 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x4 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x4 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x4 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x4 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x4 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x4 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x4 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x4 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x4 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x4 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x4 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xBC++0x3 line.long 0x0 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x0 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x0 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x0 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT1612_NS" base ad:0x50322C00 group.long 0x0++0x3 line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" group.long 0x30++0x7 line.long 0x0 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x0 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x0 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x0 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x0 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x0 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x0 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x0 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x0 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x4 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x4 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x4 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x4 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x4 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x4 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x4 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x4 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x4 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x4 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x4 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x4 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x4 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x4 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x4 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" group.long 0x3C++0x7 line.long 0x0 "GTST,General PWM Timer Status Register" bitfld.long 0x0 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x0 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x0 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x0 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x0 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x0 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x0 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x0 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x0 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x0 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x0 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x0 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x0 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x0 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x0 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x0 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x0 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x4 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x4 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x4 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x4 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x4 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x4 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x4 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x4 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x4 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x4 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x4 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x4 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xBC++0x3 line.long 0x0 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x0 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x0 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x0 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT1613" base ad:0x40322D00 group.long 0x0++0x3 line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" group.long 0x30++0x7 line.long 0x0 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x0 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x0 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x0 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x0 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x0 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x0 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x0 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x0 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x4 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x4 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x4 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x4 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x4 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x4 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x4 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x4 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x4 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x4 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x4 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x4 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x4 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x4 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x4 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" group.long 0x3C++0x7 line.long 0x0 "GTST,General PWM Timer Status Register" bitfld.long 0x0 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x0 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x0 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x0 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x0 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x0 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x0 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x0 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x0 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x0 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x0 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x0 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x0 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x0 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x0 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x0 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x0 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x4 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x4 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x4 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x4 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x4 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x4 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x4 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x4 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x4 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x4 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x4 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x4 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xBC++0x3 line.long 0x0 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x0 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x0 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x0 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT1613_NS" base ad:0x50322D00 group.long 0x0++0x3 line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" group.long 0x30++0x7 line.long 0x0 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x0 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x0 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x0 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x0 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x0 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x0 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x0 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x0 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x4 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x4 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x4 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x4 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x4 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x4 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x4 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x4 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x4 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x4 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x4 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x4 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x4 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x4 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x4 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" group.long 0x3C++0x7 line.long 0x0 "GTST,General PWM Timer Status Register" bitfld.long 0x0 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x0 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x0 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x0 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x0 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x0 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x0 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x0 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x0 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x0 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x0 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x0 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x0 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x0 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x0 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x0 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x0 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x4 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x4 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x4 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x4 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x4 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x4 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x4 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x4 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x4 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x4 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x4 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x4 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xBC++0x3 line.long 0x0 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x0 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x0 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x0 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree.end tree "GPT32 (General PWM 32-bit Timer)" tree "GPT320" base ad:0x40322000 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" line.long 0x2C "GTST,General PWM Timer Status Register" bitfld.long 0x2C 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x2C 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x2C 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x2C 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x2C 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x30 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x30 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x30 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x70++0x1F line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" line.long 0x18 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x18 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x1C "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x7 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" line.long 0x4 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x4 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x4 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x4 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT320_NS" base ad:0x50322000 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" line.long 0x2C "GTST,General PWM Timer Status Register" bitfld.long 0x2C 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x2C 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x2C 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x2C 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x2C 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x30 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x30 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x30 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x70++0x1F line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" line.long 0x18 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x18 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x1C "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x7 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" line.long 0x4 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x4 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x4 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x4 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT321" base ad:0x40322100 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" line.long 0x2C "GTST,General PWM Timer Status Register" bitfld.long 0x2C 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x2C 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x2C 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x2C 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x2C 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x30 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x30 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x30 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x70++0x1F line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" line.long 0x18 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x18 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x1C "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x7 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" line.long 0x4 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x4 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x4 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x4 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT321_NS" base ad:0x50322100 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" line.long 0x2C "GTST,General PWM Timer Status Register" bitfld.long 0x2C 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x2C 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x2C 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x2C 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x2C 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x30 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x30 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x30 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x70++0x1F line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" line.long 0x18 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x18 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x1C "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x7 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" line.long 0x4 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x4 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x4 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x4 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT322" base ad:0x40322200 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" line.long 0x2C "GTST,General PWM Timer Status Register" bitfld.long 0x2C 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x2C 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x2C 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x2C 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x2C 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x30 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x30 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x30 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x70++0x1F line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" line.long 0x18 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x18 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x1C "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x7 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" line.long 0x4 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x4 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x4 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x4 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT322_NS" base ad:0x50322200 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" line.long 0x2C "GTST,General PWM Timer Status Register" bitfld.long 0x2C 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x2C 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x2C 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x2C 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x2C 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x30 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x30 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x30 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x70++0x1F line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" line.long 0x18 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x18 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x1C "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x7 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" line.long 0x4 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x4 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x4 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x4 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT323" base ad:0x40322300 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" line.long 0x2C "GTST,General PWM Timer Status Register" bitfld.long 0x2C 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x2C 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x2C 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x2C 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x2C 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x30 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x30 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x30 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x70++0x1F line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" line.long 0x18 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x18 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x1C "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x7 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" line.long 0x4 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x4 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x4 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x4 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT323_NS" base ad:0x50322300 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" line.long 0x2C "GTST,General PWM Timer Status Register" bitfld.long 0x2C 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x2C 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x2C 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x2C 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x2C 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x30 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x30 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x30 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x70++0x1F line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" line.long 0x18 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x18 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x1C "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x7 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" line.long 0x4 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x4 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x4 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x4 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT324" base ad:0x40322400 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" line.long 0x2C "GTST,General PWM Timer Status Register" bitfld.long 0x2C 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x2C 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x2C 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x2C 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x2C 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x30 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x30 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x30 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x70++0x1F line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" line.long 0x18 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x18 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x1C "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x7 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" line.long 0x4 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x4 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x4 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x4 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT324_NS" base ad:0x50322400 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" line.long 0x2C "GTST,General PWM Timer Status Register" bitfld.long 0x2C 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x2C 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x2C 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x2C 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x2C 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x30 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x30 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x30 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x70++0x1F line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" line.long 0x18 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x18 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x1C "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x7 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" line.long 0x4 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x4 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x4 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x4 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT325" base ad:0x40322500 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" line.long 0x2C "GTST,General PWM Timer Status Register" bitfld.long 0x2C 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x2C 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x2C 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x2C 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x2C 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x30 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x30 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x30 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x70++0x1F line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" line.long 0x18 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x18 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x1C "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x7 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" line.long 0x4 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x4 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x4 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x4 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT325_NS" base ad:0x50322500 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" line.long 0x2C "GTST,General PWM Timer Status Register" bitfld.long 0x2C 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x2C 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x2C 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x2C 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x2C 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x30 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x30 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x30 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x70++0x1F line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" line.long 0x18 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x18 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x1C "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x7 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" line.long 0x4 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x4 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x4 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x4 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT326" base ad:0x40322600 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" line.long 0x2C "GTST,General PWM Timer Status Register" bitfld.long 0x2C 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x2C 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x2C 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x2C 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x2C 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x30 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x30 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x30 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x70++0x1F line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" line.long 0x18 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x18 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x1C "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x7 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" line.long 0x4 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x4 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x4 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x4 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT326_NS" base ad:0x50322600 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" line.long 0x2C "GTST,General PWM Timer Status Register" bitfld.long 0x2C 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x2C 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x2C 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x2C 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x2C 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x30 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x30 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x30 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x70++0x1F line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" line.long 0x18 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x18 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x1C "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x7 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" line.long 0x4 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x4 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x4 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x4 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT327" base ad:0x40322700 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" line.long 0x2C "GTST,General PWM Timer Status Register" bitfld.long 0x2C 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x2C 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x2C 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x2C 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x2C 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x30 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x30 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x30 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x70++0x1F line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" line.long 0x18 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x18 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x1C "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x7 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" line.long 0x4 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x4 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x4 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x4 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree "GPT327_NS" base ad:0x50322700 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" bitfld.long 0x0 4. "CMNWP,Common Register Write Disabled" "0: Write to the register is enabled,1: Write to the register is disabled" newline bitfld.long 0x0 3. "CLRWP,GTCLR.CCLR Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 2. "STPWP,GTSTP.CSTOP Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" newline bitfld.long 0x0 1. "STRWP,GTSTR.CSTRT Bit Write Disable" "0: Write to the bit is enabled,1: Write to the bit is disabled" bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" newline bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start" line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" newline bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop" wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" newline bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register" bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTH input,1: Counter start enabled at the ELC_GPTH input" newline bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTG input,1: Counter start enabled at the ELC_GPTG input" bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTF input,1: Counter start enabled at the ELC_GPTF input" newline bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTE input,1: Counter start enabled at the ELC_GPTE input" bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input" newline bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input" bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input" newline bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input" bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." newline bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 7. "SSGTRGDF,GTETRGD Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 6. "SSGTRGDR,GTETRGD Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 5. "SSGTRGCF,GTETRGC Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 4. "SSGTRGCR,GTETRGC Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register" bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTH input,1: Counter stop enabled at the ELC_GPTH input" newline bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTG input,1: Counter stop enabled at the ELC_GPTG input" bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTF input,1: Counter stop enabled at the ELC_GPTF input" newline bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTE input,1: Counter stop enabled at the ELC_GPTE input" bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input" newline bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input" bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input" newline bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input" bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." newline bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 7. "PSGTRGDF,GTETRGD Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 6. "PSGTRGDR,GTETRGD Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 5. "PSGTRGCF,GTETRGC Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 4. "PSGTRGCR,GTETRGC Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register" bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTH input,1: Counter clear enabled at the ELC_GPTH input" newline bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTG input,1: Counter clear enabled at the ELC_GPTG input" bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTF input,1: Counter clear enabled at the ELC_GPTF input" newline bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTE input,1: Counter clear enabled at the ELC_GPTE input" bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input" newline bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input" bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input" newline bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input" bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." newline bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." bitfld.long 0x8 7. "CSGTRGDF,GTETRGD Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 6. "CSGTRGDR,GTETRGD Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 5. "CSGTRGCF,GTETRGC Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 4. "CSGTRGCR,GTETRGC Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTH input,1: Counter count up enabled at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTG input,1: Counter count up enabled at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTF input,1: Counter count up enabled at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTE input,1: Counter count up enabled at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." newline bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 7. "USGTRGDF,GTETRGD Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 6. "USGTRGDR,GTETRGD Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 5. "USGTRGCF,GTETRGC Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 4. "USGTRGCR,GTETRGC Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTG input,1: Counter count down enabled at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTF input,1: Counter count down enabled at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTE input,1: Counter count down enabled at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 7. "DSGTRGDF,GTETRGD Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 6. "DSGTRGDR,GTETRGD Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 5. "DSGTRGCF,GTETRGC Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 4. "DSGTRGCR,GTETRGC Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTH..,1: GTCCRA input capture enabled at the ELC_GPTH input" bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTG..,1: GTCCRA input capture enabled at the ELC_GPTG input" newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTF..,1: GTCCRA input capture enabled at the ELC_GPTF input" bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTE..,1: GTCCRA input capture enabled at the ELC_GPTE input" newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input" bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input" newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input" bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input" newline bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 7. "ASGTRGDF,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 6. "ASGTRGDR,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 5. "ASGTRGCF,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 4. "ASGTRGCR,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTH..,1: GTCCRB input capture enabled at the ELC_GPTH input" bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTG..,1: GTCCRB input capture enabled at the ELC_GPTG input" newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTF..,1: GTCCRB input capture enabled at the ELC_GPTF input" bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTE..,1: GTCCRB input capture enabled at the ELC_GPTE input" newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input" bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input" newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input" bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input" newline bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 7. "BSGTRGDF,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 6. "BSGTRGDR,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 5. "BSGTRGCF,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 4. "BSGTRGCR,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.." line.long 0x1C "GTCR,General PWM Timer Control Register" hexmask.long.byte 0x1C 23.--26. 1. "TPCS,Timer Prescaler Select" bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?" bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.." newline bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?" newline bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up" line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled" newline bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?" bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.." bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled" bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?" newline bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.." newline bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled" bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.." newline bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Group A output disable request is selected,1: Group B output disable request is selected,?,?" line.long 0x2C "GTST,General PWM Timer Status Register" bitfld.long 0x2C 31. "PCF,Period Count Function Finish Flag" "0: No period count function finish has occurred,1: A period count function finish has occurred" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.." newline rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated" newline bitfld.long 0x2C 19. "ADTRBDF,GTADTRB Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." bitfld.long 0x2C 18. "ADTRBUF,GTADTRB Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRB register compare match has occurred..,1: A GTADTRB register compare match has occurred in.." newline bitfld.long 0x2C 17. "ADTRADF,GTADTRA Register Compare Match (Down-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." bitfld.long 0x2C 16. "ADTRAUF,GTADTRA Register Compare Match (Up-Counting) A/D Conversion Start Request Flag" "0: No GTADTRA register compare match has occurred..,1: A GTADTRA register compare match has occurred in.." newline rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward" bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred" newline bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred" bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated" newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated" bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated" newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated" bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 30. "ADTDB,GTADTRB Register Double Buffer Operation" "0: Single buffer operation (GTADTBRB --> GTADTRB),1: Double buffer operation (GTADTDBRB --> GTADTBRB.." bitfld.long 0x30 28.--29. "ADTTB,GTADTRB Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 26. "ADTDA,GTADTRA Register Double Buffer Operation" "0: Single buffer operation (GTADTBRA --> GTADTRA),1: Double buffer operation (GTADTDBRA --> GTADTBRA.." bitfld.long 0x30 24.--25. "ADTTA,GTADTRA Register Buffer Transfer Timing Select" "0: In triangle wave mode no transfer. In saw-wave..,1: In triangle wave mode transfer at crest. In..,?,?" newline bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1" bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?" newline bitfld.long 0x30 2. "BD2,GTADTRA/GTADTRB Registers Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" newline bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" group.long 0x70++0x1F line.long 0x0 "GTADTRA,A/D Conversion Start Request Timing Register A" line.long 0x4 "GTADTBRA,A/D Conversion Start Request Timing Buffer Register A" line.long 0x8 "GTADTDBRA,A/D Conversion Start Request Timing Double-Buffer Register A" line.long 0xC "GTADTRB,A/D Conversion Start Request Timing Register B" line.long 0x10 "GTADTBRB,A/D Conversion Start Request Timing Buffer Register B" line.long 0x14 "GTADTDBRB,A/D Conversion Start Request Timing Double-Buffer Register B" line.long 0x18 "GTDTCR,General PWM Timer Dead Time Control Register" bitfld.long 0x18 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.." line.long 0x1C "GTDVU,General PWM Timer Dead Time Value Register U" group.long 0xA4++0x3 line.long 0x0 "GTADSMR,General PWM Timer A/D Conversion Start Request Signal Monitoring Register" bitfld.long 0x0 24. "ADSMEN1,A/D Conversion Start Request Signal Monitor 1 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 16.--17. "ADSMS1,A/D Conversion Start Request Signal Monitor 1 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" newline bitfld.long 0x0 8. "ADSMEN0,A/D Conversion Start Request Signal Monitor 0 Output Enabling" "0: Output of A/D conversion start request signal..,1: Output of A/D conversion start request signal.." bitfld.long 0x0 0.--1. "ADSMS0,A/D Conversion Start Request Signal Monitor 0 Selection" "0: A/D conversion start request signal generated by..,1: A/D conversion start request signal generated by..,?,?" group.long 0xB8++0x7 line.long 0x0 "GTICLF,General PWM Timer Inter Channel Logical Operation Function Setting Register" hexmask.long.byte 0x0 20.--25. 1. "ICLFSELD,Inter Channel Signal D Select" bitfld.long 0x0 16.--18. "ICLFB,GTIOCnB Output Logical Operation Function Select" "0: B (no delay),1: NOT B (no delay),?,?,?,?,?,?" newline hexmask.long.byte 0x0 4.--9. 1. "ICLFSELC,Inter Channel Signal C Select" bitfld.long 0x0 0.--2. "ICLFA,GTIOCnA Output Logical Operation Function Select" "0: A (no delay),1: NOT A (no delay),?,?,?,?,?,?" line.long 0x4 "GTPC,General PWM Timer Period Count Register" hexmask.long.word 0x4 16.--27. 1. "PCNT,Period Counter" bitfld.long 0x4 8. "ASTP,Automatic Stop Function Enable" "0: Automatic stop function is disabled,1: Automatic stop function is enabled" newline bitfld.long 0x4 0. "PCEN,Period Count Function Enable" "0: Period count function is disabled,1: Period count function is enabled" group.long 0xD0++0x7 line.long 0x0 "GTSECSR,General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register" bitfld.long 0x0 13. "SECSEL13,Channel 13 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 12. "SECSEL12,Channel 12 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 11. "SECSEL11,Channel 11 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 10. "SECSEL10,Channel 10 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 5. "SECSEL5,Channel 5 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 4. "SECSEL4,Channel 4 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 3. "SECSEL3,Channel 3 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 2. "SECSEL2,Channel 2 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" newline bitfld.long 0x0 1. "SECSEL1,Channel 1 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" bitfld.long 0x0 0. "SECSEL0,Channel 0 Operation Enable Bit Simultaneous Control Channel Select" "0: Disable simultaneous control,1: Enable simultaneous control" line.long 0x4 "GTSECR,General PWM Timer Operation Enable Bit Simultaneous Control Register" bitfld.long 0x4 24. "SPCD,Period Count Function Simultaneous Disable" "0: Disable simultaneous disabling period count..,1: Disable period count function simultaneously" bitfld.long 0x4 16. "SPCE,Period Count Function Simultaneous Enable" "0: Disable simultaneous enabling period count..,1: Enable period count function simultaneously" newline bitfld.long 0x4 10. "SBDAD,GTADTR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTADTR buffer..,1: Disable GTADTR register buffer operations.." bitfld.long 0x4 9. "SBDPD,GTPR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTPR buffer..,1: Disable GTPR register buffer operations.." newline bitfld.long 0x4 8. "SBDCD,GTCCR Register Buffer Operation Simultaneous Disable" "0: Disable simultaneous disabling GTCCR buffer..,1: Disable GTCCR register buffer operations.." bitfld.long 0x4 2. "SBDAE,GTADTR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTADTR buffer..,1: Enable GTADTR register buffer operations.." newline bitfld.long 0x4 1. "SBDPE,GTPR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTPR buffer..,1: Enable GTPR register buffer operations.." bitfld.long 0x4 0. "SBDCE,GTCCR Register Buffer Operation Simultaneous Enable" "0: Disable simultaneous enabling GTCCR buffer..,1: Enable GTCCR register buffer operations.." tree.end tree.end tree.end tree "ICU (Interrupt Controller)" base ad:0x0 tree "ICU" base ad:0x4000C000 group.word 0x100++0x1 line.word 0x0 "NMIER,Non-Maskable Interrupt Enable Register" bitfld.word 0x0 15. "LUEN" "0: Disabled,1: Enabled" bitfld.word 0x0 13. "CMEN" "0: Disabled,1: Enabled" newline bitfld.word 0x0 12. "BUSEN" "0: Disabled,1: Enabled" bitfld.word 0x0 7. "NMIEN,NMI Pin Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "OSTEN,Main Clock Oscillation Stop Detection Interrupt Enable" "0: Disabled,1: Enabled" bitfld.word 0x0 3. "PVD2EN,Voltage monitor 2 Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "PVD1EN,Voltage monitor 1 Interrupt Enable" "0: Disabled,1: Enabled" bitfld.word 0x0 1. "WDTEN,WDT Underflow/Refresh Error Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 0. "IWDTEN,IWDT Underflow/Refresh Error Interrupt Enable" "0: Disabled,1: Enabled" group.word 0x110++0x1 line.word 0x0 "NMICLR,Non-Maskable Interrupt Status Clear Register" bitfld.word 0x0 15. "LUCLR" "0: No effect,1: Clear the NMISR.LUST flag" bitfld.word 0x0 13. "CMCLR" "0: No effect,1: Clear the NMISR.CMST flag" newline bitfld.word 0x0 12. "BUSCLR" "0: No effect,1: Clear the NMISR.BUSST flag" bitfld.word 0x0 7. "NMICLR,NMI Pin Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.NMIST flag" newline bitfld.word 0x0 6. "OSTCLR,Oscillation Stop Detection Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.OSTST flag" bitfld.word 0x0 3. "PVD2CLR,Voltage Monitor 2 Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.PVD2ST flag." newline bitfld.word 0x0 2. "PVD1CLR,Voltage Monitor 1 Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.PVD1ST flag" bitfld.word 0x0 1. "WDTCLR,WDT Underflow/Refresh Error Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.WDTST flag" newline bitfld.word 0x0 0. "IWDTCLR,IWDT Underflow/Refresh Error Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.IWDTST flag" rgroup.word 0x120++0x1 line.word 0x0 "NMISR,Non-Maskable Interrupt Status Register" bitfld.word 0x0 15. "LUST" "0: Interrupt not requested,1: Interrupt requested" bitfld.word 0x0 13. "CMST" "0: Interrupt not requested,1: Interrupt requested" newline bitfld.word 0x0 12. "BUSST,Bus Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested" bitfld.word 0x0 7. "NMIST,NMI Pin Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested" newline bitfld.word 0x0 6. "OSTST,Main Clock Oscillation Stop Detection Interrupt Status Flag" "0: Interrupt not requested for main clock..,1: Interrupt requested for main clock oscillation.." bitfld.word 0x0 3. "PVD2ST,Voltage Monitor 2 Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested" newline bitfld.word 0x0 2. "PVD1ST,Voltage Monitor 1 Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested" bitfld.word 0x0 1. "WDTST,WDT Underflow/Refresh Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested" newline bitfld.word 0x0 0. "IWDTST,IWDT Underflow/Refresh Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested" group.long 0x1A0++0x7 line.long 0x0 "WUPEN0,Wake Up Interrupt Enable Register 0" bitfld.long 0x0 31. "IIC0WUPEN,IIC0 Address Match Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by IIC0..,1: Deep Sleep/Software Standby Mode returns by IIC0.." bitfld.long 0x0 30. "AGT1CBWUPEN,AGT1 Compare Match B Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by AGT1..,1: Deep Sleep/Software Standby Mode returns by AGT1.." newline bitfld.long 0x0 29. "AGT1CAWUPEN,AGT1 Compare Match A Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by AGT1..,1: Deep Sleep/Software Standby Mode returns by AGT1.." bitfld.long 0x0 28. "AGT1UDWUPEN,AGT1 Underflow Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by AGT1..,1: Deep Sleep/Software Standby Mode returns by AGT1.." newline bitfld.long 0x0 27. "USBFS0WUPEN,USBFS Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by..,1: Deep Sleep/Software Standby Mode returns by.." bitfld.long 0x0 25. "RTCPRDWUPEN,RTC Period Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by RTC..,1: Deep Sleep/Software Standby Mode returns by RTC.." newline bitfld.long 0x0 24. "RTCALMWUPEN,RTC Alarm Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by RTC..,1: Deep Sleep/Software Standby Mode returns by RTC.." bitfld.long 0x0 20. "VBATTWUPEN,VBATT Monitor Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by..,1: Deep Sleep/Software Standby Mode returns by.." newline bitfld.long 0x0 19. "PVD2WUPEN,PVD2 Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by PVD2..,1: Deep Sleep/Software Standby Mode returns by PVD2.." bitfld.long 0x0 18. "PVD1WUPEN,PVD1 Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by PVD1..,1: Deep Sleep/Software Standby Mode returns by PVD1.." newline bitfld.long 0x0 16. "IWDTWUPEN,IWDT Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by IWDT..,1: Deep Sleep/Software Standby Mode returns by IWDT.." hexmask.long.word 0x0 0.--15. 1. "IRQWUPEN" line.long 0x4 "WUPEN1,Wake Up interrupt enable register 1" bitfld.long 0x4 14. "ULP1BWUPEN,ULPT1 Compare Match B Interrupt Deep Sleep/Software Standby Mode returns Enable bit" "0: Deep Sleep/Software Standby returns by ULPT1..,1: Deep Sleep/Software Standby returns by ULPT1.." bitfld.long 0x4 13. "ULP1AWUPEN,ULPT1 Compare Match A Interrupt Deep Sleep/Software Standby Mode returns Enable bit" "0: Deep Sleep/Software Standby returns by ULPT1..,1: Deep Sleep/Software Standby returns by ULPT1.." newline bitfld.long 0x4 12. "ULP1UWUPEN,ULPT1 Underflow Interrupt Deep Sleep/Software Standby Mode returns Enable bit" "0: Deep Sleep/Software Standby returns by ULPT1..,1: Deep Sleep/Software Standby returns by ULPT1.." bitfld.long 0x4 10. "ULP0BWUPEN,ULPT0 Compare Match B Interrupt Deep Sleep/Software Standby Mode returns Enable bit" "0: Deep Sleep/Software Standby returns by ULPT0..,1: Deep Sleep/Software Standby returns by ULPT0.." newline bitfld.long 0x4 9. "ULP0AWUPEN,ULPT0 Compare Match A Interrupt Deep Sleep/Software Standby Mode returns Enable bit" "0: Deep Sleep/Software Standby returns by ULPT0..,1: Deep Sleep/Software Standby returns by ULPT0.." bitfld.long 0x4 8. "ULP0UWUPEN,ULPT0 Underflow Interrupt Deep Sleep/Software Standby Mode returns Enable bit" "0: Deep Sleep/Software Standby returns by ULPT0..,1: Deep Sleep/Software Standby returns by ULPT0.." newline bitfld.long 0x4 3. "COMPHS0WUPEN,Comparator-HS0 Interrupt Deep Sleep/Software Standby Mode returns Enable bit" "0: Deep Sleep/Software Standby returns by..,1: Deep Sleep/Software Standby returns by ULPT0.." repeat 96. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x300)++0x3 line.long 0x0 "IELSR$1,ICU Event Link Setting Register %s" repeat.end tree.end tree "ICU_COMMON" base ad:0x40006000 repeat 16. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "IRQCR$1,IRQ Control Register %s" bitfld.byte 0x0 7. "FLTEN,IRQi Digital Filter Enable" "0: Digital filter is disabled,1: Digital filter is enabled." bitfld.byte 0x0 4.--5. "FCLKSEL,IRQi Digital Filter Sampling Clock Select" "0: PCLKB,1: PCLKB/8,?,?" bitfld.byte 0x0 0.--1. "IRQMD,IRQi Detection Sense Select" "0: Falling edge,1: Rising edge,?,?" repeat.end group.byte 0x10++0x0 line.byte 0x0 "NMICR,NMI Pin Interrupt Control Register" bitfld.byte 0x0 7. "NFLTEN,NMI Digital Filter Enable" "0: Disabled,1: Enabled" bitfld.byte 0x0 4.--5. "NFCLKSEL,NMI Digital Filter Sampling Clock Select" "0: PCLKB,1: PCLKB/8,?,?" bitfld.byte 0x0 0. "NMIMD,NMI Detection Set" "0: Falling edge,1: Rising edge" tree.end tree "ICU_COMMON_NS" base ad:0x50006000 repeat 16. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "IRQCR$1,IRQ Control Register %s" bitfld.byte 0x0 7. "FLTEN,IRQi Digital Filter Enable" "0: Digital filter is disabled,1: Digital filter is enabled." bitfld.byte 0x0 4.--5. "FCLKSEL,IRQi Digital Filter Sampling Clock Select" "0: PCLKB,1: PCLKB/8,?,?" bitfld.byte 0x0 0.--1. "IRQMD,IRQi Detection Sense Select" "0: Falling edge,1: Rising edge,?,?" repeat.end group.byte 0x10++0x0 line.byte 0x0 "NMICR,NMI Pin Interrupt Control Register" bitfld.byte 0x0 7. "NFLTEN,NMI Digital Filter Enable" "0: Disabled,1: Enabled" bitfld.byte 0x0 4.--5. "NFCLKSEL,NMI Digital Filter Sampling Clock Select" "0: PCLKB,1: PCLKB/8,?,?" bitfld.byte 0x0 0. "NMIMD,NMI Detection Set" "0: Falling edge,1: Rising edge" tree.end tree "ICU_NS" base ad:0x5000C000 group.word 0x100++0x1 line.word 0x0 "NMIER,Non-Maskable Interrupt Enable Register" bitfld.word 0x0 15. "LUEN" "0: Disabled,1: Enabled" bitfld.word 0x0 13. "CMEN" "0: Disabled,1: Enabled" newline bitfld.word 0x0 12. "BUSEN" "0: Disabled,1: Enabled" bitfld.word 0x0 7. "NMIEN,NMI Pin Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "OSTEN,Main Clock Oscillation Stop Detection Interrupt Enable" "0: Disabled,1: Enabled" bitfld.word 0x0 3. "PVD2EN,Voltage monitor 2 Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "PVD1EN,Voltage monitor 1 Interrupt Enable" "0: Disabled,1: Enabled" bitfld.word 0x0 1. "WDTEN,WDT Underflow/Refresh Error Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 0. "IWDTEN,IWDT Underflow/Refresh Error Interrupt Enable" "0: Disabled,1: Enabled" group.word 0x110++0x1 line.word 0x0 "NMICLR,Non-Maskable Interrupt Status Clear Register" bitfld.word 0x0 15. "LUCLR" "0: No effect,1: Clear the NMISR.LUST flag" bitfld.word 0x0 13. "CMCLR" "0: No effect,1: Clear the NMISR.CMST flag" newline bitfld.word 0x0 12. "BUSCLR" "0: No effect,1: Clear the NMISR.BUSST flag" bitfld.word 0x0 7. "NMICLR,NMI Pin Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.NMIST flag" newline bitfld.word 0x0 6. "OSTCLR,Oscillation Stop Detection Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.OSTST flag" bitfld.word 0x0 3. "PVD2CLR,Voltage Monitor 2 Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.PVD2ST flag." newline bitfld.word 0x0 2. "PVD1CLR,Voltage Monitor 1 Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.PVD1ST flag" bitfld.word 0x0 1. "WDTCLR,WDT Underflow/Refresh Error Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.WDTST flag" newline bitfld.word 0x0 0. "IWDTCLR,IWDT Underflow/Refresh Error Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.IWDTST flag" rgroup.word 0x120++0x1 line.word 0x0 "NMISR,Non-Maskable Interrupt Status Register" bitfld.word 0x0 15. "LUST" "0: Interrupt not requested,1: Interrupt requested" bitfld.word 0x0 13. "CMST" "0: Interrupt not requested,1: Interrupt requested" newline bitfld.word 0x0 12. "BUSST,Bus Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested" bitfld.word 0x0 7. "NMIST,NMI Pin Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested" newline bitfld.word 0x0 6. "OSTST,Main Clock Oscillation Stop Detection Interrupt Status Flag" "0: Interrupt not requested for main clock..,1: Interrupt requested for main clock oscillation.." bitfld.word 0x0 3. "PVD2ST,Voltage Monitor 2 Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested" newline bitfld.word 0x0 2. "PVD1ST,Voltage Monitor 1 Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested" bitfld.word 0x0 1. "WDTST,WDT Underflow/Refresh Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested" newline bitfld.word 0x0 0. "IWDTST,IWDT Underflow/Refresh Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested" group.long 0x1A0++0x7 line.long 0x0 "WUPEN0,Wake Up Interrupt Enable Register 0" bitfld.long 0x0 31. "IIC0WUPEN,IIC0 Address Match Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by IIC0..,1: Deep Sleep/Software Standby Mode returns by IIC0.." bitfld.long 0x0 30. "AGT1CBWUPEN,AGT1 Compare Match B Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by AGT1..,1: Deep Sleep/Software Standby Mode returns by AGT1.." newline bitfld.long 0x0 29. "AGT1CAWUPEN,AGT1 Compare Match A Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by AGT1..,1: Deep Sleep/Software Standby Mode returns by AGT1.." bitfld.long 0x0 28. "AGT1UDWUPEN,AGT1 Underflow Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by AGT1..,1: Deep Sleep/Software Standby Mode returns by AGT1.." newline bitfld.long 0x0 27. "USBFS0WUPEN,USBFS Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by..,1: Deep Sleep/Software Standby Mode returns by.." bitfld.long 0x0 25. "RTCPRDWUPEN,RTC Period Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by RTC..,1: Deep Sleep/Software Standby Mode returns by RTC.." newline bitfld.long 0x0 24. "RTCALMWUPEN,RTC Alarm Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by RTC..,1: Deep Sleep/Software Standby Mode returns by RTC.." bitfld.long 0x0 20. "VBATTWUPEN,VBATT Monitor Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by..,1: Deep Sleep/Software Standby Mode returns by.." newline bitfld.long 0x0 19. "PVD2WUPEN,PVD2 Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by PVD2..,1: Deep Sleep/Software Standby Mode returns by PVD2.." bitfld.long 0x0 18. "PVD1WUPEN,PVD1 Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by PVD1..,1: Deep Sleep/Software Standby Mode returns by PVD1.." newline bitfld.long 0x0 16. "IWDTWUPEN,IWDT Interrupt Deep Sleep/Software Standby Mode Returns Enable" "0: Deep Sleep/Software Standby Mode returns by IWDT..,1: Deep Sleep/Software Standby Mode returns by IWDT.." hexmask.long.word 0x0 0.--15. 1. "IRQWUPEN" line.long 0x4 "WUPEN1,Wake Up interrupt enable register 1" bitfld.long 0x4 14. "ULP1BWUPEN,ULPT1 Compare Match B Interrupt Deep Sleep/Software Standby Mode returns Enable bit" "0: Deep Sleep/Software Standby returns by ULPT1..,1: Deep Sleep/Software Standby returns by ULPT1.." bitfld.long 0x4 13. "ULP1AWUPEN,ULPT1 Compare Match A Interrupt Deep Sleep/Software Standby Mode returns Enable bit" "0: Deep Sleep/Software Standby returns by ULPT1..,1: Deep Sleep/Software Standby returns by ULPT1.." newline bitfld.long 0x4 12. "ULP1UWUPEN,ULPT1 Underflow Interrupt Deep Sleep/Software Standby Mode returns Enable bit" "0: Deep Sleep/Software Standby returns by ULPT1..,1: Deep Sleep/Software Standby returns by ULPT1.." bitfld.long 0x4 10. "ULP0BWUPEN,ULPT0 Compare Match B Interrupt Deep Sleep/Software Standby Mode returns Enable bit" "0: Deep Sleep/Software Standby returns by ULPT0..,1: Deep Sleep/Software Standby returns by ULPT0.." newline bitfld.long 0x4 9. "ULP0AWUPEN,ULPT0 Compare Match A Interrupt Deep Sleep/Software Standby Mode returns Enable bit" "0: Deep Sleep/Software Standby returns by ULPT0..,1: Deep Sleep/Software Standby returns by ULPT0.." bitfld.long 0x4 8. "ULP0UWUPEN,ULPT0 Underflow Interrupt Deep Sleep/Software Standby Mode returns Enable bit" "0: Deep Sleep/Software Standby returns by ULPT0..,1: Deep Sleep/Software Standby returns by ULPT0.." newline bitfld.long 0x4 3. "COMPHS0WUPEN,Comparator-HS0 Interrupt Deep Sleep/Software Standby Mode returns Enable bit" "0: Deep Sleep/Software Standby returns by..,1: Deep Sleep/Software Standby returns by ULPT0.." repeat 96. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x300)++0x3 line.long 0x0 "IELSR$1,ICU Event Link Setting Register %s" bitfld.long 0x0 24. "DTCE,DTC Activation Enable" "0: DTC activation is disabled.,1: DTC activation is enabled." bitfld.long 0x0 16. "IR,Interrupt Status Flag" "0: No interrupt request generated.,1: An interrupt request is generated." newline hexmask.long.word 0x0 0.--8. 1. "IELS,ICU Event Link Select" repeat.end tree.end tree.end tree "IIC (I2C Bus Interface)" base ad:0x0 tree "IIC0_NS" base ad:0x5025E000 group.byte 0x0++0x9 line.byte 0x0 "ICCR1,I2C Bus Control Register 1" bitfld.byte 0x0 7. "ICE,I2C Bus Interface Enable" "0: Disable (SCLn and SDAn pins in inactive state),1: Enable (SCLn and SDAn pins in active state)" bitfld.byte 0x0 6. "IICRST,I2C Bus Interface Internal Reset" "0: Release IIC reset or internal reset,1: Initiate IIC reset or internal reset" newline bitfld.byte 0x0 5. "CLO,Extra SCL Clock Cycle Output" "0: Do not output extra SCL clock cycle (default),1: Output extra SCL clock cycle" bitfld.byte 0x0 4. "SOWP,SCLO/SDAO Write Protect" "0: Write enable SCLO and SDAO bits,1: Write protect SCLO and SDAO bits" newline bitfld.byte 0x0 3. "SCLO,SCL Output Control/Monitor" "0: Read: IIC drives SCLn pin low Write: IIC drives..,1: Read: IIC releases SCLn pin Write: IIC releases.." bitfld.byte 0x0 2. "SDAO,SDA Output Control/Monitor" "0: Read: IIC drives SDAn pin low Write: IIC drives..,1: Read: IIC releases SDAn pin Write: IIC releases.." newline rbitfld.byte 0x0 1. "SCLI,SCL Line Monitor" "0: SCLn line is low,1: SCLn line is high" rbitfld.byte 0x0 0. "SDAI,SDA Line Monitor" "0: SDAn line is low,1: SDAn line is high" line.byte 0x1 "ICCR2,I2C Bus Control Register 2" rbitfld.byte 0x1 7. "BBSY,Bus Busy Detection Flag" "0: I2C bus released (bus free state),1: I2C bus occupied (bus busy state)" bitfld.byte 0x1 6. "MST,Master/Slave Mode" "0: Slave mode,1: Master mode" newline bitfld.byte 0x1 5. "TRS,Transmit/Receive Mode" "0: Receive mode,1: Transmit mode" bitfld.byte 0x1 3. "SP,Stop Condition Issuance Request" "0: Do not issue a stop condition request,1: Issue a stop condition request" newline bitfld.byte 0x1 2. "RS,Restart Condition Issuance Request" "0: Do not issue a restart condition request,1: Issue a restart condition request" bitfld.byte 0x1 1. "ST,Start Condition Issuance Request" "0: Do not issue a start condition request,1: Issue a start condition request" line.byte 0x2 "ICMR1,I2C Bus Mode Register 1" bitfld.byte 0x2 7. "MTWP,MST/TRS Write Protect" "0: Write protect MST and TRS bits in ICCR2,1: Write enable MST and TRS bits in ICCR2" bitfld.byte 0x2 4.--6. "CKS,Internal Reference Clock Select" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x2 3. "BCWP,BC Write Protect" "0: Write enable BC[2:0] bits,1: Write protect BC[2:0] bits" bitfld.byte 0x2 0.--2. "BC,Bit Counter" "0: 9 bits,1: 2 bits,?,?,?,?,?,?" line.byte 0x3 "ICMR2,I2C Bus Mode Register 2" bitfld.byte 0x3 7. "DLCS,SDA Output Delay Clock Source Select" "0: Select internal reference clock (IIC-phi) as the..,1: Select internal reference clock divided by 2.." bitfld.byte 0x3 4.--6. "SDDL,SDA Output Delay Counter" "0: No output delay,1: 1 IIC-phi cycle (When ICMR2.DLCS = 0 (IIC-phi))..,?,?,?,?,?,?" newline bitfld.byte 0x3 2. "TMOH,Timeout H Count Control" "0: Disable count while SCLn line is high,1: Enable count while SCLn line is high" bitfld.byte 0x3 1. "TMOL,Timeout L Count Control" "0: Disable count while SCLn line is low,1: Enable count while SCLn line is low" newline bitfld.byte 0x3 0. "TMOS,Timeout Detection Time Select" "0: Select long mode,1: Select short mode" line.byte 0x4 "ICMR3,I2C Bus Mode Register 3" bitfld.byte 0x4 7. "SMBS,SMBus/I2C Bus Select" "0: Select I2C Bus,1: Select SMBus" bitfld.byte 0x4 6. "WAIT,Low-hold is released by reading ICDRR." "0: No wait (The SCLn line is not held low during..,1: Wait (The SCLn line is held low during the.." newline bitfld.byte 0x4 5. "RDRFS,RDRF Flag Set Timing Select" "0: Set the RDRF flag on the rising edge of the 9th..,1: Set the RDRF flag on the rising edge of the 8th.." bitfld.byte 0x4 4. "ACKWP,ACKBT Write Protect" "0: Write protect ACKBT bit,1: Write enable ACKBT bit" newline bitfld.byte 0x4 3. "ACKBT,Transmit Acknowledge" "0: Send 0 as the acknowledge bit (ACK transmission),1: Send 1 as the acknowledge bit (NACK transmission)" rbitfld.byte 0x4 2. "ACKBR,Receive Acknowledge" "0: 0 received as the acknowledge bit (ACK reception),1: 1 received as the acknowledge bit (NACK reception)" newline bitfld.byte 0x4 0.--1. "NF,Noise Filter Stage Select" "0: Filter out noise of up to 1 IIC-phi cycle..,1: Filter out noise of up to 2 IIC-phi cycles..,?,?" line.byte 0x5 "ICFER,I2C Bus Function Enable Register" bitfld.byte 0x5 7. "FMPE,Fast-Mode Plus Enable" "0: Do not use the Fm+ slope control circuit for the..,1: Use the Fm+ slope control circuit for the SCLn.." bitfld.byte 0x5 6. "SCLE,SCL Synchronous Circuit Enable" "0: Do not use the SCL synchronous circuit,1: Use the SCL synchronous circuit" newline bitfld.byte 0x5 5. "NFE,Digital Noise Filter Circuit Enable" "0: Do not use the digital noise filter circuit,1: Use the digital noise filter circuit" bitfld.byte 0x5 4. "NACKE,NACK Reception Transfer Suspension Enable" "0: Do not suspend transfer operation during NACK..,1: Suspend transfer operation during NACK reception.." newline bitfld.byte 0x5 3. "SALE,Slave Arbitration-Lost Detection Enable" "0: Disable,1: Enable" bitfld.byte 0x5 2. "NALE,NACK Transmission Arbitration-Lost Detection Enable" "0: Disable,1: Enable" newline bitfld.byte 0x5 1. "MALE,Master Arbitration-Lost Detection Enable" "0: Disable the arbitration-lost detection function..,1: Enable the arbitration-lost detection function.." bitfld.byte 0x5 0. "TMOE,Timeout Function Enable" "0: Disable,1: Enable" line.byte 0x6 "ICSER,I2C Bus Status Enable Register" bitfld.byte 0x6 7. "HOAE,Host Address Enable" "0: Disable host address detection,1: Enable host address detection" bitfld.byte 0x6 5. "DIDE,Device-ID Address Detection Enable" "0: Disable device-ID address detection,1: Enable device-ID address detection" newline bitfld.byte 0x6 3. "GCAE,General Call Address Enable" "0: Disable general call address detection,1: Enable general call address detection" bitfld.byte 0x6 2. "SAR2E,Slave Address Register 2 Enable" "0: Disable slave address in SARL2 and SARU2,1: Enable slave address in SARL2 and SARU2" newline bitfld.byte 0x6 1. "SAR1E,Slave Address Register 1 Enable" "0: Disable slave address in SARL1 and SARU1,1: Enable slave address in SARL1 and SARU1" bitfld.byte 0x6 0. "SAR0E,Slave Address Register 0 Enable" "0: Disable slave address in SARL0 and SARU0,1: Enable slave address in SARL0 and SARU0" line.byte 0x7 "ICIER,I2C Bus Interrupt Enable Register" bitfld.byte 0x7 7. "TIE,Transmit Data Empty Interrupt Request Enable" "0: Disable transmit data empty interrupt (IICn_TXI)..,1: Enable transmit data empty interrupt (IICn_TXI).." bitfld.byte 0x7 6. "TEIE,Transmit End Interrupt Request Enable" "0: Disable transmit end interrupt (IICn_TEI) request,1: Enable transmit end interrupt (IICn_TEI) request" newline bitfld.byte 0x7 5. "RIE,Receive Data Full Interrupt Request Enable" "0: Disable receive data full interrupt (IICn_RXI)..,1: Enable receive data full interrupt (IICn_RXI).." bitfld.byte 0x7 4. "NAKIE,NACK Reception Interrupt Request Enable" "0: Disable NACK reception interrupt (NAKI) request,1: Enable NACK reception interrupt (NAKI) request" newline bitfld.byte 0x7 3. "SPIE,Stop Condition Detection Interrupt Request Enable" "0: Disable stop condition detection interrupt (SPI)..,1: Enable stop condition detection interrupt (SPI).." bitfld.byte 0x7 2. "STIE,Start Condition Detection Interrupt Request Enable" "0: Disable start condition detection interrupt..,1: Enable start condition detection interrupt (STI).." newline bitfld.byte 0x7 1. "ALIE,Arbitration-Lost Interrupt Request Enable" "0: Disable arbitration-lost interrupt (ALI) request,1: Enable arbitration-lost interrupt (ALI) request" bitfld.byte 0x7 0. "TMOIE,Timeout Interrupt Request Enable" "0: Disable timeout interrupt (TMOI) request,1: Enable timeout interrupt (TMOI) request" line.byte 0x8 "ICSR1,I2C Bus Status Register 1" bitfld.byte 0x8 7. "HOA,Host Address Detection Flag" "0: Host address not detected,1: Host address detected" bitfld.byte 0x8 5. "DID,Device-ID Address Detection Flag" "0: Device-ID command not detected,1: Device-ID command detected" newline bitfld.byte 0x8 3. "GCA,General Call Address Detection Flag" "0: General call address not detected,1: General call address detected" bitfld.byte 0x8 2. "AAS2,Slave Address 2 Detection Flag" "0: Slave address 2 not detected,1: Slave address 2 detected" newline bitfld.byte 0x8 1. "AAS1,Slave Address 1 Detection Flag" "0: Slave address 1 not detected,1: Slave address 1 detected" bitfld.byte 0x8 0. "AAS0,Slave Address 0 Detection Flag" "0: Slave address 0 not detected,1: Slave address 0 detected" line.byte 0x9 "ICSR2,I2C Bus Status Register 2" rbitfld.byte 0x9 7. "TDRE,Transmit Data Empty Flag" "0: ICDRT contains transmit data,1: ICDRT contains no transmit data" bitfld.byte 0x9 6. "TEND,Transmit End Flag" "0: Data being transmitted,1: Data transmit complete" newline bitfld.byte 0x9 5. "RDRF,Receive Data Full Flag" "0: ICDRR contains no receive data,1: ICDRR contains receive data" bitfld.byte 0x9 4. "NACKF,NACK Detection Flag" "0: NACK not detected,1: NACK detected" newline bitfld.byte 0x9 3. "STOP,Stop Condition Detection Flag" "0: Stop condition not detected,1: Stop condition detected" bitfld.byte 0x9 2. "START,Start Condition Detection Flag" "0: Start condition not detected,1: Start condition detected" newline bitfld.byte 0x9 1. "AL,Arbitration-Lost Flag" "0: Arbitration not lost,1: Arbitration lost" bitfld.byte 0x9 0. "TMOF,Timeout Detection Flag" "0: Timeout not detected,1: Timeout detected" repeat 3. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0xA)++0x0 line.byte 0x0 "SARL$1,Slave Address Register Ly" hexmask.byte 0x0 1.--7. 1. "SVA,7-bit Address/10-bit Address Lower Bits" bitfld.byte 0x0 0. "SVA0,10-bit Address LSB" "0,1" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0xB)++0x0 line.byte 0x0 "SARU$1,Slave Address Register Uy" bitfld.byte 0x0 1.--2. "SVA,10-bit Address Upper Bits" "0,1,2,3" bitfld.byte 0x0 0. "FS,7-bit/10-bit Address Format Select" "0: Select 7-bit address format,1: Select 10-bit address format" repeat.end group.byte 0x10++0x2 line.byte 0x0 "ICBRL,I2C Bus Bit Rate Low-Level Register" hexmask.byte 0x0 0.--4. 1. "BRL,Bit Rate Low-Level Period" line.byte 0x1 "ICBRH,I2C Bus Bit Rate High-Level Register" hexmask.byte 0x1 0.--4. 1. "BRH,Bit Rate High-Level Period" line.byte 0x2 "ICDRT,I2C Bus Transmit Data Register" rgroup.byte 0x13++0x0 line.byte 0x0 "ICDRR,I2C Bus Receive Data Register" tree.end tree "IIC0WU" base ad:0x4025E014 group.byte 0x2++0x1 line.byte 0x0 "ICWUR,I2C Bus Wakeup Unit Register" bitfld.byte 0x0 7. "WUE,Wakeup Function Enable" "0: Disable wakeup function,1: Enable wakeup function" bitfld.byte 0x0 6. "WUIE,Wakeup Interrupt Request Enable" "0: Disable wakeup interrupt request (IIC0_WUI),1: Enable wakeup interrupt request (IIC0_WUI)" newline bitfld.byte 0x0 5. "WUF,Wakeup Event Occurrence Flag" "0: Slave address not matching during wakeup,1: Slave address matching during wakeup" bitfld.byte 0x0 4. "WUACK,ACK Bit for Wakeup Mode" "0,1" newline bitfld.byte 0x0 0. "WUAFA,Wakeup Analog Filter Additional Selection" "0: Do not add the wakeup analog filter,1: Add the wakeup analog filter" line.byte 0x1 "ICWUR2,I2C Bus Wakeup Unit Register 2" rbitfld.byte 0x1 2. "WUSYF,Wakeup Function Synchronous Operation Status Flag" "0: IIC asynchronous circuit enable condition,1: IIC synchronous circuit enable condition" rbitfld.byte 0x1 1. "WUASYF,Wakeup Function Asynchronous Operation Status Flag" "0: IIC synchronous circuit enable condition,1: IIC asynchronous circuit enable condition" newline bitfld.byte 0x1 0. "WUSEN,Wakeup Function Synchronous Enable" "0: IIC asynchronous circuit enable,1: IIC synchronous circuit enable" tree.end tree "IIC0WU_NS" base ad:0x5025E014 group.byte 0x2++0x1 line.byte 0x0 "ICWUR,I2C Bus Wakeup Unit Register" bitfld.byte 0x0 7. "WUE,Wakeup Function Enable" "0: Disable wakeup function,1: Enable wakeup function" bitfld.byte 0x0 6. "WUIE,Wakeup Interrupt Request Enable" "0: Disable wakeup interrupt request (IIC0_WUI),1: Enable wakeup interrupt request (IIC0_WUI)" newline bitfld.byte 0x0 5. "WUF,Wakeup Event Occurrence Flag" "0: Slave address not matching during wakeup,1: Slave address matching during wakeup" bitfld.byte 0x0 4. "WUACK,ACK Bit for Wakeup Mode" "0,1" newline bitfld.byte 0x0 0. "WUAFA,Wakeup Analog Filter Additional Selection" "0: Do not add the wakeup analog filter,1: Add the wakeup analog filter" line.byte 0x1 "ICWUR2,I2C Bus Wakeup Unit Register 2" rbitfld.byte 0x1 2. "WUSYF,Wakeup Function Synchronous Operation Status Flag" "0: IIC asynchronous circuit enable condition,1: IIC synchronous circuit enable condition" rbitfld.byte 0x1 1. "WUASYF,Wakeup Function Asynchronous Operation Status Flag" "0: IIC synchronous circuit enable condition,1: IIC asynchronous circuit enable condition" newline bitfld.byte 0x1 0. "WUSEN,Wakeup Function Synchronous Enable" "0: IIC asynchronous circuit enable,1: IIC synchronous circuit enable" tree.end tree "IIC1_NS" base ad:0x5025E100 group.byte 0x0++0x9 line.byte 0x0 "ICCR1,I2C Bus Control Register 1" bitfld.byte 0x0 7. "ICE,I2C Bus Interface Enable" "0: Disable (SCLn and SDAn pins in inactive state),1: Enable (SCLn and SDAn pins in active state)" bitfld.byte 0x0 6. "IICRST,I2C Bus Interface Internal Reset" "0: Release IIC reset or internal reset,1: Initiate IIC reset or internal reset" newline bitfld.byte 0x0 5. "CLO,Extra SCL Clock Cycle Output" "0: Do not output extra SCL clock cycle (default),1: Output extra SCL clock cycle" bitfld.byte 0x0 4. "SOWP,SCLO/SDAO Write Protect" "0: Write enable SCLO and SDAO bits,1: Write protect SCLO and SDAO bits" newline bitfld.byte 0x0 3. "SCLO,SCL Output Control/Monitor" "0: Read: IIC drives SCLn pin low Write: IIC drives..,1: Read: IIC releases SCLn pin Write: IIC releases.." bitfld.byte 0x0 2. "SDAO,SDA Output Control/Monitor" "0: Read: IIC drives SDAn pin low Write: IIC drives..,1: Read: IIC releases SDAn pin Write: IIC releases.." newline rbitfld.byte 0x0 1. "SCLI,SCL Line Monitor" "0: SCLn line is low,1: SCLn line is high" rbitfld.byte 0x0 0. "SDAI,SDA Line Monitor" "0: SDAn line is low,1: SDAn line is high" line.byte 0x1 "ICCR2,I2C Bus Control Register 2" rbitfld.byte 0x1 7. "BBSY,Bus Busy Detection Flag" "0: I2C bus released (bus free state),1: I2C bus occupied (bus busy state)" bitfld.byte 0x1 6. "MST,Master/Slave Mode" "0: Slave mode,1: Master mode" newline bitfld.byte 0x1 5. "TRS,Transmit/Receive Mode" "0: Receive mode,1: Transmit mode" bitfld.byte 0x1 3. "SP,Stop Condition Issuance Request" "0: Do not issue a stop condition request,1: Issue a stop condition request" newline bitfld.byte 0x1 2. "RS,Restart Condition Issuance Request" "0: Do not issue a restart condition request,1: Issue a restart condition request" bitfld.byte 0x1 1. "ST,Start Condition Issuance Request" "0: Do not issue a start condition request,1: Issue a start condition request" line.byte 0x2 "ICMR1,I2C Bus Mode Register 1" bitfld.byte 0x2 7. "MTWP,MST/TRS Write Protect" "0: Write protect MST and TRS bits in ICCR2,1: Write enable MST and TRS bits in ICCR2" bitfld.byte 0x2 4.--6. "CKS,Internal Reference Clock Select" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x2 3. "BCWP,BC Write Protect" "0: Write enable BC[2:0] bits,1: Write protect BC[2:0] bits" bitfld.byte 0x2 0.--2. "BC,Bit Counter" "0: 9 bits,1: 2 bits,?,?,?,?,?,?" line.byte 0x3 "ICMR2,I2C Bus Mode Register 2" bitfld.byte 0x3 7. "DLCS,SDA Output Delay Clock Source Select" "0: Select internal reference clock (IIC-phi) as the..,1: Select internal reference clock divided by 2.." bitfld.byte 0x3 4.--6. "SDDL,SDA Output Delay Counter" "0: No output delay,1: 1 IIC-phi cycle (When ICMR2.DLCS = 0 (IIC-phi))..,?,?,?,?,?,?" newline bitfld.byte 0x3 2. "TMOH,Timeout H Count Control" "0: Disable count while SCLn line is high,1: Enable count while SCLn line is high" bitfld.byte 0x3 1. "TMOL,Timeout L Count Control" "0: Disable count while SCLn line is low,1: Enable count while SCLn line is low" newline bitfld.byte 0x3 0. "TMOS,Timeout Detection Time Select" "0: Select long mode,1: Select short mode" line.byte 0x4 "ICMR3,I2C Bus Mode Register 3" bitfld.byte 0x4 7. "SMBS,SMBus/I2C Bus Select" "0: Select I2C Bus,1: Select SMBus" bitfld.byte 0x4 6. "WAIT,Low-hold is released by reading ICDRR." "0: No wait (The SCLn line is not held low during..,1: Wait (The SCLn line is held low during the.." newline bitfld.byte 0x4 5. "RDRFS,RDRF Flag Set Timing Select" "0: Set the RDRF flag on the rising edge of the 9th..,1: Set the RDRF flag on the rising edge of the 8th.." bitfld.byte 0x4 4. "ACKWP,ACKBT Write Protect" "0: Write protect ACKBT bit,1: Write enable ACKBT bit" newline bitfld.byte 0x4 3. "ACKBT,Transmit Acknowledge" "0: Send 0 as the acknowledge bit (ACK transmission),1: Send 1 as the acknowledge bit (NACK transmission)" rbitfld.byte 0x4 2. "ACKBR,Receive Acknowledge" "0: 0 received as the acknowledge bit (ACK reception),1: 1 received as the acknowledge bit (NACK reception)" newline bitfld.byte 0x4 0.--1. "NF,Noise Filter Stage Select" "0: Filter out noise of up to 1 IIC-phi cycle..,1: Filter out noise of up to 2 IIC-phi cycles..,?,?" line.byte 0x5 "ICFER,I2C Bus Function Enable Register" bitfld.byte 0x5 7. "FMPE,Fast-Mode Plus Enable" "0: Do not use the Fm+ slope control circuit for the..,1: Use the Fm+ slope control circuit for the SCLn.." bitfld.byte 0x5 6. "SCLE,SCL Synchronous Circuit Enable" "0: Do not use the SCL synchronous circuit,1: Use the SCL synchronous circuit" newline bitfld.byte 0x5 5. "NFE,Digital Noise Filter Circuit Enable" "0: Do not use the digital noise filter circuit,1: Use the digital noise filter circuit" bitfld.byte 0x5 4. "NACKE,NACK Reception Transfer Suspension Enable" "0: Do not suspend transfer operation during NACK..,1: Suspend transfer operation during NACK reception.." newline bitfld.byte 0x5 3. "SALE,Slave Arbitration-Lost Detection Enable" "0: Disable,1: Enable" bitfld.byte 0x5 2. "NALE,NACK Transmission Arbitration-Lost Detection Enable" "0: Disable,1: Enable" newline bitfld.byte 0x5 1. "MALE,Master Arbitration-Lost Detection Enable" "0: Disable the arbitration-lost detection function..,1: Enable the arbitration-lost detection function.." bitfld.byte 0x5 0. "TMOE,Timeout Function Enable" "0: Disable,1: Enable" line.byte 0x6 "ICSER,I2C Bus Status Enable Register" bitfld.byte 0x6 7. "HOAE,Host Address Enable" "0: Disable host address detection,1: Enable host address detection" bitfld.byte 0x6 5. "DIDE,Device-ID Address Detection Enable" "0: Disable device-ID address detection,1: Enable device-ID address detection" newline bitfld.byte 0x6 3. "GCAE,General Call Address Enable" "0: Disable general call address detection,1: Enable general call address detection" bitfld.byte 0x6 2. "SAR2E,Slave Address Register 2 Enable" "0: Disable slave address in SARL2 and SARU2,1: Enable slave address in SARL2 and SARU2" newline bitfld.byte 0x6 1. "SAR1E,Slave Address Register 1 Enable" "0: Disable slave address in SARL1 and SARU1,1: Enable slave address in SARL1 and SARU1" bitfld.byte 0x6 0. "SAR0E,Slave Address Register 0 Enable" "0: Disable slave address in SARL0 and SARU0,1: Enable slave address in SARL0 and SARU0" line.byte 0x7 "ICIER,I2C Bus Interrupt Enable Register" bitfld.byte 0x7 7. "TIE,Transmit Data Empty Interrupt Request Enable" "0: Disable transmit data empty interrupt (IICn_TXI)..,1: Enable transmit data empty interrupt (IICn_TXI).." bitfld.byte 0x7 6. "TEIE,Transmit End Interrupt Request Enable" "0: Disable transmit end interrupt (IICn_TEI) request,1: Enable transmit end interrupt (IICn_TEI) request" newline bitfld.byte 0x7 5. "RIE,Receive Data Full Interrupt Request Enable" "0: Disable receive data full interrupt (IICn_RXI)..,1: Enable receive data full interrupt (IICn_RXI).." bitfld.byte 0x7 4. "NAKIE,NACK Reception Interrupt Request Enable" "0: Disable NACK reception interrupt (NAKI) request,1: Enable NACK reception interrupt (NAKI) request" newline bitfld.byte 0x7 3. "SPIE,Stop Condition Detection Interrupt Request Enable" "0: Disable stop condition detection interrupt (SPI)..,1: Enable stop condition detection interrupt (SPI).." bitfld.byte 0x7 2. "STIE,Start Condition Detection Interrupt Request Enable" "0: Disable start condition detection interrupt..,1: Enable start condition detection interrupt (STI).." newline bitfld.byte 0x7 1. "ALIE,Arbitration-Lost Interrupt Request Enable" "0: Disable arbitration-lost interrupt (ALI) request,1: Enable arbitration-lost interrupt (ALI) request" bitfld.byte 0x7 0. "TMOIE,Timeout Interrupt Request Enable" "0: Disable timeout interrupt (TMOI) request,1: Enable timeout interrupt (TMOI) request" line.byte 0x8 "ICSR1,I2C Bus Status Register 1" bitfld.byte 0x8 7. "HOA,Host Address Detection Flag" "0: Host address not detected,1: Host address detected" bitfld.byte 0x8 5. "DID,Device-ID Address Detection Flag" "0: Device-ID command not detected,1: Device-ID command detected" newline bitfld.byte 0x8 3. "GCA,General Call Address Detection Flag" "0: General call address not detected,1: General call address detected" bitfld.byte 0x8 2. "AAS2,Slave Address 2 Detection Flag" "0: Slave address 2 not detected,1: Slave address 2 detected" newline bitfld.byte 0x8 1. "AAS1,Slave Address 1 Detection Flag" "0: Slave address 1 not detected,1: Slave address 1 detected" bitfld.byte 0x8 0. "AAS0,Slave Address 0 Detection Flag" "0: Slave address 0 not detected,1: Slave address 0 detected" line.byte 0x9 "ICSR2,I2C Bus Status Register 2" rbitfld.byte 0x9 7. "TDRE,Transmit Data Empty Flag" "0: ICDRT contains transmit data,1: ICDRT contains no transmit data" bitfld.byte 0x9 6. "TEND,Transmit End Flag" "0: Data being transmitted,1: Data transmit complete" newline bitfld.byte 0x9 5. "RDRF,Receive Data Full Flag" "0: ICDRR contains no receive data,1: ICDRR contains receive data" bitfld.byte 0x9 4. "NACKF,NACK Detection Flag" "0: NACK not detected,1: NACK detected" newline bitfld.byte 0x9 3. "STOP,Stop Condition Detection Flag" "0: Stop condition not detected,1: Stop condition detected" bitfld.byte 0x9 2. "START,Start Condition Detection Flag" "0: Start condition not detected,1: Start condition detected" newline bitfld.byte 0x9 1. "AL,Arbitration-Lost Flag" "0: Arbitration not lost,1: Arbitration lost" bitfld.byte 0x9 0. "TMOF,Timeout Detection Flag" "0: Timeout not detected,1: Timeout detected" repeat 3. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0xA)++0x0 line.byte 0x0 "SARL$1,Slave Address Register Ly" hexmask.byte 0x0 1.--7. 1. "SVA,7-bit Address/10-bit Address Lower Bits" bitfld.byte 0x0 0. "SVA0,10-bit Address LSB" "0,1" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0xB)++0x0 line.byte 0x0 "SARU$1,Slave Address Register Uy" bitfld.byte 0x0 1.--2. "SVA,10-bit Address Upper Bits" "0,1,2,3" bitfld.byte 0x0 0. "FS,7-bit/10-bit Address Format Select" "0: Select 7-bit address format,1: Select 10-bit address format" repeat.end group.byte 0x10++0x2 line.byte 0x0 "ICBRL,I2C Bus Bit Rate Low-Level Register" hexmask.byte 0x0 0.--4. 1. "BRL,Bit Rate Low-Level Period" line.byte 0x1 "ICBRH,I2C Bus Bit Rate High-Level Register" hexmask.byte 0x1 0.--4. 1. "BRH,Bit Rate High-Level Period" line.byte 0x2 "ICDRT,I2C Bus Transmit Data Register" rgroup.byte 0x13++0x0 line.byte 0x0 "ICDRR,I2C Bus Receive Data Register" tree.end tree.end tree "IOP (I/O Ports)" base ad:0x0 tree "PFS (Pin Function Select)" tree "PFS" base ad:0x40400800 repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "P00$1PFS,Port 00%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2)++0x1 line.word 0x0 "P00$1PFS_HA,Port 00%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2)++0x0 line.byte 0x0 "P00$1PFS_BY,Port 00%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x28)++0x3 line.long 0x0 "P0$1PFS,Port 0%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x28)++0x1 line.word 0x0 "P0$1PFS_HA,Port 0%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x28)++0x0 line.byte 0x0 "P0$1PFS_BY,Port 0%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x38)++0x3 line.long 0x0 "P0$1PFS,Port 0%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x38)++0x1 line.word 0x0 "P0$1PFS_HA,Port 0%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x38)++0x0 line.byte 0x0 "P0$1PFS_BY,Port 0%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "P10$1PFS,Port 10%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x40)++0x1 line.word 0x0 "P10$1PFS_HA,Port 10%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x40)++0x0 line.byte 0x0 "P10$1PFS_BY,Port 10%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "P1$1PFS,Port 1%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x70)++0x1 line.word 0x0 "P1$1PFS_HA,Port 1%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x70)++0x0 line.byte 0x0 "P1$1PFS_BY,Port 1%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end group.long 0x80++0x3 line.long 0x0 "P200PFS,Port 200 Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0x80++0x1 line.word 0x0 "P200PFS_HA,Port 200 Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" group.byte 0x80++0x0 line.byte 0x0 "P200PFS_BY,Port 200 Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" group.long 0x84++0x3 line.long 0x0 "P201PFS,Port 201 Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0x84++0x1 line.word 0x0 "P201PFS_HA,Port 201 Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" group.byte 0x84++0x0 line.byte 0x0 "P201PFS_BY,Port 201 Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x88)++0x3 line.long 0x0 "P20$1PFS,Port 20%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x88)++0x1 line.word 0x0 "P20$1PFS_HA,Port 20%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x88)++0x0 line.byte 0x0 "P20$1PFS_BY,Port 20%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end group.long 0xA0++0x3 line.long 0x0 "P208PFS,Port 208 Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0xA0++0x1 line.word 0x0 "P208PFS_HA,Port 208 Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" group.byte 0xA0++0x0 line.byte 0x0 "P208PFS_BY,Port 208 Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" group.long 0xA4++0x3 line.long 0x0 "P209PFS,Port 209 Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0xA4++0x1 line.word 0x0 "P209PFS_HA,Port 209 Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" group.byte 0xA4++0x0 line.byte 0x0 "P209PFS_BY,Port 209 Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" group.long 0xA8++0x3 line.long 0x0 "P210PFS,Port 210 Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0xA8++0x1 line.word 0x0 "P210PFS_HA,Port 210 Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" group.byte 0xA8++0x0 line.byte 0x0 "P210PFS_BY,Port 210 Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" group.long 0xAC++0x3 line.long 0x0 "P211PFS,Port 211 Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0xAC++0x1 line.word 0x0 "P211PFS_HA,Port 211 Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" group.byte 0xAC++0x0 line.byte 0x0 "P211PFS_BY,Port 211 Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xB0)++0x3 line.long 0x0 "P2$1PFS,Port 2%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0xB0)++0x1 line.word 0x0 "P2$1PFS_HA,Port 2%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0xB0)++0x0 line.byte 0x0 "P2$1PFS_BY,Port 2%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC0)++0x3 line.long 0x0 "P30$1PFS,Port 30%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0xC0)++0x1 line.word 0x0 "P30$1PFS_HA,Port 30%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0xC0)++0x0 line.byte 0x0 "P30$1PFS_BY,Port 30%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xE8)++0x3 line.long 0x0 "P3$1PFS,Port 3%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0xE8)++0x1 line.word 0x0 "P3$1PFS_HA,Port 3%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0xE8)++0x0 line.byte 0x0 "P3$1PFS_BY,Port 3%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x100)++0x3 line.long 0x0 "P40$1PFS,Port 40%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x100)++0x1 line.word 0x0 "P40$1PFS_HA,Port 40%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x100)++0x0 line.byte 0x0 "P40$1PFS_BY,Port 40%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x128)++0x3 line.long 0x0 "P4$1PFS,Port 4%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x128)++0x1 line.word 0x0 "P4$1PFS_HA,Port 4%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x128)++0x0 line.byte 0x0 "P4$1PFS_BY,Port 4%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x140)++0x3 line.long 0x0 "P50$1PFS,Port 50%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x140)++0x1 line.word 0x0 "P50$1PFS_HA,Port 50%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x140)++0x0 line.byte 0x0 "P50$1PFS_BY,Port 50%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x168)++0x3 line.long 0x0 "P5$1PFS,Port 5%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x168)++0x1 line.word 0x0 "P5$1PFS_HA,Port 5%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x168)++0x0 line.byte 0x0 "P5$1PFS_BY,Port 5%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x180)++0x3 line.long 0x0 "P60$1PFS,Port 60%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x180)++0x1 line.word 0x0 "P60$1PFS_HA,Port 60%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x180)++0x0 line.byte 0x0 "P60$1PFS_BY,Port 60%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1A8)++0x3 line.long 0x0 "P6$1PFS,Port 6%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x1A8)++0x1 line.word 0x0 "P6$1PFS_HA,Port 6%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x1A8)++0x0 line.byte 0x0 "P6$1PFS_BY,Port 6%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1C0)++0x3 line.long 0x0 "P70$1PFS,Port 70%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x1C0)++0x1 line.word 0x0 "P70$1PFS_HA,Port 70%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x1C0)++0x0 line.byte 0x0 "P70$1PFS_BY,Port 70%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1E8)++0x3 line.long 0x0 "P7$1PFS,Port 7%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x1E8)++0x1 line.word 0x0 "P7$1PFS_HA,Port 7%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x1E8)++0x0 line.byte 0x0 "P7$1PFS_BY,Port 7%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "P80$1PFS,Port 80%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x200)++0x1 line.word 0x0 "P80$1PFS_HA,Port 80%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x200)++0x0 line.byte 0x0 "P80$1PFS_BY,Port 80%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x228)++0x3 line.long 0x0 "P8$1PFS,Port 8%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x228)++0x1 line.word 0x0 "P8$1PFS_HA,Port 8%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x228)++0x0 line.byte 0x0 "P8$1PFS_BY,Port 8%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x238)++0x3 line.long 0x0 "P8$1PFS,Port 8%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x238)++0x1 line.word 0x0 "P8$1PFS_HA,Port 8%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x238)++0x0 line.byte 0x0 "P8$1PFS_BY,Port 8%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x240)++0x3 line.long 0x0 "P90$1PFS,Port 90%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x240)++0x1 line.word 0x0 "P90$1PFS_HA,Port 90%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x240)++0x0 line.byte 0x0 "P90$1PFS_BY,Port 90%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x268)++0x3 line.long 0x0 "P9$1PFS,Port 9%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x268)++0x1 line.word 0x0 "P9$1PFS_HA,Port 9%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x268)++0x0 line.byte 0x0 "P9$1PFS_BY,Port 9%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x280)++0x3 line.long 0x0 "PA0$1PFS,Port A0%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x280)++0x1 line.word 0x0 "PA0$1PFS_HA,Port A0%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x280)++0x0 line.byte 0x0 "PA0$1PFS_BY,Port A0%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x2A8)++0x3 line.long 0x0 "PA$1PFS,Port An Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x2A8)++0x1 line.word 0x0 "PA$1PFS_HA,Port An Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x2A8)++0x0 line.byte 0x0 "PA$1PFS_BY,Port An Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x2C0)++0x3 line.long 0x0 "PB0$1PFS,Port B0%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" newline bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x2C0)++0x1 line.word 0x0 "PB0$1PFS_HA,Port B0%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x2C0)++0x0 line.byte 0x0 "PB0$1PFS_BY,Port B0%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end group.byte 0x514++0x0 line.byte 0x0 "PWPR_S,Write-Protect Register for Secure" bitfld.byte 0x0 7. "B0WI,PFSWE Bit Write Disable" "0: Enable writes the PFSWE bit,1: Disable writes to the PFSWE bit" bitfld.byte 0x0 6. "PFSWE,PmnPFS Register Write Enable" "0: Disable writes to the PmnPFS register,1: Enable writes to the PmnPFS register" repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x530)++0x1 line.word 0x0 "P$1SAR,Port Security Attribution register" hexmask.word 0x0 0.--15. 1. "PMNSA,Pmn Security Attribution" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x558)++0x1 line.word 0x0 "P$1SAR,Port Security Attribution register" hexmask.word 0x0 0.--15. 1. "PMNSA,Pmn Security Attribution" repeat.end tree.end tree "PFS_NS" base ad:0x50400800 repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "P00$1PFS,Port 00%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2)++0x1 line.word 0x0 "P00$1PFS_HA,Port 00%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2)++0x0 line.byte 0x0 "P00$1PFS_BY,Port 00%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x28)++0x3 line.long 0x0 "P0$1PFS,Port 0%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x28)++0x1 line.word 0x0 "P0$1PFS_HA,Port 0%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x28)++0x0 line.byte 0x0 "P0$1PFS_BY,Port 0%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x38)++0x3 line.long 0x0 "P0$1PFS,Port 0%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x38)++0x1 line.word 0x0 "P0$1PFS_HA,Port 0%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x38)++0x0 line.byte 0x0 "P0$1PFS_BY,Port 0%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "P10$1PFS,Port 10%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x40)++0x1 line.word 0x0 "P10$1PFS_HA,Port 10%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x40)++0x0 line.byte 0x0 "P10$1PFS_BY,Port 10%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "P1$1PFS,Port 1%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x70)++0x1 line.word 0x0 "P1$1PFS_HA,Port 1%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x70)++0x0 line.byte 0x0 "P1$1PFS_BY,Port 1%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end group.long 0x80++0x3 line.long 0x0 "P200PFS,Port 200 Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0x80++0x1 line.word 0x0 "P200PFS_HA,Port 200 Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" group.byte 0x80++0x0 line.byte 0x0 "P200PFS_BY,Port 200 Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" group.long 0x84++0x3 line.long 0x0 "P201PFS,Port 201 Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0x84++0x1 line.word 0x0 "P201PFS_HA,Port 201 Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" group.byte 0x84++0x0 line.byte 0x0 "P201PFS_BY,Port 201 Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x88)++0x3 line.long 0x0 "P20$1PFS,Port 20%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x88)++0x1 line.word 0x0 "P20$1PFS_HA,Port 20%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x88)++0x0 line.byte 0x0 "P20$1PFS_BY,Port 20%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end group.long 0xA0++0x3 line.long 0x0 "P208PFS,Port 208 Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0xA0++0x1 line.word 0x0 "P208PFS_HA,Port 208 Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" group.byte 0xA0++0x0 line.byte 0x0 "P208PFS_BY,Port 208 Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" group.long 0xA4++0x3 line.long 0x0 "P209PFS,Port 209 Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0xA4++0x1 line.word 0x0 "P209PFS_HA,Port 209 Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" group.byte 0xA4++0x0 line.byte 0x0 "P209PFS_BY,Port 209 Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" group.long 0xA8++0x3 line.long 0x0 "P210PFS,Port 210 Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0xA8++0x1 line.word 0x0 "P210PFS_HA,Port 210 Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" group.byte 0xA8++0x0 line.byte 0x0 "P210PFS_BY,Port 210 Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" group.long 0xAC++0x3 line.long 0x0 "P211PFS,Port 211 Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0xAC++0x1 line.word 0x0 "P211PFS_HA,Port 211 Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" group.byte 0xAC++0x0 line.byte 0x0 "P211PFS_BY,Port 211 Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xB0)++0x3 line.long 0x0 "P2$1PFS,Port 2%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0xB0)++0x1 line.word 0x0 "P2$1PFS_HA,Port 2%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0xB0)++0x0 line.byte 0x0 "P2$1PFS_BY,Port 2%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC0)++0x3 line.long 0x0 "P30$1PFS,Port 30%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0xC0)++0x1 line.word 0x0 "P30$1PFS_HA,Port 30%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0xC0)++0x0 line.byte 0x0 "P30$1PFS_BY,Port 30%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xE8)++0x3 line.long 0x0 "P3$1PFS,Port 3%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0xE8)++0x1 line.word 0x0 "P3$1PFS_HA,Port 3%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0xE8)++0x0 line.byte 0x0 "P3$1PFS_BY,Port 3%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x100)++0x3 line.long 0x0 "P40$1PFS,Port 40%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x100)++0x1 line.word 0x0 "P40$1PFS_HA,Port 40%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x100)++0x0 line.byte 0x0 "P40$1PFS_BY,Port 40%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x128)++0x3 line.long 0x0 "P4$1PFS,Port 4%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x128)++0x1 line.word 0x0 "P4$1PFS_HA,Port 4%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x128)++0x0 line.byte 0x0 "P4$1PFS_BY,Port 4%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x140)++0x3 line.long 0x0 "P50$1PFS,Port 50%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x140)++0x1 line.word 0x0 "P50$1PFS_HA,Port 50%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x140)++0x0 line.byte 0x0 "P50$1PFS_BY,Port 50%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x168)++0x3 line.long 0x0 "P5$1PFS,Port 5%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x168)++0x1 line.word 0x0 "P5$1PFS_HA,Port 5%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x168)++0x0 line.byte 0x0 "P5$1PFS_BY,Port 5%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x180)++0x3 line.long 0x0 "P60$1PFS,Port 60%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x180)++0x1 line.word 0x0 "P60$1PFS_HA,Port 60%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x180)++0x0 line.byte 0x0 "P60$1PFS_BY,Port 60%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1A8)++0x3 line.long 0x0 "P6$1PFS,Port 6%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x1A8)++0x1 line.word 0x0 "P6$1PFS_HA,Port 6%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x1A8)++0x0 line.byte 0x0 "P6$1PFS_BY,Port 6%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1C0)++0x3 line.long 0x0 "P70$1PFS,Port 70%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x1C0)++0x1 line.word 0x0 "P70$1PFS_HA,Port 70%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x1C0)++0x0 line.byte 0x0 "P70$1PFS_BY,Port 70%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1E8)++0x3 line.long 0x0 "P7$1PFS,Port 7%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x1E8)++0x1 line.word 0x0 "P7$1PFS_HA,Port 7%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x1E8)++0x0 line.byte 0x0 "P7$1PFS_BY,Port 7%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "P80$1PFS,Port 80%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x200)++0x1 line.word 0x0 "P80$1PFS_HA,Port 80%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x200)++0x0 line.byte 0x0 "P80$1PFS_BY,Port 80%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x228)++0x3 line.long 0x0 "P8$1PFS,Port 8%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x228)++0x1 line.word 0x0 "P8$1PFS_HA,Port 8%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x228)++0x0 line.byte 0x0 "P8$1PFS_BY,Port 8%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x238)++0x3 line.long 0x0 "P8$1PFS,Port 8%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x238)++0x1 line.word 0x0 "P8$1PFS_HA,Port 8%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x238)++0x0 line.byte 0x0 "P8$1PFS_BY,Port 8%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x240)++0x3 line.long 0x0 "P90$1PFS,Port 90%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x240)++0x1 line.word 0x0 "P90$1PFS_HA,Port 90%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x240)++0x0 line.byte 0x0 "P90$1PFS_BY,Port 90%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x268)++0x3 line.long 0x0 "P9$1PFS,Port 9%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x268)++0x1 line.word 0x0 "P9$1PFS_HA,Port 9%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x268)++0x0 line.byte 0x0 "P9$1PFS_BY,Port 9%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x280)++0x3 line.long 0x0 "PA0$1PFS,Port A0%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x280)++0x1 line.word 0x0 "PA0$1PFS_HA,Port A0%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x280)++0x0 line.byte 0x0 "PA0$1PFS_BY,Port A0%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x2A8)++0x3 line.long 0x0 "PA$1PFS,Port An Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x2A8)++0x1 line.word 0x0 "PA$1PFS_HA,Port An Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x2A8)++0x0 line.byte 0x0 "PA$1PFS_BY,Port An Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x2C0)++0x3 line.long 0x0 "PB0$1PFS,Port B0%s Pin Function Select Register" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select" bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" newline bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Not used as an analog pin,1: Used as an analog pin" bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Not used as an IRQn input pin,1: Used as an IRQn input pin" newline bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?" bitfld.long 0x0 10.--11. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive,?,?" newline bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: CMOS output,1: NMOS open-drain output" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up" newline bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rbitfld.long 0x0 1. "PIDR,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x2C0)++0x1 line.word 0x0 "PB0$1PFS_HA,Port B0%s Pin Function Select Register" hexmask.word.byte 0x0 8.--12. 1. "PSEL,Peripheral Select" bitfld.word 0x0 0. "PMR,Port Mode Control" "0: Used as a general I/O pin,1: Used as an I/O port for peripheral functions" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x2C0)++0x0 line.byte 0x0 "PB0$1PFS_BY,Port B0%s Pin Function Select Register" hexmask.byte 0x0 0.--4. 1. "PSEL,Peripheral Select" repeat.end group.byte 0x50C++0x0 line.byte 0x0 "PWPR_NS,Write-Protect Register for Non-secure" bitfld.byte 0x0 7. "B0WI,PFSWE Bit Write Disable" "0: Writing to the PFSWE bit is enabled,1: Writing to the PFSWE bit is disabled" bitfld.byte 0x0 6. "PFSWE,PmnPFS Register Write Enable" "0: Writing to the PmnPFS register is disabled,1: Writing to the PmnPFS register is enabled" repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x530)++0x1 line.word 0x0 "P$1SAR,Port Security Attribution register" hexmask.word 0x0 0.--15. 1. "PMNSA,Pmn Security Attribution" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x558)++0x1 line.word 0x0 "P$1SAR,Port Security Attribution register" hexmask.word 0x0 0.--15. 1. "PMNSA,Pmn Security Attribution" repeat.end tree.end tree.end tree "PORT (Port Control)" tree "PORT0" base ad:0x40400000 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x1 line.word 0x0 "PIDR,Port Control Register 2" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" tree.end tree "PORT0_NS" base ad:0x50400000 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x1 line.word 0x0 "PIDR,Port Control Register 2" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" tree.end tree "PORT1" base ad:0x40400020 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 31. "EIDR15,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 30. "EIDR14,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 29. "EIDR13,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 28. "EIDR12,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 27. "EIDR11,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 26. "EIDR10,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 25. "EIDR09,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 24. "EIDR08,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 23. "EIDR07,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 22. "EIDR06,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 21. "EIDR05,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 20. "EIDR04,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 19. "EIDR03,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 18. "EIDR02,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 17. "EIDR01,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 16. "EIDR00,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x3 line.word 0x0 "PIDR,Port Control Register 2" bitfld.word 0x0 15. "EIDR15,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 14. "EIDR14,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 13. "EIDR13,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 12. "EIDR12,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 11. "EIDR11,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 10. "EIDR10,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 9. "EIDR09,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 8. "EIDR08,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 7. "EIDR07,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 6. "EIDR06,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 5. "EIDR05,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 4. "EIDR04,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 3. "EIDR03,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 2. "EIDR02,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 1. "EIDR01,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 0. "EIDR00,Port Event Input Data" "0: Low input,1: High input" line.word 0x2 "EIDR,Port Control Register 2" bitfld.word 0x2 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 0. "PIDR00,Pmn State" "0: Low level,1: High level" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" group.long 0xC++0x3 line.long 0x0 "PCNTR4,Port Control Register 4" bitfld.long 0x0 31. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output" group.word 0xC++0x3 line.word 0x0 "EOSR,Port Control Register 4" bitfld.word 0x0 15. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "EORR,Port Control Register 4" bitfld.word 0x2 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output" tree.end tree "PORT1_NS" base ad:0x50400020 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 31. "EIDR15,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 30. "EIDR14,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 29. "EIDR13,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 28. "EIDR12,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 27. "EIDR11,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 26. "EIDR10,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 25. "EIDR09,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 24. "EIDR08,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 23. "EIDR07,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 22. "EIDR06,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 21. "EIDR05,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 20. "EIDR04,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 19. "EIDR03,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 18. "EIDR02,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 17. "EIDR01,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 16. "EIDR00,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x3 line.word 0x0 "PIDR,Port Control Register 2" bitfld.word 0x0 15. "EIDR15,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 14. "EIDR14,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 13. "EIDR13,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 12. "EIDR12,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 11. "EIDR11,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 10. "EIDR10,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 9. "EIDR09,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 8. "EIDR08,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 7. "EIDR07,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 6. "EIDR06,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 5. "EIDR05,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 4. "EIDR04,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 3. "EIDR03,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 2. "EIDR02,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 1. "EIDR01,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 0. "EIDR00,Port Event Input Data" "0: Low input,1: High input" line.word 0x2 "EIDR,Port Control Register 2" bitfld.word 0x2 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 0. "PIDR00,Pmn State" "0: Low level,1: High level" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" group.long 0xC++0x3 line.long 0x0 "PCNTR4,Port Control Register 4" bitfld.long 0x0 31. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output" group.word 0xC++0x3 line.word 0x0 "EOSR,Port Control Register 4" bitfld.word 0x0 15. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "EORR,Port Control Register 4" bitfld.word 0x2 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output" tree.end tree "PORT2" base ad:0x40400040 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 31. "EIDR15,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 30. "EIDR14,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 29. "EIDR13,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 28. "EIDR12,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 27. "EIDR11,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 26. "EIDR10,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 25. "EIDR09,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 24. "EIDR08,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 23. "EIDR07,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 22. "EIDR06,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 21. "EIDR05,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 20. "EIDR04,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 19. "EIDR03,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 18. "EIDR02,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 17. "EIDR01,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 16. "EIDR00,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x3 line.word 0x0 "PIDR,Port Control Register 2" bitfld.word 0x0 15. "EIDR15,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 14. "EIDR14,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 13. "EIDR13,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 12. "EIDR12,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 11. "EIDR11,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 10. "EIDR10,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 9. "EIDR09,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 8. "EIDR08,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 7. "EIDR07,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 6. "EIDR06,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 5. "EIDR05,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 4. "EIDR04,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 3. "EIDR03,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 2. "EIDR02,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 1. "EIDR01,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 0. "EIDR00,Port Event Input Data" "0: Low input,1: High input" line.word 0x2 "EIDR,Port Control Register 2" bitfld.word 0x2 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 0. "PIDR00,Pmn State" "0: Low level,1: High level" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" group.long 0xC++0x3 line.long 0x0 "PCNTR4,Port Control Register 4" bitfld.long 0x0 31. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output" group.word 0xC++0x3 line.word 0x0 "EOSR,Port Control Register 4" bitfld.word 0x0 15. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "EORR,Port Control Register 4" bitfld.word 0x2 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output" tree.end tree "PORT2_NS" base ad:0x50400040 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 31. "EIDR15,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 30. "EIDR14,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 29. "EIDR13,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 28. "EIDR12,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 27. "EIDR11,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 26. "EIDR10,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 25. "EIDR09,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 24. "EIDR08,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 23. "EIDR07,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 22. "EIDR06,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 21. "EIDR05,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 20. "EIDR04,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 19. "EIDR03,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 18. "EIDR02,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 17. "EIDR01,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 16. "EIDR00,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x3 line.word 0x0 "PIDR,Port Control Register 2" bitfld.word 0x0 15. "EIDR15,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 14. "EIDR14,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 13. "EIDR13,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 12. "EIDR12,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 11. "EIDR11,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 10. "EIDR10,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 9. "EIDR09,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 8. "EIDR08,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 7. "EIDR07,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 6. "EIDR06,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 5. "EIDR05,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 4. "EIDR04,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 3. "EIDR03,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 2. "EIDR02,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 1. "EIDR01,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 0. "EIDR00,Port Event Input Data" "0: Low input,1: High input" line.word 0x2 "EIDR,Port Control Register 2" bitfld.word 0x2 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 0. "PIDR00,Pmn State" "0: Low level,1: High level" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" group.long 0xC++0x3 line.long 0x0 "PCNTR4,Port Control Register 4" bitfld.long 0x0 31. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output" group.word 0xC++0x3 line.word 0x0 "EOSR,Port Control Register 4" bitfld.word 0x0 15. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "EORR,Port Control Register 4" bitfld.word 0x2 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output" tree.end tree "PORT3" base ad:0x40400060 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 31. "EIDR15,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 30. "EIDR14,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 29. "EIDR13,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 28. "EIDR12,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 27. "EIDR11,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 26. "EIDR10,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 25. "EIDR09,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 24. "EIDR08,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 23. "EIDR07,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 22. "EIDR06,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 21. "EIDR05,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 20. "EIDR04,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 19. "EIDR03,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 18. "EIDR02,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 17. "EIDR01,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 16. "EIDR00,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x3 line.word 0x0 "PIDR,Port Control Register 2" bitfld.word 0x0 15. "EIDR15,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 14. "EIDR14,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 13. "EIDR13,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 12. "EIDR12,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 11. "EIDR11,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 10. "EIDR10,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 9. "EIDR09,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 8. "EIDR08,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 7. "EIDR07,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 6. "EIDR06,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 5. "EIDR05,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 4. "EIDR04,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 3. "EIDR03,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 2. "EIDR02,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 1. "EIDR01,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 0. "EIDR00,Port Event Input Data" "0: Low input,1: High input" line.word 0x2 "EIDR,Port Control Register 2" bitfld.word 0x2 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 0. "PIDR00,Pmn State" "0: Low level,1: High level" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" group.long 0xC++0x3 line.long 0x0 "PCNTR4,Port Control Register 4" bitfld.long 0x0 31. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output" group.word 0xC++0x3 line.word 0x0 "EOSR,Port Control Register 4" bitfld.word 0x0 15. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "EORR,Port Control Register 4" bitfld.word 0x2 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output" tree.end tree "PORT3_NS" base ad:0x50400060 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 31. "EIDR15,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 30. "EIDR14,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 29. "EIDR13,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 28. "EIDR12,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 27. "EIDR11,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 26. "EIDR10,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 25. "EIDR09,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 24. "EIDR08,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 23. "EIDR07,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 22. "EIDR06,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 21. "EIDR05,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 20. "EIDR04,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 19. "EIDR03,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 18. "EIDR02,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 17. "EIDR01,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 16. "EIDR00,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x3 line.word 0x0 "PIDR,Port Control Register 2" bitfld.word 0x0 15. "EIDR15,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 14. "EIDR14,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 13. "EIDR13,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 12. "EIDR12,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 11. "EIDR11,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 10. "EIDR10,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 9. "EIDR09,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 8. "EIDR08,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 7. "EIDR07,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 6. "EIDR06,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 5. "EIDR05,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 4. "EIDR04,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 3. "EIDR03,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 2. "EIDR02,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 1. "EIDR01,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 0. "EIDR00,Port Event Input Data" "0: Low input,1: High input" line.word 0x2 "EIDR,Port Control Register 2" bitfld.word 0x2 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 0. "PIDR00,Pmn State" "0: Low level,1: High level" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" group.long 0xC++0x3 line.long 0x0 "PCNTR4,Port Control Register 4" bitfld.long 0x0 31. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output" group.word 0xC++0x3 line.word 0x0 "EOSR,Port Control Register 4" bitfld.word 0x0 15. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "EORR,Port Control Register 4" bitfld.word 0x2 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output" tree.end tree "PORT4" base ad:0x40400080 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 31. "EIDR15,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 30. "EIDR14,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 29. "EIDR13,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 28. "EIDR12,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 27. "EIDR11,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 26. "EIDR10,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 25. "EIDR09,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 24. "EIDR08,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 23. "EIDR07,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 22. "EIDR06,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 21. "EIDR05,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 20. "EIDR04,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 19. "EIDR03,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 18. "EIDR02,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 17. "EIDR01,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 16. "EIDR00,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x3 line.word 0x0 "PIDR,Port Control Register 2" bitfld.word 0x0 15. "EIDR15,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 14. "EIDR14,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 13. "EIDR13,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 12. "EIDR12,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 11. "EIDR11,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 10. "EIDR10,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 9. "EIDR09,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 8. "EIDR08,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 7. "EIDR07,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 6. "EIDR06,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 5. "EIDR05,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 4. "EIDR04,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 3. "EIDR03,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 2. "EIDR02,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 1. "EIDR01,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 0. "EIDR00,Port Event Input Data" "0: Low input,1: High input" line.word 0x2 "EIDR,Port Control Register 2" bitfld.word 0x2 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 0. "PIDR00,Pmn State" "0: Low level,1: High level" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" group.long 0xC++0x3 line.long 0x0 "PCNTR4,Port Control Register 4" bitfld.long 0x0 31. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output" group.word 0xC++0x3 line.word 0x0 "EOSR,Port Control Register 4" bitfld.word 0x0 15. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "EORR,Port Control Register 4" bitfld.word 0x2 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output" tree.end tree "PORT4_NS" base ad:0x50400080 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 31. "EIDR15,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 30. "EIDR14,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 29. "EIDR13,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 28. "EIDR12,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 27. "EIDR11,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 26. "EIDR10,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 25. "EIDR09,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 24. "EIDR08,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 23. "EIDR07,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 22. "EIDR06,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 21. "EIDR05,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 20. "EIDR04,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 19. "EIDR03,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 18. "EIDR02,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 17. "EIDR01,Port Event Input Data" "0: Low input,1: High input" newline bitfld.long 0x0 16. "EIDR00,Port Event Input Data" "0: Low input,1: High input" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x3 line.word 0x0 "PIDR,Port Control Register 2" bitfld.word 0x0 15. "EIDR15,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 14. "EIDR14,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 13. "EIDR13,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 12. "EIDR12,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 11. "EIDR11,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 10. "EIDR10,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 9. "EIDR09,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 8. "EIDR08,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 7. "EIDR07,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 6. "EIDR06,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 5. "EIDR05,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 4. "EIDR04,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 3. "EIDR03,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 2. "EIDR02,Port Event Input Data" "0: Low input,1: High input" bitfld.word 0x0 1. "EIDR01,Port Event Input Data" "0: Low input,1: High input" newline bitfld.word 0x0 0. "EIDR00,Port Event Input Data" "0: Low input,1: High input" line.word 0x2 "EIDR,Port Control Register 2" bitfld.word 0x2 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.word 0x2 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.word 0x2 0. "PIDR00,Pmn State" "0: Low level,1: High level" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" group.long 0xC++0x3 line.long 0x0 "PCNTR4,Port Control Register 4" bitfld.long 0x0 31. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output" group.word 0xC++0x3 line.word 0x0 "EOSR,Port Control Register 4" bitfld.word 0x0 15. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "EORR,Port Control Register 4" bitfld.word 0x2 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output" tree.end tree "PORT5" base ad:0x404000A0 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x1 line.word 0x0 "PIDR,Port Control Register 2" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" tree.end tree "PORT5_NS" base ad:0x504000A0 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x1 line.word 0x0 "PIDR,Port Control Register 2" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" tree.end tree "PORT6" base ad:0x404000C0 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x1 line.word 0x0 "PIDR,Port Control Register 2" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" tree.end tree "PORT6_NS" base ad:0x504000C0 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x1 line.word 0x0 "PIDR,Port Control Register 2" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" tree.end tree "PORT7" base ad:0x404000E0 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x1 line.word 0x0 "PIDR,Port Control Register 2" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" tree.end tree "PORT7_NS" base ad:0x504000E0 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x1 line.word 0x0 "PIDR,Port Control Register 2" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" tree.end tree "PORT8" base ad:0x40400100 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x1 line.word 0x0 "PIDR,Port Control Register 2" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" tree.end tree "PORT8_NS" base ad:0x50400100 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x1 line.word 0x0 "PIDR,Port Control Register 2" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" tree.end tree "PORT9" base ad:0x40400120 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x1 line.word 0x0 "PIDR,Port Control Register 2" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" tree.end tree "PORT9_NS" base ad:0x50400120 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x1 line.word 0x0 "PIDR,Port Control Register 2" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" tree.end tree "PORTA" base ad:0x40400140 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x1 line.word 0x0 "PIDR,Port Control Register 2" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" tree.end tree "PORTA_NS" base ad:0x50400140 rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x1 line.word 0x0 "PIDR,Port Control Register 2" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" tree.end tree "PORTB" base ad:0x40400160 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output" bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" group.word 0x0++0x3 line.word 0x0 "PDR,Port Control Register 1" bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output" bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output" newline bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output" line.word 0x2 "PODR,Port Control Register 1" bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" newline bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x1 line.word 0x0 "PIDR,Port Control Register 2" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" tree.end tree "PORTB_NS" base ad:0x50400160 rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level" newline bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level" bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level" rgroup.word 0x4++0x1 line.word 0x0 "PIDR,Port Control Register 2" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" wgroup.word 0x8++0x3 line.word 0x0 "POSR,Port Control Register 3" bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output" newline bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output" bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output" line.word 0x2 "PORR,Port Control Register 3" bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output" newline bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output" bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output" tree.end tree.end tree.end tree "IWDT (Independent Watchdog Timer)" base ad:0x0 tree "IWDT" base ad:0x40202200 group.byte 0x0++0x0 line.byte 0x0 "IWDTRR,IWDT Refresh Register" hexmask.byte 0x0 0.--7. 1. "REFRESH,Refresh Register" group.word 0x2++0x3 line.word 0x0 "IWDTCR,IWDT Control Register" bitfld.word 0x0 12.--13. "RPSS,Window Start Position Select" "0: 25%,1: 50%,?,?" bitfld.word 0x0 8.--9. "RPES,Window End Position Select" "0: 75%,1: 50%,?,?" hexmask.word.byte 0x0 4.--7. 1. "CKS,Clock Division Ratio Select" bitfld.word 0x0 0.--1. "TOPS,Timeout Period Select" "0: 128 cycles (0x007F),1: 512 cycles (0x01FF),?,?" line.word 0x2 "IWDTSR,IWDT Status Register" bitfld.word 0x2 15. "REFEF,Refresh Error Flag" "0: No refresh error occurred.,1: Refresh error occurred." bitfld.word 0x2 14. "UNDFF,Underflow Flag" "0: No underflow occurred.,1: Underflow occurred." hexmask.word 0x2 0.--13. 1. "CNTVAL,Down-Counter Value" group.byte 0x6++0x0 line.byte 0x0 "IWDTRCR,IWDT Reset Control Register" bitfld.byte 0x0 7. "RSTIRQS,Reset Interrupt Request Select" "0: Enable non-maskable interrupt requests or..,1: Enable reset output." group.byte 0x8++0x0 line.byte 0x0 "IWDTCSTPR,IWDT Count Stop Control Register" bitfld.byte 0x0 7. "SLCSTP,CPU Sleep-Mode Count Stop Select" "0: Disable count stop.,1: Stop the counter when the CPU enters CPU Sleep.." tree.end tree "IWDT_NS" base ad:0x50202200 group.byte 0x0++0x0 line.byte 0x0 "IWDTRR,IWDT Refresh Register" hexmask.byte 0x0 0.--7. 1. "REFRESH,Refresh Register" group.word 0x2++0x3 line.word 0x0 "IWDTCR,IWDT Control Register" bitfld.word 0x0 12.--13. "RPSS,Window Start Position Select" "0: 25%,1: 50%,?,?" bitfld.word 0x0 8.--9. "RPES,Window End Position Select" "0: 75%,1: 50%,?,?" hexmask.word.byte 0x0 4.--7. 1. "CKS,Clock Division Ratio Select" bitfld.word 0x0 0.--1. "TOPS,Timeout Period Select" "0: 128 cycles (0x007F),1: 512 cycles (0x01FF),?,?" line.word 0x2 "IWDTSR,IWDT Status Register" bitfld.word 0x2 15. "REFEF,Refresh Error Flag" "0: No refresh error occurred.,1: Refresh error occurred." bitfld.word 0x2 14. "UNDFF,Underflow Flag" "0: No underflow occurred.,1: Underflow occurred." hexmask.word 0x2 0.--13. 1. "CNTVAL,Down-Counter Value" group.byte 0x6++0x0 line.byte 0x0 "IWDTRCR,IWDT Reset Control Register" bitfld.byte 0x0 7. "RSTIRQS,Reset Interrupt Request Select" "0: Enable non-maskable interrupt requests or..,1: Enable reset output." group.byte 0x8++0x0 line.byte 0x0 "IWDTCSTPR,IWDT Count Stop Control Register" bitfld.byte 0x0 7. "SLCSTP,CPU Sleep-Mode Count Stop Select" "0: Disable count stop.,1: Stop the counter when the CPU enters CPU Sleep.." tree.end tree.end tree "MSTP (Module Stop Control Register)" base ad:0x0 tree "MSTP" base ad:0x40203000 group.long 0x0++0x13 line.long 0x0 "MSTPCRA,Module Stop Control Register A" bitfld.long 0x0 22. "MSTPA22,DMA Controller and Data Transfer Controller Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x0 15. "MSTPA15,Standby SRAM Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x0 1. "MSTPA1,SRAM1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x0 0. "MSTPA0,SRAM0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" line.long 0x4 "MSTPCRB,Module Stop Control Register B" bitfld.long 0x4 31. "MSTPB31,Serial Communication Interface 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 30. "MSTPB30,Serial Communication Interface 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 29. "MSTPB29,Serial Communication Interface 2 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x4 28. "MSTPB28,Serial Communication Interface 3 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 27. "MSTPB27,Serial Communication Interface 4 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 22. "MSTPB22,Serial Communication Interface 9 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x4 19. "MSTPB19,Serial Peripheral Interface 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 18. "MSTPB18,Serial Peripheral Interface 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 16. "MSTPB16,Octal Serial Peripheral Interface Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x4 11. "MSTPB11,Universal Serial Bus 2.0 FS Interface Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 9. "MSTPB9,I2C Bus Interface 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 8. "MSTPB8,I2C Bus Interface 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" line.long 0x8 "MSTPCRC,Module Stop Control Register C" bitfld.long 0x8 31. "MSTPC31,Renesas Secure IP Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 27. "MSTPC27,Controller Area Network with Flexible Data-Rate 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 26. "MSTPC26,Controller Area Network with Flexible Data-Rate 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x8 14. "MSTPC14,Event Link Controller Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 13. "MSTPC13,Data Operation Circuit Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 8. "MSTPC8,Serial Sound Interface Enhanced 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x8 7. "MSTPC7,Serial Sound Interface Enhanced 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 6. "MSTPC6,2D Drawing Engine Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 4. "MSTPC4,Graphics LCD Controller Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x8 1. "MSTPC1,Cyclic Redundancy Check Calculator Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 0. "MSTPC0,Clock Frequency Accuracy Measurement Circuit Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" line.long 0xC "MSTPCRD,Module Stop Control Register D" bitfld.long 0xC 28. "MSTPD28,High-Speed Analog Comparator 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0xC 27. "MSTPD27,High-Speed Analog Comparator 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0xC 22. "MSTPD22,Temperature Sensor Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0xC 20. "MSTPD20,12-bit D/A Converter Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0xC 16. "MSTPD16,12-bit A/D Converter 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0xC 15. "MSTPD15,12-bit A/D Converter 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0xC 14. "MSTPD14,Port Output Enable for GPT Group A Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0xC 13. "MSTPD13,Port Output Enable for GPT Group B Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0xC 12. "MSTPD12,Port Output Enable for GPT Group C Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0xC 11. "MSTPD11,Port Output Enable for GPT Group D Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0xC 5. "MSTPD5,Low Power Asynchronous General Purpose Timer 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0xC 4. "MSTPD4,Low Power Asynchronous General Purpose Timer 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" line.long 0x10 "MSTPCRE,Module Stop Control Register E" bitfld.long 0x10 31. "MSTPE31,General PWM Timer 0 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x10 30. "MSTPE30,General PWM Timer 1 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x10 29. "MSTPE29,General PWM Timer 2 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x10 28. "MSTPE28,General PWM Timer 3 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x10 27. "MSTPE27,General PWM Timer 4 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x10 26. "MSTPE26,General PWM Timer 5 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x10 21. "MSTPE21,General PWM Timer 10 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x10 20. "MSTPE20,General PWM Timer 11 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x10 19. "MSTPE19,General PWM Timer 12 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x10 18. "MSTPE18,General PWM Timer 13 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x10 9. "MSTPE9,Ultra-Low Power Timer 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x10 8. "MSTPE8,Ultra-Low Power Timer 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" tree.end tree "MSTP_NS" base ad:0x50203000 group.long 0x0++0x13 line.long 0x0 "MSTPCRA,Module Stop Control Register A" bitfld.long 0x0 22. "MSTPA22,DMA Controller and Data Transfer Controller Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x0 15. "MSTPA15,Standby SRAM Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x0 1. "MSTPA1,SRAM1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x0 0. "MSTPA0,SRAM0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" line.long 0x4 "MSTPCRB,Module Stop Control Register B" bitfld.long 0x4 31. "MSTPB31,Serial Communication Interface 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 30. "MSTPB30,Serial Communication Interface 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 29. "MSTPB29,Serial Communication Interface 2 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x4 28. "MSTPB28,Serial Communication Interface 3 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 27. "MSTPB27,Serial Communication Interface 4 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 22. "MSTPB22,Serial Communication Interface 9 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x4 19. "MSTPB19,Serial Peripheral Interface 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 18. "MSTPB18,Serial Peripheral Interface 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 16. "MSTPB16,Octal Serial Peripheral Interface Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x4 11. "MSTPB11,Universal Serial Bus 2.0 FS Interface Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 9. "MSTPB9,I2C Bus Interface 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 8. "MSTPB8,I2C Bus Interface 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" line.long 0x8 "MSTPCRC,Module Stop Control Register C" bitfld.long 0x8 31. "MSTPC31,Renesas Secure IP Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 27. "MSTPC27,Controller Area Network with Flexible Data-Rate 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 26. "MSTPC26,Controller Area Network with Flexible Data-Rate 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x8 14. "MSTPC14,Event Link Controller Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 13. "MSTPC13,Data Operation Circuit Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 8. "MSTPC8,Serial Sound Interface Enhanced 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x8 7. "MSTPC7,Serial Sound Interface Enhanced 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 6. "MSTPC6,2D Drawing Engine Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 4. "MSTPC4,Graphics LCD Controller Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x8 1. "MSTPC1,Cyclic Redundancy Check Calculator Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 0. "MSTPC0,Clock Frequency Accuracy Measurement Circuit Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" line.long 0xC "MSTPCRD,Module Stop Control Register D" bitfld.long 0xC 28. "MSTPD28,High-Speed Analog Comparator 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0xC 27. "MSTPD27,High-Speed Analog Comparator 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0xC 22. "MSTPD22,Temperature Sensor Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0xC 20. "MSTPD20,12-bit D/A Converter Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0xC 16. "MSTPD16,12-bit A/D Converter 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0xC 15. "MSTPD15,12-bit A/D Converter 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0xC 14. "MSTPD14,Port Output Enable for GPT Group A Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0xC 13. "MSTPD13,Port Output Enable for GPT Group B Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0xC 12. "MSTPD12,Port Output Enable for GPT Group C Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0xC 11. "MSTPD11,Port Output Enable for GPT Group D Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0xC 5. "MSTPD5,Low Power Asynchronous General Purpose Timer 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0xC 4. "MSTPD4,Low Power Asynchronous General Purpose Timer 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" line.long 0x10 "MSTPCRE,Module Stop Control Register E" bitfld.long 0x10 31. "MSTPE31,General PWM Timer 0 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x10 30. "MSTPE30,General PWM Timer 1 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x10 29. "MSTPE29,General PWM Timer 2 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x10 28. "MSTPE28,General PWM Timer 3 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x10 27. "MSTPE27,General PWM Timer 4 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x10 26. "MSTPE26,General PWM Timer 5 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x10 21. "MSTPE21,General PWM Timer 10 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x10 20. "MSTPE20,General PWM Timer 11 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x10 19. "MSTPE19,General PWM Timer 12 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x10 18. "MSTPE18,General PWM Timer 13 Module" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x10 9. "MSTPE9,Ultra-Low Power Timer 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x10 8. "MSTPE8,Ultra-Low Power Timer 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" tree.end tree.end tree "OCD (On-Chip Debug)" base ad:0x0 tree "OCD_CPU" base ad:0x40011000 group.long 0x4++0x3 line.long 0x0 "MCUCTRL,MCU Control Register" bitfld.long 0x0 16. "CPUWAIT" "0: Deassert CPUWAIT CPU starts boot-up sequence and..,1: Assert CPUWAIT CPU is forced into a quiescent.." bitfld.long 0x0 0. "EDBGRQ,External Debug Request. Writing 1 to the bit causes a CPU Halt or Debug Monitor exception request." "0: Debug event is not requested,1: Debug event is requested" group.long 0x100++0x3 line.long 0x0 "JBMDR,JTAG Boot Mode Entry Register" hexmask.long.byte 0x0 0.--7. 1. "KEY,Mode entry key" group.long 0x120++0x3 line.long 0x0 "JBRDR,JTAG Boot Receive Data Register" hexmask.long 0x0 0.--31. 1. "RDAT,Received data register" group.long 0x130++0x3 line.long 0x0 "JBTDR,JTAG Boot Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TDAT,Transmitted data register" group.long 0x140++0x3 line.long 0x0 "JBSTR,JTAG Boot Status Register" bitfld.long 0x0 1. "TDE,Transmit data empty" "0: There is data transmission,1: No data transmission" bitfld.long 0x0 0. "RDF,Receive buffer full" "0: No receiving data,1: There is receiving data" group.long 0x150++0x3 line.long 0x0 "JBICR,JTAG Boot Interrupt Control Register" bitfld.long 0x0 0. "RDFIE,Receive buffer full interrupt enabled" "0: Interrupt request disabled by RDF = 1,1: Enable interrupt request by RDF = 1" tree.end tree "OCD_CPU_NS" base ad:0x50011000 group.long 0x4++0x3 line.long 0x0 "MCUCTRL,MCU Control Register" bitfld.long 0x0 16. "CPUWAIT" "0: Deassert CPUWAIT CPU starts boot-up sequence and..,1: Assert CPUWAIT CPU is forced into a quiescent.." bitfld.long 0x0 0. "EDBGRQ,External Debug Request. Writing 1 to the bit causes a CPU Halt or Debug Monitor exception request." "0: Debug event is not requested,1: Debug event is requested" group.long 0x100++0x3 line.long 0x0 "JBMDR,JTAG Boot Mode Entry Register" hexmask.long.byte 0x0 0.--7. 1. "KEY,Mode entry key" group.long 0x120++0x3 line.long 0x0 "JBRDR,JTAG Boot Receive Data Register" hexmask.long 0x0 0.--31. 1. "RDAT,Received data register" group.long 0x130++0x3 line.long 0x0 "JBTDR,JTAG Boot Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TDAT,Transmitted data register" group.long 0x140++0x3 line.long 0x0 "JBSTR,JTAG Boot Status Register" bitfld.long 0x0 1. "TDE,Transmit data empty" "0: There is data transmission,1: No data transmission" bitfld.long 0x0 0. "RDF,Receive buffer full" "0: No receiving data,1: There is receiving data" group.long 0x150++0x3 line.long 0x0 "JBICR,JTAG Boot Interrupt Control Register" bitfld.long 0x0 0. "RDFIE,Receive buffer full interrupt enabled" "0: Interrupt request disabled by RDF = 1,1: Enable interrupt request by RDF = 1" tree.end tree.end tree "OSPI (Octa Serial Peripheral Interface)" base ad:0x0 tree "OSPI0_B" base ad:0x40268000 group.long 0x0++0x7 line.long 0x0 "WRAPCFG,OSPI Wrapper Configuration Register" hexmask.long.byte 0x0 24.--28. 1. "DSSFTCS1,OM_DQS shift for slave1" hexmask.long.byte 0x0 8.--12. 1. "DSSFTCS0,OM_DQS shift for slave0" line.long 0x4 "COMCFG,OSPI Common Configuration Register" bitfld.long 0x4 17. "OENEGEX,Output Enable Negating extension" "0: No extend 1 cycle Output enable,1: Extend 1 cycle Output enable" bitfld.long 0x4 16. "OEASTEX,Output Enable Asserting extension" "0: No extend 1 cycle Output enable,1: Extend 1 cycle Output enable" newline bitfld.long 0x4 0.--1. "ARBMD,Channel arbitration mode" "0: Round-Robbin (ch0-ch1-ch0-ch1…),1: Always ch0 win,?,?" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x8)++0x3 line.long 0x0 "BMCFGCH$1,OSPI Bridge Map Configuration Register chn (n = 0. 1)" hexmask.long.byte 0x0 24.--31. 1. "CMBTIM,Combination timer" bitfld.long 0x0 16. "PREEN,Prefetch enable" "0: Disable prefetch function,1: Enable prefetch function" newline hexmask.long.byte 0x0 8.--15. 1. "MWRSIZE,Memory Write Size" bitfld.long 0x0 7. "MWRCOMB,Memory Write Combination mode" "0: Disable combination mode,1: Enable combination mode" newline bitfld.long 0x0 0. "WRMD,System bus Write Response mode" "0: Return response after storing to Internal Write..,1: Return response after issuing write transaction.." repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x10)++0x3 line.long 0x0 "CMCFG0CS$1,OSPI Command Map Configuration Register 0 CSn" hexmask.long.byte 0x0 24.--31. 1. "ADDRPCD,Address Replace Code" hexmask.long.byte 0x0 16.--23. 1. "ADDRPEN,Address Replace Enable" newline bitfld.long 0x0 5. "ARYAMD,Array address mode" "0: Normal address mode,1: Array address mode" bitfld.long 0x0 4. "WPBSTMD,Wrapping burst mode" "0: Separate xSPI transfer at the wrapping address..,1: Not separate xSPI transfer at the wrapping.." newline bitfld.long 0x0 2.--3. "ADDSIZE,Address size" "0: 1 byte (256-byte address space),1: 2 bytes (64 KB address space),?,?" bitfld.long 0x0 0.--1. "FFMT,Frame format" "0: Normal format: Command 1 byte Address ADDSIZE..,1: 8D-8D-8D profile 1.0 format: Command 2 bytes..,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x14)++0x3 line.long 0x0 "CMCFG1CS$1,OSPI Command Map Configuration Register 1 CSn" hexmask.long.byte 0x0 16.--20. 1. "RDLATE,Read latency cycle" hexmask.long.word 0x0 0.--15. 1. "RDCMD,Read command" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x18)++0x3 line.long 0x0 "CMCFG2CS$1,OSPI Command Map Configuration Register 2 CSn" hexmask.long.byte 0x0 16.--20. 1. "WRLATE,Write latency cycle" hexmask.long.word 0x0 0.--15. 1. "WRCMD,Write command" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "LIOCFGCS$1,OSPI Link I/O Configuration Register CSn" hexmask.long.byte 0x0 28.--31. 1. "DDRSMPEX,DDR sampling window extend" hexmask.long.byte 0x0 24.--27. 1. "SDRSMPSFT,SDR Sampling window shift" newline bitfld.long 0x0 23. "SDRSMPMD,SDR Sampling mode" "0: Samples data input at falling-edge,1: Samples data input at rising-edge" bitfld.long 0x0 22. "SDRDRV,SDR driving timing" "0: Drive at 1/2 cycle before CK rising-edge,1: Drive at CK rising-edge" newline bitfld.long 0x0 21. "CSNEGEX,CS negating extension" "0: No extension,1: Extend 1 cycle" bitfld.long 0x0 20. "CSASTEX,CS asserting extension" "0: No extension,1: Extend 1 cycle" newline hexmask.long.byte 0x0 16.--19. 1. "CSMIN,CS minimum idle term" bitfld.long 0x0 11. "WRMSKMD,Write mask mode" "0: Write mask disable,1: Write mask enable" newline bitfld.long 0x0 10. "LATEMD,Latency mode" "0,1" hexmask.long.word 0x0 0.--9. 1. "PRTMD,Protocol mode" repeat.end group.long 0x60++0x3 line.long 0x0 "BMCTL0,OSPI Bridge Map Control Register 0" bitfld.long 0x0 6.--7. "CH1CS1ACC,System bus ch1 to slave1 memory area access enable" "0: Read/Write disable,1: Read enable Write disable,?,?" bitfld.long 0x0 4.--5. "CH1CS0ACC,System bus ch1 to slave0 memory area access enable" "0: Read/Write disable,1: Read enable Write disable,?,?" newline bitfld.long 0x0 2.--3. "CH0CS1ACC,System bus ch0 to slave1 memory area access enable" "0: Read/Write disable,1: Read enable Write disable,?,?" bitfld.long 0x0 0.--1. "CH0CS0ACC,System bus ch0 to slave0 memory area access enable" "0: Read/Write disable,1: Read enable Write disable,?,?" wgroup.long 0x64++0x3 line.long 0x0 "BMCTL1,OSPI Bridge Map Control Register 1" bitfld.long 0x0 11. "PBUFCLRCH1,Prefetch Buffer clear for ch1" "0,1" bitfld.long 0x0 10. "PBUFCLRCH0,Prefetch Buffer clear for ch0" "0: No command,1: Clear request" newline bitfld.long 0x0 9. "MWRPUSHCH1,Memory Write Data Push for ch1" "0,1" bitfld.long 0x0 8. "MWRPUSHCH0,Memory Write Data Push for ch0" "0: No command,1: Push request" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x68)++0x3 line.long 0x0 "CMCTLCH$1,OSPI Command Map Control register chn (n = 0. 1)" bitfld.long 0x0 16. "XIPEN,XiP mode enable" "0: Disable XiP mode,1: Enable XiP mode" hexmask.long.byte 0x0 8.--15. 1. "XIPEXCODE,XiP mode exit code" newline hexmask.long.byte 0x0 0.--7. 1. "XIPENCODE,XiP mode enter code" repeat.end group.long 0x70++0xB line.long 0x0 "CDCTL0,OSPI Command Manual Control Register 0" hexmask.long.byte 0x0 24.--27. 1. "PERREP,Periodic transaction repeat" hexmask.long.byte 0x0 16.--20. 1. "PERITV,Periodic transaction interval" newline bitfld.long 0x0 4.--5. "TRNUM,Transaction number" "0: Issue 1 command (using command buffer 0),1: Issue 2 commands (using command buffer 0-1),?,?" bitfld.long 0x0 3. "CSSEL,Chip select" "0: CS0,1: CS1" newline bitfld.long 0x0 1. "PERMD,Periodic mode" "0: Direct manual-command mode,1: Periodic manual-command mode" bitfld.long 0x0 0. "TRREQ,Transaction request" "0: No transaction,1: Request transaction" line.long 0x4 "CDCTL1,OSPI Command Manual Control Register 1" hexmask.long 0x4 0.--31. 1. "PEREXP,Periodic transaction expected value" line.long 0x8 "CDCTL2,OSPI Command Manual Control Register 2" hexmask.long 0x8 0.--31. 1. "PERMSK,Periodic transaction masked value" repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x80)++0x3 line.long 0x0 "CDTBUF$1,OSPI Command Manual Type Buf %s" hexmask.long.word 0x0 16.--31. 1. "CMD,Command (1-2 bytes)" bitfld.long 0x0 15. "TRTYPE,Transaction Type" "0: Read transaction (Readout data from slave device),1: Not read transaction" newline hexmask.long.byte 0x0 9.--13. 1. "LATE,Latency cycle" hexmask.long.byte 0x0 5.--8. 1. "DATASIZE,Write/Read Data Size" newline bitfld.long 0x0 2.--4. "ADDSIZE,Address size" "0: Setting prohibited,1: 1 byte,?,?,?,?,?,?" bitfld.long 0x0 0.--1. "CMDSIZE,Command Size" "0: Setting prohibited,1: 1 byte,?,?" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x84)++0x3 line.long 0x0 "CDABUF$1,OSPI Command Manual Address Buf %s" hexmask.long 0x0 0.--31. 1. "ADD,Address" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x88)++0x3 line.long 0x0 "CDD0BUF$1,OSPI Command Manual Data 0 Buf %s" hexmask.long 0x0 0.--31. 1. "DATA,Write/Read Data" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x8C)++0x3 line.long 0x0 "CDD1BUF$1,OSPI Command Manual Data 1 Buf %s" hexmask.long 0x0 0.--31. 1. "DATA,Write/Read Data" repeat.end group.long 0x100++0xB line.long 0x0 "LPCTL0,OSPI Link Pattern Control Register 0" bitfld.long 0x0 31. "XD2VAL,XiP Disable pattern 2nd phase value" "0: Low drive,1: High drive" hexmask.long.byte 0x0 24.--28. 1. "XD2LEN,XiP Disable pattern 2nd phase length" newline bitfld.long 0x0 23. "XD1VAL,XiP Disable pattern 1st phase value" "0: Low drive,1: High drive" hexmask.long.byte 0x0 16.--20. 1. "XD1LEN,XiP Disable pattern 1st phase length" newline bitfld.long 0x0 4.--5. "XDPIN,XiP Disable pattern pin" "0: 1 pin,1: 2 pins,?,?" bitfld.long 0x0 3. "CSSEL,Chip select" "0: slave0 (CS0),1: slave1 (CS1)" newline bitfld.long 0x0 0. "PATREQ,Pattern request" "0: No request XiP Disable pattern,1: Request XiP Disable pattern" line.long 0x4 "LPCTL1,OSPI Link Pattern Control Register 1" bitfld.long 0x4 12.--14. "RSTSU,Reset pattern data output setup time" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "RSTWID,Reset pattern width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--5. "RSTREP,Reset pattern repeat" "0: 4 times (Specified on Reset Signaling Protocol),1: 5 times,?,?" bitfld.long 0x4 3. "CSSEL,Chip select" "0: slave0 (CS0),1: slave1 (CS1)" newline bitfld.long 0x4 0.--1. "PATREQ,Pattern request" "0: No request,1: Request Reset pattern,?,?" line.long 0x8 "LIOCTL,OSPI Link I/O Control Register" bitfld.long 0x8 16. "RSTCS0,Reset drive" "0: Drive Low level,1: Drive High level" bitfld.long 0x8 1. "WPCS1,WP drive for slave1" "0: Drive Low level,1: Drive High level" repeat 2. (increment 0x0 0x1)(increment 0x0 0x20) group.long ($2+0x130)++0x3 line.long 0x0 "CCCTL0CS$1,OSPI Command Calibration Control Register 0 CSn" hexmask.long.byte 0x0 24.--28. 1. "CASFTEND,Calibration OM_DQS shift end value" hexmask.long.byte 0x0 16.--20. 1. "CASFTSTA,Calibration OM_DQS shift start value" newline hexmask.long.byte 0x0 8.--12. 1. "CAITV,Calibration interval" bitfld.long 0x0 1. "CANOWR,Calibration no write mode" "0: Calibration sequence with write command,1: Calibration sequence without write command" newline bitfld.long 0x0 0. "CAEN,Automatic Calibration Enable" "0: Disable automatic calibration,1: Enable automatic calibration" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x20) group.long ($2+0x134)++0x3 line.long 0x0 "CCCTL1CS$1,OSPI Command Calibration Control Register 1 CSn" hexmask.long.byte 0x0 24.--28. 1. "CARDLATE,Read Latency cycle" hexmask.long.byte 0x0 16.--20. 1. "CAWRLATE,Write Latency cycle" newline hexmask.long.byte 0x0 5.--8. 1. "CADATASIZE,Write/Read Data Size" bitfld.long 0x0 2.--4. "CAADDSIZE,Address size" "0: Setting prohibited,1: 1 byte,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "CACMDSIZE,Command Size" "0: 0 bytes (No command phase),1: 1 byte,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x20) group.long ($2+0x138)++0x3 line.long 0x0 "CCCTL2CS$1,OSPI Command Calibration Control Register 2 CSn" hexmask.long.word 0x0 16.--31. 1. "CARDCMD,Calibration pattern read command" hexmask.long.word 0x0 0.--15. 1. "CAWRCMD,Calibration pattern write command" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x20) group.long ($2+0x13C)++0x3 line.long 0x0 "CCCTL3CS$1,OSPI Command Calibration Control Register 3 CSn" hexmask.long 0x0 0.--31. 1. "CAADD,Calibration pattern address" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x20) group.long ($2+0x140)++0x3 line.long 0x0 "CCCTL4CS$1,OSPI Command Calibration Control Register 4 CSn" hexmask.long 0x0 0.--31. 1. "CADATA,Calibration pattern data" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x20) group.long ($2+0x144)++0x3 line.long 0x0 "CCCTL5CS$1,OSPI Command Calibration Control Register 5 CSn" hexmask.long 0x0 0.--31. 1. "CADATA,Calibration pattern data" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x20) group.long ($2+0x148)++0x3 line.long 0x0 "CCCTL6CS$1,OSPI Command Calibration Control Register 6 CSn" hexmask.long 0x0 0.--31. 1. "CADATA,Calibration pattern data" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x20) group.long ($2+0x14C)++0x3 line.long 0x0 "CCCTL7CS$1,OSPI Command Calibration Control Register 7 CSn" hexmask.long 0x0 0.--31. 1. "CADATA,Calibration pattern data" repeat.end rgroup.long 0x184++0x3 line.long 0x0 "COMSTT,OSPI Common Status Register" bitfld.long 0x0 22. "RSTOCS1,RSTO monitor for slave1" "0: Low level,1: High level" bitfld.long 0x0 21. "INTCS1,INT monitor for slave1" "0: Low level,1: High level" newline bitfld.long 0x0 20. "ECSCS1,ECS monitor for slave1" "0: Low level,1: High level" bitfld.long 0x0 7. "WRBUFNECH1,Write Buffer Not Empty for ch1" "0,1" newline bitfld.long 0x0 6. "WRBUFNECH0,Write Buffer Not Empty for ch0" "0: Empty,1: Not empty" bitfld.long 0x0 5. "PBUFNECH1,Prefetch Buffer Not Empty for ch1" "0,1" newline bitfld.long 0x0 4. "PBUFNECH0,Prefetch Buffer Not Empty for ch0" "0: Empty,1: Not empty" bitfld.long 0x0 1. "MEMACCCH1,Memory access ongoing from ch1" "0,1" newline bitfld.long 0x0 0. "MEMACCCH0,Memory access ongoing from ch0" "0: System bus bridge ch0 is not accessing to memory.,1: System bus bridge ch0 is accessing to memory." repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x188)++0x3 line.long 0x0 "CASTTCS$1,OSPI Calibration Status Register CSn" hexmask.long 0x0 0.--31. 1. "CASUC,Calibration Success" repeat.end rgroup.long 0x190++0x3 line.long 0x0 "INTS,OSPI Interrupt Status Register" bitfld.long 0x0 31. "CASUCCS1,Calibration success for slave1" "0: No detection,1: Detection" bitfld.long 0x0 30. "CASUCCS0,Calibration success for slave0" "0: No detection,1: Detection" newline bitfld.long 0x0 29. "CAFAILCS1,Calibration failed for slave1" "0: No detection,1: Detection" bitfld.long 0x0 28. "CAFAILCS0,Calibration failed for slave0" "0: No detection,1: Detection" newline bitfld.long 0x0 21. "BUSERRCH1,System bus error for ch1" "0,1" bitfld.long 0x0 20. "BUSERRCH0,System bus error for ch0" "0,1" newline bitfld.long 0x0 13. "INTCS1,Interrupt detection for slave1" "0: No detection,1: Detection" bitfld.long 0x0 9. "ECSCS1,ECC error detection for slave1" "0: No detection,1: Detection" newline bitfld.long 0x0 5. "DSTOCS1,OM_DQS timeout for slave1" "0: No detection,1: Detection" bitfld.long 0x0 4. "DSTOCS0,OM_DQS timeout for slave0" "0: No detection,1: Detection" newline bitfld.long 0x0 3. "PERTO,Periodic transaction timeout" "0: No detection,1: Detection" bitfld.long 0x0 1. "PATCMP,Pattern Completed" "0: No detection,1: Detection" newline bitfld.long 0x0 0. "CMDCMP,Command Completed" "0: No detection,1: Detection" wgroup.long 0x194++0x3 line.long 0x0 "INTC,OSPI Interrupt Clear Register" bitfld.long 0x0 31. "CASUCCS1C,Calibration success for slave1 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" bitfld.long 0x0 30. "CASUCCS0C,Calibration success for slave0 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" newline bitfld.long 0x0 29. "CAFAILCS1C,Calibration failed for slave1 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" bitfld.long 0x0 28. "CAFAILCS0C,Calibration failed for slave0 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" newline bitfld.long 0x0 21. "BUSERRCH1C,System bus error for ch1 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" bitfld.long 0x0 20. "BUSERRCH0C,System bus error for ch0 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" newline bitfld.long 0x0 13. "INTCS1C,Interrupt detection for slave1 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" bitfld.long 0x0 9. "ECSCS1C,ECC error detection for slave1 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" newline bitfld.long 0x0 5. "DSTOCS1C,OM_DQS timeout for slave1 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" bitfld.long 0x0 4. "DSTOCS0C,OM_DQS timeout for slave0 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" newline bitfld.long 0x0 3. "PERTOC,Periodic transaction timeout interrupt clear" "0: No change interrupt status,1: Clear interrupt status" bitfld.long 0x0 1. "PATCMPC,Pattern Completed interrupt clear" "0: No change interrupt status,1: Clear interrupt status" newline bitfld.long 0x0 0. "CMDCMPC,Command Completed interrupt clear" "0: No change interrupt status,1: Clear interrupt status" group.long 0x198++0x3 line.long 0x0 "INTE,OSPI Interrupt Enable Register" bitfld.long 0x0 31. "CASUCCS1E,Calibration success for slave1 interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 30. "CASUCCS0E,Calibration success for slave0 interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 29. "CAFAILCS1E,Calibration failed for slave1 interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 28. "CAFAILCS0E,Calibration failed for slave0 interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "BUSERRCH1E,System bus error for ch1 interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 20. "BUSERRCH0E,System bus error for ch0 interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 13. "INTCS1E,Interrupt detection for slave1 interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 9. "ECSCS1E,ECC error detection for slave1 interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "DSTOCS1E,OM_DQS timeout for slave1 interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 4. "DSTOCS0E,OM_DQS timeout for slave0 interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "PERTOE,Periodic transaction timeout interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 1. "PATCMPE,Pattern Completed interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "CMDCMPE,Command Completed interrupt enable" "0: Disabled,1: Enabled" tree.end tree "OSPI0_B_NS" base ad:0x50268000 group.long 0x0++0x7 line.long 0x0 "WRAPCFG,OSPI Wrapper Configuration Register" hexmask.long.byte 0x0 24.--28. 1. "DSSFTCS1,OM_DQS shift for slave1" hexmask.long.byte 0x0 8.--12. 1. "DSSFTCS0,OM_DQS shift for slave0" line.long 0x4 "COMCFG,OSPI Common Configuration Register" bitfld.long 0x4 17. "OENEGEX,Output Enable Negating extension" "0: No extend 1 cycle Output enable,1: Extend 1 cycle Output enable" bitfld.long 0x4 16. "OEASTEX,Output Enable Asserting extension" "0: No extend 1 cycle Output enable,1: Extend 1 cycle Output enable" newline bitfld.long 0x4 0.--1. "ARBMD,Channel arbitration mode" "0: Round-Robbin (ch0-ch1-ch0-ch1…),1: Always ch0 win,?,?" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x8)++0x3 line.long 0x0 "BMCFGCH$1,OSPI Bridge Map Configuration Register chn (n = 0. 1)" hexmask.long.byte 0x0 24.--31. 1. "CMBTIM,Combination timer" bitfld.long 0x0 16. "PREEN,Prefetch enable" "0: Disable prefetch function,1: Enable prefetch function" newline hexmask.long.byte 0x0 8.--15. 1. "MWRSIZE,Memory Write Size" bitfld.long 0x0 7. "MWRCOMB,Memory Write Combination mode" "0: Disable combination mode,1: Enable combination mode" newline bitfld.long 0x0 0. "WRMD,System bus Write Response mode" "0: Return response after storing to Internal Write..,1: Return response after issuing write transaction.." repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x10)++0x3 line.long 0x0 "CMCFG0CS$1,OSPI Command Map Configuration Register 0 CSn" hexmask.long.byte 0x0 24.--31. 1. "ADDRPCD,Address Replace Code" hexmask.long.byte 0x0 16.--23. 1. "ADDRPEN,Address Replace Enable" newline bitfld.long 0x0 5. "ARYAMD,Array address mode" "0: Normal address mode,1: Array address mode" bitfld.long 0x0 4. "WPBSTMD,Wrapping burst mode" "0: Separate xSPI transfer at the wrapping address..,1: Not separate xSPI transfer at the wrapping.." newline bitfld.long 0x0 2.--3. "ADDSIZE,Address size" "0: 1 byte (256-byte address space),1: 2 bytes (64 KB address space),?,?" bitfld.long 0x0 0.--1. "FFMT,Frame format" "0: Normal format: Command 1 byte Address ADDSIZE..,1: 8D-8D-8D profile 1.0 format: Command 2 bytes..,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x14)++0x3 line.long 0x0 "CMCFG1CS$1,OSPI Command Map Configuration Register 1 CSn" hexmask.long.byte 0x0 16.--20. 1. "RDLATE,Read latency cycle" hexmask.long.word 0x0 0.--15. 1. "RDCMD,Read command" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x18)++0x3 line.long 0x0 "CMCFG2CS$1,OSPI Command Map Configuration Register 2 CSn" hexmask.long.byte 0x0 16.--20. 1. "WRLATE,Write latency cycle" hexmask.long.word 0x0 0.--15. 1. "WRCMD,Write command" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "LIOCFGCS$1,OSPI Link I/O Configuration Register CSn" hexmask.long.byte 0x0 28.--31. 1. "DDRSMPEX,DDR sampling window extend" hexmask.long.byte 0x0 24.--27. 1. "SDRSMPSFT,SDR Sampling window shift" newline bitfld.long 0x0 23. "SDRSMPMD,SDR Sampling mode" "0: Samples data input at falling-edge,1: Samples data input at rising-edge" bitfld.long 0x0 22. "SDRDRV,SDR driving timing" "0: Drive at 1/2 cycle before CK rising-edge,1: Drive at CK rising-edge" newline bitfld.long 0x0 21. "CSNEGEX,CS negating extension" "0: No extension,1: Extend 1 cycle" bitfld.long 0x0 20. "CSASTEX,CS asserting extension" "0: No extension,1: Extend 1 cycle" newline hexmask.long.byte 0x0 16.--19. 1. "CSMIN,CS minimum idle term" bitfld.long 0x0 11. "WRMSKMD,Write mask mode" "0: Write mask disable,1: Write mask enable" newline bitfld.long 0x0 10. "LATEMD,Latency mode" "0,1" hexmask.long.word 0x0 0.--9. 1. "PRTMD,Protocol mode" repeat.end group.long 0x60++0x3 line.long 0x0 "BMCTL0,OSPI Bridge Map Control Register 0" bitfld.long 0x0 6.--7. "CH1CS1ACC,System bus ch1 to slave1 memory area access enable" "0: Read/Write disable,1: Read enable Write disable,?,?" bitfld.long 0x0 4.--5. "CH1CS0ACC,System bus ch1 to slave0 memory area access enable" "0: Read/Write disable,1: Read enable Write disable,?,?" newline bitfld.long 0x0 2.--3. "CH0CS1ACC,System bus ch0 to slave1 memory area access enable" "0: Read/Write disable,1: Read enable Write disable,?,?" bitfld.long 0x0 0.--1. "CH0CS0ACC,System bus ch0 to slave0 memory area access enable" "0: Read/Write disable,1: Read enable Write disable,?,?" wgroup.long 0x64++0x3 line.long 0x0 "BMCTL1,OSPI Bridge Map Control Register 1" bitfld.long 0x0 11. "PBUFCLRCH1,Prefetch Buffer clear for ch1" "0,1" bitfld.long 0x0 10. "PBUFCLRCH0,Prefetch Buffer clear for ch0" "0: No command,1: Clear request" newline bitfld.long 0x0 9. "MWRPUSHCH1,Memory Write Data Push for ch1" "0,1" bitfld.long 0x0 8. "MWRPUSHCH0,Memory Write Data Push for ch0" "0: No command,1: Push request" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x68)++0x3 line.long 0x0 "CMCTLCH$1,OSPI Command Map Control register chn (n = 0. 1)" bitfld.long 0x0 16. "XIPEN,XiP mode enable" "0: Disable XiP mode,1: Enable XiP mode" hexmask.long.byte 0x0 8.--15. 1. "XIPEXCODE,XiP mode exit code" newline hexmask.long.byte 0x0 0.--7. 1. "XIPENCODE,XiP mode enter code" repeat.end group.long 0x70++0xB line.long 0x0 "CDCTL0,OSPI Command Manual Control Register 0" hexmask.long.byte 0x0 24.--27. 1. "PERREP,Periodic transaction repeat" hexmask.long.byte 0x0 16.--20. 1. "PERITV,Periodic transaction interval" newline bitfld.long 0x0 4.--5. "TRNUM,Transaction number" "0: Issue 1 command (using command buffer 0),1: Issue 2 commands (using command buffer 0-1),?,?" bitfld.long 0x0 3. "CSSEL,Chip select" "0: CS0,1: CS1" newline bitfld.long 0x0 1. "PERMD,Periodic mode" "0: Direct manual-command mode,1: Periodic manual-command mode" bitfld.long 0x0 0. "TRREQ,Transaction request" "0: No transaction,1: Request transaction" line.long 0x4 "CDCTL1,OSPI Command Manual Control Register 1" hexmask.long 0x4 0.--31. 1. "PEREXP,Periodic transaction expected value" line.long 0x8 "CDCTL2,OSPI Command Manual Control Register 2" hexmask.long 0x8 0.--31. 1. "PERMSK,Periodic transaction masked value" repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x80)++0x3 line.long 0x0 "CDTBUF$1,OSPI Command Manual Type Buf %s" hexmask.long.word 0x0 16.--31. 1. "CMD,Command (1-2 bytes)" bitfld.long 0x0 15. "TRTYPE,Transaction Type" "0: Read transaction (Readout data from slave device),1: Not read transaction" newline hexmask.long.byte 0x0 9.--13. 1. "LATE,Latency cycle" hexmask.long.byte 0x0 5.--8. 1. "DATASIZE,Write/Read Data Size" newline bitfld.long 0x0 2.--4. "ADDSIZE,Address size" "0: Setting prohibited,1: 1 byte,?,?,?,?,?,?" bitfld.long 0x0 0.--1. "CMDSIZE,Command Size" "0: Setting prohibited,1: 1 byte,?,?" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x84)++0x3 line.long 0x0 "CDABUF$1,OSPI Command Manual Address Buf %s" hexmask.long 0x0 0.--31. 1. "ADD,Address" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x88)++0x3 line.long 0x0 "CDD0BUF$1,OSPI Command Manual Data 0 Buf %s" hexmask.long 0x0 0.--31. 1. "DATA,Write/Read Data" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x8C)++0x3 line.long 0x0 "CDD1BUF$1,OSPI Command Manual Data 1 Buf %s" hexmask.long 0x0 0.--31. 1. "DATA,Write/Read Data" repeat.end group.long 0x100++0xB line.long 0x0 "LPCTL0,OSPI Link Pattern Control Register 0" bitfld.long 0x0 31. "XD2VAL,XiP Disable pattern 2nd phase value" "0: Low drive,1: High drive" hexmask.long.byte 0x0 24.--28. 1. "XD2LEN,XiP Disable pattern 2nd phase length" newline bitfld.long 0x0 23. "XD1VAL,XiP Disable pattern 1st phase value" "0: Low drive,1: High drive" hexmask.long.byte 0x0 16.--20. 1. "XD1LEN,XiP Disable pattern 1st phase length" newline bitfld.long 0x0 4.--5. "XDPIN,XiP Disable pattern pin" "0: 1 pin,1: 2 pins,?,?" bitfld.long 0x0 3. "CSSEL,Chip select" "0: slave0 (CS0),1: slave1 (CS1)" newline bitfld.long 0x0 0. "PATREQ,Pattern request" "0: No request XiP Disable pattern,1: Request XiP Disable pattern" line.long 0x4 "LPCTL1,OSPI Link Pattern Control Register 1" bitfld.long 0x4 12.--14. "RSTSU,Reset pattern data output setup time" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "RSTWID,Reset pattern width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--5. "RSTREP,Reset pattern repeat" "0: 4 times (Specified on Reset Signaling Protocol),1: 5 times,?,?" bitfld.long 0x4 3. "CSSEL,Chip select" "0: slave0 (CS0),1: slave1 (CS1)" newline bitfld.long 0x4 0.--1. "PATREQ,Pattern request" "0: No request,1: Request Reset pattern,?,?" line.long 0x8 "LIOCTL,OSPI Link I/O Control Register" bitfld.long 0x8 16. "RSTCS0,Reset drive" "0: Drive Low level,1: Drive High level" bitfld.long 0x8 1. "WPCS1,WP drive for slave1" "0: Drive Low level,1: Drive High level" repeat 2. (increment 0x0 0x1)(increment 0x0 0x20) group.long ($2+0x130)++0x3 line.long 0x0 "CCCTL0CS$1,OSPI Command Calibration Control Register 0 CSn" hexmask.long.byte 0x0 24.--28. 1. "CASFTEND,Calibration OM_DQS shift end value" hexmask.long.byte 0x0 16.--20. 1. "CASFTSTA,Calibration OM_DQS shift start value" newline hexmask.long.byte 0x0 8.--12. 1. "CAITV,Calibration interval" bitfld.long 0x0 1. "CANOWR,Calibration no write mode" "0: Calibration sequence with write command,1: Calibration sequence without write command" newline bitfld.long 0x0 0. "CAEN,Automatic Calibration Enable" "0: Disable automatic calibration,1: Enable automatic calibration" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x20) group.long ($2+0x134)++0x3 line.long 0x0 "CCCTL1CS$1,OSPI Command Calibration Control Register 1 CSn" hexmask.long.byte 0x0 24.--28. 1. "CARDLATE,Read Latency cycle" hexmask.long.byte 0x0 16.--20. 1. "CAWRLATE,Write Latency cycle" newline hexmask.long.byte 0x0 5.--8. 1. "CADATASIZE,Write/Read Data Size" bitfld.long 0x0 2.--4. "CAADDSIZE,Address size" "0: Setting prohibited,1: 1 byte,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "CACMDSIZE,Command Size" "0: 0 bytes (No command phase),1: 1 byte,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x20) group.long ($2+0x138)++0x3 line.long 0x0 "CCCTL2CS$1,OSPI Command Calibration Control Register 2 CSn" hexmask.long.word 0x0 16.--31. 1. "CARDCMD,Calibration pattern read command" hexmask.long.word 0x0 0.--15. 1. "CAWRCMD,Calibration pattern write command" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x20) group.long ($2+0x13C)++0x3 line.long 0x0 "CCCTL3CS$1,OSPI Command Calibration Control Register 3 CSn" hexmask.long 0x0 0.--31. 1. "CAADD,Calibration pattern address" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x20) group.long ($2+0x140)++0x3 line.long 0x0 "CCCTL4CS$1,OSPI Command Calibration Control Register 4 CSn" hexmask.long 0x0 0.--31. 1. "CADATA,Calibration pattern data" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x20) group.long ($2+0x144)++0x3 line.long 0x0 "CCCTL5CS$1,OSPI Command Calibration Control Register 5 CSn" hexmask.long 0x0 0.--31. 1. "CADATA,Calibration pattern data" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x20) group.long ($2+0x148)++0x3 line.long 0x0 "CCCTL6CS$1,OSPI Command Calibration Control Register 6 CSn" hexmask.long 0x0 0.--31. 1. "CADATA,Calibration pattern data" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x20) group.long ($2+0x14C)++0x3 line.long 0x0 "CCCTL7CS$1,OSPI Command Calibration Control Register 7 CSn" hexmask.long 0x0 0.--31. 1. "CADATA,Calibration pattern data" repeat.end rgroup.long 0x184++0x3 line.long 0x0 "COMSTT,OSPI Common Status Register" bitfld.long 0x0 22. "RSTOCS1,RSTO monitor for slave1" "0: Low level,1: High level" bitfld.long 0x0 21. "INTCS1,INT monitor for slave1" "0: Low level,1: High level" newline bitfld.long 0x0 20. "ECSCS1,ECS monitor for slave1" "0: Low level,1: High level" bitfld.long 0x0 7. "WRBUFNECH1,Write Buffer Not Empty for ch1" "0,1" newline bitfld.long 0x0 6. "WRBUFNECH0,Write Buffer Not Empty for ch0" "0: Empty,1: Not empty" bitfld.long 0x0 5. "PBUFNECH1,Prefetch Buffer Not Empty for ch1" "0,1" newline bitfld.long 0x0 4. "PBUFNECH0,Prefetch Buffer Not Empty for ch0" "0: Empty,1: Not empty" bitfld.long 0x0 1. "MEMACCCH1,Memory access ongoing from ch1" "0,1" newline bitfld.long 0x0 0. "MEMACCCH0,Memory access ongoing from ch0" "0: System bus bridge ch0 is not accessing to memory.,1: System bus bridge ch0 is accessing to memory." repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x188)++0x3 line.long 0x0 "CASTTCS$1,OSPI Calibration Status Register CSn" hexmask.long 0x0 0.--31. 1. "CASUC,Calibration Success" repeat.end rgroup.long 0x190++0x3 line.long 0x0 "INTS,OSPI Interrupt Status Register" bitfld.long 0x0 31. "CASUCCS1,Calibration success for slave1" "0: No detection,1: Detection" bitfld.long 0x0 30. "CASUCCS0,Calibration success for slave0" "0: No detection,1: Detection" newline bitfld.long 0x0 29. "CAFAILCS1,Calibration failed for slave1" "0: No detection,1: Detection" bitfld.long 0x0 28. "CAFAILCS0,Calibration failed for slave0" "0: No detection,1: Detection" newline bitfld.long 0x0 21. "BUSERRCH1,System bus error for ch1" "0,1" bitfld.long 0x0 20. "BUSERRCH0,System bus error for ch0" "0,1" newline bitfld.long 0x0 13. "INTCS1,Interrupt detection for slave1" "0: No detection,1: Detection" bitfld.long 0x0 9. "ECSCS1,ECC error detection for slave1" "0: No detection,1: Detection" newline bitfld.long 0x0 5. "DSTOCS1,OM_DQS timeout for slave1" "0: No detection,1: Detection" bitfld.long 0x0 4. "DSTOCS0,OM_DQS timeout for slave0" "0: No detection,1: Detection" newline bitfld.long 0x0 3. "PERTO,Periodic transaction timeout" "0: No detection,1: Detection" bitfld.long 0x0 1. "PATCMP,Pattern Completed" "0: No detection,1: Detection" newline bitfld.long 0x0 0. "CMDCMP,Command Completed" "0: No detection,1: Detection" wgroup.long 0x194++0x3 line.long 0x0 "INTC,OSPI Interrupt Clear Register" bitfld.long 0x0 31. "CASUCCS1C,Calibration success for slave1 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" bitfld.long 0x0 30. "CASUCCS0C,Calibration success for slave0 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" newline bitfld.long 0x0 29. "CAFAILCS1C,Calibration failed for slave1 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" bitfld.long 0x0 28. "CAFAILCS0C,Calibration failed for slave0 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" newline bitfld.long 0x0 21. "BUSERRCH1C,System bus error for ch1 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" bitfld.long 0x0 20. "BUSERRCH0C,System bus error for ch0 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" newline bitfld.long 0x0 13. "INTCS1C,Interrupt detection for slave1 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" bitfld.long 0x0 9. "ECSCS1C,ECC error detection for slave1 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" newline bitfld.long 0x0 5. "DSTOCS1C,OM_DQS timeout for slave1 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" bitfld.long 0x0 4. "DSTOCS0C,OM_DQS timeout for slave0 interrupt clear" "0: No change interrupt status,1: Clear interrupt status" newline bitfld.long 0x0 3. "PERTOC,Periodic transaction timeout interrupt clear" "0: No change interrupt status,1: Clear interrupt status" bitfld.long 0x0 1. "PATCMPC,Pattern Completed interrupt clear" "0: No change interrupt status,1: Clear interrupt status" newline bitfld.long 0x0 0. "CMDCMPC,Command Completed interrupt clear" "0: No change interrupt status,1: Clear interrupt status" group.long 0x198++0x3 line.long 0x0 "INTE,OSPI Interrupt Enable Register" bitfld.long 0x0 31. "CASUCCS1E,Calibration success for slave1 interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 30. "CASUCCS0E,Calibration success for slave0 interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 29. "CAFAILCS1E,Calibration failed for slave1 interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 28. "CAFAILCS0E,Calibration failed for slave0 interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "BUSERRCH1E,System bus error for ch1 interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 20. "BUSERRCH0E,System bus error for ch0 interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 13. "INTCS1E,Interrupt detection for slave1 interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 9. "ECSCS1E,ECC error detection for slave1 interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "DSTOCS1E,OM_DQS timeout for slave1 interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 4. "DSTOCS0E,OM_DQS timeout for slave0 interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "PERTOE,Periodic transaction timeout interrupt enable" "0: Disabled,1: Enabled" bitfld.long 0x0 1. "PATCMPE,Pattern Completed interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "CMDCMPE,Command Completed interrupt enable" "0: Disabled,1: Enabled" tree.end tree.end tree "POEG (Port Output Enable for GPT)" base ad:0x0 tree "POEG" base ad:0x40212000 group.long 0x0++0x3 line.long 0x0 "POEGGA,POEG Group A Setting Register" bitfld.long 0x0 30.--31. "NFCS,Noise Filter Clock Select" "0: Sample GTETRGn pin input level three times every..,1: Sample GTETRGn pin input level three times every..,?,?" bitfld.long 0x0 29. "NFEN,Noise Filter Enable" "0: Disable noise filtering,1: Enable noise filtering" newline bitfld.long 0x0 28. "INV,GTETRGn Input Reverse" "0: Input GTETRGn as-is,1: Input GTETRGn in reverse" rbitfld.long 0x0 16. "ST,GTETRGn Input Status Flag" "0: GTETRGn input after filtering was 0,1: GTETRGn input after filtering was 1" newline bitfld.long 0x0 9. "CDRE1" "0: Disable output-disable request from ACMPHS1,1: Enable output-disable request from ACMPHS1" bitfld.long 0x0 8. "CDRE0" "0: Disable output-disable request from ACMPHS0,1: Enable output-disable request from ACMPHS0" newline bitfld.long 0x0 6. "OSTPE,Oscillation Stop Detection Enable" "0: Disable output-disable requests from oscillation..,1: Enable output-disable requests from oscillation.." bitfld.long 0x0 5. "IOCE,Enable for GPT Output-Disable Request" "0: Disable output-disable requests from GPT,1: Enable output-disable requests from GPT" newline bitfld.long 0x0 4. "PIDE,Port Input Detection Enable" "0: Disable output-disable requests from the GTETRGn..,1: Enable output-disable requests from the GTETRGn.." bitfld.long 0x0 3. "SSF,Software Stop Flag" "0: No output-disable request from software occurred,1: Output-disable request from software occurred" newline bitfld.long 0x0 2. "OSTPF,Oscillation Stop Detection Flag" "0: No output-disable request from oscillation stop..,1: Output-disable request from oscillation stop.." bitfld.long 0x0 1. "IOCF,Detection Flag for GPT or ACMPHS Output-Disable Request" "0: No output-disable request from GPT or comparator..,1: Output-disable request from GPT or comparator.." newline bitfld.long 0x0 0. "PIDF,Port Input Detection Flag" "0: No output-disable request from the GTETRGn pin..,1: Output-disable request from the GTETRGn pin.." group.long 0x100++0x3 line.long 0x0 "POEGGB,POEG Group B Setting Register" bitfld.long 0x0 30.--31. "NFCS,Noise Filter Clock Select" "0: Sample GTETRGn pin input level three times every..,1: Sample GTETRGn pin input level three times every..,?,?" bitfld.long 0x0 29. "NFEN,Noise Filter Enable" "0: Disable noise filtering,1: Enable noise filtering" newline bitfld.long 0x0 28. "INV,GTETRGn Input Reverse" "0: Input GTETRGn as-is,1: Input GTETRGn in reverse" rbitfld.long 0x0 16. "ST,GTETRGn Input Status Flag" "0: GTETRGn input after filtering was 0,1: GTETRGn input after filtering was 1" newline bitfld.long 0x0 9. "CDRE1" "0: Disable output-disable request from ACMPHS1,1: Enable output-disable request from ACMPHS1" bitfld.long 0x0 8. "CDRE0" "0: Disable output-disable request from ACMPHS0,1: Enable output-disable request from ACMPHS0" newline bitfld.long 0x0 6. "OSTPE,Oscillation Stop Detection Enable" "0: Disable output-disable requests from oscillation..,1: Enable output-disable requests from oscillation.." bitfld.long 0x0 5. "IOCE,Enable for GPT Output-Disable Request" "0: Disable output-disable requests from GPT,1: Enable output-disable requests from GPT" newline bitfld.long 0x0 4. "PIDE,Port Input Detection Enable" "0: Disable output-disable requests from the GTETRGn..,1: Enable output-disable requests from the GTETRGn.." bitfld.long 0x0 3. "SSF,Software Stop Flag" "0: No output-disable request from software occurred,1: Output-disable request from software occurred" newline bitfld.long 0x0 2. "OSTPF,Oscillation Stop Detection Flag" "0: No output-disable request from oscillation stop..,1: Output-disable request from oscillation stop.." bitfld.long 0x0 1. "IOCF,Detection Flag for GPT or ACMPHS Output-Disable Request" "0: No output-disable request from GPT or comparator..,1: Output-disable request from GPT or comparator.." newline bitfld.long 0x0 0. "PIDF,Port Input Detection Flag" "0: No output-disable request from the GTETRGn pin..,1: Output-disable request from the GTETRGn pin.." group.long 0x200++0x3 line.long 0x0 "POEGGC,POEG Group C Setting Register" bitfld.long 0x0 30.--31. "NFCS,Noise Filter Clock Select" "0: Sample GTETRGn pin input level three times every..,1: Sample GTETRGn pin input level three times every..,?,?" bitfld.long 0x0 29. "NFEN,Noise Filter Enable" "0: Disable noise filtering,1: Enable noise filtering" newline bitfld.long 0x0 28. "INV,GTETRGn Input Reverse" "0: Input GTETRGn as-is,1: Input GTETRGn in reverse" rbitfld.long 0x0 16. "ST,GTETRGn Input Status Flag" "0: GTETRGn input after filtering was 0,1: GTETRGn input after filtering was 1" newline bitfld.long 0x0 9. "CDRE1" "0: Disable output-disable request from ACMPHS1,1: Enable output-disable request from ACMPHS1" bitfld.long 0x0 8. "CDRE0" "0: Disable output-disable request from ACMPHS0,1: Enable output-disable request from ACMPHS0" newline bitfld.long 0x0 6. "OSTPE,Oscillation Stop Detection Enable" "0: Disable output-disable requests from oscillation..,1: Enable output-disable requests from oscillation.." bitfld.long 0x0 5. "IOCE,Enable for GPT Output-Disable Request" "0: Disable output-disable requests from GPT,1: Enable output-disable requests from GPT" newline bitfld.long 0x0 4. "PIDE,Port Input Detection Enable" "0: Disable output-disable requests from the GTETRGn..,1: Enable output-disable requests from the GTETRGn.." bitfld.long 0x0 3. "SSF,Software Stop Flag" "0: No output-disable request from software occurred,1: Output-disable request from software occurred" newline bitfld.long 0x0 2. "OSTPF,Oscillation Stop Detection Flag" "0: No output-disable request from oscillation stop..,1: Output-disable request from oscillation stop.." bitfld.long 0x0 1. "IOCF,Detection Flag for GPT or ACMPHS Output-Disable Request" "0: No output-disable request from GPT or comparator..,1: Output-disable request from GPT or comparator.." newline bitfld.long 0x0 0. "PIDF,Port Input Detection Flag" "0: No output-disable request from the GTETRGn pin..,1: Output-disable request from the GTETRGn pin.." group.long 0x300++0x3 line.long 0x0 "POEGGD,POEG Group D Setting Register" bitfld.long 0x0 30.--31. "NFCS,Noise Filter Clock Select" "0: Sample GTETRGn pin input level three times every..,1: Sample GTETRGn pin input level three times every..,?,?" bitfld.long 0x0 29. "NFEN,Noise Filter Enable" "0: Disable noise filtering,1: Enable noise filtering" newline bitfld.long 0x0 28. "INV,GTETRGn Input Reverse" "0: Input GTETRGn as-is,1: Input GTETRGn in reverse" rbitfld.long 0x0 16. "ST,GTETRGn Input Status Flag" "0: GTETRGn input after filtering was 0,1: GTETRGn input after filtering was 1" newline bitfld.long 0x0 9. "CDRE1" "0: Disable output-disable request from ACMPHS1,1: Enable output-disable request from ACMPHS1" bitfld.long 0x0 8. "CDRE0" "0: Disable output-disable request from ACMPHS0,1: Enable output-disable request from ACMPHS0" newline bitfld.long 0x0 6. "OSTPE,Oscillation Stop Detection Enable" "0: Disable output-disable requests from oscillation..,1: Enable output-disable requests from oscillation.." bitfld.long 0x0 5. "IOCE,Enable for GPT Output-Disable Request" "0: Disable output-disable requests from GPT,1: Enable output-disable requests from GPT" newline bitfld.long 0x0 4. "PIDE,Port Input Detection Enable" "0: Disable output-disable requests from the GTETRGn..,1: Enable output-disable requests from the GTETRGn.." bitfld.long 0x0 3. "SSF,Software Stop Flag" "0: No output-disable request from software occurred,1: Output-disable request from software occurred" newline bitfld.long 0x0 2. "OSTPF,Oscillation Stop Detection Flag" "0: No output-disable request from oscillation stop..,1: Output-disable request from oscillation stop.." bitfld.long 0x0 1. "IOCF,Detection Flag for GPT or ACMPHS Output-Disable Request" "0: No output-disable request from GPT or comparator..,1: Output-disable request from GPT or comparator.." newline bitfld.long 0x0 0. "PIDF,Port Input Detection Flag" "0: No output-disable request from the GTETRGn pin..,1: Output-disable request from the GTETRGn pin.." tree.end tree "POEG_NS" base ad:0x50212000 group.long 0x0++0x3 line.long 0x0 "POEGGA,POEG Group A Setting Register" bitfld.long 0x0 30.--31. "NFCS,Noise Filter Clock Select" "0: Sample GTETRGn pin input level three times every..,1: Sample GTETRGn pin input level three times every..,?,?" bitfld.long 0x0 29. "NFEN,Noise Filter Enable" "0: Disable noise filtering,1: Enable noise filtering" newline bitfld.long 0x0 28. "INV,GTETRGn Input Reverse" "0: Input GTETRGn as-is,1: Input GTETRGn in reverse" rbitfld.long 0x0 16. "ST,GTETRGn Input Status Flag" "0: GTETRGn input after filtering was 0,1: GTETRGn input after filtering was 1" newline bitfld.long 0x0 9. "CDRE1" "0: Disable output-disable request from ACMPHS1,1: Enable output-disable request from ACMPHS1" bitfld.long 0x0 8. "CDRE0" "0: Disable output-disable request from ACMPHS0,1: Enable output-disable request from ACMPHS0" newline bitfld.long 0x0 6. "OSTPE,Oscillation Stop Detection Enable" "0: Disable output-disable requests from oscillation..,1: Enable output-disable requests from oscillation.." bitfld.long 0x0 5. "IOCE,Enable for GPT Output-Disable Request" "0: Disable output-disable requests from GPT,1: Enable output-disable requests from GPT" newline bitfld.long 0x0 4. "PIDE,Port Input Detection Enable" "0: Disable output-disable requests from the GTETRGn..,1: Enable output-disable requests from the GTETRGn.." bitfld.long 0x0 3. "SSF,Software Stop Flag" "0: No output-disable request from software occurred,1: Output-disable request from software occurred" newline bitfld.long 0x0 2. "OSTPF,Oscillation Stop Detection Flag" "0: No output-disable request from oscillation stop..,1: Output-disable request from oscillation stop.." bitfld.long 0x0 1. "IOCF,Detection Flag for GPT or ACMPHS Output-Disable Request" "0: No output-disable request from GPT or comparator..,1: Output-disable request from GPT or comparator.." newline bitfld.long 0x0 0. "PIDF,Port Input Detection Flag" "0: No output-disable request from the GTETRGn pin..,1: Output-disable request from the GTETRGn pin.." group.long 0x100++0x3 line.long 0x0 "POEGGB,POEG Group B Setting Register" bitfld.long 0x0 30.--31. "NFCS,Noise Filter Clock Select" "0: Sample GTETRGn pin input level three times every..,1: Sample GTETRGn pin input level three times every..,?,?" bitfld.long 0x0 29. "NFEN,Noise Filter Enable" "0: Disable noise filtering,1: Enable noise filtering" newline bitfld.long 0x0 28. "INV,GTETRGn Input Reverse" "0: Input GTETRGn as-is,1: Input GTETRGn in reverse" rbitfld.long 0x0 16. "ST,GTETRGn Input Status Flag" "0: GTETRGn input after filtering was 0,1: GTETRGn input after filtering was 1" newline bitfld.long 0x0 9. "CDRE1" "0: Disable output-disable request from ACMPHS1,1: Enable output-disable request from ACMPHS1" bitfld.long 0x0 8. "CDRE0" "0: Disable output-disable request from ACMPHS0,1: Enable output-disable request from ACMPHS0" newline bitfld.long 0x0 6. "OSTPE,Oscillation Stop Detection Enable" "0: Disable output-disable requests from oscillation..,1: Enable output-disable requests from oscillation.." bitfld.long 0x0 5. "IOCE,Enable for GPT Output-Disable Request" "0: Disable output-disable requests from GPT,1: Enable output-disable requests from GPT" newline bitfld.long 0x0 4. "PIDE,Port Input Detection Enable" "0: Disable output-disable requests from the GTETRGn..,1: Enable output-disable requests from the GTETRGn.." bitfld.long 0x0 3. "SSF,Software Stop Flag" "0: No output-disable request from software occurred,1: Output-disable request from software occurred" newline bitfld.long 0x0 2. "OSTPF,Oscillation Stop Detection Flag" "0: No output-disable request from oscillation stop..,1: Output-disable request from oscillation stop.." bitfld.long 0x0 1. "IOCF,Detection Flag for GPT or ACMPHS Output-Disable Request" "0: No output-disable request from GPT or comparator..,1: Output-disable request from GPT or comparator.." newline bitfld.long 0x0 0. "PIDF,Port Input Detection Flag" "0: No output-disable request from the GTETRGn pin..,1: Output-disable request from the GTETRGn pin.." group.long 0x200++0x3 line.long 0x0 "POEGGC,POEG Group C Setting Register" bitfld.long 0x0 30.--31. "NFCS,Noise Filter Clock Select" "0: Sample GTETRGn pin input level three times every..,1: Sample GTETRGn pin input level three times every..,?,?" bitfld.long 0x0 29. "NFEN,Noise Filter Enable" "0: Disable noise filtering,1: Enable noise filtering" newline bitfld.long 0x0 28. "INV,GTETRGn Input Reverse" "0: Input GTETRGn as-is,1: Input GTETRGn in reverse" rbitfld.long 0x0 16. "ST,GTETRGn Input Status Flag" "0: GTETRGn input after filtering was 0,1: GTETRGn input after filtering was 1" newline bitfld.long 0x0 9. "CDRE1" "0: Disable output-disable request from ACMPHS1,1: Enable output-disable request from ACMPHS1" bitfld.long 0x0 8. "CDRE0" "0: Disable output-disable request from ACMPHS0,1: Enable output-disable request from ACMPHS0" newline bitfld.long 0x0 6. "OSTPE,Oscillation Stop Detection Enable" "0: Disable output-disable requests from oscillation..,1: Enable output-disable requests from oscillation.." bitfld.long 0x0 5. "IOCE,Enable for GPT Output-Disable Request" "0: Disable output-disable requests from GPT,1: Enable output-disable requests from GPT" newline bitfld.long 0x0 4. "PIDE,Port Input Detection Enable" "0: Disable output-disable requests from the GTETRGn..,1: Enable output-disable requests from the GTETRGn.." bitfld.long 0x0 3. "SSF,Software Stop Flag" "0: No output-disable request from software occurred,1: Output-disable request from software occurred" newline bitfld.long 0x0 2. "OSTPF,Oscillation Stop Detection Flag" "0: No output-disable request from oscillation stop..,1: Output-disable request from oscillation stop.." bitfld.long 0x0 1. "IOCF,Detection Flag for GPT or ACMPHS Output-Disable Request" "0: No output-disable request from GPT or comparator..,1: Output-disable request from GPT or comparator.." newline bitfld.long 0x0 0. "PIDF,Port Input Detection Flag" "0: No output-disable request from the GTETRGn pin..,1: Output-disable request from the GTETRGn pin.." group.long 0x300++0x3 line.long 0x0 "POEGGD,POEG Group D Setting Register" bitfld.long 0x0 30.--31. "NFCS,Noise Filter Clock Select" "0: Sample GTETRGn pin input level three times every..,1: Sample GTETRGn pin input level three times every..,?,?" bitfld.long 0x0 29. "NFEN,Noise Filter Enable" "0: Disable noise filtering,1: Enable noise filtering" newline bitfld.long 0x0 28. "INV,GTETRGn Input Reverse" "0: Input GTETRGn as-is,1: Input GTETRGn in reverse" rbitfld.long 0x0 16. "ST,GTETRGn Input Status Flag" "0: GTETRGn input after filtering was 0,1: GTETRGn input after filtering was 1" newline bitfld.long 0x0 9. "CDRE1" "0: Disable output-disable request from ACMPHS1,1: Enable output-disable request from ACMPHS1" bitfld.long 0x0 8. "CDRE0" "0: Disable output-disable request from ACMPHS0,1: Enable output-disable request from ACMPHS0" newline bitfld.long 0x0 6. "OSTPE,Oscillation Stop Detection Enable" "0: Disable output-disable requests from oscillation..,1: Enable output-disable requests from oscillation.." bitfld.long 0x0 5. "IOCE,Enable for GPT Output-Disable Request" "0: Disable output-disable requests from GPT,1: Enable output-disable requests from GPT" newline bitfld.long 0x0 4. "PIDE,Port Input Detection Enable" "0: Disable output-disable requests from the GTETRGn..,1: Enable output-disable requests from the GTETRGn.." bitfld.long 0x0 3. "SSF,Software Stop Flag" "0: No output-disable request from software occurred,1: Output-disable request from software occurred" newline bitfld.long 0x0 2. "OSTPF,Oscillation Stop Detection Flag" "0: No output-disable request from oscillation stop..,1: Output-disable request from oscillation stop.." bitfld.long 0x0 1. "IOCF,Detection Flag for GPT or ACMPHS Output-Disable Request" "0: No output-disable request from GPT or comparator..,1: Output-disable request from GPT or comparator.." newline bitfld.long 0x0 0. "PIDF,Port Input Detection Flag" "0: No output-disable request from the GTETRGn pin..,1: Output-disable request from the GTETRGn pin.." tree.end tree.end tree "PSCU (Peripheral Security Control Unit)" base ad:0x0 tree "PSCU" base ad:0x40204000 group.long 0x4++0x13 line.long 0x0 "PSARB,Peripheral Security Attribution Register B" bitfld.long 0x0 31. "PSARB31,Serial Communication Interface 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 30. "PSARB30,Serial Communication Interface 1 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 29. "PSARB29,Serial Communication Interface 2 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 28. "PSARB28,Serial Communication Interface 3 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 27. "PSARB27,Serial Communication Interface 4 Security Attribution" "0: Secure,1: Non-secure" newline bitfld.long 0x0 22. "PSARB22,Serial Communication Interface 9 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 19. "PSARB19,Serial Peripheral Interface 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 18. "PSARB18,Serial Peripheral Interface 1 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 16. "PSARB16,Octa Memory Controller Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 11. "PSARB11,Universal Serial Bus 2.0 FS Interface 0 Security Attribution" "0: Secure,1: Non-secure" newline bitfld.long 0x0 9. "PSARB9,I2C Bus Interface 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 8. "PSARB8,I2C Bus Interface 1 Security Attribution" "0: Secure,1: Non-secure" line.long 0x4 "PSARC,Peripheral Security Attribution Register C" bitfld.long 0x4 31. "PSARC31,RSIP-E51A Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x4 27. "PSARC27,Controller Area Network with Flexible Data-Rate 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x4 26. "PSARC26,Controller Area Network with Flexible Data-Rate 1 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x4 15. "PSARC15,Graphic (GLCDC DRW) Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x4 13. "PSARC13,Data Operation Circuit Security Attribution" "0: Secure,1: Non-secure" newline bitfld.long 0x4 8. "PSARC8,Serial Sound Interface Enhanced (channel 0) Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x4 7. "PSARC7,Serial Sound Interface Enhanced (channel 1) Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x4 1. "PSARC1,Cyclic Redundancy Check Calculator Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x4 0. "PSARC0,Clock Frequency Accuracy Measurement Circuit Security Attribution register specifies the security attribution for each module and the corresponding bit in Module Stop Control Register." "0: Secure,1: Non-secure" line.long 0x8 "PSARD,Peripheral Security Attribution Register D" bitfld.long 0x8 28. "PSARD28,High Speed Analog Comparator 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 27. "PSARD27,High Speed Analog Comparator 1 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 22. "PSARD22,Temperature Sensor Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 20. "PSARD20,12-Bit D/A Converter Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 16. "PSARD16,12-Bit A/D 0 Converter Security Attribution" "0: Secure,1: Non-secure" newline bitfld.long 0x8 15. "PSARD15,12-Bit A/D 1 Converter Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 14. "PSARD14,Port Output Enable for GPT Group 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 13. "PSARD13,Port Output Enable for GPT Group 1 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 12. "PSARD12,Port Output Enable for GPT Group 2 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 11. "PSARD11,Port Output Enable for GPT Group 3 Security Attribution" "0: Secure,1: Non-secure" newline bitfld.long 0x8 5. "PSARD5,Asynchronous General Purpose Timer 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 4. "PSARD4,Asynchronous General Purpose Timer 1 Security Attribution" "0: Secure,1: Non-secure" line.long 0xC "PSARE,Peripheral Security Attribution Register E" bitfld.long 0xC 31. "PSARE31,General PWM Timer Channel 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 30. "PSARE30,General PWM Timer Channel 1 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 29. "PSARE29,General PWM Timer Channel 2 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 28. "PSARE28,General PWM Timer Channel 3 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 27. "PSARE27,General PWM Timer Channel 4 Security Attribution" "0: Secure,1: Non-secure" newline bitfld.long 0xC 26. "PSARE26,General PWM Timer Channel 5 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 21. "PSARE21,General PWM Timer Channel 10 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 20. "PSARE20,General PWM Timer Channel 11 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 19. "PSARE19,General PWM Timer Channel 12 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 18. "PSARE18,General PWM Timer Channel 13 Security Attribution" "0: Secure,1: Non-secure" newline bitfld.long 0xC 9. "PSARE9,ULPT0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 8. "PSARE8,ULPT1 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 3. "PSARE3,Real Time Clock Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 2. "PSARE2,IWDT Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 1. "PSARE1,WDT Security Attribution" "0: Secure,1: Non-secure" line.long 0x10 "MSSAR,Module Stop Security Attribution Register" bitfld.long 0x10 31. "MSSAR31,ELC Clock Stop Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x10 22. "MSSAR22,DMAC/DTC Clock Stop Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x10 15. "MSSAR15,Standby RAM Clock Stop Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x10 1. "MSSAR1,SRAM1 Clock Stop Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x10 0. "MSSAR0,SRAM0 Clock Stop Security Attribution" "0: Secure,1: Non-secure" group.long 0x1C++0x13 line.long 0x0 "PPARB,Peripheral Privilege Attribution Register B" bitfld.long 0x0 31. "PPARB31,Serial Communication Interface 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 30. "PPARB30,Serial Communication Interface 1 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 29. "PPARB29,Serial Communication Interface 2 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 28. "PPARB28,Serial Communication Interface 3 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 27. "PPARB27,Serial Communication Interface 4 Privilege Attribution" "0: Privileged,1: UnPrivileged" newline bitfld.long 0x0 22. "PPARB22,Serial Communication Interface 9 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 19. "PPARB19,Serial Peripheral Interface 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 18. "PPARB18,Serial Peripheral Interface 1 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 16. "PPARB16,Octa Memory Controller Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 11. "PPARB11,Universal Serial Bus 2.0 FS Interface 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" newline bitfld.long 0x0 9. "PPARB9,I2C Bus Interface 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 8. "PPARB8,I2C Bus Interface 1 Privilege Attribution" "0: Privileged,1: UnPrivileged" line.long 0x4 "PPARC,Peripheral Privilege Attribution Register C" bitfld.long 0x4 31. "PPARC31,RSIP-E51A Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x4 27. "PPARC27,Controller Area Network with Flexible Data-Rate 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x4 26. "PPARC26,Controller Area Network with Flexible Data-Rate 1 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x4 15. "PPARC15,Graphic (GLCDC DRW) Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x4 13. "PPARC13,Data Operation Circuit Privilege Attribution" "0: Privileged,1: UnPrivileged" newline bitfld.long 0x4 8. "PPARC8,Serial Sound Interface Enhanced (Channel 0) Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x4 7. "PPARC7,Serial Sound Interface Enhanced (Channel 1) Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x4 1. "PPARC1,Cyclic Redundancy Check Calculator Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x4 0. "PPARC0,Clock Frequency Accuracy Measurement Circuit Privilege Attribution" "0: Privileged,1: UnPrivileged" line.long 0x8 "PPARD,Peripheral Privilege Attribution Register D" bitfld.long 0x8 28. "PPARD28,High speed analog Comparator 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 27. "PPARD27,High speed analog Comparator 1 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 22. "PPARD22,Temperature Sensor Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 20. "PPARD20,12-Bit D/A Converter Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 16. "PPARD16,12-Bit A/D 0 Converter Privilege Attribution" "0: Privileged,1: UnPrivileged" newline bitfld.long 0x8 15. "PPARD15,12-Bit A/D 1 Converter Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 14. "PPARD14,Port Output Enable for GPT Group 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 13. "PPARD13,Port Output Enable for GPT Group 1 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 12. "PPARD12,Port Output Enable for GPT Group 2 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 11. "PPARD11,Port Output Enable for GPT Group 3 Privilege Attribution" "0: Privileged,1: UnPrivileged" newline bitfld.long 0x8 5. "PPARD5,Asynchronous General Purpose Timer 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 4. "PPARD4,Asynchronous General Purpose Timer 1 Privilege Attribution" "0: Privileged,1: UnPrivileged" line.long 0xC "PPARE,Peripheral Privilege Attribution Register E" bitfld.long 0xC 31. "PPARE31,General PWM Timer Channel 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 30. "PPARE30,General PWM Timer Channel 1 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 29. "PPARE29,General PWM Timer Channel 2 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 28. "PPARE28,General PWM Timer Channel 3 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 27. "PPARE27,General PWM Timer Channel 4 Privilege Attribution" "0: Privileged,1: UnPrivileged" newline bitfld.long 0xC 26. "PPARE26,General PWM Timer Channel 5 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 21. "PPARE21,General PWM Timer Channel 10 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 20. "PPARE20,General PWM Timer Channel 11 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 19. "PPARE19,General PWM Timer Channel 12 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 18. "PPARE18,General PWM Timer Channel 13 Privilege Attribution" "0: Privileged,1: UnPrivileged" newline bitfld.long 0xC 9. "PPARE9,ULPT0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 8. "PPARE8,ULPT1 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 3. "PPARE3,Real Time Clock Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 2. "PPARE2,IWDT Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 1. "PPARE1,WDT Privilege Attribution" "0: Privileged,1: UnPrivileged" line.long 0x10 "MSPAR,Module Stop Privilege Attribution Register" bitfld.long 0x10 31. "MSPAR31,ELC Clock Stop Privilege Attribution" "0: Privileged,1: UnPrivileged" rgroup.long 0x30++0xB line.long 0x0 "CFSAMONA,Code Flash Security Attribution Monitor Register A" hexmask.long.word 0x0 15.--23. 1. "CFS2,Code Flash Secure Area" line.long 0x4 "DFSAMON,Data Flash Security Attribution Monitor Register" hexmask.long.byte 0x4 10.--15. 1. "DFS,Data Flash Secure Area" line.long 0x8 "DLMMON,Device Lifecycle Management State Monitor Register" hexmask.long.byte 0x8 0.--3. 1. "DLMMON,Device Lifecycle Management State Monitor" tree.end tree "PSCU_NS" base ad:0x50204000 group.long 0x4++0x13 line.long 0x0 "PSARB,Peripheral Security Attribution Register B" bitfld.long 0x0 31. "PSARB31,Serial Communication Interface 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 30. "PSARB30,Serial Communication Interface 1 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 29. "PSARB29,Serial Communication Interface 2 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 28. "PSARB28,Serial Communication Interface 3 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 27. "PSARB27,Serial Communication Interface 4 Security Attribution" "0: Secure,1: Non-secure" newline bitfld.long 0x0 22. "PSARB22,Serial Communication Interface 9 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 19. "PSARB19,Serial Peripheral Interface 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 18. "PSARB18,Serial Peripheral Interface 1 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 16. "PSARB16,Octa Memory Controller Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 11. "PSARB11,Universal Serial Bus 2.0 FS Interface 0 Security Attribution" "0: Secure,1: Non-secure" newline bitfld.long 0x0 9. "PSARB9,I2C Bus Interface 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x0 8. "PSARB8,I2C Bus Interface 1 Security Attribution" "0: Secure,1: Non-secure" line.long 0x4 "PSARC,Peripheral Security Attribution Register C" bitfld.long 0x4 31. "PSARC31,RSIP-E51A Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x4 27. "PSARC27,Controller Area Network with Flexible Data-Rate 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x4 26. "PSARC26,Controller Area Network with Flexible Data-Rate 1 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x4 15. "PSARC15,Graphic (GLCDC DRW) Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x4 13. "PSARC13,Data Operation Circuit Security Attribution" "0: Secure,1: Non-secure" newline bitfld.long 0x4 8. "PSARC8,Serial Sound Interface Enhanced (channel 0) Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x4 7. "PSARC7,Serial Sound Interface Enhanced (channel 1) Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x4 1. "PSARC1,Cyclic Redundancy Check Calculator Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x4 0. "PSARC0,Clock Frequency Accuracy Measurement Circuit Security Attribution register specifies the security attribution for each module and the corresponding bit in Module Stop Control Register." "0: Secure,1: Non-secure" line.long 0x8 "PSARD,Peripheral Security Attribution Register D" bitfld.long 0x8 28. "PSARD28,High Speed Analog Comparator 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 27. "PSARD27,High Speed Analog Comparator 1 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 22. "PSARD22,Temperature Sensor Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 20. "PSARD20,12-Bit D/A Converter Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 16. "PSARD16,12-Bit A/D 0 Converter Security Attribution" "0: Secure,1: Non-secure" newline bitfld.long 0x8 15. "PSARD15,12-Bit A/D 1 Converter Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 14. "PSARD14,Port Output Enable for GPT Group 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 13. "PSARD13,Port Output Enable for GPT Group 1 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 12. "PSARD12,Port Output Enable for GPT Group 2 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 11. "PSARD11,Port Output Enable for GPT Group 3 Security Attribution" "0: Secure,1: Non-secure" newline bitfld.long 0x8 5. "PSARD5,Asynchronous General Purpose Timer 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x8 4. "PSARD4,Asynchronous General Purpose Timer 1 Security Attribution" "0: Secure,1: Non-secure" line.long 0xC "PSARE,Peripheral Security Attribution Register E" bitfld.long 0xC 31. "PSARE31,General PWM Timer Channel 0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 30. "PSARE30,General PWM Timer Channel 1 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 29. "PSARE29,General PWM Timer Channel 2 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 28. "PSARE28,General PWM Timer Channel 3 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 27. "PSARE27,General PWM Timer Channel 4 Security Attribution" "0: Secure,1: Non-secure" newline bitfld.long 0xC 26. "PSARE26,General PWM Timer Channel 5 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 21. "PSARE21,General PWM Timer Channel 10 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 20. "PSARE20,General PWM Timer Channel 11 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 19. "PSARE19,General PWM Timer Channel 12 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 18. "PSARE18,General PWM Timer Channel 13 Security Attribution" "0: Secure,1: Non-secure" newline bitfld.long 0xC 9. "PSARE9,ULPT0 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 8. "PSARE8,ULPT1 Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 3. "PSARE3,Real Time Clock Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 2. "PSARE2,IWDT Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0xC 1. "PSARE1,WDT Security Attribution" "0: Secure,1: Non-secure" line.long 0x10 "MSSAR,Module Stop Security Attribution Register" bitfld.long 0x10 31. "MSSAR31,ELC Clock Stop Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x10 22. "MSSAR22,DMAC/DTC Clock Stop Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x10 15. "MSSAR15,Standby RAM Clock Stop Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x10 1. "MSSAR1,SRAM1 Clock Stop Security Attribution" "0: Secure,1: Non-secure" bitfld.long 0x10 0. "MSSAR0,SRAM0 Clock Stop Security Attribution" "0: Secure,1: Non-secure" group.long 0x1C++0x13 line.long 0x0 "PPARB,Peripheral Privilege Attribution Register B" bitfld.long 0x0 31. "PPARB31,Serial Communication Interface 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 30. "PPARB30,Serial Communication Interface 1 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 29. "PPARB29,Serial Communication Interface 2 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 28. "PPARB28,Serial Communication Interface 3 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 27. "PPARB27,Serial Communication Interface 4 Privilege Attribution" "0: Privileged,1: UnPrivileged" newline bitfld.long 0x0 22. "PPARB22,Serial Communication Interface 9 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 19. "PPARB19,Serial Peripheral Interface 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 18. "PPARB18,Serial Peripheral Interface 1 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 16. "PPARB16,Octa Memory Controller Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 11. "PPARB11,Universal Serial Bus 2.0 FS Interface 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" newline bitfld.long 0x0 9. "PPARB9,I2C Bus Interface 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x0 8. "PPARB8,I2C Bus Interface 1 Privilege Attribution" "0: Privileged,1: UnPrivileged" line.long 0x4 "PPARC,Peripheral Privilege Attribution Register C" bitfld.long 0x4 31. "PPARC31,RSIP-E51A Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x4 27. "PPARC27,Controller Area Network with Flexible Data-Rate 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x4 26. "PPARC26,Controller Area Network with Flexible Data-Rate 1 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x4 15. "PPARC15,Graphic (GLCDC DRW) Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x4 13. "PPARC13,Data Operation Circuit Privilege Attribution" "0: Privileged,1: UnPrivileged" newline bitfld.long 0x4 8. "PPARC8,Serial Sound Interface Enhanced (Channel 0) Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x4 7. "PPARC7,Serial Sound Interface Enhanced (Channel 1) Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x4 1. "PPARC1,Cyclic Redundancy Check Calculator Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x4 0. "PPARC0,Clock Frequency Accuracy Measurement Circuit Privilege Attribution" "0: Privileged,1: UnPrivileged" line.long 0x8 "PPARD,Peripheral Privilege Attribution Register D" bitfld.long 0x8 28. "PPARD28,High speed analog Comparator 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 27. "PPARD27,High speed analog Comparator 1 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 22. "PPARD22,Temperature Sensor Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 20. "PPARD20,12-Bit D/A Converter Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 16. "PPARD16,12-Bit A/D 0 Converter Privilege Attribution" "0: Privileged,1: UnPrivileged" newline bitfld.long 0x8 15. "PPARD15,12-Bit A/D 1 Converter Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 14. "PPARD14,Port Output Enable for GPT Group 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 13. "PPARD13,Port Output Enable for GPT Group 1 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 12. "PPARD12,Port Output Enable for GPT Group 2 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 11. "PPARD11,Port Output Enable for GPT Group 3 Privilege Attribution" "0: Privileged,1: UnPrivileged" newline bitfld.long 0x8 5. "PPARD5,Asynchronous General Purpose Timer 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0x8 4. "PPARD4,Asynchronous General Purpose Timer 1 Privilege Attribution" "0: Privileged,1: UnPrivileged" line.long 0xC "PPARE,Peripheral Privilege Attribution Register E" bitfld.long 0xC 31. "PPARE31,General PWM Timer Channel 0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 30. "PPARE30,General PWM Timer Channel 1 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 29. "PPARE29,General PWM Timer Channel 2 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 28. "PPARE28,General PWM Timer Channel 3 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 27. "PPARE27,General PWM Timer Channel 4 Privilege Attribution" "0: Privileged,1: UnPrivileged" newline bitfld.long 0xC 26. "PPARE26,General PWM Timer Channel 5 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 21. "PPARE21,General PWM Timer Channel 10 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 20. "PPARE20,General PWM Timer Channel 11 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 19. "PPARE19,General PWM Timer Channel 12 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 18. "PPARE18,General PWM Timer Channel 13 Privilege Attribution" "0: Privileged,1: UnPrivileged" newline bitfld.long 0xC 9. "PPARE9,ULPT0 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 8. "PPARE8,ULPT1 Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 3. "PPARE3,Real Time Clock Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 2. "PPARE2,IWDT Privilege Attribution" "0: Privileged,1: UnPrivileged" bitfld.long 0xC 1. "PPARE1,WDT Privilege Attribution" "0: Privileged,1: UnPrivileged" line.long 0x10 "MSPAR,Module Stop Privilege Attribution Register" bitfld.long 0x10 31. "MSPAR31,ELC Clock Stop Privilege Attribution" "0: Privileged,1: UnPrivileged" rgroup.long 0x30++0xB line.long 0x0 "CFSAMONA,Code Flash Security Attribution Monitor Register A" hexmask.long.word 0x0 15.--23. 1. "CFS2,Code Flash Secure Area" line.long 0x4 "DFSAMON,Data Flash Security Attribution Monitor Register" hexmask.long.byte 0x4 10.--15. 1. "DFS,Data Flash Secure Area" line.long 0x8 "DLMMON,Device Lifecycle Management State Monitor Register" hexmask.long.byte 0x8 0.--3. 1. "DLMMON,Device Lifecycle Management State Monitor" tree.end tree.end tree "RMPU (Renesas Memory Protection Unit)" base ad:0x0 tree "RMPU" base ad:0x40000000 group.word 0x0++0x1 line.word 0x0 "MMPUOAD,MMPU Operation After Detection Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "OAD,Operation after detection" "0: NMI,1: Reset" group.word 0x4++0x1 line.word 0x0 "MMPUOADPT,MMPU Operation After Detection Protect Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: MMPUOAD register writing is possible.,1: MMPUOAD register writing is protected. Read is.." group.word 0x100++0x1 line.word 0x0 "MMPUENDMAC,MMPU Enable Register for DMAC" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "ENABLE,Bus master MPU of DMAC Enable" "0: Bus master MPU of DMAC is disabled.,1: Bus master MPU of DMAC is enabled." group.word 0x104++0x1 line.word 0x0 "MMPUENPTDMAC,MMPU Enable Protect Register for DMAC" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: MMPUENDMAC register write is possible.,1: MMPUENDMAC register write is protected. Read is.." group.word 0x10C++0x1 line.word 0x0 "MMPURPTDMAC_SEC,MMPU Regions Protect register for DMAC Secure" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: Bus master MPU register for DMAC Secure write is..,1: Bus master MPU register for DMAC Secure write is.." repeat 8. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0x200)++0x1 line.word 0x0 "MMPUACDMAC$1,MMPU Access Control Register for DMAC (n = 0 to 7)" bitfld.word 0x0 3. "PP,Privilege protection" "0: Unprivileged access permission,1: Unprivileged access protection" bitfld.word 0x0 2. "WP,Write protection" "0: Write permission,1: Write protection" newline bitfld.word 0x0 1. "RP,Read protection" "0: Read permission,1: Read protection" bitfld.word 0x0 0. "ENABLE,Region Enable" "0: DMAC region n unit is disabled.,1: DMAC region n unit is enabled." repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x204)++0x3 line.long 0x0 "MMPUSDMAC$1,MMPU Start Address Register for DMAC (n = 0 to 7)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x208)++0x3 line.long 0x0 "MMPUEDMAC$1,MMPU End Address Register for DMAC (n = 0 to 7)" repeat.end group.word 0x700++0x1 line.word 0x0 "MMPUENGLCDC,MMPU Enable Register for GLCDC" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "ENABLE,Bus master MPU of GLCDC Enable" "0: Bus master MPU of GLCDC is disabled.,1: Bus master MPU of GLCDC is enabled." group.word 0x704++0x1 line.word 0x0 "MMPUENPTGLCDC,MMPU Enable Protect Register for GLCDC" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: MMPUENGLCDC register write is possible.,1: MMPUENGLCDC register write is protected. Read is.." group.word 0x708++0x1 line.word 0x0 "MMPURPTGLCDC,MMPU Regions Protect Register for GLCDC" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: Bus master MPU register for GLCDC write is..,1: Bus master MPU register for GLCDC write is.." repeat 2. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0x800)++0x1 line.word 0x0 "MMPUACGLCDC$1,MMPU Access Control Register for GLCDC (n = 0. 1)" bitfld.word 0x0 2. "WP,Write protection" "0: Write permission,1: Write protection" bitfld.word 0x0 1. "RP,Read protection" "0: Read permission,1: Read protection" newline bitfld.word 0x0 0. "ENABLE,Region Enable" "0: GLCDC region n unit is disabled.,1: GLCDC region n unit is enabled." repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x804)++0x3 line.long 0x0 "MMPUSGLCDC$1,MMPU Start Address Register for GLCDC (n = 0. 1)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x808)++0x3 line.long 0x0 "MMPUEGLCDC$1,MMPU End Address Register for GLCDC (n = 0 to 1)" repeat.end group.word 0x900++0x1 line.word 0x0 "MMPUENDRW,MMPU Enable Register for DRW" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "ENABLE,Bus master MPU of DRW Enable" "0: Bus master MPU of DRW is disabled.,1: Bus master MPU of DRW is enabled." group.word 0x904++0x1 line.word 0x0 "MMPUENPDRW,MMPU Enable Protect Register for DRW" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: MMPUENDRW register write is possible.,1: MMPUENDRW register write is protected. Read is.." group.word 0x908++0x1 line.word 0x0 "MMPURPTDRW,MMPU Regions Protect Register for DRW" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: Bus master MPU register for DRW write is possible.,1: Bus master MPU register for DRW write is.." repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0xA00)++0x1 line.word 0x0 "MMPUACDRW$1,MMPU Access Control Register for DRW (n = 0 to 2)" bitfld.word 0x0 2. "WP,Write protection" "0: Write permission,1: Write protection" bitfld.word 0x0 1. "RP,Read protection" "0: Read permission,1: Read protection" newline bitfld.word 0x0 0. "ENABLE,Region Enable" "0: DRW region n unit is disabled.,1: DRW region n unit is enabled." repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0xA04)++0x3 line.long 0x0 "MMPUSDRW$1,MMPU Start Address Register for DRW (n = 0 to 2)" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0xA08)++0x3 line.long 0x0 "MMPUEDRW$1,MMPU End Address Register for DRW (n = 0 to 2)" repeat.end tree.end tree "RMPU_NS" base ad:0x50000000 group.word 0x0++0x1 line.word 0x0 "MMPUOAD,MMPU Operation After Detection Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "OAD,Operation after detection" "0: NMI,1: Reset" group.word 0x4++0x1 line.word 0x0 "MMPUOADPT,MMPU Operation After Detection Protect Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: MMPUOAD register writing is possible.,1: MMPUOAD register writing is protected. Read is.." group.word 0x100++0x1 line.word 0x0 "MMPUENDMAC,MMPU Enable Register for DMAC" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "ENABLE,Bus master MPU of DMAC Enable" "0: Bus master MPU of DMAC is disabled.,1: Bus master MPU of DMAC is enabled." group.word 0x104++0x1 line.word 0x0 "MMPUENPTDMAC,MMPU Enable Protect Register for DMAC" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: MMPUENDMAC register write is possible.,1: MMPUENDMAC register write is protected. Read is.." group.word 0x108++0x1 line.word 0x0 "MMPURPTDMAC,MMPU Regions Protect Register for DMAC Non-secure" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: Bus master MPU register for DMAC write is..,1: Bus master MPU register for DMAC write is.." repeat 8. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0x200)++0x1 line.word 0x0 "MMPUACDMAC$1,MMPU Access Control Register for DMAC (n = 0 to 7)" bitfld.word 0x0 3. "PP,Privilege protection" "0: Unprivileged access permission,1: Unprivileged access protection" bitfld.word 0x0 2. "WP,Write protection" "0: Write permission,1: Write protection" newline bitfld.word 0x0 1. "RP,Read protection" "0: Read permission,1: Read protection" bitfld.word 0x0 0. "ENABLE,Region Enable" "0: DMAC region n unit is disabled.,1: DMAC region n unit is enabled." repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x204)++0x3 line.long 0x0 "MMPUSDMAC$1,MMPU Start Address Register for DMAC (n = 0 to 7)" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x208)++0x3 line.long 0x0 "MMPUEDMAC$1,MMPU End Address Register for DMAC (n = 0 to 7)" repeat.end group.word 0x700++0x1 line.word 0x0 "MMPUENGLCDC,MMPU Enable Register for GLCDC" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "ENABLE,Bus master MPU of GLCDC Enable" "0: Bus master MPU of GLCDC is disabled.,1: Bus master MPU of GLCDC is enabled." group.word 0x704++0x1 line.word 0x0 "MMPUENPTGLCDC,MMPU Enable Protect Register for GLCDC" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: MMPUENGLCDC register write is possible.,1: MMPUENGLCDC register write is protected. Read is.." group.word 0x708++0x1 line.word 0x0 "MMPURPTGLCDC,MMPU Regions Protect Register for GLCDC" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: Bus master MPU register for GLCDC write is..,1: Bus master MPU register for GLCDC write is.." repeat 2. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0x800)++0x1 line.word 0x0 "MMPUACGLCDC$1,MMPU Access Control Register for GLCDC (n = 0. 1)" bitfld.word 0x0 2. "WP,Write protection" "0: Write permission,1: Write protection" bitfld.word 0x0 1. "RP,Read protection" "0: Read permission,1: Read protection" newline bitfld.word 0x0 0. "ENABLE,Region Enable" "0: GLCDC region n unit is disabled.,1: GLCDC region n unit is enabled." repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x804)++0x3 line.long 0x0 "MMPUSGLCDC$1,MMPU Start Address Register for GLCDC (n = 0. 1)" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x808)++0x3 line.long 0x0 "MMPUEGLCDC$1,MMPU End Address Register for GLCDC (n = 0 to 1)" repeat.end group.word 0x900++0x1 line.word 0x0 "MMPUENDRW,MMPU Enable Register for DRW" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "ENABLE,Bus master MPU of DRW Enable" "0: Bus master MPU of DRW is disabled.,1: Bus master MPU of DRW is enabled." group.word 0x904++0x1 line.word 0x0 "MMPUENPDRW,MMPU Enable Protect Register for DRW" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: MMPUENDRW register write is possible.,1: MMPUENDRW register write is protected. Read is.." group.word 0x908++0x1 line.word 0x0 "MMPURPTDRW,MMPU Regions Protect Register for DRW" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code" bitfld.word 0x0 0. "PROTECT,Protection of register" "0: Bus master MPU register for DRW write is possible.,1: Bus master MPU register for DRW write is.." repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0xA00)++0x1 line.word 0x0 "MMPUACDRW$1,MMPU Access Control Register for DRW (n = 0 to 2)" bitfld.word 0x0 2. "WP,Write protection" "0: Write permission,1: Write protection" bitfld.word 0x0 1. "RP,Read protection" "0: Read permission,1: Read protection" newline bitfld.word 0x0 0. "ENABLE,Region Enable" "0: DRW region n unit is disabled.,1: DRW region n unit is enabled." repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0xA04)++0x3 line.long 0x0 "MMPUSDRW$1,MMPU Start Address Register for DRW (n = 0 to 2)" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0xA08)++0x3 line.long 0x0 "MMPUEDRW$1,MMPU End Address Register for DRW (n = 0 to 2)" repeat.end tree.end tree.end tree "RTC (Realtime Clock)" base ad:0x0 tree "RTC" base ad:0x40202000 rgroup.byte 0x0++0x0 line.byte 0x0 "R64CNT,64-Hz Counter" bitfld.byte 0x0 6. "F1HZ,1-Hz Flag" "0,1" bitfld.byte 0x0 5. "F2HZ,2-Hz Flag" "0,1" newline bitfld.byte 0x0 4. "F4HZ,4-Hz Flag" "0,1" bitfld.byte 0x0 3. "F8HZ,8-Hz Flag" "0,1" newline bitfld.byte 0x0 2. "F16HZ,16-Hz Flag" "0,1" bitfld.byte 0x0 1. "F32HZ,32-Hz Flag" "0,1" newline bitfld.byte 0x0 0. "F64HZ,64-Hz Flag" "0,1" repeat 4. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0x2)++0x0 line.byte 0x0 "BCNT$1,Binary Counter %s" hexmask.byte 0x0 0.--7. 1. "BCNT,Binary Counter" repeat.end group.byte 0x2++0x0 line.byte 0x0 "RSECCNT,Second Counter (in Calendar Count Mode)" bitfld.byte 0x0 4.--6. "SEC10,10-Second Count" "0,1,2,3,4,5,6,7" hexmask.byte 0x0 0.--3. 1. "SEC1,1-Second Count" group.byte 0x4++0x0 line.byte 0x0 "RMINCNT,Minute Counter (in Calendar Count Mode)" bitfld.byte 0x0 4.--6. "MIN10,10-Minute Count" "0,1,2,3,4,5,6,7" hexmask.byte 0x0 0.--3. 1. "MIN1,1-Minute Count" group.byte 0x6++0x0 line.byte 0x0 "RHRCNT,Hour Counter (in Calendar Count Mode)" bitfld.byte 0x0 6. "PM,AM/PM select for time counter setting." "0: AM,1: PM" bitfld.byte 0x0 4.--5. "HR10,10-Hour Count" "0,1,2,3" newline hexmask.byte 0x0 0.--3. 1. "HR1,1-Hour Count" group.byte 0x8++0x0 line.byte 0x0 "RWKCNT,Day-of-Week Counter (in Calendar Count Mode)" bitfld.byte 0x0 0.--2. "DAYW,Day-of-Week Counting" "0: Sunday,1: Monday,?,?,?,?,?,?" group.byte 0xA++0x0 line.byte 0x0 "RDAYCNT,Day Counter" bitfld.byte 0x0 4.--5. "DATE10,10-Day Count" "0,1,2,3" hexmask.byte 0x0 0.--3. 1. "DATE1,1-Day Count" group.byte 0xC++0x0 line.byte 0x0 "RMONCNT,Month Counter" bitfld.byte 0x0 4. "MON10,10-Month Count" "0,1" hexmask.byte 0x0 0.--3. 1. "MON1,1-Month Count" group.word 0xE++0x1 line.word 0x0 "RYRCNT,Year Counter" hexmask.word.byte 0x0 4.--7. 1. "YR10,10-Year Count" hexmask.word.byte 0x0 0.--3. 1. "YR1,1-Year Count" repeat 4. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0x10)++0x0 line.byte 0x0 "BCNT$1AR,Binary Counter %s Alarm Register" hexmask.byte 0x0 0.--7. 1. "BCNTAR,Alarm register associated with the 32-bit binary counter" repeat.end group.byte 0x10++0x0 line.byte 0x0 "RSECAR,Second Alarm Register (in Calendar Count Mode)" bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RSECCNT..,1: Compare register value with RSECCNT counter value" bitfld.byte 0x0 4.--6. "SEC10,10 Seconds" "0,1,2,3,4,5,6,7" newline hexmask.byte 0x0 0.--3. 1. "SEC1,1 Second" group.byte 0x12++0x0 line.byte 0x0 "RMINAR,Minute Alarm Register (in Calendar Count Mode)" bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RMINCNT..,1: Compare register value with RMINCNT counter value" bitfld.byte 0x0 4.--6. "MIN10,10 Minutes" "0,1,2,3,4,5,6,7" newline hexmask.byte 0x0 0.--3. 1. "MIN1,1 Minute" group.byte 0x14++0x0 line.byte 0x0 "RHRAR,Hour Alarm Register (in Calendar Count Mode)" bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RHRCNT..,1: Compare register value with RHRCNT counter value" bitfld.byte 0x0 6. "PM,AM/PM select for alarm setting." "0: AM,1: PM" newline bitfld.byte 0x0 4.--5. "HR10,10 Hours" "0,1,2,3" hexmask.byte 0x0 0.--3. 1. "HR1,1 Hour" group.byte 0x16++0x0 line.byte 0x0 "RWKAR,Day-of-Week Alarm Register (in Calendar Count Mode)" bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RWKCNT..,1: Compare register value with RWKCNT counter value" bitfld.byte 0x0 0.--2. "DAYW,Day-of-Week Setting" "0: Sunday,1: Monday,?,?,?,?,?,?" repeat 4. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0x18)++0x0 line.byte 0x0 "BCNT$1AER,Binary Counter %s Alarm Enable Register" hexmask.byte 0x0 0.--7. 1. "ENB,Setting the alarm enable associated with the 32-bit binary counter" repeat.end group.byte 0x18++0x0 line.byte 0x0 "RDAYAR,Date Alarm Register (in Calendar Count Mode)" bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RDAYCNT..,1: Compare register value with RDAYCNT counter value" bitfld.byte 0x0 4.--5. "DATE10,10 Days" "0,1,2,3" newline hexmask.byte 0x0 0.--3. 1. "DATE1,1 Day" group.byte 0x1A++0x0 line.byte 0x0 "RMONAR,Month Alarm Register (in Calendar Count Mode)" bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RMONCNT..,1: Compare register value with RMONCNT counter value" bitfld.byte 0x0 4. "MON10,10 Months" "0,1" newline hexmask.byte 0x0 0.--3. 1. "MON1,1 Month" group.word 0x1C++0x1 line.word 0x0 "RYRAR,Year Alarm Register (in Calendar Count Mode)" hexmask.word.byte 0x0 4.--7. 1. "YR10,10 Years" hexmask.word.byte 0x0 0.--3. 1. "YR1,1 Year" group.byte 0x1E++0x0 line.byte 0x0 "RYRAREN,Year Alarm Enable Register (in Calendar Count Mode)" bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with the RYRCNT..,1: Compare register value with the RYRCNT counter.." group.byte 0x22++0x0 line.byte 0x0 "RCR1,RTC Control Register 1" hexmask.byte 0x0 4.--7. 1. "PES,Periodic Interrupt Select" bitfld.byte 0x0 3. "RTCOS,RTCOUT Output Select" "0: Outputs 1 Hz on RTCOUT,1: Outputs 64 Hz RTCOUT" newline bitfld.byte 0x0 2. "PIE,Periodic Interrupt Enable" "0: Disable periodic interrupt requests,1: Enable periodic interrupt requests" bitfld.byte 0x0 1. "CIE,Carry Interrupt Enable" "0: Disable carry interrupt requests,1: Enable carry interrupt requests" newline bitfld.byte 0x0 0. "AIE,Alarm Interrupt Enable" "0: Disable alarm interrupt requests,1: Enable alarm interrupt requests" group.byte 0x24++0x0 line.byte 0x0 "RCR2,RTC Control Register 2 (in Calendar Count Mode)" bitfld.byte 0x0 7. "CNTMD,Count Mode Select" "0: Calendar count mode,1: Binary count mode" bitfld.byte 0x0 6. "HR24,Hours Mode" "0: Operate RTC in 12-hour mode,1: Operate RTC in 24-hour mode" newline bitfld.byte 0x0 5. "AADJP,Automatic Adjustment Period Select" "0: The RADJ.ADJ[5:0] setting from the count value..,1: The RADJ.ADJ[5:0] setting value is adjusted from.." bitfld.byte 0x0 4. "AADJE,Automatic Adjustment Enable" "0: Disable automatic adjustment,1: Enable automatic adjustment" newline bitfld.byte 0x0 3. "RTCOE,RTCOUT Output Enable" "0: Disable RTCOUT output,1: Enable RTCOUT output" bitfld.byte 0x0 2. "ADJ30,30-Second Adjustment" "0: In writing: Invalid (writing 0 has no effect).,1: In writing: Execute 30-second adjustment. In.." newline bitfld.byte 0x0 1. "RESET,RTC Software Reset" "0: In writing: Invalid (writing 0 has no effect).,1: In writing: Initialize the prescaler and target.." bitfld.byte 0x0 0. "START,Start" "0: Stop prescaler and time counter,1: Operate prescaler and time counter normally" group.byte 0x24++0x0 line.byte 0x0 "RCR2_BCNT,RTC Control Register 2 (in Binary Count Mode)" bitfld.byte 0x0 7. "CNTMD,Count Mode Select" "0: Calendar count mode,1: Binary count mode" bitfld.byte 0x0 5. "AADJP,Automatic Adjustment Period Select" "0: Add or subtract RADJ.ADJ [5:0] bits from..,1: Add or subtract RADJ.ADJ [5:0] bits from.." newline bitfld.byte 0x0 4. "AADJE,Automatic Adjustment Enable" "0: Disable automatic adjustment,1: Enable automatic adjustment" bitfld.byte 0x0 3. "RTCOE,RTCOUT Output Enable" "0: Disable RTCOUT output,1: Enable RTCOUT output" newline bitfld.byte 0x0 1. "RESET,RTC Software Reset" "0: In writing: Invalid (writing 0 has no effect).,1: In writing: Initialize the prescaler and target.." bitfld.byte 0x0 0. "START,Start" "0: Stop the 32-bit binary counter 64-Hz counter and..,1: Operate the 32-bit binary counter 64-Hz counter.." group.byte 0x28++0x0 line.byte 0x0 "RCR4,RTC Control Register 4" bitfld.byte 0x0 0. "RCKSEL,Count Source Select" "0: Sub-clock oscillator is selected,1: LOCO is selected" group.word 0x2A++0x3 line.word 0x0 "RFRH,Frequency Register H" bitfld.word 0x0 0. "RFC16,Write 0 before writing to the RFRL register after a cold start." "0,1" line.word 0x2 "RFRL,Frequency Register L" hexmask.word 0x2 0.--15. 1. "RFC,Frequency Comparison Value" group.byte 0x2E++0x0 line.byte 0x0 "RADJ,Time Error Adjustment Register" bitfld.byte 0x0 6.--7. "PMADJ,Plus-Minus" "0: Do not perform adjustment.,1: Adjustment is performed by the addition to the..,?,?" hexmask.byte 0x0 0.--5. 1. "ADJ,Adjustment Value" repeat 3. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0x40)++0x0 line.byte 0x0 "RTCCR$1,Time Capture Control Register %s" bitfld.byte 0x0 7. "TCEN,Time Capture Event Input Pin Enable" "0: Disable the RTCICn pin as the time capture event..,1: Enable the RTCICn pin as the time capture event.." bitfld.byte 0x0 4.--5. "TCNF,Time Capture Noise Filter Control" "0: Turn noise filter off,1: Setting prohibited,?,?" newline bitfld.byte 0x0 2. "TCST,Time Capture Status" "0: No event detected,1: Event detected" bitfld.byte 0x0 0.--1. "TCCT,Time Capture Control" "0: Do not detect events,1: Detect rising edge,?,?" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x52)++0x0 line.byte 0x0 "BCNT0CP$1,BCNT0 Capture Register %s" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x52)++0x0 line.byte 0x0 "RSECCP$1,Second Capture Register %s" bitfld.byte 0x0 4.--6. "SEC10,10-Second Capture" "0,1,2,3,4,5,6,7" hexmask.byte 0x0 0.--3. 1. "SEC1,1-Second Capture" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x54)++0x0 line.byte 0x0 "BCNT1CP$1,BCNT1 Capture Register %s" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x54)++0x0 line.byte 0x0 "RMINCP$1,Minute Capture Register %s" bitfld.byte 0x0 4.--6. "MIN10,10-Minute Capture" "0,1,2,3,4,5,6,7" hexmask.byte 0x0 0.--3. 1. "MIN1,1-Minute Capture" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x56)++0x0 line.byte 0x0 "BCNT2CP$1,BCNT2 Capture Register %s" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x56)++0x0 line.byte 0x0 "RHRCP$1,Hour Capture Register %s" bitfld.byte 0x0 6. "PM,PM" "0: AM,1: PM" bitfld.byte 0x0 4.--5. "HR10,10-Hour Capture" "0,1,2,3" newline hexmask.byte 0x0 0.--3. 1. "HR1,1-Hour Capture" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x5A)++0x0 line.byte 0x0 "BCNT3CP$1,BCNT3 Capture Register %s" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x5A)++0x0 line.byte 0x0 "RDAYCP$1,Date Capture Register %s" bitfld.byte 0x0 4.--5. "DATE10,10-Day Capture" "0,1,2,3" hexmask.byte 0x0 0.--3. 1. "DATE1,1-Day Capture" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x5C)++0x0 line.byte 0x0 "RMONCP$1,Month Capture Register %s" bitfld.byte 0x0 4. "MON10,10-Month Capture" "0,1" hexmask.byte 0x0 0.--3. 1. "MON1,1-Month Capture" repeat.end tree.end tree "RTC_NS" base ad:0x50202000 rgroup.byte 0x0++0x0 line.byte 0x0 "R64CNT,64-Hz Counter" bitfld.byte 0x0 6. "F1HZ,1-Hz Flag" "0,1" bitfld.byte 0x0 5. "F2HZ,2-Hz Flag" "0,1" newline bitfld.byte 0x0 4. "F4HZ,4-Hz Flag" "0,1" bitfld.byte 0x0 3. "F8HZ,8-Hz Flag" "0,1" newline bitfld.byte 0x0 2. "F16HZ,16-Hz Flag" "0,1" bitfld.byte 0x0 1. "F32HZ,32-Hz Flag" "0,1" newline bitfld.byte 0x0 0. "F64HZ,64-Hz Flag" "0,1" repeat 4. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0x2)++0x0 line.byte 0x0 "BCNT$1,Binary Counter %s" hexmask.byte 0x0 0.--7. 1. "BCNT,Binary Counter" repeat.end group.byte 0x2++0x0 line.byte 0x0 "RSECCNT,Second Counter (in Calendar Count Mode)" bitfld.byte 0x0 4.--6. "SEC10,10-Second Count" "0,1,2,3,4,5,6,7" hexmask.byte 0x0 0.--3. 1. "SEC1,1-Second Count" group.byte 0x4++0x0 line.byte 0x0 "RMINCNT,Minute Counter (in Calendar Count Mode)" bitfld.byte 0x0 4.--6. "MIN10,10-Minute Count" "0,1,2,3,4,5,6,7" hexmask.byte 0x0 0.--3. 1. "MIN1,1-Minute Count" group.byte 0x6++0x0 line.byte 0x0 "RHRCNT,Hour Counter (in Calendar Count Mode)" bitfld.byte 0x0 6. "PM,AM/PM select for time counter setting." "0: AM,1: PM" bitfld.byte 0x0 4.--5. "HR10,10-Hour Count" "0,1,2,3" newline hexmask.byte 0x0 0.--3. 1. "HR1,1-Hour Count" group.byte 0x8++0x0 line.byte 0x0 "RWKCNT,Day-of-Week Counter (in Calendar Count Mode)" bitfld.byte 0x0 0.--2. "DAYW,Day-of-Week Counting" "0: Sunday,1: Monday,?,?,?,?,?,?" group.byte 0xA++0x0 line.byte 0x0 "RDAYCNT,Day Counter" bitfld.byte 0x0 4.--5. "DATE10,10-Day Count" "0,1,2,3" hexmask.byte 0x0 0.--3. 1. "DATE1,1-Day Count" group.byte 0xC++0x0 line.byte 0x0 "RMONCNT,Month Counter" bitfld.byte 0x0 4. "MON10,10-Month Count" "0,1" hexmask.byte 0x0 0.--3. 1. "MON1,1-Month Count" group.word 0xE++0x1 line.word 0x0 "RYRCNT,Year Counter" hexmask.word.byte 0x0 4.--7. 1. "YR10,10-Year Count" hexmask.word.byte 0x0 0.--3. 1. "YR1,1-Year Count" repeat 4. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0x10)++0x0 line.byte 0x0 "BCNT$1AR,Binary Counter %s Alarm Register" hexmask.byte 0x0 0.--7. 1. "BCNTAR,Alarm register associated with the 32-bit binary counter" repeat.end group.byte 0x10++0x0 line.byte 0x0 "RSECAR,Second Alarm Register (in Calendar Count Mode)" bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RSECCNT..,1: Compare register value with RSECCNT counter value" bitfld.byte 0x0 4.--6. "SEC10,10 Seconds" "0,1,2,3,4,5,6,7" newline hexmask.byte 0x0 0.--3. 1. "SEC1,1 Second" group.byte 0x12++0x0 line.byte 0x0 "RMINAR,Minute Alarm Register (in Calendar Count Mode)" bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RMINCNT..,1: Compare register value with RMINCNT counter value" bitfld.byte 0x0 4.--6. "MIN10,10 Minutes" "0,1,2,3,4,5,6,7" newline hexmask.byte 0x0 0.--3. 1. "MIN1,1 Minute" group.byte 0x14++0x0 line.byte 0x0 "RHRAR,Hour Alarm Register (in Calendar Count Mode)" bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RHRCNT..,1: Compare register value with RHRCNT counter value" bitfld.byte 0x0 6. "PM,AM/PM select for alarm setting." "0: AM,1: PM" newline bitfld.byte 0x0 4.--5. "HR10,10 Hours" "0,1,2,3" hexmask.byte 0x0 0.--3. 1. "HR1,1 Hour" group.byte 0x16++0x0 line.byte 0x0 "RWKAR,Day-of-Week Alarm Register (in Calendar Count Mode)" bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RWKCNT..,1: Compare register value with RWKCNT counter value" bitfld.byte 0x0 0.--2. "DAYW,Day-of-Week Setting" "0: Sunday,1: Monday,?,?,?,?,?,?" repeat 4. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0x18)++0x0 line.byte 0x0 "BCNT$1AER,Binary Counter %s Alarm Enable Register" hexmask.byte 0x0 0.--7. 1. "ENB,Setting the alarm enable associated with the 32-bit binary counter" repeat.end group.byte 0x18++0x0 line.byte 0x0 "RDAYAR,Date Alarm Register (in Calendar Count Mode)" bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RDAYCNT..,1: Compare register value with RDAYCNT counter value" bitfld.byte 0x0 4.--5. "DATE10,10 Days" "0,1,2,3" newline hexmask.byte 0x0 0.--3. 1. "DATE1,1 Day" group.byte 0x1A++0x0 line.byte 0x0 "RMONAR,Month Alarm Register (in Calendar Count Mode)" bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RMONCNT..,1: Compare register value with RMONCNT counter value" bitfld.byte 0x0 4. "MON10,10 Months" "0,1" newline hexmask.byte 0x0 0.--3. 1. "MON1,1 Month" group.word 0x1C++0x1 line.word 0x0 "RYRAR,Year Alarm Register (in Calendar Count Mode)" hexmask.word.byte 0x0 4.--7. 1. "YR10,10 Years" hexmask.word.byte 0x0 0.--3. 1. "YR1,1 Year" group.byte 0x1E++0x0 line.byte 0x0 "RYRAREN,Year Alarm Enable Register (in Calendar Count Mode)" bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with the RYRCNT..,1: Compare register value with the RYRCNT counter.." group.byte 0x22++0x0 line.byte 0x0 "RCR1,RTC Control Register 1" hexmask.byte 0x0 4.--7. 1. "PES,Periodic Interrupt Select" bitfld.byte 0x0 3. "RTCOS,RTCOUT Output Select" "0: Outputs 1 Hz on RTCOUT,1: Outputs 64 Hz RTCOUT" newline bitfld.byte 0x0 2. "PIE,Periodic Interrupt Enable" "0: Disable periodic interrupt requests,1: Enable periodic interrupt requests" bitfld.byte 0x0 1. "CIE,Carry Interrupt Enable" "0: Disable carry interrupt requests,1: Enable carry interrupt requests" newline bitfld.byte 0x0 0. "AIE,Alarm Interrupt Enable" "0: Disable alarm interrupt requests,1: Enable alarm interrupt requests" group.byte 0x24++0x0 line.byte 0x0 "RCR2,RTC Control Register 2 (in Calendar Count Mode)" bitfld.byte 0x0 7. "CNTMD,Count Mode Select" "0: Calendar count mode,1: Binary count mode" bitfld.byte 0x0 6. "HR24,Hours Mode" "0: Operate RTC in 12-hour mode,1: Operate RTC in 24-hour mode" newline bitfld.byte 0x0 5. "AADJP,Automatic Adjustment Period Select" "0: The RADJ.ADJ[5:0] setting from the count value..,1: The RADJ.ADJ[5:0] setting value is adjusted from.." bitfld.byte 0x0 4. "AADJE,Automatic Adjustment Enable" "0: Disable automatic adjustment,1: Enable automatic adjustment" newline bitfld.byte 0x0 3. "RTCOE,RTCOUT Output Enable" "0: Disable RTCOUT output,1: Enable RTCOUT output" bitfld.byte 0x0 2. "ADJ30,30-Second Adjustment" "0: In writing: Invalid (writing 0 has no effect).,1: In writing: Execute 30-second adjustment. In.." newline bitfld.byte 0x0 1. "RESET,RTC Software Reset" "0: In writing: Invalid (writing 0 has no effect).,1: In writing: Initialize the prescaler and target.." bitfld.byte 0x0 0. "START,Start" "0: Stop prescaler and time counter,1: Operate prescaler and time counter normally" group.byte 0x24++0x0 line.byte 0x0 "RCR2_BCNT,RTC Control Register 2 (in Binary Count Mode)" bitfld.byte 0x0 7. "CNTMD,Count Mode Select" "0: Calendar count mode,1: Binary count mode" bitfld.byte 0x0 5. "AADJP,Automatic Adjustment Period Select" "0: Add or subtract RADJ.ADJ [5:0] bits from..,1: Add or subtract RADJ.ADJ [5:0] bits from.." newline bitfld.byte 0x0 4. "AADJE,Automatic Adjustment Enable" "0: Disable automatic adjustment,1: Enable automatic adjustment" bitfld.byte 0x0 3. "RTCOE,RTCOUT Output Enable" "0: Disable RTCOUT output,1: Enable RTCOUT output" newline bitfld.byte 0x0 1. "RESET,RTC Software Reset" "0: In writing: Invalid (writing 0 has no effect).,1: In writing: Initialize the prescaler and target.." bitfld.byte 0x0 0. "START,Start" "0: Stop the 32-bit binary counter 64-Hz counter and..,1: Operate the 32-bit binary counter 64-Hz counter.." group.byte 0x28++0x0 line.byte 0x0 "RCR4,RTC Control Register 4" bitfld.byte 0x0 0. "RCKSEL,Count Source Select" "0: Sub-clock oscillator is selected,1: LOCO is selected" group.word 0x2A++0x3 line.word 0x0 "RFRH,Frequency Register H" bitfld.word 0x0 0. "RFC16,Write 0 before writing to the RFRL register after a cold start." "0,1" line.word 0x2 "RFRL,Frequency Register L" hexmask.word 0x2 0.--15. 1. "RFC,Frequency Comparison Value" group.byte 0x2E++0x0 line.byte 0x0 "RADJ,Time Error Adjustment Register" bitfld.byte 0x0 6.--7. "PMADJ,Plus-Minus" "0: Do not perform adjustment.,1: Adjustment is performed by the addition to the..,?,?" hexmask.byte 0x0 0.--5. 1. "ADJ,Adjustment Value" repeat 3. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0x40)++0x0 line.byte 0x0 "RTCCR$1,Time Capture Control Register %s" bitfld.byte 0x0 7. "TCEN,Time Capture Event Input Pin Enable" "0: Disable the RTCICn pin as the time capture event..,1: Enable the RTCICn pin as the time capture event.." bitfld.byte 0x0 4.--5. "TCNF,Time Capture Noise Filter Control" "0: Turn noise filter off,1: Setting prohibited,?,?" newline bitfld.byte 0x0 2. "TCST,Time Capture Status" "0: No event detected,1: Event detected" bitfld.byte 0x0 0.--1. "TCCT,Time Capture Control" "0: Do not detect events,1: Detect rising edge,?,?" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x52)++0x0 line.byte 0x0 "BCNT0CP$1,BCNT0 Capture Register %s" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x52)++0x0 line.byte 0x0 "RSECCP$1,Second Capture Register %s" bitfld.byte 0x0 4.--6. "SEC10,10-Second Capture" "0,1,2,3,4,5,6,7" hexmask.byte 0x0 0.--3. 1. "SEC1,1-Second Capture" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x54)++0x0 line.byte 0x0 "BCNT1CP$1,BCNT1 Capture Register %s" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x54)++0x0 line.byte 0x0 "RMINCP$1,Minute Capture Register %s" bitfld.byte 0x0 4.--6. "MIN10,10-Minute Capture" "0,1,2,3,4,5,6,7" hexmask.byte 0x0 0.--3. 1. "MIN1,1-Minute Capture" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x56)++0x0 line.byte 0x0 "BCNT2CP$1,BCNT2 Capture Register %s" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x56)++0x0 line.byte 0x0 "RHRCP$1,Hour Capture Register %s" bitfld.byte 0x0 6. "PM,PM" "0: AM,1: PM" bitfld.byte 0x0 4.--5. "HR10,10-Hour Capture" "0,1,2,3" newline hexmask.byte 0x0 0.--3. 1. "HR1,1-Hour Capture" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x5A)++0x0 line.byte 0x0 "BCNT3CP$1,BCNT3 Capture Register %s" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x5A)++0x0 line.byte 0x0 "RDAYCP$1,Date Capture Register %s" bitfld.byte 0x0 4.--5. "DATE10,10-Day Capture" "0,1,2,3" hexmask.byte 0x0 0.--3. 1. "DATE1,1-Day Capture" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x5C)++0x0 line.byte 0x0 "RMONCP$1,Month Capture Register %s" bitfld.byte 0x0 4. "MON10,10-Month Capture" "0,1" hexmask.byte 0x0 0.--3. 1. "MON1,1-Month Capture" repeat.end tree.end tree.end tree "SCI (Serial Communication Interface)" base ad:0x0 tree "SCI0_B" base ad:0x40358000 rgroup.long 0x0++0x3 line.long 0x0 "RDR,Receive Data Register" bitfld.long 0x0 28. "FER,Framing error flag" "0,1" bitfld.long 0x0 27. "PER,Parity error flag" "0,1" newline bitfld.long 0x0 24. "ORER,Overrun Error flag" "0,1" bitfld.long 0x0 12. "FFER,FIFO framing error flag" "0: There is no framing error in the data read from..,1: There is framing error in the data read from the.." newline bitfld.long 0x0 11. "FPER,FIFO parity error flag" "0: There is no parity error in the data read from..,1: There is parity error in the data read from the.." bitfld.long 0x0 10. "DR,Receive data ready flag" "0,1" newline bitfld.long 0x0 9. "MPB,Multi-processor flag" "0: Data transmission cycles,1: ID transmission cycles" hexmask.long.word 0x0 0.--8. 1. "RDAT,Serial receive data" rgroup.byte 0x0++0x0 line.byte 0x0 "RDR_BY,Receive Data Register" bitfld.byte 0x0 4. "FER,Framing error flag" "0,1" bitfld.byte 0x0 3. "PER,Parity error flag" "0,1" newline bitfld.byte 0x0 0. "ORER,Overrun Error flag" "0,1" group.long 0x4++0x3 line.long 0x0 "TDR,Transmit Data Register" bitfld.long 0x0 12. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.long 0x0 9. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline hexmask.long.word 0x0 0.--8. 1. "TDAT,Serial transmit data" group.byte 0x4++0x1 line.byte 0x0 "TDRLL,Transmit Data Register" line.byte 0x1 "TDRLH,Transmit Data Register" bitfld.byte 0x1 4. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.byte 0x1 1. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline bitfld.byte 0x1 0. "TDAT,Serial transmit data" "0,1" group.long 0x8++0x13 line.long 0x0 "CCR0,Common Control Register 0" bitfld.long 0x0 24. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled,1: SSn pin function is enabled" bitfld.long 0x0 21. "TEIE,Transmit End Interrupt Enable" "0: SCIn_TEI interrupt request is disabled,1: SCIn_TEI interrupt request is enabled" newline bitfld.long 0x0 20. "TIE,Transmit Interrupt Enable" "0: SCIn_TXI interrupt request is disabled,1: SCIn_TXI interrupt request is enabled" bitfld.long 0x0 16. "RIE,Receive Interrupt Enable" "0: SCIn_RXI and SCIn_ERI interrupt requests are..,1: SCIn_RXI and SCIn_ERI interrupt requests are.." newline bitfld.long 0x0 10. "IDSEL,ID Frame Select" "0: Compare data irrespective of the value of the..,1: Compare data only when the MPB bit is 1 (ID frame)" bitfld.long 0x0 9. "DCME,Data Compare Match Enable" "0: Address match function is disabled,1: Address match function is enabled" newline bitfld.long 0x0 8. "MPIE,Multi-Processor Interrupt Enable" "0: Non-multi-processor reception,1: Multi-processor reception When the data with the.." bitfld.long 0x0 4. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" newline bitfld.long 0x0 0. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" line.long 0x4 "CCR1,Common Control Register 1" bitfld.long 0x4 29. "NFM,Noise Filter Mode" "0: 3-point matching mode,1: Majority vote mode" bitfld.long 0x4 28. "NFEN,Digital Noise Filter Function Enable" "0: In Asynchronous Manchester Simple LIN modes:..,1: In Asynchronous Manchester Simple LIN modes:.." newline bitfld.long 0x4 24.--26. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: The on-chip baud rate generator source clock..,?,?,?,?,?,?" bitfld.long 0x4 20. "SHARPS,Half-Duplex Communication Select" "0: TXDn pin RXDn pin independent,1: TXDn/RXDn pin combination use (half-duplex.." newline bitfld.long 0x4 16. "SPLP,Loopback Control" "0: Normal mode,1: Loopback mode" bitfld.long 0x4 13. "RINV,RXD Invert" "0: Received data from RXDn is not inverted and input,1: Received data from RXDn is inverted and input" newline bitfld.long 0x4 12. "TINV,TXD Invert" "0: Transmit data is not inverted and output to TXDn,1: Transmit data is inverted and output to TXDn" bitfld.long 0x4 9. "PM,Parity Mode" "0: Selects even parity,1: Selects odd parity" newline bitfld.long 0x4 8. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.." bitfld.long 0x4 5. "SPB2IO,Serial Port Break I/O" "0: The value of SPB2DT bit is not output in TXDn pin,1: The value of SPB2DT bit is output in TXDn pin" newline bitfld.long 0x4 4. "SPB2DT,Serial Port Break Data Select" "0: When TINV is 0 low level is output in TXDn pin.,1: When TINV is 0 high level is output in TXDn pin." bitfld.long 0x4 1. "CTSPEN,CTS External Pin Enable" "0: Alternate setting to use CTS and RTS functions..,1: Dedicated setting for separately using CTS and.." newline bitfld.long 0x4 0. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled" line.long 0x8 "CCR2,Common Control Register 2" hexmask.long.byte 0x8 24.--31. 1. "MDDR,Modulation Duty Setting" bitfld.long 0x8 20.--21. "CKS,Clock Select" "0: TCLK clock (n = 0),1: TCLK/4 clock (n = 1),?,?" newline bitfld.long 0x8 16. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled,1: Bit rate modulation function is enabled" hexmask.long.byte 0x8 8.--15. 1. "BRR,Bit Rate Setting" newline bitfld.long 0x8 7. "ABCSE2,Asynchronous Mode Extended Base Clock Select 2" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 4 base clock cycles for 1-bit.." bitfld.long 0x8 6. "ABCSE,Asynchronous Mode Extended Base Clock Select" "0: Clock cycles for 1-bit period is determined by..,1: Baud rate is 6 base clock cycles for 1-bit.." newline bitfld.long 0x8 5. "ABCS,Asynchronous Mode Base Clock Select" "0: Selects 16 base clock cycles for 1-bit period,1: Selects 8 base clock cycles for 1-bit period" bitfld.long 0x8 4. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.long 0x8 0.--2. "BCP,Base Clock Pulse" "0: 93 clock cycles (S = 93),1: 128 clock cycles (S = 128),?,?,?,?,?,?" line.long 0xC "CCR3,Common Control Register 3" bitfld.long 0xC 29. "BLK,Block Transfer Mode" "0: Non-block transfer mode operation,1: Block transfer mode operation" bitfld.long 0xC 28. "GM,GSM Mode" "0: Non-GSM mode operation,1: GSM mode operation" newline bitfld.long 0xC 26. "ACS0,Asynchronous Mode Clock Source Select" "0: External clock input,1: Logical AND of compare matches output from the.." bitfld.long 0xC 24.--25. "CKE,Clock Enable" "0,1,2,3" newline bitfld.long 0xC 21. "DEN,Driver Enable" "0: RS-485 driver control function disabled,1: RS-485 driver control function enabled" bitfld.long 0xC 20. "FM,FIFO Mode Select" "0: TDR register and RDR register are non-FIFO..,1: TDR register and RDR register are FIFO buffer.." newline bitfld.long 0xC 19. "MP,Multi-Processor Mode" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" bitfld.long 0xC 16.--18. "MOD,Communication Mode Select" "0: Asynchronous mode (multi-processor mode),1: Smart card interface mode,?,?,?,?,?,?" newline bitfld.long 0xC 15. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.long 0xC 14. "STP,Stop Bit Length" "0: 1 stop bit/break delimiter length is 1-bit,1: 2 stop bits/break delimiter length is 2-bit" newline bitfld.long 0xC 13. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted to TSR as is. RSR..,1: TDR contents are inverted before being.." bitfld.long 0xC 12. "LSBF,LSB First select" "0: MSB-first,1: LSB-first" newline bitfld.long 0xC 8.--9. "CHR,Character Length" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 9-bit data length,?,?" bitfld.long 0xC 7. "BPEN,Synchronizer Bypass Enable" "0: Synchronizer circuit is not bypassed,1: Synchronizer circuit is bypassed" newline bitfld.long 0xC 1. "CPOL,Clock Polarity Select" "0: SCKn in idle state is 0,1: SCKn in idle state is 1" bitfld.long 0xC 0. "CPHA,Clock Phase Select" "0: Data is sampled at an odd edge and changes at an..,1: Data changes at an odd edge and is sampled at an.." line.long 0x10 "CCR4,Common Control Register 4" bitfld.long 0x10 31. "AET,Adjustment Edge for Transmit Timing" "0: When CCR1.TINV is 0 adjust the rising edge..,1: When CCR1.TINV is 0 adjust the falling edge.." bitfld.long 0x10 28.--30. "ATT,Adjustment Value for Transmit Timing" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "AJD,Adjustment Direction for Receive Sampling Timing" "0: The sampling timing is adjusted backward to the..,1: The sampling timing is adjusted forward to the.." bitfld.long 0x10 24.--26. "AST,Adjustment Value for Receive Sampling Timing" "0: Setting prohibited,1: 2-TCLK delay,?,?,?,?,?,?" newline bitfld.long 0x10 19. "SCKSEL,Master receive clock selection" "0: Master receive clock is disabled,1: Master receive clock is enabled" bitfld.long 0x10 17. "ATEN,Adjust Transmit Timing Enable" "0: Adjust transmit timing disabled,1: Adjust transmit timing enabled" newline bitfld.long 0x10 16. "ASEN,Adjust Receive Sampling Timing Enable" "0: Adjust sampling timing disabled,1: Adjust sampling timing enabled" hexmask.long.word 0x10 0.--8. 1. "CMPD,Compare Match Data" rgroup.byte 0x1C++0x0 line.byte 0x0 "CESR,Communication Enable Status Register" bitfld.byte 0x0 4. "TIST,TE Internal Status" "0: TE signal internal state value 0,1: TE signal internal state value 1" bitfld.byte 0x0 0. "RIST,RE Internal Status" "0: RE signal internal state value 0,1: RE signal internal state value 1" group.long 0x20++0x7 line.long 0x0 "ICR,Simple IIC Control Register" bitfld.long 0x0 22.--23. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition,?,?" bitfld.long 0x0 20.--21. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition,?,?" newline bitfld.long 0x0 18. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated" bitfld.long 0x0 17. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated,1: A restart condition is generated" newline bitfld.long 0x0 16. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated,1: A start condition is generated" bitfld.long 0x0 13. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.long 0x0 9. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" bitfld.long 0x0 8. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts" newline hexmask.long.byte 0x0 0.--4. 1. "IICDL,SDA Delay Output Select" line.long 0x4 "FCR,FIFO Control Register" hexmask.long.byte 0x4 24.--28. 1. "RSTRG,RTS Output Active Trigger Number Select" bitfld.long 0x4 23. "RFRST,Receive FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Receive-FIFO(RDR.." newline hexmask.long.byte 0x4 16.--20. 1. "RTRG,Receive FIFO Data Trigger Number" bitfld.long 0x4 15. "TFRST,Transmit FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Transmit-FIFO (TDR.." newline hexmask.long.byte 0x4 8.--12. 1. "TTRG,Transmit FIFO Data Trigger Number" bitfld.long 0x4 0. "DRES,Receive Data Ready Error Select Bit" "0: Reception data full interrupt (SCIn_RXI),1: Receive error interrupt (SCIn_ERI)" group.long 0x2C++0x13 line.long 0x0 "MCR,Manchester Control Register" bitfld.long 0x0 26. "SBEREN,Start Bit Error Enable" "0: Does not handle a start bit error as an..,1: Handles a start bit error as an interrupt source" bitfld.long 0x0 25. "SYEREN,Receive SYNC Error Enable" "0: Does not handle a receive SYNC error as an..,1: Handles a receive SYNC error as an interrupt.." newline bitfld.long 0x0 24. "PFEREN,Preface Error Enable" "0: Does not handle a preface error as an interrupt..,1: Handles a preface error as an interrupt source" bitfld.long 0x0 20.--21. "RPPAT,Receive Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 16.--19. 1. "RPLEN,Receive Preface Length" bitfld.long 0x0 12.--13. "TPPAT,Transmit Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "TPLEN,Transmit Preface Length" bitfld.long 0x0 6. "SBSEL,Start Bit Select" "0: The start bit area consists of one bit,1: The start bit area consists of three bits.." newline bitfld.long 0x0 5. "SYNSEL,SYNC Select" "0: The start bit pattern is set with the SYNVAL bit,1: The start bit pattern is set with the TSYNC bit" bitfld.long 0x0 4. "SYNVAL,SYNC value Setting" "0,1" newline bitfld.long 0x0 2. "ERTEN,Manchester Edge Retiming Enable" "0: Disables the receive retiming function,1: Enables the receive retiming function" bitfld.long 0x0 1. "TMPOL,Polarity of Transmit Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." newline bitfld.long 0x0 0. "RMPOL,Polarity of Received Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." line.long 0x4 "DCR,Driver Control Register" hexmask.long.byte 0x4 16.--20. 1. "DENGT,Driver Negate Time" hexmask.long.byte 0x4 8.--12. 1. "DEAST,Driver Assertion Time" newline bitfld.long 0x4 0. "DEPOL,Driver Effective Polarity Select" "0: The DEn signal is active-high,1: The DEn signal is active-low" line.long 0x8 "XCR0,Simple LIN Control Register 0" bitfld.long 0x8 24.--25. "BCCS,Bus Conflict Detection Clock Selection" "0: Base clock,1: Base clock/2,?,?" bitfld.long 0x8 22. "AEDIE,Active Edge Detection Interrupt Enable" "0: Active edge detection interrupt disabled,1: Active edge detection interrupt enabled" newline bitfld.long 0x8 21. "COFIE,Counter Overflow Interrupt Enable" "0: Counter overflow is not included in SCIn_ERI..,1: Counter overflow is included in SCIn_ERI.." bitfld.long 0x8 20. "BFDIE,Break Field Detection Interrupt Enable" "0: Break Field detection interrupt disabled,1: Break Field detection interrupt enabled" newline bitfld.long 0x8 17. "BCDIE,Bus Conflict Detection Interrupt Enable" "0: Bus conflict detection is not included in..,1: Bus conflict detection is included in SCIn_ERI.." bitfld.long 0x8 16. "BFOIE,Break Field Output Completion Interrupt Enable" "0: Break Field output completion is not included in..,1: Break Field output completion is included in.." newline bitfld.long 0x8 13.--15. "PIBS,Priority Interrupt Bit Select" "0: Bit 0 of Control Field 1,1: Bit 1 of Control Field 1,?,?,?,?,?,?" bitfld.long 0x8 12. "PIBE,Priority Interrupt Bit Enable" "0: Priority interrupt bit disabled,1: Priority interrupt bit enabled" newline bitfld.long 0x8 10.--11. "CF1DS,Control Field1 Compare Data Select" "0: Select XCR1.PCF1D[7:0] as the compare data,1: Select XCR1.SCF1D[7:0] as the compare data,?,?" bitfld.long 0x8 9. "CF0RE,Control Field 0 Enable" "0: No Control Field 0,1: With Control Field 0" newline bitfld.long 0x8 8. "BFE,Break Field Enable" "0: No Break Field,1: With Break Field" bitfld.long 0x8 0.--1. "TCSS,Timer Count Clock Source Selection" "?,1: TCLK/4,?,?" line.long 0xC "XCR1,Simple LIN Control Register 1" hexmask.long.byte 0xC 24.--31. 1. "CF1CE,Control Field 1 Compare Bit Enable" hexmask.long.byte 0xC 16.--23. 1. "SCF1D,Secondary Compare Data for Control Field 1" newline hexmask.long.byte 0xC 8.--15. 1. "PCF1D,Priority Compare Data for Control Field 1" bitfld.long 0xC 5. "BMEN,Bit Rate Measurement Enable" "0: Bit rate measurement disabled,1: Bit rate measurement enabled" newline bitfld.long 0xC 4. "SDST,Start Frame Detection Enable" "0: Start Frame/Break Field detection disabled,1: Start Frame/Break Field detection enabled" bitfld.long 0xC 0. "TCST,Break Field Output Timer Count Start Trigger" "0: Break Field output timer count stopped,1: Break Field output timer count start" line.long 0x10 "XCR2,Simple LIN Control Register 2" hexmask.long.word 0x10 16.--31. 1. "BFLW,Break Field Length Setting" hexmask.long.byte 0x10 8.--15. 1. "CF0CE,Control Field 0 Compare Bit Enable" newline hexmask.long.byte 0x10 0.--7. 1. "CF0D,Control Field 0 Compare Data" rgroup.long 0x48++0x1B line.long 0x0 "CSR,Common Status Register" bitfld.long 0x0 31. "RDRF,Receive Data Full Flag" "0: Non-FIFO selected (CCR3.FM = 0): No received..,1: Non-FIFO selected (CCR3.FM = 0): Received data.." bitfld.long 0x0 30. "TEND,Transmit End Flag" "0: A character is being transmitted or standing by..,1: Character transfer has been completed or sending.." newline bitfld.long 0x0 29. "TDRE,Transmit Data Empty Flag" "0: Non-FIFO selected (CCR3.FM = 0): Transmit data..,1: Non-FIFO selected (CCR3.FM = 0): No transmit.." bitfld.long 0x0 28. "FER,Framing Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No framing..,1: Non-FIFO selected (CCR3.FM = 0): A framing error.." newline bitfld.long 0x0 27. "PER,Parity Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No parity error..,1: Non-FIFO selected (CCR3.FM = 0): A parity error.." bitfld.long 0x0 26. "MFF,Mode Fault Error Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.long 0x0 24. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.long 0x0 18. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred at address match..,1: A framing error has occurred at address match.." newline bitfld.long 0x0 17. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred at address match..,1: A parity error has occurred at address match.." bitfld.long 0x0 16. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" newline bitfld.long 0x0 15. "RXDMON,Serial Input Data Monitor Bit" "0: When RINV is 0 RXDn pin is the low level. When..,1: When RINV is 0 RXDn pin is the high level. When.." bitfld.long 0x0 4. "ERS,Error Signal Status Flag" "0: Error signal low not responded,1: Error signal low responded" line.long 0x4 "ISR,Simple IIC Status Register" bitfld.long 0x4 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.long 0x4 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" line.long 0x8 "FRSR,FIFO Receive Status Register" hexmask.long.byte 0x8 24.--29. 1. "FNUM,Framing Error Count" hexmask.long.byte 0x8 16.--21. 1. "PNUM,Parity Error Count" newline hexmask.long.byte 0x8 8.--13. 1. "R,Receive-FIFO Data Count" bitfld.long 0x8 0. "DR,Receive Data Ready Flag" "0: Receiving is in progress or no received data..,1: The following receive data is not received for a.." line.long 0xC "FTSR,FIFO Transmit Status Register" hexmask.long.byte 0xC 0.--5. 1. "T,Transmit-FIFO Data Count" line.long 0x10 "MSR,Manchester Status Register" bitfld.long 0x10 6. "RSYNC,Receive SYNC Data Bit" "0: The received start bit is DATA SYNC,1: The received start bit is COMMAND SYNC" bitfld.long 0x10 4. "MER,Manchester Error Flag" "0: No Manchester error occurred,1: Manchester error has occurred" newline bitfld.long 0x10 2. "SBER,Start Bit Error Flag" "0: No start bit error detected,1: Start bit error detected" bitfld.long 0x10 1. "SYER,SYNC Error Flag" "0: No receive SYNC error detected,1: Receive SYNC error detected" newline bitfld.long 0x10 0. "PFER,Preface Error Flag" "0: No preface error detected,1: Preface error detected" line.long 0x14 "XSR0,Simple LIN Status Register 0" hexmask.long.byte 0x14 24.--31. 1. "CF1RD,Control Field 1 received data" hexmask.long.byte 0x14 16.--23. 1. "CF0RD,Control Field 0 received data" newline bitfld.long 0x14 15. "AEDF,Active Edge Detection Flag" "0: No valid edge detected,1: Detected a valid edge" bitfld.long 0x14 14. "COF,Counter Overflow Flag" "0: Break Field detection counter has not overflowed,1: Break Field detection counter overflowed" newline bitfld.long 0x14 13. "PIBDF,Priority Interrupt Bit Detection Flag" "0: Priority interrupt bit is not detected,1: Priority interrupt bit is detected" bitfld.long 0x14 12. "CF1MF,Control Field 1 Compare Match Flag" "0: Control Field 1 received data does not match the..,1: Control Field 1 received data matches the.." newline bitfld.long 0x14 11. "CF0MF,Control Field 0 Compare Match Flag" "0: Control Field 0 received data does not match the..,1: Control Field 0 received data matches the.." bitfld.long 0x14 10. "BFDF,Break Field Detection Flag" "0: Break Field is not detected,1: Break Field is detected" newline bitfld.long 0x14 9. "BCDF,Bus Conflict Detection Flag" "0: No bus collision detected,1: Detected a bus collision" bitfld.long 0x14 8. "BFOF,Break Field Output Completion Flag" "0: Break Field is being output or is not being output,1: Completed BF output" newline bitfld.long 0x14 1. "RXDSF,RXDn Input Status Flag" "0: RXDn input to SCI is enabled,1: RXDn input to SCI is disabled" bitfld.long 0x14 0. "SFSF,Start Frame Status Flag" "0: Start Frame detection disabled or Start Frame..,1: Before Start Frame detection or during detection" line.long 0x18 "XSR1,Simple LIN Status Register 1" hexmask.long.word 0x18 0.--15. 1. "TCNT,Timer Count Capture Value" wgroup.long 0x68++0x13 line.long 0x0 "CFCLR,Common Flag Clear Register" bitfld.long 0x0 31. "RDRFC,RDRF Clear Bit" "0,1" bitfld.long 0x0 29. "TDREC,TDRE Clear Bit" "0,1" newline bitfld.long 0x0 28. "FERC,FER Clear Bit" "0,1" bitfld.long 0x0 27. "PERC,PER Clear Bit" "0,1" newline bitfld.long 0x0 26. "MFFC,MFF Clear Bit" "0,1" bitfld.long 0x0 24. "ORERC,ORER Clear Bit" "0,1" newline bitfld.long 0x0 18. "DFERC,DFER Clear Bit" "0,1" bitfld.long 0x0 17. "DPERC,DPER Clear Bit" "0,1" newline bitfld.long 0x0 16. "DCMFC,DCMF Clear Bit" "0,1" bitfld.long 0x0 4. "ERSC,ERS Clear Bit" "0,1" line.long 0x4 "ICFCLR,Simple IIC Flag Clear Register" bitfld.long 0x4 3. "IICSTIFC,IICSTIF Clear Bit" "0,1" line.long 0x8 "FFCLR,FIFO Flag Clear Register" bitfld.long 0x8 0. "DRC,DR Clear Bit" "0,1" line.long 0xC "MFCLR,Manchester Flag Clear Register" bitfld.long 0xC 4. "MERC,MER Clear Bit" "0,1" bitfld.long 0xC 2. "SBERC,SBER Clear Bit" "0,1" newline bitfld.long 0xC 1. "SYERC,SYER Clear Bit" "0,1" bitfld.long 0xC 0. "PFERC,PFER Clear Bit" "0,1" line.long 0x10 "XFCLR,Simple LIN Flag Clear Register" bitfld.long 0x10 15. "AEDC,AEDF Clear Bit" "0,1" bitfld.long 0x10 14. "COFC,COFF Clear Bit" "0,1" newline bitfld.long 0x10 13. "PIBDC,PIBDF Clear Bit" "0,1" bitfld.long 0x10 12. "CF1MC,CF1MF Clear Bit" "0,1" newline bitfld.long 0x10 11. "CF0MC,CF0MF Clear Bit" "0,1" bitfld.long 0x10 10. "BFDC,BFDF Clear Bit" "0,1" newline bitfld.long 0x10 9. "BCDC,BCDF Clear Bit" "0,1" bitfld.long 0x10 8. "BFOC,BFOF Clear Bit" "0,1" tree.end tree "SCI0_B_NS" base ad:0x50358000 rgroup.long 0x0++0x3 line.long 0x0 "RDR,Receive Data Register" bitfld.long 0x0 28. "FER,Framing error flag" "0,1" bitfld.long 0x0 27. "PER,Parity error flag" "0,1" newline bitfld.long 0x0 24. "ORER,Overrun Error flag" "0,1" bitfld.long 0x0 12. "FFER,FIFO framing error flag" "0: There is no framing error in the data read from..,1: There is framing error in the data read from the.." newline bitfld.long 0x0 11. "FPER,FIFO parity error flag" "0: There is no parity error in the data read from..,1: There is parity error in the data read from the.." bitfld.long 0x0 10. "DR,Receive data ready flag" "0,1" newline bitfld.long 0x0 9. "MPB,Multi-processor flag" "0: Data transmission cycles,1: ID transmission cycles" hexmask.long.word 0x0 0.--8. 1. "RDAT,Serial receive data" rgroup.byte 0x0++0x0 line.byte 0x0 "RDR_BY,Receive Data Register" bitfld.byte 0x0 4. "FER,Framing error flag" "0,1" bitfld.byte 0x0 3. "PER,Parity error flag" "0,1" newline bitfld.byte 0x0 0. "ORER,Overrun Error flag" "0,1" group.long 0x4++0x3 line.long 0x0 "TDR,Transmit Data Register" bitfld.long 0x0 12. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.long 0x0 9. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline hexmask.long.word 0x0 0.--8. 1. "TDAT,Serial transmit data" group.byte 0x4++0x1 line.byte 0x0 "TDRLL,Transmit Data Register" line.byte 0x1 "TDRLH,Transmit Data Register" bitfld.byte 0x1 4. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.byte 0x1 1. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline bitfld.byte 0x1 0. "TDAT,Serial transmit data" "0,1" group.long 0x8++0x13 line.long 0x0 "CCR0,Common Control Register 0" bitfld.long 0x0 24. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled,1: SSn pin function is enabled" bitfld.long 0x0 21. "TEIE,Transmit End Interrupt Enable" "0: SCIn_TEI interrupt request is disabled,1: SCIn_TEI interrupt request is enabled" newline bitfld.long 0x0 20. "TIE,Transmit Interrupt Enable" "0: SCIn_TXI interrupt request is disabled,1: SCIn_TXI interrupt request is enabled" bitfld.long 0x0 16. "RIE,Receive Interrupt Enable" "0: SCIn_RXI and SCIn_ERI interrupt requests are..,1: SCIn_RXI and SCIn_ERI interrupt requests are.." newline bitfld.long 0x0 10. "IDSEL,ID Frame Select" "0: Compare data irrespective of the value of the..,1: Compare data only when the MPB bit is 1 (ID frame)" bitfld.long 0x0 9. "DCME,Data Compare Match Enable" "0: Address match function is disabled,1: Address match function is enabled" newline bitfld.long 0x0 8. "MPIE,Multi-Processor Interrupt Enable" "0: Non-multi-processor reception,1: Multi-processor reception When the data with the.." bitfld.long 0x0 4. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" newline bitfld.long 0x0 0. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" line.long 0x4 "CCR1,Common Control Register 1" bitfld.long 0x4 29. "NFM,Noise Filter Mode" "0: 3-point matching mode,1: Majority vote mode" bitfld.long 0x4 28. "NFEN,Digital Noise Filter Function Enable" "0: In Asynchronous Manchester Simple LIN modes:..,1: In Asynchronous Manchester Simple LIN modes:.." newline bitfld.long 0x4 24.--26. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: The on-chip baud rate generator source clock..,?,?,?,?,?,?" bitfld.long 0x4 20. "SHARPS,Half-Duplex Communication Select" "0: TXDn pin RXDn pin independent,1: TXDn/RXDn pin combination use (half-duplex.." newline bitfld.long 0x4 16. "SPLP,Loopback Control" "0: Normal mode,1: Loopback mode" bitfld.long 0x4 13. "RINV,RXD Invert" "0: Received data from RXDn is not inverted and input,1: Received data from RXDn is inverted and input" newline bitfld.long 0x4 12. "TINV,TXD Invert" "0: Transmit data is not inverted and output to TXDn,1: Transmit data is inverted and output to TXDn" bitfld.long 0x4 9. "PM,Parity Mode" "0: Selects even parity,1: Selects odd parity" newline bitfld.long 0x4 8. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.." bitfld.long 0x4 5. "SPB2IO,Serial Port Break I/O" "0: The value of SPB2DT bit is not output in TXDn pin,1: The value of SPB2DT bit is output in TXDn pin" newline bitfld.long 0x4 4. "SPB2DT,Serial Port Break Data Select" "0: When TINV is 0 low level is output in TXDn pin.,1: When TINV is 0 high level is output in TXDn pin." bitfld.long 0x4 1. "CTSPEN,CTS External Pin Enable" "0: Alternate setting to use CTS and RTS functions..,1: Dedicated setting for separately using CTS and.." newline bitfld.long 0x4 0. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled" line.long 0x8 "CCR2,Common Control Register 2" hexmask.long.byte 0x8 24.--31. 1. "MDDR,Modulation Duty Setting" bitfld.long 0x8 20.--21. "CKS,Clock Select" "0: TCLK clock (n = 0),1: TCLK/4 clock (n = 1),?,?" newline bitfld.long 0x8 16. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled,1: Bit rate modulation function is enabled" hexmask.long.byte 0x8 8.--15. 1. "BRR,Bit Rate Setting" newline bitfld.long 0x8 7. "ABCSE2,Asynchronous Mode Extended Base Clock Select 2" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 4 base clock cycles for 1-bit.." bitfld.long 0x8 6. "ABCSE,Asynchronous Mode Extended Base Clock Select" "0: Clock cycles for 1-bit period is determined by..,1: Baud rate is 6 base clock cycles for 1-bit.." newline bitfld.long 0x8 5. "ABCS,Asynchronous Mode Base Clock Select" "0: Selects 16 base clock cycles for 1-bit period,1: Selects 8 base clock cycles for 1-bit period" bitfld.long 0x8 4. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.long 0x8 0.--2. "BCP,Base Clock Pulse" "0: 93 clock cycles (S = 93),1: 128 clock cycles (S = 128),?,?,?,?,?,?" line.long 0xC "CCR3,Common Control Register 3" bitfld.long 0xC 29. "BLK,Block Transfer Mode" "0: Non-block transfer mode operation,1: Block transfer mode operation" bitfld.long 0xC 28. "GM,GSM Mode" "0: Non-GSM mode operation,1: GSM mode operation" newline bitfld.long 0xC 26. "ACS0,Asynchronous Mode Clock Source Select" "0: External clock input,1: Logical AND of compare matches output from the.." bitfld.long 0xC 24.--25. "CKE,Clock Enable" "0,1,2,3" newline bitfld.long 0xC 21. "DEN,Driver Enable" "0: RS-485 driver control function disabled,1: RS-485 driver control function enabled" bitfld.long 0xC 20. "FM,FIFO Mode Select" "0: TDR register and RDR register are non-FIFO..,1: TDR register and RDR register are FIFO buffer.." newline bitfld.long 0xC 19. "MP,Multi-Processor Mode" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" bitfld.long 0xC 16.--18. "MOD,Communication Mode Select" "0: Asynchronous mode (multi-processor mode),1: Smart card interface mode,?,?,?,?,?,?" newline bitfld.long 0xC 15. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.long 0xC 14. "STP,Stop Bit Length" "0: 1 stop bit/break delimiter length is 1-bit,1: 2 stop bits/break delimiter length is 2-bit" newline bitfld.long 0xC 13. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted to TSR as is. RSR..,1: TDR contents are inverted before being.." bitfld.long 0xC 12. "LSBF,LSB First select" "0: MSB-first,1: LSB-first" newline bitfld.long 0xC 8.--9. "CHR,Character Length" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 9-bit data length,?,?" bitfld.long 0xC 7. "BPEN,Synchronizer Bypass Enable" "0: Synchronizer circuit is not bypassed,1: Synchronizer circuit is bypassed" newline bitfld.long 0xC 1. "CPOL,Clock Polarity Select" "0: SCKn in idle state is 0,1: SCKn in idle state is 1" bitfld.long 0xC 0. "CPHA,Clock Phase Select" "0: Data is sampled at an odd edge and changes at an..,1: Data changes at an odd edge and is sampled at an.." line.long 0x10 "CCR4,Common Control Register 4" bitfld.long 0x10 31. "AET,Adjustment Edge for Transmit Timing" "0: When CCR1.TINV is 0 adjust the rising edge..,1: When CCR1.TINV is 0 adjust the falling edge.." bitfld.long 0x10 28.--30. "ATT,Adjustment Value for Transmit Timing" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "AJD,Adjustment Direction for Receive Sampling Timing" "0: The sampling timing is adjusted backward to the..,1: The sampling timing is adjusted forward to the.." bitfld.long 0x10 24.--26. "AST,Adjustment Value for Receive Sampling Timing" "0: Setting prohibited,1: 2-TCLK delay,?,?,?,?,?,?" newline bitfld.long 0x10 19. "SCKSEL,Master receive clock selection" "0: Master receive clock is disabled,1: Master receive clock is enabled" bitfld.long 0x10 17. "ATEN,Adjust Transmit Timing Enable" "0: Adjust transmit timing disabled,1: Adjust transmit timing enabled" newline bitfld.long 0x10 16. "ASEN,Adjust Receive Sampling Timing Enable" "0: Adjust sampling timing disabled,1: Adjust sampling timing enabled" hexmask.long.word 0x10 0.--8. 1. "CMPD,Compare Match Data" rgroup.byte 0x1C++0x0 line.byte 0x0 "CESR,Communication Enable Status Register" bitfld.byte 0x0 4. "TIST,TE Internal Status" "0: TE signal internal state value 0,1: TE signal internal state value 1" bitfld.byte 0x0 0. "RIST,RE Internal Status" "0: RE signal internal state value 0,1: RE signal internal state value 1" group.long 0x20++0x7 line.long 0x0 "ICR,Simple IIC Control Register" bitfld.long 0x0 22.--23. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition,?,?" bitfld.long 0x0 20.--21. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition,?,?" newline bitfld.long 0x0 18. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated" bitfld.long 0x0 17. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated,1: A restart condition is generated" newline bitfld.long 0x0 16. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated,1: A start condition is generated" bitfld.long 0x0 13. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.long 0x0 9. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" bitfld.long 0x0 8. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts" newline hexmask.long.byte 0x0 0.--4. 1. "IICDL,SDA Delay Output Select" line.long 0x4 "FCR,FIFO Control Register" hexmask.long.byte 0x4 24.--28. 1. "RSTRG,RTS Output Active Trigger Number Select" bitfld.long 0x4 23. "RFRST,Receive FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Receive-FIFO(RDR.." newline hexmask.long.byte 0x4 16.--20. 1. "RTRG,Receive FIFO Data Trigger Number" bitfld.long 0x4 15. "TFRST,Transmit FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Transmit-FIFO (TDR.." newline hexmask.long.byte 0x4 8.--12. 1. "TTRG,Transmit FIFO Data Trigger Number" bitfld.long 0x4 0. "DRES,Receive Data Ready Error Select Bit" "0: Reception data full interrupt (SCIn_RXI),1: Receive error interrupt (SCIn_ERI)" group.long 0x2C++0x13 line.long 0x0 "MCR,Manchester Control Register" bitfld.long 0x0 26. "SBEREN,Start Bit Error Enable" "0: Does not handle a start bit error as an..,1: Handles a start bit error as an interrupt source" bitfld.long 0x0 25. "SYEREN,Receive SYNC Error Enable" "0: Does not handle a receive SYNC error as an..,1: Handles a receive SYNC error as an interrupt.." newline bitfld.long 0x0 24. "PFEREN,Preface Error Enable" "0: Does not handle a preface error as an interrupt..,1: Handles a preface error as an interrupt source" bitfld.long 0x0 20.--21. "RPPAT,Receive Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 16.--19. 1. "RPLEN,Receive Preface Length" bitfld.long 0x0 12.--13. "TPPAT,Transmit Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "TPLEN,Transmit Preface Length" bitfld.long 0x0 6. "SBSEL,Start Bit Select" "0: The start bit area consists of one bit,1: The start bit area consists of three bits.." newline bitfld.long 0x0 5. "SYNSEL,SYNC Select" "0: The start bit pattern is set with the SYNVAL bit,1: The start bit pattern is set with the TSYNC bit" bitfld.long 0x0 4. "SYNVAL,SYNC value Setting" "0,1" newline bitfld.long 0x0 2. "ERTEN,Manchester Edge Retiming Enable" "0: Disables the receive retiming function,1: Enables the receive retiming function" bitfld.long 0x0 1. "TMPOL,Polarity of Transmit Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." newline bitfld.long 0x0 0. "RMPOL,Polarity of Received Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." line.long 0x4 "DCR,Driver Control Register" hexmask.long.byte 0x4 16.--20. 1. "DENGT,Driver Negate Time" hexmask.long.byte 0x4 8.--12. 1. "DEAST,Driver Assertion Time" newline bitfld.long 0x4 0. "DEPOL,Driver Effective Polarity Select" "0: The DEn signal is active-high,1: The DEn signal is active-low" line.long 0x8 "XCR0,Simple LIN Control Register 0" bitfld.long 0x8 24.--25. "BCCS,Bus Conflict Detection Clock Selection" "0: Base clock,1: Base clock/2,?,?" bitfld.long 0x8 22. "AEDIE,Active Edge Detection Interrupt Enable" "0: Active edge detection interrupt disabled,1: Active edge detection interrupt enabled" newline bitfld.long 0x8 21. "COFIE,Counter Overflow Interrupt Enable" "0: Counter overflow is not included in SCIn_ERI..,1: Counter overflow is included in SCIn_ERI.." bitfld.long 0x8 20. "BFDIE,Break Field Detection Interrupt Enable" "0: Break Field detection interrupt disabled,1: Break Field detection interrupt enabled" newline bitfld.long 0x8 17. "BCDIE,Bus Conflict Detection Interrupt Enable" "0: Bus conflict detection is not included in..,1: Bus conflict detection is included in SCIn_ERI.." bitfld.long 0x8 16. "BFOIE,Break Field Output Completion Interrupt Enable" "0: Break Field output completion is not included in..,1: Break Field output completion is included in.." newline bitfld.long 0x8 13.--15. "PIBS,Priority Interrupt Bit Select" "0: Bit 0 of Control Field 1,1: Bit 1 of Control Field 1,?,?,?,?,?,?" bitfld.long 0x8 12. "PIBE,Priority Interrupt Bit Enable" "0: Priority interrupt bit disabled,1: Priority interrupt bit enabled" newline bitfld.long 0x8 10.--11. "CF1DS,Control Field1 Compare Data Select" "0: Select XCR1.PCF1D[7:0] as the compare data,1: Select XCR1.SCF1D[7:0] as the compare data,?,?" bitfld.long 0x8 9. "CF0RE,Control Field 0 Enable" "0: No Control Field 0,1: With Control Field 0" newline bitfld.long 0x8 8. "BFE,Break Field Enable" "0: No Break Field,1: With Break Field" bitfld.long 0x8 0.--1. "TCSS,Timer Count Clock Source Selection" "?,1: TCLK/4,?,?" line.long 0xC "XCR1,Simple LIN Control Register 1" hexmask.long.byte 0xC 24.--31. 1. "CF1CE,Control Field 1 Compare Bit Enable" hexmask.long.byte 0xC 16.--23. 1. "SCF1D,Secondary Compare Data for Control Field 1" newline hexmask.long.byte 0xC 8.--15. 1. "PCF1D,Priority Compare Data for Control Field 1" bitfld.long 0xC 5. "BMEN,Bit Rate Measurement Enable" "0: Bit rate measurement disabled,1: Bit rate measurement enabled" newline bitfld.long 0xC 4. "SDST,Start Frame Detection Enable" "0: Start Frame/Break Field detection disabled,1: Start Frame/Break Field detection enabled" bitfld.long 0xC 0. "TCST,Break Field Output Timer Count Start Trigger" "0: Break Field output timer count stopped,1: Break Field output timer count start" line.long 0x10 "XCR2,Simple LIN Control Register 2" hexmask.long.word 0x10 16.--31. 1. "BFLW,Break Field Length Setting" hexmask.long.byte 0x10 8.--15. 1. "CF0CE,Control Field 0 Compare Bit Enable" newline hexmask.long.byte 0x10 0.--7. 1. "CF0D,Control Field 0 Compare Data" rgroup.long 0x48++0x1B line.long 0x0 "CSR,Common Status Register" bitfld.long 0x0 31. "RDRF,Receive Data Full Flag" "0: Non-FIFO selected (CCR3.FM = 0): No received..,1: Non-FIFO selected (CCR3.FM = 0): Received data.." bitfld.long 0x0 30. "TEND,Transmit End Flag" "0: A character is being transmitted or standing by..,1: Character transfer has been completed or sending.." newline bitfld.long 0x0 29. "TDRE,Transmit Data Empty Flag" "0: Non-FIFO selected (CCR3.FM = 0): Transmit data..,1: Non-FIFO selected (CCR3.FM = 0): No transmit.." bitfld.long 0x0 28. "FER,Framing Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No framing..,1: Non-FIFO selected (CCR3.FM = 0): A framing error.." newline bitfld.long 0x0 27. "PER,Parity Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No parity error..,1: Non-FIFO selected (CCR3.FM = 0): A parity error.." bitfld.long 0x0 26. "MFF,Mode Fault Error Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.long 0x0 24. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.long 0x0 18. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred at address match..,1: A framing error has occurred at address match.." newline bitfld.long 0x0 17. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred at address match..,1: A parity error has occurred at address match.." bitfld.long 0x0 16. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" newline bitfld.long 0x0 15. "RXDMON,Serial Input Data Monitor Bit" "0: When RINV is 0 RXDn pin is the low level. When..,1: When RINV is 0 RXDn pin is the high level. When.." bitfld.long 0x0 4. "ERS,Error Signal Status Flag" "0: Error signal low not responded,1: Error signal low responded" line.long 0x4 "ISR,Simple IIC Status Register" bitfld.long 0x4 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.long 0x4 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" line.long 0x8 "FRSR,FIFO Receive Status Register" hexmask.long.byte 0x8 24.--29. 1. "FNUM,Framing Error Count" hexmask.long.byte 0x8 16.--21. 1. "PNUM,Parity Error Count" newline hexmask.long.byte 0x8 8.--13. 1. "R,Receive-FIFO Data Count" bitfld.long 0x8 0. "DR,Receive Data Ready Flag" "0: Receiving is in progress or no received data..,1: The following receive data is not received for a.." line.long 0xC "FTSR,FIFO Transmit Status Register" hexmask.long.byte 0xC 0.--5. 1. "T,Transmit-FIFO Data Count" line.long 0x10 "MSR,Manchester Status Register" bitfld.long 0x10 6. "RSYNC,Receive SYNC Data Bit" "0: The received start bit is DATA SYNC,1: The received start bit is COMMAND SYNC" bitfld.long 0x10 4. "MER,Manchester Error Flag" "0: No Manchester error occurred,1: Manchester error has occurred" newline bitfld.long 0x10 2. "SBER,Start Bit Error Flag" "0: No start bit error detected,1: Start bit error detected" bitfld.long 0x10 1. "SYER,SYNC Error Flag" "0: No receive SYNC error detected,1: Receive SYNC error detected" newline bitfld.long 0x10 0. "PFER,Preface Error Flag" "0: No preface error detected,1: Preface error detected" line.long 0x14 "XSR0,Simple LIN Status Register 0" hexmask.long.byte 0x14 24.--31. 1. "CF1RD,Control Field 1 received data" hexmask.long.byte 0x14 16.--23. 1. "CF0RD,Control Field 0 received data" newline bitfld.long 0x14 15. "AEDF,Active Edge Detection Flag" "0: No valid edge detected,1: Detected a valid edge" bitfld.long 0x14 14. "COF,Counter Overflow Flag" "0: Break Field detection counter has not overflowed,1: Break Field detection counter overflowed" newline bitfld.long 0x14 13. "PIBDF,Priority Interrupt Bit Detection Flag" "0: Priority interrupt bit is not detected,1: Priority interrupt bit is detected" bitfld.long 0x14 12. "CF1MF,Control Field 1 Compare Match Flag" "0: Control Field 1 received data does not match the..,1: Control Field 1 received data matches the.." newline bitfld.long 0x14 11. "CF0MF,Control Field 0 Compare Match Flag" "0: Control Field 0 received data does not match the..,1: Control Field 0 received data matches the.." bitfld.long 0x14 10. "BFDF,Break Field Detection Flag" "0: Break Field is not detected,1: Break Field is detected" newline bitfld.long 0x14 9. "BCDF,Bus Conflict Detection Flag" "0: No bus collision detected,1: Detected a bus collision" bitfld.long 0x14 8. "BFOF,Break Field Output Completion Flag" "0: Break Field is being output or is not being output,1: Completed BF output" newline bitfld.long 0x14 1. "RXDSF,RXDn Input Status Flag" "0: RXDn input to SCI is enabled,1: RXDn input to SCI is disabled" bitfld.long 0x14 0. "SFSF,Start Frame Status Flag" "0: Start Frame detection disabled or Start Frame..,1: Before Start Frame detection or during detection" line.long 0x18 "XSR1,Simple LIN Status Register 1" hexmask.long.word 0x18 0.--15. 1. "TCNT,Timer Count Capture Value" wgroup.long 0x68++0x13 line.long 0x0 "CFCLR,Common Flag Clear Register" bitfld.long 0x0 31. "RDRFC,RDRF Clear Bit" "0,1" bitfld.long 0x0 29. "TDREC,TDRE Clear Bit" "0,1" newline bitfld.long 0x0 28. "FERC,FER Clear Bit" "0,1" bitfld.long 0x0 27. "PERC,PER Clear Bit" "0,1" newline bitfld.long 0x0 26. "MFFC,MFF Clear Bit" "0,1" bitfld.long 0x0 24. "ORERC,ORER Clear Bit" "0,1" newline bitfld.long 0x0 18. "DFERC,DFER Clear Bit" "0,1" bitfld.long 0x0 17. "DPERC,DPER Clear Bit" "0,1" newline bitfld.long 0x0 16. "DCMFC,DCMF Clear Bit" "0,1" bitfld.long 0x0 4. "ERSC,ERS Clear Bit" "0,1" line.long 0x4 "ICFCLR,Simple IIC Flag Clear Register" bitfld.long 0x4 3. "IICSTIFC,IICSTIF Clear Bit" "0,1" line.long 0x8 "FFCLR,FIFO Flag Clear Register" bitfld.long 0x8 0. "DRC,DR Clear Bit" "0,1" line.long 0xC "MFCLR,Manchester Flag Clear Register" bitfld.long 0xC 4. "MERC,MER Clear Bit" "0,1" bitfld.long 0xC 2. "SBERC,SBER Clear Bit" "0,1" newline bitfld.long 0xC 1. "SYERC,SYER Clear Bit" "0,1" bitfld.long 0xC 0. "PFERC,PFER Clear Bit" "0,1" line.long 0x10 "XFCLR,Simple LIN Flag Clear Register" bitfld.long 0x10 15. "AEDC,AEDF Clear Bit" "0,1" bitfld.long 0x10 14. "COFC,COFF Clear Bit" "0,1" newline bitfld.long 0x10 13. "PIBDC,PIBDF Clear Bit" "0,1" bitfld.long 0x10 12. "CF1MC,CF1MF Clear Bit" "0,1" newline bitfld.long 0x10 11. "CF0MC,CF0MF Clear Bit" "0,1" bitfld.long 0x10 10. "BFDC,BFDF Clear Bit" "0,1" newline bitfld.long 0x10 9. "BCDC,BCDF Clear Bit" "0,1" bitfld.long 0x10 8. "BFOC,BFOF Clear Bit" "0,1" tree.end tree "SCI1_B" base ad:0x40358100 rgroup.long 0x0++0x3 line.long 0x0 "RDR,Receive Data Register" bitfld.long 0x0 28. "FER,Framing error flag" "0,1" bitfld.long 0x0 27. "PER,Parity error flag" "0,1" newline bitfld.long 0x0 24. "ORER,Overrun Error flag" "0,1" bitfld.long 0x0 12. "FFER,FIFO framing error flag" "0: There is no framing error in the data read from..,1: There is framing error in the data read from the.." newline bitfld.long 0x0 11. "FPER,FIFO parity error flag" "0: There is no parity error in the data read from..,1: There is parity error in the data read from the.." bitfld.long 0x0 10. "DR,Receive data ready flag" "0,1" newline bitfld.long 0x0 9. "MPB,Multi-processor flag" "0: Data transmission cycles,1: ID transmission cycles" hexmask.long.word 0x0 0.--8. 1. "RDAT,Serial receive data" rgroup.byte 0x0++0x0 line.byte 0x0 "RDR_BY,Receive Data Register" bitfld.byte 0x0 4. "FER,Framing error flag" "0,1" bitfld.byte 0x0 3. "PER,Parity error flag" "0,1" newline bitfld.byte 0x0 0. "ORER,Overrun Error flag" "0,1" group.long 0x4++0x3 line.long 0x0 "TDR,Transmit Data Register" bitfld.long 0x0 12. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.long 0x0 9. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline hexmask.long.word 0x0 0.--8. 1. "TDAT,Serial transmit data" group.byte 0x4++0x1 line.byte 0x0 "TDRLL,Transmit Data Register" line.byte 0x1 "TDRLH,Transmit Data Register" bitfld.byte 0x1 4. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.byte 0x1 1. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline bitfld.byte 0x1 0. "TDAT,Serial transmit data" "0,1" group.long 0x8++0x13 line.long 0x0 "CCR0,Common Control Register 0" bitfld.long 0x0 24. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled,1: SSn pin function is enabled" bitfld.long 0x0 21. "TEIE,Transmit End Interrupt Enable" "0: SCIn_TEI interrupt request is disabled,1: SCIn_TEI interrupt request is enabled" newline bitfld.long 0x0 20. "TIE,Transmit Interrupt Enable" "0: SCIn_TXI interrupt request is disabled,1: SCIn_TXI interrupt request is enabled" bitfld.long 0x0 16. "RIE,Receive Interrupt Enable" "0: SCIn_RXI and SCIn_ERI interrupt requests are..,1: SCIn_RXI and SCIn_ERI interrupt requests are.." newline bitfld.long 0x0 10. "IDSEL,ID Frame Select" "0: Compare data irrespective of the value of the..,1: Compare data only when the MPB bit is 1 (ID frame)" bitfld.long 0x0 9. "DCME,Data Compare Match Enable" "0: Address match function is disabled,1: Address match function is enabled" newline bitfld.long 0x0 8. "MPIE,Multi-Processor Interrupt Enable" "0: Non-multi-processor reception,1: Multi-processor reception When the data with the.." bitfld.long 0x0 4. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" newline bitfld.long 0x0 0. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" line.long 0x4 "CCR1,Common Control Register 1" bitfld.long 0x4 29. "NFM,Noise Filter Mode" "0: 3-point matching mode,1: Majority vote mode" bitfld.long 0x4 28. "NFEN,Digital Noise Filter Function Enable" "0: In Asynchronous Manchester Simple LIN modes:..,1: In Asynchronous Manchester Simple LIN modes:.." newline bitfld.long 0x4 24.--26. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: The on-chip baud rate generator source clock..,?,?,?,?,?,?" bitfld.long 0x4 20. "SHARPS,Half-Duplex Communication Select" "0: TXDn pin RXDn pin independent,1: TXDn/RXDn pin combination use (half-duplex.." newline bitfld.long 0x4 16. "SPLP,Loopback Control" "0: Normal mode,1: Loopback mode" bitfld.long 0x4 13. "RINV,RXD Invert" "0: Received data from RXDn is not inverted and input,1: Received data from RXDn is inverted and input" newline bitfld.long 0x4 12. "TINV,TXD Invert" "0: Transmit data is not inverted and output to TXDn,1: Transmit data is inverted and output to TXDn" bitfld.long 0x4 9. "PM,Parity Mode" "0: Selects even parity,1: Selects odd parity" newline bitfld.long 0x4 8. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.." bitfld.long 0x4 5. "SPB2IO,Serial Port Break I/O" "0: The value of SPB2DT bit is not output in TXDn pin,1: The value of SPB2DT bit is output in TXDn pin" newline bitfld.long 0x4 4. "SPB2DT,Serial Port Break Data Select" "0: When TINV is 0 low level is output in TXDn pin.,1: When TINV is 0 high level is output in TXDn pin." bitfld.long 0x4 1. "CTSPEN,CTS External Pin Enable" "0: Alternate setting to use CTS and RTS functions..,1: Dedicated setting for separately using CTS and.." newline bitfld.long 0x4 0. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled" line.long 0x8 "CCR2,Common Control Register 2" hexmask.long.byte 0x8 24.--31. 1. "MDDR,Modulation Duty Setting" bitfld.long 0x8 20.--21. "CKS,Clock Select" "0: TCLK clock (n = 0),1: TCLK/4 clock (n = 1),?,?" newline bitfld.long 0x8 16. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled,1: Bit rate modulation function is enabled" hexmask.long.byte 0x8 8.--15. 1. "BRR,Bit Rate Setting" newline bitfld.long 0x8 7. "ABCSE2,Asynchronous Mode Extended Base Clock Select 2" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 4 base clock cycles for 1-bit.." bitfld.long 0x8 6. "ABCSE,Asynchronous Mode Extended Base Clock Select" "0: Clock cycles for 1-bit period is determined by..,1: Baud rate is 6 base clock cycles for 1-bit.." newline bitfld.long 0x8 5. "ABCS,Asynchronous Mode Base Clock Select" "0: Selects 16 base clock cycles for 1-bit period,1: Selects 8 base clock cycles for 1-bit period" bitfld.long 0x8 4. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.long 0x8 0.--2. "BCP,Base Clock Pulse" "0: 93 clock cycles (S = 93),1: 128 clock cycles (S = 128),?,?,?,?,?,?" line.long 0xC "CCR3,Common Control Register 3" bitfld.long 0xC 29. "BLK,Block Transfer Mode" "0: Non-block transfer mode operation,1: Block transfer mode operation" bitfld.long 0xC 28. "GM,GSM Mode" "0: Non-GSM mode operation,1: GSM mode operation" newline bitfld.long 0xC 26. "ACS0,Asynchronous Mode Clock Source Select" "0: External clock input,1: Logical AND of compare matches output from the.." bitfld.long 0xC 24.--25. "CKE,Clock Enable" "0,1,2,3" newline bitfld.long 0xC 21. "DEN,Driver Enable" "0: RS-485 driver control function disabled,1: RS-485 driver control function enabled" bitfld.long 0xC 20. "FM,FIFO Mode Select" "0: TDR register and RDR register are non-FIFO..,1: TDR register and RDR register are FIFO buffer.." newline bitfld.long 0xC 19. "MP,Multi-Processor Mode" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" bitfld.long 0xC 16.--18. "MOD,Communication Mode Select" "0: Asynchronous mode (multi-processor mode),1: Smart card interface mode,?,?,?,?,?,?" newline bitfld.long 0xC 15. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.long 0xC 14. "STP,Stop Bit Length" "0: 1 stop bit/break delimiter length is 1-bit,1: 2 stop bits/break delimiter length is 2-bit" newline bitfld.long 0xC 13. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted to TSR as is. RSR..,1: TDR contents are inverted before being.." bitfld.long 0xC 12. "LSBF,LSB First select" "0: MSB-first,1: LSB-first" newline bitfld.long 0xC 8.--9. "CHR,Character Length" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 9-bit data length,?,?" bitfld.long 0xC 7. "BPEN,Synchronizer Bypass Enable" "0: Synchronizer circuit is not bypassed,1: Synchronizer circuit is bypassed" newline bitfld.long 0xC 1. "CPOL,Clock Polarity Select" "0: SCKn in idle state is 0,1: SCKn in idle state is 1" bitfld.long 0xC 0. "CPHA,Clock Phase Select" "0: Data is sampled at an odd edge and changes at an..,1: Data changes at an odd edge and is sampled at an.." line.long 0x10 "CCR4,Common Control Register 4" bitfld.long 0x10 31. "AET,Adjustment Edge for Transmit Timing" "0: When CCR1.TINV is 0 adjust the rising edge..,1: When CCR1.TINV is 0 adjust the falling edge.." bitfld.long 0x10 28.--30. "ATT,Adjustment Value for Transmit Timing" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "AJD,Adjustment Direction for Receive Sampling Timing" "0: The sampling timing is adjusted backward to the..,1: The sampling timing is adjusted forward to the.." bitfld.long 0x10 24.--26. "AST,Adjustment Value for Receive Sampling Timing" "0: Setting prohibited,1: 2-TCLK delay,?,?,?,?,?,?" newline bitfld.long 0x10 19. "SCKSEL,Master receive clock selection" "0: Master receive clock is disabled,1: Master receive clock is enabled" bitfld.long 0x10 17. "ATEN,Adjust Transmit Timing Enable" "0: Adjust transmit timing disabled,1: Adjust transmit timing enabled" newline bitfld.long 0x10 16. "ASEN,Adjust Receive Sampling Timing Enable" "0: Adjust sampling timing disabled,1: Adjust sampling timing enabled" hexmask.long.word 0x10 0.--8. 1. "CMPD,Compare Match Data" rgroup.byte 0x1C++0x0 line.byte 0x0 "CESR,Communication Enable Status Register" bitfld.byte 0x0 4. "TIST,TE Internal Status" "0: TE signal internal state value 0,1: TE signal internal state value 1" bitfld.byte 0x0 0. "RIST,RE Internal Status" "0: RE signal internal state value 0,1: RE signal internal state value 1" group.long 0x20++0x7 line.long 0x0 "ICR,Simple IIC Control Register" bitfld.long 0x0 22.--23. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition,?,?" bitfld.long 0x0 20.--21. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition,?,?" newline bitfld.long 0x0 18. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated" bitfld.long 0x0 17. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated,1: A restart condition is generated" newline bitfld.long 0x0 16. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated,1: A start condition is generated" bitfld.long 0x0 13. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.long 0x0 9. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" bitfld.long 0x0 8. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts" newline hexmask.long.byte 0x0 0.--4. 1. "IICDL,SDA Delay Output Select" line.long 0x4 "FCR,FIFO Control Register" hexmask.long.byte 0x4 24.--28. 1. "RSTRG,RTS Output Active Trigger Number Select" bitfld.long 0x4 23. "RFRST,Receive FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Receive-FIFO(RDR.." newline hexmask.long.byte 0x4 16.--20. 1. "RTRG,Receive FIFO Data Trigger Number" bitfld.long 0x4 15. "TFRST,Transmit FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Transmit-FIFO (TDR.." newline hexmask.long.byte 0x4 8.--12. 1. "TTRG,Transmit FIFO Data Trigger Number" bitfld.long 0x4 0. "DRES,Receive Data Ready Error Select Bit" "0: Reception data full interrupt (SCIn_RXI),1: Receive error interrupt (SCIn_ERI)" group.long 0x2C++0x13 line.long 0x0 "MCR,Manchester Control Register" bitfld.long 0x0 26. "SBEREN,Start Bit Error Enable" "0: Does not handle a start bit error as an..,1: Handles a start bit error as an interrupt source" bitfld.long 0x0 25. "SYEREN,Receive SYNC Error Enable" "0: Does not handle a receive SYNC error as an..,1: Handles a receive SYNC error as an interrupt.." newline bitfld.long 0x0 24. "PFEREN,Preface Error Enable" "0: Does not handle a preface error as an interrupt..,1: Handles a preface error as an interrupt source" bitfld.long 0x0 20.--21. "RPPAT,Receive Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 16.--19. 1. "RPLEN,Receive Preface Length" bitfld.long 0x0 12.--13. "TPPAT,Transmit Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "TPLEN,Transmit Preface Length" bitfld.long 0x0 6. "SBSEL,Start Bit Select" "0: The start bit area consists of one bit,1: The start bit area consists of three bits.." newline bitfld.long 0x0 5. "SYNSEL,SYNC Select" "0: The start bit pattern is set with the SYNVAL bit,1: The start bit pattern is set with the TSYNC bit" bitfld.long 0x0 4. "SYNVAL,SYNC value Setting" "0,1" newline bitfld.long 0x0 2. "ERTEN,Manchester Edge Retiming Enable" "0: Disables the receive retiming function,1: Enables the receive retiming function" bitfld.long 0x0 1. "TMPOL,Polarity of Transmit Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." newline bitfld.long 0x0 0. "RMPOL,Polarity of Received Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." line.long 0x4 "DCR,Driver Control Register" hexmask.long.byte 0x4 16.--20. 1. "DENGT,Driver Negate Time" hexmask.long.byte 0x4 8.--12. 1. "DEAST,Driver Assertion Time" newline bitfld.long 0x4 0. "DEPOL,Driver Effective Polarity Select" "0: The DEn signal is active-high,1: The DEn signal is active-low" line.long 0x8 "XCR0,Simple LIN Control Register 0" bitfld.long 0x8 24.--25. "BCCS,Bus Conflict Detection Clock Selection" "0: Base clock,1: Base clock/2,?,?" bitfld.long 0x8 22. "AEDIE,Active Edge Detection Interrupt Enable" "0: Active edge detection interrupt disabled,1: Active edge detection interrupt enabled" newline bitfld.long 0x8 21. "COFIE,Counter Overflow Interrupt Enable" "0: Counter overflow is not included in SCIn_ERI..,1: Counter overflow is included in SCIn_ERI.." bitfld.long 0x8 20. "BFDIE,Break Field Detection Interrupt Enable" "0: Break Field detection interrupt disabled,1: Break Field detection interrupt enabled" newline bitfld.long 0x8 17. "BCDIE,Bus Conflict Detection Interrupt Enable" "0: Bus conflict detection is not included in..,1: Bus conflict detection is included in SCIn_ERI.." bitfld.long 0x8 16. "BFOIE,Break Field Output Completion Interrupt Enable" "0: Break Field output completion is not included in..,1: Break Field output completion is included in.." newline bitfld.long 0x8 13.--15. "PIBS,Priority Interrupt Bit Select" "0: Bit 0 of Control Field 1,1: Bit 1 of Control Field 1,?,?,?,?,?,?" bitfld.long 0x8 12. "PIBE,Priority Interrupt Bit Enable" "0: Priority interrupt bit disabled,1: Priority interrupt bit enabled" newline bitfld.long 0x8 10.--11. "CF1DS,Control Field1 Compare Data Select" "0: Select XCR1.PCF1D[7:0] as the compare data,1: Select XCR1.SCF1D[7:0] as the compare data,?,?" bitfld.long 0x8 9. "CF0RE,Control Field 0 Enable" "0: No Control Field 0,1: With Control Field 0" newline bitfld.long 0x8 8. "BFE,Break Field Enable" "0: No Break Field,1: With Break Field" bitfld.long 0x8 0.--1. "TCSS,Timer Count Clock Source Selection" "?,1: TCLK/4,?,?" line.long 0xC "XCR1,Simple LIN Control Register 1" hexmask.long.byte 0xC 24.--31. 1. "CF1CE,Control Field 1 Compare Bit Enable" hexmask.long.byte 0xC 16.--23. 1. "SCF1D,Secondary Compare Data for Control Field 1" newline hexmask.long.byte 0xC 8.--15. 1. "PCF1D,Priority Compare Data for Control Field 1" bitfld.long 0xC 5. "BMEN,Bit Rate Measurement Enable" "0: Bit rate measurement disabled,1: Bit rate measurement enabled" newline bitfld.long 0xC 4. "SDST,Start Frame Detection Enable" "0: Start Frame/Break Field detection disabled,1: Start Frame/Break Field detection enabled" bitfld.long 0xC 0. "TCST,Break Field Output Timer Count Start Trigger" "0: Break Field output timer count stopped,1: Break Field output timer count start" line.long 0x10 "XCR2,Simple LIN Control Register 2" hexmask.long.word 0x10 16.--31. 1. "BFLW,Break Field Length Setting" hexmask.long.byte 0x10 8.--15. 1. "CF0CE,Control Field 0 Compare Bit Enable" newline hexmask.long.byte 0x10 0.--7. 1. "CF0D,Control Field 0 Compare Data" rgroup.long 0x48++0x1B line.long 0x0 "CSR,Common Status Register" bitfld.long 0x0 31. "RDRF,Receive Data Full Flag" "0: Non-FIFO selected (CCR3.FM = 0): No received..,1: Non-FIFO selected (CCR3.FM = 0): Received data.." bitfld.long 0x0 30. "TEND,Transmit End Flag" "0: A character is being transmitted or standing by..,1: Character transfer has been completed or sending.." newline bitfld.long 0x0 29. "TDRE,Transmit Data Empty Flag" "0: Non-FIFO selected (CCR3.FM = 0): Transmit data..,1: Non-FIFO selected (CCR3.FM = 0): No transmit.." bitfld.long 0x0 28. "FER,Framing Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No framing..,1: Non-FIFO selected (CCR3.FM = 0): A framing error.." newline bitfld.long 0x0 27. "PER,Parity Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No parity error..,1: Non-FIFO selected (CCR3.FM = 0): A parity error.." bitfld.long 0x0 26. "MFF,Mode Fault Error Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.long 0x0 24. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.long 0x0 18. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred at address match..,1: A framing error has occurred at address match.." newline bitfld.long 0x0 17. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred at address match..,1: A parity error has occurred at address match.." bitfld.long 0x0 16. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" newline bitfld.long 0x0 15. "RXDMON,Serial Input Data Monitor Bit" "0: When RINV is 0 RXDn pin is the low level. When..,1: When RINV is 0 RXDn pin is the high level. When.." bitfld.long 0x0 4. "ERS,Error Signal Status Flag" "0: Error signal low not responded,1: Error signal low responded" line.long 0x4 "ISR,Simple IIC Status Register" bitfld.long 0x4 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.long 0x4 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" line.long 0x8 "FRSR,FIFO Receive Status Register" hexmask.long.byte 0x8 24.--29. 1. "FNUM,Framing Error Count" hexmask.long.byte 0x8 16.--21. 1. "PNUM,Parity Error Count" newline hexmask.long.byte 0x8 8.--13. 1. "R,Receive-FIFO Data Count" bitfld.long 0x8 0. "DR,Receive Data Ready Flag" "0: Receiving is in progress or no received data..,1: The following receive data is not received for a.." line.long 0xC "FTSR,FIFO Transmit Status Register" hexmask.long.byte 0xC 0.--5. 1. "T,Transmit-FIFO Data Count" line.long 0x10 "MSR,Manchester Status Register" bitfld.long 0x10 6. "RSYNC,Receive SYNC Data Bit" "0: The received start bit is DATA SYNC,1: The received start bit is COMMAND SYNC" bitfld.long 0x10 4. "MER,Manchester Error Flag" "0: No Manchester error occurred,1: Manchester error has occurred" newline bitfld.long 0x10 2. "SBER,Start Bit Error Flag" "0: No start bit error detected,1: Start bit error detected" bitfld.long 0x10 1. "SYER,SYNC Error Flag" "0: No receive SYNC error detected,1: Receive SYNC error detected" newline bitfld.long 0x10 0. "PFER,Preface Error Flag" "0: No preface error detected,1: Preface error detected" line.long 0x14 "XSR0,Simple LIN Status Register 0" hexmask.long.byte 0x14 24.--31. 1. "CF1RD,Control Field 1 received data" hexmask.long.byte 0x14 16.--23. 1. "CF0RD,Control Field 0 received data" newline bitfld.long 0x14 15. "AEDF,Active Edge Detection Flag" "0: No valid edge detected,1: Detected a valid edge" bitfld.long 0x14 14. "COF,Counter Overflow Flag" "0: Break Field detection counter has not overflowed,1: Break Field detection counter overflowed" newline bitfld.long 0x14 13. "PIBDF,Priority Interrupt Bit Detection Flag" "0: Priority interrupt bit is not detected,1: Priority interrupt bit is detected" bitfld.long 0x14 12. "CF1MF,Control Field 1 Compare Match Flag" "0: Control Field 1 received data does not match the..,1: Control Field 1 received data matches the.." newline bitfld.long 0x14 11. "CF0MF,Control Field 0 Compare Match Flag" "0: Control Field 0 received data does not match the..,1: Control Field 0 received data matches the.." bitfld.long 0x14 10. "BFDF,Break Field Detection Flag" "0: Break Field is not detected,1: Break Field is detected" newline bitfld.long 0x14 9. "BCDF,Bus Conflict Detection Flag" "0: No bus collision detected,1: Detected a bus collision" bitfld.long 0x14 8. "BFOF,Break Field Output Completion Flag" "0: Break Field is being output or is not being output,1: Completed BF output" newline bitfld.long 0x14 1. "RXDSF,RXDn Input Status Flag" "0: RXDn input to SCI is enabled,1: RXDn input to SCI is disabled" bitfld.long 0x14 0. "SFSF,Start Frame Status Flag" "0: Start Frame detection disabled or Start Frame..,1: Before Start Frame detection or during detection" line.long 0x18 "XSR1,Simple LIN Status Register 1" hexmask.long.word 0x18 0.--15. 1. "TCNT,Timer Count Capture Value" wgroup.long 0x68++0x13 line.long 0x0 "CFCLR,Common Flag Clear Register" bitfld.long 0x0 31. "RDRFC,RDRF Clear Bit" "0,1" bitfld.long 0x0 29. "TDREC,TDRE Clear Bit" "0,1" newline bitfld.long 0x0 28. "FERC,FER Clear Bit" "0,1" bitfld.long 0x0 27. "PERC,PER Clear Bit" "0,1" newline bitfld.long 0x0 26. "MFFC,MFF Clear Bit" "0,1" bitfld.long 0x0 24. "ORERC,ORER Clear Bit" "0,1" newline bitfld.long 0x0 18. "DFERC,DFER Clear Bit" "0,1" bitfld.long 0x0 17. "DPERC,DPER Clear Bit" "0,1" newline bitfld.long 0x0 16. "DCMFC,DCMF Clear Bit" "0,1" bitfld.long 0x0 4. "ERSC,ERS Clear Bit" "0,1" line.long 0x4 "ICFCLR,Simple IIC Flag Clear Register" bitfld.long 0x4 3. "IICSTIFC,IICSTIF Clear Bit" "0,1" line.long 0x8 "FFCLR,FIFO Flag Clear Register" bitfld.long 0x8 0. "DRC,DR Clear Bit" "0,1" line.long 0xC "MFCLR,Manchester Flag Clear Register" bitfld.long 0xC 4. "MERC,MER Clear Bit" "0,1" bitfld.long 0xC 2. "SBERC,SBER Clear Bit" "0,1" newline bitfld.long 0xC 1. "SYERC,SYER Clear Bit" "0,1" bitfld.long 0xC 0. "PFERC,PFER Clear Bit" "0,1" line.long 0x10 "XFCLR,Simple LIN Flag Clear Register" bitfld.long 0x10 15. "AEDC,AEDF Clear Bit" "0,1" bitfld.long 0x10 14. "COFC,COFF Clear Bit" "0,1" newline bitfld.long 0x10 13. "PIBDC,PIBDF Clear Bit" "0,1" bitfld.long 0x10 12. "CF1MC,CF1MF Clear Bit" "0,1" newline bitfld.long 0x10 11. "CF0MC,CF0MF Clear Bit" "0,1" bitfld.long 0x10 10. "BFDC,BFDF Clear Bit" "0,1" newline bitfld.long 0x10 9. "BCDC,BCDF Clear Bit" "0,1" bitfld.long 0x10 8. "BFOC,BFOF Clear Bit" "0,1" tree.end tree "SCI1_B_NS" base ad:0x50358100 rgroup.long 0x0++0x3 line.long 0x0 "RDR,Receive Data Register" bitfld.long 0x0 28. "FER,Framing error flag" "0,1" bitfld.long 0x0 27. "PER,Parity error flag" "0,1" newline bitfld.long 0x0 24. "ORER,Overrun Error flag" "0,1" bitfld.long 0x0 12. "FFER,FIFO framing error flag" "0: There is no framing error in the data read from..,1: There is framing error in the data read from the.." newline bitfld.long 0x0 11. "FPER,FIFO parity error flag" "0: There is no parity error in the data read from..,1: There is parity error in the data read from the.." bitfld.long 0x0 10. "DR,Receive data ready flag" "0,1" newline bitfld.long 0x0 9. "MPB,Multi-processor flag" "0: Data transmission cycles,1: ID transmission cycles" hexmask.long.word 0x0 0.--8. 1. "RDAT,Serial receive data" rgroup.byte 0x0++0x0 line.byte 0x0 "RDR_BY,Receive Data Register" bitfld.byte 0x0 4. "FER,Framing error flag" "0,1" bitfld.byte 0x0 3. "PER,Parity error flag" "0,1" newline bitfld.byte 0x0 0. "ORER,Overrun Error flag" "0,1" group.long 0x4++0x3 line.long 0x0 "TDR,Transmit Data Register" bitfld.long 0x0 12. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.long 0x0 9. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline hexmask.long.word 0x0 0.--8. 1. "TDAT,Serial transmit data" group.byte 0x4++0x1 line.byte 0x0 "TDRLL,Transmit Data Register" line.byte 0x1 "TDRLH,Transmit Data Register" bitfld.byte 0x1 4. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.byte 0x1 1. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline bitfld.byte 0x1 0. "TDAT,Serial transmit data" "0,1" group.long 0x8++0x13 line.long 0x0 "CCR0,Common Control Register 0" bitfld.long 0x0 24. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled,1: SSn pin function is enabled" bitfld.long 0x0 21. "TEIE,Transmit End Interrupt Enable" "0: SCIn_TEI interrupt request is disabled,1: SCIn_TEI interrupt request is enabled" newline bitfld.long 0x0 20. "TIE,Transmit Interrupt Enable" "0: SCIn_TXI interrupt request is disabled,1: SCIn_TXI interrupt request is enabled" bitfld.long 0x0 16. "RIE,Receive Interrupt Enable" "0: SCIn_RXI and SCIn_ERI interrupt requests are..,1: SCIn_RXI and SCIn_ERI interrupt requests are.." newline bitfld.long 0x0 10. "IDSEL,ID Frame Select" "0: Compare data irrespective of the value of the..,1: Compare data only when the MPB bit is 1 (ID frame)" bitfld.long 0x0 9. "DCME,Data Compare Match Enable" "0: Address match function is disabled,1: Address match function is enabled" newline bitfld.long 0x0 8. "MPIE,Multi-Processor Interrupt Enable" "0: Non-multi-processor reception,1: Multi-processor reception When the data with the.." bitfld.long 0x0 4. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" newline bitfld.long 0x0 0. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" line.long 0x4 "CCR1,Common Control Register 1" bitfld.long 0x4 29. "NFM,Noise Filter Mode" "0: 3-point matching mode,1: Majority vote mode" bitfld.long 0x4 28. "NFEN,Digital Noise Filter Function Enable" "0: In Asynchronous Manchester Simple LIN modes:..,1: In Asynchronous Manchester Simple LIN modes:.." newline bitfld.long 0x4 24.--26. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: The on-chip baud rate generator source clock..,?,?,?,?,?,?" bitfld.long 0x4 20. "SHARPS,Half-Duplex Communication Select" "0: TXDn pin RXDn pin independent,1: TXDn/RXDn pin combination use (half-duplex.." newline bitfld.long 0x4 16. "SPLP,Loopback Control" "0: Normal mode,1: Loopback mode" bitfld.long 0x4 13. "RINV,RXD Invert" "0: Received data from RXDn is not inverted and input,1: Received data from RXDn is inverted and input" newline bitfld.long 0x4 12. "TINV,TXD Invert" "0: Transmit data is not inverted and output to TXDn,1: Transmit data is inverted and output to TXDn" bitfld.long 0x4 9. "PM,Parity Mode" "0: Selects even parity,1: Selects odd parity" newline bitfld.long 0x4 8. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.." bitfld.long 0x4 5. "SPB2IO,Serial Port Break I/O" "0: The value of SPB2DT bit is not output in TXDn pin,1: The value of SPB2DT bit is output in TXDn pin" newline bitfld.long 0x4 4. "SPB2DT,Serial Port Break Data Select" "0: When TINV is 0 low level is output in TXDn pin.,1: When TINV is 0 high level is output in TXDn pin." bitfld.long 0x4 1. "CTSPEN,CTS External Pin Enable" "0: Alternate setting to use CTS and RTS functions..,1: Dedicated setting for separately using CTS and.." newline bitfld.long 0x4 0. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled" line.long 0x8 "CCR2,Common Control Register 2" hexmask.long.byte 0x8 24.--31. 1. "MDDR,Modulation Duty Setting" bitfld.long 0x8 20.--21. "CKS,Clock Select" "0: TCLK clock (n = 0),1: TCLK/4 clock (n = 1),?,?" newline bitfld.long 0x8 16. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled,1: Bit rate modulation function is enabled" hexmask.long.byte 0x8 8.--15. 1. "BRR,Bit Rate Setting" newline bitfld.long 0x8 7. "ABCSE2,Asynchronous Mode Extended Base Clock Select 2" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 4 base clock cycles for 1-bit.." bitfld.long 0x8 6. "ABCSE,Asynchronous Mode Extended Base Clock Select" "0: Clock cycles for 1-bit period is determined by..,1: Baud rate is 6 base clock cycles for 1-bit.." newline bitfld.long 0x8 5. "ABCS,Asynchronous Mode Base Clock Select" "0: Selects 16 base clock cycles for 1-bit period,1: Selects 8 base clock cycles for 1-bit period" bitfld.long 0x8 4. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.long 0x8 0.--2. "BCP,Base Clock Pulse" "0: 93 clock cycles (S = 93),1: 128 clock cycles (S = 128),?,?,?,?,?,?" line.long 0xC "CCR3,Common Control Register 3" bitfld.long 0xC 29. "BLK,Block Transfer Mode" "0: Non-block transfer mode operation,1: Block transfer mode operation" bitfld.long 0xC 28. "GM,GSM Mode" "0: Non-GSM mode operation,1: GSM mode operation" newline bitfld.long 0xC 26. "ACS0,Asynchronous Mode Clock Source Select" "0: External clock input,1: Logical AND of compare matches output from the.." bitfld.long 0xC 24.--25. "CKE,Clock Enable" "0,1,2,3" newline bitfld.long 0xC 21. "DEN,Driver Enable" "0: RS-485 driver control function disabled,1: RS-485 driver control function enabled" bitfld.long 0xC 20. "FM,FIFO Mode Select" "0: TDR register and RDR register are non-FIFO..,1: TDR register and RDR register are FIFO buffer.." newline bitfld.long 0xC 19. "MP,Multi-Processor Mode" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" bitfld.long 0xC 16.--18. "MOD,Communication Mode Select" "0: Asynchronous mode (multi-processor mode),1: Smart card interface mode,?,?,?,?,?,?" newline bitfld.long 0xC 15. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.long 0xC 14. "STP,Stop Bit Length" "0: 1 stop bit/break delimiter length is 1-bit,1: 2 stop bits/break delimiter length is 2-bit" newline bitfld.long 0xC 13. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted to TSR as is. RSR..,1: TDR contents are inverted before being.." bitfld.long 0xC 12. "LSBF,LSB First select" "0: MSB-first,1: LSB-first" newline bitfld.long 0xC 8.--9. "CHR,Character Length" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 9-bit data length,?,?" bitfld.long 0xC 7. "BPEN,Synchronizer Bypass Enable" "0: Synchronizer circuit is not bypassed,1: Synchronizer circuit is bypassed" newline bitfld.long 0xC 1. "CPOL,Clock Polarity Select" "0: SCKn in idle state is 0,1: SCKn in idle state is 1" bitfld.long 0xC 0. "CPHA,Clock Phase Select" "0: Data is sampled at an odd edge and changes at an..,1: Data changes at an odd edge and is sampled at an.." line.long 0x10 "CCR4,Common Control Register 4" bitfld.long 0x10 31. "AET,Adjustment Edge for Transmit Timing" "0: When CCR1.TINV is 0 adjust the rising edge..,1: When CCR1.TINV is 0 adjust the falling edge.." bitfld.long 0x10 28.--30. "ATT,Adjustment Value for Transmit Timing" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "AJD,Adjustment Direction for Receive Sampling Timing" "0: The sampling timing is adjusted backward to the..,1: The sampling timing is adjusted forward to the.." bitfld.long 0x10 24.--26. "AST,Adjustment Value for Receive Sampling Timing" "0: Setting prohibited,1: 2-TCLK delay,?,?,?,?,?,?" newline bitfld.long 0x10 19. "SCKSEL,Master receive clock selection" "0: Master receive clock is disabled,1: Master receive clock is enabled" bitfld.long 0x10 17. "ATEN,Adjust Transmit Timing Enable" "0: Adjust transmit timing disabled,1: Adjust transmit timing enabled" newline bitfld.long 0x10 16. "ASEN,Adjust Receive Sampling Timing Enable" "0: Adjust sampling timing disabled,1: Adjust sampling timing enabled" hexmask.long.word 0x10 0.--8. 1. "CMPD,Compare Match Data" rgroup.byte 0x1C++0x0 line.byte 0x0 "CESR,Communication Enable Status Register" bitfld.byte 0x0 4. "TIST,TE Internal Status" "0: TE signal internal state value 0,1: TE signal internal state value 1" bitfld.byte 0x0 0. "RIST,RE Internal Status" "0: RE signal internal state value 0,1: RE signal internal state value 1" group.long 0x20++0x7 line.long 0x0 "ICR,Simple IIC Control Register" bitfld.long 0x0 22.--23. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition,?,?" bitfld.long 0x0 20.--21. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition,?,?" newline bitfld.long 0x0 18. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated" bitfld.long 0x0 17. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated,1: A restart condition is generated" newline bitfld.long 0x0 16. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated,1: A start condition is generated" bitfld.long 0x0 13. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.long 0x0 9. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" bitfld.long 0x0 8. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts" newline hexmask.long.byte 0x0 0.--4. 1. "IICDL,SDA Delay Output Select" line.long 0x4 "FCR,FIFO Control Register" hexmask.long.byte 0x4 24.--28. 1. "RSTRG,RTS Output Active Trigger Number Select" bitfld.long 0x4 23. "RFRST,Receive FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Receive-FIFO(RDR.." newline hexmask.long.byte 0x4 16.--20. 1. "RTRG,Receive FIFO Data Trigger Number" bitfld.long 0x4 15. "TFRST,Transmit FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Transmit-FIFO (TDR.." newline hexmask.long.byte 0x4 8.--12. 1. "TTRG,Transmit FIFO Data Trigger Number" bitfld.long 0x4 0. "DRES,Receive Data Ready Error Select Bit" "0: Reception data full interrupt (SCIn_RXI),1: Receive error interrupt (SCIn_ERI)" group.long 0x2C++0x13 line.long 0x0 "MCR,Manchester Control Register" bitfld.long 0x0 26. "SBEREN,Start Bit Error Enable" "0: Does not handle a start bit error as an..,1: Handles a start bit error as an interrupt source" bitfld.long 0x0 25. "SYEREN,Receive SYNC Error Enable" "0: Does not handle a receive SYNC error as an..,1: Handles a receive SYNC error as an interrupt.." newline bitfld.long 0x0 24. "PFEREN,Preface Error Enable" "0: Does not handle a preface error as an interrupt..,1: Handles a preface error as an interrupt source" bitfld.long 0x0 20.--21. "RPPAT,Receive Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 16.--19. 1. "RPLEN,Receive Preface Length" bitfld.long 0x0 12.--13. "TPPAT,Transmit Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "TPLEN,Transmit Preface Length" bitfld.long 0x0 6. "SBSEL,Start Bit Select" "0: The start bit area consists of one bit,1: The start bit area consists of three bits.." newline bitfld.long 0x0 5. "SYNSEL,SYNC Select" "0: The start bit pattern is set with the SYNVAL bit,1: The start bit pattern is set with the TSYNC bit" bitfld.long 0x0 4. "SYNVAL,SYNC value Setting" "0,1" newline bitfld.long 0x0 2. "ERTEN,Manchester Edge Retiming Enable" "0: Disables the receive retiming function,1: Enables the receive retiming function" bitfld.long 0x0 1. "TMPOL,Polarity of Transmit Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." newline bitfld.long 0x0 0. "RMPOL,Polarity of Received Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." line.long 0x4 "DCR,Driver Control Register" hexmask.long.byte 0x4 16.--20. 1. "DENGT,Driver Negate Time" hexmask.long.byte 0x4 8.--12. 1. "DEAST,Driver Assertion Time" newline bitfld.long 0x4 0. "DEPOL,Driver Effective Polarity Select" "0: The DEn signal is active-high,1: The DEn signal is active-low" line.long 0x8 "XCR0,Simple LIN Control Register 0" bitfld.long 0x8 24.--25. "BCCS,Bus Conflict Detection Clock Selection" "0: Base clock,1: Base clock/2,?,?" bitfld.long 0x8 22. "AEDIE,Active Edge Detection Interrupt Enable" "0: Active edge detection interrupt disabled,1: Active edge detection interrupt enabled" newline bitfld.long 0x8 21. "COFIE,Counter Overflow Interrupt Enable" "0: Counter overflow is not included in SCIn_ERI..,1: Counter overflow is included in SCIn_ERI.." bitfld.long 0x8 20. "BFDIE,Break Field Detection Interrupt Enable" "0: Break Field detection interrupt disabled,1: Break Field detection interrupt enabled" newline bitfld.long 0x8 17. "BCDIE,Bus Conflict Detection Interrupt Enable" "0: Bus conflict detection is not included in..,1: Bus conflict detection is included in SCIn_ERI.." bitfld.long 0x8 16. "BFOIE,Break Field Output Completion Interrupt Enable" "0: Break Field output completion is not included in..,1: Break Field output completion is included in.." newline bitfld.long 0x8 13.--15. "PIBS,Priority Interrupt Bit Select" "0: Bit 0 of Control Field 1,1: Bit 1 of Control Field 1,?,?,?,?,?,?" bitfld.long 0x8 12. "PIBE,Priority Interrupt Bit Enable" "0: Priority interrupt bit disabled,1: Priority interrupt bit enabled" newline bitfld.long 0x8 10.--11. "CF1DS,Control Field1 Compare Data Select" "0: Select XCR1.PCF1D[7:0] as the compare data,1: Select XCR1.SCF1D[7:0] as the compare data,?,?" bitfld.long 0x8 9. "CF0RE,Control Field 0 Enable" "0: No Control Field 0,1: With Control Field 0" newline bitfld.long 0x8 8. "BFE,Break Field Enable" "0: No Break Field,1: With Break Field" bitfld.long 0x8 0.--1. "TCSS,Timer Count Clock Source Selection" "?,1: TCLK/4,?,?" line.long 0xC "XCR1,Simple LIN Control Register 1" hexmask.long.byte 0xC 24.--31. 1. "CF1CE,Control Field 1 Compare Bit Enable" hexmask.long.byte 0xC 16.--23. 1. "SCF1D,Secondary Compare Data for Control Field 1" newline hexmask.long.byte 0xC 8.--15. 1. "PCF1D,Priority Compare Data for Control Field 1" bitfld.long 0xC 5. "BMEN,Bit Rate Measurement Enable" "0: Bit rate measurement disabled,1: Bit rate measurement enabled" newline bitfld.long 0xC 4. "SDST,Start Frame Detection Enable" "0: Start Frame/Break Field detection disabled,1: Start Frame/Break Field detection enabled" bitfld.long 0xC 0. "TCST,Break Field Output Timer Count Start Trigger" "0: Break Field output timer count stopped,1: Break Field output timer count start" line.long 0x10 "XCR2,Simple LIN Control Register 2" hexmask.long.word 0x10 16.--31. 1. "BFLW,Break Field Length Setting" hexmask.long.byte 0x10 8.--15. 1. "CF0CE,Control Field 0 Compare Bit Enable" newline hexmask.long.byte 0x10 0.--7. 1. "CF0D,Control Field 0 Compare Data" rgroup.long 0x48++0x1B line.long 0x0 "CSR,Common Status Register" bitfld.long 0x0 31. "RDRF,Receive Data Full Flag" "0: Non-FIFO selected (CCR3.FM = 0): No received..,1: Non-FIFO selected (CCR3.FM = 0): Received data.." bitfld.long 0x0 30. "TEND,Transmit End Flag" "0: A character is being transmitted or standing by..,1: Character transfer has been completed or sending.." newline bitfld.long 0x0 29. "TDRE,Transmit Data Empty Flag" "0: Non-FIFO selected (CCR3.FM = 0): Transmit data..,1: Non-FIFO selected (CCR3.FM = 0): No transmit.." bitfld.long 0x0 28. "FER,Framing Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No framing..,1: Non-FIFO selected (CCR3.FM = 0): A framing error.." newline bitfld.long 0x0 27. "PER,Parity Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No parity error..,1: Non-FIFO selected (CCR3.FM = 0): A parity error.." bitfld.long 0x0 26. "MFF,Mode Fault Error Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.long 0x0 24. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.long 0x0 18. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred at address match..,1: A framing error has occurred at address match.." newline bitfld.long 0x0 17. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred at address match..,1: A parity error has occurred at address match.." bitfld.long 0x0 16. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" newline bitfld.long 0x0 15. "RXDMON,Serial Input Data Monitor Bit" "0: When RINV is 0 RXDn pin is the low level. When..,1: When RINV is 0 RXDn pin is the high level. When.." bitfld.long 0x0 4. "ERS,Error Signal Status Flag" "0: Error signal low not responded,1: Error signal low responded" line.long 0x4 "ISR,Simple IIC Status Register" bitfld.long 0x4 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.long 0x4 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" line.long 0x8 "FRSR,FIFO Receive Status Register" hexmask.long.byte 0x8 24.--29. 1. "FNUM,Framing Error Count" hexmask.long.byte 0x8 16.--21. 1. "PNUM,Parity Error Count" newline hexmask.long.byte 0x8 8.--13. 1. "R,Receive-FIFO Data Count" bitfld.long 0x8 0. "DR,Receive Data Ready Flag" "0: Receiving is in progress or no received data..,1: The following receive data is not received for a.." line.long 0xC "FTSR,FIFO Transmit Status Register" hexmask.long.byte 0xC 0.--5. 1. "T,Transmit-FIFO Data Count" line.long 0x10 "MSR,Manchester Status Register" bitfld.long 0x10 6. "RSYNC,Receive SYNC Data Bit" "0: The received start bit is DATA SYNC,1: The received start bit is COMMAND SYNC" bitfld.long 0x10 4. "MER,Manchester Error Flag" "0: No Manchester error occurred,1: Manchester error has occurred" newline bitfld.long 0x10 2. "SBER,Start Bit Error Flag" "0: No start bit error detected,1: Start bit error detected" bitfld.long 0x10 1. "SYER,SYNC Error Flag" "0: No receive SYNC error detected,1: Receive SYNC error detected" newline bitfld.long 0x10 0. "PFER,Preface Error Flag" "0: No preface error detected,1: Preface error detected" line.long 0x14 "XSR0,Simple LIN Status Register 0" hexmask.long.byte 0x14 24.--31. 1. "CF1RD,Control Field 1 received data" hexmask.long.byte 0x14 16.--23. 1. "CF0RD,Control Field 0 received data" newline bitfld.long 0x14 15. "AEDF,Active Edge Detection Flag" "0: No valid edge detected,1: Detected a valid edge" bitfld.long 0x14 14. "COF,Counter Overflow Flag" "0: Break Field detection counter has not overflowed,1: Break Field detection counter overflowed" newline bitfld.long 0x14 13. "PIBDF,Priority Interrupt Bit Detection Flag" "0: Priority interrupt bit is not detected,1: Priority interrupt bit is detected" bitfld.long 0x14 12. "CF1MF,Control Field 1 Compare Match Flag" "0: Control Field 1 received data does not match the..,1: Control Field 1 received data matches the.." newline bitfld.long 0x14 11. "CF0MF,Control Field 0 Compare Match Flag" "0: Control Field 0 received data does not match the..,1: Control Field 0 received data matches the.." bitfld.long 0x14 10. "BFDF,Break Field Detection Flag" "0: Break Field is not detected,1: Break Field is detected" newline bitfld.long 0x14 9. "BCDF,Bus Conflict Detection Flag" "0: No bus collision detected,1: Detected a bus collision" bitfld.long 0x14 8. "BFOF,Break Field Output Completion Flag" "0: Break Field is being output or is not being output,1: Completed BF output" newline bitfld.long 0x14 1. "RXDSF,RXDn Input Status Flag" "0: RXDn input to SCI is enabled,1: RXDn input to SCI is disabled" bitfld.long 0x14 0. "SFSF,Start Frame Status Flag" "0: Start Frame detection disabled or Start Frame..,1: Before Start Frame detection or during detection" line.long 0x18 "XSR1,Simple LIN Status Register 1" hexmask.long.word 0x18 0.--15. 1. "TCNT,Timer Count Capture Value" wgroup.long 0x68++0x13 line.long 0x0 "CFCLR,Common Flag Clear Register" bitfld.long 0x0 31. "RDRFC,RDRF Clear Bit" "0,1" bitfld.long 0x0 29. "TDREC,TDRE Clear Bit" "0,1" newline bitfld.long 0x0 28. "FERC,FER Clear Bit" "0,1" bitfld.long 0x0 27. "PERC,PER Clear Bit" "0,1" newline bitfld.long 0x0 26. "MFFC,MFF Clear Bit" "0,1" bitfld.long 0x0 24. "ORERC,ORER Clear Bit" "0,1" newline bitfld.long 0x0 18. "DFERC,DFER Clear Bit" "0,1" bitfld.long 0x0 17. "DPERC,DPER Clear Bit" "0,1" newline bitfld.long 0x0 16. "DCMFC,DCMF Clear Bit" "0,1" bitfld.long 0x0 4. "ERSC,ERS Clear Bit" "0,1" line.long 0x4 "ICFCLR,Simple IIC Flag Clear Register" bitfld.long 0x4 3. "IICSTIFC,IICSTIF Clear Bit" "0,1" line.long 0x8 "FFCLR,FIFO Flag Clear Register" bitfld.long 0x8 0. "DRC,DR Clear Bit" "0,1" line.long 0xC "MFCLR,Manchester Flag Clear Register" bitfld.long 0xC 4. "MERC,MER Clear Bit" "0,1" bitfld.long 0xC 2. "SBERC,SBER Clear Bit" "0,1" newline bitfld.long 0xC 1. "SYERC,SYER Clear Bit" "0,1" bitfld.long 0xC 0. "PFERC,PFER Clear Bit" "0,1" line.long 0x10 "XFCLR,Simple LIN Flag Clear Register" bitfld.long 0x10 15. "AEDC,AEDF Clear Bit" "0,1" bitfld.long 0x10 14. "COFC,COFF Clear Bit" "0,1" newline bitfld.long 0x10 13. "PIBDC,PIBDF Clear Bit" "0,1" bitfld.long 0x10 12. "CF1MC,CF1MF Clear Bit" "0,1" newline bitfld.long 0x10 11. "CF0MC,CF0MF Clear Bit" "0,1" bitfld.long 0x10 10. "BFDC,BFDF Clear Bit" "0,1" newline bitfld.long 0x10 9. "BCDC,BCDF Clear Bit" "0,1" bitfld.long 0x10 8. "BFOC,BFOF Clear Bit" "0,1" tree.end tree "SCI2_B" base ad:0x40358200 rgroup.long 0x0++0x3 line.long 0x0 "RDR,Receive Data Register" bitfld.long 0x0 28. "FER,Framing error flag" "0,1" bitfld.long 0x0 27. "PER,Parity error flag" "0,1" newline bitfld.long 0x0 24. "ORER,Overrun Error flag" "0,1" bitfld.long 0x0 12. "FFER,FIFO framing error flag" "0: There is no framing error in the data read from..,1: There is framing error in the data read from the.." newline bitfld.long 0x0 11. "FPER,FIFO parity error flag" "0: There is no parity error in the data read from..,1: There is parity error in the data read from the.." bitfld.long 0x0 10. "DR,Receive data ready flag" "0,1" newline bitfld.long 0x0 9. "MPB,Multi-processor flag" "0: Data transmission cycles,1: ID transmission cycles" hexmask.long.word 0x0 0.--8. 1. "RDAT,Serial receive data" rgroup.byte 0x0++0x0 line.byte 0x0 "RDR_BY,Receive Data Register" bitfld.byte 0x0 4. "FER,Framing error flag" "0,1" bitfld.byte 0x0 3. "PER,Parity error flag" "0,1" newline bitfld.byte 0x0 0. "ORER,Overrun Error flag" "0,1" group.long 0x4++0x3 line.long 0x0 "TDR,Transmit Data Register" bitfld.long 0x0 12. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.long 0x0 9. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline hexmask.long.word 0x0 0.--8. 1. "TDAT,Serial transmit data" group.byte 0x4++0x1 line.byte 0x0 "TDRLL,Transmit Data Register" line.byte 0x1 "TDRLH,Transmit Data Register" bitfld.byte 0x1 4. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.byte 0x1 1. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline bitfld.byte 0x1 0. "TDAT,Serial transmit data" "0,1" group.long 0x8++0x13 line.long 0x0 "CCR0,Common Control Register 0" bitfld.long 0x0 24. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled,1: SSn pin function is enabled" bitfld.long 0x0 21. "TEIE,Transmit End Interrupt Enable" "0: SCIn_TEI interrupt request is disabled,1: SCIn_TEI interrupt request is enabled" newline bitfld.long 0x0 20. "TIE,Transmit Interrupt Enable" "0: SCIn_TXI interrupt request is disabled,1: SCIn_TXI interrupt request is enabled" bitfld.long 0x0 16. "RIE,Receive Interrupt Enable" "0: SCIn_RXI and SCIn_ERI interrupt requests are..,1: SCIn_RXI and SCIn_ERI interrupt requests are.." newline bitfld.long 0x0 10. "IDSEL,ID Frame Select" "0: Compare data irrespective of the value of the..,1: Compare data only when the MPB bit is 1 (ID frame)" bitfld.long 0x0 9. "DCME,Data Compare Match Enable" "0: Address match function is disabled,1: Address match function is enabled" newline bitfld.long 0x0 8. "MPIE,Multi-Processor Interrupt Enable" "0: Non-multi-processor reception,1: Multi-processor reception When the data with the.." bitfld.long 0x0 4. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" newline bitfld.long 0x0 0. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" line.long 0x4 "CCR1,Common Control Register 1" bitfld.long 0x4 29. "NFM,Noise Filter Mode" "0: 3-point matching mode,1: Majority vote mode" bitfld.long 0x4 28. "NFEN,Digital Noise Filter Function Enable" "0: In Asynchronous Manchester Simple LIN modes:..,1: In Asynchronous Manchester Simple LIN modes:.." newline bitfld.long 0x4 24.--26. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: The on-chip baud rate generator source clock..,?,?,?,?,?,?" bitfld.long 0x4 20. "SHARPS,Half-Duplex Communication Select" "0: TXDn pin RXDn pin independent,1: TXDn/RXDn pin combination use (half-duplex.." newline bitfld.long 0x4 16. "SPLP,Loopback Control" "0: Normal mode,1: Loopback mode" bitfld.long 0x4 13. "RINV,RXD Invert" "0: Received data from RXDn is not inverted and input,1: Received data from RXDn is inverted and input" newline bitfld.long 0x4 12. "TINV,TXD Invert" "0: Transmit data is not inverted and output to TXDn,1: Transmit data is inverted and output to TXDn" bitfld.long 0x4 9. "PM,Parity Mode" "0: Selects even parity,1: Selects odd parity" newline bitfld.long 0x4 8. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.." bitfld.long 0x4 5. "SPB2IO,Serial Port Break I/O" "0: The value of SPB2DT bit is not output in TXDn pin,1: The value of SPB2DT bit is output in TXDn pin" newline bitfld.long 0x4 4. "SPB2DT,Serial Port Break Data Select" "0: When TINV is 0 low level is output in TXDn pin.,1: When TINV is 0 high level is output in TXDn pin." bitfld.long 0x4 1. "CTSPEN,CTS External Pin Enable" "0: Alternate setting to use CTS and RTS functions..,1: Dedicated setting for separately using CTS and.." newline bitfld.long 0x4 0. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled" line.long 0x8 "CCR2,Common Control Register 2" hexmask.long.byte 0x8 24.--31. 1. "MDDR,Modulation Duty Setting" bitfld.long 0x8 20.--21. "CKS,Clock Select" "0: TCLK clock (n = 0),1: TCLK/4 clock (n = 1),?,?" newline bitfld.long 0x8 16. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled,1: Bit rate modulation function is enabled" hexmask.long.byte 0x8 8.--15. 1. "BRR,Bit Rate Setting" newline bitfld.long 0x8 7. "ABCSE2,Asynchronous Mode Extended Base Clock Select 2" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 4 base clock cycles for 1-bit.." bitfld.long 0x8 6. "ABCSE,Asynchronous Mode Extended Base Clock Select" "0: Clock cycles for 1-bit period is determined by..,1: Baud rate is 6 base clock cycles for 1-bit.." newline bitfld.long 0x8 5. "ABCS,Asynchronous Mode Base Clock Select" "0: Selects 16 base clock cycles for 1-bit period,1: Selects 8 base clock cycles for 1-bit period" bitfld.long 0x8 4. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.long 0x8 0.--2. "BCP,Base Clock Pulse" "0: 93 clock cycles (S = 93),1: 128 clock cycles (S = 128),?,?,?,?,?,?" line.long 0xC "CCR3,Common Control Register 3" bitfld.long 0xC 29. "BLK,Block Transfer Mode" "0: Non-block transfer mode operation,1: Block transfer mode operation" bitfld.long 0xC 28. "GM,GSM Mode" "0: Non-GSM mode operation,1: GSM mode operation" newline bitfld.long 0xC 26. "ACS0,Asynchronous Mode Clock Source Select" "0: External clock input,1: Logical AND of compare matches output from the.." bitfld.long 0xC 24.--25. "CKE,Clock Enable" "0,1,2,3" newline bitfld.long 0xC 21. "DEN,Driver Enable" "0: RS-485 driver control function disabled,1: RS-485 driver control function enabled" bitfld.long 0xC 20. "FM,FIFO Mode Select" "0: TDR register and RDR register are non-FIFO..,1: TDR register and RDR register are FIFO buffer.." newline bitfld.long 0xC 19. "MP,Multi-Processor Mode" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" bitfld.long 0xC 16.--18. "MOD,Communication Mode Select" "0: Asynchronous mode (multi-processor mode),1: Smart card interface mode,?,?,?,?,?,?" newline bitfld.long 0xC 15. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.long 0xC 14. "STP,Stop Bit Length" "0: 1 stop bit/break delimiter length is 1-bit,1: 2 stop bits/break delimiter length is 2-bit" newline bitfld.long 0xC 13. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted to TSR as is. RSR..,1: TDR contents are inverted before being.." bitfld.long 0xC 12. "LSBF,LSB First select" "0: MSB-first,1: LSB-first" newline bitfld.long 0xC 8.--9. "CHR,Character Length" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 9-bit data length,?,?" bitfld.long 0xC 7. "BPEN,Synchronizer Bypass Enable" "0: Synchronizer circuit is not bypassed,1: Synchronizer circuit is bypassed" newline bitfld.long 0xC 1. "CPOL,Clock Polarity Select" "0: SCKn in idle state is 0,1: SCKn in idle state is 1" bitfld.long 0xC 0. "CPHA,Clock Phase Select" "0: Data is sampled at an odd edge and changes at an..,1: Data changes at an odd edge and is sampled at an.." line.long 0x10 "CCR4,Common Control Register 4" bitfld.long 0x10 31. "AET,Adjustment Edge for Transmit Timing" "0: When CCR1.TINV is 0 adjust the rising edge..,1: When CCR1.TINV is 0 adjust the falling edge.." bitfld.long 0x10 28.--30. "ATT,Adjustment Value for Transmit Timing" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "AJD,Adjustment Direction for Receive Sampling Timing" "0: The sampling timing is adjusted backward to the..,1: The sampling timing is adjusted forward to the.." bitfld.long 0x10 24.--26. "AST,Adjustment Value for Receive Sampling Timing" "0: Setting prohibited,1: 2-TCLK delay,?,?,?,?,?,?" newline bitfld.long 0x10 19. "SCKSEL,Master receive clock selection" "0: Master receive clock is disabled,1: Master receive clock is enabled" bitfld.long 0x10 17. "ATEN,Adjust Transmit Timing Enable" "0: Adjust transmit timing disabled,1: Adjust transmit timing enabled" newline bitfld.long 0x10 16. "ASEN,Adjust Receive Sampling Timing Enable" "0: Adjust sampling timing disabled,1: Adjust sampling timing enabled" hexmask.long.word 0x10 0.--8. 1. "CMPD,Compare Match Data" rgroup.byte 0x1C++0x0 line.byte 0x0 "CESR,Communication Enable Status Register" bitfld.byte 0x0 4. "TIST,TE Internal Status" "0: TE signal internal state value 0,1: TE signal internal state value 1" bitfld.byte 0x0 0. "RIST,RE Internal Status" "0: RE signal internal state value 0,1: RE signal internal state value 1" group.long 0x20++0x7 line.long 0x0 "ICR,Simple IIC Control Register" bitfld.long 0x0 22.--23. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition,?,?" bitfld.long 0x0 20.--21. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition,?,?" newline bitfld.long 0x0 18. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated" bitfld.long 0x0 17. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated,1: A restart condition is generated" newline bitfld.long 0x0 16. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated,1: A start condition is generated" bitfld.long 0x0 13. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.long 0x0 9. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" bitfld.long 0x0 8. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts" newline hexmask.long.byte 0x0 0.--4. 1. "IICDL,SDA Delay Output Select" line.long 0x4 "FCR,FIFO Control Register" hexmask.long.byte 0x4 24.--28. 1. "RSTRG,RTS Output Active Trigger Number Select" bitfld.long 0x4 23. "RFRST,Receive FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Receive-FIFO(RDR.." newline hexmask.long.byte 0x4 16.--20. 1. "RTRG,Receive FIFO Data Trigger Number" bitfld.long 0x4 15. "TFRST,Transmit FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Transmit-FIFO (TDR.." newline hexmask.long.byte 0x4 8.--12. 1. "TTRG,Transmit FIFO Data Trigger Number" bitfld.long 0x4 0. "DRES,Receive Data Ready Error Select Bit" "0: Reception data full interrupt (SCIn_RXI),1: Receive error interrupt (SCIn_ERI)" group.long 0x2C++0x13 line.long 0x0 "MCR,Manchester Control Register" bitfld.long 0x0 26. "SBEREN,Start Bit Error Enable" "0: Does not handle a start bit error as an..,1: Handles a start bit error as an interrupt source" bitfld.long 0x0 25. "SYEREN,Receive SYNC Error Enable" "0: Does not handle a receive SYNC error as an..,1: Handles a receive SYNC error as an interrupt.." newline bitfld.long 0x0 24. "PFEREN,Preface Error Enable" "0: Does not handle a preface error as an interrupt..,1: Handles a preface error as an interrupt source" bitfld.long 0x0 20.--21. "RPPAT,Receive Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 16.--19. 1. "RPLEN,Receive Preface Length" bitfld.long 0x0 12.--13. "TPPAT,Transmit Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "TPLEN,Transmit Preface Length" bitfld.long 0x0 6. "SBSEL,Start Bit Select" "0: The start bit area consists of one bit,1: The start bit area consists of three bits.." newline bitfld.long 0x0 5. "SYNSEL,SYNC Select" "0: The start bit pattern is set with the SYNVAL bit,1: The start bit pattern is set with the TSYNC bit" bitfld.long 0x0 4. "SYNVAL,SYNC value Setting" "0,1" newline bitfld.long 0x0 2. "ERTEN,Manchester Edge Retiming Enable" "0: Disables the receive retiming function,1: Enables the receive retiming function" bitfld.long 0x0 1. "TMPOL,Polarity of Transmit Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." newline bitfld.long 0x0 0. "RMPOL,Polarity of Received Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." line.long 0x4 "DCR,Driver Control Register" hexmask.long.byte 0x4 16.--20. 1. "DENGT,Driver Negate Time" hexmask.long.byte 0x4 8.--12. 1. "DEAST,Driver Assertion Time" newline bitfld.long 0x4 0. "DEPOL,Driver Effective Polarity Select" "0: The DEn signal is active-high,1: The DEn signal is active-low" line.long 0x8 "XCR0,Simple LIN Control Register 0" bitfld.long 0x8 24.--25. "BCCS,Bus Conflict Detection Clock Selection" "0: Base clock,1: Base clock/2,?,?" bitfld.long 0x8 22. "AEDIE,Active Edge Detection Interrupt Enable" "0: Active edge detection interrupt disabled,1: Active edge detection interrupt enabled" newline bitfld.long 0x8 21. "COFIE,Counter Overflow Interrupt Enable" "0: Counter overflow is not included in SCIn_ERI..,1: Counter overflow is included in SCIn_ERI.." bitfld.long 0x8 20. "BFDIE,Break Field Detection Interrupt Enable" "0: Break Field detection interrupt disabled,1: Break Field detection interrupt enabled" newline bitfld.long 0x8 17. "BCDIE,Bus Conflict Detection Interrupt Enable" "0: Bus conflict detection is not included in..,1: Bus conflict detection is included in SCIn_ERI.." bitfld.long 0x8 16. "BFOIE,Break Field Output Completion Interrupt Enable" "0: Break Field output completion is not included in..,1: Break Field output completion is included in.." newline bitfld.long 0x8 13.--15. "PIBS,Priority Interrupt Bit Select" "0: Bit 0 of Control Field 1,1: Bit 1 of Control Field 1,?,?,?,?,?,?" bitfld.long 0x8 12. "PIBE,Priority Interrupt Bit Enable" "0: Priority interrupt bit disabled,1: Priority interrupt bit enabled" newline bitfld.long 0x8 10.--11. "CF1DS,Control Field1 Compare Data Select" "0: Select XCR1.PCF1D[7:0] as the compare data,1: Select XCR1.SCF1D[7:0] as the compare data,?,?" bitfld.long 0x8 9. "CF0RE,Control Field 0 Enable" "0: No Control Field 0,1: With Control Field 0" newline bitfld.long 0x8 8. "BFE,Break Field Enable" "0: No Break Field,1: With Break Field" bitfld.long 0x8 0.--1. "TCSS,Timer Count Clock Source Selection" "?,1: TCLK/4,?,?" line.long 0xC "XCR1,Simple LIN Control Register 1" hexmask.long.byte 0xC 24.--31. 1. "CF1CE,Control Field 1 Compare Bit Enable" hexmask.long.byte 0xC 16.--23. 1. "SCF1D,Secondary Compare Data for Control Field 1" newline hexmask.long.byte 0xC 8.--15. 1. "PCF1D,Priority Compare Data for Control Field 1" bitfld.long 0xC 5. "BMEN,Bit Rate Measurement Enable" "0: Bit rate measurement disabled,1: Bit rate measurement enabled" newline bitfld.long 0xC 4. "SDST,Start Frame Detection Enable" "0: Start Frame/Break Field detection disabled,1: Start Frame/Break Field detection enabled" bitfld.long 0xC 0. "TCST,Break Field Output Timer Count Start Trigger" "0: Break Field output timer count stopped,1: Break Field output timer count start" line.long 0x10 "XCR2,Simple LIN Control Register 2" hexmask.long.word 0x10 16.--31. 1. "BFLW,Break Field Length Setting" hexmask.long.byte 0x10 8.--15. 1. "CF0CE,Control Field 0 Compare Bit Enable" newline hexmask.long.byte 0x10 0.--7. 1. "CF0D,Control Field 0 Compare Data" rgroup.long 0x48++0x1B line.long 0x0 "CSR,Common Status Register" bitfld.long 0x0 31. "RDRF,Receive Data Full Flag" "0: Non-FIFO selected (CCR3.FM = 0): No received..,1: Non-FIFO selected (CCR3.FM = 0): Received data.." bitfld.long 0x0 30. "TEND,Transmit End Flag" "0: A character is being transmitted or standing by..,1: Character transfer has been completed or sending.." newline bitfld.long 0x0 29. "TDRE,Transmit Data Empty Flag" "0: Non-FIFO selected (CCR3.FM = 0): Transmit data..,1: Non-FIFO selected (CCR3.FM = 0): No transmit.." bitfld.long 0x0 28. "FER,Framing Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No framing..,1: Non-FIFO selected (CCR3.FM = 0): A framing error.." newline bitfld.long 0x0 27. "PER,Parity Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No parity error..,1: Non-FIFO selected (CCR3.FM = 0): A parity error.." bitfld.long 0x0 26. "MFF,Mode Fault Error Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.long 0x0 24. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.long 0x0 18. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred at address match..,1: A framing error has occurred at address match.." newline bitfld.long 0x0 17. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred at address match..,1: A parity error has occurred at address match.." bitfld.long 0x0 16. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" newline bitfld.long 0x0 15. "RXDMON,Serial Input Data Monitor Bit" "0: When RINV is 0 RXDn pin is the low level. When..,1: When RINV is 0 RXDn pin is the high level. When.." bitfld.long 0x0 4. "ERS,Error Signal Status Flag" "0: Error signal low not responded,1: Error signal low responded" line.long 0x4 "ISR,Simple IIC Status Register" bitfld.long 0x4 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.long 0x4 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" line.long 0x8 "FRSR,FIFO Receive Status Register" hexmask.long.byte 0x8 24.--29. 1. "FNUM,Framing Error Count" hexmask.long.byte 0x8 16.--21. 1. "PNUM,Parity Error Count" newline hexmask.long.byte 0x8 8.--13. 1. "R,Receive-FIFO Data Count" bitfld.long 0x8 0. "DR,Receive Data Ready Flag" "0: Receiving is in progress or no received data..,1: The following receive data is not received for a.." line.long 0xC "FTSR,FIFO Transmit Status Register" hexmask.long.byte 0xC 0.--5. 1. "T,Transmit-FIFO Data Count" line.long 0x10 "MSR,Manchester Status Register" bitfld.long 0x10 6. "RSYNC,Receive SYNC Data Bit" "0: The received start bit is DATA SYNC,1: The received start bit is COMMAND SYNC" bitfld.long 0x10 4. "MER,Manchester Error Flag" "0: No Manchester error occurred,1: Manchester error has occurred" newline bitfld.long 0x10 2. "SBER,Start Bit Error Flag" "0: No start bit error detected,1: Start bit error detected" bitfld.long 0x10 1. "SYER,SYNC Error Flag" "0: No receive SYNC error detected,1: Receive SYNC error detected" newline bitfld.long 0x10 0. "PFER,Preface Error Flag" "0: No preface error detected,1: Preface error detected" line.long 0x14 "XSR0,Simple LIN Status Register 0" hexmask.long.byte 0x14 24.--31. 1. "CF1RD,Control Field 1 received data" hexmask.long.byte 0x14 16.--23. 1. "CF0RD,Control Field 0 received data" newline bitfld.long 0x14 15. "AEDF,Active Edge Detection Flag" "0: No valid edge detected,1: Detected a valid edge" bitfld.long 0x14 14. "COF,Counter Overflow Flag" "0: Break Field detection counter has not overflowed,1: Break Field detection counter overflowed" newline bitfld.long 0x14 13. "PIBDF,Priority Interrupt Bit Detection Flag" "0: Priority interrupt bit is not detected,1: Priority interrupt bit is detected" bitfld.long 0x14 12. "CF1MF,Control Field 1 Compare Match Flag" "0: Control Field 1 received data does not match the..,1: Control Field 1 received data matches the.." newline bitfld.long 0x14 11. "CF0MF,Control Field 0 Compare Match Flag" "0: Control Field 0 received data does not match the..,1: Control Field 0 received data matches the.." bitfld.long 0x14 10. "BFDF,Break Field Detection Flag" "0: Break Field is not detected,1: Break Field is detected" newline bitfld.long 0x14 9. "BCDF,Bus Conflict Detection Flag" "0: No bus collision detected,1: Detected a bus collision" bitfld.long 0x14 8. "BFOF,Break Field Output Completion Flag" "0: Break Field is being output or is not being output,1: Completed BF output" newline bitfld.long 0x14 1. "RXDSF,RXDn Input Status Flag" "0: RXDn input to SCI is enabled,1: RXDn input to SCI is disabled" bitfld.long 0x14 0. "SFSF,Start Frame Status Flag" "0: Start Frame detection disabled or Start Frame..,1: Before Start Frame detection or during detection" line.long 0x18 "XSR1,Simple LIN Status Register 1" hexmask.long.word 0x18 0.--15. 1. "TCNT,Timer Count Capture Value" wgroup.long 0x68++0x13 line.long 0x0 "CFCLR,Common Flag Clear Register" bitfld.long 0x0 31. "RDRFC,RDRF Clear Bit" "0,1" bitfld.long 0x0 29. "TDREC,TDRE Clear Bit" "0,1" newline bitfld.long 0x0 28. "FERC,FER Clear Bit" "0,1" bitfld.long 0x0 27. "PERC,PER Clear Bit" "0,1" newline bitfld.long 0x0 26. "MFFC,MFF Clear Bit" "0,1" bitfld.long 0x0 24. "ORERC,ORER Clear Bit" "0,1" newline bitfld.long 0x0 18. "DFERC,DFER Clear Bit" "0,1" bitfld.long 0x0 17. "DPERC,DPER Clear Bit" "0,1" newline bitfld.long 0x0 16. "DCMFC,DCMF Clear Bit" "0,1" bitfld.long 0x0 4. "ERSC,ERS Clear Bit" "0,1" line.long 0x4 "ICFCLR,Simple IIC Flag Clear Register" bitfld.long 0x4 3. "IICSTIFC,IICSTIF Clear Bit" "0,1" line.long 0x8 "FFCLR,FIFO Flag Clear Register" bitfld.long 0x8 0. "DRC,DR Clear Bit" "0,1" line.long 0xC "MFCLR,Manchester Flag Clear Register" bitfld.long 0xC 4. "MERC,MER Clear Bit" "0,1" bitfld.long 0xC 2. "SBERC,SBER Clear Bit" "0,1" newline bitfld.long 0xC 1. "SYERC,SYER Clear Bit" "0,1" bitfld.long 0xC 0. "PFERC,PFER Clear Bit" "0,1" line.long 0x10 "XFCLR,Simple LIN Flag Clear Register" bitfld.long 0x10 15. "AEDC,AEDF Clear Bit" "0,1" bitfld.long 0x10 14. "COFC,COFF Clear Bit" "0,1" newline bitfld.long 0x10 13. "PIBDC,PIBDF Clear Bit" "0,1" bitfld.long 0x10 12. "CF1MC,CF1MF Clear Bit" "0,1" newline bitfld.long 0x10 11. "CF0MC,CF0MF Clear Bit" "0,1" bitfld.long 0x10 10. "BFDC,BFDF Clear Bit" "0,1" newline bitfld.long 0x10 9. "BCDC,BCDF Clear Bit" "0,1" bitfld.long 0x10 8. "BFOC,BFOF Clear Bit" "0,1" tree.end tree "SCI2_B_NS" base ad:0x50358200 rgroup.long 0x0++0x3 line.long 0x0 "RDR,Receive Data Register" bitfld.long 0x0 28. "FER,Framing error flag" "0,1" bitfld.long 0x0 27. "PER,Parity error flag" "0,1" newline bitfld.long 0x0 24. "ORER,Overrun Error flag" "0,1" bitfld.long 0x0 12. "FFER,FIFO framing error flag" "0: There is no framing error in the data read from..,1: There is framing error in the data read from the.." newline bitfld.long 0x0 11. "FPER,FIFO parity error flag" "0: There is no parity error in the data read from..,1: There is parity error in the data read from the.." bitfld.long 0x0 10. "DR,Receive data ready flag" "0,1" newline bitfld.long 0x0 9. "MPB,Multi-processor flag" "0: Data transmission cycles,1: ID transmission cycles" hexmask.long.word 0x0 0.--8. 1. "RDAT,Serial receive data" rgroup.byte 0x0++0x0 line.byte 0x0 "RDR_BY,Receive Data Register" bitfld.byte 0x0 4. "FER,Framing error flag" "0,1" bitfld.byte 0x0 3. "PER,Parity error flag" "0,1" newline bitfld.byte 0x0 0. "ORER,Overrun Error flag" "0,1" group.long 0x4++0x3 line.long 0x0 "TDR,Transmit Data Register" bitfld.long 0x0 12. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.long 0x0 9. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline hexmask.long.word 0x0 0.--8. 1. "TDAT,Serial transmit data" group.byte 0x4++0x1 line.byte 0x0 "TDRLL,Transmit Data Register" line.byte 0x1 "TDRLH,Transmit Data Register" bitfld.byte 0x1 4. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.byte 0x1 1. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline bitfld.byte 0x1 0. "TDAT,Serial transmit data" "0,1" group.long 0x8++0x13 line.long 0x0 "CCR0,Common Control Register 0" bitfld.long 0x0 24. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled,1: SSn pin function is enabled" bitfld.long 0x0 21. "TEIE,Transmit End Interrupt Enable" "0: SCIn_TEI interrupt request is disabled,1: SCIn_TEI interrupt request is enabled" newline bitfld.long 0x0 20. "TIE,Transmit Interrupt Enable" "0: SCIn_TXI interrupt request is disabled,1: SCIn_TXI interrupt request is enabled" bitfld.long 0x0 16. "RIE,Receive Interrupt Enable" "0: SCIn_RXI and SCIn_ERI interrupt requests are..,1: SCIn_RXI and SCIn_ERI interrupt requests are.." newline bitfld.long 0x0 10. "IDSEL,ID Frame Select" "0: Compare data irrespective of the value of the..,1: Compare data only when the MPB bit is 1 (ID frame)" bitfld.long 0x0 9. "DCME,Data Compare Match Enable" "0: Address match function is disabled,1: Address match function is enabled" newline bitfld.long 0x0 8. "MPIE,Multi-Processor Interrupt Enable" "0: Non-multi-processor reception,1: Multi-processor reception When the data with the.." bitfld.long 0x0 4. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" newline bitfld.long 0x0 0. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" line.long 0x4 "CCR1,Common Control Register 1" bitfld.long 0x4 29. "NFM,Noise Filter Mode" "0: 3-point matching mode,1: Majority vote mode" bitfld.long 0x4 28. "NFEN,Digital Noise Filter Function Enable" "0: In Asynchronous Manchester Simple LIN modes:..,1: In Asynchronous Manchester Simple LIN modes:.." newline bitfld.long 0x4 24.--26. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: The on-chip baud rate generator source clock..,?,?,?,?,?,?" bitfld.long 0x4 20. "SHARPS,Half-Duplex Communication Select" "0: TXDn pin RXDn pin independent,1: TXDn/RXDn pin combination use (half-duplex.." newline bitfld.long 0x4 16. "SPLP,Loopback Control" "0: Normal mode,1: Loopback mode" bitfld.long 0x4 13. "RINV,RXD Invert" "0: Received data from RXDn is not inverted and input,1: Received data from RXDn is inverted and input" newline bitfld.long 0x4 12. "TINV,TXD Invert" "0: Transmit data is not inverted and output to TXDn,1: Transmit data is inverted and output to TXDn" bitfld.long 0x4 9. "PM,Parity Mode" "0: Selects even parity,1: Selects odd parity" newline bitfld.long 0x4 8. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.." bitfld.long 0x4 5. "SPB2IO,Serial Port Break I/O" "0: The value of SPB2DT bit is not output in TXDn pin,1: The value of SPB2DT bit is output in TXDn pin" newline bitfld.long 0x4 4. "SPB2DT,Serial Port Break Data Select" "0: When TINV is 0 low level is output in TXDn pin.,1: When TINV is 0 high level is output in TXDn pin." bitfld.long 0x4 1. "CTSPEN,CTS External Pin Enable" "0: Alternate setting to use CTS and RTS functions..,1: Dedicated setting for separately using CTS and.." newline bitfld.long 0x4 0. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled" line.long 0x8 "CCR2,Common Control Register 2" hexmask.long.byte 0x8 24.--31. 1. "MDDR,Modulation Duty Setting" bitfld.long 0x8 20.--21. "CKS,Clock Select" "0: TCLK clock (n = 0),1: TCLK/4 clock (n = 1),?,?" newline bitfld.long 0x8 16. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled,1: Bit rate modulation function is enabled" hexmask.long.byte 0x8 8.--15. 1. "BRR,Bit Rate Setting" newline bitfld.long 0x8 7. "ABCSE2,Asynchronous Mode Extended Base Clock Select 2" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 4 base clock cycles for 1-bit.." bitfld.long 0x8 6. "ABCSE,Asynchronous Mode Extended Base Clock Select" "0: Clock cycles for 1-bit period is determined by..,1: Baud rate is 6 base clock cycles for 1-bit.." newline bitfld.long 0x8 5. "ABCS,Asynchronous Mode Base Clock Select" "0: Selects 16 base clock cycles for 1-bit period,1: Selects 8 base clock cycles for 1-bit period" bitfld.long 0x8 4. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.long 0x8 0.--2. "BCP,Base Clock Pulse" "0: 93 clock cycles (S = 93),1: 128 clock cycles (S = 128),?,?,?,?,?,?" line.long 0xC "CCR3,Common Control Register 3" bitfld.long 0xC 29. "BLK,Block Transfer Mode" "0: Non-block transfer mode operation,1: Block transfer mode operation" bitfld.long 0xC 28. "GM,GSM Mode" "0: Non-GSM mode operation,1: GSM mode operation" newline bitfld.long 0xC 26. "ACS0,Asynchronous Mode Clock Source Select" "0: External clock input,1: Logical AND of compare matches output from the.." bitfld.long 0xC 24.--25. "CKE,Clock Enable" "0,1,2,3" newline bitfld.long 0xC 21. "DEN,Driver Enable" "0: RS-485 driver control function disabled,1: RS-485 driver control function enabled" bitfld.long 0xC 20. "FM,FIFO Mode Select" "0: TDR register and RDR register are non-FIFO..,1: TDR register and RDR register are FIFO buffer.." newline bitfld.long 0xC 19. "MP,Multi-Processor Mode" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" bitfld.long 0xC 16.--18. "MOD,Communication Mode Select" "0: Asynchronous mode (multi-processor mode),1: Smart card interface mode,?,?,?,?,?,?" newline bitfld.long 0xC 15. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.long 0xC 14. "STP,Stop Bit Length" "0: 1 stop bit/break delimiter length is 1-bit,1: 2 stop bits/break delimiter length is 2-bit" newline bitfld.long 0xC 13. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted to TSR as is. RSR..,1: TDR contents are inverted before being.." bitfld.long 0xC 12. "LSBF,LSB First select" "0: MSB-first,1: LSB-first" newline bitfld.long 0xC 8.--9. "CHR,Character Length" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 9-bit data length,?,?" bitfld.long 0xC 7. "BPEN,Synchronizer Bypass Enable" "0: Synchronizer circuit is not bypassed,1: Synchronizer circuit is bypassed" newline bitfld.long 0xC 1. "CPOL,Clock Polarity Select" "0: SCKn in idle state is 0,1: SCKn in idle state is 1" bitfld.long 0xC 0. "CPHA,Clock Phase Select" "0: Data is sampled at an odd edge and changes at an..,1: Data changes at an odd edge and is sampled at an.." line.long 0x10 "CCR4,Common Control Register 4" bitfld.long 0x10 31. "AET,Adjustment Edge for Transmit Timing" "0: When CCR1.TINV is 0 adjust the rising edge..,1: When CCR1.TINV is 0 adjust the falling edge.." bitfld.long 0x10 28.--30. "ATT,Adjustment Value for Transmit Timing" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "AJD,Adjustment Direction for Receive Sampling Timing" "0: The sampling timing is adjusted backward to the..,1: The sampling timing is adjusted forward to the.." bitfld.long 0x10 24.--26. "AST,Adjustment Value for Receive Sampling Timing" "0: Setting prohibited,1: 2-TCLK delay,?,?,?,?,?,?" newline bitfld.long 0x10 19. "SCKSEL,Master receive clock selection" "0: Master receive clock is disabled,1: Master receive clock is enabled" bitfld.long 0x10 17. "ATEN,Adjust Transmit Timing Enable" "0: Adjust transmit timing disabled,1: Adjust transmit timing enabled" newline bitfld.long 0x10 16. "ASEN,Adjust Receive Sampling Timing Enable" "0: Adjust sampling timing disabled,1: Adjust sampling timing enabled" hexmask.long.word 0x10 0.--8. 1. "CMPD,Compare Match Data" rgroup.byte 0x1C++0x0 line.byte 0x0 "CESR,Communication Enable Status Register" bitfld.byte 0x0 4. "TIST,TE Internal Status" "0: TE signal internal state value 0,1: TE signal internal state value 1" bitfld.byte 0x0 0. "RIST,RE Internal Status" "0: RE signal internal state value 0,1: RE signal internal state value 1" group.long 0x20++0x7 line.long 0x0 "ICR,Simple IIC Control Register" bitfld.long 0x0 22.--23. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition,?,?" bitfld.long 0x0 20.--21. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition,?,?" newline bitfld.long 0x0 18. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated" bitfld.long 0x0 17. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated,1: A restart condition is generated" newline bitfld.long 0x0 16. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated,1: A start condition is generated" bitfld.long 0x0 13. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.long 0x0 9. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" bitfld.long 0x0 8. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts" newline hexmask.long.byte 0x0 0.--4. 1. "IICDL,SDA Delay Output Select" line.long 0x4 "FCR,FIFO Control Register" hexmask.long.byte 0x4 24.--28. 1. "RSTRG,RTS Output Active Trigger Number Select" bitfld.long 0x4 23. "RFRST,Receive FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Receive-FIFO(RDR.." newline hexmask.long.byte 0x4 16.--20. 1. "RTRG,Receive FIFO Data Trigger Number" bitfld.long 0x4 15. "TFRST,Transmit FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Transmit-FIFO (TDR.." newline hexmask.long.byte 0x4 8.--12. 1. "TTRG,Transmit FIFO Data Trigger Number" bitfld.long 0x4 0. "DRES,Receive Data Ready Error Select Bit" "0: Reception data full interrupt (SCIn_RXI),1: Receive error interrupt (SCIn_ERI)" group.long 0x2C++0x13 line.long 0x0 "MCR,Manchester Control Register" bitfld.long 0x0 26. "SBEREN,Start Bit Error Enable" "0: Does not handle a start bit error as an..,1: Handles a start bit error as an interrupt source" bitfld.long 0x0 25. "SYEREN,Receive SYNC Error Enable" "0: Does not handle a receive SYNC error as an..,1: Handles a receive SYNC error as an interrupt.." newline bitfld.long 0x0 24. "PFEREN,Preface Error Enable" "0: Does not handle a preface error as an interrupt..,1: Handles a preface error as an interrupt source" bitfld.long 0x0 20.--21. "RPPAT,Receive Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 16.--19. 1. "RPLEN,Receive Preface Length" bitfld.long 0x0 12.--13. "TPPAT,Transmit Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "TPLEN,Transmit Preface Length" bitfld.long 0x0 6. "SBSEL,Start Bit Select" "0: The start bit area consists of one bit,1: The start bit area consists of three bits.." newline bitfld.long 0x0 5. "SYNSEL,SYNC Select" "0: The start bit pattern is set with the SYNVAL bit,1: The start bit pattern is set with the TSYNC bit" bitfld.long 0x0 4. "SYNVAL,SYNC value Setting" "0,1" newline bitfld.long 0x0 2. "ERTEN,Manchester Edge Retiming Enable" "0: Disables the receive retiming function,1: Enables the receive retiming function" bitfld.long 0x0 1. "TMPOL,Polarity of Transmit Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." newline bitfld.long 0x0 0. "RMPOL,Polarity of Received Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." line.long 0x4 "DCR,Driver Control Register" hexmask.long.byte 0x4 16.--20. 1. "DENGT,Driver Negate Time" hexmask.long.byte 0x4 8.--12. 1. "DEAST,Driver Assertion Time" newline bitfld.long 0x4 0. "DEPOL,Driver Effective Polarity Select" "0: The DEn signal is active-high,1: The DEn signal is active-low" line.long 0x8 "XCR0,Simple LIN Control Register 0" bitfld.long 0x8 24.--25. "BCCS,Bus Conflict Detection Clock Selection" "0: Base clock,1: Base clock/2,?,?" bitfld.long 0x8 22. "AEDIE,Active Edge Detection Interrupt Enable" "0: Active edge detection interrupt disabled,1: Active edge detection interrupt enabled" newline bitfld.long 0x8 21. "COFIE,Counter Overflow Interrupt Enable" "0: Counter overflow is not included in SCIn_ERI..,1: Counter overflow is included in SCIn_ERI.." bitfld.long 0x8 20. "BFDIE,Break Field Detection Interrupt Enable" "0: Break Field detection interrupt disabled,1: Break Field detection interrupt enabled" newline bitfld.long 0x8 17. "BCDIE,Bus Conflict Detection Interrupt Enable" "0: Bus conflict detection is not included in..,1: Bus conflict detection is included in SCIn_ERI.." bitfld.long 0x8 16. "BFOIE,Break Field Output Completion Interrupt Enable" "0: Break Field output completion is not included in..,1: Break Field output completion is included in.." newline bitfld.long 0x8 13.--15. "PIBS,Priority Interrupt Bit Select" "0: Bit 0 of Control Field 1,1: Bit 1 of Control Field 1,?,?,?,?,?,?" bitfld.long 0x8 12. "PIBE,Priority Interrupt Bit Enable" "0: Priority interrupt bit disabled,1: Priority interrupt bit enabled" newline bitfld.long 0x8 10.--11. "CF1DS,Control Field1 Compare Data Select" "0: Select XCR1.PCF1D[7:0] as the compare data,1: Select XCR1.SCF1D[7:0] as the compare data,?,?" bitfld.long 0x8 9. "CF0RE,Control Field 0 Enable" "0: No Control Field 0,1: With Control Field 0" newline bitfld.long 0x8 8. "BFE,Break Field Enable" "0: No Break Field,1: With Break Field" bitfld.long 0x8 0.--1. "TCSS,Timer Count Clock Source Selection" "?,1: TCLK/4,?,?" line.long 0xC "XCR1,Simple LIN Control Register 1" hexmask.long.byte 0xC 24.--31. 1. "CF1CE,Control Field 1 Compare Bit Enable" hexmask.long.byte 0xC 16.--23. 1. "SCF1D,Secondary Compare Data for Control Field 1" newline hexmask.long.byte 0xC 8.--15. 1. "PCF1D,Priority Compare Data for Control Field 1" bitfld.long 0xC 5. "BMEN,Bit Rate Measurement Enable" "0: Bit rate measurement disabled,1: Bit rate measurement enabled" newline bitfld.long 0xC 4. "SDST,Start Frame Detection Enable" "0: Start Frame/Break Field detection disabled,1: Start Frame/Break Field detection enabled" bitfld.long 0xC 0. "TCST,Break Field Output Timer Count Start Trigger" "0: Break Field output timer count stopped,1: Break Field output timer count start" line.long 0x10 "XCR2,Simple LIN Control Register 2" hexmask.long.word 0x10 16.--31. 1. "BFLW,Break Field Length Setting" hexmask.long.byte 0x10 8.--15. 1. "CF0CE,Control Field 0 Compare Bit Enable" newline hexmask.long.byte 0x10 0.--7. 1. "CF0D,Control Field 0 Compare Data" rgroup.long 0x48++0x1B line.long 0x0 "CSR,Common Status Register" bitfld.long 0x0 31. "RDRF,Receive Data Full Flag" "0: Non-FIFO selected (CCR3.FM = 0): No received..,1: Non-FIFO selected (CCR3.FM = 0): Received data.." bitfld.long 0x0 30. "TEND,Transmit End Flag" "0: A character is being transmitted or standing by..,1: Character transfer has been completed or sending.." newline bitfld.long 0x0 29. "TDRE,Transmit Data Empty Flag" "0: Non-FIFO selected (CCR3.FM = 0): Transmit data..,1: Non-FIFO selected (CCR3.FM = 0): No transmit.." bitfld.long 0x0 28. "FER,Framing Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No framing..,1: Non-FIFO selected (CCR3.FM = 0): A framing error.." newline bitfld.long 0x0 27. "PER,Parity Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No parity error..,1: Non-FIFO selected (CCR3.FM = 0): A parity error.." bitfld.long 0x0 26. "MFF,Mode Fault Error Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.long 0x0 24. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.long 0x0 18. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred at address match..,1: A framing error has occurred at address match.." newline bitfld.long 0x0 17. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred at address match..,1: A parity error has occurred at address match.." bitfld.long 0x0 16. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" newline bitfld.long 0x0 15. "RXDMON,Serial Input Data Monitor Bit" "0: When RINV is 0 RXDn pin is the low level. When..,1: When RINV is 0 RXDn pin is the high level. When.." bitfld.long 0x0 4. "ERS,Error Signal Status Flag" "0: Error signal low not responded,1: Error signal low responded" line.long 0x4 "ISR,Simple IIC Status Register" bitfld.long 0x4 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.long 0x4 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" line.long 0x8 "FRSR,FIFO Receive Status Register" hexmask.long.byte 0x8 24.--29. 1. "FNUM,Framing Error Count" hexmask.long.byte 0x8 16.--21. 1. "PNUM,Parity Error Count" newline hexmask.long.byte 0x8 8.--13. 1. "R,Receive-FIFO Data Count" bitfld.long 0x8 0. "DR,Receive Data Ready Flag" "0: Receiving is in progress or no received data..,1: The following receive data is not received for a.." line.long 0xC "FTSR,FIFO Transmit Status Register" hexmask.long.byte 0xC 0.--5. 1. "T,Transmit-FIFO Data Count" line.long 0x10 "MSR,Manchester Status Register" bitfld.long 0x10 6. "RSYNC,Receive SYNC Data Bit" "0: The received start bit is DATA SYNC,1: The received start bit is COMMAND SYNC" bitfld.long 0x10 4. "MER,Manchester Error Flag" "0: No Manchester error occurred,1: Manchester error has occurred" newline bitfld.long 0x10 2. "SBER,Start Bit Error Flag" "0: No start bit error detected,1: Start bit error detected" bitfld.long 0x10 1. "SYER,SYNC Error Flag" "0: No receive SYNC error detected,1: Receive SYNC error detected" newline bitfld.long 0x10 0. "PFER,Preface Error Flag" "0: No preface error detected,1: Preface error detected" line.long 0x14 "XSR0,Simple LIN Status Register 0" hexmask.long.byte 0x14 24.--31. 1. "CF1RD,Control Field 1 received data" hexmask.long.byte 0x14 16.--23. 1. "CF0RD,Control Field 0 received data" newline bitfld.long 0x14 15. "AEDF,Active Edge Detection Flag" "0: No valid edge detected,1: Detected a valid edge" bitfld.long 0x14 14. "COF,Counter Overflow Flag" "0: Break Field detection counter has not overflowed,1: Break Field detection counter overflowed" newline bitfld.long 0x14 13. "PIBDF,Priority Interrupt Bit Detection Flag" "0: Priority interrupt bit is not detected,1: Priority interrupt bit is detected" bitfld.long 0x14 12. "CF1MF,Control Field 1 Compare Match Flag" "0: Control Field 1 received data does not match the..,1: Control Field 1 received data matches the.." newline bitfld.long 0x14 11. "CF0MF,Control Field 0 Compare Match Flag" "0: Control Field 0 received data does not match the..,1: Control Field 0 received data matches the.." bitfld.long 0x14 10. "BFDF,Break Field Detection Flag" "0: Break Field is not detected,1: Break Field is detected" newline bitfld.long 0x14 9. "BCDF,Bus Conflict Detection Flag" "0: No bus collision detected,1: Detected a bus collision" bitfld.long 0x14 8. "BFOF,Break Field Output Completion Flag" "0: Break Field is being output or is not being output,1: Completed BF output" newline bitfld.long 0x14 1. "RXDSF,RXDn Input Status Flag" "0: RXDn input to SCI is enabled,1: RXDn input to SCI is disabled" bitfld.long 0x14 0. "SFSF,Start Frame Status Flag" "0: Start Frame detection disabled or Start Frame..,1: Before Start Frame detection or during detection" line.long 0x18 "XSR1,Simple LIN Status Register 1" hexmask.long.word 0x18 0.--15. 1. "TCNT,Timer Count Capture Value" wgroup.long 0x68++0x13 line.long 0x0 "CFCLR,Common Flag Clear Register" bitfld.long 0x0 31. "RDRFC,RDRF Clear Bit" "0,1" bitfld.long 0x0 29. "TDREC,TDRE Clear Bit" "0,1" newline bitfld.long 0x0 28. "FERC,FER Clear Bit" "0,1" bitfld.long 0x0 27. "PERC,PER Clear Bit" "0,1" newline bitfld.long 0x0 26. "MFFC,MFF Clear Bit" "0,1" bitfld.long 0x0 24. "ORERC,ORER Clear Bit" "0,1" newline bitfld.long 0x0 18. "DFERC,DFER Clear Bit" "0,1" bitfld.long 0x0 17. "DPERC,DPER Clear Bit" "0,1" newline bitfld.long 0x0 16. "DCMFC,DCMF Clear Bit" "0,1" bitfld.long 0x0 4. "ERSC,ERS Clear Bit" "0,1" line.long 0x4 "ICFCLR,Simple IIC Flag Clear Register" bitfld.long 0x4 3. "IICSTIFC,IICSTIF Clear Bit" "0,1" line.long 0x8 "FFCLR,FIFO Flag Clear Register" bitfld.long 0x8 0. "DRC,DR Clear Bit" "0,1" line.long 0xC "MFCLR,Manchester Flag Clear Register" bitfld.long 0xC 4. "MERC,MER Clear Bit" "0,1" bitfld.long 0xC 2. "SBERC,SBER Clear Bit" "0,1" newline bitfld.long 0xC 1. "SYERC,SYER Clear Bit" "0,1" bitfld.long 0xC 0. "PFERC,PFER Clear Bit" "0,1" line.long 0x10 "XFCLR,Simple LIN Flag Clear Register" bitfld.long 0x10 15. "AEDC,AEDF Clear Bit" "0,1" bitfld.long 0x10 14. "COFC,COFF Clear Bit" "0,1" newline bitfld.long 0x10 13. "PIBDC,PIBDF Clear Bit" "0,1" bitfld.long 0x10 12. "CF1MC,CF1MF Clear Bit" "0,1" newline bitfld.long 0x10 11. "CF0MC,CF0MF Clear Bit" "0,1" bitfld.long 0x10 10. "BFDC,BFDF Clear Bit" "0,1" newline bitfld.long 0x10 9. "BCDC,BCDF Clear Bit" "0,1" bitfld.long 0x10 8. "BFOC,BFOF Clear Bit" "0,1" tree.end tree "SCI3_B" base ad:0x40358300 rgroup.long 0x0++0x3 line.long 0x0 "RDR,Receive Data Register" bitfld.long 0x0 28. "FER,Framing error flag" "0,1" bitfld.long 0x0 27. "PER,Parity error flag" "0,1" newline bitfld.long 0x0 24. "ORER,Overrun Error flag" "0,1" bitfld.long 0x0 12. "FFER,FIFO framing error flag" "0: There is no framing error in the data read from..,1: There is framing error in the data read from the.." newline bitfld.long 0x0 11. "FPER,FIFO parity error flag" "0: There is no parity error in the data read from..,1: There is parity error in the data read from the.." bitfld.long 0x0 10. "DR,Receive data ready flag" "0,1" newline bitfld.long 0x0 9. "MPB,Multi-processor flag" "0: Data transmission cycles,1: ID transmission cycles" hexmask.long.word 0x0 0.--8. 1. "RDAT,Serial receive data" rgroup.byte 0x0++0x0 line.byte 0x0 "RDR_BY,Receive Data Register" bitfld.byte 0x0 4. "FER,Framing error flag" "0,1" bitfld.byte 0x0 3. "PER,Parity error flag" "0,1" newline bitfld.byte 0x0 0. "ORER,Overrun Error flag" "0,1" group.long 0x4++0x3 line.long 0x0 "TDR,Transmit Data Register" bitfld.long 0x0 12. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.long 0x0 9. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline hexmask.long.word 0x0 0.--8. 1. "TDAT,Serial transmit data" group.byte 0x4++0x1 line.byte 0x0 "TDRLL,Transmit Data Register" line.byte 0x1 "TDRLH,Transmit Data Register" bitfld.byte 0x1 4. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.byte 0x1 1. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline bitfld.byte 0x1 0. "TDAT,Serial transmit data" "0,1" group.long 0x8++0x13 line.long 0x0 "CCR0,Common Control Register 0" bitfld.long 0x0 24. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled,1: SSn pin function is enabled" bitfld.long 0x0 21. "TEIE,Transmit End Interrupt Enable" "0: SCIn_TEI interrupt request is disabled,1: SCIn_TEI interrupt request is enabled" newline bitfld.long 0x0 20. "TIE,Transmit Interrupt Enable" "0: SCIn_TXI interrupt request is disabled,1: SCIn_TXI interrupt request is enabled" bitfld.long 0x0 16. "RIE,Receive Interrupt Enable" "0: SCIn_RXI and SCIn_ERI interrupt requests are..,1: SCIn_RXI and SCIn_ERI interrupt requests are.." newline bitfld.long 0x0 10. "IDSEL,ID Frame Select" "0: Compare data irrespective of the value of the..,1: Compare data only when the MPB bit is 1 (ID frame)" bitfld.long 0x0 9. "DCME,Data Compare Match Enable" "0: Address match function is disabled,1: Address match function is enabled" newline bitfld.long 0x0 8. "MPIE,Multi-Processor Interrupt Enable" "0: Non-multi-processor reception,1: Multi-processor reception When the data with the.." bitfld.long 0x0 4. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" newline bitfld.long 0x0 0. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" line.long 0x4 "CCR1,Common Control Register 1" bitfld.long 0x4 29. "NFM,Noise Filter Mode" "0: 3-point matching mode,1: Majority vote mode" bitfld.long 0x4 28. "NFEN,Digital Noise Filter Function Enable" "0: In Asynchronous Manchester Simple LIN modes:..,1: In Asynchronous Manchester Simple LIN modes:.." newline bitfld.long 0x4 24.--26. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: The on-chip baud rate generator source clock..,?,?,?,?,?,?" bitfld.long 0x4 20. "SHARPS,Half-Duplex Communication Select" "0: TXDn pin RXDn pin independent,1: TXDn/RXDn pin combination use (half-duplex.." newline bitfld.long 0x4 16. "SPLP,Loopback Control" "0: Normal mode,1: Loopback mode" bitfld.long 0x4 13. "RINV,RXD Invert" "0: Received data from RXDn is not inverted and input,1: Received data from RXDn is inverted and input" newline bitfld.long 0x4 12. "TINV,TXD Invert" "0: Transmit data is not inverted and output to TXDn,1: Transmit data is inverted and output to TXDn" bitfld.long 0x4 9. "PM,Parity Mode" "0: Selects even parity,1: Selects odd parity" newline bitfld.long 0x4 8. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.." bitfld.long 0x4 5. "SPB2IO,Serial Port Break I/O" "0: The value of SPB2DT bit is not output in TXDn pin,1: The value of SPB2DT bit is output in TXDn pin" newline bitfld.long 0x4 4. "SPB2DT,Serial Port Break Data Select" "0: When TINV is 0 low level is output in TXDn pin.,1: When TINV is 0 high level is output in TXDn pin." bitfld.long 0x4 1. "CTSPEN,CTS External Pin Enable" "0: Alternate setting to use CTS and RTS functions..,1: Dedicated setting for separately using CTS and.." newline bitfld.long 0x4 0. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled" line.long 0x8 "CCR2,Common Control Register 2" hexmask.long.byte 0x8 24.--31. 1. "MDDR,Modulation Duty Setting" bitfld.long 0x8 20.--21. "CKS,Clock Select" "0: TCLK clock (n = 0),1: TCLK/4 clock (n = 1),?,?" newline bitfld.long 0x8 16. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled,1: Bit rate modulation function is enabled" hexmask.long.byte 0x8 8.--15. 1. "BRR,Bit Rate Setting" newline bitfld.long 0x8 7. "ABCSE2,Asynchronous Mode Extended Base Clock Select 2" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 4 base clock cycles for 1-bit.." bitfld.long 0x8 6. "ABCSE,Asynchronous Mode Extended Base Clock Select" "0: Clock cycles for 1-bit period is determined by..,1: Baud rate is 6 base clock cycles for 1-bit.." newline bitfld.long 0x8 5. "ABCS,Asynchronous Mode Base Clock Select" "0: Selects 16 base clock cycles for 1-bit period,1: Selects 8 base clock cycles for 1-bit period" bitfld.long 0x8 4. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.long 0x8 0.--2. "BCP,Base Clock Pulse" "0: 93 clock cycles (S = 93),1: 128 clock cycles (S = 128),?,?,?,?,?,?" line.long 0xC "CCR3,Common Control Register 3" bitfld.long 0xC 29. "BLK,Block Transfer Mode" "0: Non-block transfer mode operation,1: Block transfer mode operation" bitfld.long 0xC 28. "GM,GSM Mode" "0: Non-GSM mode operation,1: GSM mode operation" newline bitfld.long 0xC 26. "ACS0,Asynchronous Mode Clock Source Select" "0: External clock input,1: Logical AND of compare matches output from the.." bitfld.long 0xC 24.--25. "CKE,Clock Enable" "0,1,2,3" newline bitfld.long 0xC 21. "DEN,Driver Enable" "0: RS-485 driver control function disabled,1: RS-485 driver control function enabled" bitfld.long 0xC 20. "FM,FIFO Mode Select" "0: TDR register and RDR register are non-FIFO..,1: TDR register and RDR register are FIFO buffer.." newline bitfld.long 0xC 19. "MP,Multi-Processor Mode" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" bitfld.long 0xC 16.--18. "MOD,Communication Mode Select" "0: Asynchronous mode (multi-processor mode),1: Smart card interface mode,?,?,?,?,?,?" newline bitfld.long 0xC 15. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.long 0xC 14. "STP,Stop Bit Length" "0: 1 stop bit/break delimiter length is 1-bit,1: 2 stop bits/break delimiter length is 2-bit" newline bitfld.long 0xC 13. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted to TSR as is. RSR..,1: TDR contents are inverted before being.." bitfld.long 0xC 12. "LSBF,LSB First select" "0: MSB-first,1: LSB-first" newline bitfld.long 0xC 8.--9. "CHR,Character Length" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 9-bit data length,?,?" bitfld.long 0xC 7. "BPEN,Synchronizer Bypass Enable" "0: Synchronizer circuit is not bypassed,1: Synchronizer circuit is bypassed" newline bitfld.long 0xC 1. "CPOL,Clock Polarity Select" "0: SCKn in idle state is 0,1: SCKn in idle state is 1" bitfld.long 0xC 0. "CPHA,Clock Phase Select" "0: Data is sampled at an odd edge and changes at an..,1: Data changes at an odd edge and is sampled at an.." line.long 0x10 "CCR4,Common Control Register 4" bitfld.long 0x10 31. "AET,Adjustment Edge for Transmit Timing" "0: When CCR1.TINV is 0 adjust the rising edge..,1: When CCR1.TINV is 0 adjust the falling edge.." bitfld.long 0x10 28.--30. "ATT,Adjustment Value for Transmit Timing" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "AJD,Adjustment Direction for Receive Sampling Timing" "0: The sampling timing is adjusted backward to the..,1: The sampling timing is adjusted forward to the.." bitfld.long 0x10 24.--26. "AST,Adjustment Value for Receive Sampling Timing" "0: Setting prohibited,1: 2-TCLK delay,?,?,?,?,?,?" newline bitfld.long 0x10 19. "SCKSEL,Master receive clock selection" "0: Master receive clock is disabled,1: Master receive clock is enabled" bitfld.long 0x10 17. "ATEN,Adjust Transmit Timing Enable" "0: Adjust transmit timing disabled,1: Adjust transmit timing enabled" newline bitfld.long 0x10 16. "ASEN,Adjust Receive Sampling Timing Enable" "0: Adjust sampling timing disabled,1: Adjust sampling timing enabled" hexmask.long.word 0x10 0.--8. 1. "CMPD,Compare Match Data" rgroup.byte 0x1C++0x0 line.byte 0x0 "CESR,Communication Enable Status Register" bitfld.byte 0x0 4. "TIST,TE Internal Status" "0: TE signal internal state value 0,1: TE signal internal state value 1" bitfld.byte 0x0 0. "RIST,RE Internal Status" "0: RE signal internal state value 0,1: RE signal internal state value 1" group.long 0x20++0x7 line.long 0x0 "ICR,Simple IIC Control Register" bitfld.long 0x0 22.--23. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition,?,?" bitfld.long 0x0 20.--21. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition,?,?" newline bitfld.long 0x0 18. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated" bitfld.long 0x0 17. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated,1: A restart condition is generated" newline bitfld.long 0x0 16. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated,1: A start condition is generated" bitfld.long 0x0 13. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.long 0x0 9. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" bitfld.long 0x0 8. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts" newline hexmask.long.byte 0x0 0.--4. 1. "IICDL,SDA Delay Output Select" line.long 0x4 "FCR,FIFO Control Register" hexmask.long.byte 0x4 24.--28. 1. "RSTRG,RTS Output Active Trigger Number Select" bitfld.long 0x4 23. "RFRST,Receive FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Receive-FIFO(RDR.." newline hexmask.long.byte 0x4 16.--20. 1. "RTRG,Receive FIFO Data Trigger Number" bitfld.long 0x4 15. "TFRST,Transmit FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Transmit-FIFO (TDR.." newline hexmask.long.byte 0x4 8.--12. 1. "TTRG,Transmit FIFO Data Trigger Number" bitfld.long 0x4 0. "DRES,Receive Data Ready Error Select Bit" "0: Reception data full interrupt (SCIn_RXI),1: Receive error interrupt (SCIn_ERI)" group.long 0x2C++0x13 line.long 0x0 "MCR,Manchester Control Register" bitfld.long 0x0 26. "SBEREN,Start Bit Error Enable" "0: Does not handle a start bit error as an..,1: Handles a start bit error as an interrupt source" bitfld.long 0x0 25. "SYEREN,Receive SYNC Error Enable" "0: Does not handle a receive SYNC error as an..,1: Handles a receive SYNC error as an interrupt.." newline bitfld.long 0x0 24. "PFEREN,Preface Error Enable" "0: Does not handle a preface error as an interrupt..,1: Handles a preface error as an interrupt source" bitfld.long 0x0 20.--21. "RPPAT,Receive Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 16.--19. 1. "RPLEN,Receive Preface Length" bitfld.long 0x0 12.--13. "TPPAT,Transmit Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "TPLEN,Transmit Preface Length" bitfld.long 0x0 6. "SBSEL,Start Bit Select" "0: The start bit area consists of one bit,1: The start bit area consists of three bits.." newline bitfld.long 0x0 5. "SYNSEL,SYNC Select" "0: The start bit pattern is set with the SYNVAL bit,1: The start bit pattern is set with the TSYNC bit" bitfld.long 0x0 4. "SYNVAL,SYNC value Setting" "0,1" newline bitfld.long 0x0 2. "ERTEN,Manchester Edge Retiming Enable" "0: Disables the receive retiming function,1: Enables the receive retiming function" bitfld.long 0x0 1. "TMPOL,Polarity of Transmit Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." newline bitfld.long 0x0 0. "RMPOL,Polarity of Received Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." line.long 0x4 "DCR,Driver Control Register" hexmask.long.byte 0x4 16.--20. 1. "DENGT,Driver Negate Time" hexmask.long.byte 0x4 8.--12. 1. "DEAST,Driver Assertion Time" newline bitfld.long 0x4 0. "DEPOL,Driver Effective Polarity Select" "0: The DEn signal is active-high,1: The DEn signal is active-low" line.long 0x8 "XCR0,Simple LIN Control Register 0" bitfld.long 0x8 24.--25. "BCCS,Bus Conflict Detection Clock Selection" "0: Base clock,1: Base clock/2,?,?" bitfld.long 0x8 22. "AEDIE,Active Edge Detection Interrupt Enable" "0: Active edge detection interrupt disabled,1: Active edge detection interrupt enabled" newline bitfld.long 0x8 21. "COFIE,Counter Overflow Interrupt Enable" "0: Counter overflow is not included in SCIn_ERI..,1: Counter overflow is included in SCIn_ERI.." bitfld.long 0x8 20. "BFDIE,Break Field Detection Interrupt Enable" "0: Break Field detection interrupt disabled,1: Break Field detection interrupt enabled" newline bitfld.long 0x8 17. "BCDIE,Bus Conflict Detection Interrupt Enable" "0: Bus conflict detection is not included in..,1: Bus conflict detection is included in SCIn_ERI.." bitfld.long 0x8 16. "BFOIE,Break Field Output Completion Interrupt Enable" "0: Break Field output completion is not included in..,1: Break Field output completion is included in.." newline bitfld.long 0x8 13.--15. "PIBS,Priority Interrupt Bit Select" "0: Bit 0 of Control Field 1,1: Bit 1 of Control Field 1,?,?,?,?,?,?" bitfld.long 0x8 12. "PIBE,Priority Interrupt Bit Enable" "0: Priority interrupt bit disabled,1: Priority interrupt bit enabled" newline bitfld.long 0x8 10.--11. "CF1DS,Control Field1 Compare Data Select" "0: Select XCR1.PCF1D[7:0] as the compare data,1: Select XCR1.SCF1D[7:0] as the compare data,?,?" bitfld.long 0x8 9. "CF0RE,Control Field 0 Enable" "0: No Control Field 0,1: With Control Field 0" newline bitfld.long 0x8 8. "BFE,Break Field Enable" "0: No Break Field,1: With Break Field" bitfld.long 0x8 0.--1. "TCSS,Timer Count Clock Source Selection" "?,1: TCLK/4,?,?" line.long 0xC "XCR1,Simple LIN Control Register 1" hexmask.long.byte 0xC 24.--31. 1. "CF1CE,Control Field 1 Compare Bit Enable" hexmask.long.byte 0xC 16.--23. 1. "SCF1D,Secondary Compare Data for Control Field 1" newline hexmask.long.byte 0xC 8.--15. 1. "PCF1D,Priority Compare Data for Control Field 1" bitfld.long 0xC 5. "BMEN,Bit Rate Measurement Enable" "0: Bit rate measurement disabled,1: Bit rate measurement enabled" newline bitfld.long 0xC 4. "SDST,Start Frame Detection Enable" "0: Start Frame/Break Field detection disabled,1: Start Frame/Break Field detection enabled" bitfld.long 0xC 0. "TCST,Break Field Output Timer Count Start Trigger" "0: Break Field output timer count stopped,1: Break Field output timer count start" line.long 0x10 "XCR2,Simple LIN Control Register 2" hexmask.long.word 0x10 16.--31. 1. "BFLW,Break Field Length Setting" hexmask.long.byte 0x10 8.--15. 1. "CF0CE,Control Field 0 Compare Bit Enable" newline hexmask.long.byte 0x10 0.--7. 1. "CF0D,Control Field 0 Compare Data" rgroup.long 0x48++0x1B line.long 0x0 "CSR,Common Status Register" bitfld.long 0x0 31. "RDRF,Receive Data Full Flag" "0: Non-FIFO selected (CCR3.FM = 0): No received..,1: Non-FIFO selected (CCR3.FM = 0): Received data.." bitfld.long 0x0 30. "TEND,Transmit End Flag" "0: A character is being transmitted or standing by..,1: Character transfer has been completed or sending.." newline bitfld.long 0x0 29. "TDRE,Transmit Data Empty Flag" "0: Non-FIFO selected (CCR3.FM = 0): Transmit data..,1: Non-FIFO selected (CCR3.FM = 0): No transmit.." bitfld.long 0x0 28. "FER,Framing Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No framing..,1: Non-FIFO selected (CCR3.FM = 0): A framing error.." newline bitfld.long 0x0 27. "PER,Parity Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No parity error..,1: Non-FIFO selected (CCR3.FM = 0): A parity error.." bitfld.long 0x0 26. "MFF,Mode Fault Error Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.long 0x0 24. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.long 0x0 18. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred at address match..,1: A framing error has occurred at address match.." newline bitfld.long 0x0 17. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred at address match..,1: A parity error has occurred at address match.." bitfld.long 0x0 16. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" newline bitfld.long 0x0 15. "RXDMON,Serial Input Data Monitor Bit" "0: When RINV is 0 RXDn pin is the low level. When..,1: When RINV is 0 RXDn pin is the high level. When.." bitfld.long 0x0 4. "ERS,Error Signal Status Flag" "0: Error signal low not responded,1: Error signal low responded" line.long 0x4 "ISR,Simple IIC Status Register" bitfld.long 0x4 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.long 0x4 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" line.long 0x8 "FRSR,FIFO Receive Status Register" hexmask.long.byte 0x8 24.--29. 1. "FNUM,Framing Error Count" hexmask.long.byte 0x8 16.--21. 1. "PNUM,Parity Error Count" newline hexmask.long.byte 0x8 8.--13. 1. "R,Receive-FIFO Data Count" bitfld.long 0x8 0. "DR,Receive Data Ready Flag" "0: Receiving is in progress or no received data..,1: The following receive data is not received for a.." line.long 0xC "FTSR,FIFO Transmit Status Register" hexmask.long.byte 0xC 0.--5. 1. "T,Transmit-FIFO Data Count" line.long 0x10 "MSR,Manchester Status Register" bitfld.long 0x10 6. "RSYNC,Receive SYNC Data Bit" "0: The received start bit is DATA SYNC,1: The received start bit is COMMAND SYNC" bitfld.long 0x10 4. "MER,Manchester Error Flag" "0: No Manchester error occurred,1: Manchester error has occurred" newline bitfld.long 0x10 2. "SBER,Start Bit Error Flag" "0: No start bit error detected,1: Start bit error detected" bitfld.long 0x10 1. "SYER,SYNC Error Flag" "0: No receive SYNC error detected,1: Receive SYNC error detected" newline bitfld.long 0x10 0. "PFER,Preface Error Flag" "0: No preface error detected,1: Preface error detected" line.long 0x14 "XSR0,Simple LIN Status Register 0" hexmask.long.byte 0x14 24.--31. 1. "CF1RD,Control Field 1 received data" hexmask.long.byte 0x14 16.--23. 1. "CF0RD,Control Field 0 received data" newline bitfld.long 0x14 15. "AEDF,Active Edge Detection Flag" "0: No valid edge detected,1: Detected a valid edge" bitfld.long 0x14 14. "COF,Counter Overflow Flag" "0: Break Field detection counter has not overflowed,1: Break Field detection counter overflowed" newline bitfld.long 0x14 13. "PIBDF,Priority Interrupt Bit Detection Flag" "0: Priority interrupt bit is not detected,1: Priority interrupt bit is detected" bitfld.long 0x14 12. "CF1MF,Control Field 1 Compare Match Flag" "0: Control Field 1 received data does not match the..,1: Control Field 1 received data matches the.." newline bitfld.long 0x14 11. "CF0MF,Control Field 0 Compare Match Flag" "0: Control Field 0 received data does not match the..,1: Control Field 0 received data matches the.." bitfld.long 0x14 10. "BFDF,Break Field Detection Flag" "0: Break Field is not detected,1: Break Field is detected" newline bitfld.long 0x14 9. "BCDF,Bus Conflict Detection Flag" "0: No bus collision detected,1: Detected a bus collision" bitfld.long 0x14 8. "BFOF,Break Field Output Completion Flag" "0: Break Field is being output or is not being output,1: Completed BF output" newline bitfld.long 0x14 1. "RXDSF,RXDn Input Status Flag" "0: RXDn input to SCI is enabled,1: RXDn input to SCI is disabled" bitfld.long 0x14 0. "SFSF,Start Frame Status Flag" "0: Start Frame detection disabled or Start Frame..,1: Before Start Frame detection or during detection" line.long 0x18 "XSR1,Simple LIN Status Register 1" hexmask.long.word 0x18 0.--15. 1. "TCNT,Timer Count Capture Value" wgroup.long 0x68++0x13 line.long 0x0 "CFCLR,Common Flag Clear Register" bitfld.long 0x0 31. "RDRFC,RDRF Clear Bit" "0,1" bitfld.long 0x0 29. "TDREC,TDRE Clear Bit" "0,1" newline bitfld.long 0x0 28. "FERC,FER Clear Bit" "0,1" bitfld.long 0x0 27. "PERC,PER Clear Bit" "0,1" newline bitfld.long 0x0 26. "MFFC,MFF Clear Bit" "0,1" bitfld.long 0x0 24. "ORERC,ORER Clear Bit" "0,1" newline bitfld.long 0x0 18. "DFERC,DFER Clear Bit" "0,1" bitfld.long 0x0 17. "DPERC,DPER Clear Bit" "0,1" newline bitfld.long 0x0 16. "DCMFC,DCMF Clear Bit" "0,1" bitfld.long 0x0 4. "ERSC,ERS Clear Bit" "0,1" line.long 0x4 "ICFCLR,Simple IIC Flag Clear Register" bitfld.long 0x4 3. "IICSTIFC,IICSTIF Clear Bit" "0,1" line.long 0x8 "FFCLR,FIFO Flag Clear Register" bitfld.long 0x8 0. "DRC,DR Clear Bit" "0,1" line.long 0xC "MFCLR,Manchester Flag Clear Register" bitfld.long 0xC 4. "MERC,MER Clear Bit" "0,1" bitfld.long 0xC 2. "SBERC,SBER Clear Bit" "0,1" newline bitfld.long 0xC 1. "SYERC,SYER Clear Bit" "0,1" bitfld.long 0xC 0. "PFERC,PFER Clear Bit" "0,1" line.long 0x10 "XFCLR,Simple LIN Flag Clear Register" bitfld.long 0x10 15. "AEDC,AEDF Clear Bit" "0,1" bitfld.long 0x10 14. "COFC,COFF Clear Bit" "0,1" newline bitfld.long 0x10 13. "PIBDC,PIBDF Clear Bit" "0,1" bitfld.long 0x10 12. "CF1MC,CF1MF Clear Bit" "0,1" newline bitfld.long 0x10 11. "CF0MC,CF0MF Clear Bit" "0,1" bitfld.long 0x10 10. "BFDC,BFDF Clear Bit" "0,1" newline bitfld.long 0x10 9. "BCDC,BCDF Clear Bit" "0,1" bitfld.long 0x10 8. "BFOC,BFOF Clear Bit" "0,1" tree.end tree "SCI3_B_NS" base ad:0x50358300 rgroup.long 0x0++0x3 line.long 0x0 "RDR,Receive Data Register" bitfld.long 0x0 28. "FER,Framing error flag" "0,1" bitfld.long 0x0 27. "PER,Parity error flag" "0,1" newline bitfld.long 0x0 24. "ORER,Overrun Error flag" "0,1" bitfld.long 0x0 12. "FFER,FIFO framing error flag" "0: There is no framing error in the data read from..,1: There is framing error in the data read from the.." newline bitfld.long 0x0 11. "FPER,FIFO parity error flag" "0: There is no parity error in the data read from..,1: There is parity error in the data read from the.." bitfld.long 0x0 10. "DR,Receive data ready flag" "0,1" newline bitfld.long 0x0 9. "MPB,Multi-processor flag" "0: Data transmission cycles,1: ID transmission cycles" hexmask.long.word 0x0 0.--8. 1. "RDAT,Serial receive data" rgroup.byte 0x0++0x0 line.byte 0x0 "RDR_BY,Receive Data Register" bitfld.byte 0x0 4. "FER,Framing error flag" "0,1" bitfld.byte 0x0 3. "PER,Parity error flag" "0,1" newline bitfld.byte 0x0 0. "ORER,Overrun Error flag" "0,1" group.long 0x4++0x3 line.long 0x0 "TDR,Transmit Data Register" bitfld.long 0x0 12. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.long 0x0 9. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline hexmask.long.word 0x0 0.--8. 1. "TDAT,Serial transmit data" group.byte 0x4++0x1 line.byte 0x0 "TDRLL,Transmit Data Register" line.byte 0x1 "TDRLH,Transmit Data Register" bitfld.byte 0x1 4. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.byte 0x1 1. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline bitfld.byte 0x1 0. "TDAT,Serial transmit data" "0,1" group.long 0x8++0x13 line.long 0x0 "CCR0,Common Control Register 0" bitfld.long 0x0 24. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled,1: SSn pin function is enabled" bitfld.long 0x0 21. "TEIE,Transmit End Interrupt Enable" "0: SCIn_TEI interrupt request is disabled,1: SCIn_TEI interrupt request is enabled" newline bitfld.long 0x0 20. "TIE,Transmit Interrupt Enable" "0: SCIn_TXI interrupt request is disabled,1: SCIn_TXI interrupt request is enabled" bitfld.long 0x0 16. "RIE,Receive Interrupt Enable" "0: SCIn_RXI and SCIn_ERI interrupt requests are..,1: SCIn_RXI and SCIn_ERI interrupt requests are.." newline bitfld.long 0x0 10. "IDSEL,ID Frame Select" "0: Compare data irrespective of the value of the..,1: Compare data only when the MPB bit is 1 (ID frame)" bitfld.long 0x0 9. "DCME,Data Compare Match Enable" "0: Address match function is disabled,1: Address match function is enabled" newline bitfld.long 0x0 8. "MPIE,Multi-Processor Interrupt Enable" "0: Non-multi-processor reception,1: Multi-processor reception When the data with the.." bitfld.long 0x0 4. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" newline bitfld.long 0x0 0. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" line.long 0x4 "CCR1,Common Control Register 1" bitfld.long 0x4 29. "NFM,Noise Filter Mode" "0: 3-point matching mode,1: Majority vote mode" bitfld.long 0x4 28. "NFEN,Digital Noise Filter Function Enable" "0: In Asynchronous Manchester Simple LIN modes:..,1: In Asynchronous Manchester Simple LIN modes:.." newline bitfld.long 0x4 24.--26. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: The on-chip baud rate generator source clock..,?,?,?,?,?,?" bitfld.long 0x4 20. "SHARPS,Half-Duplex Communication Select" "0: TXDn pin RXDn pin independent,1: TXDn/RXDn pin combination use (half-duplex.." newline bitfld.long 0x4 16. "SPLP,Loopback Control" "0: Normal mode,1: Loopback mode" bitfld.long 0x4 13. "RINV,RXD Invert" "0: Received data from RXDn is not inverted and input,1: Received data from RXDn is inverted and input" newline bitfld.long 0x4 12. "TINV,TXD Invert" "0: Transmit data is not inverted and output to TXDn,1: Transmit data is inverted and output to TXDn" bitfld.long 0x4 9. "PM,Parity Mode" "0: Selects even parity,1: Selects odd parity" newline bitfld.long 0x4 8. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.." bitfld.long 0x4 5. "SPB2IO,Serial Port Break I/O" "0: The value of SPB2DT bit is not output in TXDn pin,1: The value of SPB2DT bit is output in TXDn pin" newline bitfld.long 0x4 4. "SPB2DT,Serial Port Break Data Select" "0: When TINV is 0 low level is output in TXDn pin.,1: When TINV is 0 high level is output in TXDn pin." bitfld.long 0x4 1. "CTSPEN,CTS External Pin Enable" "0: Alternate setting to use CTS and RTS functions..,1: Dedicated setting for separately using CTS and.." newline bitfld.long 0x4 0. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled" line.long 0x8 "CCR2,Common Control Register 2" hexmask.long.byte 0x8 24.--31. 1. "MDDR,Modulation Duty Setting" bitfld.long 0x8 20.--21. "CKS,Clock Select" "0: TCLK clock (n = 0),1: TCLK/4 clock (n = 1),?,?" newline bitfld.long 0x8 16. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled,1: Bit rate modulation function is enabled" hexmask.long.byte 0x8 8.--15. 1. "BRR,Bit Rate Setting" newline bitfld.long 0x8 7. "ABCSE2,Asynchronous Mode Extended Base Clock Select 2" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 4 base clock cycles for 1-bit.." bitfld.long 0x8 6. "ABCSE,Asynchronous Mode Extended Base Clock Select" "0: Clock cycles for 1-bit period is determined by..,1: Baud rate is 6 base clock cycles for 1-bit.." newline bitfld.long 0x8 5. "ABCS,Asynchronous Mode Base Clock Select" "0: Selects 16 base clock cycles for 1-bit period,1: Selects 8 base clock cycles for 1-bit period" bitfld.long 0x8 4. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.long 0x8 0.--2. "BCP,Base Clock Pulse" "0: 93 clock cycles (S = 93),1: 128 clock cycles (S = 128),?,?,?,?,?,?" line.long 0xC "CCR3,Common Control Register 3" bitfld.long 0xC 29. "BLK,Block Transfer Mode" "0: Non-block transfer mode operation,1: Block transfer mode operation" bitfld.long 0xC 28. "GM,GSM Mode" "0: Non-GSM mode operation,1: GSM mode operation" newline bitfld.long 0xC 26. "ACS0,Asynchronous Mode Clock Source Select" "0: External clock input,1: Logical AND of compare matches output from the.." bitfld.long 0xC 24.--25. "CKE,Clock Enable" "0,1,2,3" newline bitfld.long 0xC 21. "DEN,Driver Enable" "0: RS-485 driver control function disabled,1: RS-485 driver control function enabled" bitfld.long 0xC 20. "FM,FIFO Mode Select" "0: TDR register and RDR register are non-FIFO..,1: TDR register and RDR register are FIFO buffer.." newline bitfld.long 0xC 19. "MP,Multi-Processor Mode" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" bitfld.long 0xC 16.--18. "MOD,Communication Mode Select" "0: Asynchronous mode (multi-processor mode),1: Smart card interface mode,?,?,?,?,?,?" newline bitfld.long 0xC 15. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.long 0xC 14. "STP,Stop Bit Length" "0: 1 stop bit/break delimiter length is 1-bit,1: 2 stop bits/break delimiter length is 2-bit" newline bitfld.long 0xC 13. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted to TSR as is. RSR..,1: TDR contents are inverted before being.." bitfld.long 0xC 12. "LSBF,LSB First select" "0: MSB-first,1: LSB-first" newline bitfld.long 0xC 8.--9. "CHR,Character Length" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 9-bit data length,?,?" bitfld.long 0xC 7. "BPEN,Synchronizer Bypass Enable" "0: Synchronizer circuit is not bypassed,1: Synchronizer circuit is bypassed" newline bitfld.long 0xC 1. "CPOL,Clock Polarity Select" "0: SCKn in idle state is 0,1: SCKn in idle state is 1" bitfld.long 0xC 0. "CPHA,Clock Phase Select" "0: Data is sampled at an odd edge and changes at an..,1: Data changes at an odd edge and is sampled at an.." line.long 0x10 "CCR4,Common Control Register 4" bitfld.long 0x10 31. "AET,Adjustment Edge for Transmit Timing" "0: When CCR1.TINV is 0 adjust the rising edge..,1: When CCR1.TINV is 0 adjust the falling edge.." bitfld.long 0x10 28.--30. "ATT,Adjustment Value for Transmit Timing" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "AJD,Adjustment Direction for Receive Sampling Timing" "0: The sampling timing is adjusted backward to the..,1: The sampling timing is adjusted forward to the.." bitfld.long 0x10 24.--26. "AST,Adjustment Value for Receive Sampling Timing" "0: Setting prohibited,1: 2-TCLK delay,?,?,?,?,?,?" newline bitfld.long 0x10 19. "SCKSEL,Master receive clock selection" "0: Master receive clock is disabled,1: Master receive clock is enabled" bitfld.long 0x10 17. "ATEN,Adjust Transmit Timing Enable" "0: Adjust transmit timing disabled,1: Adjust transmit timing enabled" newline bitfld.long 0x10 16. "ASEN,Adjust Receive Sampling Timing Enable" "0: Adjust sampling timing disabled,1: Adjust sampling timing enabled" hexmask.long.word 0x10 0.--8. 1. "CMPD,Compare Match Data" rgroup.byte 0x1C++0x0 line.byte 0x0 "CESR,Communication Enable Status Register" bitfld.byte 0x0 4. "TIST,TE Internal Status" "0: TE signal internal state value 0,1: TE signal internal state value 1" bitfld.byte 0x0 0. "RIST,RE Internal Status" "0: RE signal internal state value 0,1: RE signal internal state value 1" group.long 0x20++0x7 line.long 0x0 "ICR,Simple IIC Control Register" bitfld.long 0x0 22.--23. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition,?,?" bitfld.long 0x0 20.--21. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition,?,?" newline bitfld.long 0x0 18. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated" bitfld.long 0x0 17. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated,1: A restart condition is generated" newline bitfld.long 0x0 16. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated,1: A start condition is generated" bitfld.long 0x0 13. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.long 0x0 9. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" bitfld.long 0x0 8. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts" newline hexmask.long.byte 0x0 0.--4. 1. "IICDL,SDA Delay Output Select" line.long 0x4 "FCR,FIFO Control Register" hexmask.long.byte 0x4 24.--28. 1. "RSTRG,RTS Output Active Trigger Number Select" bitfld.long 0x4 23. "RFRST,Receive FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Receive-FIFO(RDR.." newline hexmask.long.byte 0x4 16.--20. 1. "RTRG,Receive FIFO Data Trigger Number" bitfld.long 0x4 15. "TFRST,Transmit FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Transmit-FIFO (TDR.." newline hexmask.long.byte 0x4 8.--12. 1. "TTRG,Transmit FIFO Data Trigger Number" bitfld.long 0x4 0. "DRES,Receive Data Ready Error Select Bit" "0: Reception data full interrupt (SCIn_RXI),1: Receive error interrupt (SCIn_ERI)" group.long 0x2C++0x13 line.long 0x0 "MCR,Manchester Control Register" bitfld.long 0x0 26. "SBEREN,Start Bit Error Enable" "0: Does not handle a start bit error as an..,1: Handles a start bit error as an interrupt source" bitfld.long 0x0 25. "SYEREN,Receive SYNC Error Enable" "0: Does not handle a receive SYNC error as an..,1: Handles a receive SYNC error as an interrupt.." newline bitfld.long 0x0 24. "PFEREN,Preface Error Enable" "0: Does not handle a preface error as an interrupt..,1: Handles a preface error as an interrupt source" bitfld.long 0x0 20.--21. "RPPAT,Receive Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 16.--19. 1. "RPLEN,Receive Preface Length" bitfld.long 0x0 12.--13. "TPPAT,Transmit Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "TPLEN,Transmit Preface Length" bitfld.long 0x0 6. "SBSEL,Start Bit Select" "0: The start bit area consists of one bit,1: The start bit area consists of three bits.." newline bitfld.long 0x0 5. "SYNSEL,SYNC Select" "0: The start bit pattern is set with the SYNVAL bit,1: The start bit pattern is set with the TSYNC bit" bitfld.long 0x0 4. "SYNVAL,SYNC value Setting" "0,1" newline bitfld.long 0x0 2. "ERTEN,Manchester Edge Retiming Enable" "0: Disables the receive retiming function,1: Enables the receive retiming function" bitfld.long 0x0 1. "TMPOL,Polarity of Transmit Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." newline bitfld.long 0x0 0. "RMPOL,Polarity of Received Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." line.long 0x4 "DCR,Driver Control Register" hexmask.long.byte 0x4 16.--20. 1. "DENGT,Driver Negate Time" hexmask.long.byte 0x4 8.--12. 1. "DEAST,Driver Assertion Time" newline bitfld.long 0x4 0. "DEPOL,Driver Effective Polarity Select" "0: The DEn signal is active-high,1: The DEn signal is active-low" line.long 0x8 "XCR0,Simple LIN Control Register 0" bitfld.long 0x8 24.--25. "BCCS,Bus Conflict Detection Clock Selection" "0: Base clock,1: Base clock/2,?,?" bitfld.long 0x8 22. "AEDIE,Active Edge Detection Interrupt Enable" "0: Active edge detection interrupt disabled,1: Active edge detection interrupt enabled" newline bitfld.long 0x8 21. "COFIE,Counter Overflow Interrupt Enable" "0: Counter overflow is not included in SCIn_ERI..,1: Counter overflow is included in SCIn_ERI.." bitfld.long 0x8 20. "BFDIE,Break Field Detection Interrupt Enable" "0: Break Field detection interrupt disabled,1: Break Field detection interrupt enabled" newline bitfld.long 0x8 17. "BCDIE,Bus Conflict Detection Interrupt Enable" "0: Bus conflict detection is not included in..,1: Bus conflict detection is included in SCIn_ERI.." bitfld.long 0x8 16. "BFOIE,Break Field Output Completion Interrupt Enable" "0: Break Field output completion is not included in..,1: Break Field output completion is included in.." newline bitfld.long 0x8 13.--15. "PIBS,Priority Interrupt Bit Select" "0: Bit 0 of Control Field 1,1: Bit 1 of Control Field 1,?,?,?,?,?,?" bitfld.long 0x8 12. "PIBE,Priority Interrupt Bit Enable" "0: Priority interrupt bit disabled,1: Priority interrupt bit enabled" newline bitfld.long 0x8 10.--11. "CF1DS,Control Field1 Compare Data Select" "0: Select XCR1.PCF1D[7:0] as the compare data,1: Select XCR1.SCF1D[7:0] as the compare data,?,?" bitfld.long 0x8 9. "CF0RE,Control Field 0 Enable" "0: No Control Field 0,1: With Control Field 0" newline bitfld.long 0x8 8. "BFE,Break Field Enable" "0: No Break Field,1: With Break Field" bitfld.long 0x8 0.--1. "TCSS,Timer Count Clock Source Selection" "?,1: TCLK/4,?,?" line.long 0xC "XCR1,Simple LIN Control Register 1" hexmask.long.byte 0xC 24.--31. 1. "CF1CE,Control Field 1 Compare Bit Enable" hexmask.long.byte 0xC 16.--23. 1. "SCF1D,Secondary Compare Data for Control Field 1" newline hexmask.long.byte 0xC 8.--15. 1. "PCF1D,Priority Compare Data for Control Field 1" bitfld.long 0xC 5. "BMEN,Bit Rate Measurement Enable" "0: Bit rate measurement disabled,1: Bit rate measurement enabled" newline bitfld.long 0xC 4. "SDST,Start Frame Detection Enable" "0: Start Frame/Break Field detection disabled,1: Start Frame/Break Field detection enabled" bitfld.long 0xC 0. "TCST,Break Field Output Timer Count Start Trigger" "0: Break Field output timer count stopped,1: Break Field output timer count start" line.long 0x10 "XCR2,Simple LIN Control Register 2" hexmask.long.word 0x10 16.--31. 1. "BFLW,Break Field Length Setting" hexmask.long.byte 0x10 8.--15. 1. "CF0CE,Control Field 0 Compare Bit Enable" newline hexmask.long.byte 0x10 0.--7. 1. "CF0D,Control Field 0 Compare Data" rgroup.long 0x48++0x1B line.long 0x0 "CSR,Common Status Register" bitfld.long 0x0 31. "RDRF,Receive Data Full Flag" "0: Non-FIFO selected (CCR3.FM = 0): No received..,1: Non-FIFO selected (CCR3.FM = 0): Received data.." bitfld.long 0x0 30. "TEND,Transmit End Flag" "0: A character is being transmitted or standing by..,1: Character transfer has been completed or sending.." newline bitfld.long 0x0 29. "TDRE,Transmit Data Empty Flag" "0: Non-FIFO selected (CCR3.FM = 0): Transmit data..,1: Non-FIFO selected (CCR3.FM = 0): No transmit.." bitfld.long 0x0 28. "FER,Framing Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No framing..,1: Non-FIFO selected (CCR3.FM = 0): A framing error.." newline bitfld.long 0x0 27. "PER,Parity Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No parity error..,1: Non-FIFO selected (CCR3.FM = 0): A parity error.." bitfld.long 0x0 26. "MFF,Mode Fault Error Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.long 0x0 24. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.long 0x0 18. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred at address match..,1: A framing error has occurred at address match.." newline bitfld.long 0x0 17. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred at address match..,1: A parity error has occurred at address match.." bitfld.long 0x0 16. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" newline bitfld.long 0x0 15. "RXDMON,Serial Input Data Monitor Bit" "0: When RINV is 0 RXDn pin is the low level. When..,1: When RINV is 0 RXDn pin is the high level. When.." bitfld.long 0x0 4. "ERS,Error Signal Status Flag" "0: Error signal low not responded,1: Error signal low responded" line.long 0x4 "ISR,Simple IIC Status Register" bitfld.long 0x4 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.long 0x4 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" line.long 0x8 "FRSR,FIFO Receive Status Register" hexmask.long.byte 0x8 24.--29. 1. "FNUM,Framing Error Count" hexmask.long.byte 0x8 16.--21. 1. "PNUM,Parity Error Count" newline hexmask.long.byte 0x8 8.--13. 1. "R,Receive-FIFO Data Count" bitfld.long 0x8 0. "DR,Receive Data Ready Flag" "0: Receiving is in progress or no received data..,1: The following receive data is not received for a.." line.long 0xC "FTSR,FIFO Transmit Status Register" hexmask.long.byte 0xC 0.--5. 1. "T,Transmit-FIFO Data Count" line.long 0x10 "MSR,Manchester Status Register" bitfld.long 0x10 6. "RSYNC,Receive SYNC Data Bit" "0: The received start bit is DATA SYNC,1: The received start bit is COMMAND SYNC" bitfld.long 0x10 4. "MER,Manchester Error Flag" "0: No Manchester error occurred,1: Manchester error has occurred" newline bitfld.long 0x10 2. "SBER,Start Bit Error Flag" "0: No start bit error detected,1: Start bit error detected" bitfld.long 0x10 1. "SYER,SYNC Error Flag" "0: No receive SYNC error detected,1: Receive SYNC error detected" newline bitfld.long 0x10 0. "PFER,Preface Error Flag" "0: No preface error detected,1: Preface error detected" line.long 0x14 "XSR0,Simple LIN Status Register 0" hexmask.long.byte 0x14 24.--31. 1. "CF1RD,Control Field 1 received data" hexmask.long.byte 0x14 16.--23. 1. "CF0RD,Control Field 0 received data" newline bitfld.long 0x14 15. "AEDF,Active Edge Detection Flag" "0: No valid edge detected,1: Detected a valid edge" bitfld.long 0x14 14. "COF,Counter Overflow Flag" "0: Break Field detection counter has not overflowed,1: Break Field detection counter overflowed" newline bitfld.long 0x14 13. "PIBDF,Priority Interrupt Bit Detection Flag" "0: Priority interrupt bit is not detected,1: Priority interrupt bit is detected" bitfld.long 0x14 12. "CF1MF,Control Field 1 Compare Match Flag" "0: Control Field 1 received data does not match the..,1: Control Field 1 received data matches the.." newline bitfld.long 0x14 11. "CF0MF,Control Field 0 Compare Match Flag" "0: Control Field 0 received data does not match the..,1: Control Field 0 received data matches the.." bitfld.long 0x14 10. "BFDF,Break Field Detection Flag" "0: Break Field is not detected,1: Break Field is detected" newline bitfld.long 0x14 9. "BCDF,Bus Conflict Detection Flag" "0: No bus collision detected,1: Detected a bus collision" bitfld.long 0x14 8. "BFOF,Break Field Output Completion Flag" "0: Break Field is being output or is not being output,1: Completed BF output" newline bitfld.long 0x14 1. "RXDSF,RXDn Input Status Flag" "0: RXDn input to SCI is enabled,1: RXDn input to SCI is disabled" bitfld.long 0x14 0. "SFSF,Start Frame Status Flag" "0: Start Frame detection disabled or Start Frame..,1: Before Start Frame detection or during detection" line.long 0x18 "XSR1,Simple LIN Status Register 1" hexmask.long.word 0x18 0.--15. 1. "TCNT,Timer Count Capture Value" wgroup.long 0x68++0x13 line.long 0x0 "CFCLR,Common Flag Clear Register" bitfld.long 0x0 31. "RDRFC,RDRF Clear Bit" "0,1" bitfld.long 0x0 29. "TDREC,TDRE Clear Bit" "0,1" newline bitfld.long 0x0 28. "FERC,FER Clear Bit" "0,1" bitfld.long 0x0 27. "PERC,PER Clear Bit" "0,1" newline bitfld.long 0x0 26. "MFFC,MFF Clear Bit" "0,1" bitfld.long 0x0 24. "ORERC,ORER Clear Bit" "0,1" newline bitfld.long 0x0 18. "DFERC,DFER Clear Bit" "0,1" bitfld.long 0x0 17. "DPERC,DPER Clear Bit" "0,1" newline bitfld.long 0x0 16. "DCMFC,DCMF Clear Bit" "0,1" bitfld.long 0x0 4. "ERSC,ERS Clear Bit" "0,1" line.long 0x4 "ICFCLR,Simple IIC Flag Clear Register" bitfld.long 0x4 3. "IICSTIFC,IICSTIF Clear Bit" "0,1" line.long 0x8 "FFCLR,FIFO Flag Clear Register" bitfld.long 0x8 0. "DRC,DR Clear Bit" "0,1" line.long 0xC "MFCLR,Manchester Flag Clear Register" bitfld.long 0xC 4. "MERC,MER Clear Bit" "0,1" bitfld.long 0xC 2. "SBERC,SBER Clear Bit" "0,1" newline bitfld.long 0xC 1. "SYERC,SYER Clear Bit" "0,1" bitfld.long 0xC 0. "PFERC,PFER Clear Bit" "0,1" line.long 0x10 "XFCLR,Simple LIN Flag Clear Register" bitfld.long 0x10 15. "AEDC,AEDF Clear Bit" "0,1" bitfld.long 0x10 14. "COFC,COFF Clear Bit" "0,1" newline bitfld.long 0x10 13. "PIBDC,PIBDF Clear Bit" "0,1" bitfld.long 0x10 12. "CF1MC,CF1MF Clear Bit" "0,1" newline bitfld.long 0x10 11. "CF0MC,CF0MF Clear Bit" "0,1" bitfld.long 0x10 10. "BFDC,BFDF Clear Bit" "0,1" newline bitfld.long 0x10 9. "BCDC,BCDF Clear Bit" "0,1" bitfld.long 0x10 8. "BFOC,BFOF Clear Bit" "0,1" tree.end tree "SCI4_B" base ad:0x40358400 rgroup.long 0x0++0x3 line.long 0x0 "RDR,Receive Data Register" bitfld.long 0x0 28. "FER,Framing error flag" "0,1" bitfld.long 0x0 27. "PER,Parity error flag" "0,1" newline bitfld.long 0x0 24. "ORER,Overrun Error flag" "0,1" bitfld.long 0x0 12. "FFER,FIFO framing error flag" "0: There is no framing error in the data read from..,1: There is framing error in the data read from the.." newline bitfld.long 0x0 11. "FPER,FIFO parity error flag" "0: There is no parity error in the data read from..,1: There is parity error in the data read from the.." bitfld.long 0x0 10. "DR,Receive data ready flag" "0,1" newline bitfld.long 0x0 9. "MPB,Multi-processor flag" "0: Data transmission cycles,1: ID transmission cycles" hexmask.long.word 0x0 0.--8. 1. "RDAT,Serial receive data" rgroup.byte 0x0++0x0 line.byte 0x0 "RDR_BY,Receive Data Register" bitfld.byte 0x0 4. "FER,Framing error flag" "0,1" bitfld.byte 0x0 3. "PER,Parity error flag" "0,1" newline bitfld.byte 0x0 0. "ORER,Overrun Error flag" "0,1" group.long 0x4++0x3 line.long 0x0 "TDR,Transmit Data Register" bitfld.long 0x0 12. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.long 0x0 9. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline hexmask.long.word 0x0 0.--8. 1. "TDAT,Serial transmit data" group.byte 0x4++0x1 line.byte 0x0 "TDRLL,Transmit Data Register" line.byte 0x1 "TDRLH,Transmit Data Register" bitfld.byte 0x1 4. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.byte 0x1 1. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline bitfld.byte 0x1 0. "TDAT,Serial transmit data" "0,1" group.long 0x8++0x13 line.long 0x0 "CCR0,Common Control Register 0" bitfld.long 0x0 24. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled,1: SSn pin function is enabled" bitfld.long 0x0 21. "TEIE,Transmit End Interrupt Enable" "0: SCIn_TEI interrupt request is disabled,1: SCIn_TEI interrupt request is enabled" newline bitfld.long 0x0 20. "TIE,Transmit Interrupt Enable" "0: SCIn_TXI interrupt request is disabled,1: SCIn_TXI interrupt request is enabled" bitfld.long 0x0 16. "RIE,Receive Interrupt Enable" "0: SCIn_RXI and SCIn_ERI interrupt requests are..,1: SCIn_RXI and SCIn_ERI interrupt requests are.." newline bitfld.long 0x0 10. "IDSEL,ID Frame Select" "0: Compare data irrespective of the value of the..,1: Compare data only when the MPB bit is 1 (ID frame)" bitfld.long 0x0 9. "DCME,Data Compare Match Enable" "0: Address match function is disabled,1: Address match function is enabled" newline bitfld.long 0x0 8. "MPIE,Multi-Processor Interrupt Enable" "0: Non-multi-processor reception,1: Multi-processor reception When the data with the.." bitfld.long 0x0 4. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" newline bitfld.long 0x0 0. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" line.long 0x4 "CCR1,Common Control Register 1" bitfld.long 0x4 29. "NFM,Noise Filter Mode" "0: 3-point matching mode,1: Majority vote mode" bitfld.long 0x4 28. "NFEN,Digital Noise Filter Function Enable" "0: In Asynchronous Manchester Simple LIN modes:..,1: In Asynchronous Manchester Simple LIN modes:.." newline bitfld.long 0x4 24.--26. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: The on-chip baud rate generator source clock..,?,?,?,?,?,?" bitfld.long 0x4 20. "SHARPS,Half-Duplex Communication Select" "0: TXDn pin RXDn pin independent,1: TXDn/RXDn pin combination use (half-duplex.." newline bitfld.long 0x4 16. "SPLP,Loopback Control" "0: Normal mode,1: Loopback mode" bitfld.long 0x4 13. "RINV,RXD Invert" "0: Received data from RXDn is not inverted and input,1: Received data from RXDn is inverted and input" newline bitfld.long 0x4 12. "TINV,TXD Invert" "0: Transmit data is not inverted and output to TXDn,1: Transmit data is inverted and output to TXDn" bitfld.long 0x4 9. "PM,Parity Mode" "0: Selects even parity,1: Selects odd parity" newline bitfld.long 0x4 8. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.." bitfld.long 0x4 5. "SPB2IO,Serial Port Break I/O" "0: The value of SPB2DT bit is not output in TXDn pin,1: The value of SPB2DT bit is output in TXDn pin" newline bitfld.long 0x4 4. "SPB2DT,Serial Port Break Data Select" "0: When TINV is 0 low level is output in TXDn pin.,1: When TINV is 0 high level is output in TXDn pin." bitfld.long 0x4 1. "CTSPEN,CTS External Pin Enable" "0: Alternate setting to use CTS and RTS functions..,1: Dedicated setting for separately using CTS and.." newline bitfld.long 0x4 0. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled" line.long 0x8 "CCR2,Common Control Register 2" hexmask.long.byte 0x8 24.--31. 1. "MDDR,Modulation Duty Setting" bitfld.long 0x8 20.--21. "CKS,Clock Select" "0: TCLK clock (n = 0),1: TCLK/4 clock (n = 1),?,?" newline bitfld.long 0x8 16. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled,1: Bit rate modulation function is enabled" hexmask.long.byte 0x8 8.--15. 1. "BRR,Bit Rate Setting" newline bitfld.long 0x8 7. "ABCSE2,Asynchronous Mode Extended Base Clock Select 2" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 4 base clock cycles for 1-bit.." bitfld.long 0x8 6. "ABCSE,Asynchronous Mode Extended Base Clock Select" "0: Clock cycles for 1-bit period is determined by..,1: Baud rate is 6 base clock cycles for 1-bit.." newline bitfld.long 0x8 5. "ABCS,Asynchronous Mode Base Clock Select" "0: Selects 16 base clock cycles for 1-bit period,1: Selects 8 base clock cycles for 1-bit period" bitfld.long 0x8 4. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.long 0x8 0.--2. "BCP,Base Clock Pulse" "0: 93 clock cycles (S = 93),1: 128 clock cycles (S = 128),?,?,?,?,?,?" line.long 0xC "CCR3,Common Control Register 3" bitfld.long 0xC 29. "BLK,Block Transfer Mode" "0: Non-block transfer mode operation,1: Block transfer mode operation" bitfld.long 0xC 28. "GM,GSM Mode" "0: Non-GSM mode operation,1: GSM mode operation" newline bitfld.long 0xC 26. "ACS0,Asynchronous Mode Clock Source Select" "0: External clock input,1: Logical AND of compare matches output from the.." bitfld.long 0xC 24.--25. "CKE,Clock Enable" "0,1,2,3" newline bitfld.long 0xC 21. "DEN,Driver Enable" "0: RS-485 driver control function disabled,1: RS-485 driver control function enabled" bitfld.long 0xC 20. "FM,FIFO Mode Select" "0: TDR register and RDR register are non-FIFO..,1: TDR register and RDR register are FIFO buffer.." newline bitfld.long 0xC 19. "MP,Multi-Processor Mode" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" bitfld.long 0xC 16.--18. "MOD,Communication Mode Select" "0: Asynchronous mode (multi-processor mode),1: Smart card interface mode,?,?,?,?,?,?" newline bitfld.long 0xC 15. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.long 0xC 14. "STP,Stop Bit Length" "0: 1 stop bit/break delimiter length is 1-bit,1: 2 stop bits/break delimiter length is 2-bit" newline bitfld.long 0xC 13. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted to TSR as is. RSR..,1: TDR contents are inverted before being.." bitfld.long 0xC 12. "LSBF,LSB First select" "0: MSB-first,1: LSB-first" newline bitfld.long 0xC 8.--9. "CHR,Character Length" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 9-bit data length,?,?" bitfld.long 0xC 7. "BPEN,Synchronizer Bypass Enable" "0: Synchronizer circuit is not bypassed,1: Synchronizer circuit is bypassed" newline bitfld.long 0xC 1. "CPOL,Clock Polarity Select" "0: SCKn in idle state is 0,1: SCKn in idle state is 1" bitfld.long 0xC 0. "CPHA,Clock Phase Select" "0: Data is sampled at an odd edge and changes at an..,1: Data changes at an odd edge and is sampled at an.." line.long 0x10 "CCR4,Common Control Register 4" bitfld.long 0x10 31. "AET,Adjustment Edge for Transmit Timing" "0: When CCR1.TINV is 0 adjust the rising edge..,1: When CCR1.TINV is 0 adjust the falling edge.." bitfld.long 0x10 28.--30. "ATT,Adjustment Value for Transmit Timing" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "AJD,Adjustment Direction for Receive Sampling Timing" "0: The sampling timing is adjusted backward to the..,1: The sampling timing is adjusted forward to the.." bitfld.long 0x10 24.--26. "AST,Adjustment Value for Receive Sampling Timing" "0: Setting prohibited,1: 2-TCLK delay,?,?,?,?,?,?" newline bitfld.long 0x10 19. "SCKSEL,Master receive clock selection" "0: Master receive clock is disabled,1: Master receive clock is enabled" bitfld.long 0x10 17. "ATEN,Adjust Transmit Timing Enable" "0: Adjust transmit timing disabled,1: Adjust transmit timing enabled" newline bitfld.long 0x10 16. "ASEN,Adjust Receive Sampling Timing Enable" "0: Adjust sampling timing disabled,1: Adjust sampling timing enabled" hexmask.long.word 0x10 0.--8. 1. "CMPD,Compare Match Data" rgroup.byte 0x1C++0x0 line.byte 0x0 "CESR,Communication Enable Status Register" bitfld.byte 0x0 4. "TIST,TE Internal Status" "0: TE signal internal state value 0,1: TE signal internal state value 1" bitfld.byte 0x0 0. "RIST,RE Internal Status" "0: RE signal internal state value 0,1: RE signal internal state value 1" group.long 0x20++0x7 line.long 0x0 "ICR,Simple IIC Control Register" bitfld.long 0x0 22.--23. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition,?,?" bitfld.long 0x0 20.--21. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition,?,?" newline bitfld.long 0x0 18. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated" bitfld.long 0x0 17. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated,1: A restart condition is generated" newline bitfld.long 0x0 16. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated,1: A start condition is generated" bitfld.long 0x0 13. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.long 0x0 9. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" bitfld.long 0x0 8. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts" newline hexmask.long.byte 0x0 0.--4. 1. "IICDL,SDA Delay Output Select" line.long 0x4 "FCR,FIFO Control Register" hexmask.long.byte 0x4 24.--28. 1. "RSTRG,RTS Output Active Trigger Number Select" bitfld.long 0x4 23. "RFRST,Receive FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Receive-FIFO(RDR.." newline hexmask.long.byte 0x4 16.--20. 1. "RTRG,Receive FIFO Data Trigger Number" bitfld.long 0x4 15. "TFRST,Transmit FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Transmit-FIFO (TDR.." newline hexmask.long.byte 0x4 8.--12. 1. "TTRG,Transmit FIFO Data Trigger Number" bitfld.long 0x4 0. "DRES,Receive Data Ready Error Select Bit" "0: Reception data full interrupt (SCIn_RXI),1: Receive error interrupt (SCIn_ERI)" group.long 0x2C++0x13 line.long 0x0 "MCR,Manchester Control Register" bitfld.long 0x0 26. "SBEREN,Start Bit Error Enable" "0: Does not handle a start bit error as an..,1: Handles a start bit error as an interrupt source" bitfld.long 0x0 25. "SYEREN,Receive SYNC Error Enable" "0: Does not handle a receive SYNC error as an..,1: Handles a receive SYNC error as an interrupt.." newline bitfld.long 0x0 24. "PFEREN,Preface Error Enable" "0: Does not handle a preface error as an interrupt..,1: Handles a preface error as an interrupt source" bitfld.long 0x0 20.--21. "RPPAT,Receive Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 16.--19. 1. "RPLEN,Receive Preface Length" bitfld.long 0x0 12.--13. "TPPAT,Transmit Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "TPLEN,Transmit Preface Length" bitfld.long 0x0 6. "SBSEL,Start Bit Select" "0: The start bit area consists of one bit,1: The start bit area consists of three bits.." newline bitfld.long 0x0 5. "SYNSEL,SYNC Select" "0: The start bit pattern is set with the SYNVAL bit,1: The start bit pattern is set with the TSYNC bit" bitfld.long 0x0 4. "SYNVAL,SYNC value Setting" "0,1" newline bitfld.long 0x0 2. "ERTEN,Manchester Edge Retiming Enable" "0: Disables the receive retiming function,1: Enables the receive retiming function" bitfld.long 0x0 1. "TMPOL,Polarity of Transmit Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." newline bitfld.long 0x0 0. "RMPOL,Polarity of Received Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." line.long 0x4 "DCR,Driver Control Register" hexmask.long.byte 0x4 16.--20. 1. "DENGT,Driver Negate Time" hexmask.long.byte 0x4 8.--12. 1. "DEAST,Driver Assertion Time" newline bitfld.long 0x4 0. "DEPOL,Driver Effective Polarity Select" "0: The DEn signal is active-high,1: The DEn signal is active-low" line.long 0x8 "XCR0,Simple LIN Control Register 0" bitfld.long 0x8 24.--25. "BCCS,Bus Conflict Detection Clock Selection" "0: Base clock,1: Base clock/2,?,?" bitfld.long 0x8 22. "AEDIE,Active Edge Detection Interrupt Enable" "0: Active edge detection interrupt disabled,1: Active edge detection interrupt enabled" newline bitfld.long 0x8 21. "COFIE,Counter Overflow Interrupt Enable" "0: Counter overflow is not included in SCIn_ERI..,1: Counter overflow is included in SCIn_ERI.." bitfld.long 0x8 20. "BFDIE,Break Field Detection Interrupt Enable" "0: Break Field detection interrupt disabled,1: Break Field detection interrupt enabled" newline bitfld.long 0x8 17. "BCDIE,Bus Conflict Detection Interrupt Enable" "0: Bus conflict detection is not included in..,1: Bus conflict detection is included in SCIn_ERI.." bitfld.long 0x8 16. "BFOIE,Break Field Output Completion Interrupt Enable" "0: Break Field output completion is not included in..,1: Break Field output completion is included in.." newline bitfld.long 0x8 13.--15. "PIBS,Priority Interrupt Bit Select" "0: Bit 0 of Control Field 1,1: Bit 1 of Control Field 1,?,?,?,?,?,?" bitfld.long 0x8 12. "PIBE,Priority Interrupt Bit Enable" "0: Priority interrupt bit disabled,1: Priority interrupt bit enabled" newline bitfld.long 0x8 10.--11. "CF1DS,Control Field1 Compare Data Select" "0: Select XCR1.PCF1D[7:0] as the compare data,1: Select XCR1.SCF1D[7:0] as the compare data,?,?" bitfld.long 0x8 9. "CF0RE,Control Field 0 Enable" "0: No Control Field 0,1: With Control Field 0" newline bitfld.long 0x8 8. "BFE,Break Field Enable" "0: No Break Field,1: With Break Field" bitfld.long 0x8 0.--1. "TCSS,Timer Count Clock Source Selection" "?,1: TCLK/4,?,?" line.long 0xC "XCR1,Simple LIN Control Register 1" hexmask.long.byte 0xC 24.--31. 1. "CF1CE,Control Field 1 Compare Bit Enable" hexmask.long.byte 0xC 16.--23. 1. "SCF1D,Secondary Compare Data for Control Field 1" newline hexmask.long.byte 0xC 8.--15. 1. "PCF1D,Priority Compare Data for Control Field 1" bitfld.long 0xC 5. "BMEN,Bit Rate Measurement Enable" "0: Bit rate measurement disabled,1: Bit rate measurement enabled" newline bitfld.long 0xC 4. "SDST,Start Frame Detection Enable" "0: Start Frame/Break Field detection disabled,1: Start Frame/Break Field detection enabled" bitfld.long 0xC 0. "TCST,Break Field Output Timer Count Start Trigger" "0: Break Field output timer count stopped,1: Break Field output timer count start" line.long 0x10 "XCR2,Simple LIN Control Register 2" hexmask.long.word 0x10 16.--31. 1. "BFLW,Break Field Length Setting" hexmask.long.byte 0x10 8.--15. 1. "CF0CE,Control Field 0 Compare Bit Enable" newline hexmask.long.byte 0x10 0.--7. 1. "CF0D,Control Field 0 Compare Data" rgroup.long 0x48++0x1B line.long 0x0 "CSR,Common Status Register" bitfld.long 0x0 31. "RDRF,Receive Data Full Flag" "0: Non-FIFO selected (CCR3.FM = 0): No received..,1: Non-FIFO selected (CCR3.FM = 0): Received data.." bitfld.long 0x0 30. "TEND,Transmit End Flag" "0: A character is being transmitted or standing by..,1: Character transfer has been completed or sending.." newline bitfld.long 0x0 29. "TDRE,Transmit Data Empty Flag" "0: Non-FIFO selected (CCR3.FM = 0): Transmit data..,1: Non-FIFO selected (CCR3.FM = 0): No transmit.." bitfld.long 0x0 28. "FER,Framing Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No framing..,1: Non-FIFO selected (CCR3.FM = 0): A framing error.." newline bitfld.long 0x0 27. "PER,Parity Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No parity error..,1: Non-FIFO selected (CCR3.FM = 0): A parity error.." bitfld.long 0x0 26. "MFF,Mode Fault Error Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.long 0x0 24. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.long 0x0 18. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred at address match..,1: A framing error has occurred at address match.." newline bitfld.long 0x0 17. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred at address match..,1: A parity error has occurred at address match.." bitfld.long 0x0 16. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" newline bitfld.long 0x0 15. "RXDMON,Serial Input Data Monitor Bit" "0: When RINV is 0 RXDn pin is the low level. When..,1: When RINV is 0 RXDn pin is the high level. When.." bitfld.long 0x0 4. "ERS,Error Signal Status Flag" "0: Error signal low not responded,1: Error signal low responded" line.long 0x4 "ISR,Simple IIC Status Register" bitfld.long 0x4 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.long 0x4 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" line.long 0x8 "FRSR,FIFO Receive Status Register" hexmask.long.byte 0x8 24.--29. 1. "FNUM,Framing Error Count" hexmask.long.byte 0x8 16.--21. 1. "PNUM,Parity Error Count" newline hexmask.long.byte 0x8 8.--13. 1. "R,Receive-FIFO Data Count" bitfld.long 0x8 0. "DR,Receive Data Ready Flag" "0: Receiving is in progress or no received data..,1: The following receive data is not received for a.." line.long 0xC "FTSR,FIFO Transmit Status Register" hexmask.long.byte 0xC 0.--5. 1. "T,Transmit-FIFO Data Count" line.long 0x10 "MSR,Manchester Status Register" bitfld.long 0x10 6. "RSYNC,Receive SYNC Data Bit" "0: The received start bit is DATA SYNC,1: The received start bit is COMMAND SYNC" bitfld.long 0x10 4. "MER,Manchester Error Flag" "0: No Manchester error occurred,1: Manchester error has occurred" newline bitfld.long 0x10 2. "SBER,Start Bit Error Flag" "0: No start bit error detected,1: Start bit error detected" bitfld.long 0x10 1. "SYER,SYNC Error Flag" "0: No receive SYNC error detected,1: Receive SYNC error detected" newline bitfld.long 0x10 0. "PFER,Preface Error Flag" "0: No preface error detected,1: Preface error detected" line.long 0x14 "XSR0,Simple LIN Status Register 0" hexmask.long.byte 0x14 24.--31. 1. "CF1RD,Control Field 1 received data" hexmask.long.byte 0x14 16.--23. 1. "CF0RD,Control Field 0 received data" newline bitfld.long 0x14 15. "AEDF,Active Edge Detection Flag" "0: No valid edge detected,1: Detected a valid edge" bitfld.long 0x14 14. "COF,Counter Overflow Flag" "0: Break Field detection counter has not overflowed,1: Break Field detection counter overflowed" newline bitfld.long 0x14 13. "PIBDF,Priority Interrupt Bit Detection Flag" "0: Priority interrupt bit is not detected,1: Priority interrupt bit is detected" bitfld.long 0x14 12. "CF1MF,Control Field 1 Compare Match Flag" "0: Control Field 1 received data does not match the..,1: Control Field 1 received data matches the.." newline bitfld.long 0x14 11. "CF0MF,Control Field 0 Compare Match Flag" "0: Control Field 0 received data does not match the..,1: Control Field 0 received data matches the.." bitfld.long 0x14 10. "BFDF,Break Field Detection Flag" "0: Break Field is not detected,1: Break Field is detected" newline bitfld.long 0x14 9. "BCDF,Bus Conflict Detection Flag" "0: No bus collision detected,1: Detected a bus collision" bitfld.long 0x14 8. "BFOF,Break Field Output Completion Flag" "0: Break Field is being output or is not being output,1: Completed BF output" newline bitfld.long 0x14 1. "RXDSF,RXDn Input Status Flag" "0: RXDn input to SCI is enabled,1: RXDn input to SCI is disabled" bitfld.long 0x14 0. "SFSF,Start Frame Status Flag" "0: Start Frame detection disabled or Start Frame..,1: Before Start Frame detection or during detection" line.long 0x18 "XSR1,Simple LIN Status Register 1" hexmask.long.word 0x18 0.--15. 1. "TCNT,Timer Count Capture Value" wgroup.long 0x68++0x13 line.long 0x0 "CFCLR,Common Flag Clear Register" bitfld.long 0x0 31. "RDRFC,RDRF Clear Bit" "0,1" bitfld.long 0x0 29. "TDREC,TDRE Clear Bit" "0,1" newline bitfld.long 0x0 28. "FERC,FER Clear Bit" "0,1" bitfld.long 0x0 27. "PERC,PER Clear Bit" "0,1" newline bitfld.long 0x0 26. "MFFC,MFF Clear Bit" "0,1" bitfld.long 0x0 24. "ORERC,ORER Clear Bit" "0,1" newline bitfld.long 0x0 18. "DFERC,DFER Clear Bit" "0,1" bitfld.long 0x0 17. "DPERC,DPER Clear Bit" "0,1" newline bitfld.long 0x0 16. "DCMFC,DCMF Clear Bit" "0,1" bitfld.long 0x0 4. "ERSC,ERS Clear Bit" "0,1" line.long 0x4 "ICFCLR,Simple IIC Flag Clear Register" bitfld.long 0x4 3. "IICSTIFC,IICSTIF Clear Bit" "0,1" line.long 0x8 "FFCLR,FIFO Flag Clear Register" bitfld.long 0x8 0. "DRC,DR Clear Bit" "0,1" line.long 0xC "MFCLR,Manchester Flag Clear Register" bitfld.long 0xC 4. "MERC,MER Clear Bit" "0,1" bitfld.long 0xC 2. "SBERC,SBER Clear Bit" "0,1" newline bitfld.long 0xC 1. "SYERC,SYER Clear Bit" "0,1" bitfld.long 0xC 0. "PFERC,PFER Clear Bit" "0,1" line.long 0x10 "XFCLR,Simple LIN Flag Clear Register" bitfld.long 0x10 15. "AEDC,AEDF Clear Bit" "0,1" bitfld.long 0x10 14. "COFC,COFF Clear Bit" "0,1" newline bitfld.long 0x10 13. "PIBDC,PIBDF Clear Bit" "0,1" bitfld.long 0x10 12. "CF1MC,CF1MF Clear Bit" "0,1" newline bitfld.long 0x10 11. "CF0MC,CF0MF Clear Bit" "0,1" bitfld.long 0x10 10. "BFDC,BFDF Clear Bit" "0,1" newline bitfld.long 0x10 9. "BCDC,BCDF Clear Bit" "0,1" bitfld.long 0x10 8. "BFOC,BFOF Clear Bit" "0,1" tree.end tree "SCI4_B_NS" base ad:0x50358400 rgroup.long 0x0++0x3 line.long 0x0 "RDR,Receive Data Register" bitfld.long 0x0 28. "FER,Framing error flag" "0,1" bitfld.long 0x0 27. "PER,Parity error flag" "0,1" newline bitfld.long 0x0 24. "ORER,Overrun Error flag" "0,1" bitfld.long 0x0 12. "FFER,FIFO framing error flag" "0: There is no framing error in the data read from..,1: There is framing error in the data read from the.." newline bitfld.long 0x0 11. "FPER,FIFO parity error flag" "0: There is no parity error in the data read from..,1: There is parity error in the data read from the.." bitfld.long 0x0 10. "DR,Receive data ready flag" "0,1" newline bitfld.long 0x0 9. "MPB,Multi-processor flag" "0: Data transmission cycles,1: ID transmission cycles" hexmask.long.word 0x0 0.--8. 1. "RDAT,Serial receive data" rgroup.byte 0x0++0x0 line.byte 0x0 "RDR_BY,Receive Data Register" bitfld.byte 0x0 4. "FER,Framing error flag" "0,1" bitfld.byte 0x0 3. "PER,Parity error flag" "0,1" newline bitfld.byte 0x0 0. "ORER,Overrun Error flag" "0,1" group.long 0x4++0x3 line.long 0x0 "TDR,Transmit Data Register" bitfld.long 0x0 12. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.long 0x0 9. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline hexmask.long.word 0x0 0.--8. 1. "TDAT,Serial transmit data" group.byte 0x4++0x1 line.byte 0x0 "TDRLL,Transmit Data Register" line.byte 0x1 "TDRLH,Transmit Data Register" bitfld.byte 0x1 4. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.byte 0x1 1. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline bitfld.byte 0x1 0. "TDAT,Serial transmit data" "0,1" group.long 0x8++0x13 line.long 0x0 "CCR0,Common Control Register 0" bitfld.long 0x0 24. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled,1: SSn pin function is enabled" bitfld.long 0x0 21. "TEIE,Transmit End Interrupt Enable" "0: SCIn_TEI interrupt request is disabled,1: SCIn_TEI interrupt request is enabled" newline bitfld.long 0x0 20. "TIE,Transmit Interrupt Enable" "0: SCIn_TXI interrupt request is disabled,1: SCIn_TXI interrupt request is enabled" bitfld.long 0x0 16. "RIE,Receive Interrupt Enable" "0: SCIn_RXI and SCIn_ERI interrupt requests are..,1: SCIn_RXI and SCIn_ERI interrupt requests are.." newline bitfld.long 0x0 10. "IDSEL,ID Frame Select" "0: Compare data irrespective of the value of the..,1: Compare data only when the MPB bit is 1 (ID frame)" bitfld.long 0x0 9. "DCME,Data Compare Match Enable" "0: Address match function is disabled,1: Address match function is enabled" newline bitfld.long 0x0 8. "MPIE,Multi-Processor Interrupt Enable" "0: Non-multi-processor reception,1: Multi-processor reception When the data with the.." bitfld.long 0x0 4. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" newline bitfld.long 0x0 0. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" line.long 0x4 "CCR1,Common Control Register 1" bitfld.long 0x4 29. "NFM,Noise Filter Mode" "0: 3-point matching mode,1: Majority vote mode" bitfld.long 0x4 28. "NFEN,Digital Noise Filter Function Enable" "0: In Asynchronous Manchester Simple LIN modes:..,1: In Asynchronous Manchester Simple LIN modes:.." newline bitfld.long 0x4 24.--26. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: The on-chip baud rate generator source clock..,?,?,?,?,?,?" bitfld.long 0x4 20. "SHARPS,Half-Duplex Communication Select" "0: TXDn pin RXDn pin independent,1: TXDn/RXDn pin combination use (half-duplex.." newline bitfld.long 0x4 16. "SPLP,Loopback Control" "0: Normal mode,1: Loopback mode" bitfld.long 0x4 13. "RINV,RXD Invert" "0: Received data from RXDn is not inverted and input,1: Received data from RXDn is inverted and input" newline bitfld.long 0x4 12. "TINV,TXD Invert" "0: Transmit data is not inverted and output to TXDn,1: Transmit data is inverted and output to TXDn" bitfld.long 0x4 9. "PM,Parity Mode" "0: Selects even parity,1: Selects odd parity" newline bitfld.long 0x4 8. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.." bitfld.long 0x4 5. "SPB2IO,Serial Port Break I/O" "0: The value of SPB2DT bit is not output in TXDn pin,1: The value of SPB2DT bit is output in TXDn pin" newline bitfld.long 0x4 4. "SPB2DT,Serial Port Break Data Select" "0: When TINV is 0 low level is output in TXDn pin.,1: When TINV is 0 high level is output in TXDn pin." bitfld.long 0x4 1. "CTSPEN,CTS External Pin Enable" "0: Alternate setting to use CTS and RTS functions..,1: Dedicated setting for separately using CTS and.." newline bitfld.long 0x4 0. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled" line.long 0x8 "CCR2,Common Control Register 2" hexmask.long.byte 0x8 24.--31. 1. "MDDR,Modulation Duty Setting" bitfld.long 0x8 20.--21. "CKS,Clock Select" "0: TCLK clock (n = 0),1: TCLK/4 clock (n = 1),?,?" newline bitfld.long 0x8 16. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled,1: Bit rate modulation function is enabled" hexmask.long.byte 0x8 8.--15. 1. "BRR,Bit Rate Setting" newline bitfld.long 0x8 7. "ABCSE2,Asynchronous Mode Extended Base Clock Select 2" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 4 base clock cycles for 1-bit.." bitfld.long 0x8 6. "ABCSE,Asynchronous Mode Extended Base Clock Select" "0: Clock cycles for 1-bit period is determined by..,1: Baud rate is 6 base clock cycles for 1-bit.." newline bitfld.long 0x8 5. "ABCS,Asynchronous Mode Base Clock Select" "0: Selects 16 base clock cycles for 1-bit period,1: Selects 8 base clock cycles for 1-bit period" bitfld.long 0x8 4. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.long 0x8 0.--2. "BCP,Base Clock Pulse" "0: 93 clock cycles (S = 93),1: 128 clock cycles (S = 128),?,?,?,?,?,?" line.long 0xC "CCR3,Common Control Register 3" bitfld.long 0xC 29. "BLK,Block Transfer Mode" "0: Non-block transfer mode operation,1: Block transfer mode operation" bitfld.long 0xC 28. "GM,GSM Mode" "0: Non-GSM mode operation,1: GSM mode operation" newline bitfld.long 0xC 26. "ACS0,Asynchronous Mode Clock Source Select" "0: External clock input,1: Logical AND of compare matches output from the.." bitfld.long 0xC 24.--25. "CKE,Clock Enable" "0,1,2,3" newline bitfld.long 0xC 21. "DEN,Driver Enable" "0: RS-485 driver control function disabled,1: RS-485 driver control function enabled" bitfld.long 0xC 20. "FM,FIFO Mode Select" "0: TDR register and RDR register are non-FIFO..,1: TDR register and RDR register are FIFO buffer.." newline bitfld.long 0xC 19. "MP,Multi-Processor Mode" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" bitfld.long 0xC 16.--18. "MOD,Communication Mode Select" "0: Asynchronous mode (multi-processor mode),1: Smart card interface mode,?,?,?,?,?,?" newline bitfld.long 0xC 15. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.long 0xC 14. "STP,Stop Bit Length" "0: 1 stop bit/break delimiter length is 1-bit,1: 2 stop bits/break delimiter length is 2-bit" newline bitfld.long 0xC 13. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted to TSR as is. RSR..,1: TDR contents are inverted before being.." bitfld.long 0xC 12. "LSBF,LSB First select" "0: MSB-first,1: LSB-first" newline bitfld.long 0xC 8.--9. "CHR,Character Length" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 9-bit data length,?,?" bitfld.long 0xC 7. "BPEN,Synchronizer Bypass Enable" "0: Synchronizer circuit is not bypassed,1: Synchronizer circuit is bypassed" newline bitfld.long 0xC 1. "CPOL,Clock Polarity Select" "0: SCKn in idle state is 0,1: SCKn in idle state is 1" bitfld.long 0xC 0. "CPHA,Clock Phase Select" "0: Data is sampled at an odd edge and changes at an..,1: Data changes at an odd edge and is sampled at an.." line.long 0x10 "CCR4,Common Control Register 4" bitfld.long 0x10 31. "AET,Adjustment Edge for Transmit Timing" "0: When CCR1.TINV is 0 adjust the rising edge..,1: When CCR1.TINV is 0 adjust the falling edge.." bitfld.long 0x10 28.--30. "ATT,Adjustment Value for Transmit Timing" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "AJD,Adjustment Direction for Receive Sampling Timing" "0: The sampling timing is adjusted backward to the..,1: The sampling timing is adjusted forward to the.." bitfld.long 0x10 24.--26. "AST,Adjustment Value for Receive Sampling Timing" "0: Setting prohibited,1: 2-TCLK delay,?,?,?,?,?,?" newline bitfld.long 0x10 19. "SCKSEL,Master receive clock selection" "0: Master receive clock is disabled,1: Master receive clock is enabled" bitfld.long 0x10 17. "ATEN,Adjust Transmit Timing Enable" "0: Adjust transmit timing disabled,1: Adjust transmit timing enabled" newline bitfld.long 0x10 16. "ASEN,Adjust Receive Sampling Timing Enable" "0: Adjust sampling timing disabled,1: Adjust sampling timing enabled" hexmask.long.word 0x10 0.--8. 1. "CMPD,Compare Match Data" rgroup.byte 0x1C++0x0 line.byte 0x0 "CESR,Communication Enable Status Register" bitfld.byte 0x0 4. "TIST,TE Internal Status" "0: TE signal internal state value 0,1: TE signal internal state value 1" bitfld.byte 0x0 0. "RIST,RE Internal Status" "0: RE signal internal state value 0,1: RE signal internal state value 1" group.long 0x20++0x7 line.long 0x0 "ICR,Simple IIC Control Register" bitfld.long 0x0 22.--23. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition,?,?" bitfld.long 0x0 20.--21. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition,?,?" newline bitfld.long 0x0 18. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated" bitfld.long 0x0 17. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated,1: A restart condition is generated" newline bitfld.long 0x0 16. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated,1: A start condition is generated" bitfld.long 0x0 13. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.long 0x0 9. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" bitfld.long 0x0 8. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts" newline hexmask.long.byte 0x0 0.--4. 1. "IICDL,SDA Delay Output Select" line.long 0x4 "FCR,FIFO Control Register" hexmask.long.byte 0x4 24.--28. 1. "RSTRG,RTS Output Active Trigger Number Select" bitfld.long 0x4 23. "RFRST,Receive FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Receive-FIFO(RDR.." newline hexmask.long.byte 0x4 16.--20. 1. "RTRG,Receive FIFO Data Trigger Number" bitfld.long 0x4 15. "TFRST,Transmit FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Transmit-FIFO (TDR.." newline hexmask.long.byte 0x4 8.--12. 1. "TTRG,Transmit FIFO Data Trigger Number" bitfld.long 0x4 0. "DRES,Receive Data Ready Error Select Bit" "0: Reception data full interrupt (SCIn_RXI),1: Receive error interrupt (SCIn_ERI)" group.long 0x2C++0x13 line.long 0x0 "MCR,Manchester Control Register" bitfld.long 0x0 26. "SBEREN,Start Bit Error Enable" "0: Does not handle a start bit error as an..,1: Handles a start bit error as an interrupt source" bitfld.long 0x0 25. "SYEREN,Receive SYNC Error Enable" "0: Does not handle a receive SYNC error as an..,1: Handles a receive SYNC error as an interrupt.." newline bitfld.long 0x0 24. "PFEREN,Preface Error Enable" "0: Does not handle a preface error as an interrupt..,1: Handles a preface error as an interrupt source" bitfld.long 0x0 20.--21. "RPPAT,Receive Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 16.--19. 1. "RPLEN,Receive Preface Length" bitfld.long 0x0 12.--13. "TPPAT,Transmit Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "TPLEN,Transmit Preface Length" bitfld.long 0x0 6. "SBSEL,Start Bit Select" "0: The start bit area consists of one bit,1: The start bit area consists of three bits.." newline bitfld.long 0x0 5. "SYNSEL,SYNC Select" "0: The start bit pattern is set with the SYNVAL bit,1: The start bit pattern is set with the TSYNC bit" bitfld.long 0x0 4. "SYNVAL,SYNC value Setting" "0,1" newline bitfld.long 0x0 2. "ERTEN,Manchester Edge Retiming Enable" "0: Disables the receive retiming function,1: Enables the receive retiming function" bitfld.long 0x0 1. "TMPOL,Polarity of Transmit Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." newline bitfld.long 0x0 0. "RMPOL,Polarity of Received Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." line.long 0x4 "DCR,Driver Control Register" hexmask.long.byte 0x4 16.--20. 1. "DENGT,Driver Negate Time" hexmask.long.byte 0x4 8.--12. 1. "DEAST,Driver Assertion Time" newline bitfld.long 0x4 0. "DEPOL,Driver Effective Polarity Select" "0: The DEn signal is active-high,1: The DEn signal is active-low" line.long 0x8 "XCR0,Simple LIN Control Register 0" bitfld.long 0x8 24.--25. "BCCS,Bus Conflict Detection Clock Selection" "0: Base clock,1: Base clock/2,?,?" bitfld.long 0x8 22. "AEDIE,Active Edge Detection Interrupt Enable" "0: Active edge detection interrupt disabled,1: Active edge detection interrupt enabled" newline bitfld.long 0x8 21. "COFIE,Counter Overflow Interrupt Enable" "0: Counter overflow is not included in SCIn_ERI..,1: Counter overflow is included in SCIn_ERI.." bitfld.long 0x8 20. "BFDIE,Break Field Detection Interrupt Enable" "0: Break Field detection interrupt disabled,1: Break Field detection interrupt enabled" newline bitfld.long 0x8 17. "BCDIE,Bus Conflict Detection Interrupt Enable" "0: Bus conflict detection is not included in..,1: Bus conflict detection is included in SCIn_ERI.." bitfld.long 0x8 16. "BFOIE,Break Field Output Completion Interrupt Enable" "0: Break Field output completion is not included in..,1: Break Field output completion is included in.." newline bitfld.long 0x8 13.--15. "PIBS,Priority Interrupt Bit Select" "0: Bit 0 of Control Field 1,1: Bit 1 of Control Field 1,?,?,?,?,?,?" bitfld.long 0x8 12. "PIBE,Priority Interrupt Bit Enable" "0: Priority interrupt bit disabled,1: Priority interrupt bit enabled" newline bitfld.long 0x8 10.--11. "CF1DS,Control Field1 Compare Data Select" "0: Select XCR1.PCF1D[7:0] as the compare data,1: Select XCR1.SCF1D[7:0] as the compare data,?,?" bitfld.long 0x8 9. "CF0RE,Control Field 0 Enable" "0: No Control Field 0,1: With Control Field 0" newline bitfld.long 0x8 8. "BFE,Break Field Enable" "0: No Break Field,1: With Break Field" bitfld.long 0x8 0.--1. "TCSS,Timer Count Clock Source Selection" "?,1: TCLK/4,?,?" line.long 0xC "XCR1,Simple LIN Control Register 1" hexmask.long.byte 0xC 24.--31. 1. "CF1CE,Control Field 1 Compare Bit Enable" hexmask.long.byte 0xC 16.--23. 1. "SCF1D,Secondary Compare Data for Control Field 1" newline hexmask.long.byte 0xC 8.--15. 1. "PCF1D,Priority Compare Data for Control Field 1" bitfld.long 0xC 5. "BMEN,Bit Rate Measurement Enable" "0: Bit rate measurement disabled,1: Bit rate measurement enabled" newline bitfld.long 0xC 4. "SDST,Start Frame Detection Enable" "0: Start Frame/Break Field detection disabled,1: Start Frame/Break Field detection enabled" bitfld.long 0xC 0. "TCST,Break Field Output Timer Count Start Trigger" "0: Break Field output timer count stopped,1: Break Field output timer count start" line.long 0x10 "XCR2,Simple LIN Control Register 2" hexmask.long.word 0x10 16.--31. 1. "BFLW,Break Field Length Setting" hexmask.long.byte 0x10 8.--15. 1. "CF0CE,Control Field 0 Compare Bit Enable" newline hexmask.long.byte 0x10 0.--7. 1. "CF0D,Control Field 0 Compare Data" rgroup.long 0x48++0x1B line.long 0x0 "CSR,Common Status Register" bitfld.long 0x0 31. "RDRF,Receive Data Full Flag" "0: Non-FIFO selected (CCR3.FM = 0): No received..,1: Non-FIFO selected (CCR3.FM = 0): Received data.." bitfld.long 0x0 30. "TEND,Transmit End Flag" "0: A character is being transmitted or standing by..,1: Character transfer has been completed or sending.." newline bitfld.long 0x0 29. "TDRE,Transmit Data Empty Flag" "0: Non-FIFO selected (CCR3.FM = 0): Transmit data..,1: Non-FIFO selected (CCR3.FM = 0): No transmit.." bitfld.long 0x0 28. "FER,Framing Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No framing..,1: Non-FIFO selected (CCR3.FM = 0): A framing error.." newline bitfld.long 0x0 27. "PER,Parity Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No parity error..,1: Non-FIFO selected (CCR3.FM = 0): A parity error.." bitfld.long 0x0 26. "MFF,Mode Fault Error Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.long 0x0 24. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.long 0x0 18. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred at address match..,1: A framing error has occurred at address match.." newline bitfld.long 0x0 17. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred at address match..,1: A parity error has occurred at address match.." bitfld.long 0x0 16. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" newline bitfld.long 0x0 15. "RXDMON,Serial Input Data Monitor Bit" "0: When RINV is 0 RXDn pin is the low level. When..,1: When RINV is 0 RXDn pin is the high level. When.." bitfld.long 0x0 4. "ERS,Error Signal Status Flag" "0: Error signal low not responded,1: Error signal low responded" line.long 0x4 "ISR,Simple IIC Status Register" bitfld.long 0x4 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.long 0x4 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" line.long 0x8 "FRSR,FIFO Receive Status Register" hexmask.long.byte 0x8 24.--29. 1. "FNUM,Framing Error Count" hexmask.long.byte 0x8 16.--21. 1. "PNUM,Parity Error Count" newline hexmask.long.byte 0x8 8.--13. 1. "R,Receive-FIFO Data Count" bitfld.long 0x8 0. "DR,Receive Data Ready Flag" "0: Receiving is in progress or no received data..,1: The following receive data is not received for a.." line.long 0xC "FTSR,FIFO Transmit Status Register" hexmask.long.byte 0xC 0.--5. 1. "T,Transmit-FIFO Data Count" line.long 0x10 "MSR,Manchester Status Register" bitfld.long 0x10 6. "RSYNC,Receive SYNC Data Bit" "0: The received start bit is DATA SYNC,1: The received start bit is COMMAND SYNC" bitfld.long 0x10 4. "MER,Manchester Error Flag" "0: No Manchester error occurred,1: Manchester error has occurred" newline bitfld.long 0x10 2. "SBER,Start Bit Error Flag" "0: No start bit error detected,1: Start bit error detected" bitfld.long 0x10 1. "SYER,SYNC Error Flag" "0: No receive SYNC error detected,1: Receive SYNC error detected" newline bitfld.long 0x10 0. "PFER,Preface Error Flag" "0: No preface error detected,1: Preface error detected" line.long 0x14 "XSR0,Simple LIN Status Register 0" hexmask.long.byte 0x14 24.--31. 1. "CF1RD,Control Field 1 received data" hexmask.long.byte 0x14 16.--23. 1. "CF0RD,Control Field 0 received data" newline bitfld.long 0x14 15. "AEDF,Active Edge Detection Flag" "0: No valid edge detected,1: Detected a valid edge" bitfld.long 0x14 14. "COF,Counter Overflow Flag" "0: Break Field detection counter has not overflowed,1: Break Field detection counter overflowed" newline bitfld.long 0x14 13. "PIBDF,Priority Interrupt Bit Detection Flag" "0: Priority interrupt bit is not detected,1: Priority interrupt bit is detected" bitfld.long 0x14 12. "CF1MF,Control Field 1 Compare Match Flag" "0: Control Field 1 received data does not match the..,1: Control Field 1 received data matches the.." newline bitfld.long 0x14 11. "CF0MF,Control Field 0 Compare Match Flag" "0: Control Field 0 received data does not match the..,1: Control Field 0 received data matches the.." bitfld.long 0x14 10. "BFDF,Break Field Detection Flag" "0: Break Field is not detected,1: Break Field is detected" newline bitfld.long 0x14 9. "BCDF,Bus Conflict Detection Flag" "0: No bus collision detected,1: Detected a bus collision" bitfld.long 0x14 8. "BFOF,Break Field Output Completion Flag" "0: Break Field is being output or is not being output,1: Completed BF output" newline bitfld.long 0x14 1. "RXDSF,RXDn Input Status Flag" "0: RXDn input to SCI is enabled,1: RXDn input to SCI is disabled" bitfld.long 0x14 0. "SFSF,Start Frame Status Flag" "0: Start Frame detection disabled or Start Frame..,1: Before Start Frame detection or during detection" line.long 0x18 "XSR1,Simple LIN Status Register 1" hexmask.long.word 0x18 0.--15. 1. "TCNT,Timer Count Capture Value" wgroup.long 0x68++0x13 line.long 0x0 "CFCLR,Common Flag Clear Register" bitfld.long 0x0 31. "RDRFC,RDRF Clear Bit" "0,1" bitfld.long 0x0 29. "TDREC,TDRE Clear Bit" "0,1" newline bitfld.long 0x0 28. "FERC,FER Clear Bit" "0,1" bitfld.long 0x0 27. "PERC,PER Clear Bit" "0,1" newline bitfld.long 0x0 26. "MFFC,MFF Clear Bit" "0,1" bitfld.long 0x0 24. "ORERC,ORER Clear Bit" "0,1" newline bitfld.long 0x0 18. "DFERC,DFER Clear Bit" "0,1" bitfld.long 0x0 17. "DPERC,DPER Clear Bit" "0,1" newline bitfld.long 0x0 16. "DCMFC,DCMF Clear Bit" "0,1" bitfld.long 0x0 4. "ERSC,ERS Clear Bit" "0,1" line.long 0x4 "ICFCLR,Simple IIC Flag Clear Register" bitfld.long 0x4 3. "IICSTIFC,IICSTIF Clear Bit" "0,1" line.long 0x8 "FFCLR,FIFO Flag Clear Register" bitfld.long 0x8 0. "DRC,DR Clear Bit" "0,1" line.long 0xC "MFCLR,Manchester Flag Clear Register" bitfld.long 0xC 4. "MERC,MER Clear Bit" "0,1" bitfld.long 0xC 2. "SBERC,SBER Clear Bit" "0,1" newline bitfld.long 0xC 1. "SYERC,SYER Clear Bit" "0,1" bitfld.long 0xC 0. "PFERC,PFER Clear Bit" "0,1" line.long 0x10 "XFCLR,Simple LIN Flag Clear Register" bitfld.long 0x10 15. "AEDC,AEDF Clear Bit" "0,1" bitfld.long 0x10 14. "COFC,COFF Clear Bit" "0,1" newline bitfld.long 0x10 13. "PIBDC,PIBDF Clear Bit" "0,1" bitfld.long 0x10 12. "CF1MC,CF1MF Clear Bit" "0,1" newline bitfld.long 0x10 11. "CF0MC,CF0MF Clear Bit" "0,1" bitfld.long 0x10 10. "BFDC,BFDF Clear Bit" "0,1" newline bitfld.long 0x10 9. "BCDC,BCDF Clear Bit" "0,1" bitfld.long 0x10 8. "BFOC,BFOF Clear Bit" "0,1" tree.end tree "SCI9_B" base ad:0x40358900 rgroup.long 0x0++0x3 line.long 0x0 "RDR,Receive Data Register" bitfld.long 0x0 28. "FER,Framing error flag" "0,1" bitfld.long 0x0 27. "PER,Parity error flag" "0,1" newline bitfld.long 0x0 24. "ORER,Overrun Error flag" "0,1" bitfld.long 0x0 12. "FFER,FIFO framing error flag" "0: There is no framing error in the data read from..,1: There is framing error in the data read from the.." newline bitfld.long 0x0 11. "FPER,FIFO parity error flag" "0: There is no parity error in the data read from..,1: There is parity error in the data read from the.." bitfld.long 0x0 10. "DR,Receive data ready flag" "0,1" newline bitfld.long 0x0 9. "MPB,Multi-processor flag" "0: Data transmission cycles,1: ID transmission cycles" hexmask.long.word 0x0 0.--8. 1. "RDAT,Serial receive data" rgroup.byte 0x0++0x0 line.byte 0x0 "RDR_BY,Receive Data Register" bitfld.byte 0x0 4. "FER,Framing error flag" "0,1" bitfld.byte 0x0 3. "PER,Parity error flag" "0,1" newline bitfld.byte 0x0 0. "ORER,Overrun Error flag" "0,1" group.long 0x4++0x3 line.long 0x0 "TDR,Transmit Data Register" bitfld.long 0x0 12. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.long 0x0 9. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline hexmask.long.word 0x0 0.--8. 1. "TDAT,Serial transmit data" group.byte 0x4++0x1 line.byte 0x0 "TDRLL,Transmit Data Register" line.byte 0x1 "TDRLH,Transmit Data Register" bitfld.byte 0x1 4. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.byte 0x1 1. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline bitfld.byte 0x1 0. "TDAT,Serial transmit data" "0,1" group.long 0x8++0x13 line.long 0x0 "CCR0,Common Control Register 0" bitfld.long 0x0 24. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled,1: SSn pin function is enabled" bitfld.long 0x0 21. "TEIE,Transmit End Interrupt Enable" "0: SCIn_TEI interrupt request is disabled,1: SCIn_TEI interrupt request is enabled" newline bitfld.long 0x0 20. "TIE,Transmit Interrupt Enable" "0: SCIn_TXI interrupt request is disabled,1: SCIn_TXI interrupt request is enabled" bitfld.long 0x0 16. "RIE,Receive Interrupt Enable" "0: SCIn_RXI and SCIn_ERI interrupt requests are..,1: SCIn_RXI and SCIn_ERI interrupt requests are.." newline bitfld.long 0x0 10. "IDSEL,ID Frame Select" "0: Compare data irrespective of the value of the..,1: Compare data only when the MPB bit is 1 (ID frame)" bitfld.long 0x0 9. "DCME,Data Compare Match Enable" "0: Address match function is disabled,1: Address match function is enabled" newline bitfld.long 0x0 8. "MPIE,Multi-Processor Interrupt Enable" "0: Non-multi-processor reception,1: Multi-processor reception When the data with the.." bitfld.long 0x0 4. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" newline bitfld.long 0x0 0. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" line.long 0x4 "CCR1,Common Control Register 1" bitfld.long 0x4 29. "NFM,Noise Filter Mode" "0: 3-point matching mode,1: Majority vote mode" bitfld.long 0x4 28. "NFEN,Digital Noise Filter Function Enable" "0: In Asynchronous Manchester Simple LIN modes:..,1: In Asynchronous Manchester Simple LIN modes:.." newline bitfld.long 0x4 24.--26. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: The on-chip baud rate generator source clock..,?,?,?,?,?,?" bitfld.long 0x4 20. "SHARPS,Half-Duplex Communication Select" "0: TXDn pin RXDn pin independent,1: TXDn/RXDn pin combination use (half-duplex.." newline bitfld.long 0x4 16. "SPLP,Loopback Control" "0: Normal mode,1: Loopback mode" bitfld.long 0x4 13. "RINV,RXD Invert" "0: Received data from RXDn is not inverted and input,1: Received data from RXDn is inverted and input" newline bitfld.long 0x4 12. "TINV,TXD Invert" "0: Transmit data is not inverted and output to TXDn,1: Transmit data is inverted and output to TXDn" bitfld.long 0x4 9. "PM,Parity Mode" "0: Selects even parity,1: Selects odd parity" newline bitfld.long 0x4 8. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.." bitfld.long 0x4 5. "SPB2IO,Serial Port Break I/O" "0: The value of SPB2DT bit is not output in TXDn pin,1: The value of SPB2DT bit is output in TXDn pin" newline bitfld.long 0x4 4. "SPB2DT,Serial Port Break Data Select" "0: When TINV is 0 low level is output in TXDn pin.,1: When TINV is 0 high level is output in TXDn pin." bitfld.long 0x4 1. "CTSPEN,CTS External Pin Enable" "0: Alternate setting to use CTS and RTS functions..,1: Dedicated setting for separately using CTS and.." newline bitfld.long 0x4 0. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled" line.long 0x8 "CCR2,Common Control Register 2" hexmask.long.byte 0x8 24.--31. 1. "MDDR,Modulation Duty Setting" bitfld.long 0x8 20.--21. "CKS,Clock Select" "0: TCLK clock (n = 0),1: TCLK/4 clock (n = 1),?,?" newline bitfld.long 0x8 16. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled,1: Bit rate modulation function is enabled" hexmask.long.byte 0x8 8.--15. 1. "BRR,Bit Rate Setting" newline bitfld.long 0x8 7. "ABCSE2,Asynchronous Mode Extended Base Clock Select 2" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 4 base clock cycles for 1-bit.." bitfld.long 0x8 6. "ABCSE,Asynchronous Mode Extended Base Clock Select" "0: Clock cycles for 1-bit period is determined by..,1: Baud rate is 6 base clock cycles for 1-bit.." newline bitfld.long 0x8 5. "ABCS,Asynchronous Mode Base Clock Select" "0: Selects 16 base clock cycles for 1-bit period,1: Selects 8 base clock cycles for 1-bit period" bitfld.long 0x8 4. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.long 0x8 0.--2. "BCP,Base Clock Pulse" "0: 93 clock cycles (S = 93),1: 128 clock cycles (S = 128),?,?,?,?,?,?" line.long 0xC "CCR3,Common Control Register 3" bitfld.long 0xC 29. "BLK,Block Transfer Mode" "0: Non-block transfer mode operation,1: Block transfer mode operation" bitfld.long 0xC 28. "GM,GSM Mode" "0: Non-GSM mode operation,1: GSM mode operation" newline bitfld.long 0xC 26. "ACS0,Asynchronous Mode Clock Source Select" "0: External clock input,1: Logical AND of compare matches output from the.." bitfld.long 0xC 24.--25. "CKE,Clock Enable" "0,1,2,3" newline bitfld.long 0xC 21. "DEN,Driver Enable" "0: RS-485 driver control function disabled,1: RS-485 driver control function enabled" bitfld.long 0xC 20. "FM,FIFO Mode Select" "0: TDR register and RDR register are non-FIFO..,1: TDR register and RDR register are FIFO buffer.." newline bitfld.long 0xC 19. "MP,Multi-Processor Mode" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" bitfld.long 0xC 16.--18. "MOD,Communication Mode Select" "0: Asynchronous mode (multi-processor mode),1: Smart card interface mode,?,?,?,?,?,?" newline bitfld.long 0xC 15. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.long 0xC 14. "STP,Stop Bit Length" "0: 1 stop bit/break delimiter length is 1-bit,1: 2 stop bits/break delimiter length is 2-bit" newline bitfld.long 0xC 13. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted to TSR as is. RSR..,1: TDR contents are inverted before being.." bitfld.long 0xC 12. "LSBF,LSB First select" "0: MSB-first,1: LSB-first" newline bitfld.long 0xC 8.--9. "CHR,Character Length" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 9-bit data length,?,?" bitfld.long 0xC 7. "BPEN,Synchronizer Bypass Enable" "0: Synchronizer circuit is not bypassed,1: Synchronizer circuit is bypassed" newline bitfld.long 0xC 1. "CPOL,Clock Polarity Select" "0: SCKn in idle state is 0,1: SCKn in idle state is 1" bitfld.long 0xC 0. "CPHA,Clock Phase Select" "0: Data is sampled at an odd edge and changes at an..,1: Data changes at an odd edge and is sampled at an.." line.long 0x10 "CCR4,Common Control Register 4" bitfld.long 0x10 31. "AET,Adjustment Edge for Transmit Timing" "0: When CCR1.TINV is 0 adjust the rising edge..,1: When CCR1.TINV is 0 adjust the falling edge.." bitfld.long 0x10 28.--30. "ATT,Adjustment Value for Transmit Timing" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "AJD,Adjustment Direction for Receive Sampling Timing" "0: The sampling timing is adjusted backward to the..,1: The sampling timing is adjusted forward to the.." bitfld.long 0x10 24.--26. "AST,Adjustment Value for Receive Sampling Timing" "0: Setting prohibited,1: 2-TCLK delay,?,?,?,?,?,?" newline bitfld.long 0x10 19. "SCKSEL,Master receive clock selection" "0: Master receive clock is disabled,1: Master receive clock is enabled" bitfld.long 0x10 17. "ATEN,Adjust Transmit Timing Enable" "0: Adjust transmit timing disabled,1: Adjust transmit timing enabled" newline bitfld.long 0x10 16. "ASEN,Adjust Receive Sampling Timing Enable" "0: Adjust sampling timing disabled,1: Adjust sampling timing enabled" hexmask.long.word 0x10 0.--8. 1. "CMPD,Compare Match Data" rgroup.byte 0x1C++0x0 line.byte 0x0 "CESR,Communication Enable Status Register" bitfld.byte 0x0 4. "TIST,TE Internal Status" "0: TE signal internal state value 0,1: TE signal internal state value 1" bitfld.byte 0x0 0. "RIST,RE Internal Status" "0: RE signal internal state value 0,1: RE signal internal state value 1" group.long 0x20++0x7 line.long 0x0 "ICR,Simple IIC Control Register" bitfld.long 0x0 22.--23. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition,?,?" bitfld.long 0x0 20.--21. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition,?,?" newline bitfld.long 0x0 18. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated" bitfld.long 0x0 17. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated,1: A restart condition is generated" newline bitfld.long 0x0 16. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated,1: A start condition is generated" bitfld.long 0x0 13. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.long 0x0 9. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" bitfld.long 0x0 8. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts" newline hexmask.long.byte 0x0 0.--4. 1. "IICDL,SDA Delay Output Select" line.long 0x4 "FCR,FIFO Control Register" hexmask.long.byte 0x4 24.--28. 1. "RSTRG,RTS Output Active Trigger Number Select" bitfld.long 0x4 23. "RFRST,Receive FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Receive-FIFO(RDR.." newline hexmask.long.byte 0x4 16.--20. 1. "RTRG,Receive FIFO Data Trigger Number" bitfld.long 0x4 15. "TFRST,Transmit FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Transmit-FIFO (TDR.." newline hexmask.long.byte 0x4 8.--12. 1. "TTRG,Transmit FIFO Data Trigger Number" bitfld.long 0x4 0. "DRES,Receive Data Ready Error Select Bit" "0: Reception data full interrupt (SCIn_RXI),1: Receive error interrupt (SCIn_ERI)" group.long 0x2C++0x13 line.long 0x0 "MCR,Manchester Control Register" bitfld.long 0x0 26. "SBEREN,Start Bit Error Enable" "0: Does not handle a start bit error as an..,1: Handles a start bit error as an interrupt source" bitfld.long 0x0 25. "SYEREN,Receive SYNC Error Enable" "0: Does not handle a receive SYNC error as an..,1: Handles a receive SYNC error as an interrupt.." newline bitfld.long 0x0 24. "PFEREN,Preface Error Enable" "0: Does not handle a preface error as an interrupt..,1: Handles a preface error as an interrupt source" bitfld.long 0x0 20.--21. "RPPAT,Receive Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 16.--19. 1. "RPLEN,Receive Preface Length" bitfld.long 0x0 12.--13. "TPPAT,Transmit Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "TPLEN,Transmit Preface Length" bitfld.long 0x0 6. "SBSEL,Start Bit Select" "0: The start bit area consists of one bit,1: The start bit area consists of three bits.." newline bitfld.long 0x0 5. "SYNSEL,SYNC Select" "0: The start bit pattern is set with the SYNVAL bit,1: The start bit pattern is set with the TSYNC bit" bitfld.long 0x0 4. "SYNVAL,SYNC value Setting" "0,1" newline bitfld.long 0x0 2. "ERTEN,Manchester Edge Retiming Enable" "0: Disables the receive retiming function,1: Enables the receive retiming function" bitfld.long 0x0 1. "TMPOL,Polarity of Transmit Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." newline bitfld.long 0x0 0. "RMPOL,Polarity of Received Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." line.long 0x4 "DCR,Driver Control Register" hexmask.long.byte 0x4 16.--20. 1. "DENGT,Driver Negate Time" hexmask.long.byte 0x4 8.--12. 1. "DEAST,Driver Assertion Time" newline bitfld.long 0x4 0. "DEPOL,Driver Effective Polarity Select" "0: The DEn signal is active-high,1: The DEn signal is active-low" line.long 0x8 "XCR0,Simple LIN Control Register 0" bitfld.long 0x8 24.--25. "BCCS,Bus Conflict Detection Clock Selection" "0: Base clock,1: Base clock/2,?,?" bitfld.long 0x8 22. "AEDIE,Active Edge Detection Interrupt Enable" "0: Active edge detection interrupt disabled,1: Active edge detection interrupt enabled" newline bitfld.long 0x8 21. "COFIE,Counter Overflow Interrupt Enable" "0: Counter overflow is not included in SCIn_ERI..,1: Counter overflow is included in SCIn_ERI.." bitfld.long 0x8 20. "BFDIE,Break Field Detection Interrupt Enable" "0: Break Field detection interrupt disabled,1: Break Field detection interrupt enabled" newline bitfld.long 0x8 17. "BCDIE,Bus Conflict Detection Interrupt Enable" "0: Bus conflict detection is not included in..,1: Bus conflict detection is included in SCIn_ERI.." bitfld.long 0x8 16. "BFOIE,Break Field Output Completion Interrupt Enable" "0: Break Field output completion is not included in..,1: Break Field output completion is included in.." newline bitfld.long 0x8 13.--15. "PIBS,Priority Interrupt Bit Select" "0: Bit 0 of Control Field 1,1: Bit 1 of Control Field 1,?,?,?,?,?,?" bitfld.long 0x8 12. "PIBE,Priority Interrupt Bit Enable" "0: Priority interrupt bit disabled,1: Priority interrupt bit enabled" newline bitfld.long 0x8 10.--11. "CF1DS,Control Field1 Compare Data Select" "0: Select XCR1.PCF1D[7:0] as the compare data,1: Select XCR1.SCF1D[7:0] as the compare data,?,?" bitfld.long 0x8 9. "CF0RE,Control Field 0 Enable" "0: No Control Field 0,1: With Control Field 0" newline bitfld.long 0x8 8. "BFE,Break Field Enable" "0: No Break Field,1: With Break Field" bitfld.long 0x8 0.--1. "TCSS,Timer Count Clock Source Selection" "?,1: TCLK/4,?,?" line.long 0xC "XCR1,Simple LIN Control Register 1" hexmask.long.byte 0xC 24.--31. 1. "CF1CE,Control Field 1 Compare Bit Enable" hexmask.long.byte 0xC 16.--23. 1. "SCF1D,Secondary Compare Data for Control Field 1" newline hexmask.long.byte 0xC 8.--15. 1. "PCF1D,Priority Compare Data for Control Field 1" bitfld.long 0xC 5. "BMEN,Bit Rate Measurement Enable" "0: Bit rate measurement disabled,1: Bit rate measurement enabled" newline bitfld.long 0xC 4. "SDST,Start Frame Detection Enable" "0: Start Frame/Break Field detection disabled,1: Start Frame/Break Field detection enabled" bitfld.long 0xC 0. "TCST,Break Field Output Timer Count Start Trigger" "0: Break Field output timer count stopped,1: Break Field output timer count start" line.long 0x10 "XCR2,Simple LIN Control Register 2" hexmask.long.word 0x10 16.--31. 1. "BFLW,Break Field Length Setting" hexmask.long.byte 0x10 8.--15. 1. "CF0CE,Control Field 0 Compare Bit Enable" newline hexmask.long.byte 0x10 0.--7. 1. "CF0D,Control Field 0 Compare Data" rgroup.long 0x48++0x1B line.long 0x0 "CSR,Common Status Register" bitfld.long 0x0 31. "RDRF,Receive Data Full Flag" "0: Non-FIFO selected (CCR3.FM = 0): No received..,1: Non-FIFO selected (CCR3.FM = 0): Received data.." bitfld.long 0x0 30. "TEND,Transmit End Flag" "0: A character is being transmitted or standing by..,1: Character transfer has been completed or sending.." newline bitfld.long 0x0 29. "TDRE,Transmit Data Empty Flag" "0: Non-FIFO selected (CCR3.FM = 0): Transmit data..,1: Non-FIFO selected (CCR3.FM = 0): No transmit.." bitfld.long 0x0 28. "FER,Framing Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No framing..,1: Non-FIFO selected (CCR3.FM = 0): A framing error.." newline bitfld.long 0x0 27. "PER,Parity Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No parity error..,1: Non-FIFO selected (CCR3.FM = 0): A parity error.." bitfld.long 0x0 26. "MFF,Mode Fault Error Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.long 0x0 24. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.long 0x0 18. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred at address match..,1: A framing error has occurred at address match.." newline bitfld.long 0x0 17. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred at address match..,1: A parity error has occurred at address match.." bitfld.long 0x0 16. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" newline bitfld.long 0x0 15. "RXDMON,Serial Input Data Monitor Bit" "0: When RINV is 0 RXDn pin is the low level. When..,1: When RINV is 0 RXDn pin is the high level. When.." bitfld.long 0x0 4. "ERS,Error Signal Status Flag" "0: Error signal low not responded,1: Error signal low responded" line.long 0x4 "ISR,Simple IIC Status Register" bitfld.long 0x4 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.long 0x4 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" line.long 0x8 "FRSR,FIFO Receive Status Register" hexmask.long.byte 0x8 24.--29. 1. "FNUM,Framing Error Count" hexmask.long.byte 0x8 16.--21. 1. "PNUM,Parity Error Count" newline hexmask.long.byte 0x8 8.--13. 1. "R,Receive-FIFO Data Count" bitfld.long 0x8 0. "DR,Receive Data Ready Flag" "0: Receiving is in progress or no received data..,1: The following receive data is not received for a.." line.long 0xC "FTSR,FIFO Transmit Status Register" hexmask.long.byte 0xC 0.--5. 1. "T,Transmit-FIFO Data Count" line.long 0x10 "MSR,Manchester Status Register" bitfld.long 0x10 6. "RSYNC,Receive SYNC Data Bit" "0: The received start bit is DATA SYNC,1: The received start bit is COMMAND SYNC" bitfld.long 0x10 4. "MER,Manchester Error Flag" "0: No Manchester error occurred,1: Manchester error has occurred" newline bitfld.long 0x10 2. "SBER,Start Bit Error Flag" "0: No start bit error detected,1: Start bit error detected" bitfld.long 0x10 1. "SYER,SYNC Error Flag" "0: No receive SYNC error detected,1: Receive SYNC error detected" newline bitfld.long 0x10 0. "PFER,Preface Error Flag" "0: No preface error detected,1: Preface error detected" line.long 0x14 "XSR0,Simple LIN Status Register 0" hexmask.long.byte 0x14 24.--31. 1. "CF1RD,Control Field 1 received data" hexmask.long.byte 0x14 16.--23. 1. "CF0RD,Control Field 0 received data" newline bitfld.long 0x14 15. "AEDF,Active Edge Detection Flag" "0: No valid edge detected,1: Detected a valid edge" bitfld.long 0x14 14. "COF,Counter Overflow Flag" "0: Break Field detection counter has not overflowed,1: Break Field detection counter overflowed" newline bitfld.long 0x14 13. "PIBDF,Priority Interrupt Bit Detection Flag" "0: Priority interrupt bit is not detected,1: Priority interrupt bit is detected" bitfld.long 0x14 12. "CF1MF,Control Field 1 Compare Match Flag" "0: Control Field 1 received data does not match the..,1: Control Field 1 received data matches the.." newline bitfld.long 0x14 11. "CF0MF,Control Field 0 Compare Match Flag" "0: Control Field 0 received data does not match the..,1: Control Field 0 received data matches the.." bitfld.long 0x14 10. "BFDF,Break Field Detection Flag" "0: Break Field is not detected,1: Break Field is detected" newline bitfld.long 0x14 9. "BCDF,Bus Conflict Detection Flag" "0: No bus collision detected,1: Detected a bus collision" bitfld.long 0x14 8. "BFOF,Break Field Output Completion Flag" "0: Break Field is being output or is not being output,1: Completed BF output" newline bitfld.long 0x14 1. "RXDSF,RXDn Input Status Flag" "0: RXDn input to SCI is enabled,1: RXDn input to SCI is disabled" bitfld.long 0x14 0. "SFSF,Start Frame Status Flag" "0: Start Frame detection disabled or Start Frame..,1: Before Start Frame detection or during detection" line.long 0x18 "XSR1,Simple LIN Status Register 1" hexmask.long.word 0x18 0.--15. 1. "TCNT,Timer Count Capture Value" wgroup.long 0x68++0x13 line.long 0x0 "CFCLR,Common Flag Clear Register" bitfld.long 0x0 31. "RDRFC,RDRF Clear Bit" "0,1" bitfld.long 0x0 29. "TDREC,TDRE Clear Bit" "0,1" newline bitfld.long 0x0 28. "FERC,FER Clear Bit" "0,1" bitfld.long 0x0 27. "PERC,PER Clear Bit" "0,1" newline bitfld.long 0x0 26. "MFFC,MFF Clear Bit" "0,1" bitfld.long 0x0 24. "ORERC,ORER Clear Bit" "0,1" newline bitfld.long 0x0 18. "DFERC,DFER Clear Bit" "0,1" bitfld.long 0x0 17. "DPERC,DPER Clear Bit" "0,1" newline bitfld.long 0x0 16. "DCMFC,DCMF Clear Bit" "0,1" bitfld.long 0x0 4. "ERSC,ERS Clear Bit" "0,1" line.long 0x4 "ICFCLR,Simple IIC Flag Clear Register" bitfld.long 0x4 3. "IICSTIFC,IICSTIF Clear Bit" "0,1" line.long 0x8 "FFCLR,FIFO Flag Clear Register" bitfld.long 0x8 0. "DRC,DR Clear Bit" "0,1" line.long 0xC "MFCLR,Manchester Flag Clear Register" bitfld.long 0xC 4. "MERC,MER Clear Bit" "0,1" bitfld.long 0xC 2. "SBERC,SBER Clear Bit" "0,1" newline bitfld.long 0xC 1. "SYERC,SYER Clear Bit" "0,1" bitfld.long 0xC 0. "PFERC,PFER Clear Bit" "0,1" line.long 0x10 "XFCLR,Simple LIN Flag Clear Register" bitfld.long 0x10 15. "AEDC,AEDF Clear Bit" "0,1" bitfld.long 0x10 14. "COFC,COFF Clear Bit" "0,1" newline bitfld.long 0x10 13. "PIBDC,PIBDF Clear Bit" "0,1" bitfld.long 0x10 12. "CF1MC,CF1MF Clear Bit" "0,1" newline bitfld.long 0x10 11. "CF0MC,CF0MF Clear Bit" "0,1" bitfld.long 0x10 10. "BFDC,BFDF Clear Bit" "0,1" newline bitfld.long 0x10 9. "BCDC,BCDF Clear Bit" "0,1" bitfld.long 0x10 8. "BFOC,BFOF Clear Bit" "0,1" tree.end tree "SCI9_B_NS" base ad:0x50358900 rgroup.long 0x0++0x3 line.long 0x0 "RDR,Receive Data Register" bitfld.long 0x0 28. "FER,Framing error flag" "0,1" bitfld.long 0x0 27. "PER,Parity error flag" "0,1" newline bitfld.long 0x0 24. "ORER,Overrun Error flag" "0,1" bitfld.long 0x0 12. "FFER,FIFO framing error flag" "0: There is no framing error in the data read from..,1: There is framing error in the data read from the.." newline bitfld.long 0x0 11. "FPER,FIFO parity error flag" "0: There is no parity error in the data read from..,1: There is parity error in the data read from the.." bitfld.long 0x0 10. "DR,Receive data ready flag" "0,1" newline bitfld.long 0x0 9. "MPB,Multi-processor flag" "0: Data transmission cycles,1: ID transmission cycles" hexmask.long.word 0x0 0.--8. 1. "RDAT,Serial receive data" rgroup.byte 0x0++0x0 line.byte 0x0 "RDR_BY,Receive Data Register" bitfld.byte 0x0 4. "FER,Framing error flag" "0,1" bitfld.byte 0x0 3. "PER,Parity error flag" "0,1" newline bitfld.byte 0x0 0. "ORER,Overrun Error flag" "0,1" group.long 0x4++0x3 line.long 0x0 "TDR,Transmit Data Register" bitfld.long 0x0 12. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.long 0x0 9. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline hexmask.long.word 0x0 0.--8. 1. "TDAT,Serial transmit data" group.byte 0x4++0x1 line.byte 0x0 "TDRLL,Transmit Data Register" line.byte 0x1 "TDRLH,Transmit Data Register" bitfld.byte 0x1 4. "TSYNC,Transmit SYNC data" "0: The Start Bit is transmitted as DATA SYNC.,1: The Start Bit is transmitted as COMMAND SYNC." bitfld.byte 0x1 1. "MPBT,Multi-processor transfer bit flag" "0: Data transmission cycles,1: ID transmission cycles" newline bitfld.byte 0x1 0. "TDAT,Serial transmit data" "0,1" group.long 0x8++0x13 line.long 0x0 "CCR0,Common Control Register 0" bitfld.long 0x0 24. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled,1: SSn pin function is enabled" bitfld.long 0x0 21. "TEIE,Transmit End Interrupt Enable" "0: SCIn_TEI interrupt request is disabled,1: SCIn_TEI interrupt request is enabled" newline bitfld.long 0x0 20. "TIE,Transmit Interrupt Enable" "0: SCIn_TXI interrupt request is disabled,1: SCIn_TXI interrupt request is enabled" bitfld.long 0x0 16. "RIE,Receive Interrupt Enable" "0: SCIn_RXI and SCIn_ERI interrupt requests are..,1: SCIn_RXI and SCIn_ERI interrupt requests are.." newline bitfld.long 0x0 10. "IDSEL,ID Frame Select" "0: Compare data irrespective of the value of the..,1: Compare data only when the MPB bit is 1 (ID frame)" bitfld.long 0x0 9. "DCME,Data Compare Match Enable" "0: Address match function is disabled,1: Address match function is enabled" newline bitfld.long 0x0 8. "MPIE,Multi-Processor Interrupt Enable" "0: Non-multi-processor reception,1: Multi-processor reception When the data with the.." bitfld.long 0x0 4. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" newline bitfld.long 0x0 0. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" line.long 0x4 "CCR1,Common Control Register 1" bitfld.long 0x4 29. "NFM,Noise Filter Mode" "0: 3-point matching mode,1: Majority vote mode" bitfld.long 0x4 28. "NFEN,Digital Noise Filter Function Enable" "0: In Asynchronous Manchester Simple LIN modes:..,1: In Asynchronous Manchester Simple LIN modes:.." newline bitfld.long 0x4 24.--26. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: The on-chip baud rate generator source clock..,?,?,?,?,?,?" bitfld.long 0x4 20. "SHARPS,Half-Duplex Communication Select" "0: TXDn pin RXDn pin independent,1: TXDn/RXDn pin combination use (half-duplex.." newline bitfld.long 0x4 16. "SPLP,Loopback Control" "0: Normal mode,1: Loopback mode" bitfld.long 0x4 13. "RINV,RXD Invert" "0: Received data from RXDn is not inverted and input,1: Received data from RXDn is inverted and input" newline bitfld.long 0x4 12. "TINV,TXD Invert" "0: Transmit data is not inverted and output to TXDn,1: Transmit data is inverted and output to TXDn" bitfld.long 0x4 9. "PM,Parity Mode" "0: Selects even parity,1: Selects odd parity" newline bitfld.long 0x4 8. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.." bitfld.long 0x4 5. "SPB2IO,Serial Port Break I/O" "0: The value of SPB2DT bit is not output in TXDn pin,1: The value of SPB2DT bit is output in TXDn pin" newline bitfld.long 0x4 4. "SPB2DT,Serial Port Break Data Select" "0: When TINV is 0 low level is output in TXDn pin.,1: When TINV is 0 high level is output in TXDn pin." bitfld.long 0x4 1. "CTSPEN,CTS External Pin Enable" "0: Alternate setting to use CTS and RTS functions..,1: Dedicated setting for separately using CTS and.." newline bitfld.long 0x4 0. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled" line.long 0x8 "CCR2,Common Control Register 2" hexmask.long.byte 0x8 24.--31. 1. "MDDR,Modulation Duty Setting" bitfld.long 0x8 20.--21. "CKS,Clock Select" "0: TCLK clock (n = 0),1: TCLK/4 clock (n = 1),?,?" newline bitfld.long 0x8 16. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled,1: Bit rate modulation function is enabled" hexmask.long.byte 0x8 8.--15. 1. "BRR,Bit Rate Setting" newline bitfld.long 0x8 7. "ABCSE2,Asynchronous Mode Extended Base Clock Select 2" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 4 base clock cycles for 1-bit.." bitfld.long 0x8 6. "ABCSE,Asynchronous Mode Extended Base Clock Select" "0: Clock cycles for 1-bit period is determined by..,1: Baud rate is 6 base clock cycles for 1-bit.." newline bitfld.long 0x8 5. "ABCS,Asynchronous Mode Base Clock Select" "0: Selects 16 base clock cycles for 1-bit period,1: Selects 8 base clock cycles for 1-bit period" bitfld.long 0x8 4. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.long 0x8 0.--2. "BCP,Base Clock Pulse" "0: 93 clock cycles (S = 93),1: 128 clock cycles (S = 128),?,?,?,?,?,?" line.long 0xC "CCR3,Common Control Register 3" bitfld.long 0xC 29. "BLK,Block Transfer Mode" "0: Non-block transfer mode operation,1: Block transfer mode operation" bitfld.long 0xC 28. "GM,GSM Mode" "0: Non-GSM mode operation,1: GSM mode operation" newline bitfld.long 0xC 26. "ACS0,Asynchronous Mode Clock Source Select" "0: External clock input,1: Logical AND of compare matches output from the.." bitfld.long 0xC 24.--25. "CKE,Clock Enable" "0,1,2,3" newline bitfld.long 0xC 21. "DEN,Driver Enable" "0: RS-485 driver control function disabled,1: RS-485 driver control function enabled" bitfld.long 0xC 20. "FM,FIFO Mode Select" "0: TDR register and RDR register are non-FIFO..,1: TDR register and RDR register are FIFO buffer.." newline bitfld.long 0xC 19. "MP,Multi-Processor Mode" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" bitfld.long 0xC 16.--18. "MOD,Communication Mode Select" "0: Asynchronous mode (multi-processor mode),1: Smart card interface mode,?,?,?,?,?,?" newline bitfld.long 0xC 15. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.long 0xC 14. "STP,Stop Bit Length" "0: 1 stop bit/break delimiter length is 1-bit,1: 2 stop bits/break delimiter length is 2-bit" newline bitfld.long 0xC 13. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted to TSR as is. RSR..,1: TDR contents are inverted before being.." bitfld.long 0xC 12. "LSBF,LSB First select" "0: MSB-first,1: LSB-first" newline bitfld.long 0xC 8.--9. "CHR,Character Length" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 9-bit data length,?,?" bitfld.long 0xC 7. "BPEN,Synchronizer Bypass Enable" "0: Synchronizer circuit is not bypassed,1: Synchronizer circuit is bypassed" newline bitfld.long 0xC 1. "CPOL,Clock Polarity Select" "0: SCKn in idle state is 0,1: SCKn in idle state is 1" bitfld.long 0xC 0. "CPHA,Clock Phase Select" "0: Data is sampled at an odd edge and changes at an..,1: Data changes at an odd edge and is sampled at an.." line.long 0x10 "CCR4,Common Control Register 4" bitfld.long 0x10 31. "AET,Adjustment Edge for Transmit Timing" "0: When CCR1.TINV is 0 adjust the rising edge..,1: When CCR1.TINV is 0 adjust the falling edge.." bitfld.long 0x10 28.--30. "ATT,Adjustment Value for Transmit Timing" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "AJD,Adjustment Direction for Receive Sampling Timing" "0: The sampling timing is adjusted backward to the..,1: The sampling timing is adjusted forward to the.." bitfld.long 0x10 24.--26. "AST,Adjustment Value for Receive Sampling Timing" "0: Setting prohibited,1: 2-TCLK delay,?,?,?,?,?,?" newline bitfld.long 0x10 19. "SCKSEL,Master receive clock selection" "0: Master receive clock is disabled,1: Master receive clock is enabled" bitfld.long 0x10 17. "ATEN,Adjust Transmit Timing Enable" "0: Adjust transmit timing disabled,1: Adjust transmit timing enabled" newline bitfld.long 0x10 16. "ASEN,Adjust Receive Sampling Timing Enable" "0: Adjust sampling timing disabled,1: Adjust sampling timing enabled" hexmask.long.word 0x10 0.--8. 1. "CMPD,Compare Match Data" rgroup.byte 0x1C++0x0 line.byte 0x0 "CESR,Communication Enable Status Register" bitfld.byte 0x0 4. "TIST,TE Internal Status" "0: TE signal internal state value 0,1: TE signal internal state value 1" bitfld.byte 0x0 0. "RIST,RE Internal Status" "0: RE signal internal state value 0,1: RE signal internal state value 1" group.long 0x20++0x7 line.long 0x0 "ICR,Simple IIC Control Register" bitfld.long 0x0 22.--23. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition,?,?" bitfld.long 0x0 20.--21. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition,?,?" newline bitfld.long 0x0 18. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated" bitfld.long 0x0 17. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated,1: A restart condition is generated" newline bitfld.long 0x0 16. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated,1: A start condition is generated" bitfld.long 0x0 13. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.long 0x0 9. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" bitfld.long 0x0 8. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts" newline hexmask.long.byte 0x0 0.--4. 1. "IICDL,SDA Delay Output Select" line.long 0x4 "FCR,FIFO Control Register" hexmask.long.byte 0x4 24.--28. 1. "RSTRG,RTS Output Active Trigger Number Select" bitfld.long 0x4 23. "RFRST,Receive FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Receive-FIFO(RDR.." newline hexmask.long.byte 0x4 16.--20. 1. "RTRG,Receive FIFO Data Trigger Number" bitfld.long 0x4 15. "TFRST,Transmit FIFO Data Register Reset" "0: When set this bit is invalid and does not affect..,1: The number of data stored in Transmit-FIFO (TDR.." newline hexmask.long.byte 0x4 8.--12. 1. "TTRG,Transmit FIFO Data Trigger Number" bitfld.long 0x4 0. "DRES,Receive Data Ready Error Select Bit" "0: Reception data full interrupt (SCIn_RXI),1: Receive error interrupt (SCIn_ERI)" group.long 0x2C++0x13 line.long 0x0 "MCR,Manchester Control Register" bitfld.long 0x0 26. "SBEREN,Start Bit Error Enable" "0: Does not handle a start bit error as an..,1: Handles a start bit error as an interrupt source" bitfld.long 0x0 25. "SYEREN,Receive SYNC Error Enable" "0: Does not handle a receive SYNC error as an..,1: Handles a receive SYNC error as an interrupt.." newline bitfld.long 0x0 24. "PFEREN,Preface Error Enable" "0: Does not handle a preface error as an interrupt..,1: Handles a preface error as an interrupt source" bitfld.long 0x0 20.--21. "RPPAT,Receive Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 16.--19. 1. "RPLEN,Receive Preface Length" bitfld.long 0x0 12.--13. "TPPAT,Transmit Preface Pattern" "0: ALL ZERO,1: ZERO ONE,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "TPLEN,Transmit Preface Length" bitfld.long 0x0 6. "SBSEL,Start Bit Select" "0: The start bit area consists of one bit,1: The start bit area consists of three bits.." newline bitfld.long 0x0 5. "SYNSEL,SYNC Select" "0: The start bit pattern is set with the SYNVAL bit,1: The start bit pattern is set with the TSYNC bit" bitfld.long 0x0 4. "SYNVAL,SYNC value Setting" "0,1" newline bitfld.long 0x0 2. "ERTEN,Manchester Edge Retiming Enable" "0: Disables the receive retiming function,1: Enables the receive retiming function" bitfld.long 0x0 1. "TMPOL,Polarity of Transmit Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." newline bitfld.long 0x0 0. "RMPOL,Polarity of Received Manchester Code" "0: Logic 0 is coded as a zero-to-one transition in..,1: Logic 0 is coded as a one-to-zero transition in.." line.long 0x4 "DCR,Driver Control Register" hexmask.long.byte 0x4 16.--20. 1. "DENGT,Driver Negate Time" hexmask.long.byte 0x4 8.--12. 1. "DEAST,Driver Assertion Time" newline bitfld.long 0x4 0. "DEPOL,Driver Effective Polarity Select" "0: The DEn signal is active-high,1: The DEn signal is active-low" line.long 0x8 "XCR0,Simple LIN Control Register 0" bitfld.long 0x8 24.--25. "BCCS,Bus Conflict Detection Clock Selection" "0: Base clock,1: Base clock/2,?,?" bitfld.long 0x8 22. "AEDIE,Active Edge Detection Interrupt Enable" "0: Active edge detection interrupt disabled,1: Active edge detection interrupt enabled" newline bitfld.long 0x8 21. "COFIE,Counter Overflow Interrupt Enable" "0: Counter overflow is not included in SCIn_ERI..,1: Counter overflow is included in SCIn_ERI.." bitfld.long 0x8 20. "BFDIE,Break Field Detection Interrupt Enable" "0: Break Field detection interrupt disabled,1: Break Field detection interrupt enabled" newline bitfld.long 0x8 17. "BCDIE,Bus Conflict Detection Interrupt Enable" "0: Bus conflict detection is not included in..,1: Bus conflict detection is included in SCIn_ERI.." bitfld.long 0x8 16. "BFOIE,Break Field Output Completion Interrupt Enable" "0: Break Field output completion is not included in..,1: Break Field output completion is included in.." newline bitfld.long 0x8 13.--15. "PIBS,Priority Interrupt Bit Select" "0: Bit 0 of Control Field 1,1: Bit 1 of Control Field 1,?,?,?,?,?,?" bitfld.long 0x8 12. "PIBE,Priority Interrupt Bit Enable" "0: Priority interrupt bit disabled,1: Priority interrupt bit enabled" newline bitfld.long 0x8 10.--11. "CF1DS,Control Field1 Compare Data Select" "0: Select XCR1.PCF1D[7:0] as the compare data,1: Select XCR1.SCF1D[7:0] as the compare data,?,?" bitfld.long 0x8 9. "CF0RE,Control Field 0 Enable" "0: No Control Field 0,1: With Control Field 0" newline bitfld.long 0x8 8. "BFE,Break Field Enable" "0: No Break Field,1: With Break Field" bitfld.long 0x8 0.--1. "TCSS,Timer Count Clock Source Selection" "?,1: TCLK/4,?,?" line.long 0xC "XCR1,Simple LIN Control Register 1" hexmask.long.byte 0xC 24.--31. 1. "CF1CE,Control Field 1 Compare Bit Enable" hexmask.long.byte 0xC 16.--23. 1. "SCF1D,Secondary Compare Data for Control Field 1" newline hexmask.long.byte 0xC 8.--15. 1. "PCF1D,Priority Compare Data for Control Field 1" bitfld.long 0xC 5. "BMEN,Bit Rate Measurement Enable" "0: Bit rate measurement disabled,1: Bit rate measurement enabled" newline bitfld.long 0xC 4. "SDST,Start Frame Detection Enable" "0: Start Frame/Break Field detection disabled,1: Start Frame/Break Field detection enabled" bitfld.long 0xC 0. "TCST,Break Field Output Timer Count Start Trigger" "0: Break Field output timer count stopped,1: Break Field output timer count start" line.long 0x10 "XCR2,Simple LIN Control Register 2" hexmask.long.word 0x10 16.--31. 1. "BFLW,Break Field Length Setting" hexmask.long.byte 0x10 8.--15. 1. "CF0CE,Control Field 0 Compare Bit Enable" newline hexmask.long.byte 0x10 0.--7. 1. "CF0D,Control Field 0 Compare Data" rgroup.long 0x48++0x1B line.long 0x0 "CSR,Common Status Register" bitfld.long 0x0 31. "RDRF,Receive Data Full Flag" "0: Non-FIFO selected (CCR3.FM = 0): No received..,1: Non-FIFO selected (CCR3.FM = 0): Received data.." bitfld.long 0x0 30. "TEND,Transmit End Flag" "0: A character is being transmitted or standing by..,1: Character transfer has been completed or sending.." newline bitfld.long 0x0 29. "TDRE,Transmit Data Empty Flag" "0: Non-FIFO selected (CCR3.FM = 0): Transmit data..,1: Non-FIFO selected (CCR3.FM = 0): No transmit.." bitfld.long 0x0 28. "FER,Framing Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No framing..,1: Non-FIFO selected (CCR3.FM = 0): A framing error.." newline bitfld.long 0x0 27. "PER,Parity Error Flag" "0: Non-FIFO selected (CCR3.FM = 0): No parity error..,1: Non-FIFO selected (CCR3.FM = 0): A parity error.." bitfld.long 0x0 26. "MFF,Mode Fault Error Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.long 0x0 24. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.long 0x0 18. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred at address match..,1: A framing error has occurred at address match.." newline bitfld.long 0x0 17. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred at address match..,1: A parity error has occurred at address match.." bitfld.long 0x0 16. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" newline bitfld.long 0x0 15. "RXDMON,Serial Input Data Monitor Bit" "0: When RINV is 0 RXDn pin is the low level. When..,1: When RINV is 0 RXDn pin is the high level. When.." bitfld.long 0x0 4. "ERS,Error Signal Status Flag" "0: Error signal low not responded,1: Error signal low responded" line.long 0x4 "ISR,Simple IIC Status Register" bitfld.long 0x4 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.long 0x4 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" line.long 0x8 "FRSR,FIFO Receive Status Register" hexmask.long.byte 0x8 24.--29. 1. "FNUM,Framing Error Count" hexmask.long.byte 0x8 16.--21. 1. "PNUM,Parity Error Count" newline hexmask.long.byte 0x8 8.--13. 1. "R,Receive-FIFO Data Count" bitfld.long 0x8 0. "DR,Receive Data Ready Flag" "0: Receiving is in progress or no received data..,1: The following receive data is not received for a.." line.long 0xC "FTSR,FIFO Transmit Status Register" hexmask.long.byte 0xC 0.--5. 1. "T,Transmit-FIFO Data Count" line.long 0x10 "MSR,Manchester Status Register" bitfld.long 0x10 6. "RSYNC,Receive SYNC Data Bit" "0: The received start bit is DATA SYNC,1: The received start bit is COMMAND SYNC" bitfld.long 0x10 4. "MER,Manchester Error Flag" "0: No Manchester error occurred,1: Manchester error has occurred" newline bitfld.long 0x10 2. "SBER,Start Bit Error Flag" "0: No start bit error detected,1: Start bit error detected" bitfld.long 0x10 1. "SYER,SYNC Error Flag" "0: No receive SYNC error detected,1: Receive SYNC error detected" newline bitfld.long 0x10 0. "PFER,Preface Error Flag" "0: No preface error detected,1: Preface error detected" line.long 0x14 "XSR0,Simple LIN Status Register 0" hexmask.long.byte 0x14 24.--31. 1. "CF1RD,Control Field 1 received data" hexmask.long.byte 0x14 16.--23. 1. "CF0RD,Control Field 0 received data" newline bitfld.long 0x14 15. "AEDF,Active Edge Detection Flag" "0: No valid edge detected,1: Detected a valid edge" bitfld.long 0x14 14. "COF,Counter Overflow Flag" "0: Break Field detection counter has not overflowed,1: Break Field detection counter overflowed" newline bitfld.long 0x14 13. "PIBDF,Priority Interrupt Bit Detection Flag" "0: Priority interrupt bit is not detected,1: Priority interrupt bit is detected" bitfld.long 0x14 12. "CF1MF,Control Field 1 Compare Match Flag" "0: Control Field 1 received data does not match the..,1: Control Field 1 received data matches the.." newline bitfld.long 0x14 11. "CF0MF,Control Field 0 Compare Match Flag" "0: Control Field 0 received data does not match the..,1: Control Field 0 received data matches the.." bitfld.long 0x14 10. "BFDF,Break Field Detection Flag" "0: Break Field is not detected,1: Break Field is detected" newline bitfld.long 0x14 9. "BCDF,Bus Conflict Detection Flag" "0: No bus collision detected,1: Detected a bus collision" bitfld.long 0x14 8. "BFOF,Break Field Output Completion Flag" "0: Break Field is being output or is not being output,1: Completed BF output" newline bitfld.long 0x14 1. "RXDSF,RXDn Input Status Flag" "0: RXDn input to SCI is enabled,1: RXDn input to SCI is disabled" bitfld.long 0x14 0. "SFSF,Start Frame Status Flag" "0: Start Frame detection disabled or Start Frame..,1: Before Start Frame detection or during detection" line.long 0x18 "XSR1,Simple LIN Status Register 1" hexmask.long.word 0x18 0.--15. 1. "TCNT,Timer Count Capture Value" wgroup.long 0x68++0x13 line.long 0x0 "CFCLR,Common Flag Clear Register" bitfld.long 0x0 31. "RDRFC,RDRF Clear Bit" "0,1" bitfld.long 0x0 29. "TDREC,TDRE Clear Bit" "0,1" newline bitfld.long 0x0 28. "FERC,FER Clear Bit" "0,1" bitfld.long 0x0 27. "PERC,PER Clear Bit" "0,1" newline bitfld.long 0x0 26. "MFFC,MFF Clear Bit" "0,1" bitfld.long 0x0 24. "ORERC,ORER Clear Bit" "0,1" newline bitfld.long 0x0 18. "DFERC,DFER Clear Bit" "0,1" bitfld.long 0x0 17. "DPERC,DPER Clear Bit" "0,1" newline bitfld.long 0x0 16. "DCMFC,DCMF Clear Bit" "0,1" bitfld.long 0x0 4. "ERSC,ERS Clear Bit" "0,1" line.long 0x4 "ICFCLR,Simple IIC Flag Clear Register" bitfld.long 0x4 3. "IICSTIFC,IICSTIF Clear Bit" "0,1" line.long 0x8 "FFCLR,FIFO Flag Clear Register" bitfld.long 0x8 0. "DRC,DR Clear Bit" "0,1" line.long 0xC "MFCLR,Manchester Flag Clear Register" bitfld.long 0xC 4. "MERC,MER Clear Bit" "0,1" bitfld.long 0xC 2. "SBERC,SBER Clear Bit" "0,1" newline bitfld.long 0xC 1. "SYERC,SYER Clear Bit" "0,1" bitfld.long 0xC 0. "PFERC,PFER Clear Bit" "0,1" line.long 0x10 "XFCLR,Simple LIN Flag Clear Register" bitfld.long 0x10 15. "AEDC,AEDF Clear Bit" "0,1" bitfld.long 0x10 14. "COFC,COFF Clear Bit" "0,1" newline bitfld.long 0x10 13. "PIBDC,PIBDF Clear Bit" "0,1" bitfld.long 0x10 12. "CF1MC,CF1MF Clear Bit" "0,1" newline bitfld.long 0x10 11. "CF0MC,CF0MF Clear Bit" "0,1" bitfld.long 0x10 10. "BFDC,BFDF Clear Bit" "0,1" newline bitfld.long 0x10 9. "BCDC,BCDF Clear Bit" "0,1" bitfld.long 0x10 8. "BFOC,BFOF Clear Bit" "0,1" tree.end tree.end tree "SPI (Serial Peripheral Interface)" base ad:0x0 tree "SPI0_B" base ad:0x4035C000 group.long 0x0++0x13 line.long 0x0 "SPDR,SPI Data Register" hexmask.long 0x0 0.--31. 1. "SPD,These bits are the interface with the buffers that hold data for transmission and reception by the SPI." line.long 0x4 "SPDECR,SPI Delay Control Register" bitfld.long 0x4 16.--18. "SPNDL,SPI Next-Access Delay" "0: 1RSPCK + 5TCLK,1: 2RSPCK + 5TCLK,?,?,?,?,?,?" bitfld.long 0x4 8.--10. "SLNDL,SSL Negation Delay" "0: 1RSPCK,1: 2RSPCK,?,?,?,?,?,?" newline bitfld.long 0x4 0.--2. "SCKDL,RSPCK Delay" "0: 1RSPCK,1: 2RSPCK,?,?,?,?,?,?" line.long 0x8 "SPCR,SPI Control Register" bitfld.long 0x8 31. "BPEN,Synchronization Circuit Bypass Enable" "0: Non-Bypass,1: Bypass" bitfld.long 0x8 30. "MSTR,SPI Master/Slave Mode Select" "0: Slave mode,1: Master mode" newline bitfld.long 0x8 28.--29. "TXMD,Communication Mode Select" "0: Receive only,1: Transmit only,?,?" bitfld.long 0x8 25. "SPFRF,SPI Frame Format Select" "0: Motorola-SPI,1: TI-SSP" newline bitfld.long 0x8 24. "SPMS,SPI Mode Select" "0: SPI operation (4-wire),1: Clock synchronous operation (3-wire)" bitfld.long 0x8 21. "CENDIE,SPI Communication End Interrupt Enable" "0: Communication end interrupt request is disabled.,1: Communication end interrupt request is enabled." newline bitfld.long 0x8 20. "SPTIE,SPI Transmit Buffer Empty Interrupt Enable" "0: SPI transmit buffer empty interrupt request is..,1: SPI transmit buffer empty interrupt request is.." bitfld.long 0x8 19. "SPDRES,SPI receive data ready error select" "0: Receive data full interrupt,1: Error interrupt" newline bitfld.long 0x8 18. "SPIIE,SPI Idle Interrupt Enable" "0: Idle interrupt request is disabled.,1: Idle interrupt request is enabled." bitfld.long 0x8 17. "SPRIE,SPI Receive Buffer Full Interrupt Enable" "0: SPI receive buffer full interrupt request is..,1: SPI receive buffer full interrupt request is.." newline bitfld.long 0x8 16. "SPEIE,SPI Error Interrupt Enable" "0: SPI error interrupt request is disabled.,1: SPI error interrupt request is enabled." bitfld.long 0x8 14. "MODFEN,Mode Fault Error Detection Enable" "0: Mode fault error detection is disabled.,1: Mode fault error detection is enabled." newline bitfld.long 0x8 13. "BFDS,Between Burst Transfer Frames Delay Select" "0: Delay (RSPCK delay SSL negation delay and..,1: Delay between frames is not inserted in burst.." bitfld.long 0x8 12. "SCKASE,RSPCK Auto-Stop Function Enable" "0: RSPCK auto-stop function is disabled.,1: RSPCK auto-stop function is enabled." newline bitfld.long 0x8 11. "PTE,Parity Self-Diagnosis Enable" "0: Parity circuit self-diagnosis function is..,1: Parity circuit self-diagnosis function is enabled." bitfld.long 0x8 9. "SPOE,Parity Mode" "0: Even parity is used for transmission and..,1: Odd parity is used for transmission and reception." newline bitfld.long 0x8 8. "SPPE,Parity Enable" "0: A parity bit is not added to transmit data.,1: A parity bit is added to transmit data." bitfld.long 0x8 0. "SPE,SPI Function Enable" "0: SPI function is disabled.,1: SPI function is enabled." line.long 0xC "SPCR2,SPI Control Register 2" bitfld.long 0xC 21. "MOIFE,MOSI Idle Fixed Value Enable" "0: The MOSI output value is the last data of..,1: The MOSI output value is the set MOIFV bit value." bitfld.long 0xC 20. "MOIFV,MOSI Idle Fixed Value" "0: The fixed value of MOSI idle = 0.,1: The fixed value of MOSI idle = 1." newline bitfld.long 0xC 17. "SPLP2,SPI Loopback 2" "0: Normal mode,1: Loopback mode (transmit data = receive data)" bitfld.long 0xC 16. "SPLP,SPI Loopback" "0: Normal mode,1: Loopback mode (inverted transmit data = receive.." newline hexmask.long.byte 0xC 8.--15. 1. "SPDRC,SPI received data ready detect adjustment" bitfld.long 0xC 7. "RMSTTG,Start Trigger in Master Receive only" "?,1: Receive Start (Writable only when Master Receive.." newline bitfld.long 0xC 6. "RMEDTG,End Trigger in Master Receive only" "?,1: Receive End (Writable only when Master Receive.." hexmask.long.byte 0xC 0.--4. 1. "RMFM,Frame processing count setting in Master Receive only" line.long 0x10 "SPCR3,SPI Control Register 3" bitfld.long 0x10 24.--26. "SPSLN,SPI Sequence Length" "0: Sequence Length is 1 (Referenced SPCMDn n =..,1: Sequence Length is 2 (Referenced SPCMDn n =..,?,?,?,?,?,?" hexmask.long.byte 0x10 8.--15. 1. "SPBR,SPI Bit Rate" newline bitfld.long 0x10 3. "SSL3P,SSL3 Signal Polarity" "0: The SSL3 signal is active low.,1: The SSL3 signal is active high." bitfld.long 0x10 2. "SSL2P,SSL2 Signal Polarity" "0: The SSL2 signal is active low.,1: The SSL2 signal is active high." newline bitfld.long 0x10 1. "SSL1P,SSL1 Signal Polarity" "0: The SSL1 signal is active low.,1: The SSL1 signal is active high." bitfld.long 0x10 0. "SSL0P,SSL0 Signal Polarity" "0: The SSL0 signal is active low.,1: The SSL0 signal is active high." repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x14)++0x3 line.long 0x0 "SPCMD$1,SPI Command Register" bitfld.long 0x0 24.--26. "SSLA,SSL Signal Assertion" "0: Setting prohibited,1: SSL1,?,?,?,?,?,?" hexmask.long.byte 0x0 16.--20. 1. "SPB,SPI Data Length" newline bitfld.long 0x0 15. "SCKDEN,RSPCK Delay Setting Enable" "0: RSPCK delay is 1 RSPCK.,1: RSPCK delay is the set value of the RSPCK delay.." bitfld.long 0x0 14. "SLNDEN,SSL Negation Delay Setting Enable" "0: [Master] SSL negation delay is 1RSPCK. [Slave in..,1: SSL negation delay is the set value of the slave.." newline bitfld.long 0x0 13. "SPNDEN,SPI Next-Access Delay Enable" "0: Next-access delay is 1RSPCK + 5TCLK,1: Next-access delay is the set value of the SPI.." bitfld.long 0x0 12. "LSBF,SPI LSB First" "0: MSB first,1: LSB first" newline bitfld.long 0x0 7. "SSLKP,SSL Signal Level Hold" "0: All SSL signals are negated at the end of..,1: SSL signal level is held after the transfer ends.." bitfld.long 0x0 2.--3. "BRDV,Bit Rate Division" "0: Base bit rate,1: Base bit rate divided by 2,?,?" newline bitfld.long 0x0 1. "CPOL,RSPCK Polarity" "0: RSPCK in idle state is 0.,1: RSPCK in idle state is 1." bitfld.long 0x0 0. "CPHA,RSPCK Phase" "0: Data is sampled at an odd edge and changes at an..,1: Data changes at an odd edge and is sampled at an.." repeat.end group.long 0x40++0x7 line.long 0x0 "SPDCR,SPI Data Control Register" bitfld.long 0x0 8.--9. "SPFC,Frame Count" "0: 1 frame,1: 2 frames,?,?" bitfld.long 0x0 4. "SINV,Serial data invert bit" "0: Not invert serial data,1: Invert serial data." newline bitfld.long 0x0 3. "SPRDTD,SPI Receive Data or Transmit Data Select" "0: The SPDR reads the receive buffer.,1: The SPDR reads the transmit buffer" bitfld.long 0x0 0. "BYSW,Byte Swap Operating Mode Select" "0: Byte Swap OFF,1: Byte Swap ON" line.long 0x4 "SPDCR2,SPI Data Control Register 2" bitfld.long 0x4 8.--9. "TTRG,Transmission FIFO threshold setting" "0: threshold 0,1: threshold 1,?,?" bitfld.long 0x4 0.--1. "RTRG,Receive FIFO threshold setting" "0: threshold 0,1: threshold 1,?,?" rgroup.long 0x50++0x3 line.long 0x0 "SPSR,SPI Status Register" bitfld.long 0x0 31. "SPRF,SPI Receive Buffer Full Flag" "0: The number of data stored in the receive FIFO..,1: The number of data stored in the receive FIFO >.." bitfld.long 0x0 30. "CENDF,Communication End Flag" "0: The SPI is not communicating or communicating.,1: The SPI communication completed." newline bitfld.long 0x0 29. "SPTEF,SPI Transmit Buffer Empty Flag" "0: The number of empty stages in the transmit FIFO..,1: The number of empty stages in the transmit FIFO.." bitfld.long 0x0 28. "UDRF,Underrun Error Flag" "0: When MODF=0 neither mode fault error nor..,1: When MODF=0 neither mode fault error nor.." newline bitfld.long 0x0 27. "PERF,Parity Error Flag" "0: No parity error is present.,1: A parity error is present." bitfld.long 0x0 26. "MODF,Mode Fault Error Flag" "0: Neither mode fault error nor underrun error is..,1: A mode fault error or underrun error is present." newline bitfld.long 0x0 25. "IDLNF,SPI Idle Flag" "0: The SPI is in the idle state.,1: The SPI is in the transfer state." bitfld.long 0x0 24. "OVRF,Overrun Error Flag" "0: No overrun error is present.,1: An overrun error is present." newline bitfld.long 0x0 23. "SPDRF,SPI Receive Data Ready Flag" "0: Receive data ready not detected,1: Receive data ready detected" bitfld.long 0x0 12.--14. "SPECM,SPI Error Command" "0: SPCMD0,1: SPCMD1,?,?,?,?,?,?" newline bitfld.long 0x0 8.--10. "SPCP,SPI Command Pointer" "0: SPCMD0,1: SPCMD1,?,?,?,?,?,?" rgroup.long 0x58++0xB line.long 0x0 "SPTFSR,SPI Transfer FIFO Status Register" bitfld.long 0x0 0.--2. "TFDN,Transmit FIFO data empty stage number" "0,1,2,3,4,5,6,7" line.long 0x4 "SPRFSR,SPI Receive FIFO Status Register" bitfld.long 0x4 0.--2. "RFDN,Receive FIFO data store stage number" "0,1,2,3,4,5,6,7" line.long 0x8 "SPPSR,SPI Polling Register" bitfld.long 0x8 0. "SPEPS,SPI Polling Status" "0: SPCR.SPE is 0,1: SPCR.SPE is 1" wgroup.long 0x68++0x7 line.long 0x0 "SPSRC,SPI Status Clear Register" bitfld.long 0x0 31. "SPRFC,SPI Receive Buffer Full Flag Clear" "0,1" bitfld.long 0x0 30. "CENDFC,Communication End Flag Clear" "0,1" newline bitfld.long 0x0 29. "SPTEFC,SPI Transmit Buffer Empty Flag Clear" "0,1" bitfld.long 0x0 28. "UDRFC,Underrun Error Flag Clear" "0,1" newline bitfld.long 0x0 27. "PERFC,Parity Error Flag Clear" "0,1" bitfld.long 0x0 26. "MODFC,Mode Fault Error Flag Clear" "0,1" newline bitfld.long 0x0 24. "OVRFC,Overrun Error Flag Clear" "0,1" bitfld.long 0x0 23. "SPDRFC,SPI Receive Data Ready Flag Clear" "0,1" line.long 0x4 "SPFCR,SPI FIFO Clear Register" bitfld.long 0x4 0. "SPFRST,SPI FIFO clear" "0,1" tree.end tree "SPI0_B_NS" base ad:0x5035C000 group.long 0x0++0x13 line.long 0x0 "SPDR,SPI Data Register" hexmask.long 0x0 0.--31. 1. "SPD,These bits are the interface with the buffers that hold data for transmission and reception by the SPI." line.long 0x4 "SPDECR,SPI Delay Control Register" bitfld.long 0x4 16.--18. "SPNDL,SPI Next-Access Delay" "0: 1RSPCK + 5TCLK,1: 2RSPCK + 5TCLK,?,?,?,?,?,?" bitfld.long 0x4 8.--10. "SLNDL,SSL Negation Delay" "0: 1RSPCK,1: 2RSPCK,?,?,?,?,?,?" newline bitfld.long 0x4 0.--2. "SCKDL,RSPCK Delay" "0: 1RSPCK,1: 2RSPCK,?,?,?,?,?,?" line.long 0x8 "SPCR,SPI Control Register" bitfld.long 0x8 31. "BPEN,Synchronization Circuit Bypass Enable" "0: Non-Bypass,1: Bypass" bitfld.long 0x8 30. "MSTR,SPI Master/Slave Mode Select" "0: Slave mode,1: Master mode" newline bitfld.long 0x8 28.--29. "TXMD,Communication Mode Select" "0: Receive only,1: Transmit only,?,?" bitfld.long 0x8 25. "SPFRF,SPI Frame Format Select" "0: Motorola-SPI,1: TI-SSP" newline bitfld.long 0x8 24. "SPMS,SPI Mode Select" "0: SPI operation (4-wire),1: Clock synchronous operation (3-wire)" bitfld.long 0x8 21. "CENDIE,SPI Communication End Interrupt Enable" "0: Communication end interrupt request is disabled.,1: Communication end interrupt request is enabled." newline bitfld.long 0x8 20. "SPTIE,SPI Transmit Buffer Empty Interrupt Enable" "0: SPI transmit buffer empty interrupt request is..,1: SPI transmit buffer empty interrupt request is.." bitfld.long 0x8 19. "SPDRES,SPI receive data ready error select" "0: Receive data full interrupt,1: Error interrupt" newline bitfld.long 0x8 18. "SPIIE,SPI Idle Interrupt Enable" "0: Idle interrupt request is disabled.,1: Idle interrupt request is enabled." bitfld.long 0x8 17. "SPRIE,SPI Receive Buffer Full Interrupt Enable" "0: SPI receive buffer full interrupt request is..,1: SPI receive buffer full interrupt request is.." newline bitfld.long 0x8 16. "SPEIE,SPI Error Interrupt Enable" "0: SPI error interrupt request is disabled.,1: SPI error interrupt request is enabled." bitfld.long 0x8 14. "MODFEN,Mode Fault Error Detection Enable" "0: Mode fault error detection is disabled.,1: Mode fault error detection is enabled." newline bitfld.long 0x8 13. "BFDS,Between Burst Transfer Frames Delay Select" "0: Delay (RSPCK delay SSL negation delay and..,1: Delay between frames is not inserted in burst.." bitfld.long 0x8 12. "SCKASE,RSPCK Auto-Stop Function Enable" "0: RSPCK auto-stop function is disabled.,1: RSPCK auto-stop function is enabled." newline bitfld.long 0x8 11. "PTE,Parity Self-Diagnosis Enable" "0: Parity circuit self-diagnosis function is..,1: Parity circuit self-diagnosis function is enabled." bitfld.long 0x8 9. "SPOE,Parity Mode" "0: Even parity is used for transmission and..,1: Odd parity is used for transmission and reception." newline bitfld.long 0x8 8. "SPPE,Parity Enable" "0: A parity bit is not added to transmit data.,1: A parity bit is added to transmit data." bitfld.long 0x8 0. "SPE,SPI Function Enable" "0: SPI function is disabled.,1: SPI function is enabled." line.long 0xC "SPCR2,SPI Control Register 2" bitfld.long 0xC 21. "MOIFE,MOSI Idle Fixed Value Enable" "0: The MOSI output value is the last data of..,1: The MOSI output value is the set MOIFV bit value." bitfld.long 0xC 20. "MOIFV,MOSI Idle Fixed Value" "0: The fixed value of MOSI idle = 0.,1: The fixed value of MOSI idle = 1." newline bitfld.long 0xC 17. "SPLP2,SPI Loopback 2" "0: Normal mode,1: Loopback mode (transmit data = receive data)" bitfld.long 0xC 16. "SPLP,SPI Loopback" "0: Normal mode,1: Loopback mode (inverted transmit data = receive.." newline hexmask.long.byte 0xC 8.--15. 1. "SPDRC,SPI received data ready detect adjustment" bitfld.long 0xC 7. "RMSTTG,Start Trigger in Master Receive only" "?,1: Receive Start (Writable only when Master Receive.." newline bitfld.long 0xC 6. "RMEDTG,End Trigger in Master Receive only" "?,1: Receive End (Writable only when Master Receive.." hexmask.long.byte 0xC 0.--4. 1. "RMFM,Frame processing count setting in Master Receive only" line.long 0x10 "SPCR3,SPI Control Register 3" bitfld.long 0x10 24.--26. "SPSLN,SPI Sequence Length" "0: Sequence Length is 1 (Referenced SPCMDn n =..,1: Sequence Length is 2 (Referenced SPCMDn n =..,?,?,?,?,?,?" hexmask.long.byte 0x10 8.--15. 1. "SPBR,SPI Bit Rate" newline bitfld.long 0x10 3. "SSL3P,SSL3 Signal Polarity" "0: The SSL3 signal is active low.,1: The SSL3 signal is active high." bitfld.long 0x10 2. "SSL2P,SSL2 Signal Polarity" "0: The SSL2 signal is active low.,1: The SSL2 signal is active high." newline bitfld.long 0x10 1. "SSL1P,SSL1 Signal Polarity" "0: The SSL1 signal is active low.,1: The SSL1 signal is active high." bitfld.long 0x10 0. "SSL0P,SSL0 Signal Polarity" "0: The SSL0 signal is active low.,1: The SSL0 signal is active high." repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x14)++0x3 line.long 0x0 "SPCMD$1,SPI Command Register" bitfld.long 0x0 24.--26. "SSLA,SSL Signal Assertion" "0: Setting prohibited,1: SSL1,?,?,?,?,?,?" hexmask.long.byte 0x0 16.--20. 1. "SPB,SPI Data Length" newline bitfld.long 0x0 15. "SCKDEN,RSPCK Delay Setting Enable" "0: RSPCK delay is 1 RSPCK.,1: RSPCK delay is the set value of the RSPCK delay.." bitfld.long 0x0 14. "SLNDEN,SSL Negation Delay Setting Enable" "0: [Master] SSL negation delay is 1RSPCK. [Slave in..,1: SSL negation delay is the set value of the slave.." newline bitfld.long 0x0 13. "SPNDEN,SPI Next-Access Delay Enable" "0: Next-access delay is 1RSPCK + 5TCLK,1: Next-access delay is the set value of the SPI.." bitfld.long 0x0 12. "LSBF,SPI LSB First" "0: MSB first,1: LSB first" newline bitfld.long 0x0 7. "SSLKP,SSL Signal Level Hold" "0: All SSL signals are negated at the end of..,1: SSL signal level is held after the transfer ends.." bitfld.long 0x0 2.--3. "BRDV,Bit Rate Division" "0: Base bit rate,1: Base bit rate divided by 2,?,?" newline bitfld.long 0x0 1. "CPOL,RSPCK Polarity" "0: RSPCK in idle state is 0.,1: RSPCK in idle state is 1." bitfld.long 0x0 0. "CPHA,RSPCK Phase" "0: Data is sampled at an odd edge and changes at an..,1: Data changes at an odd edge and is sampled at an.." repeat.end group.long 0x40++0x7 line.long 0x0 "SPDCR,SPI Data Control Register" bitfld.long 0x0 8.--9. "SPFC,Frame Count" "0: 1 frame,1: 2 frames,?,?" bitfld.long 0x0 4. "SINV,Serial data invert bit" "0: Not invert serial data,1: Invert serial data." newline bitfld.long 0x0 3. "SPRDTD,SPI Receive Data or Transmit Data Select" "0: The SPDR reads the receive buffer.,1: The SPDR reads the transmit buffer" bitfld.long 0x0 0. "BYSW,Byte Swap Operating Mode Select" "0: Byte Swap OFF,1: Byte Swap ON" line.long 0x4 "SPDCR2,SPI Data Control Register 2" bitfld.long 0x4 8.--9. "TTRG,Transmission FIFO threshold setting" "0: threshold 0,1: threshold 1,?,?" bitfld.long 0x4 0.--1. "RTRG,Receive FIFO threshold setting" "0: threshold 0,1: threshold 1,?,?" rgroup.long 0x50++0x3 line.long 0x0 "SPSR,SPI Status Register" bitfld.long 0x0 31. "SPRF,SPI Receive Buffer Full Flag" "0: The number of data stored in the receive FIFO..,1: The number of data stored in the receive FIFO >.." bitfld.long 0x0 30. "CENDF,Communication End Flag" "0: The SPI is not communicating or communicating.,1: The SPI communication completed." newline bitfld.long 0x0 29. "SPTEF,SPI Transmit Buffer Empty Flag" "0: The number of empty stages in the transmit FIFO..,1: The number of empty stages in the transmit FIFO.." bitfld.long 0x0 28. "UDRF,Underrun Error Flag" "0: When MODF=0 neither mode fault error nor..,1: When MODF=0 neither mode fault error nor.." newline bitfld.long 0x0 27. "PERF,Parity Error Flag" "0: No parity error is present.,1: A parity error is present." bitfld.long 0x0 26. "MODF,Mode Fault Error Flag" "0: Neither mode fault error nor underrun error is..,1: A mode fault error or underrun error is present." newline bitfld.long 0x0 25. "IDLNF,SPI Idle Flag" "0: The SPI is in the idle state.,1: The SPI is in the transfer state." bitfld.long 0x0 24. "OVRF,Overrun Error Flag" "0: No overrun error is present.,1: An overrun error is present." newline bitfld.long 0x0 23. "SPDRF,SPI Receive Data Ready Flag" "0: Receive data ready not detected,1: Receive data ready detected" bitfld.long 0x0 12.--14. "SPECM,SPI Error Command" "0: SPCMD0,1: SPCMD1,?,?,?,?,?,?" newline bitfld.long 0x0 8.--10. "SPCP,SPI Command Pointer" "0: SPCMD0,1: SPCMD1,?,?,?,?,?,?" rgroup.long 0x58++0xB line.long 0x0 "SPTFSR,SPI Transfer FIFO Status Register" bitfld.long 0x0 0.--2. "TFDN,Transmit FIFO data empty stage number" "0,1,2,3,4,5,6,7" line.long 0x4 "SPRFSR,SPI Receive FIFO Status Register" bitfld.long 0x4 0.--2. "RFDN,Receive FIFO data store stage number" "0,1,2,3,4,5,6,7" line.long 0x8 "SPPSR,SPI Polling Register" bitfld.long 0x8 0. "SPEPS,SPI Polling Status" "0: SPCR.SPE is 0,1: SPCR.SPE is 1" wgroup.long 0x68++0x7 line.long 0x0 "SPSRC,SPI Status Clear Register" bitfld.long 0x0 31. "SPRFC,SPI Receive Buffer Full Flag Clear" "0,1" bitfld.long 0x0 30. "CENDFC,Communication End Flag Clear" "0,1" newline bitfld.long 0x0 29. "SPTEFC,SPI Transmit Buffer Empty Flag Clear" "0,1" bitfld.long 0x0 28. "UDRFC,Underrun Error Flag Clear" "0,1" newline bitfld.long 0x0 27. "PERFC,Parity Error Flag Clear" "0,1" bitfld.long 0x0 26. "MODFC,Mode Fault Error Flag Clear" "0,1" newline bitfld.long 0x0 24. "OVRFC,Overrun Error Flag Clear" "0,1" bitfld.long 0x0 23. "SPDRFC,SPI Receive Data Ready Flag Clear" "0,1" line.long 0x4 "SPFCR,SPI FIFO Clear Register" bitfld.long 0x4 0. "SPFRST,SPI FIFO clear" "0,1" tree.end tree "SPI1_B" base ad:0x4035C100 group.long 0x0++0x13 line.long 0x0 "SPDR,SPI Data Register" hexmask.long 0x0 0.--31. 1. "SPD,These bits are the interface with the buffers that hold data for transmission and reception by the SPI." line.long 0x4 "SPDECR,SPI Delay Control Register" bitfld.long 0x4 16.--18. "SPNDL,SPI Next-Access Delay" "0: 1RSPCK + 5TCLK,1: 2RSPCK + 5TCLK,?,?,?,?,?,?" bitfld.long 0x4 8.--10. "SLNDL,SSL Negation Delay" "0: 1RSPCK,1: 2RSPCK,?,?,?,?,?,?" newline bitfld.long 0x4 0.--2. "SCKDL,RSPCK Delay" "0: 1RSPCK,1: 2RSPCK,?,?,?,?,?,?" line.long 0x8 "SPCR,SPI Control Register" bitfld.long 0x8 31. "BPEN,Synchronization Circuit Bypass Enable" "0: Non-Bypass,1: Bypass" bitfld.long 0x8 30. "MSTR,SPI Master/Slave Mode Select" "0: Slave mode,1: Master mode" newline bitfld.long 0x8 28.--29. "TXMD,Communication Mode Select" "0: Receive only,1: Transmit only,?,?" bitfld.long 0x8 25. "SPFRF,SPI Frame Format Select" "0: Motorola-SPI,1: TI-SSP" newline bitfld.long 0x8 24. "SPMS,SPI Mode Select" "0: SPI operation (4-wire),1: Clock synchronous operation (3-wire)" bitfld.long 0x8 21. "CENDIE,SPI Communication End Interrupt Enable" "0: Communication end interrupt request is disabled.,1: Communication end interrupt request is enabled." newline bitfld.long 0x8 20. "SPTIE,SPI Transmit Buffer Empty Interrupt Enable" "0: SPI transmit buffer empty interrupt request is..,1: SPI transmit buffer empty interrupt request is.." bitfld.long 0x8 19. "SPDRES,SPI receive data ready error select" "0: Receive data full interrupt,1: Error interrupt" newline bitfld.long 0x8 18. "SPIIE,SPI Idle Interrupt Enable" "0: Idle interrupt request is disabled.,1: Idle interrupt request is enabled." bitfld.long 0x8 17. "SPRIE,SPI Receive Buffer Full Interrupt Enable" "0: SPI receive buffer full interrupt request is..,1: SPI receive buffer full interrupt request is.." newline bitfld.long 0x8 16. "SPEIE,SPI Error Interrupt Enable" "0: SPI error interrupt request is disabled.,1: SPI error interrupt request is enabled." bitfld.long 0x8 14. "MODFEN,Mode Fault Error Detection Enable" "0: Mode fault error detection is disabled.,1: Mode fault error detection is enabled." newline bitfld.long 0x8 13. "BFDS,Between Burst Transfer Frames Delay Select" "0: Delay (RSPCK delay SSL negation delay and..,1: Delay between frames is not inserted in burst.." bitfld.long 0x8 12. "SCKASE,RSPCK Auto-Stop Function Enable" "0: RSPCK auto-stop function is disabled.,1: RSPCK auto-stop function is enabled." newline bitfld.long 0x8 11. "PTE,Parity Self-Diagnosis Enable" "0: Parity circuit self-diagnosis function is..,1: Parity circuit self-diagnosis function is enabled." bitfld.long 0x8 9. "SPOE,Parity Mode" "0: Even parity is used for transmission and..,1: Odd parity is used for transmission and reception." newline bitfld.long 0x8 8. "SPPE,Parity Enable" "0: A parity bit is not added to transmit data.,1: A parity bit is added to transmit data." bitfld.long 0x8 0. "SPE,SPI Function Enable" "0: SPI function is disabled.,1: SPI function is enabled." line.long 0xC "SPCR2,SPI Control Register 2" bitfld.long 0xC 21. "MOIFE,MOSI Idle Fixed Value Enable" "0: The MOSI output value is the last data of..,1: The MOSI output value is the set MOIFV bit value." bitfld.long 0xC 20. "MOIFV,MOSI Idle Fixed Value" "0: The fixed value of MOSI idle = 0.,1: The fixed value of MOSI idle = 1." newline bitfld.long 0xC 17. "SPLP2,SPI Loopback 2" "0: Normal mode,1: Loopback mode (transmit data = receive data)" bitfld.long 0xC 16. "SPLP,SPI Loopback" "0: Normal mode,1: Loopback mode (inverted transmit data = receive.." newline hexmask.long.byte 0xC 8.--15. 1. "SPDRC,SPI received data ready detect adjustment" bitfld.long 0xC 7. "RMSTTG,Start Trigger in Master Receive only" "?,1: Receive Start (Writable only when Master Receive.." newline bitfld.long 0xC 6. "RMEDTG,End Trigger in Master Receive only" "?,1: Receive End (Writable only when Master Receive.." hexmask.long.byte 0xC 0.--4. 1. "RMFM,Frame processing count setting in Master Receive only" line.long 0x10 "SPCR3,SPI Control Register 3" bitfld.long 0x10 24.--26. "SPSLN,SPI Sequence Length" "0: Sequence Length is 1 (Referenced SPCMDn n =..,1: Sequence Length is 2 (Referenced SPCMDn n =..,?,?,?,?,?,?" hexmask.long.byte 0x10 8.--15. 1. "SPBR,SPI Bit Rate" newline bitfld.long 0x10 3. "SSL3P,SSL3 Signal Polarity" "0: The SSL3 signal is active low.,1: The SSL3 signal is active high." bitfld.long 0x10 2. "SSL2P,SSL2 Signal Polarity" "0: The SSL2 signal is active low.,1: The SSL2 signal is active high." newline bitfld.long 0x10 1. "SSL1P,SSL1 Signal Polarity" "0: The SSL1 signal is active low.,1: The SSL1 signal is active high." bitfld.long 0x10 0. "SSL0P,SSL0 Signal Polarity" "0: The SSL0 signal is active low.,1: The SSL0 signal is active high." repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x14)++0x3 line.long 0x0 "SPCMD$1,SPI Command Register" bitfld.long 0x0 24.--26. "SSLA,SSL Signal Assertion" "0: Setting prohibited,1: SSL1,?,?,?,?,?,?" hexmask.long.byte 0x0 16.--20. 1. "SPB,SPI Data Length" newline bitfld.long 0x0 15. "SCKDEN,RSPCK Delay Setting Enable" "0: RSPCK delay is 1 RSPCK.,1: RSPCK delay is the set value of the RSPCK delay.." bitfld.long 0x0 14. "SLNDEN,SSL Negation Delay Setting Enable" "0: [Master] SSL negation delay is 1RSPCK. [Slave in..,1: SSL negation delay is the set value of the slave.." newline bitfld.long 0x0 13. "SPNDEN,SPI Next-Access Delay Enable" "0: Next-access delay is 1RSPCK + 5TCLK,1: Next-access delay is the set value of the SPI.." bitfld.long 0x0 12. "LSBF,SPI LSB First" "0: MSB first,1: LSB first" newline bitfld.long 0x0 7. "SSLKP,SSL Signal Level Hold" "0: All SSL signals are negated at the end of..,1: SSL signal level is held after the transfer ends.." bitfld.long 0x0 2.--3. "BRDV,Bit Rate Division" "0: Base bit rate,1: Base bit rate divided by 2,?,?" newline bitfld.long 0x0 1. "CPOL,RSPCK Polarity" "0: RSPCK in idle state is 0.,1: RSPCK in idle state is 1." bitfld.long 0x0 0. "CPHA,RSPCK Phase" "0: Data is sampled at an odd edge and changes at an..,1: Data changes at an odd edge and is sampled at an.." repeat.end group.long 0x40++0x7 line.long 0x0 "SPDCR,SPI Data Control Register" bitfld.long 0x0 8.--9. "SPFC,Frame Count" "0: 1 frame,1: 2 frames,?,?" bitfld.long 0x0 4. "SINV,Serial data invert bit" "0: Not invert serial data,1: Invert serial data." newline bitfld.long 0x0 3. "SPRDTD,SPI Receive Data or Transmit Data Select" "0: The SPDR reads the receive buffer.,1: The SPDR reads the transmit buffer" bitfld.long 0x0 0. "BYSW,Byte Swap Operating Mode Select" "0: Byte Swap OFF,1: Byte Swap ON" line.long 0x4 "SPDCR2,SPI Data Control Register 2" bitfld.long 0x4 8.--9. "TTRG,Transmission FIFO threshold setting" "0: threshold 0,1: threshold 1,?,?" bitfld.long 0x4 0.--1. "RTRG,Receive FIFO threshold setting" "0: threshold 0,1: threshold 1,?,?" rgroup.long 0x50++0x3 line.long 0x0 "SPSR,SPI Status Register" bitfld.long 0x0 31. "SPRF,SPI Receive Buffer Full Flag" "0: The number of data stored in the receive FIFO..,1: The number of data stored in the receive FIFO >.." bitfld.long 0x0 30. "CENDF,Communication End Flag" "0: The SPI is not communicating or communicating.,1: The SPI communication completed." newline bitfld.long 0x0 29. "SPTEF,SPI Transmit Buffer Empty Flag" "0: The number of empty stages in the transmit FIFO..,1: The number of empty stages in the transmit FIFO.." bitfld.long 0x0 28. "UDRF,Underrun Error Flag" "0: When MODF=0 neither mode fault error nor..,1: When MODF=0 neither mode fault error nor.." newline bitfld.long 0x0 27. "PERF,Parity Error Flag" "0: No parity error is present.,1: A parity error is present." bitfld.long 0x0 26. "MODF,Mode Fault Error Flag" "0: Neither mode fault error nor underrun error is..,1: A mode fault error or underrun error is present." newline bitfld.long 0x0 25. "IDLNF,SPI Idle Flag" "0: The SPI is in the idle state.,1: The SPI is in the transfer state." bitfld.long 0x0 24. "OVRF,Overrun Error Flag" "0: No overrun error is present.,1: An overrun error is present." newline bitfld.long 0x0 23. "SPDRF,SPI Receive Data Ready Flag" "0: Receive data ready not detected,1: Receive data ready detected" bitfld.long 0x0 12.--14. "SPECM,SPI Error Command" "0: SPCMD0,1: SPCMD1,?,?,?,?,?,?" newline bitfld.long 0x0 8.--10. "SPCP,SPI Command Pointer" "0: SPCMD0,1: SPCMD1,?,?,?,?,?,?" rgroup.long 0x58++0xB line.long 0x0 "SPTFSR,SPI Transfer FIFO Status Register" bitfld.long 0x0 0.--2. "TFDN,Transmit FIFO data empty stage number" "0,1,2,3,4,5,6,7" line.long 0x4 "SPRFSR,SPI Receive FIFO Status Register" bitfld.long 0x4 0.--2. "RFDN,Receive FIFO data store stage number" "0,1,2,3,4,5,6,7" line.long 0x8 "SPPSR,SPI Polling Register" bitfld.long 0x8 0. "SPEPS,SPI Polling Status" "0: SPCR.SPE is 0,1: SPCR.SPE is 1" wgroup.long 0x68++0x7 line.long 0x0 "SPSRC,SPI Status Clear Register" bitfld.long 0x0 31. "SPRFC,SPI Receive Buffer Full Flag Clear" "0,1" bitfld.long 0x0 30. "CENDFC,Communication End Flag Clear" "0,1" newline bitfld.long 0x0 29. "SPTEFC,SPI Transmit Buffer Empty Flag Clear" "0,1" bitfld.long 0x0 28. "UDRFC,Underrun Error Flag Clear" "0,1" newline bitfld.long 0x0 27. "PERFC,Parity Error Flag Clear" "0,1" bitfld.long 0x0 26. "MODFC,Mode Fault Error Flag Clear" "0,1" newline bitfld.long 0x0 24. "OVRFC,Overrun Error Flag Clear" "0,1" bitfld.long 0x0 23. "SPDRFC,SPI Receive Data Ready Flag Clear" "0,1" line.long 0x4 "SPFCR,SPI FIFO Clear Register" bitfld.long 0x4 0. "SPFRST,SPI FIFO clear" "0,1" tree.end tree "SPI1_B_NS" base ad:0x5035C100 group.long 0x0++0x13 line.long 0x0 "SPDR,SPI Data Register" hexmask.long 0x0 0.--31. 1. "SPD,These bits are the interface with the buffers that hold data for transmission and reception by the SPI." line.long 0x4 "SPDECR,SPI Delay Control Register" bitfld.long 0x4 16.--18. "SPNDL,SPI Next-Access Delay" "0: 1RSPCK + 5TCLK,1: 2RSPCK + 5TCLK,?,?,?,?,?,?" bitfld.long 0x4 8.--10. "SLNDL,SSL Negation Delay" "0: 1RSPCK,1: 2RSPCK,?,?,?,?,?,?" newline bitfld.long 0x4 0.--2. "SCKDL,RSPCK Delay" "0: 1RSPCK,1: 2RSPCK,?,?,?,?,?,?" line.long 0x8 "SPCR,SPI Control Register" bitfld.long 0x8 31. "BPEN,Synchronization Circuit Bypass Enable" "0: Non-Bypass,1: Bypass" bitfld.long 0x8 30. "MSTR,SPI Master/Slave Mode Select" "0: Slave mode,1: Master mode" newline bitfld.long 0x8 28.--29. "TXMD,Communication Mode Select" "0: Receive only,1: Transmit only,?,?" bitfld.long 0x8 25. "SPFRF,SPI Frame Format Select" "0: Motorola-SPI,1: TI-SSP" newline bitfld.long 0x8 24. "SPMS,SPI Mode Select" "0: SPI operation (4-wire),1: Clock synchronous operation (3-wire)" bitfld.long 0x8 21. "CENDIE,SPI Communication End Interrupt Enable" "0: Communication end interrupt request is disabled.,1: Communication end interrupt request is enabled." newline bitfld.long 0x8 20. "SPTIE,SPI Transmit Buffer Empty Interrupt Enable" "0: SPI transmit buffer empty interrupt request is..,1: SPI transmit buffer empty interrupt request is.." bitfld.long 0x8 19. "SPDRES,SPI receive data ready error select" "0: Receive data full interrupt,1: Error interrupt" newline bitfld.long 0x8 18. "SPIIE,SPI Idle Interrupt Enable" "0: Idle interrupt request is disabled.,1: Idle interrupt request is enabled." bitfld.long 0x8 17. "SPRIE,SPI Receive Buffer Full Interrupt Enable" "0: SPI receive buffer full interrupt request is..,1: SPI receive buffer full interrupt request is.." newline bitfld.long 0x8 16. "SPEIE,SPI Error Interrupt Enable" "0: SPI error interrupt request is disabled.,1: SPI error interrupt request is enabled." bitfld.long 0x8 14. "MODFEN,Mode Fault Error Detection Enable" "0: Mode fault error detection is disabled.,1: Mode fault error detection is enabled." newline bitfld.long 0x8 13. "BFDS,Between Burst Transfer Frames Delay Select" "0: Delay (RSPCK delay SSL negation delay and..,1: Delay between frames is not inserted in burst.." bitfld.long 0x8 12. "SCKASE,RSPCK Auto-Stop Function Enable" "0: RSPCK auto-stop function is disabled.,1: RSPCK auto-stop function is enabled." newline bitfld.long 0x8 11. "PTE,Parity Self-Diagnosis Enable" "0: Parity circuit self-diagnosis function is..,1: Parity circuit self-diagnosis function is enabled." bitfld.long 0x8 9. "SPOE,Parity Mode" "0: Even parity is used for transmission and..,1: Odd parity is used for transmission and reception." newline bitfld.long 0x8 8. "SPPE,Parity Enable" "0: A parity bit is not added to transmit data.,1: A parity bit is added to transmit data." bitfld.long 0x8 0. "SPE,SPI Function Enable" "0: SPI function is disabled.,1: SPI function is enabled." line.long 0xC "SPCR2,SPI Control Register 2" bitfld.long 0xC 21. "MOIFE,MOSI Idle Fixed Value Enable" "0: The MOSI output value is the last data of..,1: The MOSI output value is the set MOIFV bit value." bitfld.long 0xC 20. "MOIFV,MOSI Idle Fixed Value" "0: The fixed value of MOSI idle = 0.,1: The fixed value of MOSI idle = 1." newline bitfld.long 0xC 17. "SPLP2,SPI Loopback 2" "0: Normal mode,1: Loopback mode (transmit data = receive data)" bitfld.long 0xC 16. "SPLP,SPI Loopback" "0: Normal mode,1: Loopback mode (inverted transmit data = receive.." newline hexmask.long.byte 0xC 8.--15. 1. "SPDRC,SPI received data ready detect adjustment" bitfld.long 0xC 7. "RMSTTG,Start Trigger in Master Receive only" "?,1: Receive Start (Writable only when Master Receive.." newline bitfld.long 0xC 6. "RMEDTG,End Trigger in Master Receive only" "?,1: Receive End (Writable only when Master Receive.." hexmask.long.byte 0xC 0.--4. 1. "RMFM,Frame processing count setting in Master Receive only" line.long 0x10 "SPCR3,SPI Control Register 3" bitfld.long 0x10 24.--26. "SPSLN,SPI Sequence Length" "0: Sequence Length is 1 (Referenced SPCMDn n =..,1: Sequence Length is 2 (Referenced SPCMDn n =..,?,?,?,?,?,?" hexmask.long.byte 0x10 8.--15. 1. "SPBR,SPI Bit Rate" newline bitfld.long 0x10 3. "SSL3P,SSL3 Signal Polarity" "0: The SSL3 signal is active low.,1: The SSL3 signal is active high." bitfld.long 0x10 2. "SSL2P,SSL2 Signal Polarity" "0: The SSL2 signal is active low.,1: The SSL2 signal is active high." newline bitfld.long 0x10 1. "SSL1P,SSL1 Signal Polarity" "0: The SSL1 signal is active low.,1: The SSL1 signal is active high." bitfld.long 0x10 0. "SSL0P,SSL0 Signal Polarity" "0: The SSL0 signal is active low.,1: The SSL0 signal is active high." repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x14)++0x3 line.long 0x0 "SPCMD$1,SPI Command Register" bitfld.long 0x0 24.--26. "SSLA,SSL Signal Assertion" "0: Setting prohibited,1: SSL1,?,?,?,?,?,?" hexmask.long.byte 0x0 16.--20. 1. "SPB,SPI Data Length" newline bitfld.long 0x0 15. "SCKDEN,RSPCK Delay Setting Enable" "0: RSPCK delay is 1 RSPCK.,1: RSPCK delay is the set value of the RSPCK delay.." bitfld.long 0x0 14. "SLNDEN,SSL Negation Delay Setting Enable" "0: [Master] SSL negation delay is 1RSPCK. [Slave in..,1: SSL negation delay is the set value of the slave.." newline bitfld.long 0x0 13. "SPNDEN,SPI Next-Access Delay Enable" "0: Next-access delay is 1RSPCK + 5TCLK,1: Next-access delay is the set value of the SPI.." bitfld.long 0x0 12. "LSBF,SPI LSB First" "0: MSB first,1: LSB first" newline bitfld.long 0x0 7. "SSLKP,SSL Signal Level Hold" "0: All SSL signals are negated at the end of..,1: SSL signal level is held after the transfer ends.." bitfld.long 0x0 2.--3. "BRDV,Bit Rate Division" "0: Base bit rate,1: Base bit rate divided by 2,?,?" newline bitfld.long 0x0 1. "CPOL,RSPCK Polarity" "0: RSPCK in idle state is 0.,1: RSPCK in idle state is 1." bitfld.long 0x0 0. "CPHA,RSPCK Phase" "0: Data is sampled at an odd edge and changes at an..,1: Data changes at an odd edge and is sampled at an.." repeat.end group.long 0x40++0x7 line.long 0x0 "SPDCR,SPI Data Control Register" bitfld.long 0x0 8.--9. "SPFC,Frame Count" "0: 1 frame,1: 2 frames,?,?" bitfld.long 0x0 4. "SINV,Serial data invert bit" "0: Not invert serial data,1: Invert serial data." newline bitfld.long 0x0 3. "SPRDTD,SPI Receive Data or Transmit Data Select" "0: The SPDR reads the receive buffer.,1: The SPDR reads the transmit buffer" bitfld.long 0x0 0. "BYSW,Byte Swap Operating Mode Select" "0: Byte Swap OFF,1: Byte Swap ON" line.long 0x4 "SPDCR2,SPI Data Control Register 2" bitfld.long 0x4 8.--9. "TTRG,Transmission FIFO threshold setting" "0: threshold 0,1: threshold 1,?,?" bitfld.long 0x4 0.--1. "RTRG,Receive FIFO threshold setting" "0: threshold 0,1: threshold 1,?,?" rgroup.long 0x50++0x3 line.long 0x0 "SPSR,SPI Status Register" bitfld.long 0x0 31. "SPRF,SPI Receive Buffer Full Flag" "0: The number of data stored in the receive FIFO..,1: The number of data stored in the receive FIFO >.." bitfld.long 0x0 30. "CENDF,Communication End Flag" "0: The SPI is not communicating or communicating.,1: The SPI communication completed." newline bitfld.long 0x0 29. "SPTEF,SPI Transmit Buffer Empty Flag" "0: The number of empty stages in the transmit FIFO..,1: The number of empty stages in the transmit FIFO.." bitfld.long 0x0 28. "UDRF,Underrun Error Flag" "0: When MODF=0 neither mode fault error nor..,1: When MODF=0 neither mode fault error nor.." newline bitfld.long 0x0 27. "PERF,Parity Error Flag" "0: No parity error is present.,1: A parity error is present." bitfld.long 0x0 26. "MODF,Mode Fault Error Flag" "0: Neither mode fault error nor underrun error is..,1: A mode fault error or underrun error is present." newline bitfld.long 0x0 25. "IDLNF,SPI Idle Flag" "0: The SPI is in the idle state.,1: The SPI is in the transfer state." bitfld.long 0x0 24. "OVRF,Overrun Error Flag" "0: No overrun error is present.,1: An overrun error is present." newline bitfld.long 0x0 23. "SPDRF,SPI Receive Data Ready Flag" "0: Receive data ready not detected,1: Receive data ready detected" bitfld.long 0x0 12.--14. "SPECM,SPI Error Command" "0: SPCMD0,1: SPCMD1,?,?,?,?,?,?" newline bitfld.long 0x0 8.--10. "SPCP,SPI Command Pointer" "0: SPCMD0,1: SPCMD1,?,?,?,?,?,?" rgroup.long 0x58++0xB line.long 0x0 "SPTFSR,SPI Transfer FIFO Status Register" bitfld.long 0x0 0.--2. "TFDN,Transmit FIFO data empty stage number" "0,1,2,3,4,5,6,7" line.long 0x4 "SPRFSR,SPI Receive FIFO Status Register" bitfld.long 0x4 0.--2. "RFDN,Receive FIFO data store stage number" "0,1,2,3,4,5,6,7" line.long 0x8 "SPPSR,SPI Polling Register" bitfld.long 0x8 0. "SPEPS,SPI Polling Status" "0: SPCR.SPE is 0,1: SPCR.SPE is 1" wgroup.long 0x68++0x7 line.long 0x0 "SPSRC,SPI Status Clear Register" bitfld.long 0x0 31. "SPRFC,SPI Receive Buffer Full Flag Clear" "0,1" bitfld.long 0x0 30. "CENDFC,Communication End Flag Clear" "0,1" newline bitfld.long 0x0 29. "SPTEFC,SPI Transmit Buffer Empty Flag Clear" "0,1" bitfld.long 0x0 28. "UDRFC,Underrun Error Flag Clear" "0,1" newline bitfld.long 0x0 27. "PERFC,Parity Error Flag Clear" "0,1" bitfld.long 0x0 26. "MODFC,Mode Fault Error Flag Clear" "0,1" newline bitfld.long 0x0 24. "OVRFC,Overrun Error Flag Clear" "0,1" bitfld.long 0x0 23. "SPDRFC,SPI Receive Data Ready Flag Clear" "0,1" line.long 0x4 "SPFCR,SPI FIFO Clear Register" bitfld.long 0x4 0. "SPFRST,SPI FIFO clear" "0,1" tree.end tree.end tree "SRAM (SRAM Control)" base ad:0x0 tree "SRAM" base ad:0x40002000 group.word 0x0++0x1 line.word 0x0 "SRAMPRCR_S,SRAM Protection Control Register for Secure" hexmask.word.byte 0x0 8.--15. 1. "KW,Write Key Code" bitfld.word 0x0 0. "PR,Register Write Control" "0: Writing to registers are disabled,1: Writing to registers are enabled" group.byte 0x8++0x0 line.byte 0x0 "SRAMWTSC,SRAM Wait State Control Register" bitfld.byte 0x0 0. "WTEN,SRAM Wait Enable" "0: No wait,1: Add wait state in read access cycle to SRAMs" group.byte 0x14++0x0 line.byte 0x0 "SRAMCR1,SRAM Control Register 1" bitfld.byte 0x0 0. "OAD,Operation after Detection for Parity Error Detection" "0: Non-maskable interrupt,1: Reset." rgroup.word 0x40++0x1 line.word 0x0 "SRAMESR,SRAM Error Status Register" bitfld.word 0x0 14. "ERRS,Standby SRAM Parity Error status" "0: Parity error has not occurred.,1: Parity error has occurred." bitfld.word 0x0 2. "ERR1,SRAM1 Parity Error Status" "0: Parity error has not occurred.,1: Parity error has occurred." group.word 0x48++0x1 line.word 0x0 "SRAMESCLR,SRAM Error Status Clear Register" bitfld.word 0x0 14. "CLRS,Standby SRAM Parity Error Status Clear" "?,1: Clear Parity error." bitfld.word 0x0 2. "CLR1,SRAM1 Parity Error Status Clear" "?,1: Clear Parity error." rgroup.long 0x58++0x3 line.long 0x0 "SRAMEAR2,SRAM Error Address Register" group.byte 0x110++0x0 line.byte 0x0 "STBRAMCR,Standby SRAM Control Register" bitfld.byte 0x0 0. "OAD,Operation after detection" "0: Non-maskable interrupt.,1: Reset." rgroup.long 0x150++0x3 line.long 0x0 "STBRAMEAR,Standby SRAM Error Address Register" tree.end tree "SRAM_NS" base ad:0x50002000 group.word 0x4++0x1 line.word 0x0 "SRAMPRCR_NS,SRAM Protection Control Register for Non-secure" hexmask.word.byte 0x0 8.--15. 1. "KW,Write Key Code" bitfld.word 0x0 0. "PR,Register Write Control" "0: Writing to registers are disabled,1: Writing to registers are enabled" group.byte 0x8++0x0 line.byte 0x0 "SRAMWTSC,SRAM Wait State Control Register" bitfld.byte 0x0 0. "WTEN,SRAM Wait Enable" "0: No wait,1: Add wait state in read access cycle to SRAMs" group.byte 0x14++0x0 line.byte 0x0 "SRAMCR1,SRAM Control Register 1" bitfld.byte 0x0 0. "OAD,Operation after Detection for Parity Error Detection" "0: Non-maskable interrupt,1: Reset." rgroup.word 0x40++0x1 line.word 0x0 "SRAMESR,SRAM Error Status Register" bitfld.word 0x0 14. "ERRS,Standby SRAM Parity Error status" "0: Parity error has not occurred.,1: Parity error has occurred." bitfld.word 0x0 2. "ERR1,SRAM1 Parity Error Status" "0: Parity error has not occurred.,1: Parity error has occurred." group.word 0x48++0x1 line.word 0x0 "SRAMESCLR,SRAM Error Status Clear Register" bitfld.word 0x0 14. "CLRS,Standby SRAM Parity Error Status Clear" "?,1: Clear Parity error." bitfld.word 0x0 2. "CLR1,SRAM1 Parity Error Status Clear" "?,1: Clear Parity error." rgroup.long 0x58++0x3 line.long 0x0 "SRAMEAR2,SRAM Error Address Register" group.byte 0x110++0x0 line.byte 0x0 "STBRAMCR,Standby SRAM Control Register" bitfld.byte 0x0 0. "OAD,Operation after detection" "0: Non-maskable interrupt.,1: Reset." rgroup.long 0x150++0x3 line.long 0x0 "STBRAMEAR,Standby SRAM Error Address Register" tree.end tree.end tree "SSIE (Serial Sound Interface Enhanced)" base ad:0x0 tree "SSIE0" base ad:0x4025D000 group.long 0x0++0x7 line.long 0x0 "SSICR,Control Register" bitfld.long 0x0 30. "CKS,Selects an Audio Clock for Master-mode Communication" "0: Selects the AUDIO_CLK input,1: Selects the GTIOC2A (GPT output)" bitfld.long 0x0 29. "TUIEN,Transmit Underflow Interrupt Output Enable" "0: Disables transmit underflow interrupt output,1: Enables transmit underflow interrupt output" newline bitfld.long 0x0 28. "TOIEN,Transmit Overflow Interrupt Output Enable" "0: Disables transmit overflow interrupt output,1: Enables transmit overflow interrupt output" bitfld.long 0x0 27. "RUIEN,Receive Underflow Interrupt Output Enable" "0: Disables receive underflow interrupt output,1: Enables receive underflow interrupt output" newline bitfld.long 0x0 26. "ROIEN,Receive Overflow Interrupt Output Enable" "0: Disables receive overflow interrupt output,1: Enables receive overflow interrupt output" bitfld.long 0x0 25. "IIEN,Idle Mode Interrupt Output Enable" "0: Disables idle mode interrupt output,1: Enables idle mode interrupt output" newline bitfld.long 0x0 22.--23. "FRM,Selects Frame Word Number" "0,1,2,3" bitfld.long 0x0 19.--21. "DWL,Selects Data Word Length" "0: 8 bits,1: 16 bits,?,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "SWL,Selects System Word Length" "0: 8 bits,1: 16 bits,?,?,?,?,?,?" bitfld.long 0x0 14. "MST,Master Enable" "0: Slave-mode communication,1: Master-mode communication" newline bitfld.long 0x0 13. "BCKP,Selects Bit Clock Polarity" "0: SSILRCKn/SSIFSn (n = 0 1) and..,1: SSILRCKn/SSIFSn (n = 0 1) and.." bitfld.long 0x0 12. "LRCKP,Selects the Initial Value and Polarity of LR Clock/Frame Synchronization Signal" "0: The initial value is at a high level. The start..,1: The initial value is at a low level. The start.." newline bitfld.long 0x0 11. "SPDP,Selects Serial Padding Polarity" "0: Padding data is at a low level,1: Padding data is at a high level" bitfld.long 0x0 10. "SDTA,Selects Serial Data Alignment" "0: Transmits and receives serial data first and..,1: Transmit and receives padding bits first and.." newline bitfld.long 0x0 9. "PDTA,Selects Placement Data Alignment" "0: Left-justifies placement data (SSIFTDR SSIFRDR),1: Right-justifies placement data (SSIFTDR SSIFRDR)" bitfld.long 0x0 8. "DEL,Selects Serial Data Delay" "0: Delay of 1 cycle of SSIBCKn (n = 0 1) between..,1: No delay between SSILRCKn/SSIFSn (n = 0 1) and.." newline hexmask.long.byte 0x0 4.--7. 1. "CKDV,Selects Bit Clock Division Ratio" bitfld.long 0x0 3. "MUEN,Mute Enable" "0: Disables muting on the next frame boundary,1: Enables muting on the next frame boundary" newline bitfld.long 0x0 1. "TEN,Transmission Enable" "0: Disables transmission,1: Enables transmission (starts transmission)" bitfld.long 0x0 0. "REN,Reception Enable" "0: Disables reception,1: Enables reception (starts reception)" line.long 0x4 "SSISR,Status Register" bitfld.long 0x4 29. "TUIRQ,Transmit Underflow Error Status flag" "0: No transmit underflow error is generated.,1: A transmit underflow error is generated." bitfld.long 0x4 28. "TOIRQ,Transmit Overflow Error Status Flag" "0: No transmit overflow error is generated.,1: A transmit overflow error is generated." newline bitfld.long 0x4 27. "RUIRQ,Receive Underflow Error Status Flag" "0: No receive underflow error is generated.,1: A receive underflow error is generated." bitfld.long 0x4 26. "ROIRQ,Receive Overflow Error Status Flag" "0: No receive overflow error is generated.,1: A receive overflow error is generated." newline rbitfld.long 0x4 25. "IIRQ,Idle Mode Status Flag" "0: In the communication state,1: In the idle state" group.long 0x10++0x7 line.long 0x0 "SSIFCR,FIFO Control Register" bitfld.long 0x0 31. "AUCKE,AUDIO_MCK Enable in Mastermode Communication" "0: Disables supply of AUDIO_MCK,1: Enables supply of AUDIO_MCK" bitfld.long 0x0 16. "SSIRST,Software Reset" "0: Clears a software reset condition,1: Sets a software reset condition" newline bitfld.long 0x0 11. "BSW,Byte Swap Enable" "0: Disables byte swap,1: Enables byte swap" bitfld.long 0x0 3. "TIE,Transmit Data Empty Interrupt Output Enable" "0: Disables transmit data empty interrupts,1: Enables transmit data empty interrupts" newline bitfld.long 0x0 2. "RIE,Receive Data Full Interrupt Output Enable" "0: Disables receive data full interrupts,1: Enables receive data full interrupts" bitfld.long 0x0 1. "TFRST,Transmit FIFO Data Register Reset" "0: Clears a transmit data FIFO reset condition,1: Sets a transmit data FIFO reset condition" newline bitfld.long 0x0 0. "RFRST,Receive FIFO Data Register Reset" "0: Clears a receive data FIFO reset condition,1: Sets a receive data FIFO reset condition" line.long 0x4 "SSIFSR,FIFO Status Register" hexmask.long.byte 0x4 24.--29. 1. "TDC,Transmit Data Count" bitfld.long 0x4 16. "TDE,Transmit Data Empty Flag" "0: The free space of SSIFTDR is not more than the..,1: The free space of SSIFTDR is not less than the.." newline hexmask.long.byte 0x4 8.--13. 1. "RDC,Receive Data Count" bitfld.long 0x4 0. "RDF,Receive Data Full Flag" "0: The size of received data in SSIFRDR is not more..,1: The size of received data in SSIFRDR is not less.." wgroup.long 0x18++0x3 line.long 0x0 "SSIFTDR,Transmit FIFO Data Register" hexmask.long 0x0 0.--31. 1. "SSIFTDR,Transmit FIFO Data" rgroup.long 0x1C++0x3 line.long 0x0 "SSIFRDR,Receive FIFO Data Register" hexmask.long 0x0 0.--31. 1. "SSIFRDR,Receive FIFO Data" group.long 0x20++0x7 line.long 0x0 "SSIOFR,Audio Format Register" bitfld.long 0x0 9. "BCKASTP,Whether to Enable Stopping BCK Output When SSIE is in Idle Status" "0: Always outputs BCK to the SSIBCKn (n = 0 1) pin,1: Automatically controls output of BCK to the.." bitfld.long 0x0 8. "LRCONT,Whether to Enable LRCK/FS Continuation" "0: Disables LRCK/FS continuation,1: Enables LRCK/FS continuation" newline bitfld.long 0x0 0.--1. "OMOD,Audio Format Select" "0: I2S format,1: TDM format,?,?" line.long 0x4 "SSISCR,Status Control Register" hexmask.long.byte 0x4 8.--12. 1. "TDES,TDE Setting Condition Select" hexmask.long.byte 0x4 0.--4. 1. "RDFS,RDF Setting Condition Select" tree.end tree "SSIE0_NS" base ad:0x5025D000 group.long 0x0++0x7 line.long 0x0 "SSICR,Control Register" bitfld.long 0x0 30. "CKS,Selects an Audio Clock for Master-mode Communication" "0: Selects the AUDIO_CLK input,1: Selects the GTIOC2A (GPT output)" bitfld.long 0x0 29. "TUIEN,Transmit Underflow Interrupt Output Enable" "0: Disables transmit underflow interrupt output,1: Enables transmit underflow interrupt output" newline bitfld.long 0x0 28. "TOIEN,Transmit Overflow Interrupt Output Enable" "0: Disables transmit overflow interrupt output,1: Enables transmit overflow interrupt output" bitfld.long 0x0 27. "RUIEN,Receive Underflow Interrupt Output Enable" "0: Disables receive underflow interrupt output,1: Enables receive underflow interrupt output" newline bitfld.long 0x0 26. "ROIEN,Receive Overflow Interrupt Output Enable" "0: Disables receive overflow interrupt output,1: Enables receive overflow interrupt output" bitfld.long 0x0 25. "IIEN,Idle Mode Interrupt Output Enable" "0: Disables idle mode interrupt output,1: Enables idle mode interrupt output" newline bitfld.long 0x0 22.--23. "FRM,Selects Frame Word Number" "0,1,2,3" bitfld.long 0x0 19.--21. "DWL,Selects Data Word Length" "0: 8 bits,1: 16 bits,?,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "SWL,Selects System Word Length" "0: 8 bits,1: 16 bits,?,?,?,?,?,?" bitfld.long 0x0 14. "MST,Master Enable" "0: Slave-mode communication,1: Master-mode communication" newline bitfld.long 0x0 13. "BCKP,Selects Bit Clock Polarity" "0: SSILRCKn/SSIFSn (n = 0 1) and..,1: SSILRCKn/SSIFSn (n = 0 1) and.." bitfld.long 0x0 12. "LRCKP,Selects the Initial Value and Polarity of LR Clock/Frame Synchronization Signal" "0: The initial value is at a high level. The start..,1: The initial value is at a low level. The start.." newline bitfld.long 0x0 11. "SPDP,Selects Serial Padding Polarity" "0: Padding data is at a low level,1: Padding data is at a high level" bitfld.long 0x0 10. "SDTA,Selects Serial Data Alignment" "0: Transmits and receives serial data first and..,1: Transmit and receives padding bits first and.." newline bitfld.long 0x0 9. "PDTA,Selects Placement Data Alignment" "0: Left-justifies placement data (SSIFTDR SSIFRDR),1: Right-justifies placement data (SSIFTDR SSIFRDR)" bitfld.long 0x0 8. "DEL,Selects Serial Data Delay" "0: Delay of 1 cycle of SSIBCKn (n = 0 1) between..,1: No delay between SSILRCKn/SSIFSn (n = 0 1) and.." newline hexmask.long.byte 0x0 4.--7. 1. "CKDV,Selects Bit Clock Division Ratio" bitfld.long 0x0 3. "MUEN,Mute Enable" "0: Disables muting on the next frame boundary,1: Enables muting on the next frame boundary" newline bitfld.long 0x0 1. "TEN,Transmission Enable" "0: Disables transmission,1: Enables transmission (starts transmission)" bitfld.long 0x0 0. "REN,Reception Enable" "0: Disables reception,1: Enables reception (starts reception)" line.long 0x4 "SSISR,Status Register" bitfld.long 0x4 29. "TUIRQ,Transmit Underflow Error Status flag" "0: No transmit underflow error is generated.,1: A transmit underflow error is generated." bitfld.long 0x4 28. "TOIRQ,Transmit Overflow Error Status Flag" "0: No transmit overflow error is generated.,1: A transmit overflow error is generated." newline bitfld.long 0x4 27. "RUIRQ,Receive Underflow Error Status Flag" "0: No receive underflow error is generated.,1: A receive underflow error is generated." bitfld.long 0x4 26. "ROIRQ,Receive Overflow Error Status Flag" "0: No receive overflow error is generated.,1: A receive overflow error is generated." newline rbitfld.long 0x4 25. "IIRQ,Idle Mode Status Flag" "0: In the communication state,1: In the idle state" group.long 0x10++0x7 line.long 0x0 "SSIFCR,FIFO Control Register" bitfld.long 0x0 31. "AUCKE,AUDIO_MCK Enable in Mastermode Communication" "0: Disables supply of AUDIO_MCK,1: Enables supply of AUDIO_MCK" bitfld.long 0x0 16. "SSIRST,Software Reset" "0: Clears a software reset condition,1: Sets a software reset condition" newline bitfld.long 0x0 11. "BSW,Byte Swap Enable" "0: Disables byte swap,1: Enables byte swap" bitfld.long 0x0 3. "TIE,Transmit Data Empty Interrupt Output Enable" "0: Disables transmit data empty interrupts,1: Enables transmit data empty interrupts" newline bitfld.long 0x0 2. "RIE,Receive Data Full Interrupt Output Enable" "0: Disables receive data full interrupts,1: Enables receive data full interrupts" bitfld.long 0x0 1. "TFRST,Transmit FIFO Data Register Reset" "0: Clears a transmit data FIFO reset condition,1: Sets a transmit data FIFO reset condition" newline bitfld.long 0x0 0. "RFRST,Receive FIFO Data Register Reset" "0: Clears a receive data FIFO reset condition,1: Sets a receive data FIFO reset condition" line.long 0x4 "SSIFSR,FIFO Status Register" hexmask.long.byte 0x4 24.--29. 1. "TDC,Transmit Data Count" bitfld.long 0x4 16. "TDE,Transmit Data Empty Flag" "0: The free space of SSIFTDR is not more than the..,1: The free space of SSIFTDR is not less than the.." newline hexmask.long.byte 0x4 8.--13. 1. "RDC,Receive Data Count" bitfld.long 0x4 0. "RDF,Receive Data Full Flag" "0: The size of received data in SSIFRDR is not more..,1: The size of received data in SSIFRDR is not less.." wgroup.long 0x18++0x3 line.long 0x0 "SSIFTDR,Transmit FIFO Data Register" hexmask.long 0x0 0.--31. 1. "SSIFTDR,Transmit FIFO Data" rgroup.long 0x1C++0x3 line.long 0x0 "SSIFRDR,Receive FIFO Data Register" hexmask.long 0x0 0.--31. 1. "SSIFRDR,Receive FIFO Data" group.long 0x20++0x7 line.long 0x0 "SSIOFR,Audio Format Register" bitfld.long 0x0 9. "BCKASTP,Whether to Enable Stopping BCK Output When SSIE is in Idle Status" "0: Always outputs BCK to the SSIBCKn (n = 0 1) pin,1: Automatically controls output of BCK to the.." bitfld.long 0x0 8. "LRCONT,Whether to Enable LRCK/FS Continuation" "0: Disables LRCK/FS continuation,1: Enables LRCK/FS continuation" newline bitfld.long 0x0 0.--1. "OMOD,Audio Format Select" "0: I2S format,1: TDM format,?,?" line.long 0x4 "SSISCR,Status Control Register" hexmask.long.byte 0x4 8.--12. 1. "TDES,TDE Setting Condition Select" hexmask.long.byte 0x4 0.--4. 1. "RDFS,RDF Setting Condition Select" tree.end tree "SSIE1" base ad:0x4025D100 group.long 0x0++0x7 line.long 0x0 "SSICR,Control Register" bitfld.long 0x0 30. "CKS,Selects an Audio Clock for Master-mode Communication" "0: Selects the AUDIO_CLK input,1: Selects the GTIOC2A (GPT output)" bitfld.long 0x0 29. "TUIEN,Transmit Underflow Interrupt Output Enable" "0: Disables transmit underflow interrupt output,1: Enables transmit underflow interrupt output" newline bitfld.long 0x0 28. "TOIEN,Transmit Overflow Interrupt Output Enable" "0: Disables transmit overflow interrupt output,1: Enables transmit overflow interrupt output" bitfld.long 0x0 27. "RUIEN,Receive Underflow Interrupt Output Enable" "0: Disables receive underflow interrupt output,1: Enables receive underflow interrupt output" newline bitfld.long 0x0 26. "ROIEN,Receive Overflow Interrupt Output Enable" "0: Disables receive overflow interrupt output,1: Enables receive overflow interrupt output" bitfld.long 0x0 25. "IIEN,Idle Mode Interrupt Output Enable" "0: Disables idle mode interrupt output,1: Enables idle mode interrupt output" newline bitfld.long 0x0 22.--23. "FRM,Selects Frame Word Number" "0,1,2,3" bitfld.long 0x0 19.--21. "DWL,Selects Data Word Length" "0: 8 bits,1: 16 bits,?,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "SWL,Selects System Word Length" "0: 8 bits,1: 16 bits,?,?,?,?,?,?" bitfld.long 0x0 14. "MST,Master Enable" "0: Slave-mode communication,1: Master-mode communication" newline bitfld.long 0x0 13. "BCKP,Selects Bit Clock Polarity" "0: SSILRCKn/SSIFSn (n = 0 1) and..,1: SSILRCKn/SSIFSn (n = 0 1) and.." bitfld.long 0x0 12. "LRCKP,Selects the Initial Value and Polarity of LR Clock/Frame Synchronization Signal" "0: The initial value is at a high level. The start..,1: The initial value is at a low level. The start.." newline bitfld.long 0x0 11. "SPDP,Selects Serial Padding Polarity" "0: Padding data is at a low level,1: Padding data is at a high level" bitfld.long 0x0 10. "SDTA,Selects Serial Data Alignment" "0: Transmits and receives serial data first and..,1: Transmit and receives padding bits first and.." newline bitfld.long 0x0 9. "PDTA,Selects Placement Data Alignment" "0: Left-justifies placement data (SSIFTDR SSIFRDR),1: Right-justifies placement data (SSIFTDR SSIFRDR)" bitfld.long 0x0 8. "DEL,Selects Serial Data Delay" "0: Delay of 1 cycle of SSIBCKn (n = 0 1) between..,1: No delay between SSILRCKn/SSIFSn (n = 0 1) and.." newline hexmask.long.byte 0x0 4.--7. 1. "CKDV,Selects Bit Clock Division Ratio" bitfld.long 0x0 3. "MUEN,Mute Enable" "0: Disables muting on the next frame boundary,1: Enables muting on the next frame boundary" newline bitfld.long 0x0 1. "TEN,Transmission Enable" "0: Disables transmission,1: Enables transmission (starts transmission)" bitfld.long 0x0 0. "REN,Reception Enable" "0: Disables reception,1: Enables reception (starts reception)" line.long 0x4 "SSISR,Status Register" bitfld.long 0x4 29. "TUIRQ,Transmit Underflow Error Status flag" "0: No transmit underflow error is generated.,1: A transmit underflow error is generated." bitfld.long 0x4 28. "TOIRQ,Transmit Overflow Error Status Flag" "0: No transmit overflow error is generated.,1: A transmit overflow error is generated." newline bitfld.long 0x4 27. "RUIRQ,Receive Underflow Error Status Flag" "0: No receive underflow error is generated.,1: A receive underflow error is generated." bitfld.long 0x4 26. "ROIRQ,Receive Overflow Error Status Flag" "0: No receive overflow error is generated.,1: A receive overflow error is generated." newline rbitfld.long 0x4 25. "IIRQ,Idle Mode Status Flag" "0: In the communication state,1: In the idle state" group.long 0x10++0x7 line.long 0x0 "SSIFCR,FIFO Control Register" bitfld.long 0x0 31. "AUCKE,AUDIO_MCK Enable in Mastermode Communication" "0: Disables supply of AUDIO_MCK,1: Enables supply of AUDIO_MCK" bitfld.long 0x0 16. "SSIRST,Software Reset" "0: Clears a software reset condition,1: Sets a software reset condition" newline bitfld.long 0x0 11. "BSW,Byte Swap Enable" "0: Disables byte swap,1: Enables byte swap" bitfld.long 0x0 3. "TIE,Transmit Data Empty Interrupt Output Enable" "0: Disables transmit data empty interrupts,1: Enables transmit data empty interrupts" newline bitfld.long 0x0 2. "RIE,Receive Data Full Interrupt Output Enable" "0: Disables receive data full interrupts,1: Enables receive data full interrupts" bitfld.long 0x0 1. "TFRST,Transmit FIFO Data Register Reset" "0: Clears a transmit data FIFO reset condition,1: Sets a transmit data FIFO reset condition" newline bitfld.long 0x0 0. "RFRST,Receive FIFO Data Register Reset" "0: Clears a receive data FIFO reset condition,1: Sets a receive data FIFO reset condition" line.long 0x4 "SSIFSR,FIFO Status Register" hexmask.long.byte 0x4 24.--29. 1. "TDC,Transmit Data Count" bitfld.long 0x4 16. "TDE,Transmit Data Empty Flag" "0: The free space of SSIFTDR is not more than the..,1: The free space of SSIFTDR is not less than the.." newline hexmask.long.byte 0x4 8.--13. 1. "RDC,Receive Data Count" bitfld.long 0x4 0. "RDF,Receive Data Full Flag" "0: The size of received data in SSIFRDR is not more..,1: The size of received data in SSIFRDR is not less.." wgroup.long 0x18++0x3 line.long 0x0 "SSIFTDR,Transmit FIFO Data Register" hexmask.long 0x0 0.--31. 1. "SSIFTDR,Transmit FIFO Data" rgroup.long 0x1C++0x3 line.long 0x0 "SSIFRDR,Receive FIFO Data Register" hexmask.long 0x0 0.--31. 1. "SSIFRDR,Receive FIFO Data" group.long 0x20++0x7 line.long 0x0 "SSIOFR,Audio Format Register" bitfld.long 0x0 9. "BCKASTP,Whether to Enable Stopping BCK Output When SSIE is in Idle Status" "0: Always outputs BCK to the SSIBCKn (n = 0 1) pin,1: Automatically controls output of BCK to the.." bitfld.long 0x0 8. "LRCONT,Whether to Enable LRCK/FS Continuation" "0: Disables LRCK/FS continuation,1: Enables LRCK/FS continuation" newline bitfld.long 0x0 0.--1. "OMOD,Audio Format Select" "0: I2S format,1: TDM format,?,?" line.long 0x4 "SSISCR,Status Control Register" hexmask.long.byte 0x4 8.--12. 1. "TDES,TDE Setting Condition Select" hexmask.long.byte 0x4 0.--4. 1. "RDFS,RDF Setting Condition Select" tree.end tree "SSIE1_NS" base ad:0x5025D100 group.long 0x0++0x7 line.long 0x0 "SSICR,Control Register" bitfld.long 0x0 30. "CKS,Selects an Audio Clock for Master-mode Communication" "0: Selects the AUDIO_CLK input,1: Selects the GTIOC2A (GPT output)" bitfld.long 0x0 29. "TUIEN,Transmit Underflow Interrupt Output Enable" "0: Disables transmit underflow interrupt output,1: Enables transmit underflow interrupt output" newline bitfld.long 0x0 28. "TOIEN,Transmit Overflow Interrupt Output Enable" "0: Disables transmit overflow interrupt output,1: Enables transmit overflow interrupt output" bitfld.long 0x0 27. "RUIEN,Receive Underflow Interrupt Output Enable" "0: Disables receive underflow interrupt output,1: Enables receive underflow interrupt output" newline bitfld.long 0x0 26. "ROIEN,Receive Overflow Interrupt Output Enable" "0: Disables receive overflow interrupt output,1: Enables receive overflow interrupt output" bitfld.long 0x0 25. "IIEN,Idle Mode Interrupt Output Enable" "0: Disables idle mode interrupt output,1: Enables idle mode interrupt output" newline bitfld.long 0x0 22.--23. "FRM,Selects Frame Word Number" "0,1,2,3" bitfld.long 0x0 19.--21. "DWL,Selects Data Word Length" "0: 8 bits,1: 16 bits,?,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "SWL,Selects System Word Length" "0: 8 bits,1: 16 bits,?,?,?,?,?,?" bitfld.long 0x0 14. "MST,Master Enable" "0: Slave-mode communication,1: Master-mode communication" newline bitfld.long 0x0 13. "BCKP,Selects Bit Clock Polarity" "0: SSILRCKn/SSIFSn (n = 0 1) and..,1: SSILRCKn/SSIFSn (n = 0 1) and.." bitfld.long 0x0 12. "LRCKP,Selects the Initial Value and Polarity of LR Clock/Frame Synchronization Signal" "0: The initial value is at a high level. The start..,1: The initial value is at a low level. The start.." newline bitfld.long 0x0 11. "SPDP,Selects Serial Padding Polarity" "0: Padding data is at a low level,1: Padding data is at a high level" bitfld.long 0x0 10. "SDTA,Selects Serial Data Alignment" "0: Transmits and receives serial data first and..,1: Transmit and receives padding bits first and.." newline bitfld.long 0x0 9. "PDTA,Selects Placement Data Alignment" "0: Left-justifies placement data (SSIFTDR SSIFRDR),1: Right-justifies placement data (SSIFTDR SSIFRDR)" bitfld.long 0x0 8. "DEL,Selects Serial Data Delay" "0: Delay of 1 cycle of SSIBCKn (n = 0 1) between..,1: No delay between SSILRCKn/SSIFSn (n = 0 1) and.." newline hexmask.long.byte 0x0 4.--7. 1. "CKDV,Selects Bit Clock Division Ratio" bitfld.long 0x0 3. "MUEN,Mute Enable" "0: Disables muting on the next frame boundary,1: Enables muting on the next frame boundary" newline bitfld.long 0x0 1. "TEN,Transmission Enable" "0: Disables transmission,1: Enables transmission (starts transmission)" bitfld.long 0x0 0. "REN,Reception Enable" "0: Disables reception,1: Enables reception (starts reception)" line.long 0x4 "SSISR,Status Register" bitfld.long 0x4 29. "TUIRQ,Transmit Underflow Error Status flag" "0: No transmit underflow error is generated.,1: A transmit underflow error is generated." bitfld.long 0x4 28. "TOIRQ,Transmit Overflow Error Status Flag" "0: No transmit overflow error is generated.,1: A transmit overflow error is generated." newline bitfld.long 0x4 27. "RUIRQ,Receive Underflow Error Status Flag" "0: No receive underflow error is generated.,1: A receive underflow error is generated." bitfld.long 0x4 26. "ROIRQ,Receive Overflow Error Status Flag" "0: No receive overflow error is generated.,1: A receive overflow error is generated." newline rbitfld.long 0x4 25. "IIRQ,Idle Mode Status Flag" "0: In the communication state,1: In the idle state" group.long 0x10++0x7 line.long 0x0 "SSIFCR,FIFO Control Register" bitfld.long 0x0 31. "AUCKE,AUDIO_MCK Enable in Mastermode Communication" "0: Disables supply of AUDIO_MCK,1: Enables supply of AUDIO_MCK" bitfld.long 0x0 16. "SSIRST,Software Reset" "0: Clears a software reset condition,1: Sets a software reset condition" newline bitfld.long 0x0 11. "BSW,Byte Swap Enable" "0: Disables byte swap,1: Enables byte swap" bitfld.long 0x0 3. "TIE,Transmit Data Empty Interrupt Output Enable" "0: Disables transmit data empty interrupts,1: Enables transmit data empty interrupts" newline bitfld.long 0x0 2. "RIE,Receive Data Full Interrupt Output Enable" "0: Disables receive data full interrupts,1: Enables receive data full interrupts" bitfld.long 0x0 1. "TFRST,Transmit FIFO Data Register Reset" "0: Clears a transmit data FIFO reset condition,1: Sets a transmit data FIFO reset condition" newline bitfld.long 0x0 0. "RFRST,Receive FIFO Data Register Reset" "0: Clears a receive data FIFO reset condition,1: Sets a receive data FIFO reset condition" line.long 0x4 "SSIFSR,FIFO Status Register" hexmask.long.byte 0x4 24.--29. 1. "TDC,Transmit Data Count" bitfld.long 0x4 16. "TDE,Transmit Data Empty Flag" "0: The free space of SSIFTDR is not more than the..,1: The free space of SSIFTDR is not less than the.." newline hexmask.long.byte 0x4 8.--13. 1. "RDC,Receive Data Count" bitfld.long 0x4 0. "RDF,Receive Data Full Flag" "0: The size of received data in SSIFRDR is not more..,1: The size of received data in SSIFRDR is not less.." wgroup.long 0x18++0x3 line.long 0x0 "SSIFTDR,Transmit FIFO Data Register" hexmask.long 0x0 0.--31. 1. "SSIFTDR,Transmit FIFO Data" rgroup.long 0x1C++0x3 line.long 0x0 "SSIFRDR,Receive FIFO Data Register" hexmask.long 0x0 0.--31. 1. "SSIFRDR,Receive FIFO Data" group.long 0x20++0x7 line.long 0x0 "SSIOFR,Audio Format Register" bitfld.long 0x0 9. "BCKASTP,Whether to Enable Stopping BCK Output When SSIE is in Idle Status" "0: Always outputs BCK to the SSIBCKn (n = 0 1) pin,1: Automatically controls output of BCK to the.." bitfld.long 0x0 8. "LRCONT,Whether to Enable LRCK/FS Continuation" "0: Disables LRCK/FS continuation,1: Enables LRCK/FS continuation" newline bitfld.long 0x0 0.--1. "OMOD,Audio Format Select" "0: I2S format,1: TDM format,?,?" line.long 0x4 "SSISCR,Status Control Register" hexmask.long.byte 0x4 8.--12. 1. "TDES,TDE Setting Condition Select" hexmask.long.byte 0x4 0.--4. 1. "RDFS,RDF Setting Condition Select" tree.end tree.end tree "SYSC (System Control)" base ad:0x0 tree "SYSC" base ad:0x4001E000 group.byte 0xC++0x0 line.byte 0x0 "SBYCR,Standby Control Register" bitfld.byte 0x0 6. "OPE,Output Port Enable" "0: In Software Standby mode or Deep Software..,1: In Software Standby mode or Deep Software.." group.long 0x20++0x3 line.long 0x0 "SCKDIVCR,System Clock Division Control Register" hexmask.long.byte 0x0 28.--31. 1. "FCK,FlashIF Clock (FCLK) Select" hexmask.long.byte 0x0 24.--27. 1. "ICK,System Clock (ICLK) Select" newline hexmask.long.byte 0x0 16.--19. 1. "BCK,External Bus Clock (BCLK) Select" hexmask.long.byte 0x0 12.--15. 1. "PCKA,Peripheral Module Clock A (PCLKA) Select" newline hexmask.long.byte 0x0 8.--11. 1. "PCKB,Peripheral Module Clock B (PCLKB) Select" hexmask.long.byte 0x0 4.--7. 1. "PCKC,Peripheral Module Clock C (PCLKC) Select" newline hexmask.long.byte 0x0 0.--3. 1. "PCKD,Peripheral Module Clock D (PCLKD) Select" group.byte 0x24++0x0 line.byte 0x0 "SCKDIVCR2,System Clock Division Control Register 2" hexmask.byte 0x0 0.--3. 1. "CPUCK,CPU Clock (CPUCLK) Select" group.byte 0x26++0x0 line.byte 0x0 "SCKSCR,System Clock Source Control Register" bitfld.byte 0x0 0.--2. "CKSEL,Clock Source Select" "0: HOCO,1: MOCO (Value after reset),?,?,?,?,?,?" group.word 0x28++0x1 line.word 0x0 "PLLCCR,PLL Clock Control Register" hexmask.word.byte 0x0 8.--15. 1. "PLLMUL,PLL1 Frequency Multiplication Factor Select" bitfld.word 0x0 6.--7. "PLLMULNF,PLL1 Frequency Multiplication Fractional Factor Select" "0: 0.00 (Value after reset),1: 0.33 (1/3),?,?" newline bitfld.word 0x0 4. "PLSRCSEL,PLL1 Clock Source Select" "0: Main clock oscillator,1: HOCO" bitfld.word 0x0 0.--1. "PLIDIV,PLL1 Input Frequency Division Ratio Select" "0: 1/1,1: 1/2,?,?" group.byte 0x2A++0x0 line.byte 0x0 "PLLCR,PLL Control Register" bitfld.byte 0x0 0. "PLLSTP,PLL1 Stop Control" "0: PLL1 is operating,1: PLL1 is stopped" group.byte 0x30++0x0 line.byte 0x0 "BCKCR,External Bus Clock Control Register" bitfld.byte 0x0 0. "BCLKDIV,BCLK Pin Output Select" "0: BCLK,1: BCLK/2" group.byte 0x32++0x0 line.byte 0x0 "MOSCCR,Main Clock Oscillator Control Register" bitfld.byte 0x0 0. "MOSTP,Main Clock Oscillator Stop" "0: Operate the main clock oscillator,1: Stop the main clock oscillator" group.byte 0x36++0x3 line.byte 0x0 "HOCOCR,High-Speed On-Chip Oscillator Control Register" bitfld.byte 0x0 0. "HCSTP,HOCO Stop" "0: Operate the HOCO clock,1: Stop the HOCO clock" line.byte 0x1 "HOCOCR2,High-Speed On-Chip Oscillator Control Register2" bitfld.byte 0x1 0.--2. "HCFRQ0,HOCO Frequency Setting 0" "0: 16MHz,1: 18MHz,?,?,?,?,?,?" line.byte 0x2 "MOCOCR,Middle-Speed On-Chip Oscillator Control Register" bitfld.byte 0x2 0. "MCSTP,MOCO Stop" "0: MOCO clock is operating,1: MOCO clock is stopped" line.byte 0x3 "FLLCR1,FLL Control Register1" bitfld.byte 0x3 0. "FLLEN,FLL Enable" "0: FLL function is disabled,1: FLL function is enabled." group.word 0x3A++0x1 line.word 0x0 "FLLCR2,FLL Control Register2" hexmask.word 0x0 0.--10. 1. "FLLCNTL,FLL Multiplication Control" rgroup.byte 0x3C++0x0 line.byte 0x0 "OSCSF,Oscillation Stabilization Flag Register" bitfld.byte 0x0 6. "PLL2SF,PLL2 Clock Oscillation Stabilization Flag" "0: The PLL2 clock is stopped or is not yet stable.,1: The PLL2 clock is stable" bitfld.byte 0x0 5. "PLLSF,PLL1 Clock Oscillation Stabilization Flag" "0: The PLL1 clock is stopped or is not yet stable.,1: The PLL1 clock is stable so is available for use.." newline bitfld.byte 0x0 3. "MOSCSF,Main Clock Oscillation Stabilization Flag" "0: The main clock oscillator is stopped or is not..,1: The main clock oscillator is stable so is.." bitfld.byte 0x0 0. "HOCOSF,HOCO Clock Oscillation Stabilization Flag" "0: The HOCO clock is stopped or is not yet stable,1: The HOCO clock is stable so is available for use.." group.byte 0x3E++0x3 line.byte 0x0 "CKOCR,Clock Out Control Register" bitfld.byte 0x0 7. "CKOEN,Clock Out Enable" "0: Disable clock out,1: Enable clock out" bitfld.byte 0x0 4.--6. "CKODIV,Clock Output Frequency Division Ratio" "0: x 1/1,1: x 1/2,?,?,?,?,?,?" newline bitfld.byte 0x0 0.--2. "CKOSEL,Clock Out Source Select" "0: Setting prohibited,1: MOCO (Value after reset),?,?,?,?,?,?" line.byte 0x1 "TRCKCR,Trace Clock Control Register" bitfld.byte 0x1 7. "TRCKEN,Trace Clock operating Enable" "0: Stop,1: Operation enable" bitfld.byte 0x1 4. "TRCKSEL,Trace Clock source select" "0: System clock source (Value after reset),1: HOCO (oscillation in debug mode)" newline hexmask.byte 0x1 0.--3. 1. "TRCK,Trace Clock operating frequency select" line.byte 0x2 "OSTDCR,Oscillation Stop Detection Control Register" bitfld.byte 0x2 7. "OSTDE,Oscillation Stop Detection Function Enable" "0: Disable oscillation stop detection function,1: Enable oscillation stop detection function" bitfld.byte 0x2 0. "OSTDIE,Oscillation Stop Detection Interrupt Enable" "0: Disable oscillation stop detection interrupt (do..,1: Enable oscillation stop detection interrupt.." line.byte 0x3 "OSTDSR,Oscillation Stop Detection Status Register" bitfld.byte 0x3 0. "OSTDF,Oscillation Stop Detection Flag" "0: Main clock oscillation stop not detected,1: Main clock oscillation stop detected" rgroup.byte 0x43++0x0 line.byte 0x0 "OSCMONR,Oscillator Monitor Register" bitfld.byte 0x0 2. "LOCOMON,LOCO operation monitor" "0: LOCO is set to operate.,1: LOCO is set to stop." bitfld.byte 0x0 1. "MOCOMON,MOCO operation monitor" "0: MOCO is set to operate.,1: MOCO is set to stop." group.word 0x48++0x1 line.word 0x0 "PLL2CCR,PLL2 Clock Control Register" hexmask.word.byte 0x0 8.--15. 1. "PLL2MUL,PLL2 Frequency Multiplication Factor Select" bitfld.word 0x0 6.--7. "PLL2MULNF,PLL2 Frequency Multiplication Fractional Factor Select" "0: 0.00 (Value after reset),1: 0.33 (1/3),?,?" newline bitfld.word 0x0 4. "PL2SRCSEL,PLL2 Clock Source Select" "0: Main clock oscillator,1: HOCO" bitfld.word 0x0 0.--1. "PL2IDIV,PLL2 Input Frequency Division Ratio Select" "0: 1/1 (Value after reset),1: 1/2,?,?" group.byte 0x4A++0x0 line.byte 0x0 "PLL2CR,PLL2 Control Register" bitfld.byte 0x0 0. "PLL2STP,PLL2 Stop Control" "0: PLL2 is operating,1: PLL2 is stopped" group.word 0x4C++0x3 line.word 0x0 "PLLCCR2,PLL Clock Control Register 2" hexmask.word.byte 0x0 8.--11. 1. "PLODIVR,PLL1 Output Frequency Division Ratio Select for output clock R" hexmask.word.byte 0x0 4.--7. 1. "PLODIVQ,PLL1 Output Frequency Division Ratio Select for output clock Q" newline hexmask.word.byte 0x0 0.--3. 1. "PLODIVP,PLL1 Output Frequency Division Ratio Select for output clock P" line.word 0x2 "PLL2CCR2,PLL2 Clock Control Register 2" hexmask.word.byte 0x2 8.--11. 1. "PL2ODIVR,PLL2 Output Frequency Division Ratio Select for output clock R" hexmask.word.byte 0x2 4.--7. 1. "PL2ODIVQ,PLL2 Output Frequency Division Ratio Select for output clock Q" newline hexmask.word.byte 0x2 0.--3. 1. "PL2ODIVP,PLL2 Output Frequency Division Ratio Select for output clock P" group.byte 0x52++0x5 line.byte 0x0 "EBCKOCR,External Bus Clock Output Control Register" bitfld.byte 0x0 0. "EBCKOEN,EBCLK Pin Output Control" "0: EBCLK pin output is disabled (fixed high),1: EBCLK pin output is enabled." line.byte 0x1 "SDCKOCR,SDRAM Clock Output Control Register" bitfld.byte 0x1 0. "SDCKOEN,SDCLK Pin Output Control" "0: SDCLK pin output is disabled. (Fixed high),1: SDCLK pin output is enabled." line.byte 0x2 "SCICKDIVCR,SCI clock Division control register" bitfld.byte 0x2 0.--2. "SCICKDIV,SCI clock (SCICLK) Division Select" "0: Setting prohibited.,1: 1/2,?,?,?,?,?,?" line.byte 0x3 "SCICKCR,SCI clock control register" rbitfld.byte 0x3 7. "SCICKSRDY,SCI clock (SCICLK) Switching Ready state flag" "0: Impossible to Switch,1: Possible to Switch" bitfld.byte 0x3 6. "SCICKSREQ,SCI clock (SCICLK) Switching Request" "0: No request,1: Request switching" newline hexmask.byte 0x3 0.--3. 1. "SCICKSEL,SCI clock (SCICLK) Source Select" line.byte 0x4 "SPICKDIVCR,SPI clock Division control register" bitfld.byte 0x4 0.--2. "SPICKDIV,SPI clock (SPICLK) Division Select" "0: Setting prohibited.,1: 1/2,?,?,?,?,?,?" line.byte 0x5 "SPICKCR,SPI clock control register" rbitfld.byte 0x5 7. "SPICKSRDY,SPI clock (SPICLK) Switching Ready state flag" "0: Impossible to Switch,1: Possible to Switch" bitfld.byte 0x5 6. "SPICKSREQ,SPI clock (SPICLK) Switching Request" "0: No request,1: Request switching" newline hexmask.byte 0x5 0.--3. 1. "SPICKSEL,SPI clock (SPICLK) Source Select" group.byte 0x5E++0x1 line.byte 0x0 "LCDCKDIVCR,LCD clock Division control register" bitfld.byte 0x0 0.--2. "LCDCKDIV,LCD clock (LCDCLK) Division Select" "0: Setting prohibited.,1: 1/2,?,?,?,?,?,?" line.byte 0x1 "LCDCKCR,LCD clock control register" rbitfld.byte 0x1 7. "LCDCKSRDY,LCD clock (LCDCLK) Switching Ready state flag" "0: Impossible to Switch,1: Possible to Switch" bitfld.byte 0x1 6. "LCDCKSREQ,LCD clock (LCDCLK) Switching Request" "0: No request,1: Request switching" newline hexmask.byte 0x1 0.--3. 1. "LCDCKSEL,LCD clock (LCDCLK) Source Select" group.byte 0x61++0x1 line.byte 0x0 "MOCOUTCR,MOCO User Trimming Control Register" hexmask.byte 0x0 0.--7. 1. "MOCOUTRM,MOCO User Trimming" line.byte 0x1 "HOCOUTCR,HOCO User Trimming Control Register" hexmask.byte 0x1 0.--7. 1. "HOCOUTRM,HOCO User Trimming" group.byte 0x6C++0x2 line.byte 0x0 "USBCKDIVCR,USB Clock Division Control Register" bitfld.byte 0x0 0.--2. "USBCKDIV,USB Clock (USBCLK) Division Select" "0: Setting prohibited.,1: 1/2,?,?,?,?,?,?" line.byte 0x1 "OCTACKDIVCR,Octal-SPI Clock Division Control Register" bitfld.byte 0x1 0.--2. "OCTACKDIV,Octal-SPI Clock (OCTACLK) Division Select" "0: Setting prohibited.,1: 1/2,?,?,?,?,?,?" line.byte 0x2 "CANFDCKDIVCR,CANFD Core Clock Division Control Register" bitfld.byte 0x2 0.--2. "CANFDCKDIV,CANFD core clock (CANFDCLK) Division Select" "0: Setting prohibited,1: 1/2,?,?,?,?,?,?" group.byte 0x74++0x2 line.byte 0x0 "USBCKCR,USB Clock Control Register" rbitfld.byte 0x0 7. "USBCKSRDY,USB Clock (USBCLK) Switching Ready state flag" "0: Impossible to Switch,1: Possible to Switch" bitfld.byte 0x0 6. "USBCKSREQ,USB Clock (USBCLK) Switching Request" "0: No request,1: Request switching." newline hexmask.byte 0x0 0.--3. 1. "USBCKSEL,USB Clock (USBCLK) Source Select" line.byte 0x1 "OCTACKCR,Octal-SPI Clock Control Register" rbitfld.byte 0x1 7. "OCTACKSRDY,Octal-SPI Clock (OCTACLK) Switching Ready state flag" "0: Impossible to Switch,1: Possible to Switch" bitfld.byte 0x1 6. "OCTACKSREQ,Octal-SPI Clock (OCTACLK) Switching Request" "0: No request,1: Request switching." newline hexmask.byte 0x1 0.--3. 1. "OCTACKSEL,Octal-SPI Clock (OCTACLK) Source Select" line.byte 0x2 "CANFDCKCR,CANFD Core Clock Control Register" bitfld.byte 0x2 6. "CANFDCKSREQ,CANFD Core Clock (CANFDCLK) Switching Request" "0: No request,1: Request switching" hexmask.byte 0x2 0.--3. 1. "CANFDCKSEL,CANFD Core Clock (CANFDCLK) Source Select" group.byte 0x7C++0x1 line.byte 0x0 "MOSCSCR,Main Clock Oscillator Standby Control Register" bitfld.byte 0x0 0. "MOSCSOKP,Main Clock Oscillator Standby Oscillation Keep select" "0: Disable,1: Enable" line.byte 0x1 "HOCOSCR,High-Speed On-Chip Oscillator Standby Control Register" bitfld.byte 0x1 0. "HOCOSOKP,HOCO Standby Oscillation Keep select." "0: Disable,1: Enable" group.byte 0xA0++0x0 line.byte 0x0 "OPCCR,Operating Power Control Register" rbitfld.byte 0x0 4. "OPCMTSF,Operating Power Control Mode Transition Status Flag" "0: Transition completed,1: During transition" bitfld.byte 0x0 0.--1. "OPCM,Operating Power Control Mode Select" "0: High-speed mode,1: Setting prohibited,?,?" group.byte 0xA2++0x0 line.byte 0x0 "MOSCWTCR,Main Clock Oscillator Wait Control Register" hexmask.byte 0x0 0.--3. 1. "MSTS,Main Clock Oscillator Wait Time Setting" group.long 0xC0++0x3 line.long 0x0 "RSTSR1,Reset Status Register 1" bitfld.long 0x0 14. "CMRF,Common Memory Error Reset Detect Flag" "0: Common memory error reset not detected,1: Common memory error reset detected" bitfld.long 0x0 10. "BUSRF,Bus Error Reset Detect Flag" "0: Bus error reset not detected,1: Bus error reset detected" newline bitfld.long 0x0 4. "CLU0RF,CPU Lockup Reset Detect Flag" "0: CPU Lockup reset not detected,1: CPU Lockup reset detected" bitfld.long 0x0 2. "SWRF,Software Reset Detect Flag" "0: Software reset not detected,1: Software reset detected" newline bitfld.long 0x0 1. "WDT0RF,Watchdog Timer Reset Detect Flag" "0: Watchdog timer reset not detected,1: Watchdog timer reset detected" bitfld.long 0x0 0. "IWDTRF,Independent Watchdog Timer Reset Detect Flag" "0: Independent watchdog timer reset not detected,1: Independent watchdog timer reset detected" rgroup.byte 0xCC++0x0 line.byte 0x0 "SYRACCR,System Register Access Control Register" bitfld.byte 0x0 0. "BUSY,Access Ready monitor" "0: Ready to read/write access,1: Writing in progress" repeat 2. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0xE0)++0x0 line.byte 0x0 "PVD$1CR1,Voltage Monitor %s Circuit Control Register 1" bitfld.byte 0x0 2. "IRQSEL,Voltage Monitor m Interrupt Type Select" "0: Non-maskable interrupt,1: Maskable interrupt" bitfld.byte 0x0 0.--1. "IDTSEL,Voltage Monitor m Interrupt Generation Condition Select" "0,1,2,3" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0xE1)++0x0 line.byte 0x0 "PVD$1SR,Voltage Monitor %s Circuit Status Register" bitfld.byte 0x0 1. "MON,Voltage Monitor 1 Signal Monitor Flag" "0,1" bitfld.byte 0x0 0. "DET,Voltage Monitor m Voltage Change Detection Flag" "0,1" repeat.end group.byte 0x110++0x0 line.byte 0x0 "PDCTRGD,Graphics Power Domain Control Register" rbitfld.byte 0x0 7. "PDPGSF,Power gating status flag" "0: Target domain is power on (not gating),1: Target domain is power off (during Gating)" rbitfld.byte 0x0 6. "PDCSF,Power control status flag" "0: Power gating control is not executed (idle),1: Power gating control is in progress" newline bitfld.byte 0x0 0. "PDDE,Power control enable" "0: Power on the target domain,1: Power off the target domain" group.word 0x140++0x1 line.word 0x0 "PDRAMSCR0,SRAM Power Domain Standby Control Register 0" bitfld.word 0x0 6. "RKEEP6,RAM Retention" "0: When entering the Software Standby mode the..,1: When entering the Software Standby mode the.." bitfld.word 0x0 5. "RKEEP5,RAM Retention" "0: When entering the Software Standby mode the..,1: When entering the Software Standby mode the.." newline bitfld.word 0x0 4. "RKEEP4,RAM Retention" "0: When entering the Software Standby mode the..,1: When entering the Software Standby mode the.." bitfld.word 0x0 3. "RKEEP3,RAM Retention" "0: When entering the Software Standby mode the..,1: When entering the Software Standby mode the.." newline bitfld.word 0x0 2. "RKEEP2,RAM Retention" "0: When entering the Software Standby mode the..,1: When entering the Software Standby mode the.." bitfld.word 0x0 1. "RKEEP1,Unnecessary Circuit Retention" "0: When entering the Software Standby mode the..,1: When entering the Software Standby mode the.." newline bitfld.word 0x0 0. "RKEEP0,Unnecessary Circuit Retention" "0: When entering the Software Standby mode the..,1: When entering the Software Standby mode the.." group.byte 0x142++0x0 line.byte 0x0 "PDRAMSCR1,SRAM Power Domain Standby Control Register 1" bitfld.byte 0x0 0. "RKEEP0,RAM Retention" "0: When entering the CPU Deep Sleep and Software..,1: When entering the CPU Deep Sleep and Software.." group.word 0x3B0++0x1 line.word 0x0 "VBRSABAR,VBATT Backup Register Security Attribute Boundary Address Register" hexmask.word 0x0 0.--15. 1. "SABA,Boundary address between secure and non-secure" group.word 0x3B4++0x1 line.word 0x0 "VBRPABARS,VBATT Backup Register Privilege Attribute Boundary Address Register for Secure Region" hexmask.word 0x0 0.--15. 1. "PABAS,Boundary address between privileged and unprivileged." group.long 0x3C0++0x13 line.long 0x0 "CGFSAR,Clock Generation Function Security Attribute Register" bitfld.long 0x0 26. "NONSEC26,Non Secure Attribute bit 26" "0: Secure,1: Non Secure" bitfld.long 0x0 22. "NONSEC22,Non Secure Attribute bit 22" "0: Secure,1: Non Secure" newline bitfld.long 0x0 21. "NONSEC21,Non Secure Attribute bit 21" "0: Secure,1: Non Secure" bitfld.long 0x0 18. "NONSEC18,Non Secure Attribute bit 18" "0: Secure,1: Non Secure" newline bitfld.long 0x0 17. "NONSEC17,Non Secure Attribute bit 17" "0: Secure,1: Non Secure" bitfld.long 0x0 16. "NONSEC16,Non Secure Attribute bit 16" "0: Secure,1: Non Secure" newline bitfld.long 0x0 13. "NONSEC13,Non Secure Attribute bit 13" "0: Secure,1: Non Secure" bitfld.long 0x0 12. "NONSEC12,Non Secure Attribute bit 12" "0: Secure,1: Non Secure" newline bitfld.long 0x0 11. "NONSEC11,Non Secure Attribute bit 11" "0: Secure,1: Non Secure" bitfld.long 0x0 9. "NONSEC09,Non Secure Attribute bit 09" "0: Secure,1: Non Secure" newline bitfld.long 0x0 8. "NONSEC08,Non Secure Attribute bit 08" "0: Secure,1: Non Secure" bitfld.long 0x0 7. "NONSEC07,Non Secure Attribute bit 07" "0: Secure,1: Non Secure" newline bitfld.long 0x0 6. "NONSEC06,Non Secure Attribute bit 06" "0: Secure,1: Non Secure" bitfld.long 0x0 5. "NONSEC05,Non Secure Attribute bit 05" "0: Secure,1: Non Secure" newline bitfld.long 0x0 4. "NONSEC04,Non Secure Attribute bit 04" "0: Secure,1: Non Secure" bitfld.long 0x0 3. "NONSEC03,Non Secure Attribute bit 03" "0: Secure,1: Non Secure" newline bitfld.long 0x0 2. "NONSEC02,Non Secure Attribute bit 02" "0: Secure,1: Non Secure" bitfld.long 0x0 0. "NONSEC00,Non Secure Attribute bit 00" "0: Secure,1: Non Secure" line.long 0x4 "RSTSAR,Reset Security Attribution Register" bitfld.long 0x4 2. "NONSEC2,Non-secure Attribute bit 2" "0: Secure,1: Non-secure" bitfld.long 0x4 1. "NONSEC1,Non-secure Attribute bit 1" "0: Secure,1: Non-secure" newline bitfld.long 0x4 0. "NONSEC0,Non-secure Attribute bit 0" "0: Secure,1: Non-secure" line.long 0x8 "LPMSAR,Low Power Mode Security Attribution Register" bitfld.long 0x8 21. "NONSEC21,Non-secure Attribute bit 21" "0: Secure,1: Non-secure" bitfld.long 0x8 19. "NONSEC19,Non-secure Attribute bit 19" "0: Secure,1: Non-secure" newline bitfld.long 0x8 18. "NONSEC18,Non-secure Attribute bit 18" "0: Secure,1: Non-secure" bitfld.long 0x8 17. "NONSEC17,Non-secure Attribute bit 17" "0: Secure,1: Non-secure" newline bitfld.long 0x8 8. "NONSEC8,Non-secure Attribute bit 8" "0: Secure,1: Non-secure" bitfld.long 0x8 2. "NONSEC2,Non-secure Attribute bit 2" "0: Secure,1: Non-secure" newline bitfld.long 0x8 1. "NONSEC1,Non-secure Attribute bit 1" "0: Secure,1: Non-secure" bitfld.long 0x8 0. "NONSEC0,Non-secure Attribute bit 0" "0: Secure,1: Non-secure" line.long 0xC "PVDSAR,Programable Voltage Detection Security Attribution Register" bitfld.long 0xC 1. "NONSEC1,Non Secure Attribute bit 1" "0: Secure,1: Non Secure" bitfld.long 0xC 0. "NONSEC0,Non Secure Attribute bit 0" "0: Secure,1: Non Secure" line.long 0x10 "BBFSAR,Battery Backup Function Security Attribute Register" bitfld.long 0x10 4. "NONSEC4,Non Secure Attribute bit 4" "0: Secure,1: Non Secure" bitfld.long 0x10 3. "NONSEC3,Non Secure Attribute bit 3" "0: Secure,1: Non Secure" newline bitfld.long 0x10 2. "NONSEC2,Non Secure Attribute bit 2" "0: Secure,1: Non Secure" bitfld.long 0x10 1. "NONSEC1,Non Secure Attribute bit 1" "0: Secure,1: Non Secure" newline bitfld.long 0x10 0. "NONSEC0,Non Secure Attribute bit 0" "0: Secure,1: Non Secure" group.long 0x3D8++0x3 line.long 0x0 "PGCSAR,Power Gating Control Security Attribution Register" bitfld.long 0x0 1. "NONSEC1,Non-secure Attribute bit 1" "0: Secure,1: Non-secure" group.long 0x3E0++0x7 line.long 0x0 "DPFSAR,Deep Software Standby Interrupt Factor Security Attribution Register" bitfld.long 0x0 31. "DPFSA31,Deep Software Standby Interrupt Factor Security Attribute bit 31" "0: Secure,1: Non-secure" bitfld.long 0x0 29. "DPFSA29,Deep Software Standby Interrupt Factor Security Attribute bit 29" "0: Secure,1: Non-secure" newline bitfld.long 0x0 27. "DPFSA27,Deep Software Standby Interrupt Factor Security Attribute bit 27" "0: Secure,1: Non-secure" bitfld.long 0x0 26. "DPFSA26,Deep Software Standby Interrupt Factor Security Attribute bit 26" "0: Secure,1: Non-secure" newline bitfld.long 0x0 24. "DPFSA24,Deep Software Standby Interrupt Factor Security Attribute bit 24" "0: Secure,1: Non-secure" bitfld.long 0x0 20. "DPFSA20,Deep Software Standby Interrupt Factor Security Attribute bit 20" "0: Secure,1: Non-secure" newline bitfld.long 0x0 19. "DPFSA19,Deep Software Standby Interrupt Factor Security Attribute bit 19" "0: Secure,1: Non-secure" bitfld.long 0x0 18. "DPFSA18,Deep Software Standby Interrupt Factor Security Attribute bit 18" "0: Secure,1: Non-secure" newline bitfld.long 0x0 17. "DPFSA17,Deep Software Standby Interrupt Factor Security Attribute bit 17" "0: Secure,1: Non-secure" bitfld.long 0x0 16. "DPFSA16,Deep Software Standby Interrupt Factor Security Attribute bit 16" "0: Secure,1: Non-secure" newline bitfld.long 0x0 15. "DPFSA15,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)" "0: Secure,1: Non-secure" bitfld.long 0x0 14. "DPFSA14,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)" "0: Secure,1: Non-secure" newline bitfld.long 0x0 13. "DPFSA13,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)" "0: Secure,1: Non-secure" bitfld.long 0x0 12. "DPFSA12,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)" "0: Secure,1: Non-secure" newline bitfld.long 0x0 11. "DPFSA11,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)" "0: Secure,1: Non-secure" bitfld.long 0x0 10. "DPFSA10,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)" "0: Secure,1: Non-secure" newline bitfld.long 0x0 9. "DPFSA09,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)" "0: Secure,1: Non-secure" bitfld.long 0x0 8. "DPFSA08,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)" "0: Secure,1: Non-secure" newline bitfld.long 0x0 7. "DPFSA7,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)" "0: Secure,1: Non-secure" bitfld.long 0x0 6. "DPFSA6,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)" "0: Secure,1: Non-secure" newline bitfld.long 0x0 5. "DPFSA5,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)" "0: Secure,1: Non-secure" bitfld.long 0x0 4. "DPFSA4,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)" "0: Secure,1: Non-secure" newline bitfld.long 0x0 3. "DPFSA3,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)" "0: Secure,1: Non-secure" bitfld.long 0x0 2. "DPFSA2,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)" "0: Secure,1: Non-secure" newline bitfld.long 0x0 1. "DPFSA1,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)" "0: Secure,1: Non-secure" bitfld.long 0x0 0. "DPFSA0,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)" "0: Secure,1: Non-secure" line.long 0x4 "RSCSAR,RAM Standby Control Security Attribution Register" bitfld.long 0x4 16. "RSCSA16,RAM Standby Control Security Attribute bit n (n = 16)" "0: Secure,1: Non-secure" bitfld.long 0x4 6. "RSCSA6,RAM Standby Control Security Attribute bit n (n = 2 to 6)" "0: Secure,1: Non-secure" newline bitfld.long 0x4 5. "RSCSA5,RAM Standby Control Security Attribute bit n (n = 2 to 6)" "0: Secure,1: Non-secure" bitfld.long 0x4 4. "RSCSA4,RAM Standby Control Security Attribute bit n (n = 2 to 6)" "0: Secure,1: Non-secure" newline bitfld.long 0x4 3. "RSCSA3,RAM Standby Control Security Attribute bit n (n = 2 to 6)" "0: Secure,1: Non-secure" bitfld.long 0x4 2. "RSCSA2,RAM Standby Control Security Attribute bit n (n = 2 to 6)" "0: Secure,1: Non-secure" newline bitfld.long 0x4 1. "RSCSA1,Unnecessary Circuit Control Security Attribution bit n (n = 0 to 1)" "0: Secure,1: Non-secure" bitfld.long 0x4 0. "RSCSA0,Unnecessary Circuit Control Security Attribution bit n (n = 0 to 1)" "0: Secure,1: Non-secure" group.word 0x3FA++0x1 line.word 0x0 "PRCR_S,Protect Register for Secure (PRCR_S)" hexmask.word.byte 0x0 8.--15. 1. "PRKEY,0xA5: Enables writing to the PRCR_S register." bitfld.word 0x0 5. "PRC5" "0: Disable writes,1: Enable writes" newline bitfld.word 0x0 4. "PRC4" "0: Disable writes,1: Enable writes" bitfld.word 0x0 3. "PRC3,Enable writing to the registers related to the PVD" "0: Disable writes,1: Enable writes" newline bitfld.word 0x0 1. "PRC1,Enable writing to the registers related to the low power modes and the battery backup function" "0: Disable writes,1: Enable writes" bitfld.word 0x0 0. "PRC0,Enable writing to the registers related to the clock generation circuit" "0: Disable writes,1: Enable writes" group.byte 0x400++0x0 line.byte 0x0 "LOCOCR,Low-Speed On-Chip Oscillator Control Register" bitfld.byte 0x0 0. "LCSTP,LOCO Stop" "0: Operate the LOCO clock,1: Stop the LOCO clock" group.byte 0x402++0x0 line.byte 0x0 "LOCOUTCR,LOCO User Trimming Control Register" hexmask.byte 0x0 0.--7. 1. "LOCOUTRM,LOCO User Trimming" group.byte 0xA00++0x0 line.byte 0x0 "DPSBYCR,Deep Software Standby Control Register" bitfld.byte 0x0 6. "IOKEEP,I/O Port Rentention" "0: When the Deep Software Standby mode is canceled..,1: When the Deep Software Standby mode is canceled.." bitfld.byte 0x0 4. "SRKEEP,Standby SRAM Retention" "0: When entering the Software Standby mode or the..,1: When entering the Software Standby mode or the.." newline bitfld.byte 0x0 2. "DCSSMODE" "0: When the Deep Software Standby mode is canceled..,1: When the Deep Software Standby mode is canceled.." group.byte 0xA04++0x0 line.byte 0x0 "DPSWCR,Deep Software Standby Wait Control Register" hexmask.byte 0x0 0.--7. 1. "WTSTS,Deep Software Wait Standby Time Setting Bit" group.byte 0xA08++0x0 line.byte 0x0 "DPSIER0,Deep Software Standby Interrupt Enable Register 0" bitfld.byte 0x0 7. "DIRQ7E,IRQ7-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 6. "DIRQ6E,IRQ6-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 5. "DIRQ5E,IRQ5-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 4. "DIRQ4E,IRQ4-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 3. "DIRQ3E,IRQ3-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 2. "DIRQ2E,IRQ2-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 1. "DIRQ1E,IRQ1-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 0. "DIRQ0E,IRQ0-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" group.byte 0xA0C++0x0 line.byte 0x0 "DPSIER1,Deep Software Standby Interrupt Enable Register 1" bitfld.byte 0x0 7. "DIRQ15E,IRQ15-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 6. "DIRQ14E,IRQ14-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 5. "DIRQ13E,IRQ13-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 4. "DIRQ12E,IRQ12-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 3. "DIRQ11E,IRQ11-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 2. "DIRQ10E,IRQ10-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 1. "DIRQ9E,IRQ9-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 0. "DIRQ8E,IRQ8-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" group.byte 0xA10++0x0 line.byte 0x0 "DPSIER2,Deep Software Standby Interrupt Enable Register 2" bitfld.byte 0x0 4. "DNMIE,NMI Pin Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 3. "DRTCAIE,RTC Alarm interrupt Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 2. "DRTCIIE,RTC Interval interrupt Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 1. "DPVD2IE,PVD2 Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 0. "DPVD1IE,PVD1 Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" group.byte 0xA14++0x0 line.byte 0x0 "DPSIER3,Deep Software Standby Interrupt Enable Register 3" bitfld.byte 0x0 7. "DVBATTADIE,VBATT Tamper Detection Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 5. "DIWDTIE,IWDT Underflow Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 3. "DULPT1IE,ULPT1 Overflow Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 2. "DULPT0IE,ULPT0 Overflow Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 0. "DUSBFSIE,USBFS Suspend/Resume Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" group.byte 0xA18++0x0 line.byte 0x0 "DPSIFR0,Deep Software Standby Interrupt Flag Register 0" bitfld.byte 0x0 7. "DIRQ7F,IRQ7-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 6. "DIRQ6F,IRQ6-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 5. "DIRQ5F,IRQ5-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 4. "DIRQ4F,IRQ4-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 3. "DIRQ3F,IRQ3-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 2. "DIRQ2F,IRQ2-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 1. "DIRQ1F,IRQ1-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 0. "DIRQ0F,IRQ0-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" group.byte 0xA1C++0x0 line.byte 0x0 "DPSIFR1,Deep Software Standby Interrupt Flag Register 1" bitfld.byte 0x0 7. "DIRQ15F,IRQ15-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 6. "DIRQ14F,IRQ14-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 5. "DIRQ13F,IRQ13-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 4. "DIRQ12F,IRQ12-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 3. "DIRQ11F,IRQ11-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 2. "DIRQ10F,IRQ10-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 1. "DIRQ9F,IRQ9-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 0. "DIRQ8F,IRQ8-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" group.byte 0xA20++0x0 line.byte 0x0 "DPSIFR2,Deep Software Standby Interrupt Flag Register 2" bitfld.byte 0x0 4. "DNMIF,NMI Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 3. "DRTCAIF,RTC Alarm Interrupt Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 2. "DRTCIIF,RTC Interval Interrupt Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 1. "DPVD2IF,PVD2 Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 0. "DPVD1IF,PVD1 Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" group.byte 0xA24++0x0 line.byte 0x0 "DPSIFR3,Deep Software Standby Interrupt Flag Register 3" bitfld.byte 0x0 7. "DVBATTADIF,VBATT Tamper Detection Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 5. "DIWDTIF,IWDT Underflow Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 3. "DULPT1IF,ULPT1 Overflow Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 2. "DULPT0IF,ULPT0 Overflow Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 0. "DUSBFSIF,USBFS Suspend/Resume Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" group.byte 0xA28++0x0 line.byte 0x0 "DPSIEGR0,Deep Software Standby Interrupt Edge Register 0" bitfld.byte 0x0 7. "DIRQ7EG,IRQ7-DS Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" bitfld.byte 0x0 6. "DIRQ6EG,IRQ6-DS Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" newline bitfld.byte 0x0 5. "DIRQ5EG,IRQ5-DS Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" bitfld.byte 0x0 4. "DIRQ4EG,IRQ4-DS Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" newline bitfld.byte 0x0 3. "DIRQ3EG,IRQ3-DS Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" bitfld.byte 0x0 2. "DIRQ2EG,IRQ2-DS Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" newline bitfld.byte 0x0 1. "DIRQ1EG,IRQ1-DS Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" bitfld.byte 0x0 0. "DIRQ0EG,IRQ0-DS Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" group.byte 0xA2C++0x0 line.byte 0x0 "DPSIEGR1,Deep Software Standby Interrupt Edge Register 1" bitfld.byte 0x0 7. "DIRQ15EG,IRQ15-DS Pin Edge Select" "0: A cancel request is generated at a falling edge.,1: A cancel request is generated at a rising edge." bitfld.byte 0x0 6. "DIRQ14EG,IRQ14-DS Pin Edge Select" "0: A cancel request is generated at a falling edge.,1: A cancel request is generated at a rising edge." newline bitfld.byte 0x0 5. "DIRQ13EG,IRQ13-DS Pin Edge Select" "0: A cancel request is generated at a falling edge.,1: A cancel request is generated at a rising edge." bitfld.byte 0x0 4. "DIRQ12EG,IRQ12-DS Pin Edge Select" "0: A cancel request is generated at a falling edge.,1: A cancel request is generated at a rising edge." newline bitfld.byte 0x0 3. "DIRQ11EG,IRQ11-DS Pin Edge Select" "0: A cancel request is generated at a falling edge.,1: A cancel request is generated at a rising edge." bitfld.byte 0x0 2. "DIRQ10EG,IRQ10-DS Pin Edge Select" "0: A cancel request is generated at a falling edge.,1: A cancel request is generated at a rising edge" newline bitfld.byte 0x0 1. "DIRQ9EG,IRQ9-DS Pin Edge Select" "0: A cancel request is generated at a falling edge.,1: A cancel request is generated at a rising edge." bitfld.byte 0x0 0. "DIRQ8EG,IRQ8-DS Pin Edge Select" "0: A cancel request is generated at a falling edge.,1: A cancel request is generated at a rising edge." group.byte 0xA30++0x0 line.byte 0x0 "DPSIEGR2,Deep Software Standby Interrupt Edge Register 2" bitfld.byte 0x0 4. "DNMIEG,NMI Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" bitfld.byte 0x0 1. "DPVD2EG,PVD2 Edge Select" "0: A cancel request is generated when VCC < Vdet2..,1: A cancel request is generated when VCC ≥ Vdet2.." newline bitfld.byte 0x0 0. "DPVD1EG,PVD1 Edge Select" "0: A cancel request is generated when VCC < Vdet1..,1: A cancel request is generated when VCC ≥ Vdet1.." group.byte 0xA38++0x0 line.byte 0x0 "SYOCDCR,System Control OCD Control Register" bitfld.byte 0x0 7. "DBGEN,Debugger Enable bit" "0: On-chip debugger is disabled,1: On-chip debugger is enabled" group.byte 0xA40++0x0 line.byte 0x0 "RSTSR0,Reset Status Register 0" bitfld.byte 0x0 7. "DPSRSTF,Deep Software Standby Reset Flag" "0: Deep Software Standby mode cancellation not..,1: Deep Software Standby mode cancellation.." bitfld.byte 0x0 3. "PVD2RF,Voltage Monitor 2 Reset Detect Flag" "0: Voltage monitor 2 reset not detected,1: Voltage monitor 2 reset detected" newline bitfld.byte 0x0 2. "PVD1RF,Voltage Monitor 1 Reset Detect Flag" "0: Voltage monitor 1 reset not detected,1: Voltage monitor 1 reset detected" bitfld.byte 0x0 1. "PVD0RF,Voltage Monitor 0 Reset Detect Flag" "0: Voltage monitor 0 reset not detected,1: Voltage monitor 0 reset detected" newline bitfld.byte 0x0 0. "PORF,Power-On Reset Detect Flag" "0: Power-on reset not detected,1: Power-on reset detected" group.byte 0xA44++0x0 line.byte 0x0 "RSTSR2,Reset Status Register 2" bitfld.byte 0x0 0. "CWSF,Cold/Warm Start Determination Flag" "0: Cold start,1: Warm start" group.byte 0xA50++0x0 line.byte 0x0 "MOMCR,Main Clock Oscillator Mode Oscillation Control Register" bitfld.byte 0x0 6. "MOSEL,Main Clock Oscillator Switching" "0: Resonator,1: External clock input" bitfld.byte 0x0 1.--3. "MODRV0,Main Clock Oscillator Drive Capability 0 Switching" "0: Setting prohibited,?,?,?,?,?,?,?" group.byte 0xA54++0x0 line.byte 0x0 "FWEPROR,Flash P/E Protect Register" bitfld.byte 0x0 0.--1. "FLWE,Flash Programming and Erasure" "0: Prohibits Program Block Erase Multi Block Erase..,1: Permits Program Block Erase Multi Block Erase..,?,?" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0xA58)++0x0 line.byte 0x0 "PVD$1CMPCR,Voltage Monitor %s Comparator Control Register" bitfld.byte 0x0 7. "PVDE,Voltage Detection m Enable" "0: Voltage detection m circuit disabled,1: Voltage detection m circuit enabled" hexmask.byte 0x0 0.--4. 1. "PVDLVL,Detection Voltage m Level Select" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0xA70)++0x0 line.byte 0x0 "PVD$1CR0,Voltage Monitor %s Circuit Control Register 0" bitfld.byte 0x0 7. "RN,Voltage Monitor m Reset Negate Select" "0,1" bitfld.byte 0x0 6. "RI,Voltage Monitor m Circuit Mode Select" "0,1" newline bitfld.byte 0x0 4.--5. "FSAMP,Sampling Clock Select" "0: 1/2 LOCO frequency,1: 1/4 LOCO frequency,?,?" bitfld.byte 0x0 2. "CMPE,Voltage Monitor m Circuit Comparison Result Output Enable" "0: Voltage monitor m circuit comparison result..,1: Voltage monitor m circuit comparison result.." newline bitfld.byte 0x0 1. "DFDIS,Voltage monitor m Digital Filter Disabled Mode Select" "0: Enable the digital filter,1: Disable the digital filter" bitfld.byte 0x0 0. "RIE,Voltage Monitor m Interrupt/Reset Enable" "0: Disable,1: Enable" repeat.end group.byte 0xA84++0x0 line.byte 0x0 "VBATTMNSELR,Battery Backup Voltage Monitor Function Select Register" bitfld.byte 0x0 0. "VBTMNSEL,VBATT Voltage Monitor Function Select Bit" "0: Disables VBATT voltage monitor function,1: Enables VBATT voltage monitor function" group.byte 0xA88++0x0 line.byte 0x0 "VBTBPCR1,VBATT Battery Power Supply Control Register 1" bitfld.byte 0x0 0. "BPWSWSTP,Battery Power Supply Switch Stop" "0: Battery power supply switch enable,1: Battery power supply switch stop" group.byte 0xA90++0x0 line.byte 0x0 "LPSCR,Low Power State Control Register" hexmask.byte 0x0 0.--3. 1. "LPMD,Low power mode setting bit" group.byte 0xA98++0x0 line.byte 0x0 "SSCR1,Software Standby Control Register 1" bitfld.byte 0x0 0. "SS1FR,Software Standby Fast Return" "0: When returning from Software Standby mode fast..,1: When returning from Software Standby mode fast.." group.byte 0xAB0++0x0 line.byte 0x0 "LVOCR,Low Voltage Operation Control register" bitfld.byte 0x0 1. "LVO1E,Low Voltage Operation 1 Enable" "0: Disable,1: Enable" bitfld.byte 0x0 0. "LVO0E,Low Voltage Operation 0 Enable" "0: Disable,1: Enable" group.byte 0xAD0++0x0 line.byte 0x0 "SYRSTMSK0,System Reset Mask Control Register 0" bitfld.byte 0x0 7. "BUSMASK,Bus Error Reset Mask" "0: Reset occurrence is enabled,1: Reset occurrence is disabled" bitfld.byte 0x0 6. "CMMASK,Common Memory Error Reset Mask" "0: Reset occurrence is enabled,1: Reset occurrence is disabled" newline bitfld.byte 0x0 4. "CLU0MASK,CPU Lockup Reset Mask" "0: Reset occurrence is enabled,1: Reset occurrence is disabled" bitfld.byte 0x0 2. "SWMASK,Software Reset Mask" "0: Reset occurrence is enabled,1: Reset occurrence is disabled" newline bitfld.byte 0x0 1. "WDT0MASK,Watchdog Timer Reset Mask" "0: Reset occurrence is enabled,1: Reset occurrence is disabled" bitfld.byte 0x0 0. "IWDTMASK,Independent Watchdog Timer Reset Mask" "0: Reset occurrence is enabled,1: Reset occurrence is disabled" group.byte 0xAD8++0x0 line.byte 0x0 "SYRSTMSK2,System Reset Mask Control Register 2" bitfld.byte 0x0 1. "PVD2MASK,Voltage Monitor 2 Reset Mask" "0: Reset occurrence is enabled,1: Reset occurrence is disabled" bitfld.byte 0x0 0. "PVD1MASK,Voltage Monitor 1 Reset Mask" "0: Reset occurrence is enabled,1: Reset occurrence is disabled" group.byte 0xB04++0x0 line.byte 0x0 "PLL1LDOCR,PLL1-LDO Control Register" bitfld.byte 0x0 1. "SKEEP,STBY Keep" "0: PLL1-LDO is stopped during Software Standby mode.,1: PLL1-LDO state before Software Standby mode is.." bitfld.byte 0x0 0. "LDOSTP,LDO Stop" "0: PLL1-LDO is enabled,1: PLL1-LDO is stopped" group.byte 0xB08++0x0 line.byte 0x0 "PLL2LDOCR,PLL2-LDO Control Register" bitfld.byte 0x0 1. "SKEEP,STBY Keep" "0: PLL2-LDO is stopped during Software Standby mode.,1: PLL2-LDO state before Software Standby mode is.." bitfld.byte 0x0 0. "LDOSTP,LDO Stop" "0: PLL2-LDO is enabled,1: PLL2-LDO is stopped" group.byte 0xB0C++0x0 line.byte 0x0 "HOCOLDOCR,HOCO-LDO Control Register" bitfld.byte 0x0 1. "SKEEP,STBY Keep" "0: HOCO-LDO is stopped during Software Standby mode.,1: HOCO-LDO state before Software Standby mode is.." bitfld.byte 0x0 0. "LDOSTP,LDO Stop" "0: HOCO-LDO is enabled,1: HOCO-LDO is stopped" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0xB20)++0x0 line.byte 0x0 "PVD$1FCR,Voltage Monitor %s Function Control Register" bitfld.byte 0x0 0. "RHSEL,Rise Hysteresis Select" "0: Hysteresis level for VCC-fall detection is..,1: Hysteresis level for VCC-rise detection is.." repeat.end group.byte 0xC00++0x1 line.byte 0x0 "SOSCCR,Sub-Clock Oscillator Control Register" bitfld.byte 0x0 0. "SOSTP,Sub-Clock Oscillator Stop" "0: Operate the sub-clock oscillator,1: Stop the sub-clock oscillator" line.byte 0x1 "SOMCR,Sub-Clock Oscillator Mode Control Register" bitfld.byte 0x1 6. "SOSEL,Sub-Clock Oscillator Switching" "0: Resonator,1: External clock input" bitfld.byte 0x1 0.--1. "SODRV,Sub-Clock Oscillator Drive Capability Switching" "0: Standard (12.5pf),1: Lowpower mode 1 (9pf),?,?" group.byte 0xC40++0x0 line.byte 0x0 "VBTBER,VBATT Backup Enable Register" bitfld.byte 0x0 3. "VBAE,VBATT backup register access enable bit" "0: Disable to access VBTBKR[n],1: Enable to access VBTBKR[n]" group.byte 0xC45++0x1 line.byte 0x0 "VBTBPCR2,VBATT Battery Power Supply Control Register 2" bitfld.byte 0x0 4. "VDETE,Voltage drop detection enable" "0: VCC Voltage drop detection disable,1: VCC Voltage drop detection enable" bitfld.byte 0x0 0.--2. "VDETLVL,VDETBAT Level Select" "0: 2.80 V,1: 2.53 V,?,?,?,?,?,?" line.byte 0x1 "VBTBPSR,VBATT Battery Power Supply Status Register" rbitfld.byte 0x1 5. "BPWSWM,Battery Power Supply Switch Status Monitor" "0: VCC voltage < VDETBATT_m,1: VCC voltage > VDETBATT_m" rbitfld.byte 0x1 4. "VBPORM,VBATT_POR Monitor" "0: VBATT_R voltage < VPDR (BATR),1: VBATT_R voltage > VPDR (BATR)" newline bitfld.byte 0x1 0. "VBPORF,VBATT_POR Flag" "0: VBATT_R voltage drop is not detected,1: VBATT_R voltage drop is detected" group.byte 0xC48++0x2 line.byte 0x0 "VBTADSR,VBATT Tamper detection Status Register" bitfld.byte 0x0 2. "VBTADF2,VBATT Tamper Detection flag 2" "0: RTCIC2 input edge is not detected,1: RTCIC2 input edge is detected" bitfld.byte 0x0 1. "VBTADF1,VBATT Tamper Detection flag 1" "0: RTCIC1 input edge is not detected,1: RTCIC1 input edge is detected" newline bitfld.byte 0x0 0. "VBTADF0,VBATT Tamper Detection flag 0" "0: RTCIC0 input edge is not detected,1: RTCIC0 input edge is detected" line.byte 0x1 "VBTADCR1,VBATT Tamper detection Control Register 1" bitfld.byte 0x1 6. "VBTADCE2,VBATT Tamper Detection Backup Register Clear Enable 2" "0: Clear Backup Register by VBTADF2 flag is disable,1: Clear Backup Register by VBTADF2 flag is enable" bitfld.byte 0x1 5. "VBTADCE1,VBATT Tamper Detection Backup Register Clear Enable 1" "0: Clear Backup Register by VBTADF1 flag is disable,1: Clear Backup Register by VBTADF1 flag is enable" newline bitfld.byte 0x1 4. "VBTADCE0,VBATT Tamper Detection Backup Register Clear Enable 0" "0: Clear Backup Register by VBTADF0 flag is disable,1: Clear Backup Register by VBTADF0 flag is enable" bitfld.byte 0x1 2. "VBTADIE2,VBATT Tamper Detection Interrupt Enable 2" "0: Interrupt by VBTADF2 flag is disable,1: Interrupt by VBTADF2 flag is enable" newline bitfld.byte 0x1 1. "VBTADIE1,VBATT Tamper Detection Interrupt Enable 1" "0: Interrupt by VBTADF1 flag is disable,1: Interrupt by VBTADF1 flag is enable" bitfld.byte 0x1 0. "VBTADIE0,VBATT Tamper Detection Interrupt Enable 0" "0: Interrupt by VBTADF0 flag is disable,1: Interrupt by VBTADF0 flag is enable" line.byte 0x2 "VBTADCR2,VBATT Tamper detection Control Register 2" bitfld.byte 0x2 2. "VBRTCES2,VBATT RTC Time Capture Event Source Select 2" "0: RTCIC2,1: VBTADF2" bitfld.byte 0x2 1. "VBRTCES1,VBATT RTC Time Capture Event Source Select 1" "0: RTCIC1,1: VBTADF1" newline bitfld.byte 0x2 0. "VBRTCES0,VBATT RTC Time Capture Event Source Select 0" "0: RTCIC0,1: VBTADF0" group.byte 0xC4C++0x1 line.byte 0x0 "VBTICTLR,VBATT Input Control Register" bitfld.byte 0x0 2. "VCH2INEN,VBATT CH2 Input Enable" "0: RTCIC2 input disable,1: RTCIC2 input enable" bitfld.byte 0x0 1. "VCH1INEN,VBATT CH1 Input Enable" "0: RTCIC1 input disable,1: RTCIC1 input enable" newline bitfld.byte 0x0 0. "VCH0INEN,VBATT CH0 Input Enable" "0: RTCIC0 input disable,1: RTCIC0 input enable" line.byte 0x1 "VBTICTLR2,VBATT Input Control Register 2" bitfld.byte 0x1 6. "VCH2EG,VBATT CH2 Input Edge Select" "0: RTCIC2 pin input event is detected on falling edge,1: RTCIC2 pin input event is detected on rising edge" bitfld.byte 0x1 5. "VCH1EG,VBATT CH1 Input Edge Select" "0: RTCIC1 pin input event is detected on falling edge,1: RTCIC1 pin input event is detected on rising edge" newline bitfld.byte 0x1 4. "VCH0EG,VBATT CH0 Input Edge Select" "0: RTCIC0 pin input event is detected on falling edge,1: RTCIC0 pin input event is detected on rising edge" bitfld.byte 0x1 2. "VCH2NCE,VBATT CH2 Input Noise Canceler Enable" "0: RTCIC2 pin input noise canceler disable,1: RTCIC2 pin input noise canceler enable" newline bitfld.byte 0x1 1. "VCH1NCE,VBATT CH1 Input Noise Canceler Enable" "0: RTCIC1 pin input noise canceler disable,1: RTCIC1 pin input noise canceler enable" bitfld.byte 0x1 0. "VCH0NCE,VBATT CH0 Input Noise Canceler Enable" "0: RTCIC0 pin input noise canceler disable,1: RTCIC0 pin input noise canceler enable" rgroup.byte 0xC4E++0x0 line.byte 0x0 "VBTIMONR,VBATT Input Monitor Register" bitfld.byte 0x0 2. "VCH2MON,VBATT CH2 Input monitor" "0: RTCIC2 pin input is low level,1: RTCIC2 pin input is high level." bitfld.byte 0x0 1. "VCH1MON,VBATT CH1 Input monitor" "0: RTCIC1 pin input is low level,1: RTCIC1 pin input is high level" newline bitfld.byte 0x0 0. "VCH0MON,VBATT CH0 Input monitor" "0: RTCIC0 pin input is low level,1: RTCIC0 pin input is high level." repeat 128. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0xD00)++0x0 line.byte 0x0 "VBTBKR[$1],VBATT Backup Register" repeat.end tree.end tree "SYSC_NS" base ad:0x5001E000 group.byte 0xC++0x0 line.byte 0x0 "SBYCR,Standby Control Register" bitfld.byte 0x0 6. "OPE,Output Port Enable" "0: In Software Standby mode or Deep Software..,1: In Software Standby mode or Deep Software.." group.long 0x20++0x3 line.long 0x0 "SCKDIVCR,System Clock Division Control Register" hexmask.long.byte 0x0 28.--31. 1. "FCK,FlashIF Clock (FCLK) Select" hexmask.long.byte 0x0 24.--27. 1. "ICK,System Clock (ICLK) Select" newline hexmask.long.byte 0x0 16.--19. 1. "BCK,External Bus Clock (BCLK) Select" hexmask.long.byte 0x0 12.--15. 1. "PCKA,Peripheral Module Clock A (PCLKA) Select" newline hexmask.long.byte 0x0 8.--11. 1. "PCKB,Peripheral Module Clock B (PCLKB) Select" hexmask.long.byte 0x0 4.--7. 1. "PCKC,Peripheral Module Clock C (PCLKC) Select" newline hexmask.long.byte 0x0 0.--3. 1. "PCKD,Peripheral Module Clock D (PCLKD) Select" group.byte 0x24++0x0 line.byte 0x0 "SCKDIVCR2,System Clock Division Control Register 2" hexmask.byte 0x0 0.--3. 1. "CPUCK,CPU Clock (CPUCLK) Select" group.byte 0x26++0x0 line.byte 0x0 "SCKSCR,System Clock Source Control Register" bitfld.byte 0x0 0.--2. "CKSEL,Clock Source Select" "0: HOCO,1: MOCO (Value after reset),?,?,?,?,?,?" group.word 0x28++0x1 line.word 0x0 "PLLCCR,PLL Clock Control Register" hexmask.word.byte 0x0 8.--15. 1. "PLLMUL,PLL1 Frequency Multiplication Factor Select" bitfld.word 0x0 6.--7. "PLLMULNF,PLL1 Frequency Multiplication Fractional Factor Select" "0: 0.00 (Value after reset),1: 0.33 (1/3),?,?" newline bitfld.word 0x0 4. "PLSRCSEL,PLL1 Clock Source Select" "0: Main clock oscillator,1: HOCO" bitfld.word 0x0 0.--1. "PLIDIV,PLL1 Input Frequency Division Ratio Select" "0: 1/1,1: 1/2,?,?" group.byte 0x2A++0x0 line.byte 0x0 "PLLCR,PLL Control Register" bitfld.byte 0x0 0. "PLLSTP,PLL1 Stop Control" "0: PLL1 is operating,1: PLL1 is stopped" group.byte 0x30++0x0 line.byte 0x0 "BCKCR,External Bus Clock Control Register" bitfld.byte 0x0 0. "BCLKDIV,BCLK Pin Output Select" "0: BCLK,1: BCLK/2" group.byte 0x32++0x0 line.byte 0x0 "MOSCCR,Main Clock Oscillator Control Register" bitfld.byte 0x0 0. "MOSTP,Main Clock Oscillator Stop" "0: Operate the main clock oscillator,1: Stop the main clock oscillator" group.byte 0x36++0x3 line.byte 0x0 "HOCOCR,High-Speed On-Chip Oscillator Control Register" bitfld.byte 0x0 0. "HCSTP,HOCO Stop" "0: Operate the HOCO clock,1: Stop the HOCO clock" line.byte 0x1 "HOCOCR2,High-Speed On-Chip Oscillator Control Register2" bitfld.byte 0x1 0.--2. "HCFRQ0,HOCO Frequency Setting 0" "0: 16MHz,1: 18MHz,?,?,?,?,?,?" line.byte 0x2 "MOCOCR,Middle-Speed On-Chip Oscillator Control Register" bitfld.byte 0x2 0. "MCSTP,MOCO Stop" "0: MOCO clock is operating,1: MOCO clock is stopped" line.byte 0x3 "FLLCR1,FLL Control Register1" bitfld.byte 0x3 0. "FLLEN,FLL Enable" "0: FLL function is disabled,1: FLL function is enabled." group.word 0x3A++0x1 line.word 0x0 "FLLCR2,FLL Control Register2" hexmask.word 0x0 0.--10. 1. "FLLCNTL,FLL Multiplication Control" rgroup.byte 0x3C++0x0 line.byte 0x0 "OSCSF,Oscillation Stabilization Flag Register" bitfld.byte 0x0 6. "PLL2SF,PLL2 Clock Oscillation Stabilization Flag" "0: The PLL2 clock is stopped or is not yet stable.,1: The PLL2 clock is stable" bitfld.byte 0x0 5. "PLLSF,PLL1 Clock Oscillation Stabilization Flag" "0: The PLL1 clock is stopped or is not yet stable.,1: The PLL1 clock is stable so is available for use.." newline bitfld.byte 0x0 3. "MOSCSF,Main Clock Oscillation Stabilization Flag" "0: The main clock oscillator is stopped or is not..,1: The main clock oscillator is stable so is.." bitfld.byte 0x0 0. "HOCOSF,HOCO Clock Oscillation Stabilization Flag" "0: The HOCO clock is stopped or is not yet stable,1: The HOCO clock is stable so is available for use.." group.byte 0x3E++0x3 line.byte 0x0 "CKOCR,Clock Out Control Register" bitfld.byte 0x0 7. "CKOEN,Clock Out Enable" "0: Disable clock out,1: Enable clock out" bitfld.byte 0x0 4.--6. "CKODIV,Clock Output Frequency Division Ratio" "0: x 1/1,1: x 1/2,?,?,?,?,?,?" newline bitfld.byte 0x0 0.--2. "CKOSEL,Clock Out Source Select" "0: Setting prohibited,1: MOCO (Value after reset),?,?,?,?,?,?" line.byte 0x1 "TRCKCR,Trace Clock Control Register" bitfld.byte 0x1 7. "TRCKEN,Trace Clock operating Enable" "0: Stop,1: Operation enable" bitfld.byte 0x1 4. "TRCKSEL,Trace Clock source select" "0: System clock source (Value after reset),1: HOCO (oscillation in debug mode)" newline hexmask.byte 0x1 0.--3. 1. "TRCK,Trace Clock operating frequency select" line.byte 0x2 "OSTDCR,Oscillation Stop Detection Control Register" bitfld.byte 0x2 7. "OSTDE,Oscillation Stop Detection Function Enable" "0: Disable oscillation stop detection function,1: Enable oscillation stop detection function" bitfld.byte 0x2 0. "OSTDIE,Oscillation Stop Detection Interrupt Enable" "0: Disable oscillation stop detection interrupt (do..,1: Enable oscillation stop detection interrupt.." line.byte 0x3 "OSTDSR,Oscillation Stop Detection Status Register" bitfld.byte 0x3 0. "OSTDF,Oscillation Stop Detection Flag" "0: Main clock oscillation stop not detected,1: Main clock oscillation stop detected" rgroup.byte 0x43++0x0 line.byte 0x0 "OSCMONR,Oscillator Monitor Register" bitfld.byte 0x0 2. "LOCOMON,LOCO operation monitor" "0: LOCO is set to operate.,1: LOCO is set to stop." bitfld.byte 0x0 1. "MOCOMON,MOCO operation monitor" "0: MOCO is set to operate.,1: MOCO is set to stop." group.word 0x48++0x1 line.word 0x0 "PLL2CCR,PLL2 Clock Control Register" hexmask.word.byte 0x0 8.--15. 1. "PLL2MUL,PLL2 Frequency Multiplication Factor Select" bitfld.word 0x0 6.--7. "PLL2MULNF,PLL2 Frequency Multiplication Fractional Factor Select" "0: 0.00 (Value after reset),1: 0.33 (1/3),?,?" newline bitfld.word 0x0 4. "PL2SRCSEL,PLL2 Clock Source Select" "0: Main clock oscillator,1: HOCO" bitfld.word 0x0 0.--1. "PL2IDIV,PLL2 Input Frequency Division Ratio Select" "0: 1/1 (Value after reset),1: 1/2,?,?" group.byte 0x4A++0x0 line.byte 0x0 "PLL2CR,PLL2 Control Register" bitfld.byte 0x0 0. "PLL2STP,PLL2 Stop Control" "0: PLL2 is operating,1: PLL2 is stopped" group.word 0x4C++0x3 line.word 0x0 "PLLCCR2,PLL Clock Control Register 2" hexmask.word.byte 0x0 8.--11. 1. "PLODIVR,PLL1 Output Frequency Division Ratio Select for output clock R" hexmask.word.byte 0x0 4.--7. 1. "PLODIVQ,PLL1 Output Frequency Division Ratio Select for output clock Q" newline hexmask.word.byte 0x0 0.--3. 1. "PLODIVP,PLL1 Output Frequency Division Ratio Select for output clock P" line.word 0x2 "PLL2CCR2,PLL2 Clock Control Register 2" hexmask.word.byte 0x2 8.--11. 1. "PL2ODIVR,PLL2 Output Frequency Division Ratio Select for output clock R" hexmask.word.byte 0x2 4.--7. 1. "PL2ODIVQ,PLL2 Output Frequency Division Ratio Select for output clock Q" newline hexmask.word.byte 0x2 0.--3. 1. "PL2ODIVP,PLL2 Output Frequency Division Ratio Select for output clock P" group.byte 0x52++0x5 line.byte 0x0 "EBCKOCR,External Bus Clock Output Control Register" bitfld.byte 0x0 0. "EBCKOEN,EBCLK Pin Output Control" "0: EBCLK pin output is disabled (fixed high),1: EBCLK pin output is enabled." line.byte 0x1 "SDCKOCR,SDRAM Clock Output Control Register" bitfld.byte 0x1 0. "SDCKOEN,SDCLK Pin Output Control" "0: SDCLK pin output is disabled. (Fixed high),1: SDCLK pin output is enabled." line.byte 0x2 "SCICKDIVCR,SCI clock Division control register" bitfld.byte 0x2 0.--2. "SCICKDIV,SCI clock (SCICLK) Division Select" "0: Setting prohibited.,1: 1/2,?,?,?,?,?,?" line.byte 0x3 "SCICKCR,SCI clock control register" rbitfld.byte 0x3 7. "SCICKSRDY,SCI clock (SCICLK) Switching Ready state flag" "0: Impossible to Switch,1: Possible to Switch" bitfld.byte 0x3 6. "SCICKSREQ,SCI clock (SCICLK) Switching Request" "0: No request,1: Request switching" newline hexmask.byte 0x3 0.--3. 1. "SCICKSEL,SCI clock (SCICLK) Source Select" line.byte 0x4 "SPICKDIVCR,SPI clock Division control register" bitfld.byte 0x4 0.--2. "SPICKDIV,SPI clock (SPICLK) Division Select" "0: Setting prohibited.,1: 1/2,?,?,?,?,?,?" line.byte 0x5 "SPICKCR,SPI clock control register" rbitfld.byte 0x5 7. "SPICKSRDY,SPI clock (SPICLK) Switching Ready state flag" "0: Impossible to Switch,1: Possible to Switch" bitfld.byte 0x5 6. "SPICKSREQ,SPI clock (SPICLK) Switching Request" "0: No request,1: Request switching" newline hexmask.byte 0x5 0.--3. 1. "SPICKSEL,SPI clock (SPICLK) Source Select" group.byte 0x5E++0x1 line.byte 0x0 "LCDCKDIVCR,LCD clock Division control register" bitfld.byte 0x0 0.--2. "LCDCKDIV,LCD clock (LCDCLK) Division Select" "0: Setting prohibited.,1: 1/2,?,?,?,?,?,?" line.byte 0x1 "LCDCKCR,LCD clock control register" rbitfld.byte 0x1 7. "LCDCKSRDY,LCD clock (LCDCLK) Switching Ready state flag" "0: Impossible to Switch,1: Possible to Switch" bitfld.byte 0x1 6. "LCDCKSREQ,LCD clock (LCDCLK) Switching Request" "0: No request,1: Request switching" newline hexmask.byte 0x1 0.--3. 1. "LCDCKSEL,LCD clock (LCDCLK) Source Select" group.byte 0x61++0x1 line.byte 0x0 "MOCOUTCR,MOCO User Trimming Control Register" hexmask.byte 0x0 0.--7. 1. "MOCOUTRM,MOCO User Trimming" line.byte 0x1 "HOCOUTCR,HOCO User Trimming Control Register" hexmask.byte 0x1 0.--7. 1. "HOCOUTRM,HOCO User Trimming" group.byte 0x6C++0x2 line.byte 0x0 "USBCKDIVCR,USB Clock Division Control Register" bitfld.byte 0x0 0.--2. "USBCKDIV,USB Clock (USBCLK) Division Select" "0: Setting prohibited.,1: 1/2,?,?,?,?,?,?" line.byte 0x1 "OCTACKDIVCR,Octal-SPI Clock Division Control Register" bitfld.byte 0x1 0.--2. "OCTACKDIV,Octal-SPI Clock (OCTACLK) Division Select" "0: Setting prohibited.,1: 1/2,?,?,?,?,?,?" line.byte 0x2 "CANFDCKDIVCR,CANFD Core Clock Division Control Register" bitfld.byte 0x2 0.--2. "CANFDCKDIV,CANFD core clock (CANFDCLK) Division Select" "0: Setting prohibited,1: 1/2,?,?,?,?,?,?" group.byte 0x74++0x2 line.byte 0x0 "USBCKCR,USB Clock Control Register" rbitfld.byte 0x0 7. "USBCKSRDY,USB Clock (USBCLK) Switching Ready state flag" "0: Impossible to Switch,1: Possible to Switch" bitfld.byte 0x0 6. "USBCKSREQ,USB Clock (USBCLK) Switching Request" "0: No request,1: Request switching." newline hexmask.byte 0x0 0.--3. 1. "USBCKSEL,USB Clock (USBCLK) Source Select" line.byte 0x1 "OCTACKCR,Octal-SPI Clock Control Register" rbitfld.byte 0x1 7. "OCTACKSRDY,Octal-SPI Clock (OCTACLK) Switching Ready state flag" "0: Impossible to Switch,1: Possible to Switch" bitfld.byte 0x1 6. "OCTACKSREQ,Octal-SPI Clock (OCTACLK) Switching Request" "0: No request,1: Request switching." newline hexmask.byte 0x1 0.--3. 1. "OCTACKSEL,Octal-SPI Clock (OCTACLK) Source Select" line.byte 0x2 "CANFDCKCR,CANFD Core Clock Control Register" bitfld.byte 0x2 6. "CANFDCKSREQ,CANFD Core Clock (CANFDCLK) Switching Request" "0: No request,1: Request switching" hexmask.byte 0x2 0.--3. 1. "CANFDCKSEL,CANFD Core Clock (CANFDCLK) Source Select" group.byte 0x7C++0x1 line.byte 0x0 "MOSCSCR,Main Clock Oscillator Standby Control Register" bitfld.byte 0x0 0. "MOSCSOKP,Main Clock Oscillator Standby Oscillation Keep select" "0: Disable,1: Enable" line.byte 0x1 "HOCOSCR,High-Speed On-Chip Oscillator Standby Control Register" bitfld.byte 0x1 0. "HOCOSOKP,HOCO Standby Oscillation Keep select." "0: Disable,1: Enable" group.byte 0xA0++0x0 line.byte 0x0 "OPCCR,Operating Power Control Register" rbitfld.byte 0x0 4. "OPCMTSF,Operating Power Control Mode Transition Status Flag" "0: Transition completed,1: During transition" bitfld.byte 0x0 0.--1. "OPCM,Operating Power Control Mode Select" "0: High-speed mode,1: Setting prohibited,?,?" group.byte 0xA2++0x0 line.byte 0x0 "MOSCWTCR,Main Clock Oscillator Wait Control Register" hexmask.byte 0x0 0.--3. 1. "MSTS,Main Clock Oscillator Wait Time Setting" group.long 0xC0++0x3 line.long 0x0 "RSTSR1,Reset Status Register 1" bitfld.long 0x0 14. "CMRF,Common Memory Error Reset Detect Flag" "0: Common memory error reset not detected,1: Common memory error reset detected" bitfld.long 0x0 10. "BUSRF,Bus Error Reset Detect Flag" "0: Bus error reset not detected,1: Bus error reset detected" newline bitfld.long 0x0 4. "CLU0RF,CPU Lockup Reset Detect Flag" "0: CPU Lockup reset not detected,1: CPU Lockup reset detected" bitfld.long 0x0 2. "SWRF,Software Reset Detect Flag" "0: Software reset not detected,1: Software reset detected" newline bitfld.long 0x0 1. "WDT0RF,Watchdog Timer Reset Detect Flag" "0: Watchdog timer reset not detected,1: Watchdog timer reset detected" bitfld.long 0x0 0. "IWDTRF,Independent Watchdog Timer Reset Detect Flag" "0: Independent watchdog timer reset not detected,1: Independent watchdog timer reset detected" rgroup.byte 0xCC++0x0 line.byte 0x0 "SYRACCR,System Register Access Control Register" bitfld.byte 0x0 0. "BUSY,Access Ready monitor" "0: Ready to read/write access,1: Writing in progress" repeat 2. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0xE0)++0x0 line.byte 0x0 "PVD$1CR1,Voltage Monitor %s Circuit Control Register 1" bitfld.byte 0x0 2. "IRQSEL,Voltage Monitor m Interrupt Type Select" "0: Non-maskable interrupt,1: Maskable interrupt" bitfld.byte 0x0 0.--1. "IDTSEL,Voltage Monitor m Interrupt Generation Condition Select" "0,1,2,3" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0xE1)++0x0 line.byte 0x0 "PVD$1SR,Voltage Monitor %s Circuit Status Register" bitfld.byte 0x0 1. "MON,Voltage Monitor 1 Signal Monitor Flag" "0,1" bitfld.byte 0x0 0. "DET,Voltage Monitor m Voltage Change Detection Flag" "0,1" repeat.end group.byte 0x110++0x0 line.byte 0x0 "PDCTRGD,Graphics Power Domain Control Register" rbitfld.byte 0x0 7. "PDPGSF,Power gating status flag" "0: Target domain is power on (not gating),1: Target domain is power off (during Gating)" rbitfld.byte 0x0 6. "PDCSF,Power control status flag" "0: Power gating control is not executed (idle),1: Power gating control is in progress" newline bitfld.byte 0x0 0. "PDDE,Power control enable" "0: Power on the target domain,1: Power off the target domain" group.word 0x140++0x1 line.word 0x0 "PDRAMSCR0,SRAM Power Domain Standby Control Register 0" bitfld.word 0x0 6. "RKEEP6,RAM Retention" "0: When entering the Software Standby mode the..,1: When entering the Software Standby mode the.." bitfld.word 0x0 5. "RKEEP5,RAM Retention" "0: When entering the Software Standby mode the..,1: When entering the Software Standby mode the.." newline bitfld.word 0x0 4. "RKEEP4,RAM Retention" "0: When entering the Software Standby mode the..,1: When entering the Software Standby mode the.." bitfld.word 0x0 3. "RKEEP3,RAM Retention" "0: When entering the Software Standby mode the..,1: When entering the Software Standby mode the.." newline bitfld.word 0x0 2. "RKEEP2,RAM Retention" "0: When entering the Software Standby mode the..,1: When entering the Software Standby mode the.." bitfld.word 0x0 1. "RKEEP1,Unnecessary Circuit Retention" "0: When entering the Software Standby mode the..,1: When entering the Software Standby mode the.." newline bitfld.word 0x0 0. "RKEEP0,Unnecessary Circuit Retention" "0: When entering the Software Standby mode the..,1: When entering the Software Standby mode the.." group.byte 0x142++0x0 line.byte 0x0 "PDRAMSCR1,SRAM Power Domain Standby Control Register 1" bitfld.byte 0x0 0. "RKEEP0,RAM Retention" "0: When entering the CPU Deep Sleep and Software..,1: When entering the CPU Deep Sleep and Software.." group.word 0x3B8++0x1 line.word 0x0 "VBRPABARNS,VBATT Backup Register Privilege Attribute Boundary Address Register for Non-secure Region" hexmask.word 0x0 0.--15. 1. "PABANS,Boundary address between privileged and unprivileged." group.long 0x3C0++0x13 line.long 0x0 "CGFSAR,Clock Generation Function Security Attribute Register" bitfld.long 0x0 26. "NONSEC26,Non Secure Attribute bit 26" "0: Secure,1: Non Secure" bitfld.long 0x0 22. "NONSEC22,Non Secure Attribute bit 22" "0: Secure,1: Non Secure" newline bitfld.long 0x0 21. "NONSEC21,Non Secure Attribute bit 21" "0: Secure,1: Non Secure" bitfld.long 0x0 18. "NONSEC18,Non Secure Attribute bit 18" "0: Secure,1: Non Secure" newline bitfld.long 0x0 17. "NONSEC17,Non Secure Attribute bit 17" "0: Secure,1: Non Secure" bitfld.long 0x0 16. "NONSEC16,Non Secure Attribute bit 16" "0: Secure,1: Non Secure" newline bitfld.long 0x0 13. "NONSEC13,Non Secure Attribute bit 13" "0: Secure,1: Non Secure" bitfld.long 0x0 12. "NONSEC12,Non Secure Attribute bit 12" "0: Secure,1: Non Secure" newline bitfld.long 0x0 11. "NONSEC11,Non Secure Attribute bit 11" "0: Secure,1: Non Secure" bitfld.long 0x0 9. "NONSEC09,Non Secure Attribute bit 09" "0: Secure,1: Non Secure" newline bitfld.long 0x0 8. "NONSEC08,Non Secure Attribute bit 08" "0: Secure,1: Non Secure" bitfld.long 0x0 7. "NONSEC07,Non Secure Attribute bit 07" "0: Secure,1: Non Secure" newline bitfld.long 0x0 6. "NONSEC06,Non Secure Attribute bit 06" "0: Secure,1: Non Secure" bitfld.long 0x0 5. "NONSEC05,Non Secure Attribute bit 05" "0: Secure,1: Non Secure" newline bitfld.long 0x0 4. "NONSEC04,Non Secure Attribute bit 04" "0: Secure,1: Non Secure" bitfld.long 0x0 3. "NONSEC03,Non Secure Attribute bit 03" "0: Secure,1: Non Secure" newline bitfld.long 0x0 2. "NONSEC02,Non Secure Attribute bit 02" "0: Secure,1: Non Secure" bitfld.long 0x0 0. "NONSEC00,Non Secure Attribute bit 00" "0: Secure,1: Non Secure" line.long 0x4 "RSTSAR,Reset Security Attribution Register" bitfld.long 0x4 2. "NONSEC2,Non-secure Attribute bit 2" "0: Secure,1: Non-secure" bitfld.long 0x4 1. "NONSEC1,Non-secure Attribute bit 1" "0: Secure,1: Non-secure" newline bitfld.long 0x4 0. "NONSEC0,Non-secure Attribute bit 0" "0: Secure,1: Non-secure" line.long 0x8 "LPMSAR,Low Power Mode Security Attribution Register" bitfld.long 0x8 21. "NONSEC21,Non-secure Attribute bit 21" "0: Secure,1: Non-secure" bitfld.long 0x8 19. "NONSEC19,Non-secure Attribute bit 19" "0: Secure,1: Non-secure" newline bitfld.long 0x8 18. "NONSEC18,Non-secure Attribute bit 18" "0: Secure,1: Non-secure" bitfld.long 0x8 17. "NONSEC17,Non-secure Attribute bit 17" "0: Secure,1: Non-secure" newline bitfld.long 0x8 8. "NONSEC8,Non-secure Attribute bit 8" "0: Secure,1: Non-secure" bitfld.long 0x8 2. "NONSEC2,Non-secure Attribute bit 2" "0: Secure,1: Non-secure" newline bitfld.long 0x8 1. "NONSEC1,Non-secure Attribute bit 1" "0: Secure,1: Non-secure" bitfld.long 0x8 0. "NONSEC0,Non-secure Attribute bit 0" "0: Secure,1: Non-secure" line.long 0xC "PVDSAR,Programable Voltage Detection Security Attribution Register" bitfld.long 0xC 1. "NONSEC1,Non Secure Attribute bit 1" "0: Secure,1: Non Secure" bitfld.long 0xC 0. "NONSEC0,Non Secure Attribute bit 0" "0: Secure,1: Non Secure" line.long 0x10 "BBFSAR,Battery Backup Function Security Attribute Register" bitfld.long 0x10 4. "NONSEC4,Non Secure Attribute bit 4" "0: Secure,1: Non Secure" bitfld.long 0x10 3. "NONSEC3,Non Secure Attribute bit 3" "0: Secure,1: Non Secure" newline bitfld.long 0x10 2. "NONSEC2,Non Secure Attribute bit 2" "0: Secure,1: Non Secure" bitfld.long 0x10 1. "NONSEC1,Non Secure Attribute bit 1" "0: Secure,1: Non Secure" newline bitfld.long 0x10 0. "NONSEC0,Non Secure Attribute bit 0" "0: Secure,1: Non Secure" group.long 0x3D8++0x3 line.long 0x0 "PGCSAR,Power Gating Control Security Attribution Register" bitfld.long 0x0 1. "NONSEC1,Non-secure Attribute bit 1" "0: Secure,1: Non-secure" group.long 0x3E0++0x7 line.long 0x0 "DPFSAR,Deep Software Standby Interrupt Factor Security Attribution Register" bitfld.long 0x0 31. "DPFSA31,Deep Software Standby Interrupt Factor Security Attribute bit 31" "0: Secure,1: Non-secure" bitfld.long 0x0 29. "DPFSA29,Deep Software Standby Interrupt Factor Security Attribute bit 29" "0: Secure,1: Non-secure" newline bitfld.long 0x0 27. "DPFSA27,Deep Software Standby Interrupt Factor Security Attribute bit 27" "0: Secure,1: Non-secure" bitfld.long 0x0 26. "DPFSA26,Deep Software Standby Interrupt Factor Security Attribute bit 26" "0: Secure,1: Non-secure" newline bitfld.long 0x0 24. "DPFSA24,Deep Software Standby Interrupt Factor Security Attribute bit 24" "0: Secure,1: Non-secure" bitfld.long 0x0 20. "DPFSA20,Deep Software Standby Interrupt Factor Security Attribute bit 20" "0: Secure,1: Non-secure" newline bitfld.long 0x0 19. "DPFSA19,Deep Software Standby Interrupt Factor Security Attribute bit 19" "0: Secure,1: Non-secure" bitfld.long 0x0 18. "DPFSA18,Deep Software Standby Interrupt Factor Security Attribute bit 18" "0: Secure,1: Non-secure" newline bitfld.long 0x0 17. "DPFSA17,Deep Software Standby Interrupt Factor Security Attribute bit 17" "0: Secure,1: Non-secure" bitfld.long 0x0 16. "DPFSA16,Deep Software Standby Interrupt Factor Security Attribute bit 16" "0: Secure,1: Non-secure" newline bitfld.long 0x0 15. "DPFSA15,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)" "0: Secure,1: Non-secure" bitfld.long 0x0 14. "DPFSA14,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)" "0: Secure,1: Non-secure" newline bitfld.long 0x0 13. "DPFSA13,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)" "0: Secure,1: Non-secure" bitfld.long 0x0 12. "DPFSA12,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)" "0: Secure,1: Non-secure" newline bitfld.long 0x0 11. "DPFSA11,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)" "0: Secure,1: Non-secure" bitfld.long 0x0 10. "DPFSA10,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)" "0: Secure,1: Non-secure" newline bitfld.long 0x0 9. "DPFSA09,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)" "0: Secure,1: Non-secure" bitfld.long 0x0 8. "DPFSA08,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 8 to 15)" "0: Secure,1: Non-secure" newline bitfld.long 0x0 7. "DPFSA7,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)" "0: Secure,1: Non-secure" bitfld.long 0x0 6. "DPFSA6,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)" "0: Secure,1: Non-secure" newline bitfld.long 0x0 5. "DPFSA5,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)" "0: Secure,1: Non-secure" bitfld.long 0x0 4. "DPFSA4,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)" "0: Secure,1: Non-secure" newline bitfld.long 0x0 3. "DPFSA3,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)" "0: Secure,1: Non-secure" bitfld.long 0x0 2. "DPFSA2,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)" "0: Secure,1: Non-secure" newline bitfld.long 0x0 1. "DPFSA1,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)" "0: Secure,1: Non-secure" bitfld.long 0x0 0. "DPFSA0,Deep Software Standby Interrupt Factor Security Attribute bit n (n = 0 to 7)" "0: Secure,1: Non-secure" line.long 0x4 "RSCSAR,RAM Standby Control Security Attribution Register" bitfld.long 0x4 16. "RSCSA16,RAM Standby Control Security Attribute bit n (n = 16)" "0: Secure,1: Non-secure" bitfld.long 0x4 6. "RSCSA6,RAM Standby Control Security Attribute bit n (n = 2 to 6)" "0: Secure,1: Non-secure" newline bitfld.long 0x4 5. "RSCSA5,RAM Standby Control Security Attribute bit n (n = 2 to 6)" "0: Secure,1: Non-secure" bitfld.long 0x4 4. "RSCSA4,RAM Standby Control Security Attribute bit n (n = 2 to 6)" "0: Secure,1: Non-secure" newline bitfld.long 0x4 3. "RSCSA3,RAM Standby Control Security Attribute bit n (n = 2 to 6)" "0: Secure,1: Non-secure" bitfld.long 0x4 2. "RSCSA2,RAM Standby Control Security Attribute bit n (n = 2 to 6)" "0: Secure,1: Non-secure" newline bitfld.long 0x4 1. "RSCSA1,Unnecessary Circuit Control Security Attribution bit n (n = 0 to 1)" "0: Secure,1: Non-secure" bitfld.long 0x4 0. "RSCSA0,Unnecessary Circuit Control Security Attribution bit n (n = 0 to 1)" "0: Secure,1: Non-secure" group.word 0x3FE++0x1 line.word 0x0 "PRCR_NS,Protect Register for Non-secure (PRCR_NS)" hexmask.word.byte 0x0 8.--15. 1. "PRKEY,0xA5: Enables writing to the PRCR_NS register." bitfld.word 0x0 4. "PRC4" "0: Disable writes,1: Enable writes" newline bitfld.word 0x0 3. "PRC3,Enable writing to the registers related to the PVD" "0: Disable writes,1: Enable writes" bitfld.word 0x0 1. "PRC1,Enable writing to the registers related to the low power modes and the battery backup function" "0: Disable writes,1: Enable writes" newline bitfld.word 0x0 0. "PRC0,Enable writing to the registers related to the clock generation circuit" "0: Disable writes,1: Enable writes" group.byte 0x400++0x0 line.byte 0x0 "LOCOCR,Low-Speed On-Chip Oscillator Control Register" bitfld.byte 0x0 0. "LCSTP,LOCO Stop" "0: Operate the LOCO clock,1: Stop the LOCO clock" group.byte 0x402++0x0 line.byte 0x0 "LOCOUTCR,LOCO User Trimming Control Register" hexmask.byte 0x0 0.--7. 1. "LOCOUTRM,LOCO User Trimming" group.byte 0xA00++0x0 line.byte 0x0 "DPSBYCR,Deep Software Standby Control Register" bitfld.byte 0x0 6. "IOKEEP,I/O Port Rentention" "0: When the Deep Software Standby mode is canceled..,1: When the Deep Software Standby mode is canceled.." bitfld.byte 0x0 4. "SRKEEP,Standby SRAM Retention" "0: When entering the Software Standby mode or the..,1: When entering the Software Standby mode or the.." newline bitfld.byte 0x0 2. "DCSSMODE" "0: When the Deep Software Standby mode is canceled..,1: When the Deep Software Standby mode is canceled.." group.byte 0xA04++0x0 line.byte 0x0 "DPSWCR,Deep Software Standby Wait Control Register" hexmask.byte 0x0 0.--7. 1. "WTSTS,Deep Software Wait Standby Time Setting Bit" group.byte 0xA08++0x0 line.byte 0x0 "DPSIER0,Deep Software Standby Interrupt Enable Register 0" bitfld.byte 0x0 7. "DIRQ7E,IRQ7-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 6. "DIRQ6E,IRQ6-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 5. "DIRQ5E,IRQ5-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 4. "DIRQ4E,IRQ4-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 3. "DIRQ3E,IRQ3-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 2. "DIRQ2E,IRQ2-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 1. "DIRQ1E,IRQ1-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 0. "DIRQ0E,IRQ0-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" group.byte 0xA0C++0x0 line.byte 0x0 "DPSIER1,Deep Software Standby Interrupt Enable Register 1" bitfld.byte 0x0 7. "DIRQ15E,IRQ15-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 6. "DIRQ14E,IRQ14-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 5. "DIRQ13E,IRQ13-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 4. "DIRQ12E,IRQ12-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 3. "DIRQ11E,IRQ11-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 2. "DIRQ10E,IRQ10-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 1. "DIRQ9E,IRQ9-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 0. "DIRQ8E,IRQ8-DS Pin Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" group.byte 0xA10++0x0 line.byte 0x0 "DPSIER2,Deep Software Standby Interrupt Enable Register 2" bitfld.byte 0x0 4. "DNMIE,NMI Pin Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 3. "DRTCAIE,RTC Alarm interrupt Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 2. "DRTCIIE,RTC Interval interrupt Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 1. "DPVD2IE,PVD2 Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 0. "DPVD1IE,PVD1 Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" group.byte 0xA14++0x0 line.byte 0x0 "DPSIER3,Deep Software Standby Interrupt Enable Register 3" bitfld.byte 0x0 7. "DVBATTADIE,VBATT Tamper Detection Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 5. "DIWDTIE,IWDT Underflow Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 3. "DULPT1IE,ULPT1 Overflow Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" bitfld.byte 0x0 2. "DULPT0IE,ULPT0 Overflow Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" newline bitfld.byte 0x0 0. "DUSBFSIE,USBFS Suspend/Resume Deep Software Standby Cancel Signal Enable" "0: Canceling Deep Software Standby mode is disabled,1: Canceling Deep Software Standby mode is enabled" group.byte 0xA18++0x0 line.byte 0x0 "DPSIFR0,Deep Software Standby Interrupt Flag Register 0" bitfld.byte 0x0 7. "DIRQ7F,IRQ7-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 6. "DIRQ6F,IRQ6-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 5. "DIRQ5F,IRQ5-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 4. "DIRQ4F,IRQ4-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 3. "DIRQ3F,IRQ3-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 2. "DIRQ2F,IRQ2-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 1. "DIRQ1F,IRQ1-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 0. "DIRQ0F,IRQ0-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" group.byte 0xA1C++0x0 line.byte 0x0 "DPSIFR1,Deep Software Standby Interrupt Flag Register 1" bitfld.byte 0x0 7. "DIRQ15F,IRQ15-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 6. "DIRQ14F,IRQ14-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 5. "DIRQ13F,IRQ13-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 4. "DIRQ12F,IRQ12-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 3. "DIRQ11F,IRQ11-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 2. "DIRQ10F,IRQ10-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 1. "DIRQ9F,IRQ9-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 0. "DIRQ8F,IRQ8-DS Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" group.byte 0xA20++0x0 line.byte 0x0 "DPSIFR2,Deep Software Standby Interrupt Flag Register 2" bitfld.byte 0x0 4. "DNMIF,NMI Pin Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 3. "DRTCAIF,RTC Alarm Interrupt Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 2. "DRTCIIF,RTC Interval Interrupt Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 1. "DPVD2IF,PVD2 Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 0. "DPVD1IF,PVD1 Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" group.byte 0xA24++0x0 line.byte 0x0 "DPSIFR3,Deep Software Standby Interrupt Flag Register 3" bitfld.byte 0x0 7. "DVBATTADIF,VBATT Tamper Detection Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 5. "DIWDTIF,IWDT Underflow Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 3. "DULPT1IF,ULPT1 Overflow Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" bitfld.byte 0x0 2. "DULPT0IF,ULPT0 Overflow Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" newline bitfld.byte 0x0 0. "DUSBFSIF,USBFS Suspend/Resume Deep Software Standby Cancel Flag" "0: The cancel request is not generated,1: The cancel request is generated" group.byte 0xA28++0x0 line.byte 0x0 "DPSIEGR0,Deep Software Standby Interrupt Edge Register 0" bitfld.byte 0x0 7. "DIRQ7EG,IRQ7-DS Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" bitfld.byte 0x0 6. "DIRQ6EG,IRQ6-DS Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" newline bitfld.byte 0x0 5. "DIRQ5EG,IRQ5-DS Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" bitfld.byte 0x0 4. "DIRQ4EG,IRQ4-DS Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" newline bitfld.byte 0x0 3. "DIRQ3EG,IRQ3-DS Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" bitfld.byte 0x0 2. "DIRQ2EG,IRQ2-DS Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" newline bitfld.byte 0x0 1. "DIRQ1EG,IRQ1-DS Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" bitfld.byte 0x0 0. "DIRQ0EG,IRQ0-DS Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" group.byte 0xA2C++0x0 line.byte 0x0 "DPSIEGR1,Deep Software Standby Interrupt Edge Register 1" bitfld.byte 0x0 7. "DIRQ15EG,IRQ15-DS Pin Edge Select" "0: A cancel request is generated at a falling edge.,1: A cancel request is generated at a rising edge." bitfld.byte 0x0 6. "DIRQ14EG,IRQ14-DS Pin Edge Select" "0: A cancel request is generated at a falling edge.,1: A cancel request is generated at a rising edge." newline bitfld.byte 0x0 5. "DIRQ13EG,IRQ13-DS Pin Edge Select" "0: A cancel request is generated at a falling edge.,1: A cancel request is generated at a rising edge." bitfld.byte 0x0 4. "DIRQ12EG,IRQ12-DS Pin Edge Select" "0: A cancel request is generated at a falling edge.,1: A cancel request is generated at a rising edge." newline bitfld.byte 0x0 3. "DIRQ11EG,IRQ11-DS Pin Edge Select" "0: A cancel request is generated at a falling edge.,1: A cancel request is generated at a rising edge." bitfld.byte 0x0 2. "DIRQ10EG,IRQ10-DS Pin Edge Select" "0: A cancel request is generated at a falling edge.,1: A cancel request is generated at a rising edge" newline bitfld.byte 0x0 1. "DIRQ9EG,IRQ9-DS Pin Edge Select" "0: A cancel request is generated at a falling edge.,1: A cancel request is generated at a rising edge." bitfld.byte 0x0 0. "DIRQ8EG,IRQ8-DS Pin Edge Select" "0: A cancel request is generated at a falling edge.,1: A cancel request is generated at a rising edge." group.byte 0xA30++0x0 line.byte 0x0 "DPSIEGR2,Deep Software Standby Interrupt Edge Register 2" bitfld.byte 0x0 4. "DNMIEG,NMI Pin Edge Select" "0: A cancel request is generated at a falling edge,1: A cancel request is generated at a rising edge" bitfld.byte 0x0 1. "DPVD2EG,PVD2 Edge Select" "0: A cancel request is generated when VCC < Vdet2..,1: A cancel request is generated when VCC ≥ Vdet2.." newline bitfld.byte 0x0 0. "DPVD1EG,PVD1 Edge Select" "0: A cancel request is generated when VCC < Vdet1..,1: A cancel request is generated when VCC ≥ Vdet1.." group.byte 0xA38++0x0 line.byte 0x0 "SYOCDCR,System Control OCD Control Register" bitfld.byte 0x0 7. "DBGEN,Debugger Enable bit" "0: On-chip debugger is disabled,1: On-chip debugger is enabled" group.byte 0xA40++0x0 line.byte 0x0 "RSTSR0,Reset Status Register 0" bitfld.byte 0x0 7. "DPSRSTF,Deep Software Standby Reset Flag" "0: Deep Software Standby mode cancellation not..,1: Deep Software Standby mode cancellation.." bitfld.byte 0x0 3. "PVD2RF,Voltage Monitor 2 Reset Detect Flag" "0: Voltage monitor 2 reset not detected,1: Voltage monitor 2 reset detected" newline bitfld.byte 0x0 2. "PVD1RF,Voltage Monitor 1 Reset Detect Flag" "0: Voltage monitor 1 reset not detected,1: Voltage monitor 1 reset detected" bitfld.byte 0x0 1. "PVD0RF,Voltage Monitor 0 Reset Detect Flag" "0: Voltage monitor 0 reset not detected,1: Voltage monitor 0 reset detected" newline bitfld.byte 0x0 0. "PORF,Power-On Reset Detect Flag" "0: Power-on reset not detected,1: Power-on reset detected" group.byte 0xA44++0x0 line.byte 0x0 "RSTSR2,Reset Status Register 2" bitfld.byte 0x0 0. "CWSF,Cold/Warm Start Determination Flag" "0: Cold start,1: Warm start" group.byte 0xA50++0x0 line.byte 0x0 "MOMCR,Main Clock Oscillator Mode Oscillation Control Register" bitfld.byte 0x0 6. "MOSEL,Main Clock Oscillator Switching" "0: Resonator,1: External clock input" bitfld.byte 0x0 1.--3. "MODRV0,Main Clock Oscillator Drive Capability 0 Switching" "0: Setting prohibited,?,?,?,?,?,?,?" group.byte 0xA54++0x0 line.byte 0x0 "FWEPROR,Flash P/E Protect Register" bitfld.byte 0x0 0.--1. "FLWE,Flash Programming and Erasure" "0: Prohibits Program Block Erase Multi Block Erase..,1: Permits Program Block Erase Multi Block Erase..,?,?" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0xA58)++0x0 line.byte 0x0 "PVD$1CMPCR,Voltage Monitor %s Comparator Control Register" bitfld.byte 0x0 7. "PVDE,Voltage Detection m Enable" "0: Voltage detection m circuit disabled,1: Voltage detection m circuit enabled" hexmask.byte 0x0 0.--4. 1. "PVDLVL,Detection Voltage m Level Select" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0xA70)++0x0 line.byte 0x0 "PVD$1CR0,Voltage Monitor %s Circuit Control Register 0" bitfld.byte 0x0 7. "RN,Voltage Monitor m Reset Negate Select" "0,1" bitfld.byte 0x0 6. "RI,Voltage Monitor m Circuit Mode Select" "0,1" newline bitfld.byte 0x0 4.--5. "FSAMP,Sampling Clock Select" "0: 1/2 LOCO frequency,1: 1/4 LOCO frequency,?,?" bitfld.byte 0x0 2. "CMPE,Voltage Monitor m Circuit Comparison Result Output Enable" "0: Voltage monitor m circuit comparison result..,1: Voltage monitor m circuit comparison result.." newline bitfld.byte 0x0 1. "DFDIS,Voltage monitor m Digital Filter Disabled Mode Select" "0: Enable the digital filter,1: Disable the digital filter" bitfld.byte 0x0 0. "RIE,Voltage Monitor m Interrupt/Reset Enable" "0: Disable,1: Enable" repeat.end group.byte 0xA84++0x0 line.byte 0x0 "VBATTMNSELR,Battery Backup Voltage Monitor Function Select Register" bitfld.byte 0x0 0. "VBTMNSEL,VBATT Voltage Monitor Function Select Bit" "0: Disables VBATT voltage monitor function,1: Enables VBATT voltage monitor function" group.byte 0xA88++0x0 line.byte 0x0 "VBTBPCR1,VBATT Battery Power Supply Control Register 1" bitfld.byte 0x0 0. "BPWSWSTP,Battery Power Supply Switch Stop" "0: Battery power supply switch enable,1: Battery power supply switch stop" group.byte 0xA90++0x0 line.byte 0x0 "LPSCR,Low Power State Control Register" hexmask.byte 0x0 0.--3. 1. "LPMD,Low power mode setting bit" group.byte 0xA98++0x0 line.byte 0x0 "SSCR1,Software Standby Control Register 1" bitfld.byte 0x0 0. "SS1FR,Software Standby Fast Return" "0: When returning from Software Standby mode fast..,1: When returning from Software Standby mode fast.." group.byte 0xAB0++0x0 line.byte 0x0 "LVOCR,Low Voltage Operation Control register" bitfld.byte 0x0 1. "LVO1E,Low Voltage Operation 1 Enable" "0: Disable,1: Enable" bitfld.byte 0x0 0. "LVO0E,Low Voltage Operation 0 Enable" "0: Disable,1: Enable" group.byte 0xB04++0x0 line.byte 0x0 "PLL1LDOCR,PLL1-LDO Control Register" bitfld.byte 0x0 1. "SKEEP,STBY Keep" "0: PLL1-LDO is stopped during Software Standby mode.,1: PLL1-LDO state before Software Standby mode is.." bitfld.byte 0x0 0. "LDOSTP,LDO Stop" "0: PLL1-LDO is enabled,1: PLL1-LDO is stopped" group.byte 0xB08++0x0 line.byte 0x0 "PLL2LDOCR,PLL2-LDO Control Register" bitfld.byte 0x0 1. "SKEEP,STBY Keep" "0: PLL2-LDO is stopped during Software Standby mode.,1: PLL2-LDO state before Software Standby mode is.." bitfld.byte 0x0 0. "LDOSTP,LDO Stop" "0: PLL2-LDO is enabled,1: PLL2-LDO is stopped" group.byte 0xB0C++0x0 line.byte 0x0 "HOCOLDOCR,HOCO-LDO Control Register" bitfld.byte 0x0 1. "SKEEP,STBY Keep" "0: HOCO-LDO is stopped during Software Standby mode.,1: HOCO-LDO state before Software Standby mode is.." bitfld.byte 0x0 0. "LDOSTP,LDO Stop" "0: HOCO-LDO is enabled,1: HOCO-LDO is stopped" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0xB20)++0x0 line.byte 0x0 "PVD$1FCR,Voltage Monitor %s Function Control Register" bitfld.byte 0x0 0. "RHSEL,Rise Hysteresis Select" "0: Hysteresis level for VCC-fall detection is..,1: Hysteresis level for VCC-rise detection is.." repeat.end group.byte 0xC00++0x1 line.byte 0x0 "SOSCCR,Sub-Clock Oscillator Control Register" bitfld.byte 0x0 0. "SOSTP,Sub-Clock Oscillator Stop" "0: Operate the sub-clock oscillator,1: Stop the sub-clock oscillator" line.byte 0x1 "SOMCR,Sub-Clock Oscillator Mode Control Register" bitfld.byte 0x1 6. "SOSEL,Sub-Clock Oscillator Switching" "0: Resonator,1: External clock input" bitfld.byte 0x1 0.--1. "SODRV,Sub-Clock Oscillator Drive Capability Switching" "0: Standard (12.5pf),1: Lowpower mode 1 (9pf),?,?" group.byte 0xC40++0x0 line.byte 0x0 "VBTBER,VBATT Backup Enable Register" bitfld.byte 0x0 3. "VBAE,VBATT backup register access enable bit" "0: Disable to access VBTBKR[n],1: Enable to access VBTBKR[n]" group.byte 0xC45++0x1 line.byte 0x0 "VBTBPCR2,VBATT Battery Power Supply Control Register 2" bitfld.byte 0x0 4. "VDETE,Voltage drop detection enable" "0: VCC Voltage drop detection disable,1: VCC Voltage drop detection enable" bitfld.byte 0x0 0.--2. "VDETLVL,VDETBAT Level Select" "0: 2.80 V,1: 2.53 V,?,?,?,?,?,?" line.byte 0x1 "VBTBPSR,VBATT Battery Power Supply Status Register" rbitfld.byte 0x1 5. "BPWSWM,Battery Power Supply Switch Status Monitor" "0: VCC voltage < VDETBATT_m,1: VCC voltage > VDETBATT_m" rbitfld.byte 0x1 4. "VBPORM,VBATT_POR Monitor" "0: VBATT_R voltage < VPDR (BATR),1: VBATT_R voltage > VPDR (BATR)" newline bitfld.byte 0x1 0. "VBPORF,VBATT_POR Flag" "0: VBATT_R voltage drop is not detected,1: VBATT_R voltage drop is detected" group.byte 0xC48++0x2 line.byte 0x0 "VBTADSR,VBATT Tamper detection Status Register" bitfld.byte 0x0 2. "VBTADF2,VBATT Tamper Detection flag 2" "0: RTCIC2 input edge is not detected,1: RTCIC2 input edge is detected" bitfld.byte 0x0 1. "VBTADF1,VBATT Tamper Detection flag 1" "0: RTCIC1 input edge is not detected,1: RTCIC1 input edge is detected" newline bitfld.byte 0x0 0. "VBTADF0,VBATT Tamper Detection flag 0" "0: RTCIC0 input edge is not detected,1: RTCIC0 input edge is detected" line.byte 0x1 "VBTADCR1,VBATT Tamper detection Control Register 1" bitfld.byte 0x1 6. "VBTADCE2,VBATT Tamper Detection Backup Register Clear Enable 2" "0: Clear Backup Register by VBTADF2 flag is disable,1: Clear Backup Register by VBTADF2 flag is enable" bitfld.byte 0x1 5. "VBTADCE1,VBATT Tamper Detection Backup Register Clear Enable 1" "0: Clear Backup Register by VBTADF1 flag is disable,1: Clear Backup Register by VBTADF1 flag is enable" newline bitfld.byte 0x1 4. "VBTADCE0,VBATT Tamper Detection Backup Register Clear Enable 0" "0: Clear Backup Register by VBTADF0 flag is disable,1: Clear Backup Register by VBTADF0 flag is enable" bitfld.byte 0x1 2. "VBTADIE2,VBATT Tamper Detection Interrupt Enable 2" "0: Interrupt by VBTADF2 flag is disable,1: Interrupt by VBTADF2 flag is enable" newline bitfld.byte 0x1 1. "VBTADIE1,VBATT Tamper Detection Interrupt Enable 1" "0: Interrupt by VBTADF1 flag is disable,1: Interrupt by VBTADF1 flag is enable" bitfld.byte 0x1 0. "VBTADIE0,VBATT Tamper Detection Interrupt Enable 0" "0: Interrupt by VBTADF0 flag is disable,1: Interrupt by VBTADF0 flag is enable" line.byte 0x2 "VBTADCR2,VBATT Tamper detection Control Register 2" bitfld.byte 0x2 2. "VBRTCES2,VBATT RTC Time Capture Event Source Select 2" "0: RTCIC2,1: VBTADF2" bitfld.byte 0x2 1. "VBRTCES1,VBATT RTC Time Capture Event Source Select 1" "0: RTCIC1,1: VBTADF1" newline bitfld.byte 0x2 0. "VBRTCES0,VBATT RTC Time Capture Event Source Select 0" "0: RTCIC0,1: VBTADF0" group.byte 0xC4C++0x1 line.byte 0x0 "VBTICTLR,VBATT Input Control Register" bitfld.byte 0x0 2. "VCH2INEN,VBATT CH2 Input Enable" "0: RTCIC2 input disable,1: RTCIC2 input enable" bitfld.byte 0x0 1. "VCH1INEN,VBATT CH1 Input Enable" "0: RTCIC1 input disable,1: RTCIC1 input enable" newline bitfld.byte 0x0 0. "VCH0INEN,VBATT CH0 Input Enable" "0: RTCIC0 input disable,1: RTCIC0 input enable" line.byte 0x1 "VBTICTLR2,VBATT Input Control Register 2" bitfld.byte 0x1 6. "VCH2EG,VBATT CH2 Input Edge Select" "0: RTCIC2 pin input event is detected on falling edge,1: RTCIC2 pin input event is detected on rising edge" bitfld.byte 0x1 5. "VCH1EG,VBATT CH1 Input Edge Select" "0: RTCIC1 pin input event is detected on falling edge,1: RTCIC1 pin input event is detected on rising edge" newline bitfld.byte 0x1 4. "VCH0EG,VBATT CH0 Input Edge Select" "0: RTCIC0 pin input event is detected on falling edge,1: RTCIC0 pin input event is detected on rising edge" bitfld.byte 0x1 2. "VCH2NCE,VBATT CH2 Input Noise Canceler Enable" "0: RTCIC2 pin input noise canceler disable,1: RTCIC2 pin input noise canceler enable" newline bitfld.byte 0x1 1. "VCH1NCE,VBATT CH1 Input Noise Canceler Enable" "0: RTCIC1 pin input noise canceler disable,1: RTCIC1 pin input noise canceler enable" bitfld.byte 0x1 0. "VCH0NCE,VBATT CH0 Input Noise Canceler Enable" "0: RTCIC0 pin input noise canceler disable,1: RTCIC0 pin input noise canceler enable" rgroup.byte 0xC4E++0x0 line.byte 0x0 "VBTIMONR,VBATT Input Monitor Register" bitfld.byte 0x0 2. "VCH2MON,VBATT CH2 Input monitor" "0: RTCIC2 pin input is low level,1: RTCIC2 pin input is high level." bitfld.byte 0x0 1. "VCH1MON,VBATT CH1 Input monitor" "0: RTCIC1 pin input is low level,1: RTCIC1 pin input is high level" newline bitfld.byte 0x0 0. "VCH0MON,VBATT CH0 Input monitor" "0: RTCIC0 pin input is low level,1: RTCIC0 pin input is high level." repeat 128. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0xD00)++0x0 line.byte 0x0 "VBTBKR[$1],VBATT Backup Register" repeat.end tree.end tree.end tree "TSD (Temperature Sensor Calibration Data)" base ad:0x0 tree "TSD" base ad:0x4011B000 rgroup.long 0x17C++0x3 line.long 0x0 "TSCDR,Temperature Sensor Calibration Data Register" hexmask.long.word 0x0 0.--15. 1. "TSCDR,Temperature Sensor Calibration Data" tree.end tree "TSD_NS" base ad:0x5011B000 rgroup.long 0x17C++0x3 line.long 0x0 "TSCDR,Temperature Sensor Calibration Data Register" hexmask.long.word 0x0 0.--15. 1. "TSCDR,Temperature Sensor Calibration Data" tree.end tree.end tree "TSN (Temperature Sensor)" base ad:0x0 tree "TSN" base ad:0x40235000 group.byte 0x0++0x0 line.byte 0x0 "TSCR,Temperature Sensor Control Register" bitfld.byte 0x0 7. "TSEN,Temperature Sensor Enable" "0: Stop the temperature sensor,1: Start the temperature sensor." bitfld.byte 0x0 4. "TSOE,Temperature Sensor Output Enable" "0: Disable output from the temperature sensor to..,1: Enable output from the temperature sensor to the.." tree.end tree "TSN_NS" base ad:0x50235000 group.byte 0x0++0x0 line.byte 0x0 "TSCR,Temperature Sensor Control Register" bitfld.byte 0x0 7. "TSEN,Temperature Sensor Enable" "0: Stop the temperature sensor,1: Start the temperature sensor." bitfld.byte 0x0 4. "TSOE,Temperature Sensor Output Enable" "0: Disable output from the temperature sensor to..,1: Enable output from the temperature sensor to the.." tree.end tree.end tree "ULPT (Ultra-Low-Power Timer)" base ad:0x0 tree "ULPT0" base ad:0x40220000 group.long 0x0++0xB line.long 0x0 "ULPTCNT,ULPT Counter Register" hexmask.long 0x0 0.--31. 1. "ULPTCNT,Setting range : 0x00000000 to 0xFFFFFFFF" line.long 0x4 "ULPTCMA,ULPT Compare Match A Register" hexmask.long 0x4 0.--31. 1. "ULPTCMA,32-bit Compare Match A Data" line.long 0x8 "ULPTCMB,ULPT Compare Match B Register" hexmask.long 0x8 0.--31. 1. "ULPTCMB,32-bit Compare Match B Data" group.byte 0xC++0x6 line.byte 0x0 "ULPTCR,ULPT Control Register" bitfld.byte 0x0 7. "TCMBF,Compare Match B Flag" "0: Not matched (counter ≠ ULPTCMB[31:0]),1: Matched (counter = ULPTCMB[31:0])" bitfld.byte 0x0 6. "TCMAF,Compare Match A Flag" "0: Not matched (counter ≠ ULPTCMA[31:0]),1: Matched (counter = ULPTCMA[31:0])" newline bitfld.byte 0x0 5. "TUNDF,Underflow Flag" "0: No underflow occurred (counter ≠ 0x00000000).,1: Underflow occurred (counter = 0x00000000)." bitfld.byte 0x0 2. "TSTOP,Counter Forcible Stop" "0: Writing is invalid.,1: Stop the counter forcibly." newline rbitfld.byte 0x0 1. "TCSTF,Counter Status Flag" "0: Counter stopped,1: Counter running" bitfld.byte 0x0 0. "TSTART,Counter Start" "0: Stop the counter.,1: Start the counter." line.byte 0x1 "ULPTMR1,ULPT Mode Register 1" bitfld.byte 0x1 5. "TCK1,Count Source" "0: Divided clock specified by the ULPTMR2.CKS[2:0]..,1: Divided clock specified by the ULPTMR2.CKS[2:0].." bitfld.byte 0x1 3. "TEDGPL,ULPTEVIn Edge Polarity" "0: Either edge (rising),1: Both edges" newline bitfld.byte 0x1 1. "TMOD1,Operating Mode" "0: Timer mode,1: Event counter mode" line.byte 0x2 "ULPTMR2,ULPT Mode Register 2" bitfld.byte 0x2 7. "LPM,Low Power Mode" "0: Normal mode,1: Low power mode" bitfld.byte 0x2 0.--2. "CKS,ULPTLCLK/ULPTSCLK Count Source Clock Division Ratio" "0: 1/1,1: 1/2,?,?,?,?,?,?" line.byte 0x3 "ULPTMR3,ULPT Mode Register 3" bitfld.byte 0x3 6.--7. "TEEPOL,ULPTEEn Edge Polarity Select" "0: Rising edge,1: Falling edge,?,?" bitfld.byte 0x3 4.--5. "TEECTL,ULPTEEn Function Select" "0: Count enable mode,?,?,?" newline bitfld.byte 0x3 2. "TOPOL,ULPTOn Polarity Select" "0: Start the ULPTOn output with low level.,1: Start the ULPTOn output with high level." bitfld.byte 0x3 1. "TEVPOL,ULPTEVIn Polarity Switch" "0: External event input (ULPTEVIn pin),1: External event input (ULPTEVIn pin) in reverse" newline bitfld.byte 0x3 0. "TCNTCTL,Count Function Select" "0: Continuous mode,1: One-shot mode" line.byte 0x4 "ULPTIOC,ULPT I/O Control Register" bitfld.byte 0x4 6. "TIOGT0,ULPTEVIn Count Control" "0: Always count external events.,1: Count external events while the ULPTEVIn pin is.." bitfld.byte 0x4 4.--5. "TIPF,ULPTEVIn Input Filter" "0: No filter,1: Filter sampling at PCLKB,?,?" newline bitfld.byte 0x4 2. "TOE,ULPTOn Output Enable" "0: Disable the ULPTOn output.,1: Enable the ULPTOn output." line.byte 0x5 "ULPTISR,ULPT Event Pin Select Register" bitfld.byte 0x5 2. "RCCPSEL2,ULPTEEn Polarity Select" "0: Count external events when low level.,1: Count external events when high level." line.byte 0x6 "ULPTCMSR,ULPT Compare Match Function Select Register" bitfld.byte 0x6 6. "TOPOLB,ULPTOBn Polarity Select" "0: Start the ULPTOBn output with low.,1: Start the ULPTOBn output with high." bitfld.byte 0x6 5. "TOEB,ULPTOBn Output Enable" "0: Disable the ULPTOBn output.,1: Enable the ULPTOBn output." newline bitfld.byte 0x6 4. "TCMEB,Compare Match B Register Enable" "0: Disable compare match B register.,1: Enable compare match B register." bitfld.byte 0x6 2. "TOPOLA,ULPTOAn Polarity Select" "0: Start the ULPTOAn output with low.,1: Start the ULPTOAn output with high." newline bitfld.byte 0x6 1. "TOEA,ULPTOAn Output Enable" "0: Disable the ULPTOAn output.,1: Enable the ULPTOAn output." bitfld.byte 0x6 0. "TCMEA,Compare Match A Register Enable" "0: Disable compare match A register.,1: Enable compare match A register." tree.end tree "ULPT0_NS" base ad:0x50220000 group.long 0x0++0xB line.long 0x0 "ULPTCNT,ULPT Counter Register" hexmask.long 0x0 0.--31. 1. "ULPTCNT,Setting range : 0x00000000 to 0xFFFFFFFF" line.long 0x4 "ULPTCMA,ULPT Compare Match A Register" hexmask.long 0x4 0.--31. 1. "ULPTCMA,32-bit Compare Match A Data" line.long 0x8 "ULPTCMB,ULPT Compare Match B Register" hexmask.long 0x8 0.--31. 1. "ULPTCMB,32-bit Compare Match B Data" group.byte 0xC++0x6 line.byte 0x0 "ULPTCR,ULPT Control Register" bitfld.byte 0x0 7. "TCMBF,Compare Match B Flag" "0: Not matched (counter ≠ ULPTCMB[31:0]),1: Matched (counter = ULPTCMB[31:0])" bitfld.byte 0x0 6. "TCMAF,Compare Match A Flag" "0: Not matched (counter ≠ ULPTCMA[31:0]),1: Matched (counter = ULPTCMA[31:0])" newline bitfld.byte 0x0 5. "TUNDF,Underflow Flag" "0: No underflow occurred (counter ≠ 0x00000000).,1: Underflow occurred (counter = 0x00000000)." bitfld.byte 0x0 2. "TSTOP,Counter Forcible Stop" "0: Writing is invalid.,1: Stop the counter forcibly." newline rbitfld.byte 0x0 1. "TCSTF,Counter Status Flag" "0: Counter stopped,1: Counter running" bitfld.byte 0x0 0. "TSTART,Counter Start" "0: Stop the counter.,1: Start the counter." line.byte 0x1 "ULPTMR1,ULPT Mode Register 1" bitfld.byte 0x1 5. "TCK1,Count Source" "0: Divided clock specified by the ULPTMR2.CKS[2:0]..,1: Divided clock specified by the ULPTMR2.CKS[2:0].." bitfld.byte 0x1 3. "TEDGPL,ULPTEVIn Edge Polarity" "0: Either edge (rising),1: Both edges" newline bitfld.byte 0x1 1. "TMOD1,Operating Mode" "0: Timer mode,1: Event counter mode" line.byte 0x2 "ULPTMR2,ULPT Mode Register 2" bitfld.byte 0x2 7. "LPM,Low Power Mode" "0: Normal mode,1: Low power mode" bitfld.byte 0x2 0.--2. "CKS,ULPTLCLK/ULPTSCLK Count Source Clock Division Ratio" "0: 1/1,1: 1/2,?,?,?,?,?,?" line.byte 0x3 "ULPTMR3,ULPT Mode Register 3" bitfld.byte 0x3 6.--7. "TEEPOL,ULPTEEn Edge Polarity Select" "0: Rising edge,1: Falling edge,?,?" bitfld.byte 0x3 4.--5. "TEECTL,ULPTEEn Function Select" "0: Count enable mode,?,?,?" newline bitfld.byte 0x3 2. "TOPOL,ULPTOn Polarity Select" "0: Start the ULPTOn output with low level.,1: Start the ULPTOn output with high level." bitfld.byte 0x3 1. "TEVPOL,ULPTEVIn Polarity Switch" "0: External event input (ULPTEVIn pin),1: External event input (ULPTEVIn pin) in reverse" newline bitfld.byte 0x3 0. "TCNTCTL,Count Function Select" "0: Continuous mode,1: One-shot mode" line.byte 0x4 "ULPTIOC,ULPT I/O Control Register" bitfld.byte 0x4 6. "TIOGT0,ULPTEVIn Count Control" "0: Always count external events.,1: Count external events while the ULPTEVIn pin is.." bitfld.byte 0x4 4.--5. "TIPF,ULPTEVIn Input Filter" "0: No filter,1: Filter sampling at PCLKB,?,?" newline bitfld.byte 0x4 2. "TOE,ULPTOn Output Enable" "0: Disable the ULPTOn output.,1: Enable the ULPTOn output." line.byte 0x5 "ULPTISR,ULPT Event Pin Select Register" bitfld.byte 0x5 2. "RCCPSEL2,ULPTEEn Polarity Select" "0: Count external events when low level.,1: Count external events when high level." line.byte 0x6 "ULPTCMSR,ULPT Compare Match Function Select Register" bitfld.byte 0x6 6. "TOPOLB,ULPTOBn Polarity Select" "0: Start the ULPTOBn output with low.,1: Start the ULPTOBn output with high." bitfld.byte 0x6 5. "TOEB,ULPTOBn Output Enable" "0: Disable the ULPTOBn output.,1: Enable the ULPTOBn output." newline bitfld.byte 0x6 4. "TCMEB,Compare Match B Register Enable" "0: Disable compare match B register.,1: Enable compare match B register." bitfld.byte 0x6 2. "TOPOLA,ULPTOAn Polarity Select" "0: Start the ULPTOAn output with low.,1: Start the ULPTOAn output with high." newline bitfld.byte 0x6 1. "TOEA,ULPTOAn Output Enable" "0: Disable the ULPTOAn output.,1: Enable the ULPTOAn output." bitfld.byte 0x6 0. "TCMEA,Compare Match A Register Enable" "0: Disable compare match A register.,1: Enable compare match A register." tree.end tree "ULPT1" base ad:0x40220100 group.long 0x0++0xB line.long 0x0 "ULPTCNT,ULPT Counter Register" hexmask.long 0x0 0.--31. 1. "ULPTCNT,Setting range : 0x00000000 to 0xFFFFFFFF" line.long 0x4 "ULPTCMA,ULPT Compare Match A Register" hexmask.long 0x4 0.--31. 1. "ULPTCMA,32-bit Compare Match A Data" line.long 0x8 "ULPTCMB,ULPT Compare Match B Register" hexmask.long 0x8 0.--31. 1. "ULPTCMB,32-bit Compare Match B Data" group.byte 0xC++0x6 line.byte 0x0 "ULPTCR,ULPT Control Register" bitfld.byte 0x0 7. "TCMBF,Compare Match B Flag" "0: Not matched (counter ≠ ULPTCMB[31:0]),1: Matched (counter = ULPTCMB[31:0])" bitfld.byte 0x0 6. "TCMAF,Compare Match A Flag" "0: Not matched (counter ≠ ULPTCMA[31:0]),1: Matched (counter = ULPTCMA[31:0])" newline bitfld.byte 0x0 5. "TUNDF,Underflow Flag" "0: No underflow occurred (counter ≠ 0x00000000).,1: Underflow occurred (counter = 0x00000000)." bitfld.byte 0x0 2. "TSTOP,Counter Forcible Stop" "0: Writing is invalid.,1: Stop the counter forcibly." newline rbitfld.byte 0x0 1. "TCSTF,Counter Status Flag" "0: Counter stopped,1: Counter running" bitfld.byte 0x0 0. "TSTART,Counter Start" "0: Stop the counter.,1: Start the counter." line.byte 0x1 "ULPTMR1,ULPT Mode Register 1" bitfld.byte 0x1 5. "TCK1,Count Source" "0: Divided clock specified by the ULPTMR2.CKS[2:0]..,1: Divided clock specified by the ULPTMR2.CKS[2:0].." bitfld.byte 0x1 3. "TEDGPL,ULPTEVIn Edge Polarity" "0: Either edge (rising),1: Both edges" newline bitfld.byte 0x1 1. "TMOD1,Operating Mode" "0: Timer mode,1: Event counter mode" line.byte 0x2 "ULPTMR2,ULPT Mode Register 2" bitfld.byte 0x2 7. "LPM,Low Power Mode" "0: Normal mode,1: Low power mode" bitfld.byte 0x2 0.--2. "CKS,ULPTLCLK/ULPTSCLK Count Source Clock Division Ratio" "0: 1/1,1: 1/2,?,?,?,?,?,?" line.byte 0x3 "ULPTMR3,ULPT Mode Register 3" bitfld.byte 0x3 6.--7. "TEEPOL,ULPTEEn Edge Polarity Select" "0: Rising edge,1: Falling edge,?,?" bitfld.byte 0x3 4.--5. "TEECTL,ULPTEEn Function Select" "0: Count enable mode,?,?,?" newline bitfld.byte 0x3 2. "TOPOL,ULPTOn Polarity Select" "0: Start the ULPTOn output with low level.,1: Start the ULPTOn output with high level." bitfld.byte 0x3 1. "TEVPOL,ULPTEVIn Polarity Switch" "0: External event input (ULPTEVIn pin),1: External event input (ULPTEVIn pin) in reverse" newline bitfld.byte 0x3 0. "TCNTCTL,Count Function Select" "0: Continuous mode,1: One-shot mode" line.byte 0x4 "ULPTIOC,ULPT I/O Control Register" bitfld.byte 0x4 6. "TIOGT0,ULPTEVIn Count Control" "0: Always count external events.,1: Count external events while the ULPTEVIn pin is.." bitfld.byte 0x4 4.--5. "TIPF,ULPTEVIn Input Filter" "0: No filter,1: Filter sampling at PCLKB,?,?" newline bitfld.byte 0x4 2. "TOE,ULPTOn Output Enable" "0: Disable the ULPTOn output.,1: Enable the ULPTOn output." line.byte 0x5 "ULPTISR,ULPT Event Pin Select Register" bitfld.byte 0x5 2. "RCCPSEL2,ULPTEEn Polarity Select" "0: Count external events when low level.,1: Count external events when high level." line.byte 0x6 "ULPTCMSR,ULPT Compare Match Function Select Register" bitfld.byte 0x6 6. "TOPOLB,ULPTOBn Polarity Select" "0: Start the ULPTOBn output with low.,1: Start the ULPTOBn output with high." bitfld.byte 0x6 5. "TOEB,ULPTOBn Output Enable" "0: Disable the ULPTOBn output.,1: Enable the ULPTOBn output." newline bitfld.byte 0x6 4. "TCMEB,Compare Match B Register Enable" "0: Disable compare match B register.,1: Enable compare match B register." bitfld.byte 0x6 2. "TOPOLA,ULPTOAn Polarity Select" "0: Start the ULPTOAn output with low.,1: Start the ULPTOAn output with high." newline bitfld.byte 0x6 1. "TOEA,ULPTOAn Output Enable" "0: Disable the ULPTOAn output.,1: Enable the ULPTOAn output." bitfld.byte 0x6 0. "TCMEA,Compare Match A Register Enable" "0: Disable compare match A register.,1: Enable compare match A register." tree.end tree "ULPT1_NS" base ad:0x50220100 group.long 0x0++0xB line.long 0x0 "ULPTCNT,ULPT Counter Register" hexmask.long 0x0 0.--31. 1. "ULPTCNT,Setting range : 0x00000000 to 0xFFFFFFFF" line.long 0x4 "ULPTCMA,ULPT Compare Match A Register" hexmask.long 0x4 0.--31. 1. "ULPTCMA,32-bit Compare Match A Data" line.long 0x8 "ULPTCMB,ULPT Compare Match B Register" hexmask.long 0x8 0.--31. 1. "ULPTCMB,32-bit Compare Match B Data" group.byte 0xC++0x6 line.byte 0x0 "ULPTCR,ULPT Control Register" bitfld.byte 0x0 7. "TCMBF,Compare Match B Flag" "0: Not matched (counter ≠ ULPTCMB[31:0]),1: Matched (counter = ULPTCMB[31:0])" bitfld.byte 0x0 6. "TCMAF,Compare Match A Flag" "0: Not matched (counter ≠ ULPTCMA[31:0]),1: Matched (counter = ULPTCMA[31:0])" newline bitfld.byte 0x0 5. "TUNDF,Underflow Flag" "0: No underflow occurred (counter ≠ 0x00000000).,1: Underflow occurred (counter = 0x00000000)." bitfld.byte 0x0 2. "TSTOP,Counter Forcible Stop" "0: Writing is invalid.,1: Stop the counter forcibly." newline rbitfld.byte 0x0 1. "TCSTF,Counter Status Flag" "0: Counter stopped,1: Counter running" bitfld.byte 0x0 0. "TSTART,Counter Start" "0: Stop the counter.,1: Start the counter." line.byte 0x1 "ULPTMR1,ULPT Mode Register 1" bitfld.byte 0x1 5. "TCK1,Count Source" "0: Divided clock specified by the ULPTMR2.CKS[2:0]..,1: Divided clock specified by the ULPTMR2.CKS[2:0].." bitfld.byte 0x1 3. "TEDGPL,ULPTEVIn Edge Polarity" "0: Either edge (rising),1: Both edges" newline bitfld.byte 0x1 1. "TMOD1,Operating Mode" "0: Timer mode,1: Event counter mode" line.byte 0x2 "ULPTMR2,ULPT Mode Register 2" bitfld.byte 0x2 7. "LPM,Low Power Mode" "0: Normal mode,1: Low power mode" bitfld.byte 0x2 0.--2. "CKS,ULPTLCLK/ULPTSCLK Count Source Clock Division Ratio" "0: 1/1,1: 1/2,?,?,?,?,?,?" line.byte 0x3 "ULPTMR3,ULPT Mode Register 3" bitfld.byte 0x3 6.--7. "TEEPOL,ULPTEEn Edge Polarity Select" "0: Rising edge,1: Falling edge,?,?" bitfld.byte 0x3 4.--5. "TEECTL,ULPTEEn Function Select" "0: Count enable mode,?,?,?" newline bitfld.byte 0x3 2. "TOPOL,ULPTOn Polarity Select" "0: Start the ULPTOn output with low level.,1: Start the ULPTOn output with high level." bitfld.byte 0x3 1. "TEVPOL,ULPTEVIn Polarity Switch" "0: External event input (ULPTEVIn pin),1: External event input (ULPTEVIn pin) in reverse" newline bitfld.byte 0x3 0. "TCNTCTL,Count Function Select" "0: Continuous mode,1: One-shot mode" line.byte 0x4 "ULPTIOC,ULPT I/O Control Register" bitfld.byte 0x4 6. "TIOGT0,ULPTEVIn Count Control" "0: Always count external events.,1: Count external events while the ULPTEVIn pin is.." bitfld.byte 0x4 4.--5. "TIPF,ULPTEVIn Input Filter" "0: No filter,1: Filter sampling at PCLKB,?,?" newline bitfld.byte 0x4 2. "TOE,ULPTOn Output Enable" "0: Disable the ULPTOn output.,1: Enable the ULPTOn output." line.byte 0x5 "ULPTISR,ULPT Event Pin Select Register" bitfld.byte 0x5 2. "RCCPSEL2,ULPTEEn Polarity Select" "0: Count external events when low level.,1: Count external events when high level." line.byte 0x6 "ULPTCMSR,ULPT Compare Match Function Select Register" bitfld.byte 0x6 6. "TOPOLB,ULPTOBn Polarity Select" "0: Start the ULPTOBn output with low.,1: Start the ULPTOBn output with high." bitfld.byte 0x6 5. "TOEB,ULPTOBn Output Enable" "0: Disable the ULPTOBn output.,1: Enable the ULPTOBn output." newline bitfld.byte 0x6 4. "TCMEB,Compare Match B Register Enable" "0: Disable compare match B register.,1: Enable compare match B register." bitfld.byte 0x6 2. "TOPOLA,ULPTOAn Polarity Select" "0: Start the ULPTOAn output with low.,1: Start the ULPTOAn output with high." newline bitfld.byte 0x6 1. "TOEA,ULPTOAn Output Enable" "0: Disable the ULPTOAn output.,1: Enable the ULPTOAn output." bitfld.byte 0x6 0. "TCMEA,Compare Match A Register Enable" "0: Disable compare match A register.,1: Enable compare match A register." tree.end tree.end tree "USBFS (USB 2.0 Full-Speed Module)" base ad:0x0 tree "USBFS" base ad:0x40250000 group.word 0x0++0x1 line.word 0x0 "SYSCFG,System Configuration Control Register" bitfld.word 0x0 10. "SCKE,USB Clock Enable" "0: Stop clock supply to the USBFS,1: Enable clock supply to the USBFS" bitfld.word 0x0 6. "DCFM,Controller Function Select" "0: Select device controller,1: Select host controller" newline bitfld.word 0x0 5. "DRPD,D+/D– Line Resistor Control" "0: Disable line pull-down,1: Enable line pull-down" bitfld.word 0x0 4. "DPRPU,D+ Line Resistor Control" "0: Disable line pull-up,1: Enable line pull-up" newline bitfld.word 0x0 0. "USBE,USBFS Operation Enable" "0: Disable,1: Enable" rgroup.word 0x4++0x1 line.word 0x0 "SYSSTS0,System Configuration Status Register 0" bitfld.word 0x0 14.--15. "OVCMON,External USB_OVRCURA USB_OVRCURA-DS USB_OVRCURB or USB_OVRCURB-DS Input Pin Monitor" "0,1,2,3" bitfld.word 0x0 6. "HTACT,USB Host Sequencer Status Monitor" "0: Host sequencer completely stopped,1: Host sequencer not completely stopped" newline bitfld.word 0x0 5. "SOFEA,Active Monitor When the Host Controller Is Selected" "0: SOF output stopped,1: SOF output operating" bitfld.word 0x0 2. "IDMON,External ID0 Input Pin Monitor" "0: USB_ID pin is low,1: USB_ID pin is high" newline bitfld.word 0x0 0.--1. "LNST,USB Data Line Status Monitor" "0,1,2,3" group.word 0x8++0x1 line.word 0x0 "DVSTCTR0,Device State Control Register 0" bitfld.word 0x0 11. "HNPBTOA,Host Negotiation Protocol (HNP) Control" "0,1" bitfld.word 0x0 10. "EXICEN,USB_EXICEN Output Pin Control" "0: Output low on external USB_EXICEN pin,1: Output high on external USB_EXICEN pin" newline bitfld.word 0x0 9. "VBUSEN,USB_VBUSEN Output Pin Control" "0: Output low on external USB_VBUSEN pin,1: Output high on external USB_VBUSEN pin" bitfld.word 0x0 8. "WKUP,Wakeup Output" "0: Do not output remote wakeup signal,1: Output remote wakeup signal" newline bitfld.word 0x0 7. "RWUPE,Wakeup Detection Enable" "0: Disable downstream port remote wakeup,1: Enable downstream port remote wakeup" bitfld.word 0x0 6. "USBRST,USB Bus Reset Output" "0: Do not output USB bus reset signal,1: Output USB bus reset signal" newline bitfld.word 0x0 5. "RESUME,Resume Output" "0: Do not output resume signal,1: Output resume signal" bitfld.word 0x0 4. "UACT,USB Bus Enable" "0: Disable downstream port (disable SOF transmission),1: Enable downstream port (enable SOF transmission)" newline rbitfld.word 0x0 0.--2. "RHST,USB Bus Reset Status" "0: In host controller mode: USB bus reset in..,1: In host controller mode: Low-speed connection In..,?,?,?,?,?,?" group.word 0x14++0x1 line.word 0x0 "CFIFO,CFIFO Port Register" hexmask.word 0x0 0.--15. 1. "FIFOPORT,FIFO Port" group.byte 0x14++0x0 line.byte 0x0 "CFIFOL,CFIFO Port Register" hexmask.byte 0x0 0.--7. 1. "FIFOPORT,FIFO Port" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x18)++0x1 line.word 0x0 "D$1FIFO,D%sFIFO Port Register" hexmask.word 0x0 0.--15. 1. "FIFOPORT,FIFO Port" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x18)++0x0 line.byte 0x0 "D$1FIFOL,D%sFIFO Port Register" hexmask.byte 0x0 0.--7. 1. "FIFOPORT,FIFO Port" repeat.end group.word 0x20++0x3 line.word 0x0 "CFIFOSEL,CFIFO Port Select Register" bitfld.word 0x0 15. "RCNT,Read Count Mode" "0: The DTLN[8:0] bits (CFIFOCTR.DTLN[8:0]..,1: The DTLN[8:0] bits are decremented each time the.." bitfld.word 0x0 14. "REW,Buffer Pointer Rewind" "0: Do not rewind buffer pointer,1: Rewind buffer pointer" newline bitfld.word 0x0 10. "MBW,CFIFO Port Access Bit Width" "0: 8-bit width,1: 16-bit width" bitfld.word 0x0 8. "BIGEND,CFIFO Port Endian Control" "0: Little endian,1: Big endian" newline bitfld.word 0x0 5. "ISEL,CFIFO Port Access Direction When DCP Is Selected" "0: Select reading from the FIFO buffer,1: Select writing to the FIFO buffer" hexmask.word.byte 0x0 0.--3. 1. "CURPIPE,CFIFO Port Access Pipe Specification" line.word 0x2 "CFIFOCTR,CFIFO Port Control Register" bitfld.word 0x2 15. "BVAL,Buffer Memory Valid Flag" "0: Invalid (writing 0 has no effect),1: Writing ended" bitfld.word 0x2 14. "BCLR,CPU Buffer Clear" "0: No operation,1: Clear FIFO buffer on the CPU side" newline rbitfld.word 0x2 13. "FRDY,FIFO Port Ready" "0: FIFO port access disabled,1: FIFO port access enabled" hexmask.word 0x2 0.--8. 1. "DTLN,Receive Data Length" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x28)++0x1 line.word 0x0 "D$1FIFOSEL,D%sFIFO Port Select Register" bitfld.word 0x0 15. "RCNT,Read Count Mode" "0: Clear DTLN[8:0] bits in (CFIFOCTR.DTLN[8:0]..,1: Decrement DTLN[8:0] bits each time receive data.." bitfld.word 0x0 14. "REW,Buffer Pointer Rewind" "0: Do not rewind buffer pointer,1: Rewind buffer pointer" newline bitfld.word 0x0 13. "DCLRM,Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read" "0: Disable auto buffer clear mode,1: Enable auto buffer clear mode" bitfld.word 0x0 12. "DREQE,DMA/DTC Transfer Request Enable" "0: Disable DMA/DTC transfer request,1: Enable DMA/DTC transfer request" newline bitfld.word 0x0 10. "MBW,FIFO Port Access Bit Width" "0: 8-bit width,1: 16-bit width" bitfld.word 0x0 8. "BIGEND,FIFO Port Endian Control" "0: Little endian,1: Big endian" newline hexmask.word.byte 0x0 0.--3. 1. "CURPIPE,FIFO Port Access Pipe Specification" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x2A)++0x1 line.word 0x0 "D$1FIFOCTR,D%sFIFO Port Control Register" bitfld.word 0x0 15. "BVAL,Buffer Memory Valid Flag" "0: Invalid (writing 0 has no effect),1: Writing ended" bitfld.word 0x0 14. "BCLR,CPU Buffer Clear" "0: No operation,1: Clear FIFO buffer on the CPU side" newline rbitfld.word 0x0 13. "FRDY,FIFO Port Ready" "0: FIFO port access disabled,1: FIFO port access enabled" hexmask.word 0x0 0.--8. 1. "DTLN,Receive Data Length" repeat.end group.word 0x30++0x3 line.word 0x0 "INTENB0,Interrupt Enable Register 0" bitfld.word 0x0 15. "VBSE,VBUS Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 14. "RSME,Resume Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x0 13. "SOFE,Frame Number Update Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 12. "DVSE,Device State Transition Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x0 11. "CTRE,Control Transfer Stage Transition Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 10. "BEMPE,Buffer Empty Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x0 9. "NRDYE,Buffer Not Ready Response Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 8. "BRDYE,Buffer Ready Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" line.word 0x2 "INTENB1,Interrupt Enable Register 1" bitfld.word 0x2 15. "OVRCRE,Overcurrent Input Change Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x2 14. "BCHGE,USB Bus Change Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x2 12. "DTCHE,Disconnection Detection Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x2 11. "ATTCHE,Connection Detection Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x2 6. "EOFERRE,EOF Error Detection Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x2 5. "SIGNE,Setup Transaction Error Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x2 4. "SACKE,Setup Transaction Normal Response Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" group.word 0x36++0x7 line.word 0x0 "BRDYENB,BRDY Interrupt Enable Register" bitfld.word 0x0 9. "PIPE9BRDYE,BRDY Interrupt Enable for Pipe 9" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 8. "PIPE8BRDYE,BRDY Interrupt Enable for Pipe 8" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x0 7. "PIPE7BRDYE,BRDY Interrupt Enable for Pipe 7" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 6. "PIPE6BRDYE,BRDY Interrupt Enable for Pipe 6" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x0 5. "PIPE5BRDYE,BRDY Interrupt Enable for Pipe 5" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 4. "PIPE4BRDYE,BRDY Interrupt Enable for Pipe 4" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x0 3. "PIPE3BRDYE,BRDY Interrupt Enable for Pipe 3" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 2. "PIPE2BRDYE,BRDY Interrupt Enable for Pipe 2" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x0 1. "PIPE1BRDYE,BRDY Interrupt Enable for Pipe 1" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 0. "PIPE0BRDYE,BRDY Interrupt Enable for Pipe 0" "0: Disable interrupt request,1: Enable interrupt request" line.word 0x2 "NRDYENB,NRDY Interrupt Enable Register" bitfld.word 0x2 9. "PIPE9NRDYE,NRDY Interrupt Enable for Pipe 9" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x2 8. "PIPE8NRDYE,NRDY Interrupt Enable for Pipe 8" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x2 7. "PIPE7NRDYE,NRDY Interrupt Enable for Pipe 7" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x2 6. "PIPE6NRDYE,NRDY Interrupt Enable for Pipe 6" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x2 5. "PIPE5NRDYE,NRDY Interrupt Enable for Pipe 5" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x2 4. "PIPE4NRDYE,NRDY Interrupt Enable for Pipe 4" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x2 3. "PIPE3NRDYE,NRDY Interrupt Enable for Pipe 3" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x2 2. "PIPE2NRDYE,NRDY Interrupt Enable for Pipe 2" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x2 1. "PIPE1NRDYE,NRDY Interrupt Enable for Pipe 1" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x2 0. "PIPE0NRDYE,NRDY Interrupt Enable for Pipe 0" "0: Disable interrupt request,1: Enable interrupt request" line.word 0x4 "BEMPENB,BEMP Interrupt Enable Register" bitfld.word 0x4 9. "PIPE9BEMPE,BEMP Interrupt Enable for Pipe 9" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x4 8. "PIPE8BEMPE,BEMP Interrupt Enable for Pipe 8" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x4 7. "PIPE7BEMPE,BEMP Interrupt Enable for Pipe 7" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x4 6. "PIPE6BEMPE,BEMP Interrupt Enable for Pipe 6" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x4 5. "PIPE5BEMPE,BEMP Interrupt Enable for Pipe 5" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x4 4. "PIPE4BEMPE,BEMP Interrupt Enable for Pipe 4" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x4 3. "PIPE3BEMPE,BEMP Interrupt Enable for Pipe 3" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x4 2. "PIPE2BEMPE,BEMP Interrupt Enable for Pipe 2" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x4 1. "PIPE1BEMPE,BEMP Interrupt Enable for Pipe 1" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x4 0. "PIPE0BEMPE,BEMP Interrupt Enable for Pipe 0" "0: Disable interrupt request,1: Enable interrupt request" line.word 0x6 "SOFCFG,SOF Output Configuration Register" bitfld.word 0x6 8. "TRNENSEL,Transaction-Enabled Time Select" "0: Not low-speed communication,1: Low-speed communication" bitfld.word 0x6 6. "BRDYM,BRDY Interrupt Status Clear Timing" "0: Clear BRDY flag by software,1: Clear BRDY flag by the USBFS through a data read.." newline rbitfld.word 0x6 4. "EDGESTS,Edge Interrupt Output Status Monitor" "0,1" group.word 0x40++0x3 line.word 0x0 "INTSTS0,Interrupt Status Register 0" bitfld.word 0x0 15. "VBINT,VBUS Interrupt Status" "0: No VBUS interrupt occurred,1: VBUS interrupt occurred" bitfld.word 0x0 14. "RESM,Resume Interrupt Status" "0: No resume interrupt occurred,1: Resume interrupt occurred" newline bitfld.word 0x0 13. "SOFR,Frame Number Refresh Interrupt Status" "0: No SOF interrupt occurred,1: SOF interrupt occurred" bitfld.word 0x0 12. "DVST,Device State Transition Interrupt Status" "0: No device state transition interrupt occurred,1: Device state transition interrupt occurred" newline bitfld.word 0x0 11. "CTRT,Control Transfer Stage Transition Interrupt Status" "0: No control transfer stage transition interrupt..,1: Control transfer stage transition interrupt.." rbitfld.word 0x0 10. "BEMP,Buffer Empty Interrupt Status" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" newline rbitfld.word 0x0 9. "NRDY,Buffer Not Ready Interrupt Status" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" rbitfld.word 0x0 8. "BRDY,Buffer Ready Interrupt Status" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" newline rbitfld.word 0x0 7. "VBSTS,VBUS Input Status" "0: USB_VBUS pin is low,1: USB_VBUS pin is high" rbitfld.word 0x0 4.--6. "DVSQ,Device State" "0: Suspend state,1: Default state,?,?,?,?,?,?" newline bitfld.word 0x0 3. "VALID,USB Request Reception" "0: Setup packet not received,1: Setup packet received" rbitfld.word 0x0 0.--2. "CTSQ,Control Transfer Stage" "0: Idle or setup stage,1: Control read data stage,?,?,?,?,?,?" line.word 0x2 "INTSTS1,Interrupt Status Register 1" bitfld.word 0x2 15. "OVRCR,Overcurrent Input Change Interrupt Status" "0: No OVRCR interrupt occurred,1: OVRCR interrupt occurred" bitfld.word 0x2 14. "BCHG,USB Bus Change Interrupt Status" "0: No BCHG interrupt occurred,1: BCHG interrupt occurred" newline bitfld.word 0x2 12. "DTCH,USB Disconnection Detection Interrupt Status" "0: No DTCH interrupt occurred,1: DTCH interrupt occurred" bitfld.word 0x2 11. "ATTCH,ATTCH Interrupt Status" "0: No ATTCH interrupt occurred,1: ATTCH interrupt occurred" newline bitfld.word 0x2 6. "EOFERR,EOF Error Detection Interrupt Status" "0: No EOFERR interrupt occurred,1: EOFERR interrupt occurred" bitfld.word 0x2 5. "SIGN,Setup Transaction Error Interrupt Status" "0: No SIGN interrupt occurred,1: SIGN interrupt occurred" newline bitfld.word 0x2 4. "SACK,Setup Transaction Normal Response Interrupt Status" "0: No SACK interrupt occurred,1: SACK interrupt occurred" group.word 0x46++0xB line.word 0x0 "BRDYSTS,BRDY Interrupt Status Register" bitfld.word 0x0 9. "PIPE9BRDY,BRDY Interrupt Status for Pipe 9" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" bitfld.word 0x0 8. "PIPE8BRDY,BRDY Interrupt Status for Pipe 8" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" newline bitfld.word 0x0 7. "PIPE7BRDY,BRDY Interrupt Status for Pipe 7" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" bitfld.word 0x0 6. "PIPE6BRDY,BRDY Interrupt Status for Pipe 6" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" newline bitfld.word 0x0 5. "PIPE5BRDY,BRDY Interrupt Status for Pipe 5" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" bitfld.word 0x0 4. "PIPE4BRDY,BRDY Interrupt Status for Pipe 4" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" newline bitfld.word 0x0 3. "PIPE3BRDY,BRDY Interrupt Status for Pipe 3" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" bitfld.word 0x0 2. "PIPE2BRDY,BRDY Interrupt Status for Pipe 2" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" newline bitfld.word 0x0 1. "PIPE1BRDY,BRDY Interrupt Status for Pipe 1" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" bitfld.word 0x0 0. "PIPE0BRDY,BRDY Interrupt Status for Pipe 0" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" line.word 0x2 "NRDYSTS,NRDY Interrupt Status Register" bitfld.word 0x2 9. "PIPE9NRDY,NRDY Interrupt Status for Pipe 9" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" bitfld.word 0x2 8. "PIPE8NRDY,NRDY Interrupt Status for Pipe 8" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" newline bitfld.word 0x2 7. "PIPE7NRDY,NRDY Interrupt Status for Pipe 7" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" bitfld.word 0x2 6. "PIPE6NRDY,NRDY Interrupt Status for Pipe 6" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" newline bitfld.word 0x2 5. "PIPE5NRDY,NRDY Interrupt Status for Pipe 5" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" bitfld.word 0x2 4. "PIPE4NRDY,NRDY Interrupt Status for Pipe 4" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" newline bitfld.word 0x2 3. "PIPE3NRDY,NRDY Interrupt Status for Pipe 3" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" bitfld.word 0x2 2. "PIPE2NRDY,NRDY Interrupt Status for Pipe 2" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" newline bitfld.word 0x2 1. "PIPE1NRDY,NRDY Interrupt Status for Pipe 1" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" bitfld.word 0x2 0. "PIPE0NRDY,NRDY Interrupt Status for Pipe 0" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" line.word 0x4 "BEMPSTS,BEMP Interrupt Status Register" bitfld.word 0x4 9. "PIPE9BEMP,BEMP Interrupt Status for Pipe 9" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" bitfld.word 0x4 8. "PIPE8BEMP,BEMP Interrupt Status for Pipe 8" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" newline bitfld.word 0x4 7. "PIPE7BEMP,BEMP Interrupt Status for Pipe 7" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" bitfld.word 0x4 6. "PIPE6BEMP,BEMP Interrupt Status for Pipe 6" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" newline bitfld.word 0x4 5. "PIPE5BEMP,BEMP Interrupt Status for Pipe 5" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" bitfld.word 0x4 4. "PIPE4BEMP,BEMP Interrupt Status for Pipe 4" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" newline bitfld.word 0x4 3. "PIPE3BEMP,BEMP Interrupt Status for Pipe 3" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" bitfld.word 0x4 2. "PIPE2BEMP,BEMP Interrupt Status for Pipe 2" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" newline bitfld.word 0x4 1. "PIPE1BEMP,BEMP Interrupt Status for Pipe 1" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" bitfld.word 0x4 0. "PIPE0BEMP,BEMP Interrupt Status for Pipe 0" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" line.word 0x6 "FRMNUM,Frame Number Register" bitfld.word 0x6 15. "OVRN,Overrun/Underrun Detection Status" "0: No error occurred,1: Error occurred" bitfld.word 0x6 14. "CRCE,Receive Data Error" "0: No error occurred,1: Error occurred" newline hexmask.word 0x6 0.--10. 1. "FRNM,Frame Number" line.word 0x8 "DVCHGR,Device State Change Register" bitfld.word 0x8 15. "DVCHG,Device State Change" "0: Disable writes to the USBADDR.STSRECOV[3:0] and..,1: Enable writes to the USBADDR.STSRECOV[3:0] and.." line.word 0xA "USBADDR,USB Address Register" hexmask.word.byte 0xA 8.--11. 1. "STSRECOV,Status Recovery" hexmask.word.byte 0xA 0.--6. 1. "USBADDR,USB Address" group.word 0x54++0xD line.word 0x0 "USBREQ,USB Request Type Register" hexmask.word.byte 0x0 8.--15. 1. "BREQUEST,Request" hexmask.word.byte 0x0 0.--7. 1. "BMREQUESTTYPE,Request Type" line.word 0x2 "USBVAL,USB Request Value Register" hexmask.word 0x2 0.--15. 1. "WVALUE,Value" line.word 0x4 "USBINDX,USB Request Index Register" hexmask.word 0x4 0.--15. 1. "WINDEX,Index" line.word 0x6 "USBLENG,USB Request Length Register" hexmask.word 0x6 0.--15. 1. "WLENTUH,Length" line.word 0x8 "DCPCFG,DCP Configuration Register" bitfld.word 0x8 7. "SHTNAK,Pipe Disabled at End of Transfer" "0: Keep pipe open after transfer ends,1: Disable pipe after transfer ends" bitfld.word 0x8 4. "DIR,Transfer Direction" "0: Data receiving direction,1: Data transmitting direction" line.word 0xA "DCPMAXP,DCP Maximum Packet Size Register" hexmask.word.byte 0xA 12.--15. 1. "DEVSEL,Device Select" hexmask.word.byte 0xA 0.--6. 1. "MXPS,Maximum Packet Size" line.word 0xC "DCPCTR,DCP Control Register" rbitfld.word 0xC 15. "BSTS,Buffer Status" "0: Buffer access disabled,1: Buffer access enabled" bitfld.word 0xC 14. "SUREQ,Setup Token Transmission" "0: Invalid (writing 0 has no effect),1: Transmit setup packet" newline bitfld.word 0xC 11. "SUREQCLR,SUREQ Bit Clear" "0: Invalid (writing 0 has no effect),1: Clear SUREQ to 0" bitfld.word 0xC 8. "SQCLR,Sequence Toggle Bit Clear" "0: Invalid (writing 0 has no effect),1: Clear the expected value for the next.." newline bitfld.word 0xC 7. "SQSET,Sequence Toggle Bit Set" "0: Invalid (writing 0 has no effect),1: Set the expected value for the next transaction.." rbitfld.word 0xC 6. "SQMON,Sequence Toggle Bit Monitor" "0: DATA0,1: DATA1" newline rbitfld.word 0xC 5. "PBUSY,Pipe Busy" "0: DCP not used for the USB bus,1: DCP in use for the USB bus" bitfld.word 0xC 2. "CCPL,Control Transfer End Enable" "0: Disable control transfer completion,1: Enable control transfer completion" newline bitfld.word 0xC 0.--1. "PID,Response PID" "0: NAK response,1: BUF response (depends on the buffer state),?,?" group.word 0x64++0x1 line.word 0x0 "PIPESEL,Pipe Window Select Register" hexmask.word.byte 0x0 0.--3. 1. "PIPESEL,Pipe Window Select" group.word 0x68++0x1 line.word 0x0 "PIPECFG,Pipe Configuration Register" bitfld.word 0x0 14.--15. "TYPE,Transfer Type" "0: Pipe not used,1: Pipes 1 and 2: Bulk transfer Pipes 3 to 5: Bulk..,?,?" bitfld.word 0x0 10. "BFRE,BRDY Interrupt Operation Specification" "0: Generate BRDY interrupt on transmitting or..,1: Generate BRDY interrupt on completion of reading.." newline bitfld.word 0x0 9. "DBLB,Double Buffer Mode" "0: Single buffer,1: Double buffer" bitfld.word 0x0 7. "SHTNAK,Pipe Disabled at End of Transfer" "0: Continue pipe operation after transfer ends,1: Disable pipe after transfer ends" newline bitfld.word 0x0 4. "DIR,Transfer Direction" "0: Receiving direction,1: Transmitting direction" hexmask.word.byte 0x0 0.--3. 1. "EPNUM,Endpoint Number" group.word 0x6C++0x3 line.word 0x0 "PIPEMAXP,Pipe Maximum Packet Size Register" hexmask.word.byte 0x0 12.--15. 1. "DEVSEL,Device Select" hexmask.word 0x0 0.--8. 1. "MXPS,Maximum Packet Size" line.word 0x2 "PIPEPERI,Pipe Cycle Control Register" bitfld.word 0x2 12. "IFIS,Isochronous IN Buffer Flush" "0: Do not flush buffer,1: Flush buffer" bitfld.word 0x2 0.--2. "IITV,Interval Error Detection Interval" "0,1,2,3,4,5,6,7" repeat 5. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0x70)++0x1 line.word 0x0 "PIPE$1CTR,PIPE%s Control Registers" rbitfld.word 0x0 15. "BSTS,Buffer Status" "0: Buffer access by the CPU disabled,1: Buffer access by the CPU enabled" rbitfld.word 0x0 14. "INBUFM,Transmit Buffer Monitor" "0: No data to be transmitted is in the FIFO buffer,1: Data to be transmitted is in the FIFO buffer" newline bitfld.word 0x0 10. "ATREPM,Auto Response Mode" "0: Disable auto response mode,1: Enable auto response mode" bitfld.word 0x0 9. "ACLRM,Auto Buffer Clear Mode" "0: Disable,1: Enable (initialize all buffers)" newline bitfld.word 0x0 8. "SQCLR,Sequence Toggle Bit Clear" "0: Invalid (writing 0 has no effect),1: Clear the expected value for the next.." bitfld.word 0x0 7. "SQSET,Sequence Toggle Bit Set" "0: Invalid (writing 0 has no effect),1: Set the expected value for the next transaction.." newline rbitfld.word 0x0 6. "SQMON,Sequence Toggle Bit Confirmation" "0: DATA0,1: DATA1" rbitfld.word 0x0 5. "PBUSY,Pipe Busy" "0: Pipe n not in use for the transaction,1: Pipe n in use for the transaction" newline bitfld.word 0x0 0.--1. "PID,Response PID" "0: NAK response,1: BUF response (depends buffer state),?,?" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0x7A)++0x1 line.word 0x0 "PIPE$1CTR,PIPE%s Control Registers" rbitfld.word 0x0 15. "BSTS,Buffer Status" "0: Buffer access disabled,1: Buffer access enabled" bitfld.word 0x0 9. "ACLRM,Auto Buffer Clear Mode" "0: Disable,1: Enable (all buffers initialized)" newline bitfld.word 0x0 8. "SQCLR,Sequence Toggle Bit Clear" "0: Invalid (writing 0 has no effect),1: Clear the expected value for the next.." bitfld.word 0x0 7. "SQSET,Sequence Toggle Bit Set" "0: Invalid (writing 0 has no effect),1: Set the expected value for the next transaction.." newline rbitfld.word 0x0 6. "SQMON,Sequence Toggle Bit Confirmation" "0: DATA0,1: DATA1" rbitfld.word 0x0 5. "PBUSY,Pipe Busy" "0: Pipe n not in use for the transaction,1: Pipe n in use for the transaction" newline bitfld.word 0x0 0.--1. "PID,Response PID" "0: NAK response,1: BUF response (depends buffer state),?,?" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x90)++0x1 line.word 0x0 "PIPE$1TRE,PIPE%s Transaction Counter Enable Register" bitfld.word 0x0 9. "TRENB,Transaction Counter Enable" "0: Disable transaction counter,1: Enable transaction counter" bitfld.word 0x0 8. "TRCLR,Transaction Counter Clear" "0: Invalid (writing 0 has no effect),1: Clear counter value" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x92)++0x1 line.word 0x0 "PIPE$1TRN,PIPE%s Transaction Counter Register" hexmask.word 0x0 0.--15. 1. "TRNCNT,Transaction Counter" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0xD0)++0x1 line.word 0x0 "DEVADD$1,Device Address %s Configuration Register" bitfld.word 0x0 6.--7. "USBSPD,Transfer Speed of Communication Target Device" "0: Do not use DEVADDn,1: Low-speed,?,?" repeat.end group.long 0x400++0x7 line.long 0x0 "DPUSR0R,Deep Software Standby USB Transceiver Control/Pin Monitor Register" rbitfld.long 0x0 23. "DVBSTS0,USB VBUS Input" "0,1" rbitfld.long 0x0 21. "DOVCB0,USB OVRCURB-DS Input" "0,1" newline rbitfld.long 0x0 20. "DOVCA0,USB OVRCURA-DS Input" "0,1" rbitfld.long 0x0 17. "DM0,USB D- Input" "0,1" newline rbitfld.long 0x0 16. "DP0,USB D+ Input" "0,1" bitfld.long 0x0 4. "FIXPHY0,USB Transceiver Output Fix" "0: Fix outputs in Normal mode and on return from..,1: Fix outputs on transition to Deep Software.." newline bitfld.long 0x0 3. "DRPD0,D+/D- Pull-Down Resistor Control" "0: Disable DP/DM pull-down resistor,1: Enable DP/DM pull-down resistor" bitfld.long 0x0 1. "RPUE0,DP Pull-Up Resistor Control" "0: Disable DP pull-up resistor,1: Enable DP pull-up resistor" newline bitfld.long 0x0 0. "SRPC0,USB Single-ended Receiver Control" "0: Disable input through DP and DM inputs,1: Enable input through DP and DM inputs" line.long 0x4 "DPUSR1R,Deep Software Standby USB Suspend/Resume Interrupt Register" rbitfld.long 0x4 23. "DVBINT0,USB VBUS Interrupt Source Recovery" "0: System has not recovered from Deep Software..,1: System recovered from Deep Software Standby mode.." rbitfld.long 0x4 21. "DOVRCRB0,USB OVRCURB-DS Interrupt Source Recovery" "0: System has not recovered from Deep Software..,1: System recovered from Deep Software Standby mode.." newline rbitfld.long 0x4 20. "DOVRCRA0,USB OVRCURA-DS Interrupt Source Recovery" "0: System has not recovered from Deep Software..,1: System recovered from Deep Software Standby mode.." rbitfld.long 0x4 17. "DMINT0,USB DM Interrupt Source Recovery" "0: System has not recovered from Deep Software..,1: System recovered from Deep Software Standby mode.." newline rbitfld.long 0x4 16. "DPINT0,USB DP Interrupt Source Recovery" "0: System has not recovered from Deep Software..,1: System recovered from Deep Software Standby mode.." bitfld.long 0x4 7. "DVBSE0,USB VBUS Interrupt Enable/Clear" "0: Disable recovery from Deep Software Standby mode..,1: Enable recovery from Deep Software Standby mode.." newline bitfld.long 0x4 5. "DOVRCRBE0,USB OVRCURB-DS Interrupt Enable/Clear" "0: Disable recovery from Deep Software Standby mode..,1: Enable recovery from Deep Software Standby mode.." bitfld.long 0x4 4. "DOVRCRAE0,USB OVRCURA-DS Interrupt Enable/Clear" "0: Disable recovery from Deep Software Standby mode..,1: Enable recovery from Deep Software Standby mode.." newline bitfld.long 0x4 1. "DMINTE0,USB DM Interrupt Enable/Clear" "0: Disable recovery from Deep Software Standby mode..,1: Enable recovery from Deep Software Standby mode.." bitfld.long 0x4 0. "DPINTE0,USB DP Interrupt Enable/Clear" "0: Disable recovery from Deep Software Standby mode..,1: Enable recovery from Deep Software Standby mode.." tree.end tree "USBFS_NS" base ad:0x50250000 group.word 0x0++0x1 line.word 0x0 "SYSCFG,System Configuration Control Register" bitfld.word 0x0 10. "SCKE,USB Clock Enable" "0: Stop clock supply to the USBFS,1: Enable clock supply to the USBFS" bitfld.word 0x0 6. "DCFM,Controller Function Select" "0: Select device controller,1: Select host controller" newline bitfld.word 0x0 5. "DRPD,D+/D– Line Resistor Control" "0: Disable line pull-down,1: Enable line pull-down" bitfld.word 0x0 4. "DPRPU,D+ Line Resistor Control" "0: Disable line pull-up,1: Enable line pull-up" newline bitfld.word 0x0 0. "USBE,USBFS Operation Enable" "0: Disable,1: Enable" rgroup.word 0x4++0x1 line.word 0x0 "SYSSTS0,System Configuration Status Register 0" bitfld.word 0x0 14.--15. "OVCMON,External USB_OVRCURA USB_OVRCURA-DS USB_OVRCURB or USB_OVRCURB-DS Input Pin Monitor" "0,1,2,3" bitfld.word 0x0 6. "HTACT,USB Host Sequencer Status Monitor" "0: Host sequencer completely stopped,1: Host sequencer not completely stopped" newline bitfld.word 0x0 5. "SOFEA,Active Monitor When the Host Controller Is Selected" "0: SOF output stopped,1: SOF output operating" bitfld.word 0x0 2. "IDMON,External ID0 Input Pin Monitor" "0: USB_ID pin is low,1: USB_ID pin is high" newline bitfld.word 0x0 0.--1. "LNST,USB Data Line Status Monitor" "0,1,2,3" group.word 0x8++0x1 line.word 0x0 "DVSTCTR0,Device State Control Register 0" bitfld.word 0x0 11. "HNPBTOA,Host Negotiation Protocol (HNP) Control" "0,1" bitfld.word 0x0 10. "EXICEN,USB_EXICEN Output Pin Control" "0: Output low on external USB_EXICEN pin,1: Output high on external USB_EXICEN pin" newline bitfld.word 0x0 9. "VBUSEN,USB_VBUSEN Output Pin Control" "0: Output low on external USB_VBUSEN pin,1: Output high on external USB_VBUSEN pin" bitfld.word 0x0 8. "WKUP,Wakeup Output" "0: Do not output remote wakeup signal,1: Output remote wakeup signal" newline bitfld.word 0x0 7. "RWUPE,Wakeup Detection Enable" "0: Disable downstream port remote wakeup,1: Enable downstream port remote wakeup" bitfld.word 0x0 6. "USBRST,USB Bus Reset Output" "0: Do not output USB bus reset signal,1: Output USB bus reset signal" newline bitfld.word 0x0 5. "RESUME,Resume Output" "0: Do not output resume signal,1: Output resume signal" bitfld.word 0x0 4. "UACT,USB Bus Enable" "0: Disable downstream port (disable SOF transmission),1: Enable downstream port (enable SOF transmission)" newline rbitfld.word 0x0 0.--2. "RHST,USB Bus Reset Status" "0: In host controller mode: USB bus reset in..,1: In host controller mode: Low-speed connection In..,?,?,?,?,?,?" group.word 0x14++0x1 line.word 0x0 "CFIFO,CFIFO Port Register" hexmask.word 0x0 0.--15. 1. "FIFOPORT,FIFO Port" group.byte 0x14++0x0 line.byte 0x0 "CFIFOL,CFIFO Port Register" hexmask.byte 0x0 0.--7. 1. "FIFOPORT,FIFO Port" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x18)++0x1 line.word 0x0 "D$1FIFO,D%sFIFO Port Register" hexmask.word 0x0 0.--15. 1. "FIFOPORT,FIFO Port" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x18)++0x0 line.byte 0x0 "D$1FIFOL,D%sFIFO Port Register" hexmask.byte 0x0 0.--7. 1. "FIFOPORT,FIFO Port" repeat.end group.word 0x20++0x3 line.word 0x0 "CFIFOSEL,CFIFO Port Select Register" bitfld.word 0x0 15. "RCNT,Read Count Mode" "0: The DTLN[8:0] bits (CFIFOCTR.DTLN[8:0]..,1: The DTLN[8:0] bits are decremented each time the.." bitfld.word 0x0 14. "REW,Buffer Pointer Rewind" "0: Do not rewind buffer pointer,1: Rewind buffer pointer" newline bitfld.word 0x0 10. "MBW,CFIFO Port Access Bit Width" "0: 8-bit width,1: 16-bit width" bitfld.word 0x0 8. "BIGEND,CFIFO Port Endian Control" "0: Little endian,1: Big endian" newline bitfld.word 0x0 5. "ISEL,CFIFO Port Access Direction When DCP Is Selected" "0: Select reading from the FIFO buffer,1: Select writing to the FIFO buffer" hexmask.word.byte 0x0 0.--3. 1. "CURPIPE,CFIFO Port Access Pipe Specification" line.word 0x2 "CFIFOCTR,CFIFO Port Control Register" bitfld.word 0x2 15. "BVAL,Buffer Memory Valid Flag" "0: Invalid (writing 0 has no effect),1: Writing ended" bitfld.word 0x2 14. "BCLR,CPU Buffer Clear" "0: No operation,1: Clear FIFO buffer on the CPU side" newline rbitfld.word 0x2 13. "FRDY,FIFO Port Ready" "0: FIFO port access disabled,1: FIFO port access enabled" hexmask.word 0x2 0.--8. 1. "DTLN,Receive Data Length" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x28)++0x1 line.word 0x0 "D$1FIFOSEL,D%sFIFO Port Select Register" bitfld.word 0x0 15. "RCNT,Read Count Mode" "0: Clear DTLN[8:0] bits in (CFIFOCTR.DTLN[8:0]..,1: Decrement DTLN[8:0] bits each time receive data.." bitfld.word 0x0 14. "REW,Buffer Pointer Rewind" "0: Do not rewind buffer pointer,1: Rewind buffer pointer" newline bitfld.word 0x0 13. "DCLRM,Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read" "0: Disable auto buffer clear mode,1: Enable auto buffer clear mode" bitfld.word 0x0 12. "DREQE,DMA/DTC Transfer Request Enable" "0: Disable DMA/DTC transfer request,1: Enable DMA/DTC transfer request" newline bitfld.word 0x0 10. "MBW,FIFO Port Access Bit Width" "0: 8-bit width,1: 16-bit width" bitfld.word 0x0 8. "BIGEND,FIFO Port Endian Control" "0: Little endian,1: Big endian" newline hexmask.word.byte 0x0 0.--3. 1. "CURPIPE,FIFO Port Access Pipe Specification" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x2A)++0x1 line.word 0x0 "D$1FIFOCTR,D%sFIFO Port Control Register" bitfld.word 0x0 15. "BVAL,Buffer Memory Valid Flag" "0: Invalid (writing 0 has no effect),1: Writing ended" bitfld.word 0x0 14. "BCLR,CPU Buffer Clear" "0: No operation,1: Clear FIFO buffer on the CPU side" newline rbitfld.word 0x0 13. "FRDY,FIFO Port Ready" "0: FIFO port access disabled,1: FIFO port access enabled" hexmask.word 0x0 0.--8. 1. "DTLN,Receive Data Length" repeat.end group.word 0x30++0x3 line.word 0x0 "INTENB0,Interrupt Enable Register 0" bitfld.word 0x0 15. "VBSE,VBUS Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 14. "RSME,Resume Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x0 13. "SOFE,Frame Number Update Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 12. "DVSE,Device State Transition Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x0 11. "CTRE,Control Transfer Stage Transition Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 10. "BEMPE,Buffer Empty Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x0 9. "NRDYE,Buffer Not Ready Response Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 8. "BRDYE,Buffer Ready Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" line.word 0x2 "INTENB1,Interrupt Enable Register 1" bitfld.word 0x2 15. "OVRCRE,Overcurrent Input Change Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x2 14. "BCHGE,USB Bus Change Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x2 12. "DTCHE,Disconnection Detection Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x2 11. "ATTCHE,Connection Detection Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x2 6. "EOFERRE,EOF Error Detection Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x2 5. "SIGNE,Setup Transaction Error Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x2 4. "SACKE,Setup Transaction Normal Response Interrupt Enable" "0: Disable interrupt request,1: Enable interrupt request" group.word 0x36++0x7 line.word 0x0 "BRDYENB,BRDY Interrupt Enable Register" bitfld.word 0x0 9. "PIPE9BRDYE,BRDY Interrupt Enable for Pipe 9" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 8. "PIPE8BRDYE,BRDY Interrupt Enable for Pipe 8" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x0 7. "PIPE7BRDYE,BRDY Interrupt Enable for Pipe 7" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 6. "PIPE6BRDYE,BRDY Interrupt Enable for Pipe 6" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x0 5. "PIPE5BRDYE,BRDY Interrupt Enable for Pipe 5" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 4. "PIPE4BRDYE,BRDY Interrupt Enable for Pipe 4" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x0 3. "PIPE3BRDYE,BRDY Interrupt Enable for Pipe 3" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 2. "PIPE2BRDYE,BRDY Interrupt Enable for Pipe 2" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x0 1. "PIPE1BRDYE,BRDY Interrupt Enable for Pipe 1" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x0 0. "PIPE0BRDYE,BRDY Interrupt Enable for Pipe 0" "0: Disable interrupt request,1: Enable interrupt request" line.word 0x2 "NRDYENB,NRDY Interrupt Enable Register" bitfld.word 0x2 9. "PIPE9NRDYE,NRDY Interrupt Enable for Pipe 9" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x2 8. "PIPE8NRDYE,NRDY Interrupt Enable for Pipe 8" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x2 7. "PIPE7NRDYE,NRDY Interrupt Enable for Pipe 7" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x2 6. "PIPE6NRDYE,NRDY Interrupt Enable for Pipe 6" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x2 5. "PIPE5NRDYE,NRDY Interrupt Enable for Pipe 5" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x2 4. "PIPE4NRDYE,NRDY Interrupt Enable for Pipe 4" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x2 3. "PIPE3NRDYE,NRDY Interrupt Enable for Pipe 3" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x2 2. "PIPE2NRDYE,NRDY Interrupt Enable for Pipe 2" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x2 1. "PIPE1NRDYE,NRDY Interrupt Enable for Pipe 1" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x2 0. "PIPE0NRDYE,NRDY Interrupt Enable for Pipe 0" "0: Disable interrupt request,1: Enable interrupt request" line.word 0x4 "BEMPENB,BEMP Interrupt Enable Register" bitfld.word 0x4 9. "PIPE9BEMPE,BEMP Interrupt Enable for Pipe 9" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x4 8. "PIPE8BEMPE,BEMP Interrupt Enable for Pipe 8" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x4 7. "PIPE7BEMPE,BEMP Interrupt Enable for Pipe 7" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x4 6. "PIPE6BEMPE,BEMP Interrupt Enable for Pipe 6" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x4 5. "PIPE5BEMPE,BEMP Interrupt Enable for Pipe 5" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x4 4. "PIPE4BEMPE,BEMP Interrupt Enable for Pipe 4" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x4 3. "PIPE3BEMPE,BEMP Interrupt Enable for Pipe 3" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x4 2. "PIPE2BEMPE,BEMP Interrupt Enable for Pipe 2" "0: Disable interrupt request,1: Enable interrupt request" newline bitfld.word 0x4 1. "PIPE1BEMPE,BEMP Interrupt Enable for Pipe 1" "0: Disable interrupt request,1: Enable interrupt request" bitfld.word 0x4 0. "PIPE0BEMPE,BEMP Interrupt Enable for Pipe 0" "0: Disable interrupt request,1: Enable interrupt request" line.word 0x6 "SOFCFG,SOF Output Configuration Register" bitfld.word 0x6 8. "TRNENSEL,Transaction-Enabled Time Select" "0: Not low-speed communication,1: Low-speed communication" bitfld.word 0x6 6. "BRDYM,BRDY Interrupt Status Clear Timing" "0: Clear BRDY flag by software,1: Clear BRDY flag by the USBFS through a data read.." newline rbitfld.word 0x6 4. "EDGESTS,Edge Interrupt Output Status Monitor" "0,1" group.word 0x40++0x3 line.word 0x0 "INTSTS0,Interrupt Status Register 0" bitfld.word 0x0 15. "VBINT,VBUS Interrupt Status" "0: No VBUS interrupt occurred,1: VBUS interrupt occurred" bitfld.word 0x0 14. "RESM,Resume Interrupt Status" "0: No resume interrupt occurred,1: Resume interrupt occurred" newline bitfld.word 0x0 13. "SOFR,Frame Number Refresh Interrupt Status" "0: No SOF interrupt occurred,1: SOF interrupt occurred" bitfld.word 0x0 12. "DVST,Device State Transition Interrupt Status" "0: No device state transition interrupt occurred,1: Device state transition interrupt occurred" newline bitfld.word 0x0 11. "CTRT,Control Transfer Stage Transition Interrupt Status" "0: No control transfer stage transition interrupt..,1: Control transfer stage transition interrupt.." rbitfld.word 0x0 10. "BEMP,Buffer Empty Interrupt Status" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" newline rbitfld.word 0x0 9. "NRDY,Buffer Not Ready Interrupt Status" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" rbitfld.word 0x0 8. "BRDY,Buffer Ready Interrupt Status" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" newline rbitfld.word 0x0 7. "VBSTS,VBUS Input Status" "0: USB_VBUS pin is low,1: USB_VBUS pin is high" rbitfld.word 0x0 4.--6. "DVSQ,Device State" "0: Suspend state,1: Default state,?,?,?,?,?,?" newline bitfld.word 0x0 3. "VALID,USB Request Reception" "0: Setup packet not received,1: Setup packet received" rbitfld.word 0x0 0.--2. "CTSQ,Control Transfer Stage" "0: Idle or setup stage,1: Control read data stage,?,?,?,?,?,?" line.word 0x2 "INTSTS1,Interrupt Status Register 1" bitfld.word 0x2 15. "OVRCR,Overcurrent Input Change Interrupt Status" "0: No OVRCR interrupt occurred,1: OVRCR interrupt occurred" bitfld.word 0x2 14. "BCHG,USB Bus Change Interrupt Status" "0: No BCHG interrupt occurred,1: BCHG interrupt occurred" newline bitfld.word 0x2 12. "DTCH,USB Disconnection Detection Interrupt Status" "0: No DTCH interrupt occurred,1: DTCH interrupt occurred" bitfld.word 0x2 11. "ATTCH,ATTCH Interrupt Status" "0: No ATTCH interrupt occurred,1: ATTCH interrupt occurred" newline bitfld.word 0x2 6. "EOFERR,EOF Error Detection Interrupt Status" "0: No EOFERR interrupt occurred,1: EOFERR interrupt occurred" bitfld.word 0x2 5. "SIGN,Setup Transaction Error Interrupt Status" "0: No SIGN interrupt occurred,1: SIGN interrupt occurred" newline bitfld.word 0x2 4. "SACK,Setup Transaction Normal Response Interrupt Status" "0: No SACK interrupt occurred,1: SACK interrupt occurred" group.word 0x46++0xB line.word 0x0 "BRDYSTS,BRDY Interrupt Status Register" bitfld.word 0x0 9. "PIPE9BRDY,BRDY Interrupt Status for Pipe 9" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" bitfld.word 0x0 8. "PIPE8BRDY,BRDY Interrupt Status for Pipe 8" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" newline bitfld.word 0x0 7. "PIPE7BRDY,BRDY Interrupt Status for Pipe 7" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" bitfld.word 0x0 6. "PIPE6BRDY,BRDY Interrupt Status for Pipe 6" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" newline bitfld.word 0x0 5. "PIPE5BRDY,BRDY Interrupt Status for Pipe 5" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" bitfld.word 0x0 4. "PIPE4BRDY,BRDY Interrupt Status for Pipe 4" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" newline bitfld.word 0x0 3. "PIPE3BRDY,BRDY Interrupt Status for Pipe 3" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" bitfld.word 0x0 2. "PIPE2BRDY,BRDY Interrupt Status for Pipe 2" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" newline bitfld.word 0x0 1. "PIPE1BRDY,BRDY Interrupt Status for Pipe 1" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" bitfld.word 0x0 0. "PIPE0BRDY,BRDY Interrupt Status for Pipe 0" "0: No BRDY interrupt occurred,1: BRDY interrupt occurred" line.word 0x2 "NRDYSTS,NRDY Interrupt Status Register" bitfld.word 0x2 9. "PIPE9NRDY,NRDY Interrupt Status for Pipe 9" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" bitfld.word 0x2 8. "PIPE8NRDY,NRDY Interrupt Status for Pipe 8" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" newline bitfld.word 0x2 7. "PIPE7NRDY,NRDY Interrupt Status for Pipe 7" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" bitfld.word 0x2 6. "PIPE6NRDY,NRDY Interrupt Status for Pipe 6" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" newline bitfld.word 0x2 5. "PIPE5NRDY,NRDY Interrupt Status for Pipe 5" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" bitfld.word 0x2 4. "PIPE4NRDY,NRDY Interrupt Status for Pipe 4" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" newline bitfld.word 0x2 3. "PIPE3NRDY,NRDY Interrupt Status for Pipe 3" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" bitfld.word 0x2 2. "PIPE2NRDY,NRDY Interrupt Status for Pipe 2" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" newline bitfld.word 0x2 1. "PIPE1NRDY,NRDY Interrupt Status for Pipe 1" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" bitfld.word 0x2 0. "PIPE0NRDY,NRDY Interrupt Status for Pipe 0" "0: No NRDY interrupt occurred,1: NRDY interrupt occurred" line.word 0x4 "BEMPSTS,BEMP Interrupt Status Register" bitfld.word 0x4 9. "PIPE9BEMP,BEMP Interrupt Status for Pipe 9" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" bitfld.word 0x4 8. "PIPE8BEMP,BEMP Interrupt Status for Pipe 8" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" newline bitfld.word 0x4 7. "PIPE7BEMP,BEMP Interrupt Status for Pipe 7" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" bitfld.word 0x4 6. "PIPE6BEMP,BEMP Interrupt Status for Pipe 6" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" newline bitfld.word 0x4 5. "PIPE5BEMP,BEMP Interrupt Status for Pipe 5" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" bitfld.word 0x4 4. "PIPE4BEMP,BEMP Interrupt Status for Pipe 4" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" newline bitfld.word 0x4 3. "PIPE3BEMP,BEMP Interrupt Status for Pipe 3" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" bitfld.word 0x4 2. "PIPE2BEMP,BEMP Interrupt Status for Pipe 2" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" newline bitfld.word 0x4 1. "PIPE1BEMP,BEMP Interrupt Status for Pipe 1" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" bitfld.word 0x4 0. "PIPE0BEMP,BEMP Interrupt Status for Pipe 0" "0: No BEMP interrupt occurred,1: BEMP interrupt occurred" line.word 0x6 "FRMNUM,Frame Number Register" bitfld.word 0x6 15. "OVRN,Overrun/Underrun Detection Status" "0: No error occurred,1: Error occurred" bitfld.word 0x6 14. "CRCE,Receive Data Error" "0: No error occurred,1: Error occurred" newline hexmask.word 0x6 0.--10. 1. "FRNM,Frame Number" line.word 0x8 "DVCHGR,Device State Change Register" bitfld.word 0x8 15. "DVCHG,Device State Change" "0: Disable writes to the USBADDR.STSRECOV[3:0] and..,1: Enable writes to the USBADDR.STSRECOV[3:0] and.." line.word 0xA "USBADDR,USB Address Register" hexmask.word.byte 0xA 8.--11. 1. "STSRECOV,Status Recovery" hexmask.word.byte 0xA 0.--6. 1. "USBADDR,USB Address" group.word 0x54++0xD line.word 0x0 "USBREQ,USB Request Type Register" hexmask.word.byte 0x0 8.--15. 1. "BREQUEST,Request" hexmask.word.byte 0x0 0.--7. 1. "BMREQUESTTYPE,Request Type" line.word 0x2 "USBVAL,USB Request Value Register" hexmask.word 0x2 0.--15. 1. "WVALUE,Value" line.word 0x4 "USBINDX,USB Request Index Register" hexmask.word 0x4 0.--15. 1. "WINDEX,Index" line.word 0x6 "USBLENG,USB Request Length Register" hexmask.word 0x6 0.--15. 1. "WLENTUH,Length" line.word 0x8 "DCPCFG,DCP Configuration Register" bitfld.word 0x8 7. "SHTNAK,Pipe Disabled at End of Transfer" "0: Keep pipe open after transfer ends,1: Disable pipe after transfer ends" bitfld.word 0x8 4. "DIR,Transfer Direction" "0: Data receiving direction,1: Data transmitting direction" line.word 0xA "DCPMAXP,DCP Maximum Packet Size Register" hexmask.word.byte 0xA 12.--15. 1. "DEVSEL,Device Select" hexmask.word.byte 0xA 0.--6. 1. "MXPS,Maximum Packet Size" line.word 0xC "DCPCTR,DCP Control Register" rbitfld.word 0xC 15. "BSTS,Buffer Status" "0: Buffer access disabled,1: Buffer access enabled" bitfld.word 0xC 14. "SUREQ,Setup Token Transmission" "0: Invalid (writing 0 has no effect),1: Transmit setup packet" newline bitfld.word 0xC 11. "SUREQCLR,SUREQ Bit Clear" "0: Invalid (writing 0 has no effect),1: Clear SUREQ to 0" bitfld.word 0xC 8. "SQCLR,Sequence Toggle Bit Clear" "0: Invalid (writing 0 has no effect),1: Clear the expected value for the next.." newline bitfld.word 0xC 7. "SQSET,Sequence Toggle Bit Set" "0: Invalid (writing 0 has no effect),1: Set the expected value for the next transaction.." rbitfld.word 0xC 6. "SQMON,Sequence Toggle Bit Monitor" "0: DATA0,1: DATA1" newline rbitfld.word 0xC 5. "PBUSY,Pipe Busy" "0: DCP not used for the USB bus,1: DCP in use for the USB bus" bitfld.word 0xC 2. "CCPL,Control Transfer End Enable" "0: Disable control transfer completion,1: Enable control transfer completion" newline bitfld.word 0xC 0.--1. "PID,Response PID" "0: NAK response,1: BUF response (depends on the buffer state),?,?" group.word 0x64++0x1 line.word 0x0 "PIPESEL,Pipe Window Select Register" hexmask.word.byte 0x0 0.--3. 1. "PIPESEL,Pipe Window Select" group.word 0x68++0x1 line.word 0x0 "PIPECFG,Pipe Configuration Register" bitfld.word 0x0 14.--15. "TYPE,Transfer Type" "0: Pipe not used,1: Pipes 1 and 2: Bulk transfer Pipes 3 to 5: Bulk..,?,?" bitfld.word 0x0 10. "BFRE,BRDY Interrupt Operation Specification" "0: Generate BRDY interrupt on transmitting or..,1: Generate BRDY interrupt on completion of reading.." newline bitfld.word 0x0 9. "DBLB,Double Buffer Mode" "0: Single buffer,1: Double buffer" bitfld.word 0x0 7. "SHTNAK,Pipe Disabled at End of Transfer" "0: Continue pipe operation after transfer ends,1: Disable pipe after transfer ends" newline bitfld.word 0x0 4. "DIR,Transfer Direction" "0: Receiving direction,1: Transmitting direction" hexmask.word.byte 0x0 0.--3. 1. "EPNUM,Endpoint Number" group.word 0x6C++0x3 line.word 0x0 "PIPEMAXP,Pipe Maximum Packet Size Register" hexmask.word.byte 0x0 12.--15. 1. "DEVSEL,Device Select" hexmask.word 0x0 0.--8. 1. "MXPS,Maximum Packet Size" line.word 0x2 "PIPEPERI,Pipe Cycle Control Register" bitfld.word 0x2 12. "IFIS,Isochronous IN Buffer Flush" "0: Do not flush buffer,1: Flush buffer" bitfld.word 0x2 0.--2. "IITV,Interval Error Detection Interval" "0,1,2,3,4,5,6,7" repeat 5. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0x70)++0x1 line.word 0x0 "PIPE$1CTR,PIPE%s Control Registers" rbitfld.word 0x0 15. "BSTS,Buffer Status" "0: Buffer access by the CPU disabled,1: Buffer access by the CPU enabled" rbitfld.word 0x0 14. "INBUFM,Transmit Buffer Monitor" "0: No data to be transmitted is in the FIFO buffer,1: Data to be transmitted is in the FIFO buffer" newline bitfld.word 0x0 10. "ATREPM,Auto Response Mode" "0: Disable auto response mode,1: Enable auto response mode" bitfld.word 0x0 9. "ACLRM,Auto Buffer Clear Mode" "0: Disable,1: Enable (initialize all buffers)" newline bitfld.word 0x0 8. "SQCLR,Sequence Toggle Bit Clear" "0: Invalid (writing 0 has no effect),1: Clear the expected value for the next.." bitfld.word 0x0 7. "SQSET,Sequence Toggle Bit Set" "0: Invalid (writing 0 has no effect),1: Set the expected value for the next transaction.." newline rbitfld.word 0x0 6. "SQMON,Sequence Toggle Bit Confirmation" "0: DATA0,1: DATA1" rbitfld.word 0x0 5. "PBUSY,Pipe Busy" "0: Pipe n not in use for the transaction,1: Pipe n in use for the transaction" newline bitfld.word 0x0 0.--1. "PID,Response PID" "0: NAK response,1: BUF response (depends buffer state),?,?" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0x7A)++0x1 line.word 0x0 "PIPE$1CTR,PIPE%s Control Registers" rbitfld.word 0x0 15. "BSTS,Buffer Status" "0: Buffer access disabled,1: Buffer access enabled" bitfld.word 0x0 9. "ACLRM,Auto Buffer Clear Mode" "0: Disable,1: Enable (all buffers initialized)" newline bitfld.word 0x0 8. "SQCLR,Sequence Toggle Bit Clear" "0: Invalid (writing 0 has no effect),1: Clear the expected value for the next.." bitfld.word 0x0 7. "SQSET,Sequence Toggle Bit Set" "0: Invalid (writing 0 has no effect),1: Set the expected value for the next transaction.." newline rbitfld.word 0x0 6. "SQMON,Sequence Toggle Bit Confirmation" "0: DATA0,1: DATA1" rbitfld.word 0x0 5. "PBUSY,Pipe Busy" "0: Pipe n not in use for the transaction,1: Pipe n in use for the transaction" newline bitfld.word 0x0 0.--1. "PID,Response PID" "0: NAK response,1: BUF response (depends buffer state),?,?" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x90)++0x1 line.word 0x0 "PIPE$1TRE,PIPE%s Transaction Counter Enable Register" bitfld.word 0x0 9. "TRENB,Transaction Counter Enable" "0: Disable transaction counter,1: Enable transaction counter" bitfld.word 0x0 8. "TRCLR,Transaction Counter Clear" "0: Invalid (writing 0 has no effect),1: Clear counter value" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x92)++0x1 line.word 0x0 "PIPE$1TRN,PIPE%s Transaction Counter Register" hexmask.word 0x0 0.--15. 1. "TRNCNT,Transaction Counter" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0xD0)++0x1 line.word 0x0 "DEVADD$1,Device Address %s Configuration Register" bitfld.word 0x0 6.--7. "USBSPD,Transfer Speed of Communication Target Device" "0: Do not use DEVADDn,1: Low-speed,?,?" repeat.end group.long 0x400++0x7 line.long 0x0 "DPUSR0R,Deep Software Standby USB Transceiver Control/Pin Monitor Register" rbitfld.long 0x0 23. "DVBSTS0,USB VBUS Input" "0,1" rbitfld.long 0x0 21. "DOVCB0,USB OVRCURB-DS Input" "0,1" newline rbitfld.long 0x0 20. "DOVCA0,USB OVRCURA-DS Input" "0,1" rbitfld.long 0x0 17. "DM0,USB D- Input" "0,1" newline rbitfld.long 0x0 16. "DP0,USB D+ Input" "0,1" bitfld.long 0x0 4. "FIXPHY0,USB Transceiver Output Fix" "0: Fix outputs in Normal mode and on return from..,1: Fix outputs on transition to Deep Software.." newline bitfld.long 0x0 3. "DRPD0,D+/D- Pull-Down Resistor Control" "0: Disable DP/DM pull-down resistor,1: Enable DP/DM pull-down resistor" bitfld.long 0x0 1. "RPUE0,DP Pull-Up Resistor Control" "0: Disable DP pull-up resistor,1: Enable DP pull-up resistor" newline bitfld.long 0x0 0. "SRPC0,USB Single-ended Receiver Control" "0: Disable input through DP and DM inputs,1: Enable input through DP and DM inputs" line.long 0x4 "DPUSR1R,Deep Software Standby USB Suspend/Resume Interrupt Register" rbitfld.long 0x4 23. "DVBINT0,USB VBUS Interrupt Source Recovery" "0: System has not recovered from Deep Software..,1: System recovered from Deep Software Standby mode.." rbitfld.long 0x4 21. "DOVRCRB0,USB OVRCURB-DS Interrupt Source Recovery" "0: System has not recovered from Deep Software..,1: System recovered from Deep Software Standby mode.." newline rbitfld.long 0x4 20. "DOVRCRA0,USB OVRCURA-DS Interrupt Source Recovery" "0: System has not recovered from Deep Software..,1: System recovered from Deep Software Standby mode.." rbitfld.long 0x4 17. "DMINT0,USB DM Interrupt Source Recovery" "0: System has not recovered from Deep Software..,1: System recovered from Deep Software Standby mode.." newline rbitfld.long 0x4 16. "DPINT0,USB DP Interrupt Source Recovery" "0: System has not recovered from Deep Software..,1: System recovered from Deep Software Standby mode.." bitfld.long 0x4 7. "DVBSE0,USB VBUS Interrupt Enable/Clear" "0: Disable recovery from Deep Software Standby mode..,1: Enable recovery from Deep Software Standby mode.." newline bitfld.long 0x4 5. "DOVRCRBE0,USB OVRCURB-DS Interrupt Enable/Clear" "0: Disable recovery from Deep Software Standby mode..,1: Enable recovery from Deep Software Standby mode.." bitfld.long 0x4 4. "DOVRCRAE0,USB OVRCURA-DS Interrupt Enable/Clear" "0: Disable recovery from Deep Software Standby mode..,1: Enable recovery from Deep Software Standby mode.." newline bitfld.long 0x4 1. "DMINTE0,USB DM Interrupt Enable/Clear" "0: Disable recovery from Deep Software Standby mode..,1: Enable recovery from Deep Software Standby mode.." bitfld.long 0x4 0. "DPINTE0,USB DP Interrupt Enable/Clear" "0: Disable recovery from Deep Software Standby mode..,1: Enable recovery from Deep Software Standby mode.." tree.end tree.end tree "WDT (Watchdog Timer)" base ad:0x0 tree "WDT0" base ad:0x40202600 group.byte 0x0++0x0 line.byte 0x0 "WDTRR,WDT Refresh Register" group.word 0x2++0x3 line.word 0x0 "WDTCR,WDT Control Register" bitfld.word 0x0 12.--13. "RPSS,Window Start Position Select" "0: 25%,1: 50%,?,?" bitfld.word 0x0 8.--9. "RPES,Window End Position Select" "0: 75%,1: 50%,?,?" hexmask.word.byte 0x0 4.--7. 1. "CKS,Clock Division Ratio Select" bitfld.word 0x0 0.--1. "TOPS,Timeout Period Select" "0: 1024 cycles (0x03FF),1: 4096 cycles (0x0FFF),?,?" line.word 0x2 "WDTSR,WDT Status Register" bitfld.word 0x2 15. "REFEF,Refresh Error Flag" "0: No refresh error occurred,1: Refresh error occurred" bitfld.word 0x2 14. "UNDFF,Underflow Flag" "0: No underflow occurred,1: Underflow occurred" hexmask.word 0x2 0.--13. 1. "CNTVAL,Down-Counter Value" group.byte 0x6++0x0 line.byte 0x0 "WDTRCR,WDT Reset Control Register" bitfld.byte 0x0 7. "RSTIRQS,WDT Behavior Selection" "0: Interrupt,1: Reset" group.byte 0x8++0x0 line.byte 0x0 "WDTCSTPR,WDT Count Stop Control Register" bitfld.byte 0x0 7. "SLCSTP,CPU Sleep-Mode Count Stop Control Register" "0: Disable count stop,1: Stop count on transition to CPU Sleep mode or.." tree.end tree "WDT0_NS" base ad:0x50202600 group.byte 0x0++0x0 line.byte 0x0 "WDTRR,WDT Refresh Register" group.word 0x2++0x3 line.word 0x0 "WDTCR,WDT Control Register" bitfld.word 0x0 12.--13. "RPSS,Window Start Position Select" "0: 25%,1: 50%,?,?" bitfld.word 0x0 8.--9. "RPES,Window End Position Select" "0: 75%,1: 50%,?,?" hexmask.word.byte 0x0 4.--7. 1. "CKS,Clock Division Ratio Select" bitfld.word 0x0 0.--1. "TOPS,Timeout Period Select" "0: 1024 cycles (0x03FF),1: 4096 cycles (0x0FFF),?,?" line.word 0x2 "WDTSR,WDT Status Register" bitfld.word 0x2 15. "REFEF,Refresh Error Flag" "0: No refresh error occurred,1: Refresh error occurred" bitfld.word 0x2 14. "UNDFF,Underflow Flag" "0: No underflow occurred,1: Underflow occurred" hexmask.word 0x2 0.--13. 1. "CNTVAL,Down-Counter Value" group.byte 0x6++0x0 line.byte 0x0 "WDTRCR,WDT Reset Control Register" bitfld.byte 0x0 7. "RSTIRQS,WDT Behavior Selection" "0: Interrupt,1: Reset" group.byte 0x8++0x0 line.byte 0x0 "WDTCSTPR,WDT Count Stop Control Register" bitfld.byte 0x0 7. "SLCSTP,CPU Sleep-Mode Count Stop Control Register" "0: Disable count stop,1: Stop count on transition to CPU Sleep mode or.." tree.end tree.end newline AUTOINDENT.OFF