; --------------------------------------------------------------------------------
; @Title: Agilex7 On-Chip Peripherals
; @Props: Released
; @Author: NEJ
; @Changelog: 2024-04-08 NEJ
; @Manufacturer: INTEL - Intel Corporation
; @Doc: Generated (TRACE32, build: 168047.), based on:
;       agilex7_hps.svd (Ver. 1.0)
; @Core: Cortex-A53
; @Chip: AGILEX7
; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: peragilex7.per 17739 2024-04-09 09:34:07Z kwisniewski $

AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree "Core Registers (Cortex-A53)"
AUTOINDENT.PUSH
AUTOINDENT.ON center tree
tree.open "AArch64"
tree "ID Registers"
rgroup.quad spr:0x30000++0x0
line.quad 0x0 "MIDR_EL1,Main ID Register"
hexmask.quad.byte 0x0 24.--31. 0x1 "IMPLEMENTER,Implementer code"
bitfld.quad 0x0 20.--23. "VARIANT,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x0 16.--19. "ARCHITECTURE,Architecture" "Reserved,ARMv4,ARMv4T,ARMv5,ARMv5T,ARMv5TE,ARMv5TEJ,ARMv6,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme"
newline
hexmask.quad.word 0x0 4.--15. 0x1 "PARTNUM,Primary Part Number"
bitfld.quad 0x0 0.--3. "REVISION,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x30005++0x00
line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register"
bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..."
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
newline
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
bitfld.quad 0x00 0.--1. "CPU_ID,CPU ID" "1,2,3,4"
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30005++0x00
line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity level 3. Third highest level affinity field"
newline
bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..."
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
newline
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field"
endif
rgroup.quad SPR:0x30006++0x0
line.quad 0x0 "REVIDR_EL1,Revision ID Register"
rgroup.quad SPR:0x30014++0x00
line.quad 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "INNERSHR,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
bitfld.quad 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
bitfld.quad 0x00 20.--23. "AUXREG,Auxiliary Register Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
bitfld.quad 0x00 12.--15. "SHARELVL,Shareability levels" "Reserved,Implemented 2 levels,?..."
bitfld.quad 0x00 8.--11. "OUTERSHR,Outer Shareable Support" "Reserved,Implemented,?..."
newline
bitfld.quad 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.quad 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
rgroup.quad SPR:0x30015++0x00
line.quad 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1"
bitfld.quad 0x00 28.--31. "BPRED,Branch Predictor" "Reserved,Reserved,Required,?..."
bitfld.quad 0x00 24.--27. "L1TSTCLN,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
bitfld.quad 0x00 20.--23. "L1UNI,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
newline
bitfld.quad 0x00 16.--19. "L1HVD,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.quad 0x00 12.--15. "L1UNISW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "L1HVDSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "L1UNIVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
bitfld.quad 0x00 0.--3. "L1HVDVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
rgroup.quad SPR:0x30016++0x00
line.quad 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2"
bitfld.quad 0x00 28.--31. "HWACCFLG,Hardware Access Flag Support" "Not supported,?..."
bitfld.quad 0x00 24.--27. "WFISTALL,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "MEMBARR,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "UNITLB,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "HVDTLB,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "LL1HVDRNG,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "L1HVDBG,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.quad 0x00 0.--3. "L1HVDFG,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.quad SPR:0x30017++0x00
line.quad 0x00 "ID_MMFR3_EL1,Memory Model Feature Register 3"
bitfld.quad 0x00 28.--31. "SUPERSEC,Supersection support" "Supported,?..."
bitfld.quad 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
bitfld.quad 0x00 20.--23. "COHWALK,Coherent walk" "Reserved,Supported,Reserved,?..."
newline
bitfld.quad 0x00 12.--15. "MAINTBCST,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BPMAINT,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "CMAINTSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 0.--3. "CMAINTVA,Invalidate Cache MVA Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30026++0x00
line.quad 0x00 "ID_MMFR4_EL1,Memory Model Feature Register 4"
bitfld.quad 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x30070++0x00
line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "TGRAN4,4KB granule supported" "Supported,?..."
bitfld.quad 0x00 24.--27. "TGRAN64,64KB granule supported" "Supported,?..."
bitfld.quad 0x00 20.--23. "TGRAN16,16KB granule supported" "Not supported,?..."
newline
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
newline
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16 TB,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30070++0x00
line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "TGRAN4,4KB granule supported" "Supported,?..."
bitfld.quad 0x00 24.--27. "TGRAN64,64KB granule supported" "Supported,?..."
bitfld.quad 0x00 20.--23. "TGRAN16,16KB granule supported" "Not supported,?..."
newline
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
newline
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..."
endif
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30071++0x00
line.quad 0x00 "ID_AA64MMFR1_EL1,AArch64 Memory Model Feature Register 1"
endif
rgroup.quad SPR:0x30020++0x00
line.quad 0x00 "ID_ISAR0_EL1,Instruction Set Attribute Register 0"
bitfld.quad 0x00 24.--27. "DIVIDE,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "DEBUG,Debug Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 16.--19. "COPROC,Coprocessor Instructions Support" "Not supported,?..."
newline
bitfld.quad 0x00 12.--15. "CMPBRANCH,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BITFIELD,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "BITCOUNT,Bit Counting Instructions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 0.--3. "SWAP,Swap Instructions Support" "Not supported,?..."
rgroup.quad SPR:0x30021++0x00
line.quad 0x00 "ID_ISAR1_EL1,Instruction Set Attribute Register 1"
bitfld.quad 0x00 28.--31. "JAZELLE,Jazelle instructions support" "Reserved,Supported,?..."
bitfld.quad 0x00 24.--27. "INTERWORK,Interwork instructions support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "IMMEDIATE,Immediate instructions support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "IFTHEN,If then instructions support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "EXTEND,Extend instructions support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "EXCEPT_AR,Exception A and R Instructions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 4.--7. "EXCEPT,Exception in ARM Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "ENDIAN,Endian Instructions Support" "Reserved,Supported,?..."
rgroup.quad SPR:0x30022++0x00
line.quad 0x00 "ID_ISAR2_EL1,Instruction Set Attribute Register 2"
bitfld.quad 0x00 28.--31. "REVERSAL,Reversal instructions support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 24.--27. "PSR_AR,PSR Instructions support" "Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "MULTU,Advanced unsigned multiply instructions support" "Reserved,Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "MULTS,Advanced signed multiply instructions support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "MULT,Multiply instructions support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "MULTIACCESSINT,Multi-access interruptible instructions support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "MEMHINT,Memory hint instructions support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "LOADSTORE,Load and store instructions support" "Reserved,Reserved,Supported,?..."
rgroup.quad SPR:0x30023++0x00
line.quad 0x00 "ID_ISAR3_EL1,Instruction Set Attribute Register 3"
bitfld.quad 0x00 28.--31. "T32EE,Thumb-EE Extensions Support" "Not supported,?..."
bitfld.quad 0x00 24.--27. "TRUENOP,True NOP Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "T32COPY,Thumb Copy Instructions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "TABBRANCH,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..."
bitfld.quad 0x00 12.--15. "SYNCHPRIM,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "SVC,SVC Instructions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 4.--7. "SIMD,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "SATURATE,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.quad SPR:0x30024++0x00
line.quad 0x00 "ID_ISAR4_EL1,Instruction Set Attribute Register 4"
bitfld.quad 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
bitfld.quad 0x00 24.--27. "PSR_M,PSR_M Instructions Support" "Not supported,?..."
bitfld.quad 0x00 20.--23. "SYNCHPRIM_FRAC,Synchronization Primitive instructions" "Supported,?..."
newline
bitfld.quad 0x00 16.--19. "BARRIER,Barrier Instructions support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "SMC,SMC Instructions support" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "WRITEBACK,Write-Back Instructions support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 4.--7. "WITHSHIFTS,With-Shift Instructions support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "UNPRIV,Unprivileged Instructions support" "Reserved,Reserved,Supported,?..."
rgroup.quad SPR:0x30025++0x00
line.quad 0x00 "ID_ISAR5_EL1,Instruction Set Attribute Register 5"
bitfld.quad 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..."
bitfld.quad 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..."
newline
bitfld.quad 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30060++0x00
line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0"
bitfld.quad 0x00 16.--19. "CRC32,CRC32" "Reserved,Implemented,?..."
bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions are implemented" "Not implemented,Implemented,?..."
bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions are implemented" "Not implemented,Implemented,?..."
newline
bitfld.quad 0x00 4.--7. "AES,AES instructions are implemented" "Not implemented,Reserved,Implemented,?..."
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30061++0x00
line.quad 0x00 "ID_AA64ISAR1_EL1,AArch64 Instruction Set Attribute Register 1"
endif
rgroup.quad SPR:0x30010++0x00
line.quad 0x00 "ID_PFR0_EL1,Processor Feature Register 0"
bitfld.quad 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.quad 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.quad SPR:0x30011++0x00
line.quad 0x00 "ID_PFR1_EL1,Processor Feature Register 1"
bitfld.quad 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
bitfld.quad 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "V,Virtualization Extensions Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
bitfld.quad 0x00 4.--7. "S,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x30040++0x00
line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0"
bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..."
bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,?..."
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,?..."
newline
bitfld.quad 0x00 12.--15. "EL3,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 8.--11. "EL2,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 4.--7. "EL1,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
newline
bitfld.quad 0x00 0.--3. "EL0,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30040++0x00
line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0"
bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..."
bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
newline
bitfld.quad 0x00 12.--15. "EL3,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 8.--11. "EL2,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 4.--7. "EL1,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
newline
bitfld.quad 0x00 0.--3. "EL0,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
endif
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30041++0x00
line.quad 0x00 "ID_AA64PFR1_EL1,AArch64 Processor Feature Register 1"
endif
if (CORENAME()=="CORTEXA57")
rgroup.quad SPR:0x30012++0x00
line.quad 0x00 "ID_DFR0_EL1,Debug Feature Register 0"
bitfld.quad 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "MPROFDBG,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.quad 0x00 16.--19. "MMAPTRC,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 12.--15. "COPTRC,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "MMAPDBG,Memory-Mapped Debug Model Support" "Not supported,?..."
bitfld.quad 0x00 4.--7. "COPSDBG,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.quad 0x00 0.--3. "COPDBG,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad SPR:0x30012++0x00
line.quad 0x00 "ID_DFR0_EL1,Debug Feature Register 0"
bitfld.quad 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "MPROFDBG,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.quad 0x00 16.--19. "MMAPTRC,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 12.--15. "COPTRC,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.quad 0x00 4.--7. "COPSDBG,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "COPDBG,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
endif
rgroup.quad spr:0x30050++0x00
line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0"
bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "Reserved,2,?..."
bitfld.quad 0x00 20.--23. "WRPS,The number of watchpoints minus 1" "Reserved,Reserved,Reserved,4,?..."
bitfld.quad 0x00 12.--15. "BRPS,The number of breakpoints minus 1" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
newline
bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitors extension version" "Reserved,Implemented,?..."
bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension" "Not implemented,?..."
bitfld.quad 0x00 0.--3. "DEBUGGER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented,?..."
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30051++0x00
line.quad 0x00 "ID_AA64DFR1_EL1,AArch64 Debug Feature Register 1"
rgroup.quad spr:0x30054++0x00
line.quad 0x00 "ID_AA64AFR0_EL1,AArch64 Auxiliary Feature Register 0"
rgroup.quad spr:0x30055++0x00
line.quad 0x00 "ID_AA64AFR1_EL1,AArch64 Auxiliary Feature Register 1"
endif
rgroup.quad SPR:0x30013++0x00
line.quad 0x00 "ID_AFR0_EL1,Auxiliary Feature Register 0"
rgroup.quad SPR:0x31007++0x00
line.quad 0x00 "AIDR_EL1,Auxiliary ID Register"
rgroup.quad SPR:0x33007++0x00
line.quad 0x00 "DCZID_EL0,Data Cache Zero ID"
bitfld.quad 0x00 4. "DZP,Prohibit the DC ZVA instruction" "Not prohibited,Prohibited"
bitfld.quad 0x00 0.--3. "BS,Block Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x30030++0x00 "Media and VFP Feature registers"
line.quad 0x00 "MVFR0_EL1,Media and VFP Feature Register 0/EL1"
bitfld.quad 0x00 28.--31. "FPROUND,Indicates the rounding modes supported by the floating-point hardware" "Reserved,Supported,?..."
bitfld.quad 0x00 24.--27. "FPSHVEC,Indicates the hardware support for floating-point short vectors" "Not supported,?..."
bitfld.quad 0x00 20.--23. "FPSQRT,Indicates the hardware support for floating-point square root operations" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "FPDIVIDE,Indicates the hardware support for floating-point divide operations" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "FPTRAP,Indicates whether the floating-point hardware implementation supports exception trapping" "Not supported,?..."
bitfld.quad 0x00 8.--11. "FPDP,Indicates the hardware support for floating-point double-precision operations" "Reserved,Reserved,VFPv3 or greater,?..."
newline
bitfld.quad 0x00 4.--7. "FPSP,Indicates the hardware support for floating-point single-precision operations" "Reserved,Reserved,VFPv3 or greater,?..."
bitfld.quad 0x00 0.--3. "SIMDREG,Indicates support for the Advanced SIMD register bank" "Reserved,Reserved,32x64-bit,?..."
rgroup.quad spr:0x30031++0x00
line.quad 0x00 "MVFR1_EL1,Media and VFP Feature Register 1/EL1"
bitfld.quad 0x00 28.--31. "SIMDFMAC,Indicates whether Advanced SIMD or floating-point supports fused multiply accumulate operations" "Reserved,Supported,?..."
bitfld.quad 0x00 24.--27. "FPHP,Indicates whether floating-point supports half-precision floating-point conversion operations" "Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "SIMDHP,Indicates whether Advanced SIMD supports half-precision floating-point conversion operations" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "SIMDSP,Indicates whether Advanced SIMD supports single-precision floating-point operations" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "SIMDINT,Indicates whether Advanced SIMD supports integer operations" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "SIMDLS,Indicates whether Advanced SIMD supports load/store instructions" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 4.--7. "FPDNAN,Indicates whether the floating-point hardware implementation supports only the Default NaN mode" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "FPFTZ,Indicates whether the floating-point hardware implementation supports only the Flush-to-Zero mode of operation" "Reserved,Supported,?..."
rgroup.quad spr:0x30032++0x00
line.quad 0x00 "MVFR2_EL1,Media and VFP Feature Register 2/EL1"
bitfld.quad 0x00 4.--7. "FPMISC,Indicates support for miscellaneous floating-point features. Supported = Selection/Conversion to Integer with Directed Rounding/Round to Integral Floating-point/MaxNum/MinNum" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "SIMDMISC,Indicates support for miscellaneous Advanced SIMD features. Supported = Selection/Conversion to Integer with Directed Rounding/Round to Integral Floating-point/MaxNum/MinNum" "Reserved,Reserved,Reserved,Supported,?..."
endif
tree.end
tree "System Control and Configuration"
group.quad spr:0x36111++0x00
line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register"
bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled"
bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled"
group.quad SPR:0x30100++0x0
line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)"
bitfld.quad 0x0 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled"
bitfld.quad 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.quad 0x0 24. "E0E,Endianness of explicit data access at EL0" "Little,Big"
bitfld.quad 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.quad 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.quad 0x0 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled"
bitfld.quad 0x0 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled"
newline
bitfld.quad 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x0 9. "UMA,User Mask Access" "Disabled,Enabled"
newline
bitfld.quad 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.quad 0x0 7. "ITD,IT instruction disable" "No,Yes"
newline
bitfld.quad 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled"
bitfld.quad 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.quad 0x0 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled"
bitfld.quad 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad SPR:0x34100++0x0
line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.quad 0x0 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad SPR:0x36100++0x0
line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)"
bitfld.quad 0x0 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
rgroup.quad SPR:0x30101++0x0
line.quad 0x00 "ACTLR_EL1,Auxiliary Control Register (EL1)"
if (CORENAME()=="CORTEXA53")
group.quad SPR:0x34101++0x0
line.quad 0x00 "ACTLR_EL2,Auxiliary Control Register (EL2)"
bitfld.quad 0x00 6. "L2ACTLR_EL1,L2ACTLR write access control" "Disabled,Enabled"
bitfld.quad 0x00 5. "L2ECTLR_EL1,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "L2CTLR_EL1,L2CTLR write access control" "Disabled,Enabled"
bitfld.quad 0x00 1. "CPUECTLR_EL1,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "CPUACTLR_EL1,CPUACTLR write access control" "Disabled,Enabled"
group.quad SPR:0x36101++0x0
line.quad 0x00 "ACTLR_EL3,Auxiliary Control Register (EL3)"
bitfld.quad 0x00 6. "L2ACTLR_EL1,L2ACTLR write access control" "Disabled,Enabled"
bitfld.quad 0x00 5. "L2ECTLR_EL1,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "L2CTLR_EL1,L2CTLR write access control" "Disabled,Enabled"
bitfld.quad 0x00 1. "CPUECTLR_EL1,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "CPUACTLR_EL1,CPUACTLR write access control" "Disabled,Enabled"
elif (CORENAME()=="CORTEXA57")
group.quad SPR:0x34101++0x0
line.quad 0x00 "ACTLR_EL2,Auxiliary Control Register (EL2)"
bitfld.quad 0x00 6. "L2ACTLR,L2ACTLR write access control" "Disabled,Enabled"
bitfld.quad 0x00 5. "L2ECTLR,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "L2CTLR,L2CTLR write access control" "Disabled,Enabled"
bitfld.quad 0x00 1. "CPUECTLR,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "CPUACTLR,CPUACTLR write access control" "Disabled,Enabled"
group.quad SPR:0x36101++0x0
line.quad 0x00 "ACTLR_EL3,Auxiliary Control Register (EL3)"
bitfld.quad 0x00 6. "L2ACTLR,L2ACTLR write access control" "Disabled,Enabled"
bitfld.quad 0x00 5. "L2ECTLR,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "L2CTLR,L2CTLR write access control" "Disabled,Enabled"
bitfld.quad 0x00 1. "CPUECTLR,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "CPUACTLR,CPUACTLR write access control" "Disabled,Enabled"
endif
group.quad SPR:0x30102++0x00
line.quad 0x00 "CPACR_EL1,Architectural Feature Access Control Register"
bitfld.quad 0x00 28. "TTA,Causes access to the Trace functionality to trap to EL1 when executed from EL0 or EL1" "Disabled,?..."
bitfld.quad 0x00 20.--21. "FPEN,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1" "Trap all,Trap El0,Trap all,Not trapped"
group.quad SPR:0x36110++0x0
line.quad 0x0 "SCR_EL3,Secure Configuration Register"
bitfld.quad 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped"
bitfld.quad 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped"
newline
bitfld.quad 0x00 11. "ST,Enable secure EL1 access" "Disabled,Enabled"
bitfld.quad 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64"
newline
bitfld.quad 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.quad 0x00 8. "HCE,Hypervisor Call enable" "No,Yes"
newline
bitfld.quad 0x00 7. "SMD,Secure Monitor Call disable" "No,Yes"
bitfld.quad 0x00 3. "EA,External Abort  exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
newline
bitfld.quad 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
bitfld.quad 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
newline
bitfld.quad 0x00 0. "NS,Secure mode" "Secure,Non-secure"
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register"
bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes"
newline
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit"
bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
newline
bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled"
bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled"
bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled"
bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
newline
bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending"
bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending"
newline
bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending"
bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled"
bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled"
group.quad spr:0x30510++0x00
line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)"
group.quad spr:0x30511++0x00
line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)"
group.quad spr:0x34510++0x00
line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)"
group.quad spr:0x34511++0x00
line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)"
group.quad spr:0x36510++0x00
line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)"
group.quad spr:0x36511++0x00
line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)"
tree.open "Exception Syndrome Registers"
if (CORENAME()=="CORTEXA57")
if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..."
elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.quad.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.quad.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
hexmask.quad.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000))
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
hexmask.quad.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..."
elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.quad.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
elif (CORENAME()=="CORTEXA53")
if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SES,System Error Source" "Processor,System,External,"
newline
hexmask.quad.tbyte 0x00 0.--21. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000)
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
hexmask.quad.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.quad.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000)
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
hexmask.quad.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000))
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.quad.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000)
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
endif
tree.end
newline
if (CORENAME()=="CORTEXA57")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
elif (CORENAME()=="CORTEXA53")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
endif
group.quad spr:0x30600++0x00
line.quad 0x00 "FAR_EL1,Fault Address Register"
group.quad spr:0x34600++0x00
line.quad 0x00 "FAR_EL2,Fault Address Register"
group.quad spr:0x36600++0x00
line.quad 0x00 "FAR_EL3,Fault Address Register"
group.quad spr:0x34604++0x00
line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register"
group.quad spr:0x30C00++0x00
line.quad 0x00 "VBAR_EL1,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address"
group.quad spr:0x34C00++0x00
line.quad 0x00 "VBAR_EL2,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address"
group.quad spr:0x36C00++0x00
line.quad 0x00 "VBAR_EL3,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x36C01++0x00
line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register"
hexmask.quad.pbyte 0x00 2.--43. 0x1 "RVBA,Reset Vector Base Address"
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x36C01++0x00
line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register"
hexmask.quad.pbyte 0x00 2.--39. 0x1 "RVBA,Reset Vector Base Address"
endif
rgroup.quad SPR:0x30C10++0x00
line.quad 0x00 "ISR_EL1,Interrupt Status Register"
bitfld.quad 0x00 8. "A,External abort pending flag" "Not pending,Pending"
bitfld.quad 0x00 7. "I,Interrupt pending flag" "Not pending,Pending"
newline
bitfld.quad 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending"
group.quad SPR:0x36C02++0x00
line.quad 0x00 "RMR_EL3,Reset Management Register"
bitfld.quad 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.quad 0x00 0. "AA64,Determines which execution state the processor boots into after a warmreset" "AArch32,AArch64"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x31F30++0x00
line.quad 0x00 "CBAR_EL1,Configuration Base Address Register"
hexmask.quad.long 0x00 18.--43. 1. "PERIPHBASE[43:18],Periphbase[43:18]"
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x31F30++0x00
line.quad 0x00 "CBAR_EL1,Configuration Base Address Register"
hexmask.quad.tbyte 0x00 18.--39. 1. "PERIPHBASE[39:18],Periphbase[39:18]"
endif
group.quad spr:0x30D01++0x00
line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register"
hexmask.quad.long 0x00 0.--31. 1. "PROCID,Process identifier"
group.quad spr:0x33D02++0x00
line.quad 0x00 "TPIDR_EL0,Software Thread ID Register"
group.quad spr:0x33D03++0x00
line.quad 0x00 "TPIDRRO_EL0,Software Thread ID Register"
group.quad spr:0x30D04++0x00
line.quad 0x00 "TPIDR_EL1,Software Thread ID Register"
group.quad spr:0x34D02++0x00
line.quad 0x00 "TPIDR_EL2,Software Thread ID Register"
group.quad spr:0x36D02++0x00
line.quad 0x00 "TPIDR_EL3,Software Thread ID Register"
tree.end
tree "Memory Management Unit"
group.quad spr:0x30100++0x0
line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)"
bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled"
bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled"
newline
bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes"
bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes"
newline
bitfld.quad 0x00 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x34100++0x0
line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x36100++0x0
line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x30200++0x00
line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad spr:0x30201++0x00
line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x30202++0x00
line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)"
bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit"
bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..."
newline
bitfld.quad 0x00 30. "TG1,TTBR1_EL1 granule size" "4 KByte,64 KByte"
bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled"
bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB"
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x30202++0x00
line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)"
bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit"
bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
newline
bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,Reserved,4 KB,64 KB"
bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled"
bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 7. "EPD0,Translation table walk disable for translations using TTBR0" "Enabled,Disabled"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x34200++0x00
line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..."
newline
bitfld.quad 0x00 14. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB"
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x36200++0x00
line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x36202++0x00
line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..."
newline
bitfld.quad 0x00 14. "TGO,TTBR0_EL3 granule size" "4 KB,64 KB"
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x36202++0x00
line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad SPR:0x34300++0x00
line.quad 0x00 "DACR32_EL2,Domain Access Control Register"
bitfld.quad 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.quad 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
newline
bitfld.quad 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.quad 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
newline
bitfld.quad 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.quad 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
newline
bitfld.quad 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.quad 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
newline
bitfld.quad 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.quad 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
newline
bitfld.quad 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.quad 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
newline
bitfld.quad 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.quad 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
newline
bitfld.quad 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.quad 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
if (CORENAME()=="CORTEXA57")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
elif (CORENAME()=="CORTEXA53")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
endif
rgroup.quad SPR:0x30510++0x00
line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)"
rgroup.quad SPR:0x34510++0x00
line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)"
rgroup.quad SPR:0x36510++0x00
line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)"
rgroup.quad SPR:0x30511++0x00
line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)"
rgroup.quad SPR:0x34511++0x00
line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)"
rgroup.quad SPR:0x36511++0x00
line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)"
if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device-not nGnRnE,?..."
newline
hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif (((per.q(spr:0x30740))&0x01)==0x00)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
newline
hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
else
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
newline
bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes"
newline
bitfld.quad 0x00 1.--6. "FST,Fault status field" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Reserved,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,?..."
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
endif
tree.open "Memory Attribute Indirection Registers"
group.quad spr:0x30A20++0x00
line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
group.quad spr:0x34A20++0x00
line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
group.quad spr:0x36A20++0x00
line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
rgroup.quad spr:0x30A30++0x00
line.quad 0x00 "AMAIR_EL1,Memory Attribute Indirection Register (EL1)"
rgroup.quad spr:0x34A30++0x00
line.quad 0x00 "AMAIR_EL2,Memory Attribute Indirection Register (EL2)"
rgroup.quad spr:0x36A30++0x00
line.quad 0x00 "AMAIR_EL3,Memory Attribute Indirection Register (EL3)"
tree.end
newline
group.quad SPR:0x30D01++0x00
line.quad 0x0 "CONTEXTIDR_EL1,Context ID Register"
tree.end
tree "Virtualization Extensions"
group.quad SPR:0x34000++0x0
line.quad 0x0 "VPIDR_EL2,Virtualization Processor ID Register"
hexmask.quad.byte 0x00 24.--31. 0x01 "IMPLEMENTER,Implementer code"
bitfld.quad 0x00 20.--23. "VARIANT,Indicates the major revision of the product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 16.--19. "ARCHITECTURE,Architecture" "Reserved,ARMv4,ARMv4T,ARMv5,ARMv5T,ARMv5TE,ARMv5TEJ,ARMv6,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Defined by ID registers"
newline
hexmask.quad.word 0x00 4.--15. 1. "PARTNUM,Primary part number"
bitfld.quad 0x00 0.--3. "REVISION,Indicates the minor revision of the product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x34005++0x00
line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register"
bitfld.quad 0x00 30. "U,Indicates a uniprocessor system" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach" "Largely independent,Very interdependent"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Second highest level affinity field"
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Third highest level affinity field"
bitfld.quad 0x00 0.--1. "CPU_ID,Indicates the core number in the Cortex-A57 device" "1,2,3,4"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x34005++0x00
line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register"
bitfld.quad 0x00 30. "U,Indicates a uniprocessor system" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach" "Largely independent,?..."
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Second highest level affinity field"
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Third highest level affinity field"
hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Lowest level affinity field"
endif
group.quad spr:0x34100++0x0
line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register"
bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes"
newline
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit"
bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
newline
bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled"
bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled"
bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled"
bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
newline
bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending"
bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending"
newline
bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending"
bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled"
bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x34111++0x00
line.quad 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)"
bitfld.quad 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
newline
bitfld.quad 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
bitfld.quad 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.quad 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.quad 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
elif (CORENAME()=="CORTEXA53")
group.quad SPR:0x34111++0x00
line.quad 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)"
bitfld.quad 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
newline
bitfld.quad 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
bitfld.quad 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.quad 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.quad 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6"
endif
group.quad SPR:0x34112++0x00
line.quad 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)"
bitfld.quad 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.quad 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped"
group.quad SPR:0x36131++0x00
line.quad 0x00 "MDCR_EL3,Hypervisor Debug Control Register (EL3)"
bitfld.quad 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes"
bitfld.quad 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes"
bitfld.quad 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 16. "SDD,AArch64 secure debug disable" "No,Yes"
bitfld.quad 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled"
bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
newline
bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
group.quad SPR:0x36112++0x00
line.quad 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)"
bitfld.quad 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.quad 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped"
group.quad SPR:0x34113++0x00
line.quad 0x00 "HSTR_EL2,Hypervisor System Trap Register"
bitfld.quad 0x00 16. "TEEE,Trap ThumbEE" "Not supported,?..."
bitfld.quad 0x00 15. "T15,Trap coprocessor primary register CRn = 15" "No effect,Trapped"
bitfld.quad 0x00 13. "T13,Trap coprocessor primary register CRn = 13" "No effect,Trapped"
newline
bitfld.quad 0x00 12. "T12,Trap coprocessor primary register CRn = 12" "No effect,Trapped"
bitfld.quad 0x00 11. "T11,Trap coprocessor primary register CRn = 11" "No effect,Trapped"
bitfld.quad 0x00 10. "T10,Trap coprocessor primary register CRn = 10" "No effect,Trapped"
newline
bitfld.quad 0x00 9. "T9,Trap coprocessor primary register CRn = 9" "No effect,Trapped"
bitfld.quad 0x00 8. "T8,Trap coprocessor primary register CRn = 8" "No effect,Trapped"
bitfld.quad 0x00 7. "T7,Trap coprocessor primary register CRn = 7" "No effect,Trapped"
newline
bitfld.quad 0x00 6. "T6,Trap coprocessor primary register CRn = 6" "No effect,Trapped"
bitfld.quad 0x00 5. "T5,Trap coprocessor primary register CRn = 5" "No effect,Trapped"
bitfld.quad 0x00 3. "T3,Trap coprocessor primary register CRn = 3" "No effect,Trapped"
newline
bitfld.quad 0x00 2. "T2,Trap coprocessor primary register CRn = 2" "No effect,Trapped"
bitfld.quad 0x00 1. "T1,Trap coprocessor primary register CRn = 1" "No effect,Trapped"
bitfld.quad 0x00 0. "T0,Trap coprocessor primary register CRn = 0" "No effect,Trapped"
rgroup.quad SPR:0x34117++0x00
line.quad 0x00 "HACR_EL2,Hypervisor Auxiliary Configuration Register"
group.quad spr:0x34210++0x00
line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,VMID for the translation table"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x34212++0x00
line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.quad 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..."
bitfld.quad 0x00 14. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB"
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3"
bitfld.quad 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3"
newline
bitfld.quad 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad SPR:0x34212++0x00
line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.quad 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,?..."
bitfld.quad 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3"
bitfld.quad 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3"
newline
bitfld.quad 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x34604++0x00
line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register"
hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting IPA bits"
tree.end
tree "Cache Control and Configuration"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x33001++0x0
line.quad 0x0 "CTR_EL0,Cache Type Register"
bitfld.quad 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x0 14.--15. "L1IP,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.quad 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x33001++0x0
line.quad 0x0 "CTR_EL0,Cache Type Register"
bitfld.quad 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x0 14.--15. "L1IP,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.quad 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
endif
group.quad SPR:0x32000++0x0
line.quad 0x0 "CSSELR_EL1,Cache Size Selection Register"
bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..."
bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
if (CORENAME()=="CORTEXA57")
rgroup.quad SPR:0x31001++0x0
line.quad 0x0 "CLIDR_EL1,Cache Level ID Register"
bitfld.quad 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.quad 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..."
bitfld.quad 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
newline
bitfld.quad 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..."
bitfld.quad 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..."
bitfld.quad 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..."
newline
bitfld.quad 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..."
bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
rgroup.quad SPR:0x31000++0x0
line.quad 0x0 "CCSIDR_EL1,Current Cache Size ID Register"
bitfld.quad 0x00 31. "WT,Write-Through" "Not Supported,?..."
bitfld.quad 0x00 30. "WB,Write-Back" "Not Supported,Supported"
bitfld.quad 0x00 29. "RA,Read-Allocate" "Reserved,Supported"
newline
bitfld.quad 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
hexmask.quad.word 0x00 13.--27. 1. 1. "NUMSETS,Number of Sets"
hexmask.quad.word 0x00 3.--12. 1. 1. "ASSOCIATIVITY,Associativity"
newline
bitfld.quad 0x00 0.--2. "LINESIZE,Line Size" "Reserved,Reserved,64 bytes,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad SPR:0x31001++0x0
line.quad 0x0 "CLIDR_EL1,Cache Level ID Register"
bitfld.quad 0x00 30.--32. "ICB,Inner cache boundary" "Not disclosed,?..."
bitfld.quad 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.quad 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..."
newline
bitfld.quad 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..."
bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
rgroup.quad SPR:0x31000++0x0
line.quad 0x0 "CCSIDR_EL1,Current Cache Size ID Register"
bitfld.quad 0x00 31. "WT,Write-Through" "Not Supported,?..."
bitfld.quad 0x00 30. "WB,Write-Back" "Not Supported,Supported"
bitfld.quad 0x00 29. "RA,Read-Allocate" "Not Supported,Supported"
newline
bitfld.quad 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
hexmask.quad.word 0x00 13.--27. 1. 1. "NUMSETS,Number of Sets"
hexmask.quad.word 0x00 3.--12. 1. 1. "ASSOCIATIVITY,Associativity"
newline
bitfld.quad 0x00 0.--2. "LINESIZE,Line Size" "1Reserved,Reserved,64 bytes,?..."
endif
tree "Level 1 memory system"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x30F10++0x00
line.quad 0x00 "DL1DATA0_EL1,Data L1 Data 0 Register"
group.quad SPR:0x30F11++0x00
line.quad 0x00 "DL1DATA1_EL1,Data L1 Data 1 Register"
group.quad SPR:0x30F12++0x00
line.quad 0x00 "DL1DATA2_EL1,Data L1 Data 2 Register"
group.quad SPR:0x30F13++0x00
line.quad 0x00 "DL1DATA3_EL1,Data L1 Data 3 Register"
group.quad SPR:0x30F00++0x00
line.quad 0x00 "IL1DATA0_EL1,Instruction L1 Data 0 Register"
group.quad SPR:0x30F01++0x00
line.quad 0x00 "IL1DATA1_EL1,Instruction L1 Data 1 Register"
group.quad SPR:0x30F02++0x00
line.quad 0x00 "IL1DATA2_EL1,Instruction L1 Data 2 Register"
group.quad SPR:0x30F03++0x00
line.quad 0x00 "IL1DATA3_EL1,Instruction L1 Data 3 Register"
group.quad spr:0x31F20++0x00
line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register"
bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced"
bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes"
bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes"
newline
bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled"
bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes"
bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes"
newline
bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled"
bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled"
bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes"
newline
bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes"
bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes"
bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes"
newline
bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes"
bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes"
bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
newline
bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes"
bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced"
bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes"
newline
bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced"
bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes"
bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes"
bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled"
bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced"
newline
bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled"
bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled"
bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
newline
bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled"
bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced"
bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced"
newline
bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes"
bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes"
bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes"
newline
bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes"
bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes"
bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced"
bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced"
bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled"
newline
bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled"
bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled"
bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced"
newline
bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes"
bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled"
bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled"
bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes"
bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes"
bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled"
group.quad spr:0x31F21++0x00
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes"
bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines"
bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines"
newline
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..."
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..."
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x31F20++0x00
line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register"
bitfld.quad 0x00 44. "ENDCCASCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes"
bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes"
newline
bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled"
bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes"
newline
bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes"
bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes"
bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes"
newline
bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams"
bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled"
bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled"
newline
bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,8"
bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes"
bitfld.quad 0x00 6. "L1DEIEN,L1 D-cache data RAM error injection enable" "Disabled,Enabled"
group.quad spr:0x31F21++0x00
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
endif
if (CORENAME()=="CORTEXA57")
group.quad spr:0x31F22++0x00
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x31F22++0x00
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address"
endif
tree.end
tree "Level 2 memory system"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x31B02++0x0
line.quad 0x00 "L2CTLR_EL1,L2 Control Register"
bitfld.quad 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes"
bitfld.quad 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4"
rbitfld.quad 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
bitfld.quad 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled"
rbitfld.quad 0x00 13. "L2AS,L2 arbitration slice" "Not presented,Presented"
newline
rbitfld.quad 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not presented,Presented"
rbitfld.quad 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not presented,1,2,?..."
bitfld.quad 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle"
newline
bitfld.quad 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles"
rbitfld.quad 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle"
bitfld.quad 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
group.quad SPR:0x31B03++0x0
line.quad 0x00 "L2ECTLR_EL1,L2 Extended Control Register"
bitfld.quad 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.quad 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
bitfld.quad 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad SPR:0x31F00++0x00
line.quad 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register"
bitfld.quad 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled"
bitfld.quad 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled"
bitfld.quad 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced"
newline
bitfld.quad 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled"
bitfld.quad 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes"
bitfld.quad 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes"
newline
bitfld.quad 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled"
bitfld.quad 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit"
bitfld.quad 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes"
newline
bitfld.quad 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled"
bitfld.quad 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes"
bitfld.quad 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
newline
bitfld.quad 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes"
bitfld.quad 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes"
bitfld.quad 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes"
newline
bitfld.quad 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes"
bitfld.quad 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled"
bitfld.quad 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes"
newline
bitfld.quad 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled"
bitfld.quad 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
bitfld.quad 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited"
newline
bitfld.quad 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled"
bitfld.quad 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes"
group.quad spr:0x31F23++0x00
line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index"
elif (CORENAME()=="CORTEXA53")
group.quad SPR:0x31B02++0x0
line.quad 0x00 "L2CTLR_EL1,L2 Control Register"
bitfld.quad 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4"
bitfld.quad 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled"
rbitfld.quad 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
newline
rbitfld.quad 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle"
rbitfld.quad 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles"
group.quad SPR:0x31B03++0x0
line.quad 0x00 "L2ECTLR_EL1,L2 Extended Control Register"
bitfld.quad 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.quad 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
bitfld.quad 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad SPR:0x31F00++0x00
line.quad 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register"
bitfld.quad 0x00 30.--31. "L2VC,L2 Victim Control" "0,1,2,3"
bitfld.quad 0x00 29. "L2DEIEN,L2 cache data RAM error injection enable" "Disabled,Enabled"
bitfld.quad 0x00 24. "L2TEIEN,L2 cache tag RAM error injection enable." "Disabled,Enabled"
newline
bitfld.quad 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
bitfld.quad 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
group.quad spr:0x31F23++0x00
line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address"
endif
tree.end
tree.end
tree "System Performance Monitor"
group.quad SPR:0x339C0++0x00
line.quad 0x0 "PMCR_EL0,Performance Monitor Control Register"
hexmask.quad.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.quad.byte 0x00 16.--23. 1. "IDCODE,Identification code"
bitfld.quad 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
bitfld.quad 0x00 4. "X,Export Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
bitfld.quad 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
newline
bitfld.quad 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
bitfld.quad 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
group.quad SPR:0x339C1++0x00
line.quad 0x00 "PMCNTENSET_EL0,Count Enable Set Register"
bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
bitfld.quad 0x00  30. "P30,Event Counter 30 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  29. "P29,Event Counter 29 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  28. "P28,Event Counter 28 enable bit" "Disabled,Enabled"
newline
bitfld.quad 0x00  27. "P27,Event Counter 27 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  26. "P26,Event Counter 26 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  25. "P25,Event Counter 25 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  24. "P24,Event Counter 24 enable bit" "Disabled,Enabled"
newline
bitfld.quad 0x00  23. "P23,Event Counter 23 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  22. "P22,Event Counter 22 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  21. "P21,Event Counter 21 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  20. "P20,Event Counter 20 enable bit" "Disabled,Enabled"
newline
bitfld.quad 0x00  19. "P19,Event Counter 19 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  18. "P18,Event Counter 18 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  17. "P17,Event Counter 17 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  16. "P16,Event Counter 16 enable bit" "Disabled,Enabled"
newline
bitfld.quad 0x00  15. "P15,Event Counter 15 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  14. "P14,Event Counter 14 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  13. "P13,Event Counter 13 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  12. "P12,Event Counter 12 enable bit" "Disabled,Enabled"
newline
bitfld.quad 0x00  11. "P11,Event Counter 11 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  10. "P10,Event Counter 10 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  9. "P9,Event Counter 9 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  8. "P8,Event Counter 8 enable bit" "Disabled,Enabled"
newline
bitfld.quad 0x00  7. "P7,Event Counter 7 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  6. "P6,Event Counter 6 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  5. "P5,Event Counter 5 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  4. "P4,Event Counter 4 enable bit" "Disabled,Enabled"
newline
bitfld.quad 0x00  3. "P3,Event Counter 3 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  2. "P2,Event Counter 2 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  1. "P1,Event Counter 1 enable bit" "Disabled,Enabled"
bitfld.quad 0x00  0. "P0,Event Counter 0 enable bit" "Disabled,Enabled"
group.quad SPR:0x339C2++0x00
line.quad 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register"
bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.quad 0x00  30. "P30,Event Counter 30 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  29. "P29,Event Counter 29 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  28. "P28,Event Counter 28 clear bit" "Disabled,Enabled"
newline
eventfld.quad 0x00  27. "P27,Event Counter 27 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  26. "P26,Event Counter 26 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  25. "P25,Event Counter 25 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  24. "P24,Event Counter 24 clear bit" "Disabled,Enabled"
newline
eventfld.quad 0x00  23. "P23,Event Counter 23 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  22. "P22,Event Counter 22 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  21. "P21,Event Counter 21 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  20. "P20,Event Counter 20 clear bit" "Disabled,Enabled"
newline
eventfld.quad 0x00  19. "P19,Event Counter 19 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  18. "P18,Event Counter 18 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  17. "P17,Event Counter 17 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  16. "P16,Event Counter 16 clear bit" "Disabled,Enabled"
newline
eventfld.quad 0x00  15. "P15,Event Counter 15 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  14. "P14,Event Counter 14 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  13. "P13,Event Counter 13 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  12. "P12,Event Counter 12 clear bit" "Disabled,Enabled"
newline
eventfld.quad 0x00  11. "P11,Event Counter 11 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  10. "P10,Event Counter 10 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  9. "P9,Event Counter 9 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  8. "P8,Event Counter 8 clear bit" "Disabled,Enabled"
newline
eventfld.quad 0x00  7. "P7,Event Counter 7 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  6. "P6,Event Counter 6 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  5. "P5,Event Counter 5 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  4. "P4,Event Counter 4 clear bit" "Disabled,Enabled"
newline
eventfld.quad 0x00  3. "P3,Event Counter 3 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  2. "P2,Event Counter 2 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  1. "P1,Event Counter 1 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  0. "P0,Event Counter 0 clear bit" "Disabled,Enabled"
group.quad SPR:0x339C3++0x00
line.quad 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register"
bitfld.quad 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
eventfld.quad 0x00  30. "P30,Event Counter 30 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  29. "P29,Event Counter 29 clear bit" "Disabled,Enabled"
eventfld.quad 0x00  28. "P28,Event Counter 28 overflow clear bit" "Disabled,Enabled"
newline
eventfld.quad 0x00  27. "P27,Event Counter 27 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  26. "P26,Event Counter 26 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  25. "P25,Event Counter 25 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  24. "P24,Event Counter 24 overflow clear bit" "Disabled,Enabled"
newline
eventfld.quad 0x00  23. "P23,Event Counter 23 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  22. "P22,Event Counter 22 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  21. "P21,Event Counter 21 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  20. "P20,Event Counter 20 overflow clear bit" "Disabled,Enabled"
newline
eventfld.quad 0x00  19. "P19,Event Counter 19 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  18. "P18,Event Counter 18 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  17. "P17,Event Counter 17 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  16. "P16,Event Counter 16 overflow clear bit" "Disabled,Enabled"
newline
eventfld.quad 0x00  15. "P15,Event Counter 15 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  14. "P14,Event Counter 14 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  13. "P13,Event Counter 13 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  12. "P12,Event Counter 12 overflow clear bit" "Disabled,Enabled"
newline
eventfld.quad 0x00  11. "P11,Event Counter 11 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  10. "P10,Event Counter 10 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  9. "P9,Event Counter 9 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  8. "P8,Event Counter 8 overflow clear bit" "Disabled,Enabled"
newline
eventfld.quad 0x00  7. "P7,Event Counter 7 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  6. "P6,Event Counter 6 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  5. "P5,Event Counter 5 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  4. "P4,Event Counter 4 overflow clear bit" "Disabled,Enabled"
newline
eventfld.quad 0x00  3. "P3,Event Counter 3 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  2. "P2,Event Counter 2 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  1. "P1,Event Counter 1 overflow clear bit" "Disabled,Enabled"
eventfld.quad 0x00  0. "P0,Event Counter 0 overflow clear bit" "Disabled,Enabled"
wgroup.quad SPR:0x339C4++0x00
line.quad 0x00 "PMSWINC_EL0,Performance Monitor Software Increment"
bitfld.quad 0x00  30. "P30,Increment PMN30" "No action,Increment"
bitfld.quad 0x00  29. "P29,Increment PMN29" "No action,Increment"
bitfld.quad 0x00  28. "P28,Increment PMN28" "No action,Increment"
bitfld.quad 0x00  27. "P27,Increment PMN27" "No action,Increment"
newline
bitfld.quad 0x00  26. "P26,Increment PMN26" "No action,Increment"
bitfld.quad 0x00  25. "P25,Increment PMN25" "No action,Increment"
bitfld.quad 0x00  24. "P24,Increment PMN24" "No action,Increment"
bitfld.quad 0x00  23. "P23,Increment PMN23" "No action,Increment"
newline
bitfld.quad 0x00  22. "P22,Increment PMN22" "No action,Increment"
bitfld.quad 0x00  21. "P21,Increment PMN21" "No action,Increment"
bitfld.quad 0x00  20. "P20,Increment PMN20" "No action,Increment"
bitfld.quad 0x00  19. "P19,Increment PMN19" "No action,Increment"
newline
bitfld.quad 0x00  18. "P18,Increment PMN18" "No action,Increment"
bitfld.quad 0x00  17. "P17,Increment PMN17" "No action,Increment"
bitfld.quad 0x00  16. "P16,Increment PMN16" "No action,Increment"
bitfld.quad 0x00  15. "P15,Increment PMN15" "No action,Increment"
newline
bitfld.quad 0x00  14. "P14,Increment PMN14" "No action,Increment"
bitfld.quad 0x00  13. "P13,Increment PMN13" "No action,Increment"
bitfld.quad 0x00  12. "P12,Increment PMN12" "No action,Increment"
bitfld.quad 0x00  11. "P11,Increment PMN11" "No action,Increment"
newline
bitfld.quad 0x00  10. "P10,Increment PMN10" "No action,Increment"
bitfld.quad 0x00  9. "P9,Increment PMN9" "No action,Increment"
bitfld.quad 0x00  8. "P8,Increment PMN8" "No action,Increment"
bitfld.quad 0x00  7. "P7,Increment PMN7" "No action,Increment"
newline
bitfld.quad 0x00  6. "P6,Increment PMN6" "No action,Increment"
bitfld.quad 0x00  5. "P5,Increment PMN5" "No action,Increment"
bitfld.quad 0x00  4. "P4,Increment PMN4" "No action,Increment"
bitfld.quad 0x00  3. "P3,Increment PMN3" "No action,Increment"
newline
bitfld.quad 0x00  2. "P2,Increment PMN2" "No action,Increment"
bitfld.quad 0x00  1. "P1,Increment PMN1" "No action,Increment"
bitfld.quad 0x00  0. "P0,Increment PMN0" "No action,Increment"
group.quad SPR:0x339C5++0x00
line.quad 0x00 "PMSELR_EL0,Performance Monitor Select Register"
bitfld.quad 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.open "Common Event Identification Registers"
if (CORENAME()=="CORTEXA57")
rgroup.quad SPR:0x339C6++0x0
line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register 0"
bitfld.quad 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
bitfld.quad 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
bitfld.quad 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
newline
bitfld.quad 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
bitfld.quad 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
bitfld.quad 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
newline
bitfld.quad 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.quad 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.quad 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
newline
bitfld.quad 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
bitfld.quad 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.quad 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
newline
bitfld.quad 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
bitfld.quad 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
bitfld.quad 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.quad 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
bitfld.quad 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.quad 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
newline
bitfld.quad 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
bitfld.quad 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.quad 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
newline
bitfld.quad 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
bitfld.quad 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.quad 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
newline
bitfld.quad 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
bitfld.quad 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.quad 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
newline
bitfld.quad 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
bitfld.quad 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.quad 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
newline
bitfld.quad 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
elif (CORENAME()=="CORTEXA53")
rgroup.quad SPR:0x339C6++0x0
line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register 0"
bitfld.quad 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented"
bitfld.quad 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
bitfld.quad 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
newline
bitfld.quad 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
bitfld.quad 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
bitfld.quad 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
newline
bitfld.quad 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
bitfld.quad 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.quad 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
newline
bitfld.quad 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
bitfld.quad 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
bitfld.quad 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
newline
bitfld.quad 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
bitfld.quad 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
bitfld.quad 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
newline
bitfld.quad 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.quad 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
bitfld.quad 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
newline
bitfld.quad 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
bitfld.quad 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
bitfld.quad 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
newline
bitfld.quad 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.quad 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
bitfld.quad 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
newline
bitfld.quad 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
bitfld.quad 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
bitfld.quad 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
newline
bitfld.quad 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
bitfld.quad 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
bitfld.quad 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
newline
bitfld.quad 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.quad 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
endif
rgroup.quad SPR:0x339C7++0x0
line.quad 0x00 "PMCEID1_EL0,Common Event Identification Register 1"
bitfld.quad 0x00 0. "EVENT32,Level 2 cache allocate" "Not implemented,Implemented"
tree.end
newline
group.quad spr:0x339D0++0x00
line.quad 0x00 "PMCCNTR_EL0,Performance Monitor Cycle Count Register"
group.quad SPR:0x339D1++0x00
line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register"
group.quad SPR:0x339D2++0x00
line.quad 0x00 "PMXEVCNTR_EL0,Performance Monitor Event Count Register"
group.quad SPR:0x339E0++0x00
line.quad 0x00 "PMUSERENR_EL0,Performance Monitor User Enable Register"
bitfld.quad 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "EC,Cycle counter read enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "EN,User mode access enable" "Disabled,Enabled"
group.quad SPR:0x309E1++0x00
line.quad 0x00 "PMINTENSET_EL1,Performance Monitor Interrupt Enable Set"
bitfld.quad 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled"
bitfld.quad 0x00  30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00  27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00  23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00  19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00  15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00  11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00  7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00  3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00  0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.quad SPR:0x309E2++0x00
line.quad 0x00 "PMINTENCLR_EL1,Performance Monitor Interrupt Enable Clear"
bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.quad 0x00  30. "P30,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  29. "P29,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  28. "P28,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.quad 0x00  27. "P27,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  26. "P26,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  25. "P25,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  24. "P24,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.quad 0x00  23. "P23,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  22. "P22,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  21. "P21,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  20. "P20,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.quad 0x00  19. "P19,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  18. "P18,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  17. "P17,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  16. "P16,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.quad 0x00  15. "P15,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  14. "P14,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  13. "P13,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  12. "P12,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.quad 0x00  11. "P11,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  10. "P10,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  9. "P9,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  8. "P8,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.quad 0x00  7. "P7,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  6. "P6,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  5. "P5,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  4. "P4,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.quad 0x00  3. "P3,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  2. "P2,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  1. "P1,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.quad 0x00  0. "P0,Overflow Interrupt Clear" "Disabled,Enabled"
group.quad SPR:0x339E3++0x00
line.quad 0x00 "PMOVSSET_EL0,Performance Monitor Overflow Flag Status Set Register"
group.quad SPR:(0x33E80+0x0)++0x00
line.quad 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0"
group.quad SPR:(0x33EC0+0x0)++0x00
line.quad 0x00 "PMEVTYPER0_EL0,Performance Monitors Selected Event Type Register 0"
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x1)++0x00
line.quad 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1"
group.quad SPR:(0x33EC0+0x1)++0x00
line.quad 0x00 "PMEVTYPER1_EL0,Performance Monitors Selected Event Type Register 1"
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x2)++0x00
line.quad 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2"
group.quad SPR:(0x33EC0+0x2)++0x00
line.quad 0x00 "PMEVTYPER2_EL0,Performance Monitors Selected Event Type Register 2"
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x3)++0x00
line.quad 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3"
group.quad SPR:(0x33EC0+0x3)++0x00
line.quad 0x00 "PMEVTYPER3_EL0,Performance Monitors Selected Event Type Register 3"
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x4)++0x00
line.quad 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4"
group.quad SPR:(0x33EC0+0x4)++0x00
line.quad 0x00 "PMEVTYPER4_EL0,Performance Monitors Selected Event Type Register 4"
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x5)++0x00
line.quad 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5"
group.quad SPR:(0x33EC0+0x5)++0x00
line.quad 0x00 "PMEVTYPER5_EL0,Performance Monitors Selected Event Type Register 5"
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:0x33EF7++0x00
line.quad 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register"
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
group.quad SPR:0x33E00++0x00
line.quad 0x00 "CNTFRQ_EL0,Counter Frequency Register"
rgroup.quad spr:0x33E01++0x00
line.quad 0x00 "CNTPCT_EL0,Counter Physical Count Register"
group.quad SPR:0x30E10++0x00
line.quad 0x00 "CNTKCTL_EL1,Timer PL1 Control Register"
bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
newline
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.quad SPR:0x33E20++0x00
line.quad 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue register"
group.quad SPR:0x33E21++0x00
line.quad 0x00 "CNTP_CTL_EL0,Counter PL1 Physical Timer Control Register"
bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad SPR:0x33E30++0x00
line.quad 0x00 "CNTV_TVAL_EL0,Counter PL1 Virtual Timer Value Register"
group.quad SPR:0x33E31++0x00
line.quad 0x00 "CNTV_CTL_EL0,Counter PL1 Virtual Timer Control Register"
bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x33E02++0x00
line.quad 0x00 "CNTVCT_EL0,Counter Virtual Count Register"
group.quad spr:0x33E22++0x00
line.quad 0x00 "CNTP_CVAL_EL0,Counter PL1 Physical Compare Value Register"
group.quad spr:0x33E32++0x00
line.quad 0x00 "CNTV_CVAL_EL0,Counter PL1 Virtual Compare Value Register"
group.quad spr:0x34E03++0x00
line.quad 0x00 "CNTVOFF_EL2,Counter Virtual Offset Register"
group.quad SPR:0x34E10++0x00
line.quad 0x00 "CNTHCTL_EL2,Counter Non-secure PL2 Control Register"
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit is the trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.quad SPR:0x34E20++0x00
line.quad 0x00 "CNTHP_TVAL_EL2,Counter Non-secure PL2 Physical Timer Value Register"
group.quad SPR:0x34E21++0x00
line.quad 0x00 "CNTHP_CTL_EL2,Counter Non-secure PL2 Physical Timer Control Register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x34E22++0x00
line.quad 0x00 "CNTHP_CVAL_EL2,Counter Non-secure PL2 Physical Compare Value Register"
group.quad SPR:0x37E20++0x00
line.quad 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical SecureTimer TimerValue register"
group.quad SPR:0x37E21++0x00
line.quad 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x37E22++0x00
line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue register"
tree.end
tree "Generic Interrupt Controller CPU Interface"
tree "AArch64 GIC Physical CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.quad spr:0x30C84++0x00
line.quad 0x00 "ICC_AP0R0_EL1,Interrupt Controller Active Priorities Group 0 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.quad spr:0x30C90++0x00
line.quad 0x00 "ICC_AP1R0_EL1,Interrupt Controller Active Priorities Group 1 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
if (((per.q(spr:0x30CB6))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated"
else
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
group.quad spr:0x30C83++0x00
line.quad 0x00 "ICC_BPR0_EL1,Interrupt Controller Binary Point Register 0"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
group.quad spr:0x30CC3++0x00
line.quad 0x00 "ICC_BPR1_EL1,Interrupt Controller Binary Point Register 1"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
group.quad spr:0x30CC4++0x00
line.quad 0x00 "ICC_CTLR_EL1,Interrupt Controller Control Register (EL1)"
rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported"
rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
newline
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Zero,Non-zero"
rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6. "PMHE,Controls whether the priority mask Register is used as a hint for interrupt distribution" "Disabled,Enabled"
bitfld.quad 0x00 1. "EOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "CBPR,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 interrupts" "Separate registers,Same Register"
group.quad spr:0x36CC4++0x00
line.quad 0x00 "ICC_CTLR_EL3,Interrupt Controller Control Register (EL3)"
rbitfld.quad 0x00 19. "ExtRange,Extended INTID range" "Not supported,Supported"
rbitfld.quad 0x00 18. "RSS,Range Selector Support" "0 - 15,0 - 255"
newline
rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported"
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported"
newline
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop"
bitfld.quad 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Secure EL1)" "Priority drop/Deactivation,Priority drop"
bitfld.quad 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (EL3)" "Enabled,Disabled"
newline
bitfld.quad 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same Register"
bitfld.quad 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same Register"
if (((per.q(spr:0x30CC4))&0x3800)==0x00)
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
elif (((per.q(spr:0x30CC4))&0x3800)==0x800)
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
endif
hgroup.quad spr:0x30C80++0x00
hide.quad 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0"
in
hgroup.quad spr:0x30CC0++0x00
hide.quad 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1"
in
newline
group.quad SPR:0x30CC6++0x00
line.quad 0x00 "ICC_IGRPEN0_EL1,Interrupt Group Enable Register 0"
bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad SPR:0x30CC7++0x00
line.quad 0x00 "ICC_IGRPEN1_EL1,Interrupt Group Enable Register 1 (EL1)"
bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad SPR:0x36CC7++0x00
line.quad 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)"
bitfld.quad 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.quad 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
group.quad SPR:0x30460++0x00
line.quad 0x00 "ICC_PMR_EL1,Priority Mask Register"
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.quad SPR:0x30CB3++0x00
line.quad 0x00 "ICC_RPR_EL1,Running Priority Register"
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
if (((per.q(spr:0x30CB7))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated."
else
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
if (((per.q(spr:0x30CB5))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated"
else
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
group.quad SPR:0x30CC5++0x00
line.quad 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1"
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.quad SPR:0x34C95++0x00
line.quad 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2"
bitfld.quad 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled"
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.quad SPR:0x36CC5++0x00
line.quad 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3"
bitfld.quad 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled"
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
tree.end
tree "AArch64 Virtual Interface Control System Registers"
tree.open "Hypervisor Active Priorities Registers"
group.quad SPR:0x34C80++0x00
line.quad 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0"
bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
if (CORENAME()=="CORTEXA53")
group.quad SPR:0x34C90++0x00
line.quad 0x00 "ICH_AP1R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0"
bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
endif
tree.end
newline
rgroup.quad SPR:0x34CB3++0x00
line.quad 0x00 "ICH_EISR_EL2,Interrupt Controller End of Interrupt Status Register"
bitfld.quad 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt"
rgroup.quad SPR:0x34CB5++0x00
line.quad 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register"
bitfld.quad 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt"
bitfld.quad 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt"
bitfld.quad 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt"
newline
bitfld.quad 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt"
group.quad SPR:0x34CB0++0x00
line.quad 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register"
bitfld.quad 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
bitfld.quad 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
bitfld.quad 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped"
newline
bitfld.quad 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
bitfld.quad 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
bitfld.quad 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
newline
bitfld.quad 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
if (((d.q(spr:(0x34CC0+0x0)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x0)++0x00
line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x0)++0x00
line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((d.q(spr:(0x34CC0+0x1)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x1)++0x00
line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x1)++0x00
line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((d.q(spr:(0x34CC0+0x2)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x2)++0x00
line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x2)++0x00
line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((d.q(spr:(0x34CC0+0x3)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x3)++0x00
line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x3)++0x00
line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
rgroup.quad SPR:0x34CB2++0x00
line.quad 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register"
bitfld.quad 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted"
bitfld.quad 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted"
bitfld.quad 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted"
newline
bitfld.quad 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted"
bitfld.quad 0x00 3. "NP,No Pending" "Not asserted,Asserted"
bitfld.quad 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted"
newline
bitfld.quad 0x00 1. "U,Underflow" "Not asserted,Asserted"
bitfld.quad 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted"
group.quad SPR:0x34CB7++0x00
line.quad 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register"
hexmask.quad.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
bitfld.quad 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.quad 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
newline
bitfld.quad 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled"
bitfld.quad 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register"
bitfld.quad 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs"
newline
bitfld.quad 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt"
bitfld.quad 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
group.quad SPR:0x34C94++0x00
line.quad 0x00 "ICH_VSEIR_EL2,Interrupt Controller Virtual System Error Interrupt Register"
rgroup.quad SPR:0x34CB1++0x00
line.quad 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register"
bitfld.quad 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
bitfld.quad 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
bitfld.quad 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported"
bitfld.quad 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported"
newline
bitfld.quad 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported"
bitfld.quad 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "Debug Registers"
rgroup.quad SPR:0x23010++0x00
line.quad 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register"
bitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
group.quad SPR:0x20020++0x00
line.quad 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable register"
bitfld.quad 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled"
bitfld.quad 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled"
group.quad spr:0x23040++0x00
line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register"
rgroup.quad SPR:0x23050++0x00
line.quad 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register"
wgroup.quad SPR:0x23050++0x00
line.quad 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register"
group.quad SPR:0x24070++0x00
line.quad 0x00 "DBGVCR32_EL2,Vector Catch Register"
bitfld.quad 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Low,High"
bitfld.quad 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Low,High"
bitfld.quad 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Low,High"
bitfld.quad 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Low,High"
newline
bitfld.quad 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Low,High"
bitfld.quad 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Low,High"
bitfld.quad 0x00 7. "SF,FIQ vector catch enable in Secure state" "Low,High"
bitfld.quad 0x00 6. "SI,IRQ vector catch enable in Secure state" "Low,High"
newline
bitfld.quad 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Low,High"
bitfld.quad 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Low,High"
bitfld.quad 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Low,High"
bitfld.quad 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Low,High"
group.quad SPR:0x20002++0x00
line.quad 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register"
group.quad SPR:0x20022++0x00
line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register"
bitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.quad 0x00 27. "RXO,Save/restore bit" "Low,High"
bitfld.quad 0x00 26. "TXU,Save/restore bit" "Low,High"
newline
bitfld.quad 0x00 22.--23. "INTDIS,Save/restore bits" "0,1,2,3"
bitfld.quad 0x00 21. "TDA,Save/restore bit" "Low,High"
bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled"
bitfld.quad 0x00 14. "HDE,Save/restore bit" "Low,High"
newline
bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled"
bitfld.quad 0x00 12. "TDCC,Trap accesses to the debug comms channel in EL0" "Disabled,Enabled"
bitfld.quad 0x00 6. "ERR,Save/restore bit" "Low,High"
bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled"
group.quad SPR:0x20032++0x00
line.quad 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register"
group.quad SPR:0x20062++0x00
line.quad 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register"
rgroup.quad spr:0x20100++0x00
line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register"
hexmask.quad 0x00 12.--47. 0x1000 "ROMADDR,ROM base physical address"
bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid"
wgroup.quad SPR:0x20104++0x00
line.quad 0x00 "OSLAR_EL1,OS Lock Access Register"
bitfld.quad 0x00 0. "OSLK,OS lock" "Unlock,Lock"
rgroup.quad SPR:0x20114++0x00
line.quad 0x00 "OSLSR_EL1,OS Lock Status Register"
bitfld.quad 0x00 2. "NTT,Not 32-bit access" "Low,High"
bitfld.quad 0x00 1. "OSLK,OS lock status" "Not locked,Locked"
bitfld.quad 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Impelemented,?..."
group.quad SPR:0x20134++0x00
line.quad 0x00 "OSDLR_EL1,OS Double-lock Register"
bitfld.quad 0x00 0. "DLK,OS double-lock control" "Not locked,Locked"
group.quad SPR:0x20144++0x00
line.quad 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register"
bitfld.quad 0x00 0. "CORENPDRQ,Core no powerdown request" "No,Yes"
group.quad SPR:0x20786++0x00
line.quad 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set"
bitfld.quad 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set"
bitfld.quad 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set"
bitfld.quad 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set"
bitfld.quad 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set"
newline
bitfld.quad 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set"
bitfld.quad 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set"
bitfld.quad 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set"
bitfld.quad 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set"
group.quad SPR:0x20796++0x00
line.quad 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear"
bitfld.quad 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.quad 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
bitfld.quad 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
bitfld.quad 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
newline
bitfld.quad 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.quad 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
bitfld.quad 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.quad 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
rgroup.quad SPR:0x207E6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
group.quad SPR:0x33450++0x00
line.quad 0x00 "DSPSR_EL0,Debug Saved Processor Status Register"
group.quad spr:0x33451++0x00
line.quad 0x00 "DLR_EL0,Debug Link Register"
tree.end
tree "Breakpoint Registers"
if (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0"
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0"
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0"
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x0)++0x0
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1"
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1"
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1"
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x10)++0x0
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2"
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2"
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2"
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x20)++0x0
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3"
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3"
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3"
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x30)++0x0
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4"
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4"
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4"
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x40)++0x0
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5"
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5"
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5"
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x50)++0x0
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Watchpoint Control Registers"
group.quad spr:(0x20006+0x0)++0x00 "Watchpoint 0"
line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
group.quad spr:(0x20006+0x10)++0x00 "Watchpoint 1"
line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
group.quad spr:(0x20006+0x20)++0x00 "Watchpoint 2"
line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
group.quad spr:(0x20006+0x30)++0x00 "Watchpoint 3"
line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree.end
tree.open "AArch32"
tree "ID Registers"
rgroup.long c15:0x0000++0x0
line.long 0x0 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code"
bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19. "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8"
newline
hexmask.long.word 0x0 4.--15. 0x10 "PART,Primary Part Number"
bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (CORENAME()=="CORTEXA57")
rgroup.long c15:0x0100++0x0
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.long c15:0x0100++0x0
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
endif
if corename()=="CORTEXA57"
rgroup.long c15:0x0300++0x0
line.long 0x0 "TLBTR,TLB Type Register"
endif
if corename()=="CORTEXA57"
rgroup.long c15:0x0500++0x0
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
newline
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented"
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
newline
bitfld.long 0x00 0.--1. "CPUID,Indicates the core number in the device" "1,2,3,4"
elif corename()=="CORTEXA53"
rgroup.long c15:0x0500++0x0
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
newline
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,?..."
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
newline
hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field"
endif
rgroup.long c15:0x0600++0x0
line.long 0x0 "REVIDR,Revision ID Register"
rgroup.long c15:0x0410++0x00
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0510++0x00
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..."
bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
rgroup.long c15:0x0610++0x00
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c15:0x0710++0x00
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..."
bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..."
rgroup.long c15:0x0620++0x00
line.long 0x00 "ID_MMFR4,ID_MMFR4"
bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented, implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
rgroup.long c15:0x0020++0x00
line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0"
bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..."
rgroup.long c15:0x0120++0x00
line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1"
bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0220++0x00
line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2"
bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0320++0x00
line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3"
bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..."
bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0420++0x00
line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4"
bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..."
newline
bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0520++0x00
line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5"
bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..."
newline
bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0010++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c15:0x0110++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
newline
bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
if corename()=="CORTEXA57"
rgroup.long c15:0x0210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
elif corename()=="CORTEXA53"
rgroup.long c15:0x0210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
endif
group.long c15:0x0310++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
if corename()=="CORTEXA57"
rgroup.long c15:0x6C9++0x0
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
newline
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
newline
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
newline
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
newline
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
newline
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
rgroup.long c15:0x7C9++0x0
line.long 0x00 "PMCEID1,Common Event Identification Register 1"
elif corename()=="CORTEXA53"
rgroup.long c15:0x6C9++0x0
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
newline
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
newline
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
newline
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
newline
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
newline
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
rgroup.long c15:0x7C9++0x0
line.long 0x00 "PMCEID1,Common Event Identification Register 1"
bitfld.long 0x00 0. "EVENT32,L2D Cache Allocate" "Not implemented,Implemented"
endif
group.long c15:0x020D++0x00
line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register"
group.long c15:0x030D++0x00
line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register"
group.long c15:0x040D++0x00
line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register"
group.long c15:0x420D++0x00
line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register"
tree.end
tree "System Control and Configuration"
if corename()=="CORTEXA57"
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,System Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
else
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
endif
group.quad c15:0x100F0++0x01
line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register"
bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced"
bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes"
newline
bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes"
bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled"
newline
bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes"
bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes"
newline
bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled"
bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled"
newline
bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes"
bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes"
newline
bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes"
bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes"
newline
bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes"
bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes"
newline
bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes"
newline
bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced"
bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes"
newline
bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced"
bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes"
newline
bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes"
bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes"
newline
bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled"
bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced"
newline
bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled"
bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled"
newline
bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced"
bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced"
newline
bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes"
bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes"
newline
bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes"
bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes"
newline
bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes"
bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced"
bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced"
newline
bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled"
bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled"
newline
bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled"
bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced"
newline
bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes"
bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled"
bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes"
bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes"
bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled"
group.quad c15:0x110F0++0x01
line.quad 0x00 "CPUECTLR,CPU Extended Control Register"
bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes"
bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines"
newline
bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines"
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
newline
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad c15:0x120F0++0x01
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address"
group.long c15:0x0101++0x0
line.long 0x0 "ACTLR,Auxiliary Control Register"
elif corename()=="CORTEXA53"
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad c15:0x100F0++0x01
line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register"
bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes"
bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes"
newline
bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled"
bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
newline
bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes"
bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes"
newline
bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes"
bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes"
newline
bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams"
bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled"
bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes"
group.quad c15:0x110F0++0x01
line.quad 0x00 "CPUECTLR,CPU Extended Control Register"
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
newline
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad c15:0x120F0++0x01
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address"
group.long c15:0x0101++0x0
line.long 0x0 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
endif
if corename()=="CORTEXA57"
group.long c15:0x0201++0x00
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x0 28. "TRCDIS,Disable CP14 access to trace registers" "No,Yes"
newline
bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full"
bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full"
elif corename()=="CORTEXA53"
group.long c15:0x201++0x00
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 only,Reserved,Full"
newline
bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 only,Reserved,Full"
endif
group.long c15:0x0011++0x0
line.long 0x00 "SCR,Secure Configuration Register"
bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped"
bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped"
newline
bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes"
newline
bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes"
bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
newline
bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
bitfld.long 0x00 3. "EA,External Abort  exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
newline
bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
newline
bitfld.long 0x00 0. "NS,Secure mode " "Secure,Non-secure"
group.long c15:0x0111++0x00
line.long 0x00 "SDER,Secure Debug Enable Register"
bitfld.long 0x00 1. "SUNIDEN,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
bitfld.long 0x00 0. "SUIDEN,Invasive Secure User Debug Enable bit" "Denied,Permitted"
group.long c15:0x0131++0x00
line.long 0x00 "SDCR,Secure Debug Control Register"
bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes"
bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes"
newline
bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled"
group.long c15:0x0211++0x00
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
newline
bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
if corename()=="CORTEXA57"
group.long c15:0x000C++0x00
line.long 0x00 "VBAR,Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
group.long c15:0x010C++0x00
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
elif corename()=="CORTEXA53"
group.long c15:0x000C++0x00
line.long 0x00 "VBAR,Vector Base Address Register"
group.long c15:0x010C++0x00
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
endif
rgroup.long c15:0x001C++0x00
line.long 0x00 "ISR,Interrupt Status Register"
bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending"
bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending"
newline
bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending"
group.long c15:0x020C++0x00
line.long 0x00 "RMR,Reset Management Register"
bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64"
group.long c15:0x0015++0x00
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
group.long c15:0x0115++0x00
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
if corename()=="CORTEXA57"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable"
bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable"
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Async. external,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Async. parity/on memory access,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable"
bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable"
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/1st level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/1st level,Permission/1nd level,Sync. external/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..."
endif
elif corename()=="CORTEXA53"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX/STREX,?..."
else
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/section,Instruction cache maintenance,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/1st level,Permission/section,Sync. external/2nd level,Permission/2nd level,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..."
endif
endif
if corename()=="CORTEXA57"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
elif corename()=="CORTEXA53"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
endif
group.long c15:0x0006++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
group.long c15:0x0206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
if corename()=="CORTEXA57"
rgroup.long c15:0x103F++0x00
line.long 0x00 "CBAR,Configuration Base Address Register"
hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]"
hexmask.long.word 0x00 0.--11. 1. "PERIPHBASE[42:32],Periphbase[42:32]"
elif corename()=="CORTEXA53"
rgroup.long c15:0x103F++0x00
line.long 0x00 "CBAR,Configuration Base Address Register"
hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]"
hexmask.long.byte 0x00 0.--7. 1. "PERIPHBASE[39:32],Periphbase[39:32]"
endif
group.long c15:0x000D++0x00
line.long 0x00 "FCSEIDR,FCSE Process ID register"
group.long c15:0x020D++0x00
line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register"
group.long c15:0x030D++0x00
line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register"
group.long c15:0x040D++0x00
line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register"
tree.end
tree "Memory Management Unit"
if corename()=="CORTEXA57"
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,System Control Register"
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled"
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled"
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
// MPIDR[31]==1 case is missing here for TTBR0 and TTBR1
group.long c15:0x0002++0x00
line.long 0x00 "TTBR0,Translation Table Base Registers"
hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base address"
bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner"
newline
bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 2. "IMP,Implementation" "Low,High"
newline
bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable"
bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable"
group.long c15:0x0102++0x00
line.long 0x00 "TTBR1,Translation Table Base Registers"
hexmask.long 0x00 6.--31. 0x40 "TTBA,Translation table base address"
bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner"
newline
bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 2. "IMP,Implementation" "Low,High"
newline
bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable"
bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable"
else
group.quad c15:0x10020++0x01
line.quad 0x00 "TTBR0,Translation Table Base Registers"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad c15:0x11020++0x01
line.quad 0x00 "TTBR1,Translation Table Base Registers"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
endif
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes"
newline
bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes"
bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7"
else
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable"
newline
bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
newline
bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes"
bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected"
newline
bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
endif
elif corename()=="CORTEXA53"
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,System Control Register"
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled"
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.quad c15:0x10020++0x01
line.quad 0x00 "TTBR0,Translation Table Base Register 0"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad c15:0x11020++0x01
line.quad 0x00 "TTBR1,Translation Table Base Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
newline
bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes"
bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected"
newline
bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
else
group.long c15:0x0002++0x00
line.long 0x00 "TTBR0,Translation Table Base Register 0"
hexmask.long 0x00 7.--31. 0x80 "TTB0,Translation table base 0 address"
bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner"
bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable"
group.long c15:0x0102++0x00
line.long 0x00 "TTBR1,Translation Table Base Register 1"
hexmask.long 0x00 7.--31. 0x80 "TTB1,Translation table base 1 address"
bitfld.long 0x00 0. 6. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner"
bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable"
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes"
newline
bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes"
bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7"
endif
endif
if corename()=="CORTEXA57"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
elif corename()=="CORTEXA53"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
endif
group.long c15:0x4202++0x00
line.long 0x00 "HTCR,Hypervisor Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
group.long c15:0x0003++0x00
line.long 0x00 "DACR,Domain Access Control Register"
bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.quad c15:0x10070++0x01
line.quad 0x00 "PAR,Physical Address Register"
else
group.long c15:0x0047++0x00
line.long 0x00 "PAR,Physical Address Register"
endif
tree.open "Memory Attribute Indirection Registers"
group.long c15:0x403A++0x00
line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0"
group.long c15:0x413A++0x00
line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1"
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x003A++0x00
line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0"
group.long c15:0x013A++0x00
line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1"
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x002A++0x0
line.long 0x00 "PRRR,Primary Region Remap Register"
bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 19. "NS1,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
bitfld.long 0x00 18. "NS0,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
newline
bitfld.long 0x00 17. "DS1,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
bitfld.long 0x00 16. "DS0,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
newline
bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
group.long c15:0x012A++0x0
line.long 0x00 "NMRR,Normal Memory Remap Register"
bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
endif
tree.end
newline
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x10d++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
else
group.long c15:0x10d++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process identifier"
hexmask.long.byte 0x00 0.--7. 1. "ASID,Address space identifier"
endif
tree.end
tree "Virtualization Extensions"
group.long c15:0x4000++0x0
line.long 0x00 "VPIDR,Virtualization Processor ID Register"
group.long c15:0x4500++0x00
line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register"
group.long c15:0x420D++0x00
line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,System Control Register"
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled"
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled"
group.long c15:0x4101++0x00
line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
if corename()=="CORTEXA57"
group.long c15:0x4011++0x00
line.long 0x00 "HCR,Hypervisor Configuration Register"
bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled"
bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled"
newline
bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
newline
bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled"
bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
newline
bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
newline
bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3"
newline
bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "Not aborted,Aborted"
newline
bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt"
newline
bitfld.long 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed"
bitfld.long 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed"
newline
bitfld.long 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed"
bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override"
bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled"
elif corename()=="CORTEXA53"
group.long c15:0x4011++0x00
line.long 0x00 "HCR,Hypervisor Configuration Register"
bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
bitfld.long 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
newline
bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled"
bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled"
newline
bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled"
bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
newline
bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled"
newline
bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3"
bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "No aborted,Aborted"
bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt"
newline
bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 5. "AMO,A-bit Mask Override" "No override,Override"
newline
bitfld.long 0x00 4. "IMO,I-bit Mask Override" "No override,Override"
bitfld.long 0x00 3. "FMO,F-bit Mask Override" "No override,Override"
newline
bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override"
newline
bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled"
endif
group.long c15:0x4411++0x00
line.long 0x00 "HCR2,Hypervisor Configuration Register 2"
bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes"
group.long c15:0x4111++0x00
line.long 0x00 "HDCR,Hypervisor Debug Control Register"
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
newline
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
newline
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long c15:0x4211++0x00
line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register"
bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.long 0x0 20. "TTA,Trap Trace Access" "Not trapped,?..."
newline
bitfld.long 0x0 15. "TASE,Trap Advanced SIMD extensions" "Not trapped,Trapped"
bitfld.long 0x0 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped"
newline
bitfld.long 0x0 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped"
group.long c15:0x4311++0x00
line.long 0x00 "HSTR,Hypervisor System Trap Register"
bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Disabled,Enabled"
bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "Reserved,?..."
newline
hexmask.long.word 0x00 5.--13. 1. "T4_15,Trap to Hypervisor mode Non-secure priv 5 - 13"
bitfld.long 0x00 0.--3. "T0_13,Trap to Hypervisor mode Non-secure priv 0 - 3," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long c15:0x4711++0x00
line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register"
if corename()=="CORTEXA57"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
elif corename()=="CORTEXA53"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
endif
group.long c15:0x4202++0x00
line.long 0x00 "HTCR,Hypervisor Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
group.long c15:0x4212++0x00
line.long 0x00 "VTCR,Virtualization Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3"
bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3"
newline
bitfld.long 0x00 4. "S,Sign-extension of the T0SZ field" "Low,High"
bitfld.long 0x00 0.--3. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long c15:0x4015++0x00
line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register"
group.long c15:0x4115++0x00
line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Syndrome Register"
group.long c15:0x4006++0x00
line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register"
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to c15,Trapped MCRR/MRRC to c15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,Reserved,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
hexmask.long 0x00 0.--24. 1. "ISS,Instruction specific syndrome"
group.long c15:0x4206++0x00
line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register"
group.long c15:0x4406++0x00
line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register"
hexmask.long 0x00 4.--31. 1. "FIPA[39:12],Bits [39:12] of the faulting intermediate physical address"
tree.open "Hypervisor Memory Attribute Indirection Registers"
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x403A++0x00
line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0"
group.long c15:0x413A++0x00
line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1"
tree.end
newline
group.long c15:0x400C++0x00
line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "HVBADDR,Hypervisor Vector Base Address"
tree.end
tree "Cache Control and Configuration"
rgroup.long c15:0x0100++0x0
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,PIPT"
newline
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
if corename()=="CORTEXA57"
rgroup.long c15:0x1100++0x0
line.long 0x0 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..."
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
newline
bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..."
bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..."
bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..."
newline
bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
elif corename()=="CORTEXA53"
rgroup.long c15:0x1100++0x0
line.long 0x0 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..."
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..."
newline
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
endif
rgroup.long c15:0x1700++0x0
line.long 0x00 "AIDR,Auxiliary ID Register"
rgroup.long c15:0x1000++0x0
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,Supported"
bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported"
newline
bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported"
bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
newline
hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "16 bytes,32 bytes,64 bytes,128 bytes,?..."
group.long c15:0x2000++0x0
line.long 0x0 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..."
bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
tree "Level 1 memory system"
if corename()=="CORTEXA57"
group.long c15:0x001F++0x00
line.long 0x00 "DL1DATA0,Data L1 Data 0 Register"
group.long c15:0x011F++0x00
line.long 0x00 "DL1DATA1,Data L1 Data 1 Register"
group.long c15:0x021F++0x00
line.long 0x00 "DL1DATA2,Data L1 Data 2 Register"
group.long c15:0x031F++0x00
line.long 0x00 "DL1DATA3,Data L1 Data 3 Register"
group.long c15:0x000F++0x00
line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register"
group.long c15:0x010F++0x00
line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register"
group.long c15:0x020F++0x00
line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register"
group.long c15:0x030F++0x00
line.long 0x00 "IL1DATA3,Instruction L1 Data 3 Register"
wgroup.long c15:0x04F++0x00
line.long 0x00 "RAMINDEX,RAM Index Operation Register"
elif corename()=="CORTEXA53"
rgroup.long c15:0x300F++0x00
line.long 0x00 "CDBGDR0,Cache Debug Data Register 0"
rgroup.long c15:0x310F++0x00
line.long 0x00 "CDBGDR1,Cache Debug Data Register 1"
rgroup.long c15:0x320F++0x00
line.long 0x00 "CDBGDR2,Cache Debug Data Register 2"
rgroup.long c15:0x330F++0x00
line.long 0x00 "CDBGDR3,Cache Debug Data Register 3"
wgroup.long c15:0x302F++0x00
line.long 0x00 "CDBGDCT,Cache Debug Data Cache Tag Read Operation Register"
wgroup.long c15:0x312F++0x00
line.long 0x00 "CDBGICT,Cache Debug Instruction Cache Tag Read Operation Register"
wgroup.long c15:0x304F++0x00
line.long 0x00 "CDBGDCD,Cache Debug Cache Debug Data Cache Data Read Operation Register"
wgroup.long c15:0x314F++0x00
line.long 0x00 "CDBGICD,Cache Debug Instruction Cache Data Read Operation Register"
wgroup.long c15:0x324F++0x00
line.long 0x00 "CDBGTD,Cache Debug TLB Data Read Operation Register"
endif
tree.end
tree "Level 2 memory system"
if corename()=="CORTEXA57"
group.long c15:0x1209++0x0
line.long 0x00 "L2CTLR,L2 Control Register"
bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes"
bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4"
newline
rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Not supported,Supported"
bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "DIECCE,Data in-line ECC enable" "Disabled,Enabled"
rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present"
newline
rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present"
rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1,2,Present"
newline
bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle"
bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles"
newline
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle"
bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
group.long c15:0x1309++0x0
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
newline
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.long c15:0x100F++0x00
line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register"
bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled"
bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced"
bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled"
newline
bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes"
bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes"
newline
bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled"
bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit"
newline
bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes"
bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes"
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
newline
bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes"
bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes"
newline
bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes"
bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes"
newline
bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled"
bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes"
newline
bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled"
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
newline
bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited"
bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes"
group.quad c15:0x130F0++0x01
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index"
elif corename()=="CORTEXA53"
group.long c15:0x1209++0x0
line.long 0x00 "L2CTLR,L2 Control Register"
bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4"
bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled"
newline
rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle"
newline
rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles"
group.long c15:0x1309++0x0
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
newline
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.long c15:0x100F++0x00
line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register"
bitfld.long 0x00 30.--31. "L2VC,L2 victim Control" "0,1,2,3"
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
group.quad c15:0x110F0++0x01
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address"
endif
tree.end
tree.end
tree "System Performance Monitor"
group.long c15:0xc9++0x00
line.long 0x0 "PMCR,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
newline
bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
newline
group.long c15:0x1c9++0x00
line.long 0x00 "PMNCNTENSET,Count Enable Set Register "
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
bitfld.long 0x00 30. "P30,Event Counter 30 enable bit" "Disabled,Enabled"
bitfld.long 0x00 29. "P29,Event Counter 29 enable bit" "Disabled,Enabled"
bitfld.long 0x00 28. "P28,Event Counter 28 enable bit" "Disabled,Enabled"
bitfld.long 0x00 27. "P27,Event Counter 27 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "P26,Event Counter 26 enable bit" "Disabled,Enabled"
bitfld.long 0x00 25. "P25,Event Counter 25 enable bit" "Disabled,Enabled"
bitfld.long 0x00 24. "P24,Event Counter 24 enable bit" "Disabled,Enabled"
bitfld.long 0x00 23. "P23,Event Counter 23 enable bit" "Disabled,Enabled"
bitfld.long 0x00 22. "P22,Event Counter 22 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "P21,Event Counter 21 enable bit" "Disabled,Enabled"
bitfld.long 0x00 20. "P20,Event Counter 20 enable bit" "Disabled,Enabled"
bitfld.long 0x00 19. "P19,Event Counter 19 enable bit" "Disabled,Enabled"
bitfld.long 0x00 18. "P18,Event Counter 18 enable bit" "Disabled,Enabled"
bitfld.long 0x00 17. "P17,Event Counter 17 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "P16,Event Counter 16 enable bit" "Disabled,Enabled"
bitfld.long 0x00 15. "P15,Event Counter 15 enable bit" "Disabled,Enabled"
bitfld.long 0x00 14. "P14,Event Counter 14 enable bit" "Disabled,Enabled"
bitfld.long 0x00 13. "P13,Event Counter 13 enable bit" "Disabled,Enabled"
bitfld.long 0x00 12. "P12,Event Counter 12 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "P11,Event Counter 11 enable bit" "Disabled,Enabled"
bitfld.long 0x00 10. "P10,Event Counter 10 enable bit" "Disabled,Enabled"
bitfld.long 0x00 9. "P9,Event Counter 9 enable bit" "Disabled,Enabled"
bitfld.long 0x00 8. "P8,Event Counter 8 enable bit" "Disabled,Enabled"
bitfld.long 0x00 7. "P7,Event Counter 7 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "P6,Event Counter 6 enable bit" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled"
bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled"
group.long c15:0x2c9++0x00
line.long 0x00 "PMCNTENCLR,Count Enable Clear Register"
eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00 30. "P30,Event Counter 30 clear bit" "Disabled,Enabled"
eventfld.long 0x00 29. "P29,Event Counter 29 clear bit " "Disabled,Enabled"
eventfld.long 0x00 28. "P28,Event Counter 28 clear bit " "Disabled,Enabled"
eventfld.long 0x00 27. "P27,Event Counter 27 clear bit " "Disabled,Enabled"
newline
eventfld.long 0x00 26. "P26,Event Counter 26 clear bit " "Disabled,Enabled"
eventfld.long 0x00 25. "P25,Event Counter 25 clear bit " "Disabled,Enabled"
eventfld.long 0x00 24. "P24,Event Counter 24 clear bit " "Disabled,Enabled"
eventfld.long 0x00 23. "P23,Event Counter 23 clear bit " "Disabled,Enabled"
eventfld.long 0x00 22. "P22,Event Counter 22 clear bit " "Disabled,Enabled"
newline
eventfld.long 0x00 21. "P21,Event Counter 21 clear bit " "Disabled,Enabled"
eventfld.long 0x00 20. "P20,Event Counter 20 clear bit " "Disabled,Enabled"
eventfld.long 0x00 19. "P19,Event Counter 19 clear bit " "Disabled,Enabled"
eventfld.long 0x00 18. "P18,Event Counter 18 clear bit " "Disabled,Enabled"
eventfld.long 0x00 17. "P17,Event Counter 17 clear bit " "Disabled,Enabled"
newline
eventfld.long 0x00 16. "P16,Event Counter 16 clear bit " "Disabled,Enabled"
eventfld.long 0x00 15. "P15,Event Counter 15 clear bit" "Disabled,Enabled"
eventfld.long 0x00 14. "P14,Event Counter 14 clear bit" "Disabled,Enabled"
eventfld.long 0x00 13. "P13,Event Counter 13 clear bit" "Disabled,Enabled"
eventfld.long 0x00 12. "P12,Event Counter 12 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00 11. "P11,Event Counter 11 clear bit" "Disabled,Enabled"
eventfld.long 0x00 10. "P10,Event Counter 10 clear bit" "Disabled,Enabled"
eventfld.long 0x00 9. "P9,Event Counter 9 clear bit" "Disabled,Enabled"
eventfld.long 0x00 8. "P8,Event Counter 8 clear bit" "Disabled,Enabled"
eventfld.long 0x00 7. "P7,Event Counter 7 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00 6. "P6,Event Counter 6 clear bit" "Disabled,Enabled"
eventfld.long 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled"
eventfld.long 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled"
eventfld.long 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled"
eventfld.long 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled"
eventfld.long 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled"
group.long c15:0x3c9++0x00
line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register"
eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
eventfld.long 0x00 30. "P30,PMN30 overflow" "No overflow,Overflow"
eventfld.long 0x00 29. "P29,PMN29 overflow" "No overflow,Overflow"
eventfld.long 0x00 28. "P28,PMN28 overflow" "No overflow,Overflow"
eventfld.long 0x00 27. "P27,PMN27 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 26. "P26,PMN26 overflow" "No overflow,Overflow"
eventfld.long 0x00 25. "P25,PMN25 overflow" "No overflow,Overflow"
eventfld.long 0x00 24. "P24,PMN24 overflow" "No overflow,Overflow"
eventfld.long 0x00 23. "P23,PMN23 overflow" "No overflow,Overflow"
eventfld.long 0x00 22. "P22,PMN22 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 21. "P21,PMN21 overflow" "No overflow,Overflow"
eventfld.long 0x00 20. "P20,PMN20 overflow" "No overflow,Overflow"
eventfld.long 0x00 19. "P19,PMN19 overflow" "No overflow,Overflow"
eventfld.long 0x00 18. "P18,PMN18 overflow" "No overflow,Overflow"
eventfld.long 0x00 17. "P17,PMN17 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 16. "P16,PMN16 overflow" "No overflow,Overflow"
eventfld.long 0x00 15. "P15,PMN15 overflow" "No overflow,Overflow"
eventfld.long 0x00 14. "P14,PMN14 overflow" "No overflow,Overflow"
eventfld.long 0x00 13. "P13,PMN13 overflow" "No overflow,Overflow"
eventfld.long 0x00 12. "P12,PMN12 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 11. "P11,PMN11 overflow" "No overflow,Overflow"
eventfld.long 0x00 10. "P10,PMN10 overflow" "No overflow,Overflow"
eventfld.long 0x00 9. "P9,PMN9 overflow" "No overflow,Overflow"
eventfld.long 0x00 8. "P8,PMN8 overflow" "No overflow,Overflow"
eventfld.long 0x00 7. "P7,PMN7 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 6. "P6,PMN6 overflow" "No overflow,Overflow"
eventfld.long 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow"
eventfld.long 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow"
eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow"
eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow"
eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow"
group.long c15:0x4c9++0x00
line.long 0x00 "PMSWINC,Performance Monitor Software Increment"
bitfld.long 0x00 30. "P30,Increment PMN30" "No action,Increment"
bitfld.long 0x00 29. "P29,Increment PMN29" "No action,Increment"
bitfld.long 0x00 28. "P28,Increment PMN28" "No action,Increment"
bitfld.long 0x00 27. "P27,Increment PMN27" "No action,Increment"
bitfld.long 0x00 26. "P26,Increment PMN26" "No action,Increment"
newline
bitfld.long 0x00 25. "P25,Increment PMN25" "No action,Increment"
bitfld.long 0x00 24. "P24,Increment PMN24" "No action,Increment"
bitfld.long 0x00 23. "P23,Increment PMN23" "No action,Increment"
bitfld.long 0x00 22. "P22,Increment PMN22" "No action,Increment"
bitfld.long 0x00 21. "P21,Increment PMN21" "No action,Increment"
newline
bitfld.long 0x00 20. "P20,Increment PMN20" "No action,Increment"
bitfld.long 0x00 19. "P19,Increment PMN19" "No action,Increment"
bitfld.long 0x00 18. "P18,Increment PMN18" "No action,Increment"
bitfld.long 0x00 17. "P17,Increment PMN17" "No action,Increment"
bitfld.long 0x00 16. "P16,Increment PMN16" "No action,Increment"
newline
bitfld.long 0x00 15. "P15,Increment PMN15" "No action,Increment"
bitfld.long 0x00 14. "P14,Increment PMN14" "No action,Increment"
bitfld.long 0x00 13. "P13,Increment PMN13" "No action,Increment"
bitfld.long 0x00 12. "P12,Increment PMN12" "No action,Increment"
bitfld.long 0x00 11. "P11,Increment PMN11" "No action,Increment"
newline
bitfld.long 0x00 10. "P10,Increment PMN10" "No action,Increment"
bitfld.long 0x00 9. "P9,Increment PMN9" "No action,Increment"
bitfld.long 0x00 8. "P8,Increment PMN8" "No action,Increment"
bitfld.long 0x00 7. "P7,Increment PMN7" "No action,Increment"
bitfld.long 0x00 6. "P6,Increment PMN6" "No action,Increment"
newline
bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment"
bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment"
bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment"
bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment"
bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment"
newline
bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment"
group.long c15:0x5c9++0x00
line.long 0x00 "PMSELR,Performance Monitor Select Register"
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..."
group.long c15:0xd9++0x00
line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register"
group.long c15:0x1d9++0x00
line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register"
group.long c15:0x2d9++0x00
line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register"
group.long c15:0xe9++0x00
line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register"
bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled"
bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled"
group.long c15:0x1e9++0x00
line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
bitfld.long 0x00 30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.long c15:0x2e9++0x00
line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear"
eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00 30. "P30,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 29. "P29,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 28. "P28,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 27. "P27,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 26. "P26,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 25. "P25,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 24. "P24,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 23. "P23,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 22. "P22,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 21. "P21,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 20. "P20,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 19. "P19,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 18. "P18,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 17. "P17,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 16. "P16,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 15. "P15,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 14. "P14,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 13. "P13,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 12. "P12,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 11. "P11,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 10. "P10,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 9. "P9,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 8. "P8,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 7. "P7,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 6. "P6,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled"
group.long c15:0x3e9++0x00
line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register"
group.long c15:0x8E++0x00
line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0"
group.long c15:(0x8E+0x40)++0x00
line.long 0x00 "PMEVTYPER0,Performance Monitors Selected Event Type Register 0"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x18E++0x00
line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1"
group.long c15:(0x18E+0x40)++0x00
line.long 0x00 "PMEVTYPER1,Performance Monitors Selected Event Type Register 1"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x28E++0x00
line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2"
group.long c15:(0x28E+0x40)++0x00
line.long 0x00 "PMEVTYPER2,Performance Monitors Selected Event Type Register 2"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x38E++0x00
line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3"
group.long c15:(0x38E+0x40)++0x00
line.long 0x00 "PMEVTYPER3,Performance Monitors Selected Event Type Register 3"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x48E++0x00
line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4"
group.long c15:(0x48E+0x40)++0x00
line.long 0x00 "PMEVTYPER4,Performance Monitors Selected Event Type Register 4"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x58E++0x00
line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5"
group.long c15:(0x58E+0x40)++0x00
line.long 0x00 "PMEVTYPER5,Performance Monitors Selected Event Type Register 5"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x07FE++0x00
line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
group.long c15:0x000E++0x00
line.long 0x00 "CNTFRQ,Counter Frequency Register"
rgroup.quad c15:0x100E0++0x01
line.quad 0x00 "CNTPCT,Counter Physical Count Register"
group.long c15:0x001E++0x00
line.long 0x00 "CNTKCTL,Timer PL1 Control Register"
bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
newline
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.long c15:0x002E++0x00
line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register"
group.long c15:0x012E++0x00
line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.long c15:0x003E++0x00
line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register"
group.long c15:0x013E++0x00
line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x110E0++0x01
line.quad 0x00 "CNTVCT,Counter Virtual Count Register"
group.quad c15:0x120E0++0x01
line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register"
group.quad c15:0x130E0++0x01
line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register"
group.quad c15:0x140E0++0x01
line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register"
group.long c15:0x401E++0x00
line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register"
bitfld.long 0x00 4.--7. "EVNTI,Select trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "EL1VCTEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
group.long c15:0x402E++0x00
line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register"
group.long c15:0x412E++0x00
line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x160E0++0x01
line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register"
tree.end
tree "Generic Interrupt Controller CPU Interface"
tree "AArch32 GIC Physical CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.long c15:0x048C++0x00
line.long 0x00 "ICC_AP0R0,Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:0x009C++0x00
line.long 0x00 "ICC_AP1R0,Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
wgroup.quad c15:0x110C0++0x01
line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "SGIID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
group.long c15:0x038C++0x00
line.long 0x00 "ICC_BPR0,Binary Point Register 0"
bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7"
group.long c15:0x03CC++0x00
line.long 0x00 "ICC_BPR1,Binary Point Register 1"
bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7"
group.long c15:0x04CC++0x00
line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,Supported"
rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1"
newline
bitfld.long 0x00 0. "CBPR,Common Binary Point Register" "0,1"
group.long c15:0x64CC++0x00
line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3"
rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported"
newline
rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled"
bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled"
bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt(EL3)" "Enabled,Disabled"
newline
bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same register"
bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same register"
if (((per.l(c15:0x4CC))&0x3800)==0x00)
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.long c15:0x018C++0x00
line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.long c15:0x01CC++0x00
line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.long c15:0x028C++0x00
line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
rgroup.long c15:0x02CC++0x00
line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
elif (((per.l(c15:0x4CC))&0x3800)==0x800)
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.long c15:0x018C++0x00
line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.long c15:0x01CC++0x00
line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.long c15:0x028C++0x00
line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
rgroup.long c15:0x02CC++0x00
line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
endif
hgroup.long c15:0x008C++0x00
hide.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0"
in
hgroup.long c15:0x00CC++0x00
hide.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1"
in
group.long c15:0x06CC++0x00
line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x07CC++0x00
line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x0064++0x00
line.long 0x00 "ICC_PMR,Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.long c15:0x03BC++0x00
line.long 0x00 "ICC_RPR,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
wgroup.quad c15:0x120C0++0x01
line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
wgroup.quad c15:0x100C0++0x01
line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
group.long c15:0x05CC++0x00
line.long 0x00 "ICC_SRE,System Register Enable Register for EL1"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
if corename()=="CORTEXA53"
group.long c15:0x459C++0x00
line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
endif
group.long c15:0x65CC++0x00
line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.long c15:0x67CC++0x00
line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable"
bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
tree.end
tree "AArch32 Virtual Interface Control System Registers"
tree.open "Hypervisor Active Priorities Registers"
group.long c15:0x408C++0x00
line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:0x409C++0x00
line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
rgroup.long c15:0x43BC++0x00
line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register"
bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt"
newline
bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt"
rgroup.long c15:0x45BC++0x00
line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register"
bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt"
bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt"
bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt"
newline
bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt"
group.long c15:0x40BC++0x00
line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register"
bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped"
newline
bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
newline
bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
group.long c15:(0x40CC+0x0)++0x00
line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x100)++0x00
line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x200)++0x00
line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x300)++0x00
line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40EC+0x0)++0x00
line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x100)++0x00
line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x200)++0x00
line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x300)++0x00
line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
rgroup.long c15:0x42BC++0x00
line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt State Register"
bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted"
bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted"
newline
bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted"
bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted"
newline
bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted"
bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted"
group.long c15:0x459C++0x00
line.long 0x00 "ICH_SRE,Hypervisor System Register"
group.long c15:0x47BC++0x00
line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
newline
bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register"
bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs"
newline
bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt"
bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
group.long c15:0x449C++0x00
line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register"
rgroup.long c15:0x41BC++0x00
line.long 0x00 "ICH_VTR,Interrupt Controller VGIC Type Register"
bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported"
bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported"
newline
bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported"
bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "Debug Registers"
tree "Coresight Management Registers"
if corename()=="CORTEXA57"
rgroup.long c14:0x0000++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
newline
hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version"
bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported"
bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented"
elif corename()=="CORTEXA53"
rgroup.long c14:0x0000++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
newline
hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version"
bitfld.long 0x0 15. "DEVID,Debug Device ID" "Low,High"
bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported"
newline
bitfld.long 0x0 13. "PCSR,PC Sample register implemented" "Not implemented,Implemented"
bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented"
hexmask.long.byte 0x0 4.--7. 1. "VARIANT,Implementation-defined Variant Number"
newline
hexmask.long.byte 0x0 0.--3. 1. "REVISION,Implementation-defined Revision Number"
endif
rgroup.long c14:0x0060++0x0
line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register"
group.long c14:0x0070++0x0
line.long 0x00 "DBGVCR,Debug Vector Catch register"
bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 30. "IRQVCE_NS,IRG vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled"
bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
group.long c14:0x0020++0x00
line.long 0x00 "DBGDCCINT,DCC Interrupt Enable Register"
bitfld.long 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled"
bitfld.long 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled"
group.long c14:0x0200++0x0
line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)"
group.long c14:0x0220++0x0
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled"
bitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled"
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
newline
bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled"
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
bitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled"
newline
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
rgroup.long c14:0x0010++0x0
line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
newline
bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
wgroup.long c14:0x0230++0x0
line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)"
group.long c14:0x0050++0x0
line.long 0x00 "DBGDTRTXINT,Debug Transmit/Receive Register (Internal View)"
group.long c14:0x0687++0x0
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set"
newline
bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set"
bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set"
newline
bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set"
group.long c14:0x0697++0x0
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
rgroup.long c14:0x06E7++0x0
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. "SNDFI,Secure non-invasive debug features implementation" "No effect,Implemented"
bitfld.long 0x00 6. "SNDE,Secure non-invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 5. "SIDFI,Secure invasive debug features implementation" "No effect,Implemented"
newline
bitfld.long 0x00 4. "SIDE,Secure invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NSNDFI,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
bitfld.long 0x00 2. "NSNDE,Non-secure non-invasive debug enable" "0,1"
newline
bitfld.long 0x00 1. "NSIDFI,Non-secure invasive debug features implementation" "Not implemented,Implemented"
bitfld.long 0x00 0. "NSIDE,Non-secure invasive debug enable" "0,1"
rgroup.long c14:0x0707++0x0
line.long 0x0 "DBGDEVID2,Debug Device ID Register 2"
rgroup.long c14:0x0717++0x0
line.long 0x0 "DBGDEVID1,Debug Device ID Register 1"
bitfld.long 0x00 0.--3. "PCSROFFSET,This field defines the offset applied to DBGPCSR samples" "0,1,No offset,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c14:0x0727++0x00
line.long 0x00 "DBGDEVID,Debug Device ID Register 0"
bitfld.long 0x00 28.--31. "CIDMASK,Specifies the level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..."
bitfld.long 0x00 24.--27. "AUXREGS,Specifies support for the Debug External Auxiliary Control Register" "Not implemented,?..."
bitfld.long 0x00 20.--23. "DOUBLELOCK,Specifies support for the Debug OS Double Lock Register" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 16.--19. "VIREXTNS,Specifies whether EL2 is implemented" "Reserved,Implemented,?..."
bitfld.long 0x00 12.--15. "VECTORCATCH,Defines the form of the vector catch event implemented" "Implemented,?..."
bitfld.long 0x00 8.--11. "BPADDRMASK,Indicates the level of support for the Immediate Virtual Address(IVA) matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented"
newline
bitfld.long 0x00 4.--7. "WPADDRMASK,Indicates the level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..."
bitfld.long 0x00 0.--3. "PCSAMPLE,Indicates the level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..."
tree.end
newline
rgroup.quad c14:0x10010++0x1
line.quad 0x0 "DBGDRAR,Debug ROM Address Register"
hexmask.quad.word 0x0 32.--47. 0x1 "ROMADDR,ROM physical address"
hexmask.quad.tbyte 0x0 12.--31. 0x10 "ROMADDR,ROM physical address"
bitfld.quad 0x0 1. "VALID1,ROM table address valid" "Not valid,Valid"
newline
bitfld.quad 0x0 0. "VALID0,ROM table address valid" "Not valid,Valid"
rgroup.quad c14:0x10020++0x1
line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register"
wgroup.long c14:0x0401++0x00
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
rgroup.long c14:0x0411++0x00
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required"
bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked"
bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..."
if (((per.l(c14:0x0411))&0x2)==0x2)
group.long c14:0x0260++0x00
line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
else
hgroup.long c14:0x0260++0x00
hide.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
endif
group.long c14:0x0431++0x00
line.long 0x00 "DBGOSDLR,Debug OS Double Lock Register"
bitfld.long 0x00 0. "DLK,OS Double Lock control bit" "Not locked,Locked"
group.long c14:0x0441++0x00
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Low,High"
tree.end
tree "Breakpoint Registers"
if (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0"
line.long 0x00 "DBGBVR0,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x0)++0x0 "Breakpoint 0"
hide.long 0x00 "DBGBVR0,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0"
line.long 0x00 "DBGBVR0,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x0)++0x0
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1"
line.long 0x00 "DBGBVR1,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x10)++0x0 "Breakpoint 1"
hide.long 0x00 "DBGBVR1,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1"
line.long 0x00 "DBGBVR1,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x10)++0x0
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2"
line.long 0x00 "DBGBVR2,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x20)++0x0 "Breakpoint 2"
hide.long 0x00 "DBGBVR2,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2"
line.long 0x00 "DBGBVR2,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x20)++0x0
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3"
line.long 0x00 "DBGBVR3,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x30)++0x0 "Breakpoint 3"
hide.long 0x00 "DBGBVR3,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3"
line.long 0x00 "DBGBVR3,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x30)++0x0
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4"
line.long 0x00 "DBGBVR4,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x40)++0x0 "Breakpoint 4"
hide.long 0x00 "DBGBVR4,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4"
line.long 0x00 "DBGBVR4,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x40)++0x0
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5"
line.long 0x00 "DBGBVR5,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x50)++0x0 "Breakpoint 5"
hide.long 0x00 "DBGBVR5,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5"
line.long 0x00 "DBGBVR5,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x50)++0x0
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
group.long c14:0x0141++0x0
line.long 0x00 "DBGBXVR4,Debug Breakpoint Extended Value Register 4"
hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value"
group.long c14:0x0151++0x0
line.long 0x00 "DBGBXVR5,Debug Breakpoint Extended Value Register 5"
hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value"
tree.end
tree "Watchpoint Control Registers"
group.long c14:(0x0600+0x0)++0x00 "Breakpoint 0"
line.long 0x00 "DBGWVR0,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x0)++0x00
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
group.long c14:(0x0600+0x10)++0x00 "Breakpoint 1"
line.long 0x00 "DBGWVR1,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x10)++0x00
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
group.long c14:(0x0600+0x20)++0x00 "Breakpoint 2"
line.long 0x00 "DBGWVR2,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x20)++0x00
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
group.long c14:(0x0600+0x30)++0x00 "Breakpoint 3"
line.long 0x00 "DBGWVR3,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x30)++0x00
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
tree.end
tree.end
AUTOINDENT.OFF
AUTOINDENT.POP
tree.open "Interrupt Controller (GIC-400)"
width 17.
width 17.
base ad:0xFFFC1000
tree "Distributor Interface"
if (((per.l(ad:0xFFFC1000+0x04))&0x400)==0x400)
if PER.ADDRESS.isSECUREEX(ad:0xFFFC1000)
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)"
bitfld.long 0x00 1. " ENABLEGRP1    ,Global Interrupt Enable Group 1" "Disabled,Enabled"
bitfld.long 0x00 0. "         ENABLEGRP0    ,Global Interrupt Enable Group 1" "Disabled,Enabled"
else
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)"
bitfld.long 0x00 0. " ENABLE        ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled"
endif
else
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register"
bitfld.long 0x00 0. " ENABLE        ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x400)==0x400)
rgroup.long 0x0004++0x03
line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register"
bitfld.long 0x00 11.--15. " LSPI          ,Locable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10. "               SECURITYEXTN  ,Indicate whether interrupt controller implements the security extensions" "Not implemented,Implemented"
textline "                          "
bitfld.long 0x00 5.--7. " CPUNUMBER     ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..."
bitfld.long 0x00 0.--4. "                ITLN          ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020"
else
rgroup.long 0x0004++0x03
line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register"
bitfld.long 0x00 10. " SECURITYEXTN  ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented"
textline "                          "
bitfld.long 0x00 5.--7. " CPUNUMBER     ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..."
bitfld.long 0x00 0.--4. "                ITLN          ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020"
endif
rgroup.long 0x0008++0x03
line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register"
bitfld.long 0x00 24.--31. " PRODID        ,Indicates the product ID" "PL390,PL390,GIC400,GIC400,?..."
bitfld.long 0x00 16.--19. "           VAR           ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                          "
bitfld.long 0x00 12.--15. " REV           ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "               IMP           ,Implementer"
sif CPU.FEATURE(hypervisor)||CPU.FEATURE(secure)
width 17.
tree "Group/Security Registers"
if PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x0080)
group.long 0x0080++0x03
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)"
bitfld.long 0x00 31. " GSB31   ,Group Status Bit 31" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB30   ,Group Status Bit 30" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB29   ,Group Status Bit 29" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB28   ,Group Status Bit 28" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB27   ,Group Status Bit 27" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB26   ,Group Status Bit 26" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB25   ,Group Status Bit 25" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB24   ,Group Status Bit 24" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB23   ,Group Status Bit 23" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB22   ,Group Status Bit 22" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB21   ,Group Status Bit 21" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB20   ,Group Status Bit 20" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB19   ,Group Status Bit 19" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB18   ,Group Status Bit 18" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB17   ,Group Status Bit 17" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB16   ,Group Status Bit 16" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB15   ,Group Status Bit 15" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB14   ,Group Status Bit 14" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB13   ,Group Status Bit 13" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB12   ,Group Status Bit 12" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB11   ,Group Status Bit 11" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB10   ,Group Status Bit 10" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB9    ,Group Status Bit 9" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB8    ,Group Status Bit 8" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB7    ,Group Status Bit 7" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB6    ,Group Status Bit 6" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB5    ,Group Status Bit 5" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB4    ,Group Status Bit 4" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB3    ,Group Status Bit 3" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB2    ,Group Status Bit 2" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB1    ,Group Status Bit 1" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB0    ,Group Status Bit 0" "Group 0 (Secure),Group 1 (Non-secure)"
else
group.long 0x0080++0x03
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)"
bitfld.long 0x00 31. " GSB31   ,Group Status Bit 31" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB30   ,Group Status Bit 30" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB29   ,Group Status Bit 29" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB28   ,Group Status Bit 28" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB27   ,Group Status Bit 27" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB26   ,Group Status Bit 26" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB25   ,Group Status Bit 25" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB24   ,Group Status Bit 24" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB23   ,Group Status Bit 23" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB22   ,Group Status Bit 22" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB21   ,Group Status Bit 21" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB20   ,Group Status Bit 20" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB19   ,Group Status Bit 19" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB18   ,Group Status Bit 18" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB17   ,Group Status Bit 17" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB16   ,Group Status Bit 16" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB15   ,Group Status Bit 15" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB14   ,Group Status Bit 14" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB13   ,Group Status Bit 13" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB12   ,Group Status Bit 12" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB11   ,Group Status Bit 11" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB10   ,Group Status Bit 10" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB9    ,Group Status Bit 9" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB8    ,Group Status Bit 8" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB7    ,Group Status Bit 7" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB6    ,Group Status Bit 6" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB5    ,Group Status Bit 5" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB4    ,Group Status Bit 4" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB3    ,Group Status Bit 3" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB2    ,Group Status Bit 2" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB1    ,Group Status Bit 1" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB0    ,Group Status Bit 0" "Group 0,Group 1"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x01)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x0084))
group.long 0x0084++0x03
line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Secure Access)"
bitfld.long 0x00 31. " GSB63   ,Group Status Bit 63" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB62   ,Group Status Bit 62" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB61   ,Group Status Bit 61" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB60   ,Group Status Bit 60" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB59   ,Group Status Bit 59" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB58   ,Group Status Bit 58" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB57   ,Group Status Bit 57" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB56   ,Group Status Bit 56" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB55   ,Group Status Bit 55" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB54   ,Group Status Bit 54" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB53   ,Group Status Bit 53" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB52   ,Group Status Bit 52" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB51   ,Group Status Bit 51" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB50   ,Group Status Bit 50" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB49   ,Group Status Bit 49" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB48   ,Group Status Bit 48" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB47   ,Group Status Bit 47" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB46   ,Group Status Bit 46" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB45   ,Group Status Bit 45" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB44   ,Group Status Bit 44" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB43   ,Group Status Bit 43" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB42   ,Group Status Bit 42" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB41   ,Group Status Bit 41" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB40   ,Group Status Bit 40" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB39   ,Group Status Bit 39" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB38   ,Group Status Bit 38" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB37   ,Group Status Bit 37" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB36   ,Group Status Bit 36" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB35   ,Group Status Bit 35" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB34   ,Group Status Bit 34" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB33   ,Group Status Bit 33" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB32   ,Group Status Bit 32" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x01)
group.long 0x0084++0x03
line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Non-secure access)"
bitfld.long 0x00 31. " GSB63   ,Group Status Bit 63" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB62   ,Group Status Bit 62" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB61   ,Group Status Bit 61" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB60   ,Group Status Bit 60" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB59   ,Group Status Bit 59" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB58   ,Group Status Bit 58" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB57   ,Group Status Bit 57" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB56   ,Group Status Bit 56" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB55   ,Group Status Bit 55" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB54   ,Group Status Bit 54" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB53   ,Group Status Bit 53" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB52   ,Group Status Bit 52" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB51   ,Group Status Bit 51" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB50   ,Group Status Bit 50" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB49   ,Group Status Bit 49" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB48   ,Group Status Bit 48" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB47   ,Group Status Bit 47" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB46   ,Group Status Bit 46" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB45   ,Group Status Bit 45" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB44   ,Group Status Bit 44" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB43   ,Group Status Bit 43" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB42   ,Group Status Bit 42" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB41   ,Group Status Bit 41" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB40   ,Group Status Bit 40" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB39   ,Group Status Bit 39" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB38   ,Group Status Bit 38" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB37   ,Group Status Bit 37" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB36   ,Group Status Bit 36" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB35   ,Group Status Bit 35" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB34   ,Group Status Bit 34" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB33   ,Group Status Bit 33" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB32   ,Group Status Bit 32" "Group 0,Group 1"
else
rgroup.long 0x0084++0x03
line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x02)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x0088))
group.long 0x0088++0x03
line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Secure access)"
bitfld.long 0x00 31. " GSB95   ,Group Status Bit 95" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB94   ,Group Status Bit 94" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB93   ,Group Status Bit 93" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB92   ,Group Status Bit 92" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB91   ,Group Status Bit 91" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB90   ,Group Status Bit 90" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB89   ,Group Status Bit 89" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB88   ,Group Status Bit 88" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB87   ,Group Status Bit 87" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB86   ,Group Status Bit 86" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB85   ,Group Status Bit 85" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB84   ,Group Status Bit 84" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB83   ,Group Status Bit 83" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB82   ,Group Status Bit 82" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB81   ,Group Status Bit 81" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB80   ,Group Status Bit 80" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB79   ,Group Status Bit 79" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB78   ,Group Status Bit 78" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB77   ,Group Status Bit 77" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB76   ,Group Status Bit 76" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB75   ,Group Status Bit 75" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB74   ,Group Status Bit 74" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB73   ,Group Status Bit 73" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB72   ,Group Status Bit 72" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB71   ,Group Status Bit 71" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB70   ,Group Status Bit 70" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB69   ,Group Status Bit 69" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB68   ,Group Status Bit 68" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB67   ,Group Status Bit 67" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB66   ,Group Status Bit 66" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB65   ,Group Status Bit 65" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB64   ,Group Status Bit 64" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x02)
group.long 0x0088++0x03
line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Non-secure access)"
bitfld.long 0x00 31. " GSB95   ,Group Status Bit 95" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB94   ,Group Status Bit 94" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB93   ,Group Status Bit 93" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB92   ,Group Status Bit 92" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB91   ,Group Status Bit 91" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB90   ,Group Status Bit 90" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB89   ,Group Status Bit 89" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB88   ,Group Status Bit 88" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB87   ,Group Status Bit 87" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB86   ,Group Status Bit 86" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB85   ,Group Status Bit 85" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB84   ,Group Status Bit 84" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB83   ,Group Status Bit 83" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB82   ,Group Status Bit 82" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB81   ,Group Status Bit 81" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB80   ,Group Status Bit 80" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB79   ,Group Status Bit 79" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB78   ,Group Status Bit 78" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB77   ,Group Status Bit 77" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB76   ,Group Status Bit 76" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB75   ,Group Status Bit 75" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB74   ,Group Status Bit 74" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB73   ,Group Status Bit 73" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB72   ,Group Status Bit 72" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB71   ,Group Status Bit 71" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB70   ,Group Status Bit 70" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB69   ,Group Status Bit 69" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB68   ,Group Status Bit 68" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB67   ,Group Status Bit 67" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB66   ,Group Status Bit 66" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB65   ,Group Status Bit 65" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB64   ,Group Status Bit 64" "Group 0,Group 1"
else
rgroup.long 0x0088++0x03
line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x03)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x008C))
group.long 0x008C++0x03
line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Secure access)"
bitfld.long 0x00 31. " GSB127  ,Group Status Bit 127" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB126  ,Group Status Bit 126" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB125  ,Group Status Bit 125" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB124  ,Group Status Bit 124" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB123  ,Group Status Bit 123" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB122  ,Group Status Bit 122" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB121  ,Group Status Bit 121" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB120  ,Group Status Bit 120" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB119  ,Group Status Bit 119" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB118  ,Group Status Bit 118" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB117  ,Group Status Bit 117" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB116  ,Group Status Bit 116" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB115  ,Group Status Bit 115" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB114  ,Group Status Bit 114" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB113  ,Group Status Bit 113" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB112  ,Group Status Bit 112" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB111  ,Group Status Bit 111" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB110  ,Group Status Bit 110" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB109  ,Group Status Bit 109" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB108  ,Group Status Bit 108" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB107  ,Group Status Bit 107" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB106  ,Group Status Bit 106" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB105  ,Group Status Bit 105" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB104  ,Group Status Bit 104" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB103  ,Group Status Bit 103" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB102  ,Group Status Bit 102" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB101  ,Group Status Bit 101" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB100  ,Group Status Bit 100" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB99   ,Group Status Bit 99" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB98   ,Group Status Bit 98" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB97   ,Group Status Bit 97" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB96   ,Group Status Bit 96" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x03)
group.long 0x008C++0x03
line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Non-secure access)"
bitfld.long 0x00 31. " GSB127  ,Group Status Bit 127" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB126  ,Group Status Bit 126" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB125  ,Group Status Bit 125" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB124  ,Group Status Bit 124" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB123  ,Group Status Bit 123" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB122  ,Group Status Bit 122" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB121  ,Group Status Bit 121" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB120  ,Group Status Bit 120" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB119  ,Group Status Bit 119" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB118  ,Group Status Bit 118" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB117  ,Group Status Bit 117" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB116  ,Group Status Bit 116" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB115  ,Group Status Bit 115" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB114  ,Group Status Bit 114" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB113  ,Group Status Bit 113" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB112  ,Group Status Bit 112" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB111  ,Group Status Bit 111" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB110  ,Group Status Bit 110" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB109  ,Group Status Bit 109" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB108  ,Group Status Bit 108" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB107  ,Group Status Bit 107" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB106  ,Group Status Bit 106" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB105  ,Group Status Bit 105" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB104  ,Group Status Bit 104" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB103  ,Group Status Bit 103" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB102  ,Group Status Bit 102" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB101  ,Group Status Bit 101" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB100  ,Group Status Bit 100" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB99   ,Group Status Bit 99" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB98   ,Group Status Bit 98" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB97   ,Group Status Bit 97" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB96   ,Group Status Bit 96" "Group 0,Group 1"
else
rgroup.long 0x008C++0x03
line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x04)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x0090))
group.long 0x0090++0x03
line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Secure access)"
bitfld.long 0x00 31. " GSB159  ,Group Status Bit 159" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB158  ,Group Status Bit 158" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB157  ,Group Status Bit 157" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB156  ,Group Status Bit 156" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB155  ,Group Status Bit 155" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB154  ,Group Status Bit 154" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB153  ,Group Status Bit 153" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB152  ,Group Status Bit 152" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB151  ,Group Status Bit 151" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB150  ,Group Status Bit 150" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB149  ,Group Status Bit 149" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB148  ,Group Status Bit 148" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB147  ,Group Status Bit 147" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB146  ,Group Status Bit 146" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB145  ,Group Status Bit 145" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB144  ,Group Status Bit 144" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB143  ,Group Status Bit 143" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB142  ,Group Status Bit 142" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB141  ,Group Status Bit 141" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB140  ,Group Status Bit 140" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB139  ,Group Status Bit 139" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB138  ,Group Status Bit 138" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB137  ,Group Status Bit 137" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB136  ,Group Status Bit 136" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB135  ,Group Status Bit 135" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB134  ,Group Status Bit 134" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB133  ,Group Status Bit 133" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB132  ,Group Status Bit 132" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB131  ,Group Status Bit 131" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB130  ,Group Status Bit 130" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB129  ,Group Status Bit 129" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB128  ,Group Status Bit 128" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x04)
group.long 0x0090++0x03
line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Non-secure access)"
bitfld.long 0x00 31. " GSB159  ,Group Status Bit 159" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB158  ,Group Status Bit 158" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB157  ,Group Status Bit 157" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB156  ,Group Status Bit 156" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB155  ,Group Status Bit 155" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB154  ,Group Status Bit 154" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB153  ,Group Status Bit 153" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB152  ,Group Status Bit 152" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB151  ,Group Status Bit 151" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB150  ,Group Status Bit 150" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB149  ,Group Status Bit 149" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB148  ,Group Status Bit 148" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB147  ,Group Status Bit 147" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB146  ,Group Status Bit 146" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB145  ,Group Status Bit 145" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB144  ,Group Status Bit 144" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB143  ,Group Status Bit 143" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB142  ,Group Status Bit 142" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB141  ,Group Status Bit 141" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB140  ,Group Status Bit 140" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB139  ,Group Status Bit 139" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB138  ,Group Status Bit 138" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB137  ,Group Status Bit 137" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB136  ,Group Status Bit 136" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB135  ,Group Status Bit 135" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB134  ,Group Status Bit 134" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB133  ,Group Status Bit 133" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB132  ,Group Status Bit 132" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB131  ,Group Status Bit 131" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB130  ,Group Status Bit 130" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB129  ,Group Status Bit 129" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB128  ,Group Status Bit 128" "Group 0,Group 1"
else
rgroup.long 0x0090++0x03
line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x05)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x0094))
group.long 0x0094++0x03
line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Secure access)"
bitfld.long 0x00 31. " GSB191  ,Group Status Bit 191" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB190  ,Group Status Bit 190" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB189  ,Group Status Bit 189" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB188  ,Group Status Bit 188" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB187  ,Group Status Bit 187" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB186  ,Group Status Bit 186" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB185  ,Group Status Bit 185" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB184  ,Group Status Bit 184" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB183  ,Group Status Bit 183" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB182  ,Group Status Bit 182" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB181  ,Group Status Bit 181" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB180  ,Group Status Bit 180" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB179  ,Group Status Bit 179" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB178  ,Group Status Bit 178" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB177  ,Group Status Bit 177" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB176  ,Group Status Bit 176" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB175  ,Group Status Bit 175" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB174  ,Group Status Bit 174" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB173  ,Group Status Bit 173" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB172  ,Group Status Bit 172" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB171  ,Group Status Bit 171" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB170  ,Group Status Bit 170" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB169  ,Group Status Bit 169" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB168  ,Group Status Bit 168" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB167  ,Group Status Bit 167" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB166  ,Group Status Bit 166" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB165  ,Group Status Bit 165" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB164  ,Group Status Bit 164" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB163  ,Group Status Bit 163" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB162  ,Group Status Bit 162" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB161  ,Group Status Bit 161" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB160  ,Group Status Bit 160" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x05)
group.long 0x0094++0x03
line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Non-secure access)"
bitfld.long 0x00 31. " GSB191  ,Group Status Bit 191" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB190  ,Group Status Bit 190" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB189  ,Group Status Bit 189" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB188  ,Group Status Bit 188" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB187  ,Group Status Bit 187" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB186  ,Group Status Bit 186" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB185  ,Group Status Bit 185" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB184  ,Group Status Bit 184" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB183  ,Group Status Bit 183" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB182  ,Group Status Bit 182" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB181  ,Group Status Bit 181" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB180  ,Group Status Bit 180" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB179  ,Group Status Bit 179" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB178  ,Group Status Bit 178" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB177  ,Group Status Bit 177" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB176  ,Group Status Bit 176" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB175  ,Group Status Bit 175" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB174  ,Group Status Bit 174" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB173  ,Group Status Bit 173" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB172  ,Group Status Bit 172" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB171  ,Group Status Bit 171" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB170  ,Group Status Bit 170" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB169  ,Group Status Bit 169" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB168  ,Group Status Bit 168" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB167  ,Group Status Bit 167" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB166  ,Group Status Bit 166" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB165  ,Group Status Bit 165" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB164  ,Group Status Bit 164" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB163  ,Group Status Bit 163" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB162  ,Group Status Bit 162" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB161  ,Group Status Bit 161" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB160  ,Group Status Bit 160" "Group 0,Group 1"
else
rgroup.long 0x0094++0x03
line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x06)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x0098))
group.long 0x0098++0x03
line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Secure access)"
bitfld.long 0x00 31. " GSB223  ,Group Status Bit 223" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB222  ,Group Status Bit 222" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB221  ,Group Status Bit 221" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB220  ,Group Status Bit 220" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB219  ,Group Status Bit 219" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB218  ,Group Status Bit 218" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB217  ,Group Status Bit 217" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB216  ,Group Status Bit 216" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB215  ,Group Status Bit 215" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB214  ,Group Status Bit 214" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB213  ,Group Status Bit 213" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB212  ,Group Status Bit 212" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB211  ,Group Status Bit 211" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB210  ,Group Status Bit 210" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB209  ,Group Status Bit 209" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB208  ,Group Status Bit 208" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB207  ,Group Status Bit 207" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB206  ,Group Status Bit 206" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB205  ,Group Status Bit 205" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB204  ,Group Status Bit 204" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB203  ,Group Status Bit 203" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB202  ,Group Status Bit 202" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB201  ,Group Status Bit 201" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB200  ,Group Status Bit 200" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB199  ,Group Status Bit 199" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB198  ,Group Status Bit 198" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB197  ,Group Status Bit 197" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB196  ,Group Status Bit 196" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB195  ,Group Status Bit 195" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB194  ,Group Status Bit 194" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB193  ,Group Status Bit 193" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB192  ,Group Status Bit 192" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x06)
group.long 0x0098++0x03
line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Non-secure access)"
bitfld.long 0x00 31. " GSB223  ,Group Status Bit 223" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB222  ,Group Status Bit 222" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB221  ,Group Status Bit 221" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB220  ,Group Status Bit 220" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB219  ,Group Status Bit 219" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB218  ,Group Status Bit 218" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB217  ,Group Status Bit 217" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB216  ,Group Status Bit 216" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB215  ,Group Status Bit 215" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB214  ,Group Status Bit 214" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB213  ,Group Status Bit 213" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB212  ,Group Status Bit 212" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB211  ,Group Status Bit 211" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB210  ,Group Status Bit 210" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB209  ,Group Status Bit 209" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB208  ,Group Status Bit 208" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB207  ,Group Status Bit 207" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB206  ,Group Status Bit 206" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB205  ,Group Status Bit 205" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB204  ,Group Status Bit 204" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB203  ,Group Status Bit 203" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB202  ,Group Status Bit 202" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB201  ,Group Status Bit 201" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB200  ,Group Status Bit 200" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB199  ,Group Status Bit 199" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB198  ,Group Status Bit 198" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB197  ,Group Status Bit 197" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB196  ,Group Status Bit 196" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB195  ,Group Status Bit 195" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB194  ,Group Status Bit 194" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB193  ,Group Status Bit 193" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB192  ,Group Status Bit 192" "Group 0,Group 1"
else
rgroup.long 0x0098++0x03
line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x07)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x009C))
group.long 0x009C++0x03
line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Secure access)"
bitfld.long 0x00 31. " GSB255  ,Group Status Bit 255" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB254  ,Group Status Bit 254" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB253  ,Group Status Bit 253" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB252  ,Group Status Bit 252" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB251  ,Group Status Bit 251" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB250  ,Group Status Bit 250" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB249  ,Group Status Bit 249" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB248  ,Group Status Bit 248" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB247  ,Group Status Bit 247" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB246  ,Group Status Bit 246" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB245  ,Group Status Bit 245" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB244  ,Group Status Bit 244" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB243  ,Group Status Bit 243" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB242  ,Group Status Bit 242" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB241  ,Group Status Bit 241" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB240  ,Group Status Bit 240" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB239  ,Group Status Bit 239" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB238  ,Group Status Bit 238" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB237  ,Group Status Bit 237" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB236  ,Group Status Bit 236" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB235  ,Group Status Bit 235" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB234  ,Group Status Bit 234" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB233  ,Group Status Bit 233" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB232  ,Group Status Bit 232" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB231  ,Group Status Bit 231" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB230  ,Group Status Bit 230" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB229  ,Group Status Bit 229" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB228  ,Group Status Bit 228" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB227  ,Group Status Bit 227" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB226  ,Group Status Bit 226" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB225  ,Group Status Bit 225" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB224  ,Group Status Bit 224" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x07)
group.long 0x009C++0x03
line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Non-secure access)"
bitfld.long 0x00 31. " GSB255  ,Group Status Bit 255" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB254  ,Group Status Bit 254" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB253  ,Group Status Bit 253" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB252  ,Group Status Bit 252" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB251  ,Group Status Bit 251" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB250  ,Group Status Bit 250" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB249  ,Group Status Bit 249" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB248  ,Group Status Bit 248" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB247  ,Group Status Bit 247" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB246  ,Group Status Bit 246" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB245  ,Group Status Bit 245" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB244  ,Group Status Bit 244" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB243  ,Group Status Bit 243" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB242  ,Group Status Bit 242" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB241  ,Group Status Bit 241" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB240  ,Group Status Bit 240" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB239  ,Group Status Bit 239" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB238  ,Group Status Bit 238" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB237  ,Group Status Bit 237" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB236  ,Group Status Bit 236" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB235  ,Group Status Bit 235" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB234  ,Group Status Bit 234" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB233  ,Group Status Bit 233" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB232  ,Group Status Bit 232" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB231  ,Group Status Bit 231" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB230  ,Group Status Bit 230" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB229  ,Group Status Bit 229" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB228  ,Group Status Bit 228" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB227  ,Group Status Bit 227" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB226  ,Group Status Bit 226" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB225  ,Group Status Bit 225" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB224  ,Group Status Bit 224" "Group 0,Group 1"
else
rgroup.long 0x009C++0x03
line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x08)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00A0))
group.long 0x00A0++0x03
line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Secure access)"
bitfld.long 0x00 31. " GSB287  ,Group Status Bit 287" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB286  ,Group Status Bit 286" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB285  ,Group Status Bit 285" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB284  ,Group Status Bit 284" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB283  ,Group Status Bit 283" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB282  ,Group Status Bit 282" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB281  ,Group Status Bit 281" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB280  ,Group Status Bit 280" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB279  ,Group Status Bit 279" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB278  ,Group Status Bit 278" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB277  ,Group Status Bit 277" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB276  ,Group Status Bit 276" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB275  ,Group Status Bit 275" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB274  ,Group Status Bit 274" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB273  ,Group Status Bit 273" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB272  ,Group Status Bit 272" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB271  ,Group Status Bit 271" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB270  ,Group Status Bit 270" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB269  ,Group Status Bit 269" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB268  ,Group Status Bit 268" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB267  ,Group Status Bit 267" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB266  ,Group Status Bit 266" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB265  ,Group Status Bit 265" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB264  ,Group Status Bit 264" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB263  ,Group Status Bit 263" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB262  ,Group Status Bit 262" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB261  ,Group Status Bit 261" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB260  ,Group Status Bit 260" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB259  ,Group Status Bit 259" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB258  ,Group Status Bit 258" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB257  ,Group Status Bit 257" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB256  ,Group Status Bit 256" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x08)
group.long 0x00A0++0x03
line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Non-secure access)"
bitfld.long 0x00 31. " GSB287  ,Group Status Bit 287" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB286  ,Group Status Bit 286" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB285  ,Group Status Bit 285" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB284  ,Group Status Bit 284" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB283  ,Group Status Bit 283" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB282  ,Group Status Bit 282" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB281  ,Group Status Bit 281" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB280  ,Group Status Bit 280" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB279  ,Group Status Bit 279" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB278  ,Group Status Bit 278" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB277  ,Group Status Bit 277" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB276  ,Group Status Bit 276" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB275  ,Group Status Bit 275" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB274  ,Group Status Bit 274" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB273  ,Group Status Bit 273" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB272  ,Group Status Bit 272" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB271  ,Group Status Bit 271" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB270  ,Group Status Bit 270" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB269  ,Group Status Bit 269" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB268  ,Group Status Bit 268" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB267  ,Group Status Bit 267" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB266  ,Group Status Bit 266" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB265  ,Group Status Bit 265" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB264  ,Group Status Bit 264" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB263  ,Group Status Bit 263" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB262  ,Group Status Bit 262" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB261  ,Group Status Bit 261" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB260  ,Group Status Bit 260" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB259  ,Group Status Bit 259" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB258  ,Group Status Bit 258" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB257  ,Group Status Bit 257" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB256  ,Group Status Bit 256" "Group 0,Group 1"
else
rgroup.long 0x00A0++0x03
line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x09)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00A4))
group.long 0x00A4++0x03
line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Secure access)"
bitfld.long 0x00 31. " GSB319  ,Group Status Bit 319" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB318  ,Group Status Bit 318" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB317  ,Group Status Bit 317" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB316  ,Group Status Bit 316" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB315  ,Group Status Bit 315" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB314  ,Group Status Bit 314" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB313  ,Group Status Bit 313" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB312  ,Group Status Bit 312" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB311  ,Group Status Bit 311" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB310  ,Group Status Bit 310" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB309  ,Group Status Bit 309" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB308  ,Group Status Bit 308" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB307  ,Group Status Bit 307" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB306  ,Group Status Bit 306" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB305  ,Group Status Bit 305" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB304  ,Group Status Bit 304" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB303  ,Group Status Bit 303" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB302  ,Group Status Bit 302" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB301  ,Group Status Bit 301" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB300  ,Group Status Bit 300" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB299  ,Group Status Bit 299" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB298  ,Group Status Bit 298" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB297  ,Group Status Bit 297" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB296  ,Group Status Bit 296" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB295  ,Group Status Bit 295" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB294  ,Group Status Bit 294" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB293  ,Group Status Bit 293" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB292  ,Group Status Bit 292" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB291  ,Group Status Bit 291" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB290  ,Group Status Bit 290" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB289  ,Group Status Bit 289" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB288  ,Group Status Bit 288" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x09)
group.long 0x00A4++0x03
line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Non-secure access)"
bitfld.long 0x00 31. " GSB319  ,Group Status Bit 319" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB318  ,Group Status Bit 318" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB317  ,Group Status Bit 317" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB316  ,Group Status Bit 316" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB315  ,Group Status Bit 315" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB314  ,Group Status Bit 314" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB313  ,Group Status Bit 313" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB312  ,Group Status Bit 312" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB311  ,Group Status Bit 311" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB310  ,Group Status Bit 310" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB309  ,Group Status Bit 309" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB308  ,Group Status Bit 308" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB307  ,Group Status Bit 307" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB306  ,Group Status Bit 306" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB305  ,Group Status Bit 305" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB304  ,Group Status Bit 304" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB303  ,Group Status Bit 303" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB302  ,Group Status Bit 302" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB301  ,Group Status Bit 301" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB300  ,Group Status Bit 300" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB299  ,Group Status Bit 299" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB298  ,Group Status Bit 298" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB297  ,Group Status Bit 297" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB296  ,Group Status Bit 296" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB295  ,Group Status Bit 295" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB294  ,Group Status Bit 294" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB293  ,Group Status Bit 293" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB292  ,Group Status Bit 292" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB291  ,Group Status Bit 291" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB290  ,Group Status Bit 290" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB289  ,Group Status Bit 289" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB288  ,Group Status Bit 288" "Group 0,Group 1"
else
rgroup.long 0x00A4++0x03
line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0A)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00A8))
group.long 0x00A8++0x03
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure access)"
bitfld.long 0x00 31. " GSB351  ,Group Status Bit 351" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB350  ,Group Status Bit 350" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB349  ,Group Status Bit 349" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB348  ,Group Status Bit 348" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB347  ,Group Status Bit 347" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB346  ,Group Status Bit 346" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB345  ,Group Status Bit 345" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB344  ,Group Status Bit 344" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB343  ,Group Status Bit 343" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB342  ,Group Status Bit 342" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB341  ,Group Status Bit 341" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB340  ,Group Status Bit 340" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB339  ,Group Status Bit 339" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB338  ,Group Status Bit 338" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB337  ,Group Status Bit 337" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB336  ,Group Status Bit 336" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB335  ,Group Status Bit 335" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB334  ,Group Status Bit 334" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB333  ,Group Status Bit 333" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB332  ,Group Status Bit 332" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB331  ,Group Status Bit 331" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB330  ,Group Status Bit 330" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB329  ,Group Status Bit 329" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB328  ,Group Status Bit 328" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB327  ,Group Status Bit 327" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB326  ,Group Status Bit 326" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB325  ,Group Status Bit 325" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB324  ,Group Status Bit 324" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB323  ,Group Status Bit 323" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB322  ,Group Status Bit 322" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB321  ,Group Status Bit 321" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB320  ,Group Status Bit 320" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0A)
group.long 0x00A8++0x03
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Non-secure access)"
bitfld.long 0x00 31. " GSB351  ,Group Status Bit 351" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB350  ,Group Status Bit 350" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB349  ,Group Status Bit 349" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB348  ,Group Status Bit 348" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB347  ,Group Status Bit 347" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB346  ,Group Status Bit 346" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB345  ,Group Status Bit 345" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB344  ,Group Status Bit 344" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB343  ,Group Status Bit 343" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB342  ,Group Status Bit 342" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB341  ,Group Status Bit 341" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB340  ,Group Status Bit 340" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB339  ,Group Status Bit 339" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB338  ,Group Status Bit 338" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB337  ,Group Status Bit 337" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB336  ,Group Status Bit 336" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB335  ,Group Status Bit 335" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB334  ,Group Status Bit 334" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB333  ,Group Status Bit 333" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB332  ,Group Status Bit 332" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB331  ,Group Status Bit 331" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB330  ,Group Status Bit 330" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB329  ,Group Status Bit 329" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB328  ,Group Status Bit 328" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB327  ,Group Status Bit 327" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB326  ,Group Status Bit 326" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB325  ,Group Status Bit 325" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB324  ,Group Status Bit 324" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB323  ,Group Status Bit 323" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB322  ,Group Status Bit 322" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB321  ,Group Status Bit 321" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB320  ,Group Status Bit 320" "Group 0,Group 1"
else
rgroup.long 0x00A8++0x03
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0B)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00AC))
group.long 0x00AC++0x03
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure access)"
bitfld.long 0x00 31. " GSB383  ,Group Status Bit 383" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB382  ,Group Status Bit 382" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB381  ,Group Status Bit 381" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB380  ,Group Status Bit 380" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB379  ,Group Status Bit 379" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB378  ,Group Status Bit 378" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB377  ,Group Status Bit 377" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB376  ,Group Status Bit 376" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB375  ,Group Status Bit 375" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB374  ,Group Status Bit 374" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB373  ,Group Status Bit 373" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB372  ,Group Status Bit 372" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB371  ,Group Status Bit 371" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB370  ,Group Status Bit 370" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB369  ,Group Status Bit 369" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB368  ,Group Status Bit 368" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB367  ,Group Status Bit 367" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB366  ,Group Status Bit 366" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB365  ,Group Status Bit 365" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB364  ,Group Status Bit 364" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB363  ,Group Status Bit 363" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB362  ,Group Status Bit 362" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB361  ,Group Status Bit 361" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB360  ,Group Status Bit 360" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB359  ,Group Status Bit 359" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB358  ,Group Status Bit 358" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB357  ,Group Status Bit 357" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB356  ,Group Status Bit 356" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB355  ,Group Status Bit 355" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB354  ,Group Status Bit 354" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB353  ,Group Status Bit 353" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB352  ,Group Status Bit 352" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0B)
group.long 0x00AC++0x03
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Non-secure access)"
bitfld.long 0x00 31. " GSB383  ,Group Status Bit 383" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB382  ,Group Status Bit 382" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB381  ,Group Status Bit 381" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB380  ,Group Status Bit 380" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB379  ,Group Status Bit 379" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB378  ,Group Status Bit 378" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB377  ,Group Status Bit 377" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB376  ,Group Status Bit 376" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB375  ,Group Status Bit 375" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB374  ,Group Status Bit 374" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB373  ,Group Status Bit 373" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB372  ,Group Status Bit 372" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB371  ,Group Status Bit 371" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB370  ,Group Status Bit 370" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB369  ,Group Status Bit 369" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB368  ,Group Status Bit 368" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB367  ,Group Status Bit 367" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB366  ,Group Status Bit 366" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB365  ,Group Status Bit 365" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB364  ,Group Status Bit 364" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB363  ,Group Status Bit 363" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB362  ,Group Status Bit 362" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB361  ,Group Status Bit 361" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB360  ,Group Status Bit 360" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB359  ,Group Status Bit 359" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB358  ,Group Status Bit 358" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB357  ,Group Status Bit 357" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB356  ,Group Status Bit 356" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB355  ,Group Status Bit 355" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB354  ,Group Status Bit 354" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB353  ,Group Status Bit 353" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB352  ,Group Status Bit 352" "Group 0,Group 1"
else
rgroup.long 0x00AC++0x03
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0C)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00B0))
group.long 0x00B0++0x03
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure access)"
bitfld.long 0x00 31. " GSB415  ,Group Status Bit 415" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB414  ,Group Status Bit 414" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB413  ,Group Status Bit 413" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB412  ,Group Status Bit 412" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB411  ,Group Status Bit 411" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB410  ,Group Status Bit 410" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB409  ,Group Status Bit 409" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB408  ,Group Status Bit 408" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB407  ,Group Status Bit 407" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB406  ,Group Status Bit 406" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB405  ,Group Status Bit 405" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB404  ,Group Status Bit 404" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB403  ,Group Status Bit 403" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB402  ,Group Status Bit 402" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB401  ,Group Status Bit 401" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB400  ,Group Status Bit 400" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB399  ,Group Status Bit 399" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB398  ,Group Status Bit 398" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB397  ,Group Status Bit 397" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB396  ,Group Status Bit 396" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB395  ,Group Status Bit 395" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB394  ,Group Status Bit 394" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB393  ,Group Status Bit 393" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB392  ,Group Status Bit 392" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB391  ,Group Status Bit 391" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB390  ,Group Status Bit 390" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB389  ,Group Status Bit 389" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB388  ,Group Status Bit 388" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB387  ,Group Status Bit 387" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB386  ,Group Status Bit 386" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB385  ,Group Status Bit 385" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB384  ,Group Status Bit 384" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0C)
group.long 0x00B0++0x03
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Non-secure access)"
bitfld.long 0x00 31. " GSB415  ,Group Status Bit 415" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB414  ,Group Status Bit 414" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB413  ,Group Status Bit 413" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB412  ,Group Status Bit 412" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB411  ,Group Status Bit 411" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB410  ,Group Status Bit 410" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB409  ,Group Status Bit 409" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB408  ,Group Status Bit 408" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB407  ,Group Status Bit 407" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB406  ,Group Status Bit 406" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB405  ,Group Status Bit 405" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB404  ,Group Status Bit 404" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB403  ,Group Status Bit 403" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB402  ,Group Status Bit 402" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB401  ,Group Status Bit 401" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB400  ,Group Status Bit 400" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB399  ,Group Status Bit 399" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB398  ,Group Status Bit 398" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB397  ,Group Status Bit 397" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB396  ,Group Status Bit 396" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB395  ,Group Status Bit 395" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB394  ,Group Status Bit 394" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB393  ,Group Status Bit 393" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB392  ,Group Status Bit 392" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB391  ,Group Status Bit 391" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB390  ,Group Status Bit 390" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB389  ,Group Status Bit 389" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB388  ,Group Status Bit 388" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB387  ,Group Status Bit 387" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB386  ,Group Status Bit 386" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB385  ,Group Status Bit 385" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB384  ,Group Status Bit 384" "Group 0,Group 1"
else
rgroup.long 0x00B0++0x03
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0D)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00B4))
group.long 0x00B4++0x03
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure access)"
bitfld.long 0x00 31. " GSB447  ,Group Status Bit 447" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB446  ,Group Status Bit 446" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB445  ,Group Status Bit 445" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB444  ,Group Status Bit 444" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB443  ,Group Status Bit 443" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB442  ,Group Status Bit 442" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB441  ,Group Status Bit 441" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB440  ,Group Status Bit 440" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB439  ,Group Status Bit 439" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB438  ,Group Status Bit 438" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB437  ,Group Status Bit 437" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB436  ,Group Status Bit 436" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB435  ,Group Status Bit 435" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB434  ,Group Status Bit 434" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB433  ,Group Status Bit 433" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB432  ,Group Status Bit 432" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB431  ,Group Status Bit 431" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB430  ,Group Status Bit 430" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB429  ,Group Status Bit 429" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB428  ,Group Status Bit 428" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB427  ,Group Status Bit 427" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB426  ,Group Status Bit 426" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB425  ,Group Status Bit 425" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB424  ,Group Status Bit 424" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB423  ,Group Status Bit 423" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB422  ,Group Status Bit 422" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB421  ,Group Status Bit 421" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB420  ,Group Status Bit 420" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB419  ,Group Status Bit 419" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB418  ,Group Status Bit 418" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB417  ,Group Status Bit 417" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB416  ,Group Status Bit 416" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0D)
group.long 0x00B4++0x03
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Non-secure access)"
bitfld.long 0x00 31. " GSB447  ,Group Status Bit 447" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB446  ,Group Status Bit 446" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB445  ,Group Status Bit 445" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB444  ,Group Status Bit 444" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB443  ,Group Status Bit 443" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB442  ,Group Status Bit 442" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB441  ,Group Status Bit 441" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB440  ,Group Status Bit 440" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB439  ,Group Status Bit 439" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB438  ,Group Status Bit 438" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB437  ,Group Status Bit 437" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB436  ,Group Status Bit 436" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB435  ,Group Status Bit 435" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB434  ,Group Status Bit 434" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB433  ,Group Status Bit 433" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB432  ,Group Status Bit 432" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB431  ,Group Status Bit 431" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB430  ,Group Status Bit 430" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB429  ,Group Status Bit 429" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB428  ,Group Status Bit 428" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB427  ,Group Status Bit 427" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB426  ,Group Status Bit 426" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB425  ,Group Status Bit 425" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB424  ,Group Status Bit 424" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB423  ,Group Status Bit 423" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB422  ,Group Status Bit 422" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB421  ,Group Status Bit 421" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB420  ,Group Status Bit 420" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB419  ,Group Status Bit 419" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB418  ,Group Status Bit 418" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB417  ,Group Status Bit 417" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB416  ,Group Status Bit 416" "Group 0,Group 1"
else
rgroup.long 0x00B4++0x03
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0E)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00B8))
group.long 0x00B8++0x03
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure access)"
bitfld.long 0x00 31. " GSB479  ,Group Status Bit 479" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB478  ,Group Status Bit 478" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB477  ,Group Status Bit 477" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB476  ,Group Status Bit 476" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB475  ,Group Status Bit 475" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB474  ,Group Status Bit 474" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB473  ,Group Status Bit 473" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB472  ,Group Status Bit 472" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB471  ,Group Status Bit 471" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB470  ,Group Status Bit 470" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB469  ,Group Status Bit 469" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB468  ,Group Status Bit 468" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB467  ,Group Status Bit 467" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB466  ,Group Status Bit 466" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB465  ,Group Status Bit 465" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB464  ,Group Status Bit 464" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB463  ,Group Status Bit 463" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB462  ,Group Status Bit 462" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB461  ,Group Status Bit 461" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB460  ,Group Status Bit 460" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB459  ,Group Status Bit 459" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB458  ,Group Status Bit 458" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB457  ,Group Status Bit 457" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB456  ,Group Status Bit 456" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB455  ,Group Status Bit 455" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB454  ,Group Status Bit 454" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB453  ,Group Status Bit 453" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB452  ,Group Status Bit 452" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB451  ,Group Status Bit 451" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB450  ,Group Status Bit 450" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB449  ,Group Status Bit 449" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB448  ,Group Status Bit 448" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0E)
group.long 0x00B8++0x03
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Non-secure access)"
bitfld.long 0x00 31. " GSB479  ,Group Status Bit 479" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB478  ,Group Status Bit 478" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB477  ,Group Status Bit 477" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB476  ,Group Status Bit 476" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB475  ,Group Status Bit 475" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB474  ,Group Status Bit 474" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB473  ,Group Status Bit 473" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB472  ,Group Status Bit 472" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB471  ,Group Status Bit 471" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB470  ,Group Status Bit 470" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB469  ,Group Status Bit 469" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB468  ,Group Status Bit 468" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB467  ,Group Status Bit 467" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB466  ,Group Status Bit 466" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB465  ,Group Status Bit 465" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB464  ,Group Status Bit 464" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB463  ,Group Status Bit 463" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB462  ,Group Status Bit 462" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB461  ,Group Status Bit 461" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB460  ,Group Status Bit 460" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB459  ,Group Status Bit 459" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB458  ,Group Status Bit 458" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB457  ,Group Status Bit 457" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB456  ,Group Status Bit 456" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB455  ,Group Status Bit 455" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB454  ,Group Status Bit 454" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB453  ,Group Status Bit 453" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB452  ,Group Status Bit 452" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB451  ,Group Status Bit 451" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB450  ,Group Status Bit 450" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB449  ,Group Status Bit 449" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB448  ,Group Status Bit 448" "Group 0,Group 1"
else
rgroup.long 0x00B8++0x03
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0F)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00BC))
group.long 0x00BC++0x03
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure access)"
bitfld.long 0x00 31. " GSB511  ,Group Status Bit 511" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB510  ,Group Status Bit 510" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB509  ,Group Status Bit 509" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB508  ,Group Status Bit 508" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB507  ,Group Status Bit 507" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB506  ,Group Status Bit 506" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB505  ,Group Status Bit 505" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB504  ,Group Status Bit 504" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB503  ,Group Status Bit 503" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB502  ,Group Status Bit 502" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB501  ,Group Status Bit 501" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB500  ,Group Status Bit 500" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB499  ,Group Status Bit 499" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB498  ,Group Status Bit 498" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB497  ,Group Status Bit 497" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB496  ,Group Status Bit 496" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB495  ,Group Status Bit 495" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB494  ,Group Status Bit 494" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB493  ,Group Status Bit 493" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB492  ,Group Status Bit 492" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB491  ,Group Status Bit 491" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB490  ,Group Status Bit 490" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB489  ,Group Status Bit 489" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB488  ,Group Status Bit 488" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB487  ,Group Status Bit 487" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB486  ,Group Status Bit 486" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB485  ,Group Status Bit 485" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB484  ,Group Status Bit 484" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB483  ,Group Status Bit 483" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB482  ,Group Status Bit 482" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB481  ,Group Status Bit 481" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB480  ,Group Status Bit 480" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0F)
group.long 0x00BC++0x03
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Non-secure access)"
bitfld.long 0x00 31. " GSB511  ,Group Status Bit 511" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB510  ,Group Status Bit 510" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB509  ,Group Status Bit 509" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB508  ,Group Status Bit 508" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB507  ,Group Status Bit 507" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB506  ,Group Status Bit 506" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB505  ,Group Status Bit 505" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB504  ,Group Status Bit 504" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB503  ,Group Status Bit 503" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB502  ,Group Status Bit 502" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB501  ,Group Status Bit 501" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB500  ,Group Status Bit 500" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB499  ,Group Status Bit 499" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB498  ,Group Status Bit 498" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB497  ,Group Status Bit 497" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB496  ,Group Status Bit 496" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB495  ,Group Status Bit 495" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB494  ,Group Status Bit 494" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB493  ,Group Status Bit 493" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB492  ,Group Status Bit 492" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB491  ,Group Status Bit 491" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB490  ,Group Status Bit 490" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB489  ,Group Status Bit 489" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB488  ,Group Status Bit 488" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB487  ,Group Status Bit 487" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB486  ,Group Status Bit 486" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB485  ,Group Status Bit 485" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB484  ,Group Status Bit 484" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB483  ,Group Status Bit 483" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB482  ,Group Status Bit 482" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB481  ,Group Status Bit 481" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB480  ,Group Status Bit 480" "Group 0,Group 1"
else
rgroup.long 0x00BC++0x03
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x10)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00C0))
group.long 0x00C0++0x03
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure access)"
bitfld.long 0x00 31. " GSB543  ,Group Status Bit 543" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB542  ,Group Status Bit 542" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB541  ,Group Status Bit 541" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB540  ,Group Status Bit 540" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB539  ,Group Status Bit 539" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB538  ,Group Status Bit 538" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB537  ,Group Status Bit 537" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB536  ,Group Status Bit 536" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB535  ,Group Status Bit 535" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB534  ,Group Status Bit 534" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB533  ,Group Status Bit 533" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB532  ,Group Status Bit 532" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB531  ,Group Status Bit 531" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB530  ,Group Status Bit 530" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB529  ,Group Status Bit 529" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB528  ,Group Status Bit 528" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB527  ,Group Status Bit 527" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB526  ,Group Status Bit 526" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB525  ,Group Status Bit 525" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB524  ,Group Status Bit 524" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB523  ,Group Status Bit 523" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB522  ,Group Status Bit 522" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB521  ,Group Status Bit 521" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB520  ,Group Status Bit 520" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB519  ,Group Status Bit 519" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB518  ,Group Status Bit 518" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB517  ,Group Status Bit 517" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB516  ,Group Status Bit 516" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB515  ,Group Status Bit 515" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB514  ,Group Status Bit 514" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB513  ,Group Status Bit 513" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB512  ,Group Status Bit 512" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x10)
group.long 0x00C0++0x03
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Non-secure access)"
bitfld.long 0x00 31. " GSB543  ,Group Status Bit 543" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB542  ,Group Status Bit 542" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB541  ,Group Status Bit 541" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB540  ,Group Status Bit 540" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB539  ,Group Status Bit 539" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB538  ,Group Status Bit 538" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB537  ,Group Status Bit 537" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB536  ,Group Status Bit 536" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB535  ,Group Status Bit 535" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB534  ,Group Status Bit 534" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB533  ,Group Status Bit 533" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB532  ,Group Status Bit 532" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB531  ,Group Status Bit 531" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB530  ,Group Status Bit 530" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB529  ,Group Status Bit 529" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB528  ,Group Status Bit 528" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB527  ,Group Status Bit 527" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB526  ,Group Status Bit 526" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB525  ,Group Status Bit 525" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB524  ,Group Status Bit 524" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB523  ,Group Status Bit 523" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB522  ,Group Status Bit 522" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB521  ,Group Status Bit 521" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB520  ,Group Status Bit 520" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB519  ,Group Status Bit 519" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB518  ,Group Status Bit 518" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB517  ,Group Status Bit 517" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB516  ,Group Status Bit 516" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB515  ,Group Status Bit 515" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB514  ,Group Status Bit 514" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB513  ,Group Status Bit 513" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB512  ,Group Status Bit 512" "Group 0,Group 1"
else
rgroup.long 0x00C0++0x03
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x11)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00C4))
group.long 0x00C4++0x03
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure access)"
bitfld.long 0x00 31. " GSB575  ,Group Status Bit 575" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB574  ,Group Status Bit 574" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB573  ,Group Status Bit 573" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB572  ,Group Status Bit 572" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB571  ,Group Status Bit 571" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB570  ,Group Status Bit 570" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB569  ,Group Status Bit 569" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB568  ,Group Status Bit 568" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB567  ,Group Status Bit 567" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB566  ,Group Status Bit 566" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB565  ,Group Status Bit 565" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB564  ,Group Status Bit 564" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB563  ,Group Status Bit 563" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB562  ,Group Status Bit 562" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB561  ,Group Status Bit 561" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB560  ,Group Status Bit 560" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB559  ,Group Status Bit 559" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB558  ,Group Status Bit 558" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB557  ,Group Status Bit 557" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB556  ,Group Status Bit 556" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB555  ,Group Status Bit 555" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB554  ,Group Status Bit 554" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB553  ,Group Status Bit 553" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB552  ,Group Status Bit 552" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB551  ,Group Status Bit 551" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB550  ,Group Status Bit 550" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB549  ,Group Status Bit 549" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB548  ,Group Status Bit 548" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB547  ,Group Status Bit 547" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB546  ,Group Status Bit 546" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB545  ,Group Status Bit 545" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB544  ,Group Status Bit 544" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x11)
group.long 0x00C4++0x03
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Non-secure access)"
bitfld.long 0x00 31. " GSB575  ,Group Status Bit 575" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB574  ,Group Status Bit 574" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB573  ,Group Status Bit 573" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB572  ,Group Status Bit 572" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB571  ,Group Status Bit 571" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB570  ,Group Status Bit 570" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB569  ,Group Status Bit 569" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB568  ,Group Status Bit 568" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB567  ,Group Status Bit 567" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB566  ,Group Status Bit 566" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB565  ,Group Status Bit 565" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB564  ,Group Status Bit 564" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB563  ,Group Status Bit 563" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB562  ,Group Status Bit 562" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB561  ,Group Status Bit 561" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB560  ,Group Status Bit 560" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB559  ,Group Status Bit 559" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB558  ,Group Status Bit 558" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB557  ,Group Status Bit 557" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB556  ,Group Status Bit 556" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB555  ,Group Status Bit 555" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB554  ,Group Status Bit 554" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB553  ,Group Status Bit 553" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB552  ,Group Status Bit 552" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB551  ,Group Status Bit 551" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB550  ,Group Status Bit 550" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB549  ,Group Status Bit 549" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB548  ,Group Status Bit 548" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB547  ,Group Status Bit 547" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB546  ,Group Status Bit 546" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB545  ,Group Status Bit 545" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB544  ,Group Status Bit 544" "Group 0,Group 1"
else
rgroup.long 0x00C4++0x03
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x12)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00C8))
group.long 0x00C8++0x03
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure access)"
bitfld.long 0x00 31. " GSB607  ,Group Status Bit 607" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB606  ,Group Status Bit 606" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB605  ,Group Status Bit 605" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB604  ,Group Status Bit 604" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB603  ,Group Status Bit 603" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB602  ,Group Status Bit 602" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB601  ,Group Status Bit 601" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB600  ,Group Status Bit 600" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB599  ,Group Status Bit 599" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB598  ,Group Status Bit 598" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB597  ,Group Status Bit 597" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB596  ,Group Status Bit 596" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB595  ,Group Status Bit 595" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB594  ,Group Status Bit 594" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB593  ,Group Status Bit 593" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB592  ,Group Status Bit 592" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB591  ,Group Status Bit 591" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB590  ,Group Status Bit 590" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB589  ,Group Status Bit 589" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB588  ,Group Status Bit 588" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB587  ,Group Status Bit 587" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB586  ,Group Status Bit 586" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB585  ,Group Status Bit 585" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB584  ,Group Status Bit 584" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB583  ,Group Status Bit 583" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB582  ,Group Status Bit 582" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB581  ,Group Status Bit 581" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB580  ,Group Status Bit 580" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB579  ,Group Status Bit 579" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB578  ,Group Status Bit 578" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB577  ,Group Status Bit 577" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB576  ,Group Status Bit 576" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x12)
group.long 0x00C8++0x03
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Non-secure access)"
bitfld.long 0x00 31. " GSB607  ,Group Status Bit 607" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB606  ,Group Status Bit 606" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB605  ,Group Status Bit 605" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB604  ,Group Status Bit 604" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB603  ,Group Status Bit 603" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB602  ,Group Status Bit 602" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB601  ,Group Status Bit 601" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB600  ,Group Status Bit 600" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB599  ,Group Status Bit 599" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB598  ,Group Status Bit 598" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB597  ,Group Status Bit 597" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB596  ,Group Status Bit 596" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB595  ,Group Status Bit 595" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB594  ,Group Status Bit 594" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB593  ,Group Status Bit 593" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB592  ,Group Status Bit 592" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB591  ,Group Status Bit 591" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB590  ,Group Status Bit 590" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB589  ,Group Status Bit 589" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB588  ,Group Status Bit 588" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB587  ,Group Status Bit 587" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB586  ,Group Status Bit 586" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB585  ,Group Status Bit 585" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB584  ,Group Status Bit 584" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB583  ,Group Status Bit 583" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB582  ,Group Status Bit 582" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB581  ,Group Status Bit 581" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB580  ,Group Status Bit 580" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB579  ,Group Status Bit 579" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB578  ,Group Status Bit 578" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB577  ,Group Status Bit 577" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB576  ,Group Status Bit 576" "Group 0,Group 1"
else
rgroup.long 0x00C8++0x03
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x13)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00CC))
group.long 0x00CC++0x03
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure access)"
bitfld.long 0x00 31. " GSB639  ,Group Status Bit 639" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB638  ,Group Status Bit 638" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB637  ,Group Status Bit 637" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB636  ,Group Status Bit 636" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB635  ,Group Status Bit 635" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB634  ,Group Status Bit 634" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB633  ,Group Status Bit 633" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB632  ,Group Status Bit 632" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB631  ,Group Status Bit 631" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB630  ,Group Status Bit 630" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB629  ,Group Status Bit 629" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB628  ,Group Status Bit 628" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB627  ,Group Status Bit 627" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB626  ,Group Status Bit 626" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB625  ,Group Status Bit 625" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB624  ,Group Status Bit 624" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB623  ,Group Status Bit 623" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB622  ,Group Status Bit 622" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB621  ,Group Status Bit 621" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB620  ,Group Status Bit 620" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB619  ,Group Status Bit 619" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB618  ,Group Status Bit 618" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB617  ,Group Status Bit 617" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB616  ,Group Status Bit 616" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB615  ,Group Status Bit 615" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB614  ,Group Status Bit 614" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB613  ,Group Status Bit 613" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB612  ,Group Status Bit 612" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB611  ,Group Status Bit 611" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB610  ,Group Status Bit 610" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB609  ,Group Status Bit 609" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB608  ,Group Status Bit 608" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x13)
group.long 0x00CC++0x03
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Non-secure access)"
bitfld.long 0x00 31. " GSB639  ,Group Status Bit 639" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB638  ,Group Status Bit 638" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB637  ,Group Status Bit 637" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB636  ,Group Status Bit 636" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB635  ,Group Status Bit 635" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB634  ,Group Status Bit 634" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB633  ,Group Status Bit 633" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB632  ,Group Status Bit 632" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB631  ,Group Status Bit 631" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB630  ,Group Status Bit 630" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB629  ,Group Status Bit 629" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB628  ,Group Status Bit 628" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB627  ,Group Status Bit 627" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB626  ,Group Status Bit 626" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB625  ,Group Status Bit 625" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB624  ,Group Status Bit 624" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB623  ,Group Status Bit 623" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB622  ,Group Status Bit 622" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB621  ,Group Status Bit 621" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB620  ,Group Status Bit 620" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB619  ,Group Status Bit 619" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB618  ,Group Status Bit 618" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB617  ,Group Status Bit 617" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB616  ,Group Status Bit 616" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB615  ,Group Status Bit 615" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB614  ,Group Status Bit 614" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB613  ,Group Status Bit 613" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB612  ,Group Status Bit 612" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB611  ,Group Status Bit 611" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB610  ,Group Status Bit 610" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB609  ,Group Status Bit 609" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB608  ,Group Status Bit 608" "Group 0,Group 1"
else
rgroup.long 0x00CC++0x03
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x14)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00D0))
group.long 0x00D0++0x03
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure access)"
bitfld.long 0x00 31. " GSB671  ,Group Status Bit 671" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB670  ,Group Status Bit 670" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB669  ,Group Status Bit 669" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB668  ,Group Status Bit 668" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB667  ,Group Status Bit 667" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB666  ,Group Status Bit 666" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB665  ,Group Status Bit 665" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB664  ,Group Status Bit 664" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB663  ,Group Status Bit 663" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB662  ,Group Status Bit 662" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB661  ,Group Status Bit 661" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB660  ,Group Status Bit 660" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB659  ,Group Status Bit 659" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB658  ,Group Status Bit 658" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB657  ,Group Status Bit 657" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB656  ,Group Status Bit 656" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB655  ,Group Status Bit 655" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB654  ,Group Status Bit 654" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB653  ,Group Status Bit 653" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB652  ,Group Status Bit 652" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB651  ,Group Status Bit 651" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB650  ,Group Status Bit 650" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB649  ,Group Status Bit 649" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB648  ,Group Status Bit 648" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB647  ,Group Status Bit 647" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB646  ,Group Status Bit 646" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB645  ,Group Status Bit 645" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB644  ,Group Status Bit 644" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB643  ,Group Status Bit 643" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB642  ,Group Status Bit 642" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB641  ,Group Status Bit 641" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB640  ,Group Status Bit 640" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x14)
group.long 0x00D0++0x03
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Non-secure access)"
bitfld.long 0x00 31. " GSB671  ,Group Status Bit 671" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB670  ,Group Status Bit 670" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB669  ,Group Status Bit 669" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB668  ,Group Status Bit 668" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB667  ,Group Status Bit 667" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB666  ,Group Status Bit 666" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB665  ,Group Status Bit 665" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB664  ,Group Status Bit 664" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB663  ,Group Status Bit 663" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB662  ,Group Status Bit 662" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB661  ,Group Status Bit 661" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB660  ,Group Status Bit 660" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB659  ,Group Status Bit 659" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB658  ,Group Status Bit 658" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB657  ,Group Status Bit 657" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB656  ,Group Status Bit 656" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB655  ,Group Status Bit 655" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB654  ,Group Status Bit 654" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB653  ,Group Status Bit 653" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB652  ,Group Status Bit 652" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB651  ,Group Status Bit 651" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB650  ,Group Status Bit 650" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB649  ,Group Status Bit 649" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB648  ,Group Status Bit 648" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB647  ,Group Status Bit 647" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB646  ,Group Status Bit 646" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB645  ,Group Status Bit 645" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB644  ,Group Status Bit 644" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB643  ,Group Status Bit 643" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB642  ,Group Status Bit 642" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB641  ,Group Status Bit 641" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB640  ,Group Status Bit 640" "Group 0,Group 1"
else
rgroup.long 0x00D0++0x03
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x15)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00D4))
group.long 0x00D4++0x03
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure access)"
bitfld.long 0x00 31. " GSB703  ,Group Status Bit 703" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB702  ,Group Status Bit 702" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB701  ,Group Status Bit 701" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB700  ,Group Status Bit 700" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB699  ,Group Status Bit 699" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB698  ,Group Status Bit 698" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB697  ,Group Status Bit 697" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB696  ,Group Status Bit 696" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB695  ,Group Status Bit 695" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB694  ,Group Status Bit 694" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB693  ,Group Status Bit 693" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB692  ,Group Status Bit 692" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB691  ,Group Status Bit 691" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB690  ,Group Status Bit 690" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB689  ,Group Status Bit 689" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB688  ,Group Status Bit 688" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB687  ,Group Status Bit 687" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB686  ,Group Status Bit 686" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB685  ,Group Status Bit 685" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB684  ,Group Status Bit 684" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB683  ,Group Status Bit 683" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB682  ,Group Status Bit 682" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB681  ,Group Status Bit 681" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB680  ,Group Status Bit 680" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB679  ,Group Status Bit 679" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB678  ,Group Status Bit 678" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB677  ,Group Status Bit 677" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB676  ,Group Status Bit 676" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB675  ,Group Status Bit 675" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB674  ,Group Status Bit 674" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB673  ,Group Status Bit 673" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB672  ,Group Status Bit 672" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x15)
group.long 0x00D4++0x03
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Non-secure access)"
bitfld.long 0x00 31. " GSB703  ,Group Status Bit 703" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB702  ,Group Status Bit 702" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB701  ,Group Status Bit 701" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB700  ,Group Status Bit 700" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB699  ,Group Status Bit 699" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB698  ,Group Status Bit 698" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB697  ,Group Status Bit 697" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB696  ,Group Status Bit 696" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB695  ,Group Status Bit 695" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB694  ,Group Status Bit 694" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB693  ,Group Status Bit 693" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB692  ,Group Status Bit 692" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB691  ,Group Status Bit 691" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB690  ,Group Status Bit 690" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB689  ,Group Status Bit 689" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB688  ,Group Status Bit 688" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB687  ,Group Status Bit 687" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB686  ,Group Status Bit 686" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB685  ,Group Status Bit 685" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB684  ,Group Status Bit 684" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB683  ,Group Status Bit 683" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB682  ,Group Status Bit 682" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB681  ,Group Status Bit 681" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB680  ,Group Status Bit 680" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB679  ,Group Status Bit 679" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB678  ,Group Status Bit 678" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB677  ,Group Status Bit 677" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB676  ,Group Status Bit 676" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB675  ,Group Status Bit 675" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB674  ,Group Status Bit 674" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB673  ,Group Status Bit 673" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB672  ,Group Status Bit 672" "Group 0,Group 1"
else
rgroup.long 0x00D4++0x03
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x16)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00D8))
group.long 0x00D8++0x03
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure access)"
bitfld.long 0x00 31. " GSB735  ,Group Status Bit 735" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB734  ,Group Status Bit 734" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB733  ,Group Status Bit 733" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB732  ,Group Status Bit 732" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB731  ,Group Status Bit 731" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB730  ,Group Status Bit 730" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB729  ,Group Status Bit 729" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB728  ,Group Status Bit 728" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB727  ,Group Status Bit 727" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB726  ,Group Status Bit 726" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB725  ,Group Status Bit 725" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB724  ,Group Status Bit 724" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB723  ,Group Status Bit 723" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB722  ,Group Status Bit 722" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB721  ,Group Status Bit 721" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB720  ,Group Status Bit 720" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB719  ,Group Status Bit 719" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB718  ,Group Status Bit 718" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB717  ,Group Status Bit 717" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB716  ,Group Status Bit 716" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB715  ,Group Status Bit 715" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB714  ,Group Status Bit 714" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB713  ,Group Status Bit 713" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB712  ,Group Status Bit 712" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB711  ,Group Status Bit 711" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB710  ,Group Status Bit 710" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB709  ,Group Status Bit 709" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB708  ,Group Status Bit 708" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB707  ,Group Status Bit 707" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB706  ,Group Status Bit 706" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB705  ,Group Status Bit 705" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB704  ,Group Status Bit 704" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x16)
group.long 0x00D8++0x03
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Non-secure access)"
bitfld.long 0x00 31. " GSB735  ,Group Status Bit 735" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB734  ,Group Status Bit 734" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB733  ,Group Status Bit 733" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB732  ,Group Status Bit 732" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB731  ,Group Status Bit 731" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB730  ,Group Status Bit 730" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB729  ,Group Status Bit 729" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB728  ,Group Status Bit 728" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB727  ,Group Status Bit 727" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB726  ,Group Status Bit 726" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB725  ,Group Status Bit 725" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB724  ,Group Status Bit 724" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB723  ,Group Status Bit 723" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB722  ,Group Status Bit 722" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB721  ,Group Status Bit 721" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB720  ,Group Status Bit 720" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB719  ,Group Status Bit 719" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB718  ,Group Status Bit 718" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB717  ,Group Status Bit 717" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB716  ,Group Status Bit 716" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB715  ,Group Status Bit 715" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB714  ,Group Status Bit 714" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB713  ,Group Status Bit 713" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB712  ,Group Status Bit 712" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB711  ,Group Status Bit 711" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB710  ,Group Status Bit 710" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB709  ,Group Status Bit 709" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB708  ,Group Status Bit 708" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB707  ,Group Status Bit 707" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB706  ,Group Status Bit 706" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB705  ,Group Status Bit 705" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB704  ,Group Status Bit 704" "Group 0,Group 1"
else
rgroup.long 0x00D8++0x03
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x17)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00DC))
group.long 0x00DC++0x03
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure access)"
bitfld.long 0x00 31. " GSB767  ,Group Status Bit 767" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB766  ,Group Status Bit 766" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB765  ,Group Status Bit 765" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB764  ,Group Status Bit 764" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB763  ,Group Status Bit 763" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB762  ,Group Status Bit 762" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB761  ,Group Status Bit 761" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB760  ,Group Status Bit 760" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB759  ,Group Status Bit 759" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB758  ,Group Status Bit 758" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB757  ,Group Status Bit 757" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB756  ,Group Status Bit 756" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB755  ,Group Status Bit 755" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB754  ,Group Status Bit 754" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB753  ,Group Status Bit 753" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB752  ,Group Status Bit 752" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB751  ,Group Status Bit 751" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB750  ,Group Status Bit 750" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB749  ,Group Status Bit 749" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB748  ,Group Status Bit 748" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB747  ,Group Status Bit 747" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB746  ,Group Status Bit 746" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB745  ,Group Status Bit 745" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB744  ,Group Status Bit 744" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB743  ,Group Status Bit 743" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB742  ,Group Status Bit 742" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB741  ,Group Status Bit 741" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB740  ,Group Status Bit 740" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB739  ,Group Status Bit 739" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB738  ,Group Status Bit 738" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB737  ,Group Status Bit 737" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB736  ,Group Status Bit 736" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x17)
group.long 0x00DC++0x03
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Non-secure access)"
bitfld.long 0x00 31. " GSB767  ,Group Status Bit 767" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB766  ,Group Status Bit 766" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB765  ,Group Status Bit 765" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB764  ,Group Status Bit 764" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB763  ,Group Status Bit 763" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB762  ,Group Status Bit 762" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB761  ,Group Status Bit 761" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB760  ,Group Status Bit 760" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB759  ,Group Status Bit 759" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB758  ,Group Status Bit 758" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB757  ,Group Status Bit 757" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB756  ,Group Status Bit 756" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB755  ,Group Status Bit 755" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB754  ,Group Status Bit 754" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB753  ,Group Status Bit 753" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB752  ,Group Status Bit 752" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB751  ,Group Status Bit 751" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB750  ,Group Status Bit 750" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB749  ,Group Status Bit 749" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB748  ,Group Status Bit 748" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB747  ,Group Status Bit 747" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB746  ,Group Status Bit 746" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB745  ,Group Status Bit 745" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB744  ,Group Status Bit 744" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB743  ,Group Status Bit 743" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB742  ,Group Status Bit 742" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB741  ,Group Status Bit 741" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB740  ,Group Status Bit 740" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB739  ,Group Status Bit 739" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB738  ,Group Status Bit 738" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB737  ,Group Status Bit 737" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB736  ,Group Status Bit 736" "Group 0,Group 1"
else
rgroup.long 0x00DC++0x03
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x18)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00E0))
group.long 0x00E0++0x03
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure access)"
bitfld.long 0x00 31. " GSB799  ,Group Status Bit 799" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB798  ,Group Status Bit 798" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB797  ,Group Status Bit 797" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB796  ,Group Status Bit 796" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB795  ,Group Status Bit 795" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB794  ,Group Status Bit 794" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB793  ,Group Status Bit 793" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB792  ,Group Status Bit 792" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB791  ,Group Status Bit 791" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB790  ,Group Status Bit 790" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB789  ,Group Status Bit 789" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB788  ,Group Status Bit 788" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB787  ,Group Status Bit 787" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB786  ,Group Status Bit 786" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB785  ,Group Status Bit 785" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB784  ,Group Status Bit 784" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB783  ,Group Status Bit 783" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB782  ,Group Status Bit 782" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB781  ,Group Status Bit 781" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB780  ,Group Status Bit 780" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB779  ,Group Status Bit 779" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB778  ,Group Status Bit 778" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB777  ,Group Status Bit 777" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB776  ,Group Status Bit 776" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB775  ,Group Status Bit 775" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB774  ,Group Status Bit 774" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB773  ,Group Status Bit 773" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB772  ,Group Status Bit 772" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB771  ,Group Status Bit 771" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB770  ,Group Status Bit 770" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB769  ,Group Status Bit 769" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB768  ,Group Status Bit 768" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x18)
group.long 0x00E0++0x03
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Non-secure access)"
bitfld.long 0x00 31. " GSB799  ,Group Status Bit 799" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB798  ,Group Status Bit 798" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB797  ,Group Status Bit 797" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB796  ,Group Status Bit 796" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB795  ,Group Status Bit 795" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB794  ,Group Status Bit 794" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB793  ,Group Status Bit 793" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB792  ,Group Status Bit 792" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB791  ,Group Status Bit 791" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB790  ,Group Status Bit 790" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB789  ,Group Status Bit 789" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB788  ,Group Status Bit 788" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB787  ,Group Status Bit 787" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB786  ,Group Status Bit 786" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB785  ,Group Status Bit 785" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB784  ,Group Status Bit 784" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB783  ,Group Status Bit 783" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB782  ,Group Status Bit 782" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB781  ,Group Status Bit 781" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB780  ,Group Status Bit 780" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB779  ,Group Status Bit 779" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB778  ,Group Status Bit 778" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB777  ,Group Status Bit 777" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB776  ,Group Status Bit 776" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB775  ,Group Status Bit 775" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB774  ,Group Status Bit 774" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB773  ,Group Status Bit 773" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB772  ,Group Status Bit 772" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB771  ,Group Status Bit 771" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB770  ,Group Status Bit 770" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB769  ,Group Status Bit 769" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB768  ,Group Status Bit 768" "Group 0,Group 1"
else
rgroup.long 0x0E0++0x03
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x19)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00E4))
group.long 0x00E4++0x03
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure access)"
bitfld.long 0x00 31. " GSB831  ,Group Status Bit 831" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB830  ,Group Status Bit 830" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB829  ,Group Status Bit 829" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB828  ,Group Status Bit 828" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB827  ,Group Status Bit 827" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB826  ,Group Status Bit 826" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB825  ,Group Status Bit 825" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB824  ,Group Status Bit 824" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB823  ,Group Status Bit 823" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB822  ,Group Status Bit 822" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB821  ,Group Status Bit 821" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB820  ,Group Status Bit 820" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB819  ,Group Status Bit 819" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB818  ,Group Status Bit 818" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB817  ,Group Status Bit 817" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB816  ,Group Status Bit 816" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB815  ,Group Status Bit 815" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB814  ,Group Status Bit 814" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB813  ,Group Status Bit 813" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB812  ,Group Status Bit 812" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB811  ,Group Status Bit 811" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB810  ,Group Status Bit 810" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB809  ,Group Status Bit 809" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB808  ,Group Status Bit 808" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB807  ,Group Status Bit 807" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB806  ,Group Status Bit 806" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB805  ,Group Status Bit 805" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB804  ,Group Status Bit 804" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB803  ,Group Status Bit 803" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB802  ,Group Status Bit 802" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB801  ,Group Status Bit 801" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB800  ,Group Status Bit 800" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x19)
group.long 0x00E4++0x03
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Non-secure access)"
bitfld.long 0x00 31. " GSB831  ,Group Status Bit 831" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB830  ,Group Status Bit 830" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB829  ,Group Status Bit 829" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB828  ,Group Status Bit 828" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB827  ,Group Status Bit 827" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB826  ,Group Status Bit 826" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB825  ,Group Status Bit 825" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB824  ,Group Status Bit 824" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB823  ,Group Status Bit 823" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB822  ,Group Status Bit 822" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB821  ,Group Status Bit 821" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB820  ,Group Status Bit 820" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB819  ,Group Status Bit 819" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB818  ,Group Status Bit 818" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB817  ,Group Status Bit 817" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB816  ,Group Status Bit 816" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB815  ,Group Status Bit 815" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB814  ,Group Status Bit 814" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB813  ,Group Status Bit 813" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB812  ,Group Status Bit 812" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB811  ,Group Status Bit 811" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB810  ,Group Status Bit 810" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB809  ,Group Status Bit 809" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB808  ,Group Status Bit 808" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB807  ,Group Status Bit 807" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB806  ,Group Status Bit 806" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB805  ,Group Status Bit 805" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB804  ,Group Status Bit 804" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB803  ,Group Status Bit 803" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB802  ,Group Status Bit 802" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB801  ,Group Status Bit 801" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB800  ,Group Status Bit 800" "Group 0,Group 1"
else
rgroup.long 0x00E4++0x03
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1A)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00E8))
group.long 0x00E8++0x03
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure access)"
bitfld.long 0x00 31. " GSB863  ,Group Status Bit 863" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB862  ,Group Status Bit 862" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB861  ,Group Status Bit 861" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB860  ,Group Status Bit 860" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB859  ,Group Status Bit 859" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB858  ,Group Status Bit 858" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB857  ,Group Status Bit 857" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB856  ,Group Status Bit 856" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB855  ,Group Status Bit 855" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB854  ,Group Status Bit 854" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB853  ,Group Status Bit 853" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB852  ,Group Status Bit 852" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB851  ,Group Status Bit 851" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB850  ,Group Status Bit 850" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB849  ,Group Status Bit 849" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB848  ,Group Status Bit 848" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB847  ,Group Status Bit 847" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB846  ,Group Status Bit 846" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB845  ,Group Status Bit 845" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB844  ,Group Status Bit 844" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB843  ,Group Status Bit 843" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB842  ,Group Status Bit 842" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB841  ,Group Status Bit 841" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB840  ,Group Status Bit 840" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB839  ,Group Status Bit 839" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB838  ,Group Status Bit 838" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB837  ,Group Status Bit 837" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB836  ,Group Status Bit 836" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB835  ,Group Status Bit 835" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB834  ,Group Status Bit 834" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB833  ,Group Status Bit 833" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB832  ,Group Status Bit 832" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1A)
group.long 0x00E8++0x03
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Non-secure access)"
bitfld.long 0x00 31. " GSB863  ,Group Status Bit 863" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB862  ,Group Status Bit 862" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB861  ,Group Status Bit 861" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB860  ,Group Status Bit 860" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB859  ,Group Status Bit 859" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB858  ,Group Status Bit 858" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB857  ,Group Status Bit 857" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB856  ,Group Status Bit 856" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB855  ,Group Status Bit 855" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB854  ,Group Status Bit 854" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB853  ,Group Status Bit 853" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB852  ,Group Status Bit 852" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB851  ,Group Status Bit 851" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB850  ,Group Status Bit 850" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB849  ,Group Status Bit 849" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB848  ,Group Status Bit 848" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB847  ,Group Status Bit 847" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB846  ,Group Status Bit 846" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB845  ,Group Status Bit 845" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB844  ,Group Status Bit 844" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB843  ,Group Status Bit 843" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB842  ,Group Status Bit 842" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB841  ,Group Status Bit 841" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB840  ,Group Status Bit 840" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB839  ,Group Status Bit 839" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB838  ,Group Status Bit 838" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB837  ,Group Status Bit 837" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB836  ,Group Status Bit 836" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB835  ,Group Status Bit 835" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB834  ,Group Status Bit 834" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB833  ,Group Status Bit 833" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB832  ,Group Status Bit 832" "Group 0,Group 1"
else
rgroup.long 0x00E8++0x03
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1B)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00EC))
group.long 0x00EC++0x03
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure access)"
bitfld.long 0x00 31. " GSB895  ,Group Status Bit 895" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB894  ,Group Status Bit 894" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB893  ,Group Status Bit 893" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB892  ,Group Status Bit 892" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB891  ,Group Status Bit 891" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB890  ,Group Status Bit 890" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB889  ,Group Status Bit 889" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB888  ,Group Status Bit 888" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB887  ,Group Status Bit 887" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB886  ,Group Status Bit 886" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB885  ,Group Status Bit 885" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB884  ,Group Status Bit 884" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB883  ,Group Status Bit 883" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB882  ,Group Status Bit 882" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB881  ,Group Status Bit 881" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB880  ,Group Status Bit 880" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB879  ,Group Status Bit 879" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB878  ,Group Status Bit 878" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB877  ,Group Status Bit 877" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB876  ,Group Status Bit 876" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB875  ,Group Status Bit 875" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB874  ,Group Status Bit 874" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB873  ,Group Status Bit 873" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB872  ,Group Status Bit 872" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB871  ,Group Status Bit 871" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB870  ,Group Status Bit 870" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB869  ,Group Status Bit 869" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB868  ,Group Status Bit 868" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB867  ,Group Status Bit 867" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB866  ,Group Status Bit 866" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB865  ,Group Status Bit 865" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB864  ,Group Status Bit 864" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1B)
group.long 0x00EC++0x03
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Non-Secure access)"
bitfld.long 0x00 31. " GSB895  ,Group Status Bit 895" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB894  ,Group Status Bit 894" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB893  ,Group Status Bit 893" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB892  ,Group Status Bit 892" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB891  ,Group Status Bit 891" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB890  ,Group Status Bit 890" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB889  ,Group Status Bit 889" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB888  ,Group Status Bit 888" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB887  ,Group Status Bit 887" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB886  ,Group Status Bit 886" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB885  ,Group Status Bit 885" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB884  ,Group Status Bit 884" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB883  ,Group Status Bit 883" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB882  ,Group Status Bit 882" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB881  ,Group Status Bit 881" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB880  ,Group Status Bit 880" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB879  ,Group Status Bit 879" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB878  ,Group Status Bit 878" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB877  ,Group Status Bit 877" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB876  ,Group Status Bit 876" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB875  ,Group Status Bit 875" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB874  ,Group Status Bit 874" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB873  ,Group Status Bit 873" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB872  ,Group Status Bit 872" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB871  ,Group Status Bit 871" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB870  ,Group Status Bit 870" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB869  ,Group Status Bit 869" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB868  ,Group Status Bit 868" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB867  ,Group Status Bit 867" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB866  ,Group Status Bit 866" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB865  ,Group Status Bit 865" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB864  ,Group Status Bit 864" "Group 0,Group 1"
else
rgroup.long 0x00EC++0x03
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1C)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00F0))
group.long 0x00F0++0x03
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure access)"
bitfld.long 0x00 31. " GSB927  ,Group Status Bit 927" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB926  ,Group Status Bit 926" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB925  ,Group Status Bit 925" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB924  ,Group Status Bit 924" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB923  ,Group Status Bit 923" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB922  ,Group Status Bit 922" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB921  ,Group Status Bit 921" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB920  ,Group Status Bit 920" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB919  ,Group Status Bit 919" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB918  ,Group Status Bit 918" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB917  ,Group Status Bit 917" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB916  ,Group Status Bit 916" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB915  ,Group Status Bit 915" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB914  ,Group Status Bit 914" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB913  ,Group Status Bit 913" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB912  ,Group Status Bit 912" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB911  ,Group Status Bit 911" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB910  ,Group Status Bit 910" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB909  ,Group Status Bit 909" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB908  ,Group Status Bit 908" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB907  ,Group Status Bit 907" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB906  ,Group Status Bit 906" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB905  ,Group Status Bit 905" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB904  ,Group Status Bit 904" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB903  ,Group Status Bit 903" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB902  ,Group Status Bit 902" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB901  ,Group Status Bit 901" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB900  ,Group Status Bit 900" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB899  ,Group Status Bit 899" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB898  ,Group Status Bit 898" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB897  ,Group Status Bit 897" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB896  ,Group Status Bit 896" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1C)
group.long 0x00F0++0x03
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Non-secure access)"
bitfld.long 0x00 31. " GSB927  ,Group Status Bit 927" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB926  ,Group Status Bit 926" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB925  ,Group Status Bit 925" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB924  ,Group Status Bit 924" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB923  ,Group Status Bit 923" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB922  ,Group Status Bit 922" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB921  ,Group Status Bit 921" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB920  ,Group Status Bit 920" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB919  ,Group Status Bit 919" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB918  ,Group Status Bit 918" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB917  ,Group Status Bit 917" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB916  ,Group Status Bit 916" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB915  ,Group Status Bit 915" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB914  ,Group Status Bit 914" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB913  ,Group Status Bit 913" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB912  ,Group Status Bit 912" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB911  ,Group Status Bit 911" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB910  ,Group Status Bit 910" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB909  ,Group Status Bit 909" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB908  ,Group Status Bit 908" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB907  ,Group Status Bit 907" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB906  ,Group Status Bit 906" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB905  ,Group Status Bit 905" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB904  ,Group Status Bit 904" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB903  ,Group Status Bit 903" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB902  ,Group Status Bit 902" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB901  ,Group Status Bit 901" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB900  ,Group Status Bit 900" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB899  ,Group Status Bit 899" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB898  ,Group Status Bit 898" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB897  ,Group Status Bit 897" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB896  ,Group Status Bit 896" "Group 0,Group 1"
else
rgroup.long 0x0F0++0x03
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1D)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00F4))
group.long 0x00F4++0x03
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure access)"
bitfld.long 0x00 31. " GSB959  ,Group Status Bit 959" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB958  ,Group Status Bit 958" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB957  ,Group Status Bit 957" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB956  ,Group Status Bit 956" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB955  ,Group Status Bit 955" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB954  ,Group Status Bit 954" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB953  ,Group Status Bit 953" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB952  ,Group Status Bit 952" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB951  ,Group Status Bit 951" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB950  ,Group Status Bit 950" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB949  ,Group Status Bit 949" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB948  ,Group Status Bit 948" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB947  ,Group Status Bit 947" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB946  ,Group Status Bit 946" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB945  ,Group Status Bit 945" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB944  ,Group Status Bit 944" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB943  ,Group Status Bit 943" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB942  ,Group Status Bit 942" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB941  ,Group Status Bit 941" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB940  ,Group Status Bit 940" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB939  ,Group Status Bit 939" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB938  ,Group Status Bit 938" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB937  ,Group Status Bit 937" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB936  ,Group Status Bit 936" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB935  ,Group Status Bit 935" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB934  ,Group Status Bit 934" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB933  ,Group Status Bit 933" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB932  ,Group Status Bit 932" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB931  ,Group Status Bit 931" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB930  ,Group Status Bit 930" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB929  ,Group Status Bit 929" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB928  ,Group Status Bit 928" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1D)
group.long 0x00F4++0x03
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Non-secure access)"
bitfld.long 0x00 31. " GSB959  ,Group Status Bit 959" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB958  ,Group Status Bit 958" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB957  ,Group Status Bit 957" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB956  ,Group Status Bit 956" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB955  ,Group Status Bit 955" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB954  ,Group Status Bit 954" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB953  ,Group Status Bit 953" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB952  ,Group Status Bit 952" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB951  ,Group Status Bit 951" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB950  ,Group Status Bit 950" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB949  ,Group Status Bit 949" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB948  ,Group Status Bit 948" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB947  ,Group Status Bit 947" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB946  ,Group Status Bit 946" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB945  ,Group Status Bit 945" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB944  ,Group Status Bit 944" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB943  ,Group Status Bit 943" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB942  ,Group Status Bit 942" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB941  ,Group Status Bit 941" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB940  ,Group Status Bit 940" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB939  ,Group Status Bit 939" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB938  ,Group Status Bit 938" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB937  ,Group Status Bit 937" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB936  ,Group Status Bit 936" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB935  ,Group Status Bit 935" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB934  ,Group Status Bit 934" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB933  ,Group Status Bit 933" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB932  ,Group Status Bit 932" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB931  ,Group Status Bit 931" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB930  ,Group Status Bit 930" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB929  ,Group Status Bit 929" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB928  ,Group Status Bit 928" "Group 0,Group 1"
else
rgroup.long 0x00F4++0x03
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1E)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00F8))
group.long 0x00F8++0x03
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure access)"
bitfld.long 0x00 31. " GSB991  ,Group Status Bit 991" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 30. "  GSB990  ,Group Status Bit 990" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 29. "  GSB989  ,Group Status Bit 989" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 28. " GSB988  ,Group Status Bit 988" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 27. "  GSB987  ,Group Status Bit 987" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB986  ,Group Status Bit 986" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB985  ,Group Status Bit 985" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB984  ,Group Status Bit 984" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB983  ,Group Status Bit 983" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB982  ,Group Status Bit 982" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB981  ,Group Status Bit 981" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB980  ,Group Status Bit 980" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB979  ,Group Status Bit 979" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB978  ,Group Status Bit 978" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB977  ,Group Status Bit 977" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB976  ,Group Status Bit 976" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB975  ,Group Status Bit 975" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB974  ,Group Status Bit 974" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB973  ,Group Status Bit 973" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB972  ,Group Status Bit 972" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB971  ,Group Status Bit 971" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB970  ,Group Status Bit 970" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB969  ,Group Status Bit 969" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB968  ,Group Status Bit 968" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB967  ,Group Status Bit 967" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB966  ,Group Status Bit 966" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB965  ,Group Status Bit 965" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB964  ,Group Status Bit 964" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB963  ,Group Status Bit 963" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB962  ,Group Status Bit 962" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB961  ,Group Status Bit 961" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB960  ,Group Status Bit 960" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1E)
group.long 0x00F8++0x03
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Non-secure access)"
bitfld.long 0x00 31. " GSB991  ,Group Status Bit 991" "Group 0,Group 1"
bitfld.long 0x00 30. "  GSB990  ,Group Status Bit 990" "Group 0,Group 1"
bitfld.long 0x00 29. "  GSB989  ,Group Status Bit 989" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB988  ,Group Status Bit 988" "Group 0,Group 1"
bitfld.long 0x00 27. "  GSB987  ,Group Status Bit 987" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB986  ,Group Status Bit 986" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB985  ,Group Status Bit 985" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB984  ,Group Status Bit 984" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB983  ,Group Status Bit 983" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB982  ,Group Status Bit 982" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB981  ,Group Status Bit 981" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB980  ,Group Status Bit 980" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB979  ,Group Status Bit 979" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB978  ,Group Status Bit 978" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB977  ,Group Status Bit 977" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB976  ,Group Status Bit 976" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB975  ,Group Status Bit 975" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB974  ,Group Status Bit 974" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB973  ,Group Status Bit 973" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB972  ,Group Status Bit 972" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB971  ,Group Status Bit 971" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB970  ,Group Status Bit 970" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB969  ,Group Status Bit 969" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB968  ,Group Status Bit 968" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB967  ,Group Status Bit 967" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB966  ,Group Status Bit 966" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB965  ,Group Status Bit 965" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB964  ,Group Status Bit 964" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB963  ,Group Status Bit 963" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB962  ,Group Status Bit 962" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB961  ,Group Status Bit 961" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB960  ,Group Status Bit 960" "Group 0,Group 1"
else
rgroup.long 0x00F8++0x03
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)==0x1F)&&(PER.ADDRESS.isSECUREEX(ad:0xFFFC1000+0x00FC))
group.long 0x00FC++0x03
line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Secure access)"
bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 26. "  GSB1018 ,Group Status Bit 1018" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 24. "  GSB1016 ,Group Status Bit 1016" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 23. "  GSB1015 ,Group Status Bit 1015" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 21. "  GSB1013 ,Group Status Bit 1013" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 20. "  GSB1012 ,Group Status Bit 1012" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 18. "  GSB1010 ,Group Status Bit 1010" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 17. "  GSB1009 ,Group Status Bit 1009" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 15. "  GSB1007 ,Group Status Bit 1007" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 14. "  GSB1006 ,Group Status Bit 1006" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 12. "  GSB1004 ,Group Status Bit 1004" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 11. "  GSB1003 ,Group Status Bit 1003" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 9. "  GSB1001 ,Group Status Bit 1001" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 8. "  GSB1000 ,Group Status Bit 1000" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 7. " GSB999  ,Group Status Bit 999" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 6. "  GSB998  ,Group Status Bit 998" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 5. "  GSB997  ,Group Status Bit 997" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 4. " GSB996  ,Group Status Bit 996" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 3. "  GSB995  ,Group Status Bit 995" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 2. "  GSB994  ,Group Status Bit 994" "Group 0 (Secure),Group 1 (Non-secure)"
textline "                          "
bitfld.long 0x00 1. " GSB993  ,Group Status Bit 993" "Group 0 (Secure),Group 1 (Non-secure)"
bitfld.long 0x00 0. "  GSB992  ,Group Status Bit 992" "Group 0 (Secure),Group 1 (Non-secure)"
elif (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)==0x1F)
group.long 0x00FC++0x03
line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Non-secure access)"
bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0,Group 1"
bitfld.long 0x00 26. "  GSB1018 ,Group Status Bit 1018" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0,Group 1"
bitfld.long 0x00 24. "  GSB1016 ,Group Status Bit 1016" "Group 0,Group 1"
bitfld.long 0x00 23. "  GSB1015 ,Group Status Bit 1015" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0,Group 1"
bitfld.long 0x00 21. "  GSB1013 ,Group Status Bit 1013" "Group 0,Group 1"
bitfld.long 0x00 20. "  GSB1012 ,Group Status Bit 1012" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0,Group 1"
bitfld.long 0x00 18. "  GSB1010 ,Group Status Bit 1010" "Group 0,Group 1"
bitfld.long 0x00 17. "  GSB1009 ,Group Status Bit 1009" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0,Group 1"
bitfld.long 0x00 15. "  GSB1007 ,Group Status Bit 1007" "Group 0,Group 1"
bitfld.long 0x00 14. "  GSB1006 ,Group Status Bit 1006" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0,Group 1"
bitfld.long 0x00 12. "  GSB1004 ,Group Status Bit 1004" "Group 0,Group 1"
bitfld.long 0x00 11. "  GSB1003 ,Group Status Bit 1003" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0,Group 1"
bitfld.long 0x00 9. "  GSB1001 ,Group Status Bit 1001" "Group 0,Group 1"
bitfld.long 0x00 8. "  GSB1000 ,Group Status Bit 1000" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB999  ,Group Status Bit 999" "Group 0,Group 1"
bitfld.long 0x00 6. "  GSB998  ,Group Status Bit 998" "Group 0,Group 1"
bitfld.long 0x00 5. "  GSB997  ,Group Status Bit 997" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB996  ,Group Status Bit 996" "Group 0,Group 1"
bitfld.long 0x00 3. "  GSB995  ,Group Status Bit 995" "Group 0,Group 1"
bitfld.long 0x00 2. "  GSB994  ,Group Status Bit 994" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB993  ,Group Status Bit 993" "Group 0,Group 1"
bitfld.long 0x00 0. "  GSB992  ,Group Status Bit 992" "Group 0,Group 1"
else
rgroup.long 0x00FC++0x03
line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
tree.end
endif
width 24.
tree "Set/Clear Enable Registers"
group.long 0x0100++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31   ,Set/Clear Enable Bit 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB30   ,Set/Clear Enable Bit 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB29   ,Set/Clear Enable Bit 29" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28   ,Set/Clear Enable Bit 28" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB27   ,Set/Clear Enable Bit 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB26   ,Set/Clear Enable Bit 26" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25   ,Set/Clear Enable Bit 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB24   ,Set/Clear Enable Bit 24" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB23   ,Set/Clear Enable Bit 23" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22   ,Set/Clear Enable Bit 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB21   ,Set/Clear Enable Bit 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB20   ,Set/Clear Enable Bit 20" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19   ,Set/Clear Enable Bit 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB18   ,Set/Clear Enable Bit 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB17   ,Set/Clear Enable Bit 17" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16   ,Set/Clear Enable Bit 16" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB15   ,Set/Clear Enable Bit 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB14   ,Set/Clear Enable Bit 14" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13   ,Set/Clear Enable Bit 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB12   ,Set/Clear Enable Bit 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB11   ,Set/Clear Enable Bit 11" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10   ,Set/Clear Enable Bit 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB9    ,Set/Clear Enable Bit 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB8    ,Set/Clear Enable Bit 8" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7    ,Set/Clear Enable Bit 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB6    ,Set/Clear Enable Bit 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB5    ,Set/Clear Enable Bit 5" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4    ,Set/Clear Enable Bit 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB3    ,Set/Clear Enable Bit 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB2    ,Set/Clear Enable Bit 2" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1    ,Set/Clear Enable Bit 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB0    ,Set/Clear Enable Bit 0" "Disabled,Enabled"
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x01)
group.long 0x0104++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63   ,Set/Clear Enable Bit 63" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB62   ,Set/Clear Enable Bit 62" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB61   ,Set/Clear Enable Bit 61" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60   ,Set/Clear Enable Bit 60" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB59   ,Set/Clear Enable Bit 59" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB58   ,Set/Clear Enable Bit 58" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57   ,Set/Clear Enable Bit 57" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB56   ,Set/Clear Enable Bit 56" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB55   ,Set/Clear Enable Bit 55" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54   ,Set/Clear Enable Bit 54" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB53   ,Set/Clear Enable Bit 53" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB52   ,Set/Clear Enable Bit 52" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51   ,Set/Clear Enable Bit 51" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB50   ,Set/Clear Enable Bit 50" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB49   ,Set/Clear Enable Bit 49" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48   ,Set/Clear Enable Bit 48" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB47   ,Set/Clear Enable Bit 47" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB46   ,Set/Clear Enable Bit 46" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45   ,Set/Clear Enable Bit 45" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB44   ,Set/Clear Enable Bit 44" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB43   ,Set/Clear Enable Bit 43" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42   ,Set/Clear Enable Bit 42" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB41   ,Set/Clear Enable Bit 41" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB40   ,Set/Clear Enable Bit 40" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39   ,Set/Clear Enable Bit 39" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB38   ,Set/Clear Enable Bit 38" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB37   ,Set/Clear Enable Bit 37" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36   ,Set/Clear Enable Bit 36" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB35   ,Set/Clear Enable Bit 35" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB34   ,Set/Clear Enable Bit 34" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33   ,Set/Clear Enable Bit 33" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB32   ,Set/Clear Enable Bit 32" "Disabled,Enabled"
else
rgroup.long 0x0104++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x02)
group.long 0x0108++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95   ,Set/Clear Enable Bit 95" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB94   ,Set/Clear Enable Bit 94" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB93   ,Set/Clear Enable Bit 93" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92   ,Set/Clear Enable Bit 92" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB91   ,Set/Clear Enable Bit 91" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB90   ,Set/Clear Enable Bit 90" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89   ,Set/Clear Enable Bit 89" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB88   ,Set/Clear Enable Bit 88" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB87   ,Set/Clear Enable Bit 87" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86   ,Set/Clear Enable Bit 86" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB85   ,Set/Clear Enable Bit 85" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB84   ,Set/Clear Enable Bit 84" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83   ,Set/Clear Enable Bit 83" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB82   ,Set/Clear Enable Bit 82" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB81   ,Set/Clear Enable Bit 81" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80   ,Set/Clear Enable Bit 80" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB79   ,Set/Clear Enable Bit 79" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB78   ,Set/Clear Enable Bit 78" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77   ,Set/Clear Enable Bit 77" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB76   ,Set/Clear Enable Bit 76" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB75   ,Set/Clear Enable Bit 75" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74   ,Set/Clear Enable Bit 74" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB73   ,Set/Clear Enable Bit 73" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB72   ,Set/Clear Enable Bit 72" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71   ,Set/Clear Enable Bit 71" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB70   ,Set/Clear Enable Bit 70" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB69   ,Set/Clear Enable Bit 69" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68   ,Set/Clear Enable Bit 68" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB67   ,Set/Clear Enable Bit 67" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB66   ,Set/Clear Enable Bit 66" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65   ,Set/Clear Enable Bit 65" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB64   ,Set/Clear Enable Bit 64" "Disabled,Enabled"
else
rgroup.long 0x0108++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x03)
group.long 0x010C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127  ,Set/Clear Enable Bit 127" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB126  ,Set/Clear Enable Bit 126" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB125  ,Set/Clear Enable Bit 125" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124  ,Set/Clear Enable Bit 124" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB123  ,Set/Clear Enable Bit 123" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB122  ,Set/Clear Enable Bit 122" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121  ,Set/Clear Enable Bit 121" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB120  ,Set/Clear Enable Bit 120" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB119  ,Set/Clear Enable Bit 119" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118  ,Set/Clear Enable Bit 118" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB117  ,Set/Clear Enable Bit 117" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB116  ,Set/Clear Enable Bit 116" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115  ,Set/Clear Enable Bit 115" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB114  ,Set/Clear Enable Bit 114" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB113  ,Set/Clear Enable Bit 113" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112  ,Set/Clear Enable Bit 112" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB111  ,Set/Clear Enable Bit 111" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB110  ,Set/Clear Enable Bit 110" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109  ,Set/Clear Enable Bit 109" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB108  ,Set/Clear Enable Bit 108" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB107  ,Set/Clear Enable Bit 107" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106  ,Set/Clear Enable Bit 106" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB105  ,Set/Clear Enable Bit 105" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB104  ,Set/Clear Enable Bit 104" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103  ,Set/Clear Enable Bit 103" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB102  ,Set/Clear Enable Bit 102" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB101  ,Set/Clear Enable Bit 101" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100  ,Set/Clear Enable Bit 100" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB99   ,Set/Clear Enable Bit 99" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB98   ,Set/Clear Enable Bit 98" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97   ,Set/Clear Enable Bit 97" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB96   ,Set/Clear Enable Bit 96" "Disabled,Enabled"
else
rgroup.long 0x010C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x04)
group.long 0x0110++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159  ,Set/Clear Enable Bit 159" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB158  ,Set/Clear Enable Bit 158" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB157  ,Set/Clear Enable Bit 157" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156  ,Set/Clear Enable Bit 156" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB155  ,Set/Clear Enable Bit 155" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB154  ,Set/Clear Enable Bit 154" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153  ,Set/Clear Enable Bit 153" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB152  ,Set/Clear Enable Bit 152" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB151  ,Set/Clear Enable Bit 151" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150  ,Set/Clear Enable Bit 150" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB149  ,Set/Clear Enable Bit 149" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB148  ,Set/Clear Enable Bit 148" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147  ,Set/Clear Enable Bit 147" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB146  ,Set/Clear Enable Bit 146" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB145  ,Set/Clear Enable Bit 145" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144  ,Set/Clear Enable Bit 144" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB143  ,Set/Clear Enable Bit 143" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB142  ,Set/Clear Enable Bit 142" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141  ,Set/Clear Enable Bit 141" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB140  ,Set/Clear Enable Bit 140" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB139  ,Set/Clear Enable Bit 139" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138  ,Set/Clear Enable Bit 138" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB137  ,Set/Clear Enable Bit 137" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB136  ,Set/Clear Enable Bit 136" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135  ,Set/Clear Enable Bit 135" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB134  ,Set/Clear Enable Bit 134" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB133  ,Set/Clear Enable Bit 133" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132  ,Set/Clear Enable Bit 132" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB131  ,Set/Clear Enable Bit 131" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB130  ,Set/Clear Enable Bit 130" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129  ,Set/Clear Enable Bit 129" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB128  ,Set/Clear Enable Bit 128" "Disabled,Enabled"
else
rgroup.long 0x0110++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x05)
group.long 0x0114++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191  ,Set/Clear Enable Bit 191" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB190  ,Set/Clear Enable Bit 190" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB189  ,Set/Clear Enable Bit 189" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188  ,Set/Clear Enable Bit 188" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB187  ,Set/Clear Enable Bit 187" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB186  ,Set/Clear Enable Bit 186" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185  ,Set/Clear Enable Bit 185" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB184  ,Set/Clear Enable Bit 184" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB183  ,Set/Clear Enable Bit 183" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182  ,Set/Clear Enable Bit 182" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB181  ,Set/Clear Enable Bit 181" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB180  ,Set/Clear Enable Bit 180" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179  ,Set/Clear Enable Bit 179" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB178  ,Set/Clear Enable Bit 178" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB177  ,Set/Clear Enable Bit 177" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176  ,Set/Clear Enable Bit 176" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB175  ,Set/Clear Enable Bit 175" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB174  ,Set/Clear Enable Bit 174" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173  ,Set/Clear Enable Bit 173" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB172  ,Set/Clear Enable Bit 172" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB171  ,Set/Clear Enable Bit 171" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170  ,Set/Clear Enable Bit 170" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB169  ,Set/Clear Enable Bit 169" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB168  ,Set/Clear Enable Bit 168" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167  ,Set/Clear Enable Bit 167" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB166  ,Set/Clear Enable Bit 166" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB165  ,Set/Clear Enable Bit 165" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164  ,Set/Clear Enable Bit 164" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB163  ,Set/Clear Enable Bit 163" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB162  ,Set/Clear Enable Bit 162" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161  ,Set/Clear Enable Bit 161" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB160  ,Set/Clear Enable Bit 160" "Disabled,Enabled"
else
rgroup.long 0x0114++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x06)
group.long 0x0118++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223  ,Set/Clear Enable Bit 223" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB222  ,Set/Clear Enable Bit 222" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB221  ,Set/Clear Enable Bit 221" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220  ,Set/Clear Enable Bit 220" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB219  ,Set/Clear Enable Bit 219" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB218  ,Set/Clear Enable Bit 218" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217  ,Set/Clear Enable Bit 217" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB216  ,Set/Clear Enable Bit 216" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB215  ,Set/Clear Enable Bit 215" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214  ,Set/Clear Enable Bit 214" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB213  ,Set/Clear Enable Bit 213" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB212  ,Set/Clear Enable Bit 212" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211  ,Set/Clear Enable Bit 211" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB210  ,Set/Clear Enable Bit 210" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB209  ,Set/Clear Enable Bit 209" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208  ,Set/Clear Enable Bit 208" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB207  ,Set/Clear Enable Bit 207" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB206  ,Set/Clear Enable Bit 206" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205  ,Set/Clear Enable Bit 205" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB204  ,Set/Clear Enable Bit 204" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB203  ,Set/Clear Enable Bit 203" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202  ,Set/Clear Enable Bit 202" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB201  ,Set/Clear Enable Bit 201" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB200  ,Set/Clear Enable Bit 200" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199  ,Set/Clear Enable Bit 199" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB198  ,Set/Clear Enable Bit 198" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB197  ,Set/Clear Enable Bit 197" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196  ,Set/Clear Enable Bit 196" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB195  ,Set/Clear Enable Bit 195" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB194  ,Set/Clear Enable Bit 194" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193  ,Set/Clear Enable Bit 193" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB192  ,Set/Clear Enable Bit 192" "Disabled,Enabled"
else
rgroup.long 0x0118++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x07)
group.long 0x011C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255  ,Set/Clear Enable Bit 255" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB254  ,Set/Clear Enable Bit 254" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB253  ,Set/Clear Enable Bit 253" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252  ,Set/Clear Enable Bit 252" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB251  ,Set/Clear Enable Bit 251" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB250  ,Set/Clear Enable Bit 250" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249  ,Set/Clear Enable Bit 249" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB248  ,Set/Clear Enable Bit 248" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB247  ,Set/Clear Enable Bit 247" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246  ,Set/Clear Enable Bit 246" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB245  ,Set/Clear Enable Bit 245" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB244  ,Set/Clear Enable Bit 244" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243  ,Set/Clear Enable Bit 243" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB242  ,Set/Clear Enable Bit 242" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB241  ,Set/Clear Enable Bit 241" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240  ,Set/Clear Enable Bit 240" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB239  ,Set/Clear Enable Bit 239" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB238  ,Set/Clear Enable Bit 238" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237  ,Set/Clear Enable Bit 237" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB236  ,Set/Clear Enable Bit 236" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB235  ,Set/Clear Enable Bit 235" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234  ,Set/Clear Enable Bit 234" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB233  ,Set/Clear Enable Bit 233" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB232  ,Set/Clear Enable Bit 232" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231  ,Set/Clear Enable Bit 231" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB230  ,Set/Clear Enable Bit 230" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB229  ,Set/Clear Enable Bit 229" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228  ,Set/Clear Enable Bit 228" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB227  ,Set/Clear Enable Bit 227" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB226  ,Set/Clear Enable Bit 226" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225  ,Set/Clear Enable Bit 225" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB224  ,Set/Clear Enable Bit 224" "Disabled,Enabled"
else
rgroup.long 0x011C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x08)
group.long 0x0120++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287  ,Set/Clear Enable Bit 287" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB286  ,Set/Clear Enable Bit 286" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB285  ,Set/Clear Enable Bit 285" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284  ,Set/Clear Enable Bit 284" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB283  ,Set/Clear Enable Bit 283" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB282  ,Set/Clear Enable Bit 282" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281  ,Set/Clear Enable Bit 281" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB280  ,Set/Clear Enable Bit 280" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB279  ,Set/Clear Enable Bit 279" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278  ,Set/Clear Enable Bit 278" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB277  ,Set/Clear Enable Bit 277" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB276  ,Set/Clear Enable Bit 276" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275  ,Set/Clear Enable Bit 275" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB274  ,Set/Clear Enable Bit 274" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB273  ,Set/Clear Enable Bit 273" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272  ,Set/Clear Enable Bit 272" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB271  ,Set/Clear Enable Bit 271" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB270  ,Set/Clear Enable Bit 270" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269  ,Set/Clear Enable Bit 269" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB268  ,Set/Clear Enable Bit 268" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB267  ,Set/Clear Enable Bit 267" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266  ,Set/Clear Enable Bit 266" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB265  ,Set/Clear Enable Bit 265" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB264  ,Set/Clear Enable Bit 264" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263  ,Set/Clear Enable Bit 263" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB262  ,Set/Clear Enable Bit 262" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB261  ,Set/Clear Enable Bit 261" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260  ,Set/Clear Enable Bit 260" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB259  ,Set/Clear Enable Bit 259" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB258  ,Set/Clear Enable Bit 258" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257  ,Set/Clear Enable Bit 257" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB256  ,Set/Clear Enable Bit 256" "Disabled,Enabled"
else
rgroup.long 0x0120++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x09)
group.long 0x0124++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319  ,Set/Clear Enable Bit 319" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB318  ,Set/Clear Enable Bit 318" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB317  ,Set/Clear Enable Bit 317" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316  ,Set/Clear Enable Bit 316" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB315  ,Set/Clear Enable Bit 315" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB314  ,Set/Clear Enable Bit 314" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313  ,Set/Clear Enable Bit 313" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB312  ,Set/Clear Enable Bit 312" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB311  ,Set/Clear Enable Bit 311" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310  ,Set/Clear Enable Bit 310" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB309  ,Set/Clear Enable Bit 309" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB308  ,Set/Clear Enable Bit 308" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307  ,Set/Clear Enable Bit 307" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB306  ,Set/Clear Enable Bit 306" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB305  ,Set/Clear Enable Bit 305" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304  ,Set/Clear Enable Bit 304" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB303  ,Set/Clear Enable Bit 303" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB302  ,Set/Clear Enable Bit 302" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301  ,Set/Clear Enable Bit 301" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB300  ,Set/Clear Enable Bit 300" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB299  ,Set/Clear Enable Bit 299" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298  ,Set/Clear Enable Bit 298" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB297  ,Set/Clear Enable Bit 297" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB296  ,Set/Clear Enable Bit 296" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295  ,Set/Clear Enable Bit 295" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB294  ,Set/Clear Enable Bit 294" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB293  ,Set/Clear Enable Bit 293" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292  ,Set/Clear Enable Bit 292" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB291  ,Set/Clear Enable Bit 291" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB290  ,Set/Clear Enable Bit 290" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289  ,Set/Clear Enable Bit 289" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB288  ,Set/Clear Enable Bit 288" "Disabled,Enabled"
else
rgroup.long 0x0124++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0A)
group.long 0x0128++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351  ,Set/Clear Enable Bit 351" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB350  ,Set/Clear Enable Bit 350" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB349  ,Set/Clear Enable Bit 349" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348  ,Set/Clear Enable Bit 348" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB347  ,Set/Clear Enable Bit 347" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB346  ,Set/Clear Enable Bit 346" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345  ,Set/Clear Enable Bit 345" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB344  ,Set/Clear Enable Bit 344" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB343  ,Set/Clear Enable Bit 343" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342  ,Set/Clear Enable Bit 342" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB341  ,Set/Clear Enable Bit 341" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB340  ,Set/Clear Enable Bit 340" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339  ,Set/Clear Enable Bit 339" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB338  ,Set/Clear Enable Bit 338" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB337  ,Set/Clear Enable Bit 337" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336  ,Set/Clear Enable Bit 336" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB335  ,Set/Clear Enable Bit 335" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB334  ,Set/Clear Enable Bit 334" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333  ,Set/Clear Enable Bit 333" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB332  ,Set/Clear Enable Bit 332" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB331  ,Set/Clear Enable Bit 331" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330  ,Set/Clear Enable Bit 330" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB329  ,Set/Clear Enable Bit 329" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB328  ,Set/Clear Enable Bit 328" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327  ,Set/Clear Enable Bit 327" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB326  ,Set/Clear Enable Bit 326" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB325  ,Set/Clear Enable Bit 325" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324  ,Set/Clear Enable Bit 324" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB323  ,Set/Clear Enable Bit 323" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB322  ,Set/Clear Enable Bit 322" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321  ,Set/Clear Enable Bit 321" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB320  ,Set/Clear Enable Bit 320" "Disabled,Enabled"
else
rgroup.long 0x0128++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0B)
group.long 0x012C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383  ,Set/Clear Enable Bit 383" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB382  ,Set/Clear Enable Bit 382" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB381  ,Set/Clear Enable Bit 381" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380  ,Set/Clear Enable Bit 380" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB379  ,Set/Clear Enable Bit 379" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB378  ,Set/Clear Enable Bit 378" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377  ,Set/Clear Enable Bit 377" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB376  ,Set/Clear Enable Bit 376" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB375  ,Set/Clear Enable Bit 375" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374  ,Set/Clear Enable Bit 374" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB373  ,Set/Clear Enable Bit 373" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB372  ,Set/Clear Enable Bit 372" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371  ,Set/Clear Enable Bit 371" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB370  ,Set/Clear Enable Bit 370" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB369  ,Set/Clear Enable Bit 369" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368  ,Set/Clear Enable Bit 368" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB367  ,Set/Clear Enable Bit 367" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB366  ,Set/Clear Enable Bit 366" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365  ,Set/Clear Enable Bit 365" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB364  ,Set/Clear Enable Bit 364" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB363  ,Set/Clear Enable Bit 363" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362  ,Set/Clear Enable Bit 362" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB361  ,Set/Clear Enable Bit 361" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB360  ,Set/Clear Enable Bit 360" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359  ,Set/Clear Enable Bit 359" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB358  ,Set/Clear Enable Bit 358" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB357  ,Set/Clear Enable Bit 357" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356  ,Set/Clear Enable Bit 356" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB355  ,Set/Clear Enable Bit 355" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB354  ,Set/Clear Enable Bit 354" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353  ,Set/Clear Enable Bit 353" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB352  ,Set/Clear Enable Bit 352" "Disabled,Enabled"
else
rgroup.long 0x012C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0C)
group.long 0x0130++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415  ,Set/Clear Enable Bit 415" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB414  ,Set/Clear Enable Bit 414" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB413  ,Set/Clear Enable Bit 413" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412  ,Set/Clear Enable Bit 412" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB411  ,Set/Clear Enable Bit 411" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB410  ,Set/Clear Enable Bit 410" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409  ,Set/Clear Enable Bit 409" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB408  ,Set/Clear Enable Bit 408" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB407  ,Set/Clear Enable Bit 407" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406  ,Set/Clear Enable Bit 406" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB405  ,Set/Clear Enable Bit 405" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB404  ,Set/Clear Enable Bit 404" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403  ,Set/Clear Enable Bit 403" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB402  ,Set/Clear Enable Bit 402" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB401  ,Set/Clear Enable Bit 401" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400  ,Set/Clear Enable Bit 400" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB399  ,Set/Clear Enable Bit 399" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB398  ,Set/Clear Enable Bit 398" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397  ,Set/Clear Enable Bit 397" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB396  ,Set/Clear Enable Bit 396" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB395  ,Set/Clear Enable Bit 395" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394  ,Set/Clear Enable Bit 394" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB393  ,Set/Clear Enable Bit 393" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB392  ,Set/Clear Enable Bit 392" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391  ,Set/Clear Enable Bit 391" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB390  ,Set/Clear Enable Bit 390" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB389  ,Set/Clear Enable Bit 389" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388  ,Set/Clear Enable Bit 388" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB387  ,Set/Clear Enable Bit 387" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB386  ,Set/Clear Enable Bit 386" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385  ,Set/Clear Enable Bit 385" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB384  ,Set/Clear Enable Bit 384" "Disabled,Enabled"
else
rgroup.long 0x0130++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0D)
group.long 0x0134++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447  ,Set/Clear Enable Bit 447" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB446  ,Set/Clear Enable Bit 446" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB445  ,Set/Clear Enable Bit 445" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444  ,Set/Clear Enable Bit 444" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB443  ,Set/Clear Enable Bit 443" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB442  ,Set/Clear Enable Bit 442" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441  ,Set/Clear Enable Bit 441" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB440  ,Set/Clear Enable Bit 440" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB439  ,Set/Clear Enable Bit 439" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438  ,Set/Clear Enable Bit 438" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB437  ,Set/Clear Enable Bit 437" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB436  ,Set/Clear Enable Bit 436" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435  ,Set/Clear Enable Bit 435" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB434  ,Set/Clear Enable Bit 434" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB433  ,Set/Clear Enable Bit 433" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432  ,Set/Clear Enable Bit 432" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB431  ,Set/Clear Enable Bit 431" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB430  ,Set/Clear Enable Bit 430" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429  ,Set/Clear Enable Bit 429" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB428  ,Set/Clear Enable Bit 428" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB427  ,Set/Clear Enable Bit 427" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426  ,Set/Clear Enable Bit 426" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB425  ,Set/Clear Enable Bit 425" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB424  ,Set/Clear Enable Bit 424" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423  ,Set/Clear Enable Bit 423" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB422  ,Set/Clear Enable Bit 422" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB421  ,Set/Clear Enable Bit 421" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420  ,Set/Clear Enable Bit 420" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB419  ,Set/Clear Enable Bit 419" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB418  ,Set/Clear Enable Bit 418" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417  ,Set/Clear Enable Bit 417" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB416  ,Set/Clear Enable Bit 416" "Disabled,Enabled"
else
rgroup.long 0x0134++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0E)
group.long 0x0138++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479  ,Set/Clear Enable Bit 479" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB478  ,Set/Clear Enable Bit 478" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB477  ,Set/Clear Enable Bit 477" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476  ,Set/Clear Enable Bit 476" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB475  ,Set/Clear Enable Bit 475" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB474  ,Set/Clear Enable Bit 474" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473  ,Set/Clear Enable Bit 473" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB472  ,Set/Clear Enable Bit 472" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB471  ,Set/Clear Enable Bit 471" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470  ,Set/Clear Enable Bit 470" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB469  ,Set/Clear Enable Bit 469" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB468  ,Set/Clear Enable Bit 468" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467  ,Set/Clear Enable Bit 467" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB466  ,Set/Clear Enable Bit 466" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB465  ,Set/Clear Enable Bit 465" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464  ,Set/Clear Enable Bit 464" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB463  ,Set/Clear Enable Bit 463" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB462  ,Set/Clear Enable Bit 462" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461  ,Set/Clear Enable Bit 461" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB460  ,Set/Clear Enable Bit 460" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB459  ,Set/Clear Enable Bit 459" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458  ,Set/Clear Enable Bit 458" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB457  ,Set/Clear Enable Bit 457" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB456  ,Set/Clear Enable Bit 456" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455  ,Set/Clear Enable Bit 455" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB454  ,Set/Clear Enable Bit 454" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB453  ,Set/Clear Enable Bit 453" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452  ,Set/Clear Enable Bit 452" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB451  ,Set/Clear Enable Bit 451" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB450  ,Set/Clear Enable Bit 450" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449  ,Set/Clear Enable Bit 449" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB448  ,Set/Clear Enable Bit 448" "Disabled,Enabled"
else
rgroup.long 0x0138++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0F)
group.long 0x013C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511  ,Set/Clear Enable Bit 511" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB510  ,Set/Clear Enable Bit 510" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB509  ,Set/Clear Enable Bit 509" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508  ,Set/Clear Enable Bit 508" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB507  ,Set/Clear Enable Bit 507" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB506  ,Set/Clear Enable Bit 506" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505  ,Set/Clear Enable Bit 505" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB504  ,Set/Clear Enable Bit 504" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB503  ,Set/Clear Enable Bit 503" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502  ,Set/Clear Enable Bit 502" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB501  ,Set/Clear Enable Bit 501" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB500  ,Set/Clear Enable Bit 500" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499  ,Set/Clear Enable Bit 499" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB498  ,Set/Clear Enable Bit 498" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB497  ,Set/Clear Enable Bit 497" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496  ,Set/Clear Enable Bit 496" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB495  ,Set/Clear Enable Bit 495" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB494  ,Set/Clear Enable Bit 494" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493  ,Set/Clear Enable Bit 493" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB492  ,Set/Clear Enable Bit 492" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB491  ,Set/Clear Enable Bit 491" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490  ,Set/Clear Enable Bit 490" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB489  ,Set/Clear Enable Bit 489" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB488  ,Set/Clear Enable Bit 488" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487  ,Set/Clear Enable Bit 487" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB486  ,Set/Clear Enable Bit 486" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB485  ,Set/Clear Enable Bit 485" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484  ,Set/Clear Enable Bit 484" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB483  ,Set/Clear Enable Bit 483" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB482  ,Set/Clear Enable Bit 482" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481  ,Set/Clear Enable Bit 481" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB480  ,Set/Clear Enable Bit 480" "Disabled,Enabled"
else
rgroup.long 0x013C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x10)
group.long 0x0140++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543  ,Set/Clear Enable Bit 543" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB542  ,Set/Clear Enable Bit 542" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB541  ,Set/Clear Enable Bit 541" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540  ,Set/Clear Enable Bit 540" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB539  ,Set/Clear Enable Bit 539" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB538  ,Set/Clear Enable Bit 538" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537  ,Set/Clear Enable Bit 537" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB536  ,Set/Clear Enable Bit 536" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB535  ,Set/Clear Enable Bit 535" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534  ,Set/Clear Enable Bit 534" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB533  ,Set/Clear Enable Bit 533" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB532  ,Set/Clear Enable Bit 532" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531  ,Set/Clear Enable Bit 531" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB530  ,Set/Clear Enable Bit 530" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB529  ,Set/Clear Enable Bit 529" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528  ,Set/Clear Enable Bit 528" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB527  ,Set/Clear Enable Bit 527" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB526  ,Set/Clear Enable Bit 526" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525  ,Set/Clear Enable Bit 525" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB524  ,Set/Clear Enable Bit 524" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB523  ,Set/Clear Enable Bit 523" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522  ,Set/Clear Enable Bit 522" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB521  ,Set/Clear Enable Bit 521" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB520  ,Set/Clear Enable Bit 520" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519  ,Set/Clear Enable Bit 519" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB518  ,Set/Clear Enable Bit 518" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB517  ,Set/Clear Enable Bit 517" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516  ,Set/Clear Enable Bit 516" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB515  ,Set/Clear Enable Bit 515" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB514  ,Set/Clear Enable Bit 514" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513  ,Set/Clear Enable Bit 513" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB512  ,Set/Clear Enable Bit 512" "Disabled,Enabled"
else
rgroup.long 0x0140++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x11)
group.long 0x0144++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575  ,Set/Clear Enable Bit 575" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB574  ,Set/Clear Enable Bit 574" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB573  ,Set/Clear Enable Bit 573" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572  ,Set/Clear Enable Bit 572" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB571  ,Set/Clear Enable Bit 571" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB570  ,Set/Clear Enable Bit 570" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569  ,Set/Clear Enable Bit 569" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB568  ,Set/Clear Enable Bit 568" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB567  ,Set/Clear Enable Bit 567" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566  ,Set/Clear Enable Bit 566" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB565  ,Set/Clear Enable Bit 565" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB564  ,Set/Clear Enable Bit 564" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563  ,Set/Clear Enable Bit 563" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB562  ,Set/Clear Enable Bit 562" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB561  ,Set/Clear Enable Bit 561" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560  ,Set/Clear Enable Bit 560" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB559  ,Set/Clear Enable Bit 559" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB558  ,Set/Clear Enable Bit 558" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557  ,Set/Clear Enable Bit 557" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB556  ,Set/Clear Enable Bit 556" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB555  ,Set/Clear Enable Bit 555" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554  ,Set/Clear Enable Bit 554" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB553  ,Set/Clear Enable Bit 553" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB552  ,Set/Clear Enable Bit 552" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551  ,Set/Clear Enable Bit 551" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB550  ,Set/Clear Enable Bit 550" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB549  ,Set/Clear Enable Bit 549" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548  ,Set/Clear Enable Bit 548" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB547  ,Set/Clear Enable Bit 547" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB546  ,Set/Clear Enable Bit 546" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545  ,Set/Clear Enable Bit 545" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB544  ,Set/Clear Enable Bit 544" "Disabled,Enabled"
else
rgroup.long 0x0144++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x12)
group.long 0x0148++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607  ,Set/Clear Enable Bit 607" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB606  ,Set/Clear Enable Bit 606" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB605  ,Set/Clear Enable Bit 605" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604  ,Set/Clear Enable Bit 604" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB603  ,Set/Clear Enable Bit 603" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB602  ,Set/Clear Enable Bit 602" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601  ,Set/Clear Enable Bit 601" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB600  ,Set/Clear Enable Bit 600" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB599  ,Set/Clear Enable Bit 599" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598  ,Set/Clear Enable Bit 598" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB597  ,Set/Clear Enable Bit 597" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB596  ,Set/Clear Enable Bit 596" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595  ,Set/Clear Enable Bit 595" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB594  ,Set/Clear Enable Bit 594" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB593  ,Set/Clear Enable Bit 593" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592  ,Set/Clear Enable Bit 592" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB591  ,Set/Clear Enable Bit 591" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB590  ,Set/Clear Enable Bit 590" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589  ,Set/Clear Enable Bit 589" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB588  ,Set/Clear Enable Bit 588" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB587  ,Set/Clear Enable Bit 587" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586  ,Set/Clear Enable Bit 586" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB585  ,Set/Clear Enable Bit 585" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB584  ,Set/Clear Enable Bit 584" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583  ,Set/Clear Enable Bit 583" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB582  ,Set/Clear Enable Bit 582" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB581  ,Set/Clear Enable Bit 581" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580  ,Set/Clear Enable Bit 580" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB579  ,Set/Clear Enable Bit 579" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB578  ,Set/Clear Enable Bit 578" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577  ,Set/Clear Enable Bit 577" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB576  ,Set/Clear Enable Bit 576" "Disabled,Enabled"
else
rgroup.long 0x0148++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x13)
group.long 0x014C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639  ,Set/Clear Enable Bit 639" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB638  ,Set/Clear Enable Bit 638" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB637  ,Set/Clear Enable Bit 637" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636  ,Set/Clear Enable Bit 636" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB635  ,Set/Clear Enable Bit 635" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB634  ,Set/Clear Enable Bit 634" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633  ,Set/Clear Enable Bit 633" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB632  ,Set/Clear Enable Bit 632" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB631  ,Set/Clear Enable Bit 631" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630  ,Set/Clear Enable Bit 630" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB629  ,Set/Clear Enable Bit 629" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB628  ,Set/Clear Enable Bit 628" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627  ,Set/Clear Enable Bit 627" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB626  ,Set/Clear Enable Bit 626" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB625  ,Set/Clear Enable Bit 625" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624  ,Set/Clear Enable Bit 624" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB623  ,Set/Clear Enable Bit 623" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB622  ,Set/Clear Enable Bit 622" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621  ,Set/Clear Enable Bit 621" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB620  ,Set/Clear Enable Bit 620" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB619  ,Set/Clear Enable Bit 619" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618  ,Set/Clear Enable Bit 618" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB617  ,Set/Clear Enable Bit 617" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB616  ,Set/Clear Enable Bit 616" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615  ,Set/Clear Enable Bit 615" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB614  ,Set/Clear Enable Bit 614" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB613  ,Set/Clear Enable Bit 613" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612  ,Set/Clear Enable Bit 612" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB611  ,Set/Clear Enable Bit 611" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB610  ,Set/Clear Enable Bit 610" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609  ,Set/Clear Enable Bit 609" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB608  ,Set/Clear Enable Bit 608" "Disabled,Enabled"
else
rgroup.long 0x014C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x14)
group.long 0x0150++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671  ,Set/Clear Enable Bit 671" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB670  ,Set/Clear Enable Bit 670" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB669  ,Set/Clear Enable Bit 669" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668  ,Set/Clear Enable Bit 668" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB667  ,Set/Clear Enable Bit 667" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB666  ,Set/Clear Enable Bit 666" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665  ,Set/Clear Enable Bit 665" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB664  ,Set/Clear Enable Bit 664" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB663  ,Set/Clear Enable Bit 663" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662  ,Set/Clear Enable Bit 662" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB661  ,Set/Clear Enable Bit 661" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB660  ,Set/Clear Enable Bit 660" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659  ,Set/Clear Enable Bit 659" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB658  ,Set/Clear Enable Bit 658" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB657  ,Set/Clear Enable Bit 657" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656  ,Set/Clear Enable Bit 656" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB655  ,Set/Clear Enable Bit 655" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB654  ,Set/Clear Enable Bit 654" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653  ,Set/Clear Enable Bit 653" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB652  ,Set/Clear Enable Bit 652" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB651  ,Set/Clear Enable Bit 651" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650  ,Set/Clear Enable Bit 650" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB649  ,Set/Clear Enable Bit 649" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB648  ,Set/Clear Enable Bit 648" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647  ,Set/Clear Enable Bit 647" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB646  ,Set/Clear Enable Bit 646" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB645  ,Set/Clear Enable Bit 645" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644  ,Set/Clear Enable Bit 644" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB643  ,Set/Clear Enable Bit 643" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB642  ,Set/Clear Enable Bit 642" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641  ,Set/Clear Enable Bit 641" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB640  ,Set/Clear Enable Bit 640" "Disabled,Enabled"
else
rgroup.long 0x0150++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x15)
group.long 0x0154++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703  ,Set/Clear Enable Bit 703" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB702  ,Set/Clear Enable Bit 702" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB701  ,Set/Clear Enable Bit 701" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700  ,Set/Clear Enable Bit 700" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB699  ,Set/Clear Enable Bit 699" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB698  ,Set/Clear Enable Bit 698" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697  ,Set/Clear Enable Bit 697" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB696  ,Set/Clear Enable Bit 696" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB695  ,Set/Clear Enable Bit 695" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694  ,Set/Clear Enable Bit 694" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB693  ,Set/Clear Enable Bit 693" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB692  ,Set/Clear Enable Bit 692" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691  ,Set/Clear Enable Bit 691" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB690  ,Set/Clear Enable Bit 690" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB689  ,Set/Clear Enable Bit 689" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688  ,Set/Clear Enable Bit 688" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB687  ,Set/Clear Enable Bit 687" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB686  ,Set/Clear Enable Bit 686" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685  ,Set/Clear Enable Bit 685" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB684  ,Set/Clear Enable Bit 684" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB683  ,Set/Clear Enable Bit 683" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682  ,Set/Clear Enable Bit 682" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB681  ,Set/Clear Enable Bit 681" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB680  ,Set/Clear Enable Bit 680" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679  ,Set/Clear Enable Bit 679" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB678  ,Set/Clear Enable Bit 678" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB677  ,Set/Clear Enable Bit 677" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676  ,Set/Clear Enable Bit 676" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB675  ,Set/Clear Enable Bit 675" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB674  ,Set/Clear Enable Bit 674" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673  ,Set/Clear Enable Bit 673" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB672  ,Set/Clear Enable Bit 672" "Disabled,Enabled"
else
rgroup.long 0x0154++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x16)
group.long 0x0158++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735  ,Set/Clear Enable Bit 735" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB734  ,Set/Clear Enable Bit 734" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB733  ,Set/Clear Enable Bit 733" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732  ,Set/Clear Enable Bit 732" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB731  ,Set/Clear Enable Bit 731" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB730  ,Set/Clear Enable Bit 730" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729  ,Set/Clear Enable Bit 729" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB728  ,Set/Clear Enable Bit 728" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB727  ,Set/Clear Enable Bit 727" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726  ,Set/Clear Enable Bit 726" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB725  ,Set/Clear Enable Bit 725" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB724  ,Set/Clear Enable Bit 724" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723  ,Set/Clear Enable Bit 723" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB722  ,Set/Clear Enable Bit 722" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB721  ,Set/Clear Enable Bit 721" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720  ,Set/Clear Enable Bit 720" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB719  ,Set/Clear Enable Bit 719" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB718  ,Set/Clear Enable Bit 718" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717  ,Set/Clear Enable Bit 717" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB716  ,Set/Clear Enable Bit 716" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB715  ,Set/Clear Enable Bit 715" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714  ,Set/Clear Enable Bit 714" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB713  ,Set/Clear Enable Bit 713" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB712  ,Set/Clear Enable Bit 712" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711  ,Set/Clear Enable Bit 711" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB710  ,Set/Clear Enable Bit 710" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB709  ,Set/Clear Enable Bit 709" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708  ,Set/Clear Enable Bit 708" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB707  ,Set/Clear Enable Bit 707" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB706  ,Set/Clear Enable Bit 706" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705  ,Set/Clear Enable Bit 705" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB704  ,Set/Clear Enable Bit 704" "Disabled,Enabled"
else
rgroup.long 0x0158++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x17)
group.long 0x015C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767  ,Set/Clear Enable Bit 767" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB766  ,Set/Clear Enable Bit 766" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB765  ,Set/Clear Enable Bit 765" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764  ,Set/Clear Enable Bit 764" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB763  ,Set/Clear Enable Bit 763" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB762  ,Set/Clear Enable Bit 762" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761  ,Set/Clear Enable Bit 761" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB760  ,Set/Clear Enable Bit 760" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB759  ,Set/Clear Enable Bit 759" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758  ,Set/Clear Enable Bit 758" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB757  ,Set/Clear Enable Bit 757" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB756  ,Set/Clear Enable Bit 756" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755  ,Set/Clear Enable Bit 755" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB754  ,Set/Clear Enable Bit 754" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB753  ,Set/Clear Enable Bit 753" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752  ,Set/Clear Enable Bit 752" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB751  ,Set/Clear Enable Bit 751" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB750  ,Set/Clear Enable Bit 750" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749  ,Set/Clear Enable Bit 749" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB748  ,Set/Clear Enable Bit 748" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB747  ,Set/Clear Enable Bit 747" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746  ,Set/Clear Enable Bit 746" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB745  ,Set/Clear Enable Bit 745" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB744  ,Set/Clear Enable Bit 744" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743  ,Set/Clear Enable Bit 743" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB742  ,Set/Clear Enable Bit 742" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB741  ,Set/Clear Enable Bit 741" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740  ,Set/Clear Enable Bit 740" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB739  ,Set/Clear Enable Bit 739" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB738  ,Set/Clear Enable Bit 738" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737  ,Set/Clear Enable Bit 737" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB736  ,Set/Clear Enable Bit 736" "Disabled,Enabled"
else
rgroup.long 0x015C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x18)
group.long 0x0160++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799  ,Set/Clear Enable Bit 799" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB798  ,Set/Clear Enable Bit 798" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB797  ,Set/Clear Enable Bit 797" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796  ,Set/Clear Enable Bit 796" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB795  ,Set/Clear Enable Bit 795" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB794  ,Set/Clear Enable Bit 794" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793  ,Set/Clear Enable Bit 793" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB792  ,Set/Clear Enable Bit 792" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB791  ,Set/Clear Enable Bit 791" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790  ,Set/Clear Enable Bit 790" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB789  ,Set/Clear Enable Bit 789" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB788  ,Set/Clear Enable Bit 788" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787  ,Set/Clear Enable Bit 787" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB786  ,Set/Clear Enable Bit 786" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB785  ,Set/Clear Enable Bit 785" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784  ,Set/Clear Enable Bit 784" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB783  ,Set/Clear Enable Bit 783" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB782  ,Set/Clear Enable Bit 782" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781  ,Set/Clear Enable Bit 781" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB780  ,Set/Clear Enable Bit 780" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB779  ,Set/Clear Enable Bit 779" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778  ,Set/Clear Enable Bit 778" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB777  ,Set/Clear Enable Bit 777" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB776  ,Set/Clear Enable Bit 776" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775  ,Set/Clear Enable Bit 775" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB774  ,Set/Clear Enable Bit 774" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB773  ,Set/Clear Enable Bit 773" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772  ,Set/Clear Enable Bit 772" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB771  ,Set/Clear Enable Bit 771" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB770  ,Set/Clear Enable Bit 770" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769  ,Set/Clear Enable Bit 769" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB768  ,Set/Clear Enable Bit 768" "Disabled,Enabled"
else
rgroup.long 0x0160++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x19)
group.long 0x0164++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831  ,Set/Clear Enable Bit 831" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB830  ,Set/Clear Enable Bit 830" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB829  ,Set/Clear Enable Bit 829" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828  ,Set/Clear Enable Bit 828" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB827  ,Set/Clear Enable Bit 827" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB826  ,Set/Clear Enable Bit 826" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825  ,Set/Clear Enable Bit 825" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB824  ,Set/Clear Enable Bit 824" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB823  ,Set/Clear Enable Bit 823" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822  ,Set/Clear Enable Bit 822" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB821  ,Set/Clear Enable Bit 821" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB820  ,Set/Clear Enable Bit 820" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819  ,Set/Clear Enable Bit 819" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB818  ,Set/Clear Enable Bit 818" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB817  ,Set/Clear Enable Bit 817" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816  ,Set/Clear Enable Bit 816" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB815  ,Set/Clear Enable Bit 815" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB814  ,Set/Clear Enable Bit 814" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813  ,Set/Clear Enable Bit 813" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB812  ,Set/Clear Enable Bit 812" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB811  ,Set/Clear Enable Bit 811" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810  ,Set/Clear Enable Bit 810" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB809  ,Set/Clear Enable Bit 809" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB808  ,Set/Clear Enable Bit 808" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807  ,Set/Clear Enable Bit 807" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB806  ,Set/Clear Enable Bit 806" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB805  ,Set/Clear Enable Bit 805" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804  ,Set/Clear Enable Bit 804" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB803  ,Set/Clear Enable Bit 803" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB802  ,Set/Clear Enable Bit 802" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801  ,Set/Clear Enable Bit 801" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB800  ,Set/Clear Enable Bit 800" "Disabled,Enabled"
else
rgroup.long 0x0164++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1A)
group.long 0x0168++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863  ,Set/Clear Enable Bit 863" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB862  ,Set/Clear Enable Bit 862" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB861  ,Set/Clear Enable Bit 861" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860  ,Set/Clear Enable Bit 860" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB859  ,Set/Clear Enable Bit 859" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB858  ,Set/Clear Enable Bit 858" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857  ,Set/Clear Enable Bit 857" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB856  ,Set/Clear Enable Bit 856" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB855  ,Set/Clear Enable Bit 855" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854  ,Set/Clear Enable Bit 854" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB853  ,Set/Clear Enable Bit 853" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB852  ,Set/Clear Enable Bit 852" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851  ,Set/Clear Enable Bit 851" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB850  ,Set/Clear Enable Bit 850" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB849  ,Set/Clear Enable Bit 849" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848  ,Set/Clear Enable Bit 848" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB847  ,Set/Clear Enable Bit 847" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB846  ,Set/Clear Enable Bit 846" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845  ,Set/Clear Enable Bit 845" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB844  ,Set/Clear Enable Bit 844" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB843  ,Set/Clear Enable Bit 843" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842  ,Set/Clear Enable Bit 842" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB841  ,Set/Clear Enable Bit 841" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB840  ,Set/Clear Enable Bit 840" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839  ,Set/Clear Enable Bit 839" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB838  ,Set/Clear Enable Bit 838" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB837  ,Set/Clear Enable Bit 837" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836  ,Set/Clear Enable Bit 836" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB835  ,Set/Clear Enable Bit 835" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB834  ,Set/Clear Enable Bit 834" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833  ,Set/Clear Enable Bit 833" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB832  ,Set/Clear Enable Bit 832" "Disabled,Enabled"
else
rgroup.long 0x0168++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1B)
group.long 0x016C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895  ,Set/Clear Enable Bit 895" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB894  ,Set/Clear Enable Bit 894" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB893  ,Set/Clear Enable Bit 893" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892  ,Set/Clear Enable Bit 892" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB891  ,Set/Clear Enable Bit 891" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB890  ,Set/Clear Enable Bit 890" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889  ,Set/Clear Enable Bit 889" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB888  ,Set/Clear Enable Bit 888" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB887  ,Set/Clear Enable Bit 887" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886  ,Set/Clear Enable Bit 886" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB885  ,Set/Clear Enable Bit 885" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB884  ,Set/Clear Enable Bit 884" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883  ,Set/Clear Enable Bit 883" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB882  ,Set/Clear Enable Bit 882" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB881  ,Set/Clear Enable Bit 881" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880  ,Set/Clear Enable Bit 880" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB879  ,Set/Clear Enable Bit 879" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB878  ,Set/Clear Enable Bit 878" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877  ,Set/Clear Enable Bit 877" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB876  ,Set/Clear Enable Bit 876" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB875  ,Set/Clear Enable Bit 875" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874  ,Set/Clear Enable Bit 874" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB873  ,Set/Clear Enable Bit 873" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB872  ,Set/Clear Enable Bit 872" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871  ,Set/Clear Enable Bit 871" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB870  ,Set/Clear Enable Bit 870" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB869  ,Set/Clear Enable Bit 869" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868  ,Set/Clear Enable Bit 868" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB867  ,Set/Clear Enable Bit 867" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB866  ,Set/Clear Enable Bit 866" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865  ,Set/Clear Enable Bit 865" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB864  ,Set/Clear Enable Bit 864" "Disabled,Enabled"
else
rgroup.long 0x016C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1C)
group.long 0x0170++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927  ,Set/Clear Enable Bit 927" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB926  ,Set/Clear Enable Bit 926" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB925  ,Set/Clear Enable Bit 925" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924  ,Set/Clear Enable Bit 924" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB923  ,Set/Clear Enable Bit 923" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB922  ,Set/Clear Enable Bit 922" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921  ,Set/Clear Enable Bit 921" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB920  ,Set/Clear Enable Bit 920" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB919  ,Set/Clear Enable Bit 919" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918  ,Set/Clear Enable Bit 918" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB917  ,Set/Clear Enable Bit 917" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB916  ,Set/Clear Enable Bit 916" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915  ,Set/Clear Enable Bit 915" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB914  ,Set/Clear Enable Bit 914" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB913  ,Set/Clear Enable Bit 913" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912  ,Set/Clear Enable Bit 912" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB911  ,Set/Clear Enable Bit 911" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB910  ,Set/Clear Enable Bit 910" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909  ,Set/Clear Enable Bit 909" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB908  ,Set/Clear Enable Bit 908" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB907  ,Set/Clear Enable Bit 907" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906  ,Set/Clear Enable Bit 906" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB905  ,Set/Clear Enable Bit 905" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB904  ,Set/Clear Enable Bit 904" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903  ,Set/Clear Enable Bit 903" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB902  ,Set/Clear Enable Bit 902" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB901  ,Set/Clear Enable Bit 901" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900  ,Set/Clear Enable Bit 900" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB899  ,Set/Clear Enable Bit 899" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB898  ,Set/Clear Enable Bit 898" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897  ,Set/Clear Enable Bit 897" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB896  ,Set/Clear Enable Bit 896" "Disabled,Enabled"
else
rgroup.long 0x0170++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1D)
group.long 0x0174++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959  ,Set/Clear Enable Bit 959" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB958  ,Set/Clear Enable Bit 958" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB957  ,Set/Clear Enable Bit 957" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956  ,Set/Clear Enable Bit 956" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB955  ,Set/Clear Enable Bit 955" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB954  ,Set/Clear Enable Bit 954" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953  ,Set/Clear Enable Bit 953" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB952  ,Set/Clear Enable Bit 952" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB951  ,Set/Clear Enable Bit 951" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950  ,Set/Clear Enable Bit 950" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB949  ,Set/Clear Enable Bit 949" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB948  ,Set/Clear Enable Bit 948" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947  ,Set/Clear Enable Bit 947" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB946  ,Set/Clear Enable Bit 946" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB945  ,Set/Clear Enable Bit 945" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944  ,Set/Clear Enable Bit 944" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB943  ,Set/Clear Enable Bit 943" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB942  ,Set/Clear Enable Bit 942" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941  ,Set/Clear Enable Bit 941" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB940  ,Set/Clear Enable Bit 940" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB939  ,Set/Clear Enable Bit 939" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938  ,Set/Clear Enable Bit 938" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB937  ,Set/Clear Enable Bit 937" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB936  ,Set/Clear Enable Bit 936" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935  ,Set/Clear Enable Bit 935" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB934  ,Set/Clear Enable Bit 934" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB933  ,Set/Clear Enable Bit 933" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932  ,Set/Clear Enable Bit 932" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB931  ,Set/Clear Enable Bit 931" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB930  ,Set/Clear Enable Bit 930" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929  ,Set/Clear Enable Bit 929" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB928  ,Set/Clear Enable Bit 928" "Disabled,Enabled"
else
rgroup.long 0x0174++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1E)
group.long 0x0178++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991  ,Set/Clear Enable Bit 991" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB990  ,Set/Clear Enable Bit 990" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB989  ,Set/Clear Enable Bit 989" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988  ,Set/Clear Enable Bit 988" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB987  ,Set/Clear Enable Bit 987" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB986  ,Set/Clear Enable Bit 986" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985  ,Set/Clear Enable Bit 985" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB984  ,Set/Clear Enable Bit 984" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB983  ,Set/Clear Enable Bit 983" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982  ,Set/Clear Enable Bit 982" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB981  ,Set/Clear Enable Bit 981" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB980  ,Set/Clear Enable Bit 980" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979  ,Set/Clear Enable Bit 979" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB978  ,Set/Clear Enable Bit 978" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB977  ,Set/Clear Enable Bit 977" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976  ,Set/Clear Enable Bit 976" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB975  ,Set/Clear Enable Bit 975" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB974  ,Set/Clear Enable Bit 974" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973  ,Set/Clear Enable Bit 973" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB972  ,Set/Clear Enable Bit 972" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB971  ,Set/Clear Enable Bit 971" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970  ,Set/Clear Enable Bit 970" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB969  ,Set/Clear Enable Bit 969" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB968  ,Set/Clear Enable Bit 968" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967  ,Set/Clear Enable Bit 967" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB966  ,Set/Clear Enable Bit 966" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB965  ,Set/Clear Enable Bit 965" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964  ,Set/Clear Enable Bit 964" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB963  ,Set/Clear Enable Bit 963" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB962  ,Set/Clear Enable Bit 962" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961  ,Set/Clear Enable Bit 961" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB960  ,Set/Clear Enable Bit 960" "Disabled,Enabled"
else
rgroup.long 0x0178++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)==0x1F)
group.long 0x017C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB1019 ,Set/Clear Enable Bit 1019" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB1018 ,Set/Clear Enable Bit 1018" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB1017 ,Set/Clear Enable Bit 1017" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB1016 ,Set/Clear Enable Bit 1016" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB1015 ,Set/Clear Enable Bit 1015" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB1014 ,Set/Clear Enable Bit 1014" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB1013 ,Set/Clear Enable Bit 1013" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB1012 ,Set/Clear Enable Bit 1012" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB1011 ,Set/Clear Enable Bit 1011" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB1010 ,Set/Clear Enable Bit 1010" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB1009 ,Set/Clear Enable Bit 1009" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB1008 ,Set/Clear Enable Bit 1008" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB1007 ,Set/Clear Enable Bit 1007" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB1006 ,Set/Clear Enable Bit 1006" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB1005 ,Set/Clear Enable Bit 1005" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB1004 ,Set/Clear Enable Bit 1004" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB1003 ,Set/Clear Enable Bit 1003" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB1002 ,Set/Clear Enable Bit 1002" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB1001 ,Set/Clear Enable Bit 1001" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB1000 ,Set/Clear Enable Bit 1000" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB999  ,Set/Clear Enable Bit 999" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB998  ,Set/Clear Enable Bit 998" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB997  ,Set/Clear Enable Bit 997" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB996  ,Set/Clear Enable Bit 996" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB995  ,Set/Clear Enable Bit 995" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB994  ,Set/Clear Enable Bit 994" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB993  ,Set/Clear Enable Bit 993" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB992  ,Set/Clear Enable Bit 992" "Disabled,Enabled"
else
rgroup.long 0x017C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
tree.end
width 22.
tree "Set/Clear Pending Registers"
group.long 0x0200++0x03
line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31   ,Set/Clear Pending Bit 31" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND30   ,Set/Clear Pending Bit 30" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND29   ,Set/Clear Pending Bit 29" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28   ,Set/Clear Pending Bit 28" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND27   ,Set/Clear Pending Bit 27" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND26   ,Set/Clear Pending Bit 26" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25   ,Set/Clear Pending Bit 25" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND24   ,Set/Clear Pending Bit 24" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND23   ,Set/Clear Pending Bit 23" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22   ,Set/Clear Pending Bit 22" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND21   ,Set/Clear Pending Bit 21" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND20   ,Set/Clear Pending Bit 20" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19   ,Set/Clear Pending Bit 19" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND18   ,Set/Clear Pending Bit 18" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND17   ,Set/Clear Pending Bit 17" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16   ,Set/Clear Pending Bit 16" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND15   ,Set/Clear Pending Bit 15" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND14   ,Set/Clear Pending Bit 14" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13   ,Set/Clear Pending Bit 13" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND12   ,Set/Clear Pending Bit 12" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND11   ,Set/Clear Pending Bit 11" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10   ,Set/Clear Pending Bit 10" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND9    ,Set/Clear Pending Bit 9" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND8    ,Set/Clear Pending Bit 8" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7    ,Set/Clear Pending Bit 7" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND6    ,Set/Clear Pending Bit 6" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND5    ,Set/Clear Pending Bit 5" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4    ,Set/Clear Pending Bit 4" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND3    ,Set/Clear Pending Bit 3" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND2    ,Set/Clear Pending Bit 2" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1    ,Set/Clear Pending Bit 1" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND0    ,Set/Clear Pending Bit 0" "Not pending,Pending"
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x01)
group.long 0x0204++0x03
line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63   ,Set/Clear Pending Bit 63" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND62   ,Set/Clear Pending Bit 62" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND61   ,Set/Clear Pending Bit 61" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60   ,Set/Clear Pending Bit 60" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND59   ,Set/Clear Pending Bit 59" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND58   ,Set/Clear Pending Bit 58" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57   ,Set/Clear Pending Bit 57" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND56   ,Set/Clear Pending Bit 56" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND55   ,Set/Clear Pending Bit 55" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54   ,Set/Clear Pending Bit 54" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND53   ,Set/Clear Pending Bit 53" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND52   ,Set/Clear Pending Bit 52" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51   ,Set/Clear Pending Bit 51" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND50   ,Set/Clear Pending Bit 50" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND49   ,Set/Clear Pending Bit 49" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48   ,Set/Clear Pending Bit 48" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND47   ,Set/Clear Pending Bit 47" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND46   ,Set/Clear Pending Bit 46" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45   ,Set/Clear Pending Bit 45" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND44   ,Set/Clear Pending Bit 44" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND43   ,Set/Clear Pending Bit 43" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42   ,Set/Clear Pending Bit 42" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND41   ,Set/Clear Pending Bit 41" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND40   ,Set/Clear Pending Bit 40" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39   ,Set/Clear Pending Bit 39" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND38   ,Set/Clear Pending Bit 38" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND37   ,Set/Clear Pending Bit 37" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36   ,Set/Clear Pending Bit 36" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND35   ,Set/Clear Pending Bit 35" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND34   ,Set/Clear Pending Bit 34" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33   ,Set/Clear Pending Bit 33" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND32   ,Set/Clear Pending Bit 32" "Not pending,Pending"
else
rgroup.long 0x0204++0x03
line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x02)
group.long 0x0208++0x03
line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95   ,Set/Clear Pending Bit 95" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND94   ,Set/Clear Pending Bit 94" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND93   ,Set/Clear Pending Bit 93" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92   ,Set/Clear Pending Bit 92" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND91   ,Set/Clear Pending Bit 91" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND90   ,Set/Clear Pending Bit 90" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89   ,Set/Clear Pending Bit 89" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND88   ,Set/Clear Pending Bit 88" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND87   ,Set/Clear Pending Bit 87" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86   ,Set/Clear Pending Bit 86" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND85   ,Set/Clear Pending Bit 85" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND84   ,Set/Clear Pending Bit 84" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83   ,Set/Clear Pending Bit 83" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND82   ,Set/Clear Pending Bit 82" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND81   ,Set/Clear Pending Bit 81" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80   ,Set/Clear Pending Bit 80" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND79   ,Set/Clear Pending Bit 79" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND78   ,Set/Clear Pending Bit 78" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77   ,Set/Clear Pending Bit 77" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND76   ,Set/Clear Pending Bit 76" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND75   ,Set/Clear Pending Bit 75" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74   ,Set/Clear Pending Bit 74" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND73   ,Set/Clear Pending Bit 73" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND72   ,Set/Clear Pending Bit 72" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71   ,Set/Clear Pending Bit 71" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND70   ,Set/Clear Pending Bit 70" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND69   ,Set/Clear Pending Bit 69" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68   ,Set/Clear Pending Bit 68" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND67   ,Set/Clear Pending Bit 67" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND66   ,Set/Clear Pending Bit 66" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65   ,Set/Clear Pending Bit 65" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND64   ,Set/Clear Pending Bit 64" "Not pending,Pending"
else
rgroup.long 0x0208++0x03
line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x03)
group.long 0x020C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127  ,Set/Clear Pending Bit 127" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND126  ,Set/Clear Pending Bit 126" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND125  ,Set/Clear Pending Bit 125" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124  ,Set/Clear Pending Bit 124" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND123  ,Set/Clear Pending Bit 123" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND122  ,Set/Clear Pending Bit 122" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121  ,Set/Clear Pending Bit 121" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND120  ,Set/Clear Pending Bit 120" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND119  ,Set/Clear Pending Bit 119" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118  ,Set/Clear Pending Bit 118" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND117  ,Set/Clear Pending Bit 117" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND116  ,Set/Clear Pending Bit 116" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115  ,Set/Clear Pending Bit 115" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND114  ,Set/Clear Pending Bit 114" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND113  ,Set/Clear Pending Bit 113" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112  ,Set/Clear Pending Bit 112" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND111  ,Set/Clear Pending Bit 111" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND110  ,Set/Clear Pending Bit 110" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109  ,Set/Clear Pending Bit 109" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND108  ,Set/Clear Pending Bit 108" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND107  ,Set/Clear Pending Bit 107" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106  ,Set/Clear Pending Bit 106" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND105  ,Set/Clear Pending Bit 105" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND104  ,Set/Clear Pending Bit 104" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103  ,Set/Clear Pending Bit 103" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND102  ,Set/Clear Pending Bit 102" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND101  ,Set/Clear Pending Bit 101" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100  ,Set/Clear Pending Bit 100" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND99   ,Set/Clear Pending Bit 99" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND98   ,Set/Clear Pending Bit 98" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97   ,Set/Clear Pending Bit 97" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND96   ,Set/Clear Pending Bit 96" "Not pending,Pending"
else
rgroup.long 0x020C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x04)
group.long 0x0210++0x03
line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159  ,Set/Clear Pending Bit 159" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND158  ,Set/Clear Pending Bit 158" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND157  ,Set/Clear Pending Bit 157" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156  ,Set/Clear Pending Bit 156" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND155  ,Set/Clear Pending Bit 155" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND154  ,Set/Clear Pending Bit 154" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153  ,Set/Clear Pending Bit 153" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND152  ,Set/Clear Pending Bit 152" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND151  ,Set/Clear Pending Bit 151" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150  ,Set/Clear Pending Bit 150" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND149  ,Set/Clear Pending Bit 149" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND148  ,Set/Clear Pending Bit 148" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147  ,Set/Clear Pending Bit 147" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND146  ,Set/Clear Pending Bit 146" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND145  ,Set/Clear Pending Bit 145" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144  ,Set/Clear Pending Bit 144" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND143  ,Set/Clear Pending Bit 143" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND142  ,Set/Clear Pending Bit 142" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141  ,Set/Clear Pending Bit 141" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND140  ,Set/Clear Pending Bit 140" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND139  ,Set/Clear Pending Bit 139" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138  ,Set/Clear Pending Bit 138" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND137  ,Set/Clear Pending Bit 137" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND136  ,Set/Clear Pending Bit 136" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135  ,Set/Clear Pending Bit 135" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND134  ,Set/Clear Pending Bit 134" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND133  ,Set/Clear Pending Bit 133" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132  ,Set/Clear Pending Bit 132" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND131  ,Set/Clear Pending Bit 131" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND130  ,Set/Clear Pending Bit 130" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129  ,Set/Clear Pending Bit 129" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND128  ,Set/Clear Pending Bit 128" "Not pending,Pending"
else
rgroup.long 0x0210++0x03
line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x05)
group.long 0x0214++0x03
line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191  ,Set/Clear Pending Bit 191" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND190  ,Set/Clear Pending Bit 190" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND189  ,Set/Clear Pending Bit 189" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188  ,Set/Clear Pending Bit 188" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND187  ,Set/Clear Pending Bit 187" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND186  ,Set/Clear Pending Bit 186" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185  ,Set/Clear Pending Bit 185" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND184  ,Set/Clear Pending Bit 184" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND183  ,Set/Clear Pending Bit 183" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182  ,Set/Clear Pending Bit 182" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND181  ,Set/Clear Pending Bit 181" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND180  ,Set/Clear Pending Bit 180" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179  ,Set/Clear Pending Bit 179" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND178  ,Set/Clear Pending Bit 178" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND177  ,Set/Clear Pending Bit 177" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176  ,Set/Clear Pending Bit 176" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND175  ,Set/Clear Pending Bit 175" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND174  ,Set/Clear Pending Bit 174" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173  ,Set/Clear Pending Bit 173" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND172  ,Set/Clear Pending Bit 172" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND171  ,Set/Clear Pending Bit 171" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170  ,Set/Clear Pending Bit 170" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND169  ,Set/Clear Pending Bit 169" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND168  ,Set/Clear Pending Bit 168" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167  ,Set/Clear Pending Bit 167" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND166  ,Set/Clear Pending Bit 166" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND165  ,Set/Clear Pending Bit 165" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164  ,Set/Clear Pending Bit 164" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND163  ,Set/Clear Pending Bit 163" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND162  ,Set/Clear Pending Bit 162" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161  ,Set/Clear Pending Bit 161" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND160  ,Set/Clear Pending Bit 160" "Not pending,Pending"
else
rgroup.long 0x0214++0x03
line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x06)
group.long 0x0218++0x03
line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223  ,Set/Clear Pending Bit 223" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND222  ,Set/Clear Pending Bit 222" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND221  ,Set/Clear Pending Bit 221" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220  ,Set/Clear Pending Bit 220" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND219  ,Set/Clear Pending Bit 219" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND218  ,Set/Clear Pending Bit 218" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217  ,Set/Clear Pending Bit 217" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND216  ,Set/Clear Pending Bit 216" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND215  ,Set/Clear Pending Bit 215" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214  ,Set/Clear Pending Bit 214" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND213  ,Set/Clear Pending Bit 213" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND212  ,Set/Clear Pending Bit 212" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211  ,Set/Clear Pending Bit 211" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND210  ,Set/Clear Pending Bit 210" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND209  ,Set/Clear Pending Bit 209" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208  ,Set/Clear Pending Bit 208" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND207  ,Set/Clear Pending Bit 207" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND206  ,Set/Clear Pending Bit 206" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205  ,Set/Clear Pending Bit 205" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND204  ,Set/Clear Pending Bit 204" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND203  ,Set/Clear Pending Bit 203" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202  ,Set/Clear Pending Bit 202" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND201  ,Set/Clear Pending Bit 201" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND200  ,Set/Clear Pending Bit 200" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199  ,Set/Clear Pending Bit 199" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND198  ,Set/Clear Pending Bit 198" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND197  ,Set/Clear Pending Bit 197" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196  ,Set/Clear Pending Bit 196" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND195  ,Set/Clear Pending Bit 195" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND194  ,Set/Clear Pending Bit 194" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193  ,Set/Clear Pending Bit 193" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND192  ,Set/Clear Pending Bit 192" "Not pending,Pending"
else
rgroup.long 0x0218++0x03
line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x07)
group.long 0x021C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255  ,Set/Clear Pending Bit 255" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND254  ,Set/Clear Pending Bit 254" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND253  ,Set/Clear Pending Bit 253" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252  ,Set/Clear Pending Bit 252" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND251  ,Set/Clear Pending Bit 251" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND250  ,Set/Clear Pending Bit 250" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249  ,Set/Clear Pending Bit 249" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND248  ,Set/Clear Pending Bit 248" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND247  ,Set/Clear Pending Bit 247" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246  ,Set/Clear Pending Bit 246" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND245  ,Set/Clear Pending Bit 245" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND244  ,Set/Clear Pending Bit 244" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243  ,Set/Clear Pending Bit 243" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND242  ,Set/Clear Pending Bit 242" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND241  ,Set/Clear Pending Bit 241" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240  ,Set/Clear Pending Bit 240" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND239  ,Set/Clear Pending Bit 239" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND238  ,Set/Clear Pending Bit 238" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237  ,Set/Clear Pending Bit 237" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND236  ,Set/Clear Pending Bit 236" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND235  ,Set/Clear Pending Bit 235" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234  ,Set/Clear Pending Bit 234" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND233  ,Set/Clear Pending Bit 233" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND232  ,Set/Clear Pending Bit 232" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231  ,Set/Clear Pending Bit 231" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND230  ,Set/Clear Pending Bit 230" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND229  ,Set/Clear Pending Bit 229" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228  ,Set/Clear Pending Bit 228" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND227  ,Set/Clear Pending Bit 227" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND226  ,Set/Clear Pending Bit 226" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225  ,Set/Clear Pending Bit 225" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND224  ,Set/Clear Pending Bit 224" "Not pending,Pending"
else
rgroup.long 0x021C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x08)
group.long 0x0220++0x03
line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287  ,Set/Clear Pending Bit 287" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND286  ,Set/Clear Pending Bit 286" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND285  ,Set/Clear Pending Bit 285" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284  ,Set/Clear Pending Bit 284" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND283  ,Set/Clear Pending Bit 283" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND282  ,Set/Clear Pending Bit 282" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281  ,Set/Clear Pending Bit 281" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND280  ,Set/Clear Pending Bit 280" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND279  ,Set/Clear Pending Bit 279" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278  ,Set/Clear Pending Bit 278" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND277  ,Set/Clear Pending Bit 277" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND276  ,Set/Clear Pending Bit 276" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275  ,Set/Clear Pending Bit 275" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND274  ,Set/Clear Pending Bit 274" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND273  ,Set/Clear Pending Bit 273" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272  ,Set/Clear Pending Bit 272" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND271  ,Set/Clear Pending Bit 271" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND270  ,Set/Clear Pending Bit 270" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269  ,Set/Clear Pending Bit 269" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND268  ,Set/Clear Pending Bit 268" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND267  ,Set/Clear Pending Bit 267" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266  ,Set/Clear Pending Bit 266" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND265  ,Set/Clear Pending Bit 265" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND264  ,Set/Clear Pending Bit 264" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263  ,Set/Clear Pending Bit 263" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND262  ,Set/Clear Pending Bit 262" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND261  ,Set/Clear Pending Bit 261" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260  ,Set/Clear Pending Bit 260" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND259  ,Set/Clear Pending Bit 259" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND258  ,Set/Clear Pending Bit 258" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257  ,Set/Clear Pending Bit 257" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND256  ,Set/Clear Pending Bit 256" "Not pending,Pending"
else
rgroup.long 0x0220++0x03
line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x09)
group.long 0x0224++0x03
line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319  ,Set/Clear Pending Bit 319" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND318  ,Set/Clear Pending Bit 318" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND317  ,Set/Clear Pending Bit 317" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316  ,Set/Clear Pending Bit 316" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND315  ,Set/Clear Pending Bit 315" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND314  ,Set/Clear Pending Bit 314" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313  ,Set/Clear Pending Bit 313" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND312  ,Set/Clear Pending Bit 312" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND311  ,Set/Clear Pending Bit 311" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310  ,Set/Clear Pending Bit 310" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND309  ,Set/Clear Pending Bit 309" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND308  ,Set/Clear Pending Bit 308" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307  ,Set/Clear Pending Bit 307" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND306  ,Set/Clear Pending Bit 306" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND305  ,Set/Clear Pending Bit 305" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304  ,Set/Clear Pending Bit 304" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND303  ,Set/Clear Pending Bit 303" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND302  ,Set/Clear Pending Bit 302" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301  ,Set/Clear Pending Bit 301" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND300  ,Set/Clear Pending Bit 300" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND299  ,Set/Clear Pending Bit 299" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298  ,Set/Clear Pending Bit 298" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND297  ,Set/Clear Pending Bit 297" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND296  ,Set/Clear Pending Bit 296" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295  ,Set/Clear Pending Bit 295" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND294  ,Set/Clear Pending Bit 294" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND293  ,Set/Clear Pending Bit 293" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292  ,Set/Clear Pending Bit 292" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND291  ,Set/Clear Pending Bit 291" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND290  ,Set/Clear Pending Bit 290" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289  ,Set/Clear Pending Bit 289" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND288  ,Set/Clear Pending Bit 288" "Not pending,Pending"
else
rgroup.long 0x0224++0x03
line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0A)
group.long 0x0228++0x03
line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351  ,Set/Clear Pending Bit 351" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND350  ,Set/Clear Pending Bit 350" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND349  ,Set/Clear Pending Bit 349" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348  ,Set/Clear Pending Bit 348" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND347  ,Set/Clear Pending Bit 347" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND346  ,Set/Clear Pending Bit 346" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345  ,Set/Clear Pending Bit 345" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND344  ,Set/Clear Pending Bit 344" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND343  ,Set/Clear Pending Bit 343" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342  ,Set/Clear Pending Bit 342" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND341  ,Set/Clear Pending Bit 341" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND340  ,Set/Clear Pending Bit 340" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339  ,Set/Clear Pending Bit 339" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND338  ,Set/Clear Pending Bit 338" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND337  ,Set/Clear Pending Bit 337" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336  ,Set/Clear Pending Bit 336" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND335  ,Set/Clear Pending Bit 335" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND334  ,Set/Clear Pending Bit 334" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333  ,Set/Clear Pending Bit 333" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND332  ,Set/Clear Pending Bit 332" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND331  ,Set/Clear Pending Bit 331" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330  ,Set/Clear Pending Bit 330" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND329  ,Set/Clear Pending Bit 329" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND328  ,Set/Clear Pending Bit 328" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327  ,Set/Clear Pending Bit 327" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND326  ,Set/Clear Pending Bit 326" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND325  ,Set/Clear Pending Bit 325" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324  ,Set/Clear Pending Bit 324" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND323  ,Set/Clear Pending Bit 323" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND322  ,Set/Clear Pending Bit 322" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321  ,Set/Clear Pending Bit 321" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND320  ,Set/Clear Pending Bit 320" "Not pending,Pending"
else
rgroup.long 0x0228++0x03
line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0B)
group.long 0x022C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383  ,Set/Clear Pending Bit 383" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND382  ,Set/Clear Pending Bit 382" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND381  ,Set/Clear Pending Bit 381" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380  ,Set/Clear Pending Bit 380" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND379  ,Set/Clear Pending Bit 379" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND378  ,Set/Clear Pending Bit 378" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377  ,Set/Clear Pending Bit 377" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND376  ,Set/Clear Pending Bit 376" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND375  ,Set/Clear Pending Bit 375" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374  ,Set/Clear Pending Bit 374" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND373  ,Set/Clear Pending Bit 373" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND372  ,Set/Clear Pending Bit 372" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371  ,Set/Clear Pending Bit 371" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND370  ,Set/Clear Pending Bit 370" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND369  ,Set/Clear Pending Bit 369" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368  ,Set/Clear Pending Bit 368" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND367  ,Set/Clear Pending Bit 367" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND366  ,Set/Clear Pending Bit 366" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365  ,Set/Clear Pending Bit 365" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND364  ,Set/Clear Pending Bit 364" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND363  ,Set/Clear Pending Bit 363" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362  ,Set/Clear Pending Bit 362" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND361  ,Set/Clear Pending Bit 361" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND360  ,Set/Clear Pending Bit 360" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359  ,Set/Clear Pending Bit 359" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND358  ,Set/Clear Pending Bit 358" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND357  ,Set/Clear Pending Bit 357" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356  ,Set/Clear Pending Bit 356" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND355  ,Set/Clear Pending Bit 355" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND354  ,Set/Clear Pending Bit 354" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353  ,Set/Clear Pending Bit 353" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND352  ,Set/Clear Pending Bit 352" "Not pending,Pending"
else
rgroup.long 0x022C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0C)
group.long 0x0230++0x03
line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415  ,Set/Clear Pending Bit 415" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND414  ,Set/Clear Pending Bit 414" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND413  ,Set/Clear Pending Bit 413" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412  ,Set/Clear Pending Bit 412" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND411  ,Set/Clear Pending Bit 411" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND410  ,Set/Clear Pending Bit 410" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409  ,Set/Clear Pending Bit 409" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND408  ,Set/Clear Pending Bit 408" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND407  ,Set/Clear Pending Bit 407" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406  ,Set/Clear Pending Bit 406" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND405  ,Set/Clear Pending Bit 405" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND404  ,Set/Clear Pending Bit 404" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403  ,Set/Clear Pending Bit 403" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND402  ,Set/Clear Pending Bit 402" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND401  ,Set/Clear Pending Bit 401" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400  ,Set/Clear Pending Bit 400" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND399  ,Set/Clear Pending Bit 399" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND398  ,Set/Clear Pending Bit 398" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397  ,Set/Clear Pending Bit 397" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND396  ,Set/Clear Pending Bit 396" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND395  ,Set/Clear Pending Bit 395" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394  ,Set/Clear Pending Bit 394" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND393  ,Set/Clear Pending Bit 393" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND392  ,Set/Clear Pending Bit 392" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391  ,Set/Clear Pending Bit 391" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND390  ,Set/Clear Pending Bit 390" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND389  ,Set/Clear Pending Bit 389" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388  ,Set/Clear Pending Bit 388" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND387  ,Set/Clear Pending Bit 387" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND386  ,Set/Clear Pending Bit 386" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385  ,Set/Clear Pending Bit 385" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND384  ,Set/Clear Pending Bit 384" "Not pending,Pending"
else
rgroup.long 0x0230++0x03
line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0D)
group.long 0x0234++0x03
line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447  ,Set/Clear Pending Bit 447" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND446  ,Set/Clear Pending Bit 446" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND445  ,Set/Clear Pending Bit 445" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444  ,Set/Clear Pending Bit 444" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND443  ,Set/Clear Pending Bit 443" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND442  ,Set/Clear Pending Bit 442" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441  ,Set/Clear Pending Bit 441" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND440  ,Set/Clear Pending Bit 440" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND439  ,Set/Clear Pending Bit 439" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438  ,Set/Clear Pending Bit 438" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND437  ,Set/Clear Pending Bit 437" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND436  ,Set/Clear Pending Bit 436" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435  ,Set/Clear Pending Bit 435" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND434  ,Set/Clear Pending Bit 434" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND433  ,Set/Clear Pending Bit 433" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432  ,Set/Clear Pending Bit 432" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND431  ,Set/Clear Pending Bit 431" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND430  ,Set/Clear Pending Bit 430" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429  ,Set/Clear Pending Bit 429" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND428  ,Set/Clear Pending Bit 428" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND427  ,Set/Clear Pending Bit 427" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426  ,Set/Clear Pending Bit 426" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND425  ,Set/Clear Pending Bit 425" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND424  ,Set/Clear Pending Bit 424" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423  ,Set/Clear Pending Bit 423" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND422  ,Set/Clear Pending Bit 422" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND421  ,Set/Clear Pending Bit 421" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420  ,Set/Clear Pending Bit 420" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND419  ,Set/Clear Pending Bit 419" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND418  ,Set/Clear Pending Bit 418" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417  ,Set/Clear Pending Bit 417" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND416  ,Set/Clear Pending Bit 416" "Not pending,Pending"
else
rgroup.long 0x0234++0x03
line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0E)
group.long 0x0238++0x03
line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479  ,Set/Clear Pending Bit 479" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND478  ,Set/Clear Pending Bit 478" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND477  ,Set/Clear Pending Bit 477" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476  ,Set/Clear Pending Bit 476" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND475  ,Set/Clear Pending Bit 475" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND474  ,Set/Clear Pending Bit 474" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473  ,Set/Clear Pending Bit 473" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND472  ,Set/Clear Pending Bit 472" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND471  ,Set/Clear Pending Bit 471" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470  ,Set/Clear Pending Bit 470" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND469  ,Set/Clear Pending Bit 469" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND468  ,Set/Clear Pending Bit 468" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467  ,Set/Clear Pending Bit 467" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND466  ,Set/Clear Pending Bit 466" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND465  ,Set/Clear Pending Bit 465" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464  ,Set/Clear Pending Bit 464" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND463  ,Set/Clear Pending Bit 463" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND462  ,Set/Clear Pending Bit 462" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461  ,Set/Clear Pending Bit 461" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND460  ,Set/Clear Pending Bit 460" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND459  ,Set/Clear Pending Bit 459" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458  ,Set/Clear Pending Bit 458" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND457  ,Set/Clear Pending Bit 457" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND456  ,Set/Clear Pending Bit 456" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455  ,Set/Clear Pending Bit 455" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND454  ,Set/Clear Pending Bit 454" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND453  ,Set/Clear Pending Bit 453" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452  ,Set/Clear Pending Bit 452" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND451  ,Set/Clear Pending Bit 451" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND450  ,Set/Clear Pending Bit 450" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449  ,Set/Clear Pending Bit 449" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND448  ,Set/Clear Pending Bit 448" "Not pending,Pending"
else
rgroup.long 0x0238++0x03
line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0F)
group.long 0x023C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511  ,Set/Clear Pending Bit 511" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND510  ,Set/Clear Pending Bit 510" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND509  ,Set/Clear Pending Bit 509" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508  ,Set/Clear Pending Bit 508" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND507  ,Set/Clear Pending Bit 507" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND506  ,Set/Clear Pending Bit 506" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505  ,Set/Clear Pending Bit 505" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND504  ,Set/Clear Pending Bit 504" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND503  ,Set/Clear Pending Bit 503" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502  ,Set/Clear Pending Bit 502" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND501  ,Set/Clear Pending Bit 501" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND500  ,Set/Clear Pending Bit 500" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499  ,Set/Clear Pending Bit 499" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND498  ,Set/Clear Pending Bit 498" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND497  ,Set/Clear Pending Bit 497" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496  ,Set/Clear Pending Bit 496" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND495  ,Set/Clear Pending Bit 495" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND494  ,Set/Clear Pending Bit 494" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493  ,Set/Clear Pending Bit 493" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND492  ,Set/Clear Pending Bit 492" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND491  ,Set/Clear Pending Bit 491" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490  ,Set/Clear Pending Bit 490" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND489  ,Set/Clear Pending Bit 489" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND488  ,Set/Clear Pending Bit 488" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487  ,Set/Clear Pending Bit 487" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND486  ,Set/Clear Pending Bit 486" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND485  ,Set/Clear Pending Bit 485" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484  ,Set/Clear Pending Bit 484" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND483  ,Set/Clear Pending Bit 483" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND482  ,Set/Clear Pending Bit 482" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481  ,Set/Clear Pending Bit 481" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND480  ,Set/Clear Pending Bit 480" "Not pending,Pending"
else
rgroup.long 0x023C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x10)
group.long 0x0240++0x03
line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543  ,Set/Clear Pending Bit 543" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND542  ,Set/Clear Pending Bit 542" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND541  ,Set/Clear Pending Bit 541" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540  ,Set/Clear Pending Bit 540" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND539  ,Set/Clear Pending Bit 539" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND538  ,Set/Clear Pending Bit 538" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537  ,Set/Clear Pending Bit 537" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND536  ,Set/Clear Pending Bit 536" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND535  ,Set/Clear Pending Bit 535" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534  ,Set/Clear Pending Bit 534" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND533  ,Set/Clear Pending Bit 533" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND532  ,Set/Clear Pending Bit 532" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531  ,Set/Clear Pending Bit 531" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND530  ,Set/Clear Pending Bit 530" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND529  ,Set/Clear Pending Bit 529" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528  ,Set/Clear Pending Bit 528" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND527  ,Set/Clear Pending Bit 527" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND526  ,Set/Clear Pending Bit 526" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525  ,Set/Clear Pending Bit 525" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND524  ,Set/Clear Pending Bit 524" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND523  ,Set/Clear Pending Bit 523" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522  ,Set/Clear Pending Bit 522" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND521  ,Set/Clear Pending Bit 521" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND520  ,Set/Clear Pending Bit 520" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519  ,Set/Clear Pending Bit 519" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND518  ,Set/Clear Pending Bit 518" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND517  ,Set/Clear Pending Bit 517" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516  ,Set/Clear Pending Bit 516" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND515  ,Set/Clear Pending Bit 515" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND514  ,Set/Clear Pending Bit 514" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513  ,Set/Clear Pending Bit 513" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND512  ,Set/Clear Pending Bit 512" "Not pending,Pending"
else
rgroup.long 0x0240++0x03
line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x11)
group.long 0x0244++0x03
line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575  ,Set/Clear Pending Bit 575" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND574  ,Set/Clear Pending Bit 574" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND573  ,Set/Clear Pending Bit 573" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572  ,Set/Clear Pending Bit 572" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND571  ,Set/Clear Pending Bit 571" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND570  ,Set/Clear Pending Bit 570" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569  ,Set/Clear Pending Bit 569" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND568  ,Set/Clear Pending Bit 568" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND567  ,Set/Clear Pending Bit 567" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566  ,Set/Clear Pending Bit 566" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND565  ,Set/Clear Pending Bit 565" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND564  ,Set/Clear Pending Bit 564" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563  ,Set/Clear Pending Bit 563" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND562  ,Set/Clear Pending Bit 562" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND561  ,Set/Clear Pending Bit 561" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560  ,Set/Clear Pending Bit 560" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND559  ,Set/Clear Pending Bit 559" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND558  ,Set/Clear Pending Bit 558" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557  ,Set/Clear Pending Bit 557" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND556  ,Set/Clear Pending Bit 556" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND555  ,Set/Clear Pending Bit 555" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554  ,Set/Clear Pending Bit 554" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND553  ,Set/Clear Pending Bit 553" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND552  ,Set/Clear Pending Bit 552" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551  ,Set/Clear Pending Bit 551" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND550  ,Set/Clear Pending Bit 550" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND549  ,Set/Clear Pending Bit 549" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548  ,Set/Clear Pending Bit 548" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND547  ,Set/Clear Pending Bit 547" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND546  ,Set/Clear Pending Bit 546" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545  ,Set/Clear Pending Bit 545" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND544  ,Set/Clear Pending Bit 544" "Not pending,Pending"
else
rgroup.long 0x0244++0x03
line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x12)
group.long 0x0248++0x03
line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607  ,Set/Clear Pending Bit 607" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND606  ,Set/Clear Pending Bit 606" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND605  ,Set/Clear Pending Bit 605" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604  ,Set/Clear Pending Bit 604" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND603  ,Set/Clear Pending Bit 603" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND602  ,Set/Clear Pending Bit 602" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601  ,Set/Clear Pending Bit 601" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND600  ,Set/Clear Pending Bit 600" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND599  ,Set/Clear Pending Bit 599" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598  ,Set/Clear Pending Bit 598" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND597  ,Set/Clear Pending Bit 597" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND596  ,Set/Clear Pending Bit 596" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595  ,Set/Clear Pending Bit 595" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND594  ,Set/Clear Pending Bit 594" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND593  ,Set/Clear Pending Bit 593" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592  ,Set/Clear Pending Bit 592" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND591  ,Set/Clear Pending Bit 591" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND590  ,Set/Clear Pending Bit 590" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589  ,Set/Clear Pending Bit 589" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND588  ,Set/Clear Pending Bit 588" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND587  ,Set/Clear Pending Bit 587" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586  ,Set/Clear Pending Bit 586" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND585  ,Set/Clear Pending Bit 585" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND584  ,Set/Clear Pending Bit 584" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583  ,Set/Clear Pending Bit 583" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND582  ,Set/Clear Pending Bit 582" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND581  ,Set/Clear Pending Bit 581" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580  ,Set/Clear Pending Bit 580" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND579  ,Set/Clear Pending Bit 579" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND578  ,Set/Clear Pending Bit 578" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577  ,Set/Clear Pending Bit 577" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND576  ,Set/Clear Pending Bit 576" "Not pending,Pending"
else
rgroup.long 0x0248++0x03
line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x13)
group.long 0x024C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639  ,Set/Clear Pending Bit 639" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND638  ,Set/Clear Pending Bit 638" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND637  ,Set/Clear Pending Bit 637" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636  ,Set/Clear Pending Bit 636" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND635  ,Set/Clear Pending Bit 635" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND634  ,Set/Clear Pending Bit 634" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633  ,Set/Clear Pending Bit 633" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND632  ,Set/Clear Pending Bit 632" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND631  ,Set/Clear Pending Bit 631" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630  ,Set/Clear Pending Bit 630" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND629  ,Set/Clear Pending Bit 629" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND628  ,Set/Clear Pending Bit 628" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627  ,Set/Clear Pending Bit 627" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND626  ,Set/Clear Pending Bit 626" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND625  ,Set/Clear Pending Bit 625" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624  ,Set/Clear Pending Bit 624" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND623  ,Set/Clear Pending Bit 623" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND622  ,Set/Clear Pending Bit 622" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621  ,Set/Clear Pending Bit 621" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND620  ,Set/Clear Pending Bit 620" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND619  ,Set/Clear Pending Bit 619" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618  ,Set/Clear Pending Bit 618" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND617  ,Set/Clear Pending Bit 617" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND616  ,Set/Clear Pending Bit 616" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615  ,Set/Clear Pending Bit 615" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND614  ,Set/Clear Pending Bit 614" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND613  ,Set/Clear Pending Bit 613" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612  ,Set/Clear Pending Bit 612" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND611  ,Set/Clear Pending Bit 611" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND610  ,Set/Clear Pending Bit 610" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609  ,Set/Clear Pending Bit 609" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND608  ,Set/Clear Pending Bit 608" "Not pending,Pending"
else
rgroup.long 0x024C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x14)
group.long 0x0250++0x03
line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671  ,Set/Clear Pending Bit 671" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND670  ,Set/Clear Pending Bit 670" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND669  ,Set/Clear Pending Bit 669" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668  ,Set/Clear Pending Bit 668" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND667  ,Set/Clear Pending Bit 667" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND666  ,Set/Clear Pending Bit 666" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665  ,Set/Clear Pending Bit 665" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND664  ,Set/Clear Pending Bit 664" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND663  ,Set/Clear Pending Bit 663" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662  ,Set/Clear Pending Bit 662" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND661  ,Set/Clear Pending Bit 661" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND660  ,Set/Clear Pending Bit 660" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659  ,Set/Clear Pending Bit 659" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND658  ,Set/Clear Pending Bit 658" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND657  ,Set/Clear Pending Bit 657" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656  ,Set/Clear Pending Bit 656" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND655  ,Set/Clear Pending Bit 655" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND654  ,Set/Clear Pending Bit 654" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653  ,Set/Clear Pending Bit 653" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND652  ,Set/Clear Pending Bit 652" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND651  ,Set/Clear Pending Bit 651" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650  ,Set/Clear Pending Bit 650" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND649  ,Set/Clear Pending Bit 649" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND648  ,Set/Clear Pending Bit 648" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647  ,Set/Clear Pending Bit 647" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND646  ,Set/Clear Pending Bit 646" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND645  ,Set/Clear Pending Bit 645" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644  ,Set/Clear Pending Bit 644" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND643  ,Set/Clear Pending Bit 643" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND642  ,Set/Clear Pending Bit 642" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641  ,Set/Clear Pending Bit 641" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND640  ,Set/Clear Pending Bit 640" "Not pending,Pending"
else
rgroup.long 0x0250++0x03
line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x15)
group.long 0x0254++0x03
line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703  ,Set/Clear Pending Bit 703" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND702  ,Set/Clear Pending Bit 702" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND701  ,Set/Clear Pending Bit 701" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700  ,Set/Clear Pending Bit 700" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND699  ,Set/Clear Pending Bit 699" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND698  ,Set/Clear Pending Bit 698" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697  ,Set/Clear Pending Bit 697" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND696  ,Set/Clear Pending Bit 696" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND695  ,Set/Clear Pending Bit 695" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694  ,Set/Clear Pending Bit 694" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND693  ,Set/Clear Pending Bit 693" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND692  ,Set/Clear Pending Bit 692" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691  ,Set/Clear Pending Bit 691" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND690  ,Set/Clear Pending Bit 690" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND689  ,Set/Clear Pending Bit 689" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688  ,Set/Clear Pending Bit 688" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND687  ,Set/Clear Pending Bit 687" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND686  ,Set/Clear Pending Bit 686" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685  ,Set/Clear Pending Bit 685" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND684  ,Set/Clear Pending Bit 684" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND683  ,Set/Clear Pending Bit 683" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682  ,Set/Clear Pending Bit 682" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND681  ,Set/Clear Pending Bit 681" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND680  ,Set/Clear Pending Bit 680" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679  ,Set/Clear Pending Bit 679" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND678  ,Set/Clear Pending Bit 678" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND677  ,Set/Clear Pending Bit 677" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676  ,Set/Clear Pending Bit 676" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND675  ,Set/Clear Pending Bit 675" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND674  ,Set/Clear Pending Bit 674" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673  ,Set/Clear Pending Bit 673" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND672  ,Set/Clear Pending Bit 672" "Not pending,Pending"
else
rgroup.long 0x0254++0x03
line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x16)
group.long 0x0258++0x03
line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735  ,Set/Clear Pending Bit 735" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND734  ,Set/Clear Pending Bit 734" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND733  ,Set/Clear Pending Bit 733" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732  ,Set/Clear Pending Bit 732" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND731  ,Set/Clear Pending Bit 731" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND730  ,Set/Clear Pending Bit 730" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729  ,Set/Clear Pending Bit 729" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND728  ,Set/Clear Pending Bit 728" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND727  ,Set/Clear Pending Bit 727" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726  ,Set/Clear Pending Bit 726" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND725  ,Set/Clear Pending Bit 725" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND724  ,Set/Clear Pending Bit 724" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723  ,Set/Clear Pending Bit 723" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND722  ,Set/Clear Pending Bit 722" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND721  ,Set/Clear Pending Bit 721" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720  ,Set/Clear Pending Bit 720" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND719  ,Set/Clear Pending Bit 719" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND718  ,Set/Clear Pending Bit 718" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717  ,Set/Clear Pending Bit 717" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND716  ,Set/Clear Pending Bit 716" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND715  ,Set/Clear Pending Bit 715" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714  ,Set/Clear Pending Bit 714" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND713  ,Set/Clear Pending Bit 713" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND712  ,Set/Clear Pending Bit 712" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711  ,Set/Clear Pending Bit 711" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND710  ,Set/Clear Pending Bit 710" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND709  ,Set/Clear Pending Bit 709" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708  ,Set/Clear Pending Bit 708" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND707  ,Set/Clear Pending Bit 707" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND706  ,Set/Clear Pending Bit 706" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705  ,Set/Clear Pending Bit 705" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND704  ,Set/Clear Pending Bit 704" "Not pending,Pending"
else
rgroup.long 0x0258++0x03
line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x17)
group.long 0x025C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767  ,Set/Clear Pending Bit 767" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND766  ,Set/Clear Pending Bit 766" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND765  ,Set/Clear Pending Bit 765" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764  ,Set/Clear Pending Bit 764" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND763  ,Set/Clear Pending Bit 763" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND762  ,Set/Clear Pending Bit 762" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761  ,Set/Clear Pending Bit 761" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND760  ,Set/Clear Pending Bit 760" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND759  ,Set/Clear Pending Bit 759" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758  ,Set/Clear Pending Bit 758" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND757  ,Set/Clear Pending Bit 757" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND756  ,Set/Clear Pending Bit 756" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755  ,Set/Clear Pending Bit 755" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND754  ,Set/Clear Pending Bit 754" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND753  ,Set/Clear Pending Bit 753" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752  ,Set/Clear Pending Bit 752" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND751  ,Set/Clear Pending Bit 751" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND750  ,Set/Clear Pending Bit 750" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749  ,Set/Clear Pending Bit 749" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND748  ,Set/Clear Pending Bit 748" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND747  ,Set/Clear Pending Bit 747" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746  ,Set/Clear Pending Bit 746" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND745  ,Set/Clear Pending Bit 745" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND744  ,Set/Clear Pending Bit 744" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743  ,Set/Clear Pending Bit 743" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND742  ,Set/Clear Pending Bit 742" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND741  ,Set/Clear Pending Bit 741" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740  ,Set/Clear Pending Bit 740" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND739  ,Set/Clear Pending Bit 739" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND738  ,Set/Clear Pending Bit 738" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737  ,Set/Clear Pending Bit 737" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND736  ,Set/Clear Pending Bit 736" "Not pending,Pending"
else
rgroup.long 0x025C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x18)
group.long 0x0260++0x03
line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799  ,Set/Clear Pending Bit 799" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND798  ,Set/Clear Pending Bit 798" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND797  ,Set/Clear Pending Bit 797" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796  ,Set/Clear Pending Bit 796" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND795  ,Set/Clear Pending Bit 795" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND794  ,Set/Clear Pending Bit 794" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793  ,Set/Clear Pending Bit 793" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND792  ,Set/Clear Pending Bit 792" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND791  ,Set/Clear Pending Bit 791" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790  ,Set/Clear Pending Bit 790" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND789  ,Set/Clear Pending Bit 789" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND788  ,Set/Clear Pending Bit 788" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787  ,Set/Clear Pending Bit 787" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND786  ,Set/Clear Pending Bit 786" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND785  ,Set/Clear Pending Bit 785" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784  ,Set/Clear Pending Bit 784" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND783  ,Set/Clear Pending Bit 783" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND782  ,Set/Clear Pending Bit 782" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781  ,Set/Clear Pending Bit 781" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND780  ,Set/Clear Pending Bit 780" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND779  ,Set/Clear Pending Bit 779" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778  ,Set/Clear Pending Bit 778" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND777  ,Set/Clear Pending Bit 777" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND776  ,Set/Clear Pending Bit 776" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775  ,Set/Clear Pending Bit 775" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND774  ,Set/Clear Pending Bit 774" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND773  ,Set/Clear Pending Bit 773" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772  ,Set/Clear Pending Bit 772" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND771  ,Set/Clear Pending Bit 771" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND770  ,Set/Clear Pending Bit 770" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769  ,Set/Clear Pending Bit 769" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND768  ,Set/Clear Pending Bit 768" "Not pending,Pending"
else
rgroup.long 0x0260++0x03
line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x19)
group.long 0x0264++0x03
line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831  ,Set/Clear Pending Bit 831" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND830  ,Set/Clear Pending Bit 830" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND829  ,Set/Clear Pending Bit 829" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828  ,Set/Clear Pending Bit 828" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND827  ,Set/Clear Pending Bit 827" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND826  ,Set/Clear Pending Bit 826" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825  ,Set/Clear Pending Bit 825" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND824  ,Set/Clear Pending Bit 824" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND823  ,Set/Clear Pending Bit 823" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822  ,Set/Clear Pending Bit 822" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND821  ,Set/Clear Pending Bit 821" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND820  ,Set/Clear Pending Bit 820" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819  ,Set/Clear Pending Bit 819" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND818  ,Set/Clear Pending Bit 818" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND817  ,Set/Clear Pending Bit 817" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816  ,Set/Clear Pending Bit 816" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND815  ,Set/Clear Pending Bit 815" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND814  ,Set/Clear Pending Bit 814" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813  ,Set/Clear Pending Bit 813" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND812  ,Set/Clear Pending Bit 812" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND811  ,Set/Clear Pending Bit 811" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810  ,Set/Clear Pending Bit 810" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND809  ,Set/Clear Pending Bit 809" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND808  ,Set/Clear Pending Bit 808" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807  ,Set/Clear Pending Bit 807" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND806  ,Set/Clear Pending Bit 806" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND805  ,Set/Clear Pending Bit 805" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804  ,Set/Clear Pending Bit 804" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND803  ,Set/Clear Pending Bit 803" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND802  ,Set/Clear Pending Bit 802" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801  ,Set/Clear Pending Bit 801" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND800  ,Set/Clear Pending Bit 800" "Not pending,Pending"
else
rgroup.long 0x0264++0x03
line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1A)
group.long 0x0268++0x03
line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863  ,Set/Clear Pending Bit 863" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND862  ,Set/Clear Pending Bit 862" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND861  ,Set/Clear Pending Bit 861" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860  ,Set/Clear Pending Bit 860" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND859  ,Set/Clear Pending Bit 859" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND858  ,Set/Clear Pending Bit 858" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857  ,Set/Clear Pending Bit 857" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND856  ,Set/Clear Pending Bit 856" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND855  ,Set/Clear Pending Bit 855" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854  ,Set/Clear Pending Bit 854" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND853  ,Set/Clear Pending Bit 853" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND852  ,Set/Clear Pending Bit 852" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851  ,Set/Clear Pending Bit 851" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND850  ,Set/Clear Pending Bit 850" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND849  ,Set/Clear Pending Bit 849" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848  ,Set/Clear Pending Bit 848" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND847  ,Set/Clear Pending Bit 847" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND846  ,Set/Clear Pending Bit 846" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845  ,Set/Clear Pending Bit 845" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND844  ,Set/Clear Pending Bit 844" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND843  ,Set/Clear Pending Bit 843" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842  ,Set/Clear Pending Bit 842" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND841  ,Set/Clear Pending Bit 841" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND840  ,Set/Clear Pending Bit 840" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839  ,Set/Clear Pending Bit 839" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND838  ,Set/Clear Pending Bit 838" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND837  ,Set/Clear Pending Bit 837" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836  ,Set/Clear Pending Bit 836" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND835  ,Set/Clear Pending Bit 835" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND834  ,Set/Clear Pending Bit 834" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833  ,Set/Clear Pending Bit 833" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND832  ,Set/Clear Pending Bit 832" "Not pending,Pending"
else
rgroup.long 0x0268++0x03
line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1B)
group.long 0x026C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895  ,Set/Clear Pending Bit 895" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND894  ,Set/Clear Pending Bit 894" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND893  ,Set/Clear Pending Bit 893" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892  ,Set/Clear Pending Bit 892" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND891  ,Set/Clear Pending Bit 891" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND890  ,Set/Clear Pending Bit 890" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889  ,Set/Clear Pending Bit 889" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND888  ,Set/Clear Pending Bit 888" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND887  ,Set/Clear Pending Bit 887" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886  ,Set/Clear Pending Bit 886" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND885  ,Set/Clear Pending Bit 885" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND884  ,Set/Clear Pending Bit 884" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883  ,Set/Clear Pending Bit 883" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND882  ,Set/Clear Pending Bit 882" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND881  ,Set/Clear Pending Bit 881" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880  ,Set/Clear Pending Bit 880" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND879  ,Set/Clear Pending Bit 879" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND878  ,Set/Clear Pending Bit 878" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877  ,Set/Clear Pending Bit 877" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND876  ,Set/Clear Pending Bit 876" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND875  ,Set/Clear Pending Bit 875" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874  ,Set/Clear Pending Bit 874" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND873  ,Set/Clear Pending Bit 873" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND872  ,Set/Clear Pending Bit 872" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871  ,Set/Clear Pending Bit 871" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND870  ,Set/Clear Pending Bit 870" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND869  ,Set/Clear Pending Bit 869" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868  ,Set/Clear Pending Bit 868" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND867  ,Set/Clear Pending Bit 867" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND866  ,Set/Clear Pending Bit 866" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865  ,Set/Clear Pending Bit 865" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND864  ,Set/Clear Pending Bit 864" "Not pending,Pending"
else
rgroup.long 0x026C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1C)
group.long 0x0270++0x03
line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927  ,Set/Clear Pending Bit 927" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND926  ,Set/Clear Pending Bit 926" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND925  ,Set/Clear Pending Bit 925" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924  ,Set/Clear Pending Bit 924" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND923  ,Set/Clear Pending Bit 923" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND922  ,Set/Clear Pending Bit 922" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921  ,Set/Clear Pending Bit 921" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND920  ,Set/Clear Pending Bit 920" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND919  ,Set/Clear Pending Bit 919" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918  ,Set/Clear Pending Bit 918" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND917  ,Set/Clear Pending Bit 917" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND916  ,Set/Clear Pending Bit 916" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915  ,Set/Clear Pending Bit 915" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND914  ,Set/Clear Pending Bit 914" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND913  ,Set/Clear Pending Bit 913" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912  ,Set/Clear Pending Bit 912" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND911  ,Set/Clear Pending Bit 911" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND910  ,Set/Clear Pending Bit 910" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909  ,Set/Clear Pending Bit 909" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND908  ,Set/Clear Pending Bit 908" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND907  ,Set/Clear Pending Bit 907" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906  ,Set/Clear Pending Bit 906" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND905  ,Set/Clear Pending Bit 905" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND904  ,Set/Clear Pending Bit 904" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903  ,Set/Clear Pending Bit 903" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND902  ,Set/Clear Pending Bit 902" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND901  ,Set/Clear Pending Bit 901" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900  ,Set/Clear Pending Bit 900" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND899  ,Set/Clear Pending Bit 899" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND898  ,Set/Clear Pending Bit 898" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897  ,Set/Clear Pending Bit 897" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND896  ,Set/Clear Pending Bit 896" "Not pending,Pending"
else
rgroup.long 0x0270++0x03
line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1D)
group.long 0x0274++0x03
line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959  ,Set/Clear Pending Bit 959" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND958  ,Set/Clear Pending Bit 958" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND957  ,Set/Clear Pending Bit 957" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956  ,Set/Clear Pending Bit 956" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND955  ,Set/Clear Pending Bit 955" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND954  ,Set/Clear Pending Bit 954" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953  ,Set/Clear Pending Bit 953" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND952  ,Set/Clear Pending Bit 952" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND951  ,Set/Clear Pending Bit 951" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950  ,Set/Clear Pending Bit 950" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND949  ,Set/Clear Pending Bit 949" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND948  ,Set/Clear Pending Bit 948" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947  ,Set/Clear Pending Bit 947" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND946  ,Set/Clear Pending Bit 946" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND945  ,Set/Clear Pending Bit 945" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944  ,Set/Clear Pending Bit 944" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND943  ,Set/Clear Pending Bit 943" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND942  ,Set/Clear Pending Bit 942" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941  ,Set/Clear Pending Bit 941" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND940  ,Set/Clear Pending Bit 940" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND939  ,Set/Clear Pending Bit 939" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938  ,Set/Clear Pending Bit 938" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND937  ,Set/Clear Pending Bit 937" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND936  ,Set/Clear Pending Bit 936" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935  ,Set/Clear Pending Bit 935" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND934  ,Set/Clear Pending Bit 934" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND933  ,Set/Clear Pending Bit 933" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932  ,Set/Clear Pending Bit 932" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND931  ,Set/Clear Pending Bit 931" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND930  ,Set/Clear Pending Bit 930" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929  ,Set/Clear Pending Bit 929" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND928  ,Set/Clear Pending Bit 928" "Not pending,Pending"
else
rgroup.long 0x0274++0x03
line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1E)
group.long 0x0278++0x03
line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991  ,Set/Clear Pending Bit 991" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND990  ,Set/Clear Pending Bit 990" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND989  ,Set/Clear Pending Bit 989" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988  ,Set/Clear Pending Bit 988" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND987  ,Set/Clear Pending Bit 987" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND986  ,Set/Clear Pending Bit 986" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985  ,Set/Clear Pending Bit 985" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND984  ,Set/Clear Pending Bit 984" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND983  ,Set/Clear Pending Bit 983" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982  ,Set/Clear Pending Bit 982" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND981  ,Set/Clear Pending Bit 981" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND980  ,Set/Clear Pending Bit 980" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979  ,Set/Clear Pending Bit 979" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND978  ,Set/Clear Pending Bit 978" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND977  ,Set/Clear Pending Bit 977" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976  ,Set/Clear Pending Bit 976" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND975  ,Set/Clear Pending Bit 975" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND974  ,Set/Clear Pending Bit 974" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973  ,Set/Clear Pending Bit 973" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND972  ,Set/Clear Pending Bit 972" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND971  ,Set/Clear Pending Bit 971" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970  ,Set/Clear Pending Bit 970" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND969  ,Set/Clear Pending Bit 969" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND968  ,Set/Clear Pending Bit 968" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967  ,Set/Clear Pending Bit 967" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND966  ,Set/Clear Pending Bit 966" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND965  ,Set/Clear Pending Bit 965" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964  ,Set/Clear Pending Bit 964" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND963  ,Set/Clear Pending Bit 963" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND962  ,Set/Clear Pending Bit 962" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961  ,Set/Clear Pending Bit 961" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND960  ,Set/Clear Pending Bit 960" "Not pending,Pending"
else
rgroup.long 0x0278++0x03
line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)==0x1F)
group.long 0x027C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND1019 ,Set/Clear Pending Bit 1019" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND1018 ,Set/Clear Pending Bit 1018" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND1017 ,Set/Clear Pending Bit 1017" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND1016 ,Set/Clear Pending Bit 1016" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND1015 ,Set/Clear Pending Bit 1015" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND1014 ,Set/Clear Pending Bit 1014" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND1013 ,Set/Clear Pending Bit 1013" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND1012 ,Set/Clear Pending Bit 1012" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND1011 ,Set/Clear Pending Bit 1011" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND1010 ,Set/Clear Pending Bit 1010" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND1009 ,Set/Clear Pending Bit 1009" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND1008 ,Set/Clear Pending Bit 1008" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND1007 ,Set/Clear Pending Bit 1007" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND1006 ,Set/Clear Pending Bit 1006" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND1005 ,Set/Clear Pending Bit 1005" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND1004 ,Set/Clear Pending Bit 1004" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND1003 ,Set/Clear Pending Bit 1003" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND1002 ,Set/Clear Pending Bit 1002" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND1001 ,Set/Clear Pending Bit 1001" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND1000 ,Set/Clear Pending Bit 1000" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND999  ,Set/Clear Pending Bit 999" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND998  ,Set/Clear Pending Bit 998" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND997  ,Set/Clear Pending Bit 997" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND996  ,Set/Clear Pending Bit 996" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND995  ,Set/Clear Pending Bit 995" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND994  ,Set/Clear Pending Bit 994" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND993  ,Set/Clear Pending Bit 993" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND992  ,Set/Clear Pending Bit 992" "Not pending,Pending"
else
rgroup.long 0x027C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
tree.end
width 24.
tree "Set/Clear Active Registers"
if (((per.l(ad:0xFFFC1000+0x08))&0xFF000000)==(0x0000000||0x1000000))
rgroup.long 0x0300++0x03
line.long 0x0 "GICD_ICDABR0,Active Status Register 0"
bitfld.long 0x00 31. " ASB31   ,Active Status Bit 31" "Not active,Active"
bitfld.long 0x00 30. "  ASB30   ,Active Status Bit 30" "Not active,Active"
bitfld.long 0x00 29. "  ASB29   ,Active Status Bit 29" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB28   ,Active Status Bit 28" "Not active,Active"
bitfld.long 0x00 27. "  ASB27   ,Active Status Bit 27" "Not active,Active"
bitfld.long 0x00 26. "  ASB26   ,Active Status Bit 26" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB25   ,Active Status Bit 25" "Not active,Active"
bitfld.long 0x00 24. "  ASB24   ,Active Status Bit 24" "Not active,Active"
bitfld.long 0x00 23. "  ASB23   ,Active Status Bit 23" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB22   ,Active Status Bit 22" "Not active,Active"
bitfld.long 0x00 21. "  ASB21   ,Active Status Bit 21" "Not active,Active"
bitfld.long 0x00 20. "  ASB20   ,Active Status Bit 20" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB19   ,Active Status Bit 19" "Not active,Active"
bitfld.long 0x00 18. "  ASB18   ,Active Status Bit 18" "Not active,Active"
bitfld.long 0x00 17. "  ASB17   ,Active Status Bit 17" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB16   ,Active Status Bit 16" "Not active,Active"
bitfld.long 0x00 15. "  ASB15   ,Active Status Bit 15" "Not active,Active"
bitfld.long 0x00 14. "  ASB14   ,Active Status Bit 14" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB13   ,Active Status Bit 13" "Not active,Active"
bitfld.long 0x00 12. "  ASB12   ,Active Status Bit 12" "Not active,Active"
bitfld.long 0x00 11. "  ASB11   ,Active Status Bit 11" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB10   ,Active Status Bit 10" "Not active,Active"
bitfld.long 0x00 9. "  ASB9    ,Active Status Bit 9" "Not active,Active"
bitfld.long 0x00 8. "  ASB8    ,Active Status Bit 8" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB7    ,Active Status Bit 7" "Not active,Active"
bitfld.long 0x00 6. "  ASB6    ,Active Status Bit 6" "Not active,Active"
bitfld.long 0x00 5. "  ASB5    ,Active Status Bit 5" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB4    ,Active Status Bit 4" "Not active,Active"
bitfld.long 0x00 3. "  ASB3    ,Active Status Bit 3" "Not active,Active"
bitfld.long 0x00 2. "  ASB2    ,Active Status Bit 2" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB1    ,Active Status Bit 1" "Not active,Active"
bitfld.long 0x00 0. "  ASB0    ,Active Status Bit 0" "Not active,Active"
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x01)
rgroup.long 0x0304++0x03
line.long 0x0 "GICD_ICDABR1,Active Status Register 1"
bitfld.long 0x00 31. " ASB63   ,Active Status Bit 63" "Not active,Active"
bitfld.long 0x00 30. "  ASB62   ,Active Status Bit 62" "Not active,Active"
bitfld.long 0x00 29. "  ASB61   ,Active Status Bit 61" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB60   ,Active Status Bit 60" "Not active,Active"
bitfld.long 0x00 27. "  ASB59   ,Active Status Bit 59" "Not active,Active"
bitfld.long 0x00 26. "  ASB58   ,Active Status Bit 58" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB57   ,Active Status Bit 57" "Not active,Active"
bitfld.long 0x00 24. "  ASB56   ,Active Status Bit 56" "Not active,Active"
bitfld.long 0x00 23. "  ASB55   ,Active Status Bit 55" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB54   ,Active Status Bit 54" "Not active,Active"
bitfld.long 0x00 21. "  ASB53   ,Active Status Bit 53" "Not active,Active"
bitfld.long 0x00 20. "  ASB52   ,Active Status Bit 52" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB51   ,Active Status Bit 51" "Not active,Active"
bitfld.long 0x00 18. "  ASB50   ,Active Status Bit 50" "Not active,Active"
bitfld.long 0x00 17. "  ASB49   ,Active Status Bit 49" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB48   ,Active Status Bit 48" "Not active,Active"
bitfld.long 0x00 15. "  ASB47   ,Active Status Bit 47" "Not active,Active"
bitfld.long 0x00 14. "  ASB46   ,Active Status Bit 46" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB45   ,Active Status Bit 45" "Not active,Active"
bitfld.long 0x00 12. "  ASB44   ,Active Status Bit 44" "Not active,Active"
bitfld.long 0x00 11. "  ASB43   ,Active Status Bit 43" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB42   ,Active Status Bit 42" "Not active,Active"
bitfld.long 0x00 9. "  ASB41   ,Active Status Bit 41" "Not active,Active"
bitfld.long 0x00 8. "  ASB40   ,Active Status Bit 40" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB39   ,Active Status Bit 39" "Not active,Active"
bitfld.long 0x00 6. "  ASB38   ,Active Status Bit 38" "Not active,Active"
bitfld.long 0x00 5. "  ASB37   ,Active Status Bit 37" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB36   ,Active Status Bit 36" "Not active,Active"
bitfld.long 0x00 3. "  ASB35   ,Active Status Bit 35" "Not active,Active"
bitfld.long 0x00 2. "  ASB34   ,Active Status Bit 34" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB33   ,Active Status Bit 33" "Not active,Active"
bitfld.long 0x00 0. "  ASB32   ,Active Status Bit 32" "Not active,Active"
else
rgroup.long 0x0304++0x03
line.long 0x0 "GICD_ICDABR1,Active Status Register 1"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x02)
rgroup.long 0x0308++0x03
line.long 0x0 "GICD_ICDABR2,Active Status Register 2"
bitfld.long 0x00 31. " ASB95   ,Active Status Bit 95" "Not active,Active"
bitfld.long 0x00 30. "  ASB94   ,Active Status Bit 94" "Not active,Active"
bitfld.long 0x00 29. "  ASB93   ,Active Status Bit 93" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB92   ,Active Status Bit 92" "Not active,Active"
bitfld.long 0x00 27. "  ASB91   ,Active Status Bit 91" "Not active,Active"
bitfld.long 0x00 26. "  ASB90   ,Active Status Bit 90" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB89   ,Active Status Bit 89" "Not active,Active"
bitfld.long 0x00 24. "  ASB88   ,Active Status Bit 88" "Not active,Active"
bitfld.long 0x00 23. "  ASB87   ,Active Status Bit 87" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB86   ,Active Status Bit 86" "Not active,Active"
bitfld.long 0x00 21. "  ASB85   ,Active Status Bit 85" "Not active,Active"
bitfld.long 0x00 20. "  ASB84   ,Active Status Bit 84" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB83   ,Active Status Bit 83" "Not active,Active"
bitfld.long 0x00 18. "  ASB82   ,Active Status Bit 82" "Not active,Active"
bitfld.long 0x00 17. "  ASB81   ,Active Status Bit 81" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB80   ,Active Status Bit 80" "Not active,Active"
bitfld.long 0x00 15. "  ASB79   ,Active Status Bit 79" "Not active,Active"
bitfld.long 0x00 14. "  ASB78   ,Active Status Bit 78" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB77   ,Active Status Bit 77" "Not active,Active"
bitfld.long 0x00 12. "  ASB76   ,Active Status Bit 76" "Not active,Active"
bitfld.long 0x00 11. "  ASB75   ,Active Status Bit 75" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB74   ,Active Status Bit 74" "Not active,Active"
bitfld.long 0x00 9. "  ASB73   ,Active Status Bit 73" "Not active,Active"
bitfld.long 0x00 8. "  ASB72   ,Active Status Bit 72" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB71   ,Active Status Bit 71" "Not active,Active"
bitfld.long 0x00 6. "  ASB70   ,Active Status Bit 70" "Not active,Active"
bitfld.long 0x00 5. "  ASB69   ,Active Status Bit 69" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB68   ,Active Status Bit 68" "Not active,Active"
bitfld.long 0x00 3. "  ASB67   ,Active Status Bit 67" "Not active,Active"
bitfld.long 0x00 2. "  ASB66   ,Active Status Bit 66" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB65   ,Active Status Bit 65" "Not active,Active"
bitfld.long 0x00 0. "  ASB64   ,Active Status Bit 64" "Not active,Active"
else
rgroup.long 0x0308++0x03
line.long 0x0 "GICD_ICDABR2,Active Status Register 2"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x03)
rgroup.long 0x030C++0x03
line.long 0x0 "GICD_ICDABR3,Active Status Register 3"
bitfld.long 0x00 31. " ASB127  ,Active Status Bit 127" "Not active,Active"
bitfld.long 0x00 30. "  ASB126  ,Active Status Bit 126" "Not active,Active"
bitfld.long 0x00 29. "  ASB125  ,Active Status Bit 125" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB124  ,Active Status Bit 124" "Not active,Active"
bitfld.long 0x00 27. "  ASB123  ,Active Status Bit 123" "Not active,Active"
bitfld.long 0x00 26. "  ASB122  ,Active Status Bit 122" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB121  ,Active Status Bit 121" "Not active,Active"
bitfld.long 0x00 24. "  ASB120  ,Active Status Bit 120" "Not active,Active"
bitfld.long 0x00 23. "  ASB119  ,Active Status Bit 119" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB118  ,Active Status Bit 118" "Not active,Active"
bitfld.long 0x00 21. "  ASB117  ,Active Status Bit 117" "Not active,Active"
bitfld.long 0x00 20. "  ASB116  ,Active Status Bit 116" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB115  ,Active Status Bit 115" "Not active,Active"
bitfld.long 0x00 18. "  ASB114  ,Active Status Bit 114" "Not active,Active"
bitfld.long 0x00 17. "  ASB113  ,Active Status Bit 113" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB112  ,Active Status Bit 112" "Not active,Active"
bitfld.long 0x00 15. "  ASB111  ,Active Status Bit 111" "Not active,Active"
bitfld.long 0x00 14. "  ASB110  ,Active Status Bit 110" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB109  ,Active Status Bit 109" "Not active,Active"
bitfld.long 0x00 12. "  ASB108  ,Active Status Bit 108" "Not active,Active"
bitfld.long 0x00 11. "  ASB107  ,Active Status Bit 107" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB106  ,Active Status Bit 106" "Not active,Active"
bitfld.long 0x00 9. "  ASB105  ,Active Status Bit 105" "Not active,Active"
bitfld.long 0x00 8. "  ASB104  ,Active Status Bit 104" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB103  ,Active Status Bit 103" "Not active,Active"
bitfld.long 0x00 6. "  ASB102  ,Active Status Bit 102" "Not active,Active"
bitfld.long 0x00 5. "  ASB101  ,Active Status Bit 101" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB100  ,Active Status Bit 100" "Not active,Active"
bitfld.long 0x00 3. "  ASB99   ,Active Status Bit 99" "Not active,Active"
bitfld.long 0x00 2. "  ASB98   ,Active Status Bit 98" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB97   ,Active Status Bit 97" "Not active,Active"
bitfld.long 0x00 0. "  ASB96   ,Active Status Bit 96" "Not active,Active"
else
rgroup.long 0x030C++0x03
line.long 0x0 "GICD_ICDABR3,Active Status Register 3"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x04)
rgroup.long 0x0310++0x03
line.long 0x0 "GICD_ICDABR4,Active Status Register 4"
bitfld.long 0x00 31. " ASB159  ,Active Status Bit 159" "Not active,Active"
bitfld.long 0x00 30. "  ASB158  ,Active Status Bit 158" "Not active,Active"
bitfld.long 0x00 29. "  ASB157  ,Active Status Bit 157" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB156  ,Active Status Bit 156" "Not active,Active"
bitfld.long 0x00 27. "  ASB155  ,Active Status Bit 155" "Not active,Active"
bitfld.long 0x00 26. "  ASB154  ,Active Status Bit 154" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB153  ,Active Status Bit 153" "Not active,Active"
bitfld.long 0x00 24. "  ASB152  ,Active Status Bit 152" "Not active,Active"
bitfld.long 0x00 23. "  ASB151  ,Active Status Bit 151" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB150  ,Active Status Bit 150" "Not active,Active"
bitfld.long 0x00 21. "  ASB149  ,Active Status Bit 149" "Not active,Active"
bitfld.long 0x00 20. "  ASB148  ,Active Status Bit 148" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB147  ,Active Status Bit 147" "Not active,Active"
bitfld.long 0x00 18. "  ASB146  ,Active Status Bit 146" "Not active,Active"
bitfld.long 0x00 17. "  ASB145  ,Active Status Bit 145" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB144  ,Active Status Bit 144" "Not active,Active"
bitfld.long 0x00 15. "  ASB143  ,Active Status Bit 143" "Not active,Active"
bitfld.long 0x00 14. "  ASB142  ,Active Status Bit 142" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB141  ,Active Status Bit 141" "Not active,Active"
bitfld.long 0x00 12. "  ASB140  ,Active Status Bit 140" "Not active,Active"
bitfld.long 0x00 11. "  ASB139  ,Active Status Bit 139" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB138  ,Active Status Bit 138" "Not active,Active"
bitfld.long 0x00 9. "  ASB137  ,Active Status Bit 137" "Not active,Active"
bitfld.long 0x00 8. "  ASB136  ,Active Status Bit 136" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB135  ,Active Status Bit 135" "Not active,Active"
bitfld.long 0x00 6. "  ASB134  ,Active Status Bit 134" "Not active,Active"
bitfld.long 0x00 5. "  ASB133  ,Active Status Bit 133" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB132  ,Active Status Bit 132" "Not active,Active"
bitfld.long 0x00 3. "  ASB131  ,Active Status Bit 131" "Not active,Active"
bitfld.long 0x00 2. "  ASB130  ,Active Status Bit 130" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB129  ,Active Status Bit 129" "Not active,Active"
bitfld.long 0x00 0. "  ASB128  ,Active Status Bit 128" "Not active,Active"
else
rgroup.long 0x0310++0x03
line.long 0x0 "GICD_ICDABR4,Active Status Register 4"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x05)
rgroup.long 0x0314++0x03
line.long 0x0 "GICD_ICDABR5,Active Status Register 5"
bitfld.long 0x00 31. " ASB191  ,Active Status Bit 191" "Not active,Active"
bitfld.long 0x00 30. "  ASB190  ,Active Status Bit 190" "Not active,Active"
bitfld.long 0x00 29. "  ASB189  ,Active Status Bit 189" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB188  ,Active Status Bit 188" "Not active,Active"
bitfld.long 0x00 27. "  ASB187  ,Active Status Bit 187" "Not active,Active"
bitfld.long 0x00 26. "  ASB186  ,Active Status Bit 186" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB185  ,Active Status Bit 185" "Not active,Active"
bitfld.long 0x00 24. "  ASB184  ,Active Status Bit 184" "Not active,Active"
bitfld.long 0x00 23. "  ASB183  ,Active Status Bit 183" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB182  ,Active Status Bit 182" "Not active,Active"
bitfld.long 0x00 21. "  ASB181  ,Active Status Bit 181" "Not active,Active"
bitfld.long 0x00 20. "  ASB180  ,Active Status Bit 180" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB179  ,Active Status Bit 179" "Not active,Active"
bitfld.long 0x00 18. "  ASB178  ,Active Status Bit 178" "Not active,Active"
bitfld.long 0x00 17. "  ASB177  ,Active Status Bit 177" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB176  ,Active Status Bit 176" "Not active,Active"
bitfld.long 0x00 15. "  ASB175  ,Active Status Bit 175" "Not active,Active"
bitfld.long 0x00 14. "  ASB174  ,Active Status Bit 174" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB173  ,Active Status Bit 173" "Not active,Active"
bitfld.long 0x00 12. "  ASB172  ,Active Status Bit 172" "Not active,Active"
bitfld.long 0x00 11. "  ASB171  ,Active Status Bit 171" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB170  ,Active Status Bit 170" "Not active,Active"
bitfld.long 0x00 9. "  ASB169  ,Active Status Bit 169" "Not active,Active"
bitfld.long 0x00 8. "  ASB168  ,Active Status Bit 168" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB167  ,Active Status Bit 167" "Not active,Active"
bitfld.long 0x00 6. "  ASB166  ,Active Status Bit 166" "Not active,Active"
bitfld.long 0x00 5. "  ASB165  ,Active Status Bit 165" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB164  ,Active Status Bit 164" "Not active,Active"
bitfld.long 0x00 3. "  ASB163  ,Active Status Bit 163" "Not active,Active"
bitfld.long 0x00 2. "  ASB162  ,Active Status Bit 162" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB161  ,Active Status Bit 161" "Not active,Active"
bitfld.long 0x00 0. "  ASB160  ,Active Status Bit 160" "Not active,Active"
else
rgroup.long 0x0314++0x03
line.long 0x0 "GICD_ICDABR5,Active Status Register 5"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x06)
rgroup.long 0x0318++0x03
line.long 0x0 "GICD_ICDABR6,Active Status Register 6"
bitfld.long 0x00 31. " ASB223  ,Active Status Bit 223" "Not active,Active"
bitfld.long 0x00 30. "  ASB222  ,Active Status Bit 222" "Not active,Active"
bitfld.long 0x00 29. "  ASB221  ,Active Status Bit 221" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB220  ,Active Status Bit 220" "Not active,Active"
bitfld.long 0x00 27. "  ASB219  ,Active Status Bit 219" "Not active,Active"
bitfld.long 0x00 26. "  ASB218  ,Active Status Bit 218" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB217  ,Active Status Bit 217" "Not active,Active"
bitfld.long 0x00 24. "  ASB216  ,Active Status Bit 216" "Not active,Active"
bitfld.long 0x00 23. "  ASB215  ,Active Status Bit 215" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB214  ,Active Status Bit 214" "Not active,Active"
bitfld.long 0x00 21. "  ASB213  ,Active Status Bit 213" "Not active,Active"
bitfld.long 0x00 20. "  ASB212  ,Active Status Bit 212" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB211  ,Active Status Bit 211" "Not active,Active"
bitfld.long 0x00 18. "  ASB210  ,Active Status Bit 210" "Not active,Active"
bitfld.long 0x00 17. "  ASB209  ,Active Status Bit 209" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB208  ,Active Status Bit 208" "Not active,Active"
bitfld.long 0x00 15. "  ASB207  ,Active Status Bit 207" "Not active,Active"
bitfld.long 0x00 14. "  ASB206  ,Active Status Bit 206" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB205  ,Active Status Bit 205" "Not active,Active"
bitfld.long 0x00 12. "  ASB204  ,Active Status Bit 204" "Not active,Active"
bitfld.long 0x00 11. "  ASB203  ,Active Status Bit 203" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB202  ,Active Status Bit 202" "Not active,Active"
bitfld.long 0x00 9. "  ASB201  ,Active Status Bit 201" "Not active,Active"
bitfld.long 0x00 8. "  ASB200  ,Active Status Bit 200" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB199  ,Active Status Bit 199" "Not active,Active"
bitfld.long 0x00 6. "  ASB198  ,Active Status Bit 198" "Not active,Active"
bitfld.long 0x00 5. "  ASB197  ,Active Status Bit 197" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB196  ,Active Status Bit 196" "Not active,Active"
bitfld.long 0x00 3. "  ASB195  ,Active Status Bit 195" "Not active,Active"
bitfld.long 0x00 2. "  ASB194  ,Active Status Bit 194" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB193  ,Active Status Bit 193" "Not active,Active"
bitfld.long 0x00 0. "  ASB192  ,Active Status Bit 192" "Not active,Active"
else
rgroup.long 0x0318++0x03
line.long 0x0 "GICD_ICDABR6,Active Status Register 6"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x07)
rgroup.long 0x031C++0x03
line.long 0x0 "GICD_ICDABR7,Active Status Register 7"
bitfld.long 0x00 31. " ASB255  ,Active Status Bit 255" "Not active,Active"
bitfld.long 0x00 30. "  ASB254  ,Active Status Bit 254" "Not active,Active"
bitfld.long 0x00 29. "  ASB253  ,Active Status Bit 253" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB252  ,Active Status Bit 252" "Not active,Active"
bitfld.long 0x00 27. "  ASB251  ,Active Status Bit 251" "Not active,Active"
bitfld.long 0x00 26. "  ASB250  ,Active Status Bit 250" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB249  ,Active Status Bit 249" "Not active,Active"
bitfld.long 0x00 24. "  ASB248  ,Active Status Bit 248" "Not active,Active"
bitfld.long 0x00 23. "  ASB247  ,Active Status Bit 247" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB246  ,Active Status Bit 246" "Not active,Active"
bitfld.long 0x00 21. "  ASB245  ,Active Status Bit 245" "Not active,Active"
bitfld.long 0x00 20. "  ASB244  ,Active Status Bit 244" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB243  ,Active Status Bit 243" "Not active,Active"
bitfld.long 0x00 18. "  ASB242  ,Active Status Bit 242" "Not active,Active"
bitfld.long 0x00 17. "  ASB241  ,Active Status Bit 241" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB240  ,Active Status Bit 240" "Not active,Active"
bitfld.long 0x00 15. "  ASB239  ,Active Status Bit 239" "Not active,Active"
bitfld.long 0x00 14. "  ASB238  ,Active Status Bit 238" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB237  ,Active Status Bit 237" "Not active,Active"
bitfld.long 0x00 12. "  ASB236  ,Active Status Bit 236" "Not active,Active"
bitfld.long 0x00 11. "  ASB235  ,Active Status Bit 235" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB234  ,Active Status Bit 234" "Not active,Active"
bitfld.long 0x00 9. "  ASB233  ,Active Status Bit 233" "Not active,Active"
bitfld.long 0x00 8. "  ASB232  ,Active Status Bit 232" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB231  ,Active Status Bit 231" "Not active,Active"
bitfld.long 0x00 6. "  ASB230  ,Active Status Bit 230" "Not active,Active"
bitfld.long 0x00 5. "  ASB229  ,Active Status Bit 229" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB228  ,Active Status Bit 228" "Not active,Active"
bitfld.long 0x00 3. "  ASB227  ,Active Status Bit 227" "Not active,Active"
bitfld.long 0x00 2. "  ASB226  ,Active Status Bit 226" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB225  ,Active Status Bit 225" "Not active,Active"
bitfld.long 0x00 0. "  ASB224  ,Active Status Bit 224" "Not active,Active"
else
rgroup.long 0x031C++0x03
line.long 0x0 "GICD_ICDABR7,Active Status Register 7"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x08)
rgroup.long 0x0320++0x03
line.long 0x0 "GICD_ICDABR8,Active Status Register 8"
bitfld.long 0x00 31. " ASB287  ,Active Status Bit 287" "Not active,Active"
bitfld.long 0x00 30. "  ASB286  ,Active Status Bit 286" "Not active,Active"
bitfld.long 0x00 29. "  ASB285  ,Active Status Bit 285" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB284  ,Active Status Bit 284" "Not active,Active"
bitfld.long 0x00 27. "  ASB283  ,Active Status Bit 283" "Not active,Active"
bitfld.long 0x00 26. "  ASB282  ,Active Status Bit 282" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB281  ,Active Status Bit 281" "Not active,Active"
bitfld.long 0x00 24. "  ASB280  ,Active Status Bit 280" "Not active,Active"
bitfld.long 0x00 23. "  ASB279  ,Active Status Bit 279" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB278  ,Active Status Bit 278" "Not active,Active"
bitfld.long 0x00 21. "  ASB277  ,Active Status Bit 277" "Not active,Active"
bitfld.long 0x00 20. "  ASB276  ,Active Status Bit 276" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB275  ,Active Status Bit 275" "Not active,Active"
bitfld.long 0x00 18. "  ASB274  ,Active Status Bit 274" "Not active,Active"
bitfld.long 0x00 17. "  ASB273  ,Active Status Bit 273" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB272  ,Active Status Bit 272" "Not active,Active"
bitfld.long 0x00 15. "  ASB271  ,Active Status Bit 271" "Not active,Active"
bitfld.long 0x00 14. "  ASB270  ,Active Status Bit 270" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB269  ,Active Status Bit 269" "Not active,Active"
bitfld.long 0x00 12. "  ASB268  ,Active Status Bit 268" "Not active,Active"
bitfld.long 0x00 11. "  ASB267  ,Active Status Bit 267" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB266  ,Active Status Bit 266" "Not active,Active"
bitfld.long 0x00 9. "  ASB265  ,Active Status Bit 265" "Not active,Active"
bitfld.long 0x00 8. "  ASB264  ,Active Status Bit 264" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB263  ,Active Status Bit 263" "Not active,Active"
bitfld.long 0x00 6. "  ASB262  ,Active Status Bit 262" "Not active,Active"
bitfld.long 0x00 5. "  ASB261  ,Active Status Bit 261" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB260  ,Active Status Bit 260" "Not active,Active"
bitfld.long 0x00 3. "  ASB259  ,Active Status Bit 259" "Not active,Active"
bitfld.long 0x00 2. "  ASB258  ,Active Status Bit 258" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB257  ,Active Status Bit 257" "Not active,Active"
bitfld.long 0x00 0. "  ASB256  ,Active Status Bit 256" "Not active,Active"
else
rgroup.long 0x0320++0x03
line.long 0x0 "GICD_ICDABR8,Active Status Register 8"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x09)
rgroup.long 0x0324++0x03
line.long 0x0 "GICD_ICDABR9,Active Status Register 9"
bitfld.long 0x00 31. " ASB319  ,Active Status Bit 319" "Not active,Active"
bitfld.long 0x00 30. "  ASB318  ,Active Status Bit 318" "Not active,Active"
bitfld.long 0x00 29. "  ASB317  ,Active Status Bit 317" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB316  ,Active Status Bit 316" "Not active,Active"
bitfld.long 0x00 27. "  ASB315  ,Active Status Bit 315" "Not active,Active"
bitfld.long 0x00 26. "  ASB314  ,Active Status Bit 314" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB313  ,Active Status Bit 313" "Not active,Active"
bitfld.long 0x00 24. "  ASB312  ,Active Status Bit 312" "Not active,Active"
bitfld.long 0x00 23. "  ASB311  ,Active Status Bit 311" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB310  ,Active Status Bit 310" "Not active,Active"
bitfld.long 0x00 21. "  ASB309  ,Active Status Bit 309" "Not active,Active"
bitfld.long 0x00 20. "  ASB308  ,Active Status Bit 308" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB307  ,Active Status Bit 307" "Not active,Active"
bitfld.long 0x00 18. "  ASB306  ,Active Status Bit 306" "Not active,Active"
bitfld.long 0x00 17. "  ASB305  ,Active Status Bit 305" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB304  ,Active Status Bit 304" "Not active,Active"
bitfld.long 0x00 15. "  ASB303  ,Active Status Bit 303" "Not active,Active"
bitfld.long 0x00 14. "  ASB302  ,Active Status Bit 302" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB301  ,Active Status Bit 301" "Not active,Active"
bitfld.long 0x00 12. "  ASB300  ,Active Status Bit 300" "Not active,Active"
bitfld.long 0x00 11. "  ASB299  ,Active Status Bit 299" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB298  ,Active Status Bit 298" "Not active,Active"
bitfld.long 0x00 9. "  ASB297  ,Active Status Bit 297" "Not active,Active"
bitfld.long 0x00 8. "  ASB296  ,Active Status Bit 296" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB295  ,Active Status Bit 295" "Not active,Active"
bitfld.long 0x00 6. "  ASB294  ,Active Status Bit 294" "Not active,Active"
bitfld.long 0x00 5. "  ASB293  ,Active Status Bit 293" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB292  ,Active Status Bit 292" "Not active,Active"
bitfld.long 0x00 3. "  ASB291  ,Active Status Bit 291" "Not active,Active"
bitfld.long 0x00 2. "  ASB290  ,Active Status Bit 290" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB289  ,Active Status Bit 289" "Not active,Active"
bitfld.long 0x00 0. "  ASB288  ,Active Status Bit 288" "Not active,Active"
else
rgroup.long 0x0324++0x03
line.long 0x0 "GICD_ICDABR9,Active Status Register 9"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0A)
rgroup.long 0x0328++0x03
line.long 0x0 "GICD_ICDABR10,Active Status Register 10"
bitfld.long 0x00 31. " ASB351  ,Active Status Bit 351" "Not active,Active"
bitfld.long 0x00 30. "  ASB350  ,Active Status Bit 350" "Not active,Active"
bitfld.long 0x00 29. "  ASB349  ,Active Status Bit 349" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB348  ,Active Status Bit 348" "Not active,Active"
bitfld.long 0x00 27. "  ASB347  ,Active Status Bit 347" "Not active,Active"
bitfld.long 0x00 26. "  ASB346  ,Active Status Bit 346" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB345  ,Active Status Bit 345" "Not active,Active"
bitfld.long 0x00 24. "  ASB344  ,Active Status Bit 344" "Not active,Active"
bitfld.long 0x00 23. "  ASB343  ,Active Status Bit 343" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB342  ,Active Status Bit 342" "Not active,Active"
bitfld.long 0x00 21. "  ASB341  ,Active Status Bit 341" "Not active,Active"
bitfld.long 0x00 20. "  ASB340  ,Active Status Bit 340" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB339  ,Active Status Bit 339" "Not active,Active"
bitfld.long 0x00 18. "  ASB338  ,Active Status Bit 338" "Not active,Active"
bitfld.long 0x00 17. "  ASB337  ,Active Status Bit 337" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB336  ,Active Status Bit 336" "Not active,Active"
bitfld.long 0x00 15. "  ASB335  ,Active Status Bit 335" "Not active,Active"
bitfld.long 0x00 14. "  ASB334  ,Active Status Bit 334" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB333  ,Active Status Bit 333" "Not active,Active"
bitfld.long 0x00 12. "  ASB332  ,Active Status Bit 332" "Not active,Active"
bitfld.long 0x00 11. "  ASB331  ,Active Status Bit 331" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB330  ,Active Status Bit 330" "Not active,Active"
bitfld.long 0x00 9. "  ASB329  ,Active Status Bit 329" "Not active,Active"
bitfld.long 0x00 8. "  ASB328  ,Active Status Bit 328" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB327  ,Active Status Bit 327" "Not active,Active"
bitfld.long 0x00 6. "  ASB326  ,Active Status Bit 326" "Not active,Active"
bitfld.long 0x00 5. "  ASB325  ,Active Status Bit 325" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB324  ,Active Status Bit 324" "Not active,Active"
bitfld.long 0x00 3. "  ASB323  ,Active Status Bit 323" "Not active,Active"
bitfld.long 0x00 2. "  ASB322  ,Active Status Bit 322" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB321  ,Active Status Bit 321" "Not active,Active"
bitfld.long 0x00 0. "  ASB320  ,Active Status Bit 320" "Not active,Active"
else
rgroup.long 0x0328++0x03
line.long 0x0 "GICD_ICDABR10,Active Status Register 10"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0B)
rgroup.long 0x032C++0x03
line.long 0x0 "GICD_ICDABR11,Active Status Register 11"
bitfld.long 0x00 31. " ASB383  ,Active Status Bit 383" "Not active,Active"
bitfld.long 0x00 30. "  ASB382  ,Active Status Bit 382" "Not active,Active"
bitfld.long 0x00 29. "  ASB381  ,Active Status Bit 381" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB380  ,Active Status Bit 380" "Not active,Active"
bitfld.long 0x00 27. "  ASB379  ,Active Status Bit 379" "Not active,Active"
bitfld.long 0x00 26. "  ASB378  ,Active Status Bit 378" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB377  ,Active Status Bit 377" "Not active,Active"
bitfld.long 0x00 24. "  ASB376  ,Active Status Bit 376" "Not active,Active"
bitfld.long 0x00 23. "  ASB375  ,Active Status Bit 375" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB374  ,Active Status Bit 374" "Not active,Active"
bitfld.long 0x00 21. "  ASB373  ,Active Status Bit 373" "Not active,Active"
bitfld.long 0x00 20. "  ASB372  ,Active Status Bit 372" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB371  ,Active Status Bit 371" "Not active,Active"
bitfld.long 0x00 18. "  ASB370  ,Active Status Bit 370" "Not active,Active"
bitfld.long 0x00 17. "  ASB369  ,Active Status Bit 369" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB368  ,Active Status Bit 368" "Not active,Active"
bitfld.long 0x00 15. "  ASB367  ,Active Status Bit 367" "Not active,Active"
bitfld.long 0x00 14. "  ASB366  ,Active Status Bit 366" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB365  ,Active Status Bit 365" "Not active,Active"
bitfld.long 0x00 12. "  ASB364  ,Active Status Bit 364" "Not active,Active"
bitfld.long 0x00 11. "  ASB363  ,Active Status Bit 363" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB362  ,Active Status Bit 362" "Not active,Active"
bitfld.long 0x00 9. "  ASB361  ,Active Status Bit 361" "Not active,Active"
bitfld.long 0x00 8. "  ASB360  ,Active Status Bit 360" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB359  ,Active Status Bit 359" "Not active,Active"
bitfld.long 0x00 6. "  ASB358  ,Active Status Bit 358" "Not active,Active"
bitfld.long 0x00 5. "  ASB357  ,Active Status Bit 357" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB356  ,Active Status Bit 356" "Not active,Active"
bitfld.long 0x00 3. "  ASB355  ,Active Status Bit 355" "Not active,Active"
bitfld.long 0x00 2. "  ASB354  ,Active Status Bit 354" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB353  ,Active Status Bit 353" "Not active,Active"
bitfld.long 0x00 0. "  ASB352  ,Active Status Bit 352" "Not active,Active"
else
rgroup.long 0x032C++0x03
line.long 0x0 "GICD_ICDABR11,Active Status Register 11"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0C)
rgroup.long 0x0330++0x03
line.long 0x0 "GICD_ICDABR12,Active Status Register 12"
bitfld.long 0x00 31. " ASB415  ,Active Status Bit 415" "Not active,Active"
bitfld.long 0x00 30. "  ASB414  ,Active Status Bit 414" "Not active,Active"
bitfld.long 0x00 29. "  ASB413  ,Active Status Bit 413" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB412  ,Active Status Bit 412" "Not active,Active"
bitfld.long 0x00 27. "  ASB411  ,Active Status Bit 411" "Not active,Active"
bitfld.long 0x00 26. "  ASB410  ,Active Status Bit 410" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB409  ,Active Status Bit 409" "Not active,Active"
bitfld.long 0x00 24. "  ASB408  ,Active Status Bit 408" "Not active,Active"
bitfld.long 0x00 23. "  ASB407  ,Active Status Bit 407" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB406  ,Active Status Bit 406" "Not active,Active"
bitfld.long 0x00 21. "  ASB405  ,Active Status Bit 405" "Not active,Active"
bitfld.long 0x00 20. "  ASB404  ,Active Status Bit 404" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB403  ,Active Status Bit 403" "Not active,Active"
bitfld.long 0x00 18. "  ASB402  ,Active Status Bit 402" "Not active,Active"
bitfld.long 0x00 17. "  ASB401  ,Active Status Bit 401" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB400  ,Active Status Bit 400" "Not active,Active"
bitfld.long 0x00 15. "  ASB399  ,Active Status Bit 399" "Not active,Active"
bitfld.long 0x00 14. "  ASB398  ,Active Status Bit 398" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB397  ,Active Status Bit 397" "Not active,Active"
bitfld.long 0x00 12. "  ASB396  ,Active Status Bit 396" "Not active,Active"
bitfld.long 0x00 11. "  ASB395  ,Active Status Bit 395" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB394  ,Active Status Bit 394" "Not active,Active"
bitfld.long 0x00 9. "  ASB393  ,Active Status Bit 393" "Not active,Active"
bitfld.long 0x00 8. "  ASB392  ,Active Status Bit 392" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB391  ,Active Status Bit 391" "Not active,Active"
bitfld.long 0x00 6. "  ASB390  ,Active Status Bit 390" "Not active,Active"
bitfld.long 0x00 5. "  ASB389  ,Active Status Bit 389" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB388  ,Active Status Bit 388" "Not active,Active"
bitfld.long 0x00 3. "  ASB387  ,Active Status Bit 387" "Not active,Active"
bitfld.long 0x00 2. "  ASB386  ,Active Status Bit 386" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB385  ,Active Status Bit 385" "Not active,Active"
bitfld.long 0x00 0. "  ASB384  ,Active Status Bit 384" "Not active,Active"
else
rgroup.long 0x0330++0x03
line.long 0x0 "GICD_ICDABR12,Active Status Register 12"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0D)
rgroup.long 0x0334++0x03
line.long 0x0 "GICD_ICDABR13,Active Status Register 13"
bitfld.long 0x00 31. " ASB447  ,Active Status Bit 447" "Not active,Active"
bitfld.long 0x00 30. "  ASB446  ,Active Status Bit 446" "Not active,Active"
bitfld.long 0x00 29. "  ASB445  ,Active Status Bit 445" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB444  ,Active Status Bit 444" "Not active,Active"
bitfld.long 0x00 27. "  ASB443  ,Active Status Bit 443" "Not active,Active"
bitfld.long 0x00 26. "  ASB442  ,Active Status Bit 442" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB441  ,Active Status Bit 441" "Not active,Active"
bitfld.long 0x00 24. "  ASB440  ,Active Status Bit 440" "Not active,Active"
bitfld.long 0x00 23. "  ASB439  ,Active Status Bit 439" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB438  ,Active Status Bit 438" "Not active,Active"
bitfld.long 0x00 21. "  ASB437  ,Active Status Bit 437" "Not active,Active"
bitfld.long 0x00 20. "  ASB436  ,Active Status Bit 436" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB435  ,Active Status Bit 435" "Not active,Active"
bitfld.long 0x00 18. "  ASB434  ,Active Status Bit 434" "Not active,Active"
bitfld.long 0x00 17. "  ASB433  ,Active Status Bit 433" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB432  ,Active Status Bit 432" "Not active,Active"
bitfld.long 0x00 15. "  ASB431  ,Active Status Bit 431" "Not active,Active"
bitfld.long 0x00 14. "  ASB430  ,Active Status Bit 430" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB429  ,Active Status Bit 429" "Not active,Active"
bitfld.long 0x00 12. "  ASB428  ,Active Status Bit 428" "Not active,Active"
bitfld.long 0x00 11. "  ASB427  ,Active Status Bit 427" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB426  ,Active Status Bit 426" "Not active,Active"
bitfld.long 0x00 9. "  ASB425  ,Active Status Bit 425" "Not active,Active"
bitfld.long 0x00 8. "  ASB424  ,Active Status Bit 424" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB423  ,Active Status Bit 423" "Not active,Active"
bitfld.long 0x00 6. "  ASB422  ,Active Status Bit 422" "Not active,Active"
bitfld.long 0x00 5. "  ASB421  ,Active Status Bit 421" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB420  ,Active Status Bit 420" "Not active,Active"
bitfld.long 0x00 3. "  ASB419  ,Active Status Bit 419" "Not active,Active"
bitfld.long 0x00 2. "  ASB418  ,Active Status Bit 418" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB417  ,Active Status Bit 417" "Not active,Active"
bitfld.long 0x00 0. "  ASB416  ,Active Status Bit 416" "Not active,Active"
else
rgroup.long 0x0334++0x03
line.long 0x0 "GICD_ICDABR13,Active Status Register 13"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0E)
rgroup.long 0x0338++0x03
line.long 0x0 "GICD_ICDABR14,Active Status Register 14"
bitfld.long 0x00 31. " ASB479  ,Active Status Bit 479" "Not active,Active"
bitfld.long 0x00 30. "  ASB478  ,Active Status Bit 478" "Not active,Active"
bitfld.long 0x00 29. "  ASB477  ,Active Status Bit 477" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB476  ,Active Status Bit 476" "Not active,Active"
bitfld.long 0x00 27. "  ASB475  ,Active Status Bit 475" "Not active,Active"
bitfld.long 0x00 26. "  ASB474  ,Active Status Bit 474" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB473  ,Active Status Bit 473" "Not active,Active"
bitfld.long 0x00 24. "  ASB472  ,Active Status Bit 472" "Not active,Active"
bitfld.long 0x00 23. "  ASB471  ,Active Status Bit 471" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB470  ,Active Status Bit 470" "Not active,Active"
bitfld.long 0x00 21. "  ASB469  ,Active Status Bit 469" "Not active,Active"
bitfld.long 0x00 20. "  ASB468  ,Active Status Bit 468" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB467  ,Active Status Bit 467" "Not active,Active"
bitfld.long 0x00 18. "  ASB466  ,Active Status Bit 466" "Not active,Active"
bitfld.long 0x00 17. "  ASB465  ,Active Status Bit 465" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB464  ,Active Status Bit 464" "Not active,Active"
bitfld.long 0x00 15. "  ASB463  ,Active Status Bit 463" "Not active,Active"
bitfld.long 0x00 14. "  ASB462  ,Active Status Bit 462" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB461  ,Active Status Bit 461" "Not active,Active"
bitfld.long 0x00 12. "  ASB460  ,Active Status Bit 460" "Not active,Active"
bitfld.long 0x00 11. "  ASB459  ,Active Status Bit 459" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB458  ,Active Status Bit 458" "Not active,Active"
bitfld.long 0x00 9. "  ASB457  ,Active Status Bit 457" "Not active,Active"
bitfld.long 0x00 8. "  ASB456  ,Active Status Bit 456" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB455  ,Active Status Bit 455" "Not active,Active"
bitfld.long 0x00 6. "  ASB454  ,Active Status Bit 454" "Not active,Active"
bitfld.long 0x00 5. "  ASB453  ,Active Status Bit 453" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB452  ,Active Status Bit 452" "Not active,Active"
bitfld.long 0x00 3. "  ASB451  ,Active Status Bit 451" "Not active,Active"
bitfld.long 0x00 2. "  ASB450  ,Active Status Bit 450" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB449  ,Active Status Bit 449" "Not active,Active"
bitfld.long 0x00 0. "  ASB448  ,Active Status Bit 448" "Not active,Active"
else
rgroup.long 0x0338++0x03
line.long 0x0 "GICD_ICDABR14,Active Status Register 14"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0F)
rgroup.long 0x033C++0x03
line.long 0x0 "GICD_ICDABR15,Active Status Register 15"
bitfld.long 0x00 31. " ASB511  ,Active Status Bit 511" "Not active,Active"
bitfld.long 0x00 30. "  ASB510  ,Active Status Bit 510" "Not active,Active"
bitfld.long 0x00 29. "  ASB509  ,Active Status Bit 509" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB508  ,Active Status Bit 508" "Not active,Active"
bitfld.long 0x00 27. "  ASB507  ,Active Status Bit 507" "Not active,Active"
bitfld.long 0x00 26. "  ASB506  ,Active Status Bit 506" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB505  ,Active Status Bit 505" "Not active,Active"
bitfld.long 0x00 24. "  ASB504  ,Active Status Bit 504" "Not active,Active"
bitfld.long 0x00 23. "  ASB503  ,Active Status Bit 503" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB502  ,Active Status Bit 502" "Not active,Active"
bitfld.long 0x00 21. "  ASB501  ,Active Status Bit 501" "Not active,Active"
bitfld.long 0x00 20. "  ASB500  ,Active Status Bit 500" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB499  ,Active Status Bit 499" "Not active,Active"
bitfld.long 0x00 18. "  ASB498  ,Active Status Bit 498" "Not active,Active"
bitfld.long 0x00 17. "  ASB497  ,Active Status Bit 497" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB496  ,Active Status Bit 496" "Not active,Active"
bitfld.long 0x00 15. "  ASB495  ,Active Status Bit 495" "Not active,Active"
bitfld.long 0x00 14. "  ASB494  ,Active Status Bit 494" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB493  ,Active Status Bit 493" "Not active,Active"
bitfld.long 0x00 12. "  ASB492  ,Active Status Bit 492" "Not active,Active"
bitfld.long 0x00 11. "  ASB491  ,Active Status Bit 491" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB490  ,Active Status Bit 490" "Not active,Active"
bitfld.long 0x00 9. "  ASB489  ,Active Status Bit 489" "Not active,Active"
bitfld.long 0x00 8. "  ASB488  ,Active Status Bit 488" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB487  ,Active Status Bit 487" "Not active,Active"
bitfld.long 0x00 6. "  ASB486  ,Active Status Bit 486" "Not active,Active"
bitfld.long 0x00 5. "  ASB485  ,Active Status Bit 485" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB484  ,Active Status Bit 484" "Not active,Active"
bitfld.long 0x00 3. "  ASB483  ,Active Status Bit 483" "Not active,Active"
bitfld.long 0x00 2. "  ASB482  ,Active Status Bit 482" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB481  ,Active Status Bit 481" "Not active,Active"
bitfld.long 0x00 0. "  ASB480  ,Active Status Bit 480" "Not active,Active"
else
rgroup.long 0x033C++0x03
line.long 0x0 "GICD_ICDABR15,Active Status Register 15"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x10)
rgroup.long 0x0340++0x03
line.long 0x0 "GICD_ICDABR16,Active Status Register 16"
bitfld.long 0x00 31. " ASB543  ,Active Status Bit 543" "Not active,Active"
bitfld.long 0x00 30. "  ASB542  ,Active Status Bit 542" "Not active,Active"
bitfld.long 0x00 29. "  ASB541  ,Active Status Bit 541" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB540  ,Active Status Bit 540" "Not active,Active"
bitfld.long 0x00 27. "  ASB539  ,Active Status Bit 539" "Not active,Active"
bitfld.long 0x00 26. "  ASB538  ,Active Status Bit 538" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB537  ,Active Status Bit 537" "Not active,Active"
bitfld.long 0x00 24. "  ASB536  ,Active Status Bit 536" "Not active,Active"
bitfld.long 0x00 23. "  ASB535  ,Active Status Bit 535" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB534  ,Active Status Bit 534" "Not active,Active"
bitfld.long 0x00 21. "  ASB533  ,Active Status Bit 533" "Not active,Active"
bitfld.long 0x00 20. "  ASB532  ,Active Status Bit 532" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB531  ,Active Status Bit 531" "Not active,Active"
bitfld.long 0x00 18. "  ASB530  ,Active Status Bit 530" "Not active,Active"
bitfld.long 0x00 17. "  ASB529  ,Active Status Bit 529" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB528  ,Active Status Bit 528" "Not active,Active"
bitfld.long 0x00 15. "  ASB527  ,Active Status Bit 527" "Not active,Active"
bitfld.long 0x00 14. "  ASB526  ,Active Status Bit 526" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB525  ,Active Status Bit 525" "Not active,Active"
bitfld.long 0x00 12. "  ASB524  ,Active Status Bit 524" "Not active,Active"
bitfld.long 0x00 11. "  ASB523  ,Active Status Bit 523" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB522  ,Active Status Bit 522" "Not active,Active"
bitfld.long 0x00 9. "  ASB521  ,Active Status Bit 521" "Not active,Active"
bitfld.long 0x00 8. "  ASB520  ,Active Status Bit 520" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB519  ,Active Status Bit 519" "Not active,Active"
bitfld.long 0x00 6. "  ASB518  ,Active Status Bit 518" "Not active,Active"
bitfld.long 0x00 5. "  ASB517  ,Active Status Bit 517" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB516  ,Active Status Bit 516" "Not active,Active"
bitfld.long 0x00 3. "  ASB515  ,Active Status Bit 515" "Not active,Active"
bitfld.long 0x00 2. "  ASB514  ,Active Status Bit 514" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB513  ,Active Status Bit 513" "Not active,Active"
bitfld.long 0x00 0. "  ASB512  ,Active Status Bit 512" "Not active,Active"
else
rgroup.long 0x0340++0x03
line.long 0x0 "GICD_ICDABR16,Active Status Register 16"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x11)
rgroup.long 0x0344++0x03
line.long 0x0 "GICD_ICDABR17,Active Status Register 17"
bitfld.long 0x00 31. " ASB575  ,Active Status Bit 575" "Not active,Active"
bitfld.long 0x00 30. "  ASB574  ,Active Status Bit 574" "Not active,Active"
bitfld.long 0x00 29. "  ASB573  ,Active Status Bit 573" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB572  ,Active Status Bit 572" "Not active,Active"
bitfld.long 0x00 27. "  ASB571  ,Active Status Bit 571" "Not active,Active"
bitfld.long 0x00 26. "  ASB570  ,Active Status Bit 570" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB569  ,Active Status Bit 569" "Not active,Active"
bitfld.long 0x00 24. "  ASB568  ,Active Status Bit 568" "Not active,Active"
bitfld.long 0x00 23. "  ASB567  ,Active Status Bit 567" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB566  ,Active Status Bit 566" "Not active,Active"
bitfld.long 0x00 21. "  ASB565  ,Active Status Bit 565" "Not active,Active"
bitfld.long 0x00 20. "  ASB564  ,Active Status Bit 564" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB563  ,Active Status Bit 563" "Not active,Active"
bitfld.long 0x00 18. "  ASB562  ,Active Status Bit 562" "Not active,Active"
bitfld.long 0x00 17. "  ASB561  ,Active Status Bit 561" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB560  ,Active Status Bit 560" "Not active,Active"
bitfld.long 0x00 15. "  ASB559  ,Active Status Bit 559" "Not active,Active"
bitfld.long 0x00 14. "  ASB558  ,Active Status Bit 558" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB557  ,Active Status Bit 557" "Not active,Active"
bitfld.long 0x00 12. "  ASB556  ,Active Status Bit 556" "Not active,Active"
bitfld.long 0x00 11. "  ASB555  ,Active Status Bit 555" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB554  ,Active Status Bit 554" "Not active,Active"
bitfld.long 0x00 9. "  ASB553  ,Active Status Bit 553" "Not active,Active"
bitfld.long 0x00 8. "  ASB552  ,Active Status Bit 552" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB551  ,Active Status Bit 551" "Not active,Active"
bitfld.long 0x00 6. "  ASB550  ,Active Status Bit 550" "Not active,Active"
bitfld.long 0x00 5. "  ASB549  ,Active Status Bit 549" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB548  ,Active Status Bit 548" "Not active,Active"
bitfld.long 0x00 3. "  ASB547  ,Active Status Bit 547" "Not active,Active"
bitfld.long 0x00 2. "  ASB546  ,Active Status Bit 546" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB545  ,Active Status Bit 545" "Not active,Active"
bitfld.long 0x00 0. "  ASB544  ,Active Status Bit 544" "Not active,Active"
else
rgroup.long 0x0344++0x03
line.long 0x0 "GICD_ICDABR17,Active Status Register 17"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x12)
rgroup.long 0x0348++0x03
line.long 0x0 "GICD_ICDABR18,Active Status Register 18"
bitfld.long 0x00 31. " ASB607  ,Active Status Bit 607" "Not active,Active"
bitfld.long 0x00 30. "  ASB606  ,Active Status Bit 606" "Not active,Active"
bitfld.long 0x00 29. "  ASB605  ,Active Status Bit 605" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB604  ,Active Status Bit 604" "Not active,Active"
bitfld.long 0x00 27. "  ASB603  ,Active Status Bit 603" "Not active,Active"
bitfld.long 0x00 26. "  ASB602  ,Active Status Bit 602" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB601  ,Active Status Bit 601" "Not active,Active"
bitfld.long 0x00 24. "  ASB600  ,Active Status Bit 600" "Not active,Active"
bitfld.long 0x00 23. "  ASB599  ,Active Status Bit 599" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB598  ,Active Status Bit 598" "Not active,Active"
bitfld.long 0x00 21. "  ASB597  ,Active Status Bit 597" "Not active,Active"
bitfld.long 0x00 20. "  ASB596  ,Active Status Bit 596" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB595  ,Active Status Bit 595" "Not active,Active"
bitfld.long 0x00 18. "  ASB594  ,Active Status Bit 594" "Not active,Active"
bitfld.long 0x00 17. "  ASB593  ,Active Status Bit 593" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB592  ,Active Status Bit 592" "Not active,Active"
bitfld.long 0x00 15. "  ASB591  ,Active Status Bit 591" "Not active,Active"
bitfld.long 0x00 14. "  ASB590  ,Active Status Bit 590" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB589  ,Active Status Bit 589" "Not active,Active"
bitfld.long 0x00 12. "  ASB588  ,Active Status Bit 588" "Not active,Active"
bitfld.long 0x00 11. "  ASB587  ,Active Status Bit 587" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB586  ,Active Status Bit 586" "Not active,Active"
bitfld.long 0x00 9. "  ASB585  ,Active Status Bit 585" "Not active,Active"
bitfld.long 0x00 8. "  ASB584  ,Active Status Bit 584" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB583  ,Active Status Bit 583" "Not active,Active"
bitfld.long 0x00 6. "  ASB582  ,Active Status Bit 582" "Not active,Active"
bitfld.long 0x00 5. "  ASB581  ,Active Status Bit 581" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB580  ,Active Status Bit 580" "Not active,Active"
bitfld.long 0x00 3. "  ASB579  ,Active Status Bit 579" "Not active,Active"
bitfld.long 0x00 2. "  ASB578  ,Active Status Bit 578" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB577  ,Active Status Bit 577" "Not active,Active"
bitfld.long 0x00 0. "  ASB576  ,Active Status Bit 576" "Not active,Active"
else
rgroup.long 0x0348++0x03
line.long 0x0 "GICD_ICDABR18,Active Status Register 18"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x13)
rgroup.long 0x034C++0x03
line.long 0x0 "GICD_ICDABR19,Active Status Register 19"
bitfld.long 0x00 31. " ASB639  ,Active Status Bit 639" "Not active,Active"
bitfld.long 0x00 30. "  ASB638  ,Active Status Bit 638" "Not active,Active"
bitfld.long 0x00 29. "  ASB637  ,Active Status Bit 637" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB636  ,Active Status Bit 636" "Not active,Active"
bitfld.long 0x00 27. "  ASB635  ,Active Status Bit 635" "Not active,Active"
bitfld.long 0x00 26. "  ASB634  ,Active Status Bit 634" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB633  ,Active Status Bit 633" "Not active,Active"
bitfld.long 0x00 24. "  ASB632  ,Active Status Bit 632" "Not active,Active"
bitfld.long 0x00 23. "  ASB631  ,Active Status Bit 631" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB630  ,Active Status Bit 630" "Not active,Active"
bitfld.long 0x00 21. "  ASB629  ,Active Status Bit 629" "Not active,Active"
bitfld.long 0x00 20. "  ASB628  ,Active Status Bit 628" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB627  ,Active Status Bit 627" "Not active,Active"
bitfld.long 0x00 18. "  ASB626  ,Active Status Bit 626" "Not active,Active"
bitfld.long 0x00 17. "  ASB625  ,Active Status Bit 625" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB624  ,Active Status Bit 624" "Not active,Active"
bitfld.long 0x00 15. "  ASB623  ,Active Status Bit 623" "Not active,Active"
bitfld.long 0x00 14. "  ASB622  ,Active Status Bit 622" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB621  ,Active Status Bit 621" "Not active,Active"
bitfld.long 0x00 12. "  ASB620  ,Active Status Bit 620" "Not active,Active"
bitfld.long 0x00 11. "  ASB619  ,Active Status Bit 619" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB618  ,Active Status Bit 618" "Not active,Active"
bitfld.long 0x00 9. "  ASB617  ,Active Status Bit 617" "Not active,Active"
bitfld.long 0x00 8. "  ASB616  ,Active Status Bit 616" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB615  ,Active Status Bit 615" "Not active,Active"
bitfld.long 0x00 6. "  ASB614  ,Active Status Bit 614" "Not active,Active"
bitfld.long 0x00 5. "  ASB613  ,Active Status Bit 613" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB612  ,Active Status Bit 612" "Not active,Active"
bitfld.long 0x00 3. "  ASB611  ,Active Status Bit 611" "Not active,Active"
bitfld.long 0x00 2. "  ASB610  ,Active Status Bit 610" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB609  ,Active Status Bit 609" "Not active,Active"
bitfld.long 0x00 0. "  ASB608  ,Active Status Bit 608" "Not active,Active"
else
rgroup.long 0x034C++0x03
line.long 0x0 "GICD_ICDABR19,Active Status Register 19"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x14)
rgroup.long 0x0350++0x03
line.long 0x0 "GICD_ICDABR20,Active Status Register 20"
bitfld.long 0x00 31. " ASB671  ,Active Status Bit 671" "Not active,Active"
bitfld.long 0x00 30. "  ASB670  ,Active Status Bit 670" "Not active,Active"
bitfld.long 0x00 29. "  ASB669  ,Active Status Bit 669" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB668  ,Active Status Bit 668" "Not active,Active"
bitfld.long 0x00 27. "  ASB667  ,Active Status Bit 667" "Not active,Active"
bitfld.long 0x00 26. "  ASB666  ,Active Status Bit 666" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB665  ,Active Status Bit 665" "Not active,Active"
bitfld.long 0x00 24. "  ASB664  ,Active Status Bit 664" "Not active,Active"
bitfld.long 0x00 23. "  ASB663  ,Active Status Bit 663" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB662  ,Active Status Bit 662" "Not active,Active"
bitfld.long 0x00 21. "  ASB661  ,Active Status Bit 661" "Not active,Active"
bitfld.long 0x00 20. "  ASB660  ,Active Status Bit 660" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB659  ,Active Status Bit 659" "Not active,Active"
bitfld.long 0x00 18. "  ASB658  ,Active Status Bit 658" "Not active,Active"
bitfld.long 0x00 17. "  ASB657  ,Active Status Bit 657" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB656  ,Active Status Bit 656" "Not active,Active"
bitfld.long 0x00 15. "  ASB655  ,Active Status Bit 655" "Not active,Active"
bitfld.long 0x00 14. "  ASB654  ,Active Status Bit 654" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB653  ,Active Status Bit 653" "Not active,Active"
bitfld.long 0x00 12. "  ASB652  ,Active Status Bit 652" "Not active,Active"
bitfld.long 0x00 11. "  ASB651  ,Active Status Bit 651" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB650  ,Active Status Bit 650" "Not active,Active"
bitfld.long 0x00 9. "  ASB649  ,Active Status Bit 649" "Not active,Active"
bitfld.long 0x00 8. "  ASB648  ,Active Status Bit 648" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB647  ,Active Status Bit 647" "Not active,Active"
bitfld.long 0x00 6. "  ASB646  ,Active Status Bit 646" "Not active,Active"
bitfld.long 0x00 5. "  ASB645  ,Active Status Bit 645" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB644  ,Active Status Bit 644" "Not active,Active"
bitfld.long 0x00 3. "  ASB643  ,Active Status Bit 643" "Not active,Active"
bitfld.long 0x00 2. "  ASB642  ,Active Status Bit 642" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB641  ,Active Status Bit 641" "Not active,Active"
bitfld.long 0x00 0. "  ASB640  ,Active Status Bit 640" "Not active,Active"
else
rgroup.long 0x0350++0x03
line.long 0x0 "GICD_ICDABR20,Active Status Register 20"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x15)
rgroup.long 0x0354++0x03
line.long 0x0 "GICD_ICDABR21,Active Status Register 21"
bitfld.long 0x00 31. " ASB703  ,Active Status Bit 703" "Not active,Active"
bitfld.long 0x00 30. "  ASB702  ,Active Status Bit 702" "Not active,Active"
bitfld.long 0x00 29. "  ASB701  ,Active Status Bit 701" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB700  ,Active Status Bit 700" "Not active,Active"
bitfld.long 0x00 27. "  ASB699  ,Active Status Bit 699" "Not active,Active"
bitfld.long 0x00 26. "  ASB698  ,Active Status Bit 698" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB697  ,Active Status Bit 697" "Not active,Active"
bitfld.long 0x00 24. "  ASB696  ,Active Status Bit 696" "Not active,Active"
bitfld.long 0x00 23. "  ASB695  ,Active Status Bit 695" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB694  ,Active Status Bit 694" "Not active,Active"
bitfld.long 0x00 21. "  ASB693  ,Active Status Bit 693" "Not active,Active"
bitfld.long 0x00 20. "  ASB692  ,Active Status Bit 692" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB691  ,Active Status Bit 691" "Not active,Active"
bitfld.long 0x00 18. "  ASB690  ,Active Status Bit 690" "Not active,Active"
bitfld.long 0x00 17. "  ASB689  ,Active Status Bit 689" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB688  ,Active Status Bit 688" "Not active,Active"
bitfld.long 0x00 15. "  ASB687  ,Active Status Bit 687" "Not active,Active"
bitfld.long 0x00 14. "  ASB686  ,Active Status Bit 686" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB685  ,Active Status Bit 685" "Not active,Active"
bitfld.long 0x00 12. "  ASB684  ,Active Status Bit 684" "Not active,Active"
bitfld.long 0x00 11. "  ASB683  ,Active Status Bit 683" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB682  ,Active Status Bit 682" "Not active,Active"
bitfld.long 0x00 9. "  ASB681  ,Active Status Bit 681" "Not active,Active"
bitfld.long 0x00 8. "  ASB680  ,Active Status Bit 680" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB679  ,Active Status Bit 679" "Not active,Active"
bitfld.long 0x00 6. "  ASB678  ,Active Status Bit 678" "Not active,Active"
bitfld.long 0x00 5. "  ASB677  ,Active Status Bit 677" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB676  ,Active Status Bit 676" "Not active,Active"
bitfld.long 0x00 3. "  ASB675  ,Active Status Bit 675" "Not active,Active"
bitfld.long 0x00 2. "  ASB674  ,Active Status Bit 674" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB673  ,Active Status Bit 673" "Not active,Active"
bitfld.long 0x00 0. "  ASB672  ,Active Status Bit 672" "Not active,Active"
else
rgroup.long 0x0354++0x03
line.long 0x0 "GICD_ICDABR21,Active Status Register 21"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x16)
rgroup.long 0x0358++0x03
line.long 0x0 "GICD_ICDABR22,Active Status Register 22"
bitfld.long 0x00 31. " ASB735  ,Active Status Bit 735" "Not active,Active"
bitfld.long 0x00 30. "  ASB734  ,Active Status Bit 734" "Not active,Active"
bitfld.long 0x00 29. "  ASB733  ,Active Status Bit 733" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB732  ,Active Status Bit 732" "Not active,Active"
bitfld.long 0x00 27. "  ASB731  ,Active Status Bit 731" "Not active,Active"
bitfld.long 0x00 26. "  ASB730  ,Active Status Bit 730" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB729  ,Active Status Bit 729" "Not active,Active"
bitfld.long 0x00 24. "  ASB728  ,Active Status Bit 728" "Not active,Active"
bitfld.long 0x00 23. "  ASB727  ,Active Status Bit 727" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB726  ,Active Status Bit 726" "Not active,Active"
bitfld.long 0x00 21. "  ASB725  ,Active Status Bit 725" "Not active,Active"
bitfld.long 0x00 20. "  ASB724  ,Active Status Bit 724" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB723  ,Active Status Bit 723" "Not active,Active"
bitfld.long 0x00 18. "  ASB722  ,Active Status Bit 722" "Not active,Active"
bitfld.long 0x00 17. "  ASB721  ,Active Status Bit 721" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB720  ,Active Status Bit 720" "Not active,Active"
bitfld.long 0x00 15. "  ASB719  ,Active Status Bit 719" "Not active,Active"
bitfld.long 0x00 14. "  ASB718  ,Active Status Bit 718" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB717  ,Active Status Bit 717" "Not active,Active"
bitfld.long 0x00 12. "  ASB716  ,Active Status Bit 716" "Not active,Active"
bitfld.long 0x00 11. "  ASB715  ,Active Status Bit 715" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB714  ,Active Status Bit 714" "Not active,Active"
bitfld.long 0x00 9. "  ASB713  ,Active Status Bit 713" "Not active,Active"
bitfld.long 0x00 8. "  ASB712  ,Active Status Bit 712" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB711  ,Active Status Bit 711" "Not active,Active"
bitfld.long 0x00 6. "  ASB710  ,Active Status Bit 710" "Not active,Active"
bitfld.long 0x00 5. "  ASB709  ,Active Status Bit 709" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB708  ,Active Status Bit 708" "Not active,Active"
bitfld.long 0x00 3. "  ASB707  ,Active Status Bit 707" "Not active,Active"
bitfld.long 0x00 2. "  ASB706  ,Active Status Bit 706" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB705  ,Active Status Bit 705" "Not active,Active"
bitfld.long 0x00 0. "  ASB704  ,Active Status Bit 704" "Not active,Active"
else
rgroup.long 0x0358++0x03
line.long 0x0 "GICD_ICDABR22,Active Status Register 22"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x17)
rgroup.long 0x035C++0x03
line.long 0x0 "GICD_ICDABR23,Active Status Register 23"
bitfld.long 0x00 31. " ASB767  ,Active Status Bit 767" "Not active,Active"
bitfld.long 0x00 30. "  ASB766  ,Active Status Bit 766" "Not active,Active"
bitfld.long 0x00 29. "  ASB765  ,Active Status Bit 765" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB764  ,Active Status Bit 764" "Not active,Active"
bitfld.long 0x00 27. "  ASB763  ,Active Status Bit 763" "Not active,Active"
bitfld.long 0x00 26. "  ASB762  ,Active Status Bit 762" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB761  ,Active Status Bit 761" "Not active,Active"
bitfld.long 0x00 24. "  ASB760  ,Active Status Bit 760" "Not active,Active"
bitfld.long 0x00 23. "  ASB759  ,Active Status Bit 759" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB758  ,Active Status Bit 758" "Not active,Active"
bitfld.long 0x00 21. "  ASB757  ,Active Status Bit 757" "Not active,Active"
bitfld.long 0x00 20. "  ASB756  ,Active Status Bit 756" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB755  ,Active Status Bit 755" "Not active,Active"
bitfld.long 0x00 18. "  ASB754  ,Active Status Bit 754" "Not active,Active"
bitfld.long 0x00 17. "  ASB753  ,Active Status Bit 753" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB752  ,Active Status Bit 752" "Not active,Active"
bitfld.long 0x00 15. "  ASB751  ,Active Status Bit 751" "Not active,Active"
bitfld.long 0x00 14. "  ASB750  ,Active Status Bit 750" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB749  ,Active Status Bit 749" "Not active,Active"
bitfld.long 0x00 12. "  ASB748  ,Active Status Bit 748" "Not active,Active"
bitfld.long 0x00 11. "  ASB747  ,Active Status Bit 747" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB746  ,Active Status Bit 746" "Not active,Active"
bitfld.long 0x00 9. "  ASB745  ,Active Status Bit 745" "Not active,Active"
bitfld.long 0x00 8. "  ASB744  ,Active Status Bit 744" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB743  ,Active Status Bit 743" "Not active,Active"
bitfld.long 0x00 6. "  ASB742  ,Active Status Bit 742" "Not active,Active"
bitfld.long 0x00 5. "  ASB741  ,Active Status Bit 741" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB740  ,Active Status Bit 740" "Not active,Active"
bitfld.long 0x00 3. "  ASB739  ,Active Status Bit 739" "Not active,Active"
bitfld.long 0x00 2. "  ASB738  ,Active Status Bit 738" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB737  ,Active Status Bit 737" "Not active,Active"
bitfld.long 0x00 0. "  ASB736  ,Active Status Bit 736" "Not active,Active"
else
rgroup.long 0x035C++0x03
line.long 0x0 "GICD_ICDABR23,Active Status Register 23"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x18)
rgroup.long 0x0360++0x03
line.long 0x0 "GICD_ICDABR24,Active Status Register 24"
bitfld.long 0x00 31. " ASB799  ,Active Status Bit 799" "Not active,Active"
bitfld.long 0x00 30. "  ASB798  ,Active Status Bit 798" "Not active,Active"
bitfld.long 0x00 29. "  ASB797  ,Active Status Bit 797" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB796  ,Active Status Bit 796" "Not active,Active"
bitfld.long 0x00 27. "  ASB795  ,Active Status Bit 795" "Not active,Active"
bitfld.long 0x00 26. "  ASB794  ,Active Status Bit 794" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB793  ,Active Status Bit 793" "Not active,Active"
bitfld.long 0x00 24. "  ASB792  ,Active Status Bit 792" "Not active,Active"
bitfld.long 0x00 23. "  ASB791  ,Active Status Bit 791" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB790  ,Active Status Bit 790" "Not active,Active"
bitfld.long 0x00 21. "  ASB789  ,Active Status Bit 789" "Not active,Active"
bitfld.long 0x00 20. "  ASB788  ,Active Status Bit 788" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB787  ,Active Status Bit 787" "Not active,Active"
bitfld.long 0x00 18. "  ASB786  ,Active Status Bit 786" "Not active,Active"
bitfld.long 0x00 17. "  ASB785  ,Active Status Bit 785" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB784  ,Active Status Bit 784" "Not active,Active"
bitfld.long 0x00 15. "  ASB783  ,Active Status Bit 783" "Not active,Active"
bitfld.long 0x00 14. "  ASB782  ,Active Status Bit 782" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB781  ,Active Status Bit 781" "Not active,Active"
bitfld.long 0x00 12. "  ASB780  ,Active Status Bit 780" "Not active,Active"
bitfld.long 0x00 11. "  ASB779  ,Active Status Bit 779" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB778  ,Active Status Bit 778" "Not active,Active"
bitfld.long 0x00 9. "  ASB777  ,Active Status Bit 777" "Not active,Active"
bitfld.long 0x00 8. "  ASB776  ,Active Status Bit 776" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB775  ,Active Status Bit 775" "Not active,Active"
bitfld.long 0x00 6. "  ASB774  ,Active Status Bit 774" "Not active,Active"
bitfld.long 0x00 5. "  ASB773  ,Active Status Bit 773" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB772  ,Active Status Bit 772" "Not active,Active"
bitfld.long 0x00 3. "  ASB771  ,Active Status Bit 771" "Not active,Active"
bitfld.long 0x00 2. "  ASB770  ,Active Status Bit 770" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB769  ,Active Status Bit 769" "Not active,Active"
bitfld.long 0x00 0. "  ASB768  ,Active Status Bit 768" "Not active,Active"
else
rgroup.long 0x0360++0x03
line.long 0x0 "GICD_ICDABR24,Active Status Register 24"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x19)
rgroup.long 0x0364++0x03
line.long 0x0 "GICD_ICDABR25,Active Status Register 25"
bitfld.long 0x00 31. " ASB831  ,Active Status Bit 831" "Not active,Active"
bitfld.long 0x00 30. "  ASB830  ,Active Status Bit 830" "Not active,Active"
bitfld.long 0x00 29. "  ASB829  ,Active Status Bit 829" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB828  ,Active Status Bit 828" "Not active,Active"
bitfld.long 0x00 27. "  ASB827  ,Active Status Bit 827" "Not active,Active"
bitfld.long 0x00 26. "  ASB826  ,Active Status Bit 826" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB825  ,Active Status Bit 825" "Not active,Active"
bitfld.long 0x00 24. "  ASB824  ,Active Status Bit 824" "Not active,Active"
bitfld.long 0x00 23. "  ASB823  ,Active Status Bit 823" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB822  ,Active Status Bit 822" "Not active,Active"
bitfld.long 0x00 21. "  ASB821  ,Active Status Bit 821" "Not active,Active"
bitfld.long 0x00 20. "  ASB820  ,Active Status Bit 820" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB819  ,Active Status Bit 819" "Not active,Active"
bitfld.long 0x00 18. "  ASB818  ,Active Status Bit 818" "Not active,Active"
bitfld.long 0x00 17. "  ASB817  ,Active Status Bit 817" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB816  ,Active Status Bit 816" "Not active,Active"
bitfld.long 0x00 15. "  ASB815  ,Active Status Bit 815" "Not active,Active"
bitfld.long 0x00 14. "  ASB814  ,Active Status Bit 814" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB813  ,Active Status Bit 813" "Not active,Active"
bitfld.long 0x00 12. "  ASB812  ,Active Status Bit 812" "Not active,Active"
bitfld.long 0x00 11. "  ASB811  ,Active Status Bit 811" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB810  ,Active Status Bit 810" "Not active,Active"
bitfld.long 0x00 9. "  ASB809  ,Active Status Bit 809" "Not active,Active"
bitfld.long 0x00 8. "  ASB808  ,Active Status Bit 808" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB807  ,Active Status Bit 807" "Not active,Active"
bitfld.long 0x00 6. "  ASB806  ,Active Status Bit 806" "Not active,Active"
bitfld.long 0x00 5. "  ASB805  ,Active Status Bit 805" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB804  ,Active Status Bit 804" "Not active,Active"
bitfld.long 0x00 3. "  ASB803  ,Active Status Bit 803" "Not active,Active"
bitfld.long 0x00 2. "  ASB802  ,Active Status Bit 802" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB801  ,Active Status Bit 801" "Not active,Active"
bitfld.long 0x00 0. "  ASB800  ,Active Status Bit 800" "Not active,Active"
else
rgroup.long 0x0364++0x03
line.long 0x0 "GICD_ICDABR25,Active Status Register 25"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1A)
rgroup.long 0x0368++0x03
line.long 0x0 "GICD_ICDABR26,Active Status Register 26"
bitfld.long 0x00 31. " ASB863  ,Active Status Bit 863" "Not active,Active"
bitfld.long 0x00 30. "  ASB862  ,Active Status Bit 862" "Not active,Active"
bitfld.long 0x00 29. "  ASB861  ,Active Status Bit 861" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB860  ,Active Status Bit 860" "Not active,Active"
bitfld.long 0x00 27. "  ASB859  ,Active Status Bit 859" "Not active,Active"
bitfld.long 0x00 26. "  ASB858  ,Active Status Bit 858" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB857  ,Active Status Bit 857" "Not active,Active"
bitfld.long 0x00 24. "  ASB856  ,Active Status Bit 856" "Not active,Active"
bitfld.long 0x00 23. "  ASB855  ,Active Status Bit 855" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB854  ,Active Status Bit 854" "Not active,Active"
bitfld.long 0x00 21. "  ASB853  ,Active Status Bit 853" "Not active,Active"
bitfld.long 0x00 20. "  ASB852  ,Active Status Bit 852" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB851  ,Active Status Bit 851" "Not active,Active"
bitfld.long 0x00 18. "  ASB850  ,Active Status Bit 850" "Not active,Active"
bitfld.long 0x00 17. "  ASB849  ,Active Status Bit 849" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB848  ,Active Status Bit 848" "Not active,Active"
bitfld.long 0x00 15. "  ASB847  ,Active Status Bit 847" "Not active,Active"
bitfld.long 0x00 14. "  ASB846  ,Active Status Bit 846" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB845  ,Active Status Bit 845" "Not active,Active"
bitfld.long 0x00 12. "  ASB844  ,Active Status Bit 844" "Not active,Active"
bitfld.long 0x00 11. "  ASB843  ,Active Status Bit 843" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB842  ,Active Status Bit 842" "Not active,Active"
bitfld.long 0x00 9. "  ASB841  ,Active Status Bit 841" "Not active,Active"
bitfld.long 0x00 8. "  ASB840  ,Active Status Bit 840" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB839  ,Active Status Bit 839" "Not active,Active"
bitfld.long 0x00 6. "  ASB838  ,Active Status Bit 838" "Not active,Active"
bitfld.long 0x00 5. "  ASB837  ,Active Status Bit 837" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB836  ,Active Status Bit 836" "Not active,Active"
bitfld.long 0x00 3. "  ASB835  ,Active Status Bit 835" "Not active,Active"
bitfld.long 0x00 2. "  ASB834  ,Active Status Bit 834" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB833  ,Active Status Bit 833" "Not active,Active"
bitfld.long 0x00 0. "  ASB832  ,Active Status Bit 832" "Not active,Active"
else
rgroup.long 0x0368++0x03
line.long 0x0 "GICD_ICDABR26,Active Status Register 26"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1B)
rgroup.long 0x036C++0x03
line.long 0x0 "GICD_ICDABR27,Active Status Register 27"
bitfld.long 0x00 31. " ASB895  ,Active Status Bit 895" "Not active,Active"
bitfld.long 0x00 30. "  ASB894  ,Active Status Bit 894" "Not active,Active"
bitfld.long 0x00 29. "  ASB893  ,Active Status Bit 893" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB892  ,Active Status Bit 892" "Not active,Active"
bitfld.long 0x00 27. "  ASB891  ,Active Status Bit 891" "Not active,Active"
bitfld.long 0x00 26. "  ASB890  ,Active Status Bit 890" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB889  ,Active Status Bit 889" "Not active,Active"
bitfld.long 0x00 24. "  ASB888  ,Active Status Bit 888" "Not active,Active"
bitfld.long 0x00 23. "  ASB887  ,Active Status Bit 887" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB886  ,Active Status Bit 886" "Not active,Active"
bitfld.long 0x00 21. "  ASB885  ,Active Status Bit 885" "Not active,Active"
bitfld.long 0x00 20. "  ASB884  ,Active Status Bit 884" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB883  ,Active Status Bit 883" "Not active,Active"
bitfld.long 0x00 18. "  ASB882  ,Active Status Bit 882" "Not active,Active"
bitfld.long 0x00 17. "  ASB881  ,Active Status Bit 881" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB880  ,Active Status Bit 880" "Not active,Active"
bitfld.long 0x00 15. "  ASB879  ,Active Status Bit 879" "Not active,Active"
bitfld.long 0x00 14. "  ASB878  ,Active Status Bit 878" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB877  ,Active Status Bit 877" "Not active,Active"
bitfld.long 0x00 12. "  ASB876  ,Active Status Bit 876" "Not active,Active"
bitfld.long 0x00 11. "  ASB875  ,Active Status Bit 875" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB874  ,Active Status Bit 874" "Not active,Active"
bitfld.long 0x00 9. "  ASB873  ,Active Status Bit 873" "Not active,Active"
bitfld.long 0x00 8. "  ASB872  ,Active Status Bit 872" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB871  ,Active Status Bit 871" "Not active,Active"
bitfld.long 0x00 6. "  ASB870  ,Active Status Bit 870" "Not active,Active"
bitfld.long 0x00 5. "  ASB869  ,Active Status Bit 869" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB868  ,Active Status Bit 868" "Not active,Active"
bitfld.long 0x00 3. "  ASB867  ,Active Status Bit 867" "Not active,Active"
bitfld.long 0x00 2. "  ASB866  ,Active Status Bit 866" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB865  ,Active Status Bit 865" "Not active,Active"
bitfld.long 0x00 0. "  ASB864  ,Active Status Bit 864" "Not active,Active"
else
rgroup.long 0x036C++0x03
line.long 0x0 "GICD_ICDABR27,Active Status Register 27"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1C)
rgroup.long 0x0370++0x03
line.long 0x0 "GICD_ICDABR28,Active Status Register 28"
bitfld.long 0x00 31. " ASB927  ,Active Status Bit 927" "Not active,Active"
bitfld.long 0x00 30. "  ASB926  ,Active Status Bit 926" "Not active,Active"
bitfld.long 0x00 29. "  ASB925  ,Active Status Bit 925" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB924  ,Active Status Bit 924" "Not active,Active"
bitfld.long 0x00 27. "  ASB923  ,Active Status Bit 923" "Not active,Active"
bitfld.long 0x00 26. "  ASB922  ,Active Status Bit 922" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB921  ,Active Status Bit 921" "Not active,Active"
bitfld.long 0x00 24. "  ASB920  ,Active Status Bit 920" "Not active,Active"
bitfld.long 0x00 23. "  ASB919  ,Active Status Bit 919" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB918  ,Active Status Bit 918" "Not active,Active"
bitfld.long 0x00 21. "  ASB917  ,Active Status Bit 917" "Not active,Active"
bitfld.long 0x00 20. "  ASB916  ,Active Status Bit 916" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB915  ,Active Status Bit 915" "Not active,Active"
bitfld.long 0x00 18. "  ASB914  ,Active Status Bit 914" "Not active,Active"
bitfld.long 0x00 17. "  ASB913  ,Active Status Bit 913" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB912  ,Active Status Bit 912" "Not active,Active"
bitfld.long 0x00 15. "  ASB911  ,Active Status Bit 911" "Not active,Active"
bitfld.long 0x00 14. "  ASB910  ,Active Status Bit 910" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB909  ,Active Status Bit 909" "Not active,Active"
bitfld.long 0x00 12. "  ASB908  ,Active Status Bit 908" "Not active,Active"
bitfld.long 0x00 11. "  ASB907  ,Active Status Bit 907" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB906  ,Active Status Bit 906" "Not active,Active"
bitfld.long 0x00 9. "  ASB905  ,Active Status Bit 905" "Not active,Active"
bitfld.long 0x00 8. "  ASB904  ,Active Status Bit 904" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB903  ,Active Status Bit 903" "Not active,Active"
bitfld.long 0x00 6. "  ASB902  ,Active Status Bit 902" "Not active,Active"
bitfld.long 0x00 5. "  ASB901  ,Active Status Bit 901" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB900  ,Active Status Bit 900" "Not active,Active"
bitfld.long 0x00 3. "  ASB899  ,Active Status Bit 899" "Not active,Active"
bitfld.long 0x00 2. "  ASB898  ,Active Status Bit 898" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB897  ,Active Status Bit 897" "Not active,Active"
bitfld.long 0x00 0. "  ASB896  ,Active Status Bit 896" "Not active,Active"
else
rgroup.long 0x0370++0x03
line.long 0x0 "GICD_ICDABR28,Active Status Register 28"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1D)
rgroup.long 0x0374++0x03
line.long 0x0 "GICD_ICDABR29,Active Status Register 29"
bitfld.long 0x00 31. " ASB959  ,Active Status Bit 959" "Not active,Active"
bitfld.long 0x00 30. "  ASB958  ,Active Status Bit 958" "Not active,Active"
bitfld.long 0x00 29. "  ASB957  ,Active Status Bit 957" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB956  ,Active Status Bit 956" "Not active,Active"
bitfld.long 0x00 27. "  ASB955  ,Active Status Bit 955" "Not active,Active"
bitfld.long 0x00 26. "  ASB954  ,Active Status Bit 954" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB953  ,Active Status Bit 953" "Not active,Active"
bitfld.long 0x00 24. "  ASB952  ,Active Status Bit 952" "Not active,Active"
bitfld.long 0x00 23. "  ASB951  ,Active Status Bit 951" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB950  ,Active Status Bit 950" "Not active,Active"
bitfld.long 0x00 21. "  ASB949  ,Active Status Bit 949" "Not active,Active"
bitfld.long 0x00 20. "  ASB948  ,Active Status Bit 948" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB947  ,Active Status Bit 947" "Not active,Active"
bitfld.long 0x00 18. "  ASB946  ,Active Status Bit 946" "Not active,Active"
bitfld.long 0x00 17. "  ASB945  ,Active Status Bit 945" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB944  ,Active Status Bit 944" "Not active,Active"
bitfld.long 0x00 15. "  ASB943  ,Active Status Bit 943" "Not active,Active"
bitfld.long 0x00 14. "  ASB942  ,Active Status Bit 942" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB941  ,Active Status Bit 941" "Not active,Active"
bitfld.long 0x00 12. "  ASB940  ,Active Status Bit 940" "Not active,Active"
bitfld.long 0x00 11. "  ASB939  ,Active Status Bit 939" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB938  ,Active Status Bit 938" "Not active,Active"
bitfld.long 0x00 9. "  ASB937  ,Active Status Bit 937" "Not active,Active"
bitfld.long 0x00 8. "  ASB936  ,Active Status Bit 936" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB935  ,Active Status Bit 935" "Not active,Active"
bitfld.long 0x00 6. "  ASB934  ,Active Status Bit 934" "Not active,Active"
bitfld.long 0x00 5. "  ASB933  ,Active Status Bit 933" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB932  ,Active Status Bit 932" "Not active,Active"
bitfld.long 0x00 3. "  ASB931  ,Active Status Bit 931" "Not active,Active"
bitfld.long 0x00 2. "  ASB930  ,Active Status Bit 930" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB929  ,Active Status Bit 929" "Not active,Active"
bitfld.long 0x00 0. "  ASB928  ,Active Status Bit 928" "Not active,Active"
else
rgroup.long 0x0374++0x03
line.long 0x0 "GICD_ICDABR29,Active Status Register 29"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1E)
rgroup.long 0x0378++0x03
line.long 0x0 "GICD_ICDABR30,Active Status Register 30"
bitfld.long 0x00 31. " ASB991  ,Active Status Bit 991" "Not active,Active"
bitfld.long 0x00 30. "  ASB990  ,Active Status Bit 990" "Not active,Active"
bitfld.long 0x00 29. "  ASB989  ,Active Status Bit 989" "Not active,Active"
textline "                                 "
bitfld.long 0x00 28. " ASB988  ,Active Status Bit 988" "Not active,Active"
bitfld.long 0x00 27. "  ASB987  ,Active Status Bit 987" "Not active,Active"
bitfld.long 0x00 26. "  ASB986  ,Active Status Bit 986" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB985  ,Active Status Bit 985" "Not active,Active"
bitfld.long 0x00 24. "  ASB984  ,Active Status Bit 984" "Not active,Active"
bitfld.long 0x00 23. "  ASB983  ,Active Status Bit 983" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB982  ,Active Status Bit 982" "Not active,Active"
bitfld.long 0x00 21. "  ASB981  ,Active Status Bit 981" "Not active,Active"
bitfld.long 0x00 20. "  ASB980  ,Active Status Bit 980" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB979  ,Active Status Bit 979" "Not active,Active"
bitfld.long 0x00 18. "  ASB978  ,Active Status Bit 978" "Not active,Active"
bitfld.long 0x00 17. "  ASB977  ,Active Status Bit 977" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB976  ,Active Status Bit 976" "Not active,Active"
bitfld.long 0x00 15. "  ASB975  ,Active Status Bit 975" "Not active,Active"
bitfld.long 0x00 14. "  ASB974  ,Active Status Bit 974" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB973  ,Active Status Bit 973" "Not active,Active"
bitfld.long 0x00 12. "  ASB972  ,Active Status Bit 972" "Not active,Active"
bitfld.long 0x00 11. "  ASB971  ,Active Status Bit 971" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB970  ,Active Status Bit 970" "Not active,Active"
bitfld.long 0x00 9. "  ASB969  ,Active Status Bit 969" "Not active,Active"
bitfld.long 0x00 8. "  ASB968  ,Active Status Bit 968" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB967  ,Active Status Bit 967" "Not active,Active"
bitfld.long 0x00 6. "  ASB966  ,Active Status Bit 966" "Not active,Active"
bitfld.long 0x00 5. "  ASB965  ,Active Status Bit 965" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB964  ,Active Status Bit 964" "Not active,Active"
bitfld.long 0x00 3. "  ASB963  ,Active Status Bit 963" "Not active,Active"
bitfld.long 0x00 2. "  ASB962  ,Active Status Bit 962" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB961  ,Active Status Bit 961" "Not active,Active"
bitfld.long 0x00 0. "  ASB960  ,Active Status Bit 960" "Not active,Active"
else
rgroup.long 0x0378++0x03
line.long 0x0 "GICD_ICDABR30,Active Status Register 30"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)==0x1F)
rgroup.long 0x037C++0x03
line.long 0x0 "GICD_ICDABR31,Active Status Register 31"
bitfld.long 0x00 27. " ASB1019 ,Active Status Bit 1019" "Not active,Active"
bitfld.long 0x00 26. "  ASB1018 ,Active Status Bit 1018" "Not active,Active"
textline "                                 "
bitfld.long 0x00 25. " ASB1017 ,Active Status Bit 1017" "Not active,Active"
bitfld.long 0x00 24. "  ASB1016 ,Active Status Bit 1016" "Not active,Active"
bitfld.long 0x00 23. "  ASB1015 ,Active Status Bit 1015" "Not active,Active"
textline "                                 "
bitfld.long 0x00 22. " ASB1014 ,Active Status Bit 1014" "Not active,Active"
bitfld.long 0x00 21. "  ASB1013 ,Active Status Bit 1013" "Not active,Active"
bitfld.long 0x00 20. "  ASB1012 ,Active Status Bit 1012" "Not active,Active"
textline "                                 "
bitfld.long 0x00 19. " ASB1011 ,Active Status Bit 1011" "Not active,Active"
bitfld.long 0x00 18. "  ASB1010 ,Active Status Bit 1010" "Not active,Active"
bitfld.long 0x00 17. "  ASB1009 ,Active Status Bit 1009" "Not active,Active"
textline "                                 "
bitfld.long 0x00 16. " ASB1008 ,Active Status Bit 1008" "Not active,Active"
bitfld.long 0x00 15. "  ASB1007 ,Active Status Bit 1007" "Not active,Active"
bitfld.long 0x00 14. "  ASB1006 ,Active Status Bit 1006" "Not active,Active"
textline "                                 "
bitfld.long 0x00 13. " ASB1005 ,Active Status Bit 1005" "Not active,Active"
bitfld.long 0x00 12. "  ASB1004 ,Active Status Bit 1004" "Not active,Active"
bitfld.long 0x00 11. "  ASB1003 ,Active Status Bit 1003" "Not active,Active"
textline "                                 "
bitfld.long 0x00 10. " ASB1002 ,Active Status Bit 1002" "Not active,Active"
bitfld.long 0x00 9. "  ASB1001 ,Active Status Bit 1001" "Not active,Active"
bitfld.long 0x00 8. "  ASB1000 ,Active Status Bit 1000" "Not active,Active"
textline "                                 "
bitfld.long 0x00 7. " ASB999  ,Active Status Bit 999" "Not active,Active"
bitfld.long 0x00 6. "  ASB998  ,Active Status Bit 998" "Not active,Active"
bitfld.long 0x00 5. "  ASB997  ,Active Status Bit 997" "Not active,Active"
textline "                                 "
bitfld.long 0x00 4. " ASB996  ,Active Status Bit 996" "Not active,Active"
bitfld.long 0x00 3. "  ASB995  ,Active Status Bit 995" "Not active,Active"
bitfld.long 0x00 2. "  ASB994  ,Active Status Bit 994" "Not active,Active"
textline "                                 "
bitfld.long 0x00 1. " ASB993  ,Active Status Bit 993" "Not active,Active"
bitfld.long 0x00 0. "  ASB992  ,Active Status Bit 992" "Not active,Active"
else
rgroup.long 0x037C++0x03
line.long 0x0 "GICD_ICDABR31,Active Status Register 31"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
else
group.long 0x0300++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31  ,Set/Clear Active Bit 31" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE30  ,Set/Clear Active Bit 30" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE29  ,Set/Clear Active Bit 29" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28  ,Set/Clear Active Bit 28" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE27  ,Set/Clear Active Bit 27" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE26  ,Set/Clear Active Bit 26" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25  ,Set/Clear Active Bit 25" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE24  ,Set/Clear Active Bit 24" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE23  ,Set/Clear Active Bit 23" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22  ,Set/Clear Active Bit 22" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE21  ,Set/Clear Active Bit 21" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE20  ,Set/Clear Active Bit 20" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19  ,Set/Clear Active Bit 19" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE18  ,Set/Clear Active Bit 18" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE17  ,Set/Clear Active Bit 17" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16  ,Set/Clear Active Bit 16" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE15  ,Set/Clear Active Bit 15" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE14  ,Set/Clear Active Bit 14" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13  ,Set/Clear Active Bit 13" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE12  ,Set/Clear Active Bit 12" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE11  ,Set/Clear Active Bit 11" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10  ,Set/Clear Active Bit 10" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE9   ,Set/Clear Active Bit 9" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE8   ,Set/Clear Active Bit 8" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7   ,Set/Clear Active Bit 7" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE6   ,Set/Clear Active Bit 6" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE5   ,Set/Clear Active Bit 5" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4   ,Set/Clear Active Bit 4" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE3   ,Set/Clear Active Bit 3" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE2   ,Set/Clear Active Bit 2" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1   ,Set/Clear Active Bit 1" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE0   ,Set/Clear Active Bit 0" "Not active,Active"
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x01)
group.long 0x0304++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63  ,Set/Clear Active Bit 63" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE62  ,Set/Clear Active Bit 62" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE61  ,Set/Clear Active Bit 61" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60  ,Set/Clear Active Bit 60" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE59  ,Set/Clear Active Bit 59" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE58  ,Set/Clear Active Bit 58" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57  ,Set/Clear Active Bit 57" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE56  ,Set/Clear Active Bit 56" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE55  ,Set/Clear Active Bit 55" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54  ,Set/Clear Active Bit 54" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE53  ,Set/Clear Active Bit 53" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE52  ,Set/Clear Active Bit 52" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51  ,Set/Clear Active Bit 51" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE50  ,Set/Clear Active Bit 50" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE49  ,Set/Clear Active Bit 49" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48  ,Set/Clear Active Bit 48" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE47  ,Set/Clear Active Bit 47" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE46  ,Set/Clear Active Bit 46" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45  ,Set/Clear Active Bit 45" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE44  ,Set/Clear Active Bit 44" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE43  ,Set/Clear Active Bit 43" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42  ,Set/Clear Active Bit 42" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE41  ,Set/Clear Active Bit 41" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE40  ,Set/Clear Active Bit 40" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39  ,Set/Clear Active Bit 39" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE38  ,Set/Clear Active Bit 38" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE37  ,Set/Clear Active Bit 37" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36  ,Set/Clear Active Bit 36" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE35  ,Set/Clear Active Bit 35" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE34  ,Set/Clear Active Bit 34" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33  ,Set/Clear Active Bit 33" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE32  ,Set/Clear Active Bit 32" "Not active,Active"
else
rgroup.long 0x0304++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x02)
group.long 0x0308++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95  ,Set/Clear Active Bit 95" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE94  ,Set/Clear Active Bit 94" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE93  ,Set/Clear Active Bit 93" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92  ,Set/Clear Active Bit 92" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE91  ,Set/Clear Active Bit 91" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE90  ,Set/Clear Active Bit 90" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89  ,Set/Clear Active Bit 89" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE88  ,Set/Clear Active Bit 88" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE87  ,Set/Clear Active Bit 87" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86  ,Set/Clear Active Bit 86" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE85  ,Set/Clear Active Bit 85" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE84  ,Set/Clear Active Bit 84" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83  ,Set/Clear Active Bit 83" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE82  ,Set/Clear Active Bit 82" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE81  ,Set/Clear Active Bit 81" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80  ,Set/Clear Active Bit 80" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE79  ,Set/Clear Active Bit 79" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE78  ,Set/Clear Active Bit 78" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77  ,Set/Clear Active Bit 77" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE76  ,Set/Clear Active Bit 76" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE75  ,Set/Clear Active Bit 75" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74  ,Set/Clear Active Bit 74" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE73  ,Set/Clear Active Bit 73" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE72  ,Set/Clear Active Bit 72" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71  ,Set/Clear Active Bit 71" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE70  ,Set/Clear Active Bit 70" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE69  ,Set/Clear Active Bit 69" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68  ,Set/Clear Active Bit 68" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE67  ,Set/Clear Active Bit 67" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE66  ,Set/Clear Active Bit 66" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65  ,Set/Clear Active Bit 65" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE64  ,Set/Clear Active Bit 64" "Not active,Active"
else
rgroup.long 0x0308++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x03)
group.long 0x030C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE99  ,Set/Clear Active Bit 99" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE98  ,Set/Clear Active Bit 98" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97  ,Set/Clear Active Bit 97" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE96  ,Set/Clear Active Bit 96" "Not active,Active"
else
rgroup.long 0x030C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x04)
group.long 0x0310++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active"
else
rgroup.long 0x0310++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x05)
group.long 0x0314++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active"
else
rgroup.long 0x0314++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x06)
group.long 0x0318++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active"
else
rgroup.long 0x0318++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x07)
group.long 0x031C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active"
else
rgroup.long 0x031C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x08)
group.long 0x0320++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active"
else
rgroup.long 0x0320++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x09)
group.long 0x0324++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active"
else
rgroup.long 0x0324++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0A)
group.long 0x0328++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active"
else
rgroup.long 0x0328++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0B)
group.long 0x032C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active"
else
rgroup.long 0x032C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0C)
group.long 0x0330++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active"
else
rgroup.long 0x0330++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0D)
group.long 0x0334++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active"
else
rgroup.long 0x0334++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0E)
group.long 0x0338++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active"
else
rgroup.long 0x0338++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0F)
group.long 0x033C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active"
else
rgroup.long 0x033C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
rgroup.long 0x0340++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0344++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0348++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x034C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0350++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0354++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0358++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x035C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0360++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0364++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0368++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x036C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0370++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0374++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x0378++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
rgroup.long 0x037C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER31,Interrupt Set/Clear Active Register 31"
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
textline "                                 "
endif
tree.end
tree "Priority Registers"
group.long 0x400++0x03
line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
hexmask.long.byte 0x00 24.--31. 1. " INTID3    ,Interrupt ID3    Priority/Priority Byte Offset 3   "
hexmask.long.byte 0x00 16.--23. 1. "  INTID2    ,Interrupt ID2     Priority/Priority Byte Offset 2   "
hexmask.long.byte 0x00 8.--15. 1. "  INTID1    ,Interrupt ID1    Priority/Priority Byte Offset 1   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID0    ,Interrupt ID0     Priority/Priority Byte Offset 0   "
group.long 0x404++0x03
line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
hexmask.long.byte 0x00 24.--31. 1. " INTID7    ,Interrupt ID7    Priority/Priority Byte Offset 7   "
hexmask.long.byte 0x00 16.--23. 1. "  INTID6    ,Interrupt ID6     Priority/Priority Byte Offset 6   "
hexmask.long.byte 0x00 8.--15. 1. "  INTID5    ,Interrupt ID5    Priority/Priority Byte Offset 5   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID4    ,Interrupt ID4     Priority/Priority Byte Offset 4   "
group.long 0x408++0x03
line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
hexmask.long.byte 0x00 24.--31. 1. " INTID11   ,Interrupt ID11   Priority/Priority Byte Offset 11  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID10   ,Interrupt ID10    Priority/Priority Byte Offset 10  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID9    ,Interrupt ID9    Priority/Priority Byte Offset 9   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID8    ,Interrupt ID8     Priority/Priority Byte Offset 8   "
group.long 0x40C++0x03
line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
hexmask.long.byte 0x00 24.--31. 1. " INTID15   ,Interrupt ID15   Priority/Priority Byte Offset 15  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID14   ,Interrupt ID14    Priority/Priority Byte Offset 14  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID13   ,Interrupt ID13   Priority/Priority Byte Offset 13  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID12   ,Interrupt ID12    Priority/Priority Byte Offset 12  "
group.long 0x410++0x03
line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
hexmask.long.byte 0x00 24.--31. 1. " INTID19   ,Interrupt ID19   Priority/Priority Byte Offset 19  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID18   ,Interrupt ID18    Priority/Priority Byte Offset 18  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID17   ,Interrupt ID17   Priority/Priority Byte Offset 17  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID16   ,Interrupt ID16    Priority/Priority Byte Offset 16  "
group.long 0x414++0x03
line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
hexmask.long.byte 0x00 24.--31. 1. " INTID23   ,Interrupt ID23   Priority/Priority Byte Offset 23  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID22   ,Interrupt ID22    Priority/Priority Byte Offset 22  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID21   ,Interrupt ID21   Priority/Priority Byte Offset 21  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID20   ,Interrupt ID20    Priority/Priority Byte Offset 20  "
group.long 0x418++0x03
line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
hexmask.long.byte 0x00 24.--31. 1. " INTID27   ,Interrupt ID27   Priority/Priority Byte Offset 27  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID26   ,Interrupt ID26    Priority/Priority Byte Offset 26  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID25   ,Interrupt ID25   Priority/Priority Byte Offset 25  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID24   ,Interrupt ID24    Priority/Priority Byte Offset 24  "
group.long 0x41C++0x03
line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
hexmask.long.byte 0x00 24.--31. 1. " INTID31   ,Interrupt ID31   Priority/Priority Byte Offset 31  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID30   ,Interrupt ID30    Priority/Priority Byte Offset 30  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID29   ,Interrupt ID29   Priority/Priority Byte Offset 29  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID28   ,Interrupt ID28    Priority/Priority Byte Offset 28  "
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x01)
group.long 0x420++0x03
line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
hexmask.long.byte 0x00 24.--31. 1. " INTID35   ,Interrupt ID35   Priority/Priority Byte Offset 35  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID34   ,Interrupt ID34    Priority/Priority Byte Offset 34  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID33   ,Interrupt ID33   Priority/Priority Byte Offset 33  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID32   ,Interrupt ID32    Priority/Priority Byte Offset 32  "
group.long 0x424++0x03
line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
hexmask.long.byte 0x00 24.--31. 1. " INTID39   ,Interrupt ID39   Priority/Priority Byte Offset 39  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID38   ,Interrupt ID38    Priority/Priority Byte Offset 38  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID37   ,Interrupt ID37   Priority/Priority Byte Offset 37  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID36   ,Interrupt ID36    Priority/Priority Byte Offset 36  "
group.long 0x428++0x03
line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
hexmask.long.byte 0x00 24.--31. 1. " INTID43   ,Interrupt ID43   Priority/Priority Byte Offset 43  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID42   ,Interrupt ID42    Priority/Priority Byte Offset 42  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID41   ,Interrupt ID41   Priority/Priority Byte Offset 41  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID40   ,Interrupt ID40    Priority/Priority Byte Offset 40  "
group.long 0x42C++0x03
line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
hexmask.long.byte 0x00 24.--31. 1. " INTID47   ,Interrupt ID47   Priority/Priority Byte Offset 47  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID46   ,Interrupt ID46    Priority/Priority Byte Offset 46  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID45   ,Interrupt ID45   Priority/Priority Byte Offset 45  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID44   ,Interrupt ID44    Priority/Priority Byte Offset 44  "
group.long 0x430++0x03
line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
hexmask.long.byte 0x00 24.--31. 1. " INTID51   ,Interrupt ID51   Priority/Priority Byte Offset 51  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID50   ,Interrupt ID50    Priority/Priority Byte Offset 50  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID49   ,Interrupt ID49   Priority/Priority Byte Offset 49  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID48   ,Interrupt ID48    Priority/Priority Byte Offset 48  "
group.long 0x434++0x03
line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
hexmask.long.byte 0x00 24.--31. 1. " INTID55   ,Interrupt ID55   Priority/Priority Byte Offset 55  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID54   ,Interrupt ID54    Priority/Priority Byte Offset 54  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID53   ,Interrupt ID53   Priority/Priority Byte Offset 53  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID52   ,Interrupt ID52    Priority/Priority Byte Offset 52  "
group.long 0x438++0x03
line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
hexmask.long.byte 0x00 24.--31. 1. " INTID59   ,Interrupt ID59   Priority/Priority Byte Offset 59  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID58   ,Interrupt ID58    Priority/Priority Byte Offset 58  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID57   ,Interrupt ID57   Priority/Priority Byte Offset 57  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID56   ,Interrupt ID56    Priority/Priority Byte Offset 56  "
group.long 0x43C++0x03
line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
hexmask.long.byte 0x00 24.--31. 1. " INTID63   ,Interrupt ID63   Priority/Priority Byte Offset 63  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID62   ,Interrupt ID62    Priority/Priority Byte Offset 62  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID61   ,Interrupt ID61   Priority/Priority Byte Offset 61  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID60   ,Interrupt ID60    Priority/Priority Byte Offset 60  "
else
rgroup.long 0x420++0x03
line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
rgroup.long 0x424++0x03
line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
rgroup.long 0x428++0x03
line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
rgroup.long 0x42C++0x03
line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
rgroup.long 0x430++0x03
line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
rgroup.long 0x434++0x03
line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
rgroup.long 0x438++0x03
line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
rgroup.long 0x43C++0x03
line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x02)
group.long 0x440++0x03
line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
hexmask.long.byte 0x00 24.--31. 1. " INTID67   ,Interrupt ID67   Priority/Priority Byte Offset 67  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID66   ,Interrupt ID66    Priority/Priority Byte Offset 66  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID65   ,Interrupt ID65   Priority/Priority Byte Offset 65  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID64   ,Interrupt ID64    Priority/Priority Byte Offset 64  "
group.long 0x444++0x03
line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
hexmask.long.byte 0x00 24.--31. 1. " INTID71   ,Interrupt ID71   Priority/Priority Byte Offset 71  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID70   ,Interrupt ID70    Priority/Priority Byte Offset 70  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID69   ,Interrupt ID69   Priority/Priority Byte Offset 69  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID68   ,Interrupt ID68    Priority/Priority Byte Offset 68  "
group.long 0x448++0x03
line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
hexmask.long.byte 0x00 24.--31. 1. " INTID75   ,Interrupt ID75   Priority/Priority Byte Offset 75  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID74   ,Interrupt ID74    Priority/Priority Byte Offset 74  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID73   ,Interrupt ID73   Priority/Priority Byte Offset 73  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID72   ,Interrupt ID72    Priority/Priority Byte Offset 72  "
group.long 0x44C++0x03
line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
hexmask.long.byte 0x00 24.--31. 1. " INTID79   ,Interrupt ID79   Priority/Priority Byte Offset 79  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID78   ,Interrupt ID78    Priority/Priority Byte Offset 78  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID77   ,Interrupt ID77   Priority/Priority Byte Offset 77  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID76   ,Interrupt ID76    Priority/Priority Byte Offset 76  "
group.long 0x450++0x03
line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
hexmask.long.byte 0x00 24.--31. 1. " INTID83   ,Interrupt ID83   Priority/Priority Byte Offset 83  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID82   ,Interrupt ID82    Priority/Priority Byte Offset 82  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID81   ,Interrupt ID81   Priority/Priority Byte Offset 81  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID80   ,Interrupt ID80    Priority/Priority Byte Offset 80  "
group.long 0x454++0x03
line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
hexmask.long.byte 0x00 24.--31. 1. " INTID87   ,Interrupt ID87   Priority/Priority Byte Offset 87  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID86   ,Interrupt ID86    Priority/Priority Byte Offset 86  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID85   ,Interrupt ID85   Priority/Priority Byte Offset 85  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID84   ,Interrupt ID84    Priority/Priority Byte Offset 84  "
group.long 0x458++0x03
line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
hexmask.long.byte 0x00 24.--31. 1. " INTID91   ,Interrupt ID91   Priority/Priority Byte Offset 91  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID90   ,Interrupt ID90    Priority/Priority Byte Offset 90  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID89   ,Interrupt ID89   Priority/Priority Byte Offset 89  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID88   ,Interrupt ID88    Priority/Priority Byte Offset 88  "
group.long 0x45C++0x03
line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
hexmask.long.byte 0x00 24.--31. 1. " INTID95   ,Interrupt ID95   Priority/Priority Byte Offset 95  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID94   ,Interrupt ID94    Priority/Priority Byte Offset 94  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID93   ,Interrupt ID93   Priority/Priority Byte Offset 93  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID92   ,Interrupt ID92    Priority/Priority Byte Offset 92  "
else
rgroup.long 0x440++0x03
line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
rgroup.long 0x444++0x03
line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
rgroup.long 0x448++0x03
line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
rgroup.long 0x44C++0x03
line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
rgroup.long 0x450++0x03
line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
rgroup.long 0x454++0x03
line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
rgroup.long 0x458++0x03
line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
rgroup.long 0x45C++0x03
line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x03)
group.long 0x460++0x03
line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
hexmask.long.byte 0x00 24.--31. 1. " INTID99   ,Interrupt ID99   Priority/Priority Byte Offset 99  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID98   ,Interrupt ID98    Priority/Priority Byte Offset 98  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID97   ,Interrupt ID97   Priority/Priority Byte Offset 97  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID96   ,Interrupt ID96    Priority/Priority Byte Offset 96  "
group.long 0x464++0x03
line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
hexmask.long.byte 0x00 24.--31. 1. " INTID103  ,Interrupt ID103  Priority/Priority Byte Offset 103 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID102  ,Interrupt ID102   Priority/Priority Byte Offset 102 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID101  ,Interrupt ID101  Priority/Priority Byte Offset 101 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID100  ,Interrupt ID100   Priority/Priority Byte Offset 100 "
group.long 0x468++0x03
line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
hexmask.long.byte 0x00 24.--31. 1. " INTID107  ,Interrupt ID107  Priority/Priority Byte Offset 107 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID106  ,Interrupt ID106   Priority/Priority Byte Offset 106 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID105  ,Interrupt ID105  Priority/Priority Byte Offset 105 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID104  ,Interrupt ID104   Priority/Priority Byte Offset 104 "
group.long 0x46C++0x03
line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
hexmask.long.byte 0x00 24.--31. 1. " INTID111  ,Interrupt ID111  Priority/Priority Byte Offset 111 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID110  ,Interrupt ID110   Priority/Priority Byte Offset 110 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID109  ,Interrupt ID109  Priority/Priority Byte Offset 109 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID108  ,Interrupt ID108   Priority/Priority Byte Offset 108 "
group.long 0x470++0x03
line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
hexmask.long.byte 0x00 24.--31. 1. " INTID115  ,Interrupt ID115  Priority/Priority Byte Offset 115 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID114  ,Interrupt ID114   Priority/Priority Byte Offset 114 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID113  ,Interrupt ID113  Priority/Priority Byte Offset 113 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID112  ,Interrupt ID112   Priority/Priority Byte Offset 112 "
group.long 0x474++0x03
line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
hexmask.long.byte 0x00 24.--31. 1. " INTID119  ,Interrupt ID119  Priority/Priority Byte Offset 119 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID118  ,Interrupt ID118   Priority/Priority Byte Offset 118 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID117  ,Interrupt ID117  Priority/Priority Byte Offset 117 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID116  ,Interrupt ID116   Priority/Priority Byte Offset 116 "
group.long 0x478++0x03
line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
hexmask.long.byte 0x00 24.--31. 1. " INTID123  ,Interrupt ID123  Priority/Priority Byte Offset 123 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID122  ,Interrupt ID122   Priority/Priority Byte Offset 122 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID121  ,Interrupt ID121  Priority/Priority Byte Offset 121 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID120  ,Interrupt ID120   Priority/Priority Byte Offset 120 "
group.long 0x47C++0x03
line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
hexmask.long.byte 0x00 24.--31. 1. " INTID127  ,Interrupt ID127  Priority/Priority Byte Offset 127 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID126  ,Interrupt ID126   Priority/Priority Byte Offset 126 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID125  ,Interrupt ID125  Priority/Priority Byte Offset 125 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID124  ,Interrupt ID124   Priority/Priority Byte Offset 124 "
else
rgroup.long 0x460++0x03
line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
rgroup.long 0x464++0x03
line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
rgroup.long 0x468++0x03
line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
rgroup.long 0x46C++0x03
line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
rgroup.long 0x470++0x03
line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
rgroup.long 0x474++0x03
line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
rgroup.long 0x478++0x03
line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
rgroup.long 0x47C++0x03
line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x04)
group.long 0x480++0x03
line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
hexmask.long.byte 0x00 24.--31. 1. " INTID131  ,Interrupt ID131  Priority/Priority Byte Offset 131 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID130  ,Interrupt ID130   Priority/Priority Byte Offset 130 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID129  ,Interrupt ID129  Priority/Priority Byte Offset 129 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID128  ,Interrupt ID128   Priority/Priority Byte Offset 128 "
group.long 0x484++0x03
line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
hexmask.long.byte 0x00 24.--31. 1. " INTID135  ,Interrupt ID135  Priority/Priority Byte Offset 135 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID134  ,Interrupt ID134   Priority/Priority Byte Offset 134 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID133  ,Interrupt ID133  Priority/Priority Byte Offset 133 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID132  ,Interrupt ID132   Priority/Priority Byte Offset 132 "
group.long 0x488++0x03
line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
hexmask.long.byte 0x00 24.--31. 1. " INTID139  ,Interrupt ID139  Priority/Priority Byte Offset 139 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID138  ,Interrupt ID138   Priority/Priority Byte Offset 138 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID137  ,Interrupt ID137  Priority/Priority Byte Offset 137 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID136  ,Interrupt ID136   Priority/Priority Byte Offset 136 "
group.long 0x48C++0x03
line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
hexmask.long.byte 0x00 24.--31. 1. " INTID143  ,Interrupt ID143  Priority/Priority Byte Offset 143 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID142  ,Interrupt ID142   Priority/Priority Byte Offset 142 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID141  ,Interrupt ID141  Priority/Priority Byte Offset 141 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID140  ,Interrupt ID140   Priority/Priority Byte Offset 140 "
group.long 0x490++0x03
line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
hexmask.long.byte 0x00 24.--31. 1. " INTID147  ,Interrupt ID147  Priority/Priority Byte Offset 147 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID146  ,Interrupt ID146   Priority/Priority Byte Offset 146 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID145  ,Interrupt ID145  Priority/Priority Byte Offset 145 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID144  ,Interrupt ID144   Priority/Priority Byte Offset 144 "
group.long 0x494++0x03
line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
hexmask.long.byte 0x00 24.--31. 1. " INTID151  ,Interrupt ID151  Priority/Priority Byte Offset 151 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID150  ,Interrupt ID150   Priority/Priority Byte Offset 150 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID149  ,Interrupt ID149  Priority/Priority Byte Offset 149 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID148  ,Interrupt ID148   Priority/Priority Byte Offset 148 "
group.long 0x498++0x03
line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
hexmask.long.byte 0x00 24.--31. 1. " INTID155  ,Interrupt ID155  Priority/Priority Byte Offset 155 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID154  ,Interrupt ID154   Priority/Priority Byte Offset 154 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID153  ,Interrupt ID153  Priority/Priority Byte Offset 153 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID152  ,Interrupt ID152   Priority/Priority Byte Offset 152 "
group.long 0x49C++0x03
line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
hexmask.long.byte 0x00 24.--31. 1. " INTID159  ,Interrupt ID159  Priority/Priority Byte Offset 159 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID158  ,Interrupt ID158   Priority/Priority Byte Offset 158 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID157  ,Interrupt ID157  Priority/Priority Byte Offset 157 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID156  ,Interrupt ID156   Priority/Priority Byte Offset 156 "
else
rgroup.long 0x480++0x03
line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
rgroup.long 0x484++0x03
line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
rgroup.long 0x488++0x03
line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
rgroup.long 0x48C++0x03
line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
rgroup.long 0x490++0x03
line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
rgroup.long 0x494++0x03
line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
rgroup.long 0x498++0x03
line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
rgroup.long 0x49C++0x03
line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x05)
group.long 0x4A0++0x03
line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
hexmask.long.byte 0x00 24.--31. 1. " INTID163  ,Interrupt ID163  Priority/Priority Byte Offset 163 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID162  ,Interrupt ID162   Priority/Priority Byte Offset 162 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID161  ,Interrupt ID161  Priority/Priority Byte Offset 161 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID160  ,Interrupt ID160   Priority/Priority Byte Offset 160 "
group.long 0x4A4++0x03
line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
hexmask.long.byte 0x00 24.--31. 1. " INTID167  ,Interrupt ID167  Priority/Priority Byte Offset 167 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID166  ,Interrupt ID166   Priority/Priority Byte Offset 166 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID165  ,Interrupt ID165  Priority/Priority Byte Offset 165 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID164  ,Interrupt ID164   Priority/Priority Byte Offset 164 "
group.long 0x4A8++0x03
line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
hexmask.long.byte 0x00 24.--31. 1. " INTID171  ,Interrupt ID171  Priority/Priority Byte Offset 171 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID170  ,Interrupt ID170   Priority/Priority Byte Offset 170 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID169  ,Interrupt ID169  Priority/Priority Byte Offset 169 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID168  ,Interrupt ID168   Priority/Priority Byte Offset 168 "
group.long 0x4AC++0x03
line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
hexmask.long.byte 0x00 24.--31. 1. " INTID175  ,Interrupt ID175  Priority/Priority Byte Offset 175 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID174  ,Interrupt ID174   Priority/Priority Byte Offset 174 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID173  ,Interrupt ID173  Priority/Priority Byte Offset 173 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID172  ,Interrupt ID172   Priority/Priority Byte Offset 172 "
group.long 0x4B0++0x03
line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
hexmask.long.byte 0x00 24.--31. 1. " INTID179  ,Interrupt ID179  Priority/Priority Byte Offset 179 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID178  ,Interrupt ID178   Priority/Priority Byte Offset 178 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID177  ,Interrupt ID177  Priority/Priority Byte Offset 177 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID176  ,Interrupt ID176   Priority/Priority Byte Offset 176 "
group.long 0x4B4++0x03
line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
hexmask.long.byte 0x00 24.--31. 1. " INTID183  ,Interrupt ID183  Priority/Priority Byte Offset 183 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID182  ,Interrupt ID182   Priority/Priority Byte Offset 182 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID181  ,Interrupt ID181  Priority/Priority Byte Offset 181 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID180  ,Interrupt ID180   Priority/Priority Byte Offset 180 "
group.long 0x4B8++0x03
line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
hexmask.long.byte 0x00 24.--31. 1. " INTID187  ,Interrupt ID187  Priority/Priority Byte Offset 187 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID186  ,Interrupt ID186   Priority/Priority Byte Offset 186 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID185  ,Interrupt ID185  Priority/Priority Byte Offset 185 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID184  ,Interrupt ID184   Priority/Priority Byte Offset 184 "
group.long 0x4BC++0x03
line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
hexmask.long.byte 0x00 24.--31. 1. " INTID191  ,Interrupt ID191  Priority/Priority Byte Offset 191 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID190  ,Interrupt ID190   Priority/Priority Byte Offset 190 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID189  ,Interrupt ID189  Priority/Priority Byte Offset 189 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID188  ,Interrupt ID188   Priority/Priority Byte Offset 188 "
else
rgroup.long 0x4A0++0x03
line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
rgroup.long 0x4A4++0x03
line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
rgroup.long 0x4A8++0x03
line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
rgroup.long 0x4AC++0x03
line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
rgroup.long 0x4B0++0x03
line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
rgroup.long 0x4B4++0x03
line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
rgroup.long 0x4B8++0x03
line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
rgroup.long 0x4BC++0x03
line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x06)
group.long 0x4C0++0x03
line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
hexmask.long.byte 0x00 24.--31. 1. " INTID195  ,Interrupt ID195  Priority/Priority Byte Offset 195 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID194  ,Interrupt ID194   Priority/Priority Byte Offset 194 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID193  ,Interrupt ID193  Priority/Priority Byte Offset 193 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID192  ,Interrupt ID192   Priority/Priority Byte Offset 192 "
group.long 0x4C4++0x03
line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
hexmask.long.byte 0x00 24.--31. 1. " INTID199  ,Interrupt ID199  Priority/Priority Byte Offset 199 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID198  ,Interrupt ID198   Priority/Priority Byte Offset 198 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID197  ,Interrupt ID197  Priority/Priority Byte Offset 197 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID196  ,Interrupt ID196   Priority/Priority Byte Offset 196 "
group.long 0x4C8++0x03
line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
hexmask.long.byte 0x00 24.--31. 1. " INTID203  ,Interrupt ID203  Priority/Priority Byte Offset 203 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID202  ,Interrupt ID202   Priority/Priority Byte Offset 202 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID201  ,Interrupt ID201  Priority/Priority Byte Offset 201 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID200  ,Interrupt ID200   Priority/Priority Byte Offset 200 "
group.long 0x4CC++0x03
line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
hexmask.long.byte 0x00 24.--31. 1. " INTID207  ,Interrupt ID207  Priority/Priority Byte Offset 207 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID206  ,Interrupt ID206   Priority/Priority Byte Offset 206 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID205  ,Interrupt ID205  Priority/Priority Byte Offset 205 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID204  ,Interrupt ID204   Priority/Priority Byte Offset 204 "
group.long 0x4D0++0x03
line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
hexmask.long.byte 0x00 24.--31. 1. " INTID211  ,Interrupt ID211  Priority/Priority Byte Offset 211 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID210  ,Interrupt ID210   Priority/Priority Byte Offset 210 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID209  ,Interrupt ID209  Priority/Priority Byte Offset 209 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID208  ,Interrupt ID208   Priority/Priority Byte Offset 208 "
group.long 0x4D4++0x03
line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
hexmask.long.byte 0x00 24.--31. 1. " INTID215  ,Interrupt ID215  Priority/Priority Byte Offset 215 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID214  ,Interrupt ID214   Priority/Priority Byte Offset 214 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID213  ,Interrupt ID213  Priority/Priority Byte Offset 213 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID212  ,Interrupt ID212   Priority/Priority Byte Offset 212 "
group.long 0x4D8++0x03
line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
hexmask.long.byte 0x00 24.--31. 1. " INTID219  ,Interrupt ID219  Priority/Priority Byte Offset 219 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID218  ,Interrupt ID218   Priority/Priority Byte Offset 218 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID217  ,Interrupt ID217  Priority/Priority Byte Offset 217 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID216  ,Interrupt ID216   Priority/Priority Byte Offset 216 "
group.long 0x4DC++0x03
line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
hexmask.long.byte 0x00 24.--31. 1. " INTID223  ,Interrupt ID223  Priority/Priority Byte Offset 223 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID222  ,Interrupt ID222   Priority/Priority Byte Offset 222 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID221  ,Interrupt ID221  Priority/Priority Byte Offset 221 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID220  ,Interrupt ID220   Priority/Priority Byte Offset 220 "
else
rgroup.long 0x4C0++0x03
line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
rgroup.long 0x4C4++0x03
line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
rgroup.long 0x4C8++0x03
line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
rgroup.long 0x4CC++0x03
line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
rgroup.long 0x4D0++0x03
line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
rgroup.long 0x4D4++0x03
line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
rgroup.long 0x4D8++0x03
line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
rgroup.long 0x4DC++0x03
line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x07)
group.long 0x4E0++0x03
line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
hexmask.long.byte 0x00 24.--31. 1. " INTID227  ,Interrupt ID227  Priority/Priority Byte Offset 227 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID226  ,Interrupt ID226   Priority/Priority Byte Offset 226 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID225  ,Interrupt ID225  Priority/Priority Byte Offset 225 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID224  ,Interrupt ID224   Priority/Priority Byte Offset 224 "
group.long 0x4E4++0x03
line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
hexmask.long.byte 0x00 24.--31. 1. " INTID231  ,Interrupt ID231  Priority/Priority Byte Offset 231 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID230  ,Interrupt ID230   Priority/Priority Byte Offset 230 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID229  ,Interrupt ID229  Priority/Priority Byte Offset 229 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID228  ,Interrupt ID228   Priority/Priority Byte Offset 228 "
group.long 0x4E8++0x03
line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
hexmask.long.byte 0x00 24.--31. 1. " INTID235  ,Interrupt ID235  Priority/Priority Byte Offset 235 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID234  ,Interrupt ID234   Priority/Priority Byte Offset 234 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID233  ,Interrupt ID233  Priority/Priority Byte Offset 233 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID232  ,Interrupt ID232   Priority/Priority Byte Offset 232 "
group.long 0x4EC++0x03
line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
hexmask.long.byte 0x00 24.--31. 1. " INTID239  ,Interrupt ID239  Priority/Priority Byte Offset 239 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID238  ,Interrupt ID238   Priority/Priority Byte Offset 238 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID237  ,Interrupt ID237  Priority/Priority Byte Offset 237 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID236  ,Interrupt ID236   Priority/Priority Byte Offset 236 "
group.long 0x4F0++0x03
line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
hexmask.long.byte 0x00 24.--31. 1. " INTID243  ,Interrupt ID243  Priority/Priority Byte Offset 243 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID242  ,Interrupt ID242   Priority/Priority Byte Offset 242 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID241  ,Interrupt ID241  Priority/Priority Byte Offset 241 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID240  ,Interrupt ID240   Priority/Priority Byte Offset 240 "
group.long 0x4F4++0x03
line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
hexmask.long.byte 0x00 24.--31. 1. " INTID247  ,Interrupt ID247  Priority/Priority Byte Offset 247 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID246  ,Interrupt ID246   Priority/Priority Byte Offset 246 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID245  ,Interrupt ID245  Priority/Priority Byte Offset 245 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID244  ,Interrupt ID244   Priority/Priority Byte Offset 244 "
group.long 0x4F8++0x03
line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
hexmask.long.byte 0x00 24.--31. 1. " INTID251  ,Interrupt ID251  Priority/Priority Byte Offset 251 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID250  ,Interrupt ID250   Priority/Priority Byte Offset 250 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID249  ,Interrupt ID249  Priority/Priority Byte Offset 249 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID248  ,Interrupt ID248   Priority/Priority Byte Offset 248 "
group.long 0x4FC++0x03
line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
hexmask.long.byte 0x00 24.--31. 1. " INTID255  ,Interrupt ID255  Priority/Priority Byte Offset 255 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID254  ,Interrupt ID254   Priority/Priority Byte Offset 254 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID253  ,Interrupt ID253  Priority/Priority Byte Offset 253 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID252  ,Interrupt ID252   Priority/Priority Byte Offset 252 "
else
rgroup.long 0x4E0++0x03
line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
rgroup.long 0x4E4++0x03
line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
rgroup.long 0x4E8++0x03
line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
rgroup.long 0x4EC++0x03
line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
rgroup.long 0x4F0++0x03
line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
rgroup.long 0x4F4++0x03
line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
rgroup.long 0x4F8++0x03
line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
rgroup.long 0x4FC++0x03
line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x08)
group.long 0x500++0x03
line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
hexmask.long.byte 0x00 24.--31. 1. " INTID259  ,Interrupt ID259  Priority/Priority Byte Offset 259 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID258  ,Interrupt ID258   Priority/Priority Byte Offset 258 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID257  ,Interrupt ID257  Priority/Priority Byte Offset 257 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID256  ,Interrupt ID256   Priority/Priority Byte Offset 256 "
group.long 0x504++0x03
line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
hexmask.long.byte 0x00 24.--31. 1. " INTID263  ,Interrupt ID263  Priority/Priority Byte Offset 263 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID262  ,Interrupt ID262   Priority/Priority Byte Offset 262 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID261  ,Interrupt ID261  Priority/Priority Byte Offset 261 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID260  ,Interrupt ID260   Priority/Priority Byte Offset 260 "
group.long 0x508++0x03
line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
hexmask.long.byte 0x00 24.--31. 1. " INTID267  ,Interrupt ID267  Priority/Priority Byte Offset 267 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID266  ,Interrupt ID266   Priority/Priority Byte Offset 266 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID265  ,Interrupt ID265  Priority/Priority Byte Offset 265 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID264  ,Interrupt ID264   Priority/Priority Byte Offset 264 "
group.long 0x50C++0x03
line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
hexmask.long.byte 0x00 24.--31. 1. " INTID271  ,Interrupt ID271  Priority/Priority Byte Offset 271 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID270  ,Interrupt ID270   Priority/Priority Byte Offset 270 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID269  ,Interrupt ID269  Priority/Priority Byte Offset 269 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID268  ,Interrupt ID268   Priority/Priority Byte Offset 268 "
group.long 0x510++0x03
line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
hexmask.long.byte 0x00 24.--31. 1. " INTID275  ,Interrupt ID275  Priority/Priority Byte Offset 275 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID274  ,Interrupt ID274   Priority/Priority Byte Offset 274 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID273  ,Interrupt ID273  Priority/Priority Byte Offset 273 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID272  ,Interrupt ID272   Priority/Priority Byte Offset 272 "
group.long 0x514++0x03
line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
hexmask.long.byte 0x00 24.--31. 1. " INTID279  ,Interrupt ID279  Priority/Priority Byte Offset 279 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID278  ,Interrupt ID278   Priority/Priority Byte Offset 278 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID277  ,Interrupt ID277  Priority/Priority Byte Offset 277 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID276  ,Interrupt ID276   Priority/Priority Byte Offset 276 "
group.long 0x518++0x03
line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
hexmask.long.byte 0x00 24.--31. 1. " INTID283  ,Interrupt ID283  Priority/Priority Byte Offset 283 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID282  ,Interrupt ID282   Priority/Priority Byte Offset 282 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID281  ,Interrupt ID281  Priority/Priority Byte Offset 281 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID280  ,Interrupt ID280   Priority/Priority Byte Offset 280 "
group.long 0x51C++0x03
line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
hexmask.long.byte 0x00 24.--31. 1. " INTID287  ,Interrupt ID287  Priority/Priority Byte Offset 287 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID286  ,Interrupt ID286   Priority/Priority Byte Offset 286 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID285  ,Interrupt ID285  Priority/Priority Byte Offset 285 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID284  ,Interrupt ID284   Priority/Priority Byte Offset 284 "
else
rgroup.long 0x500++0x03
line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
rgroup.long 0x504++0x03
line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
rgroup.long 0x508++0x03
line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
rgroup.long 0x50C++0x03
line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
rgroup.long 0x510++0x03
line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
rgroup.long 0x514++0x03
line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
rgroup.long 0x518++0x03
line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
rgroup.long 0x51C++0x03
line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x09)
group.long 0x520++0x03
line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
hexmask.long.byte 0x00 24.--31. 1. " INTID291  ,Interrupt ID291  Priority/Priority Byte Offset 291 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID290  ,Interrupt ID290   Priority/Priority Byte Offset 290 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID289  ,Interrupt ID289  Priority/Priority Byte Offset 289 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID288  ,Interrupt ID288   Priority/Priority Byte Offset 288 "
group.long 0x524++0x03
line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
hexmask.long.byte 0x00 24.--31. 1. " INTID295  ,Interrupt ID295  Priority/Priority Byte Offset 295 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID294  ,Interrupt ID294   Priority/Priority Byte Offset 294 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID293  ,Interrupt ID293  Priority/Priority Byte Offset 293 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID292  ,Interrupt ID292   Priority/Priority Byte Offset 292 "
group.long 0x528++0x03
line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
hexmask.long.byte 0x00 24.--31. 1. " INTID299  ,Interrupt ID299  Priority/Priority Byte Offset 299 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID298  ,Interrupt ID298   Priority/Priority Byte Offset 298 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID297  ,Interrupt ID297  Priority/Priority Byte Offset 297 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID296  ,Interrupt ID296   Priority/Priority Byte Offset 296 "
group.long 0x52C++0x03
line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
hexmask.long.byte 0x00 24.--31. 1. " INTID303  ,Interrupt ID303  Priority/Priority Byte Offset 303 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID302  ,Interrupt ID302   Priority/Priority Byte Offset 302 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID301  ,Interrupt ID301  Priority/Priority Byte Offset 301 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID300  ,Interrupt ID300   Priority/Priority Byte Offset 300 "
group.long 0x530++0x03
line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
hexmask.long.byte 0x00 24.--31. 1. " INTID307  ,Interrupt ID307  Priority/Priority Byte Offset 307 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID306  ,Interrupt ID306   Priority/Priority Byte Offset 306 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID305  ,Interrupt ID305  Priority/Priority Byte Offset 305 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID304  ,Interrupt ID304   Priority/Priority Byte Offset 304 "
group.long 0x534++0x03
line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
hexmask.long.byte 0x00 24.--31. 1. " INTID311  ,Interrupt ID311  Priority/Priority Byte Offset 311 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID310  ,Interrupt ID310   Priority/Priority Byte Offset 310 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID309  ,Interrupt ID309  Priority/Priority Byte Offset 309 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID308  ,Interrupt ID308   Priority/Priority Byte Offset 308 "
group.long 0x538++0x03
line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
hexmask.long.byte 0x00 24.--31. 1. " INTID315  ,Interrupt ID315  Priority/Priority Byte Offset 315 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID314  ,Interrupt ID314   Priority/Priority Byte Offset 314 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID313  ,Interrupt ID313  Priority/Priority Byte Offset 313 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID312  ,Interrupt ID312   Priority/Priority Byte Offset 312 "
group.long 0x53C++0x03
line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
hexmask.long.byte 0x00 24.--31. 1. " INTID319  ,Interrupt ID319  Priority/Priority Byte Offset 319 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID318  ,Interrupt ID318   Priority/Priority Byte Offset 318 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID317  ,Interrupt ID317  Priority/Priority Byte Offset 317 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID316  ,Interrupt ID316   Priority/Priority Byte Offset 316 "
else
rgroup.long 0x520++0x03
line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
rgroup.long 0x524++0x03
line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
rgroup.long 0x528++0x03
line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
rgroup.long 0x52C++0x03
line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
rgroup.long 0x530++0x03
line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
rgroup.long 0x534++0x03
line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
rgroup.long 0x538++0x03
line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
rgroup.long 0x53C++0x03
line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0A)
group.long 0x540++0x03
line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
hexmask.long.byte 0x00 24.--31. 1. " INTID323  ,Interrupt ID323  Priority/Priority Byte Offset 323 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID322  ,Interrupt ID322   Priority/Priority Byte Offset 322 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID321  ,Interrupt ID321  Priority/Priority Byte Offset 321 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID320  ,Interrupt ID320   Priority/Priority Byte Offset 320 "
group.long 0x544++0x03
line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
hexmask.long.byte 0x00 24.--31. 1. " INTID327  ,Interrupt ID327  Priority/Priority Byte Offset 327 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID326  ,Interrupt ID326   Priority/Priority Byte Offset 326 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID325  ,Interrupt ID325  Priority/Priority Byte Offset 325 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID324  ,Interrupt ID324   Priority/Priority Byte Offset 324 "
group.long 0x548++0x03
line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
hexmask.long.byte 0x00 24.--31. 1. " INTID331  ,Interrupt ID331  Priority/Priority Byte Offset 331 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID330  ,Interrupt ID330   Priority/Priority Byte Offset 330 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID329  ,Interrupt ID329  Priority/Priority Byte Offset 329 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID328  ,Interrupt ID328   Priority/Priority Byte Offset 328 "
group.long 0x54C++0x03
line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
hexmask.long.byte 0x00 24.--31. 1. " INTID335  ,Interrupt ID335  Priority/Priority Byte Offset 335 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID334  ,Interrupt ID334   Priority/Priority Byte Offset 334 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID333  ,Interrupt ID333  Priority/Priority Byte Offset 333 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID332  ,Interrupt ID332   Priority/Priority Byte Offset 332 "
group.long 0x550++0x03
line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
hexmask.long.byte 0x00 24.--31. 1. " INTID339  ,Interrupt ID339  Priority/Priority Byte Offset 339 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID338  ,Interrupt ID338   Priority/Priority Byte Offset 338 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID337  ,Interrupt ID337  Priority/Priority Byte Offset 337 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID336  ,Interrupt ID336   Priority/Priority Byte Offset 336 "
group.long 0x554++0x03
line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
hexmask.long.byte 0x00 24.--31. 1. " INTID343  ,Interrupt ID343  Priority/Priority Byte Offset 343 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID342  ,Interrupt ID342   Priority/Priority Byte Offset 342 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID341  ,Interrupt ID341  Priority/Priority Byte Offset 341 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID340  ,Interrupt ID340   Priority/Priority Byte Offset 340 "
group.long 0x558++0x03
line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
hexmask.long.byte 0x00 24.--31. 1. " INTID347  ,Interrupt ID347  Priority/Priority Byte Offset 347 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID346  ,Interrupt ID346   Priority/Priority Byte Offset 346 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID345  ,Interrupt ID345  Priority/Priority Byte Offset 345 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID344  ,Interrupt ID344   Priority/Priority Byte Offset 344 "
group.long 0x55C++0x03
line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
hexmask.long.byte 0x00 24.--31. 1. " INTID351  ,Interrupt ID351  Priority/Priority Byte Offset 351 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID350  ,Interrupt ID350   Priority/Priority Byte Offset 350 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID349  ,Interrupt ID349  Priority/Priority Byte Offset 349 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID348  ,Interrupt ID348   Priority/Priority Byte Offset 348 "
else
rgroup.long 0x540++0x03
line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
rgroup.long 0x544++0x03
line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
rgroup.long 0x548++0x03
line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
rgroup.long 0x54C++0x03
line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
rgroup.long 0x550++0x03
line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
rgroup.long 0x554++0x03
line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
rgroup.long 0x558++0x03
line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
rgroup.long 0x55C++0x03
line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0B)
group.long 0x560++0x03
line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
hexmask.long.byte 0x00 24.--31. 1. " INTID355  ,Interrupt ID355  Priority/Priority Byte Offset 355 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID354  ,Interrupt ID354   Priority/Priority Byte Offset 354 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID353  ,Interrupt ID353  Priority/Priority Byte Offset 353 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID352  ,Interrupt ID352   Priority/Priority Byte Offset 352 "
group.long 0x564++0x03
line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
hexmask.long.byte 0x00 24.--31. 1. " INTID359  ,Interrupt ID359  Priority/Priority Byte Offset 359 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID358  ,Interrupt ID358   Priority/Priority Byte Offset 358 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID357  ,Interrupt ID357  Priority/Priority Byte Offset 357 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID356  ,Interrupt ID356   Priority/Priority Byte Offset 356 "
group.long 0x568++0x03
line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
hexmask.long.byte 0x00 24.--31. 1. " INTID363  ,Interrupt ID363  Priority/Priority Byte Offset 363 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID362  ,Interrupt ID362   Priority/Priority Byte Offset 362 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID361  ,Interrupt ID361  Priority/Priority Byte Offset 361 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID360  ,Interrupt ID360   Priority/Priority Byte Offset 360 "
group.long 0x56C++0x03
line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
hexmask.long.byte 0x00 24.--31. 1. " INTID367  ,Interrupt ID367  Priority/Priority Byte Offset 367 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID366  ,Interrupt ID366   Priority/Priority Byte Offset 366 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID365  ,Interrupt ID365  Priority/Priority Byte Offset 365 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID364  ,Interrupt ID364   Priority/Priority Byte Offset 364 "
group.long 0x570++0x03
line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
hexmask.long.byte 0x00 24.--31. 1. " INTID371  ,Interrupt ID371  Priority/Priority Byte Offset 371 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID370  ,Interrupt ID370   Priority/Priority Byte Offset 370 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID369  ,Interrupt ID369  Priority/Priority Byte Offset 369 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID368  ,Interrupt ID368   Priority/Priority Byte Offset 368 "
group.long 0x574++0x03
line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
hexmask.long.byte 0x00 24.--31. 1. " INTID375  ,Interrupt ID375  Priority/Priority Byte Offset 375 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID374  ,Interrupt ID374   Priority/Priority Byte Offset 374 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID373  ,Interrupt ID373  Priority/Priority Byte Offset 373 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID372  ,Interrupt ID372   Priority/Priority Byte Offset 372 "
group.long 0x578++0x03
line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
hexmask.long.byte 0x00 24.--31. 1. " INTID379  ,Interrupt ID379  Priority/Priority Byte Offset 379 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID378  ,Interrupt ID378   Priority/Priority Byte Offset 378 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID377  ,Interrupt ID377  Priority/Priority Byte Offset 377 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID376  ,Interrupt ID376   Priority/Priority Byte Offset 376 "
group.long 0x57C++0x03
line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
hexmask.long.byte 0x00 24.--31. 1. " INTID383  ,Interrupt ID383  Priority/Priority Byte Offset 383 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID382  ,Interrupt ID382   Priority/Priority Byte Offset 382 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID381  ,Interrupt ID381  Priority/Priority Byte Offset 381 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID380  ,Interrupt ID380   Priority/Priority Byte Offset 380 "
else
rgroup.long 0x560++0x03
line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
rgroup.long 0x564++0x03
line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
rgroup.long 0x568++0x03
line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
rgroup.long 0x56C++0x03
line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
rgroup.long 0x570++0x03
line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
rgroup.long 0x574++0x03
line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
rgroup.long 0x578++0x03
line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
rgroup.long 0x57C++0x03
line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0C)
group.long 0x580++0x03
line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
hexmask.long.byte 0x00 24.--31. 1. " INTID387  ,Interrupt ID387  Priority/Priority Byte Offset 387 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID386  ,Interrupt ID386   Priority/Priority Byte Offset 386 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID385  ,Interrupt ID385  Priority/Priority Byte Offset 385 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID384  ,Interrupt ID384   Priority/Priority Byte Offset 384 "
group.long 0x584++0x03
line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
hexmask.long.byte 0x00 24.--31. 1. " INTID391  ,Interrupt ID391  Priority/Priority Byte Offset 391 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID390  ,Interrupt ID390   Priority/Priority Byte Offset 390 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID389  ,Interrupt ID389  Priority/Priority Byte Offset 389 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID388  ,Interrupt ID388   Priority/Priority Byte Offset 388 "
group.long 0x588++0x03
line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
hexmask.long.byte 0x00 24.--31. 1. " INTID395  ,Interrupt ID395  Priority/Priority Byte Offset 395 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID394  ,Interrupt ID394   Priority/Priority Byte Offset 394 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID393  ,Interrupt ID393  Priority/Priority Byte Offset 393 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID392  ,Interrupt ID392   Priority/Priority Byte Offset 392 "
group.long 0x58C++0x03
line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
hexmask.long.byte 0x00 24.--31. 1. " INTID399  ,Interrupt ID399  Priority/Priority Byte Offset 399 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID398  ,Interrupt ID398   Priority/Priority Byte Offset 398 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID397  ,Interrupt ID397  Priority/Priority Byte Offset 397 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID396  ,Interrupt ID396   Priority/Priority Byte Offset 396 "
group.long 0x590++0x03
line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
hexmask.long.byte 0x00 24.--31. 1. " INTID403  ,Interrupt ID403  Priority/Priority Byte Offset 403 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID402  ,Interrupt ID402   Priority/Priority Byte Offset 402 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID401  ,Interrupt ID401  Priority/Priority Byte Offset 401 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID400  ,Interrupt ID400   Priority/Priority Byte Offset 400 "
group.long 0x594++0x03
line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
hexmask.long.byte 0x00 24.--31. 1. " INTID407  ,Interrupt ID407  Priority/Priority Byte Offset 407 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID406  ,Interrupt ID406   Priority/Priority Byte Offset 406 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID405  ,Interrupt ID405  Priority/Priority Byte Offset 405 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID404  ,Interrupt ID404   Priority/Priority Byte Offset 404 "
group.long 0x598++0x03
line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
hexmask.long.byte 0x00 24.--31. 1. " INTID411  ,Interrupt ID411  Priority/Priority Byte Offset 411 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID410  ,Interrupt ID410   Priority/Priority Byte Offset 410 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID409  ,Interrupt ID409  Priority/Priority Byte Offset 409 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID408  ,Interrupt ID408   Priority/Priority Byte Offset 408 "
group.long 0x59C++0x03
line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
hexmask.long.byte 0x00 24.--31. 1. " INTID415  ,Interrupt ID415  Priority/Priority Byte Offset 415 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID414  ,Interrupt ID414   Priority/Priority Byte Offset 414 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID413  ,Interrupt ID413  Priority/Priority Byte Offset 413 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID412  ,Interrupt ID412   Priority/Priority Byte Offset 412 "
else
rgroup.long 0x580++0x03
line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
rgroup.long 0x584++0x03
line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
rgroup.long 0x588++0x03
line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
rgroup.long 0x58C++0x03
line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
rgroup.long 0x590++0x03
line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
rgroup.long 0x594++0x03
line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
rgroup.long 0x598++0x03
line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
rgroup.long 0x59C++0x03
line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0D)
group.long 0x5A0++0x03
line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
hexmask.long.byte 0x00 24.--31. 1. " INTID419  ,Interrupt ID419  Priority/Priority Byte Offset 419 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID418  ,Interrupt ID418   Priority/Priority Byte Offset 418 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID417  ,Interrupt ID417  Priority/Priority Byte Offset 417 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID416  ,Interrupt ID416   Priority/Priority Byte Offset 416 "
group.long 0x5A4++0x03
line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
hexmask.long.byte 0x00 24.--31. 1. " INTID423  ,Interrupt ID423  Priority/Priority Byte Offset 423 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID422  ,Interrupt ID422   Priority/Priority Byte Offset 422 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID421  ,Interrupt ID421  Priority/Priority Byte Offset 421 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID420  ,Interrupt ID420   Priority/Priority Byte Offset 420 "
group.long 0x5A8++0x03
line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
hexmask.long.byte 0x00 24.--31. 1. " INTID427  ,Interrupt ID427  Priority/Priority Byte Offset 427 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID426  ,Interrupt ID426   Priority/Priority Byte Offset 426 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID425  ,Interrupt ID425  Priority/Priority Byte Offset 425 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID424  ,Interrupt ID424   Priority/Priority Byte Offset 424 "
group.long 0x5AC++0x03
line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
hexmask.long.byte 0x00 24.--31. 1. " INTID431  ,Interrupt ID431  Priority/Priority Byte Offset 431 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID430  ,Interrupt ID430   Priority/Priority Byte Offset 430 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID429  ,Interrupt ID429  Priority/Priority Byte Offset 429 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID428  ,Interrupt ID428   Priority/Priority Byte Offset 428 "
group.long 0x5B0++0x03
line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
hexmask.long.byte 0x00 24.--31. 1. " INTID435  ,Interrupt ID435  Priority/Priority Byte Offset 435 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID434  ,Interrupt ID434   Priority/Priority Byte Offset 434 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID433  ,Interrupt ID433  Priority/Priority Byte Offset 433 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID432  ,Interrupt ID432   Priority/Priority Byte Offset 432 "
group.long 0x5B4++0x03
line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
hexmask.long.byte 0x00 24.--31. 1. " INTID439  ,Interrupt ID439  Priority/Priority Byte Offset 439 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID438  ,Interrupt ID438   Priority/Priority Byte Offset 438 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID437  ,Interrupt ID437  Priority/Priority Byte Offset 437 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID436  ,Interrupt ID436   Priority/Priority Byte Offset 436 "
group.long 0x5B8++0x03
line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
hexmask.long.byte 0x00 24.--31. 1. " INTID443  ,Interrupt ID443  Priority/Priority Byte Offset 443 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID442  ,Interrupt ID442   Priority/Priority Byte Offset 442 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID441  ,Interrupt ID441  Priority/Priority Byte Offset 441 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID440  ,Interrupt ID440   Priority/Priority Byte Offset 440 "
group.long 0x5BC++0x03
line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
hexmask.long.byte 0x00 24.--31. 1. " INTID447  ,Interrupt ID447  Priority/Priority Byte Offset 447 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID446  ,Interrupt ID446   Priority/Priority Byte Offset 446 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID445  ,Interrupt ID445  Priority/Priority Byte Offset 445 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID444  ,Interrupt ID444   Priority/Priority Byte Offset 444 "
else
rgroup.long 0x5A0++0x03
line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
rgroup.long 0x5A4++0x03
line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
rgroup.long 0x5A8++0x03
line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
rgroup.long 0x5AC++0x03
line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
rgroup.long 0x5B0++0x03
line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
rgroup.long 0x5B4++0x03
line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
rgroup.long 0x5B8++0x03
line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
rgroup.long 0x5BC++0x03
line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0E)
group.long 0x5C0++0x03
line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
hexmask.long.byte 0x00 24.--31. 1. " INTID451  ,Interrupt ID451  Priority/Priority Byte Offset 451 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID450  ,Interrupt ID450   Priority/Priority Byte Offset 450 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID449  ,Interrupt ID449  Priority/Priority Byte Offset 449 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID448  ,Interrupt ID448   Priority/Priority Byte Offset 448 "
group.long 0x5C4++0x03
line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
hexmask.long.byte 0x00 24.--31. 1. " INTID455  ,Interrupt ID455  Priority/Priority Byte Offset 455 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID454  ,Interrupt ID454   Priority/Priority Byte Offset 454 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID453  ,Interrupt ID453  Priority/Priority Byte Offset 453 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID452  ,Interrupt ID452   Priority/Priority Byte Offset 452 "
group.long 0x5C8++0x03
line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
hexmask.long.byte 0x00 24.--31. 1. " INTID459  ,Interrupt ID459  Priority/Priority Byte Offset 459 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID458  ,Interrupt ID458   Priority/Priority Byte Offset 458 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID457  ,Interrupt ID457  Priority/Priority Byte Offset 457 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID456  ,Interrupt ID456   Priority/Priority Byte Offset 456 "
group.long 0x5CC++0x03
line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
hexmask.long.byte 0x00 24.--31. 1. " INTID463  ,Interrupt ID463  Priority/Priority Byte Offset 463 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID462  ,Interrupt ID462   Priority/Priority Byte Offset 462 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID461  ,Interrupt ID461  Priority/Priority Byte Offset 461 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID460  ,Interrupt ID460   Priority/Priority Byte Offset 460 "
group.long 0x5D0++0x03
line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
hexmask.long.byte 0x00 24.--31. 1. " INTID467  ,Interrupt ID467  Priority/Priority Byte Offset 467 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID466  ,Interrupt ID466   Priority/Priority Byte Offset 466 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID465  ,Interrupt ID465  Priority/Priority Byte Offset 465 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID464  ,Interrupt ID464   Priority/Priority Byte Offset 464 "
group.long 0x5D4++0x03
line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
hexmask.long.byte 0x00 24.--31. 1. " INTID471  ,Interrupt ID471  Priority/Priority Byte Offset 471 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID470  ,Interrupt ID470   Priority/Priority Byte Offset 470 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID469  ,Interrupt ID469  Priority/Priority Byte Offset 469 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID468  ,Interrupt ID468   Priority/Priority Byte Offset 468 "
group.long 0x5D8++0x03
line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
hexmask.long.byte 0x00 24.--31. 1. " INTID475  ,Interrupt ID475  Priority/Priority Byte Offset 475 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID474  ,Interrupt ID474   Priority/Priority Byte Offset 474 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID473  ,Interrupt ID473  Priority/Priority Byte Offset 473 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID472  ,Interrupt ID472   Priority/Priority Byte Offset 472 "
group.long 0x5DC++0x03
line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
hexmask.long.byte 0x00 24.--31. 1. " INTID479  ,Interrupt ID479  Priority/Priority Byte Offset 479 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID478  ,Interrupt ID478   Priority/Priority Byte Offset 478 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID477  ,Interrupt ID477  Priority/Priority Byte Offset 477 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID476  ,Interrupt ID476   Priority/Priority Byte Offset 476 "
else
rgroup.long 0x5C0++0x03
line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
rgroup.long 0x5C4++0x03
line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
rgroup.long 0x5C8++0x03
line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
rgroup.long 0x5CC++0x03
line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
rgroup.long 0x5D0++0x03
line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
rgroup.long 0x5D4++0x03
line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
rgroup.long 0x5D8++0x03
line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
rgroup.long 0x5DC++0x03
line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0F)
group.long 0x5E0++0x03
line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
hexmask.long.byte 0x00 24.--31. 1. " INTID483  ,Interrupt ID483  Priority/Priority Byte Offset 483 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID482  ,Interrupt ID482   Priority/Priority Byte Offset 482 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID481  ,Interrupt ID481  Priority/Priority Byte Offset 481 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID480  ,Interrupt ID480   Priority/Priority Byte Offset 480 "
group.long 0x5E4++0x03
line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
hexmask.long.byte 0x00 24.--31. 1. " INTID487  ,Interrupt ID487  Priority/Priority Byte Offset 487 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID486  ,Interrupt ID486   Priority/Priority Byte Offset 486 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID485  ,Interrupt ID485  Priority/Priority Byte Offset 485 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID484  ,Interrupt ID484   Priority/Priority Byte Offset 484 "
group.long 0x5E8++0x03
line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
hexmask.long.byte 0x00 24.--31. 1. " INTID491  ,Interrupt ID491  Priority/Priority Byte Offset 491 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID490  ,Interrupt ID490   Priority/Priority Byte Offset 490 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID489  ,Interrupt ID489  Priority/Priority Byte Offset 489 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID488  ,Interrupt ID488   Priority/Priority Byte Offset 488 "
group.long 0x5EC++0x03
line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
hexmask.long.byte 0x00 24.--31. 1. " INTID495  ,Interrupt ID495  Priority/Priority Byte Offset 495 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID494  ,Interrupt ID494   Priority/Priority Byte Offset 494 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID493  ,Interrupt ID493  Priority/Priority Byte Offset 493 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID492  ,Interrupt ID492   Priority/Priority Byte Offset 492 "
group.long 0x5F0++0x03
line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
hexmask.long.byte 0x00 24.--31. 1. " INTID499  ,Interrupt ID499  Priority/Priority Byte Offset 499 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID498  ,Interrupt ID498   Priority/Priority Byte Offset 498 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID497  ,Interrupt ID497  Priority/Priority Byte Offset 497 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID496  ,Interrupt ID496   Priority/Priority Byte Offset 496 "
group.long 0x5F4++0x03
line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
hexmask.long.byte 0x00 24.--31. 1. " INTID503  ,Interrupt ID503  Priority/Priority Byte Offset 503 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID502  ,Interrupt ID502   Priority/Priority Byte Offset 502 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID501  ,Interrupt ID501  Priority/Priority Byte Offset 501 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID500  ,Interrupt ID500   Priority/Priority Byte Offset 500 "
group.long 0x5F8++0x03
line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
hexmask.long.byte 0x00 24.--31. 1. " INTID507  ,Interrupt ID507  Priority/Priority Byte Offset 507 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID506  ,Interrupt ID506   Priority/Priority Byte Offset 506 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID505  ,Interrupt ID505  Priority/Priority Byte Offset 505 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID504  ,Interrupt ID504   Priority/Priority Byte Offset 504 "
group.long 0x5FC++0x03
line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
hexmask.long.byte 0x00 24.--31. 1. " INTID511  ,Interrupt ID511  Priority/Priority Byte Offset 511 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID510  ,Interrupt ID510   Priority/Priority Byte Offset 510 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID509  ,Interrupt ID509  Priority/Priority Byte Offset 509 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID508  ,Interrupt ID508   Priority/Priority Byte Offset 508 "
else
rgroup.long 0x5E0++0x03
line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
rgroup.long 0x5E4++0x03
line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
rgroup.long 0x5E8++0x03
line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
rgroup.long 0x5EC++0x03
line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
rgroup.long 0x5F0++0x03
line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
rgroup.long 0x5F4++0x03
line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
rgroup.long 0x5F8++0x03
line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
rgroup.long 0x5FC++0x03
line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x10)
group.long 0x600++0x03
line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
hexmask.long.byte 0x00 24.--31. 1. " INTID515  ,Interrupt ID515  Priority/Priority Byte Offset 515 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID514  ,Interrupt ID514   Priority/Priority Byte Offset 514 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID513  ,Interrupt ID513  Priority/Priority Byte Offset 513 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID512  ,Interrupt ID512   Priority/Priority Byte Offset 512 "
group.long 0x604++0x03
line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
hexmask.long.byte 0x00 24.--31. 1. " INTID519  ,Interrupt ID519  Priority/Priority Byte Offset 519 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID518  ,Interrupt ID518   Priority/Priority Byte Offset 518 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID517  ,Interrupt ID517  Priority/Priority Byte Offset 517 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID516  ,Interrupt ID516   Priority/Priority Byte Offset 516 "
group.long 0x608++0x03
line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
hexmask.long.byte 0x00 24.--31. 1. " INTID523  ,Interrupt ID523  Priority/Priority Byte Offset 523 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID522  ,Interrupt ID522   Priority/Priority Byte Offset 522 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID521  ,Interrupt ID521  Priority/Priority Byte Offset 521 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID520  ,Interrupt ID520   Priority/Priority Byte Offset 520 "
group.long 0x60C++0x03
line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
hexmask.long.byte 0x00 24.--31. 1. " INTID527  ,Interrupt ID527  Priority/Priority Byte Offset 527 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID526  ,Interrupt ID526   Priority/Priority Byte Offset 526 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID525  ,Interrupt ID525  Priority/Priority Byte Offset 525 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID524  ,Interrupt ID524   Priority/Priority Byte Offset 524 "
group.long 0x610++0x03
line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
hexmask.long.byte 0x00 24.--31. 1. " INTID531  ,Interrupt ID531  Priority/Priority Byte Offset 531 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID530  ,Interrupt ID530   Priority/Priority Byte Offset 530 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID529  ,Interrupt ID529  Priority/Priority Byte Offset 529 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID528  ,Interrupt ID528   Priority/Priority Byte Offset 528 "
group.long 0x614++0x03
line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
hexmask.long.byte 0x00 24.--31. 1. " INTID535  ,Interrupt ID535  Priority/Priority Byte Offset 535 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID534  ,Interrupt ID534   Priority/Priority Byte Offset 534 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID533  ,Interrupt ID533  Priority/Priority Byte Offset 533 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID532  ,Interrupt ID532   Priority/Priority Byte Offset 532 "
group.long 0x618++0x03
line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
hexmask.long.byte 0x00 24.--31. 1. " INTID539  ,Interrupt ID539  Priority/Priority Byte Offset 539 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID538  ,Interrupt ID538   Priority/Priority Byte Offset 538 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID537  ,Interrupt ID537  Priority/Priority Byte Offset 537 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID536  ,Interrupt ID536   Priority/Priority Byte Offset 536 "
group.long 0x61C++0x03
line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
hexmask.long.byte 0x00 24.--31. 1. " INTID543  ,Interrupt ID543  Priority/Priority Byte Offset 543 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID542  ,Interrupt ID542   Priority/Priority Byte Offset 542 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID541  ,Interrupt ID541  Priority/Priority Byte Offset 541 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID540  ,Interrupt ID540   Priority/Priority Byte Offset 540 "
else
rgroup.long 0x600++0x03
line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
rgroup.long 0x604++0x03
line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
rgroup.long 0x608++0x03
line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
rgroup.long 0x60C++0x03
line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
rgroup.long 0x610++0x03
line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
rgroup.long 0x614++0x03
line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
rgroup.long 0x618++0x03
line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
rgroup.long 0x61C++0x03
line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x11)
group.long 0x620++0x03
line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
hexmask.long.byte 0x00 24.--31. 1. " INTID547  ,Interrupt ID547  Priority/Priority Byte Offset 547 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID546  ,Interrupt ID546   Priority/Priority Byte Offset 546 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID545  ,Interrupt ID545  Priority/Priority Byte Offset 545 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID544  ,Interrupt ID544   Priority/Priority Byte Offset 544 "
group.long 0x624++0x03
line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
hexmask.long.byte 0x00 24.--31. 1. " INTID551  ,Interrupt ID551  Priority/Priority Byte Offset 551 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID550  ,Interrupt ID550   Priority/Priority Byte Offset 550 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID549  ,Interrupt ID549  Priority/Priority Byte Offset 549 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID548  ,Interrupt ID548   Priority/Priority Byte Offset 548 "
group.long 0x628++0x03
line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
hexmask.long.byte 0x00 24.--31. 1. " INTID555  ,Interrupt ID555  Priority/Priority Byte Offset 555 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID554  ,Interrupt ID554   Priority/Priority Byte Offset 554 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID553  ,Interrupt ID553  Priority/Priority Byte Offset 553 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID552  ,Interrupt ID552   Priority/Priority Byte Offset 552 "
group.long 0x62C++0x03
line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
hexmask.long.byte 0x00 24.--31. 1. " INTID559  ,Interrupt ID559  Priority/Priority Byte Offset 559 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID558  ,Interrupt ID558   Priority/Priority Byte Offset 558 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID557  ,Interrupt ID557  Priority/Priority Byte Offset 557 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID556  ,Interrupt ID556   Priority/Priority Byte Offset 556 "
group.long 0x630++0x03
line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
hexmask.long.byte 0x00 24.--31. 1. " INTID563  ,Interrupt ID563  Priority/Priority Byte Offset 563 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID562  ,Interrupt ID562   Priority/Priority Byte Offset 562 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID561  ,Interrupt ID561  Priority/Priority Byte Offset 561 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID560  ,Interrupt ID560   Priority/Priority Byte Offset 560 "
group.long 0x634++0x03
line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
hexmask.long.byte 0x00 24.--31. 1. " INTID567  ,Interrupt ID567  Priority/Priority Byte Offset 567 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID566  ,Interrupt ID566   Priority/Priority Byte Offset 566 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID565  ,Interrupt ID565  Priority/Priority Byte Offset 565 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID564  ,Interrupt ID564   Priority/Priority Byte Offset 564 "
group.long 0x638++0x03
line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
hexmask.long.byte 0x00 24.--31. 1. " INTID571  ,Interrupt ID571  Priority/Priority Byte Offset 571 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID570  ,Interrupt ID570   Priority/Priority Byte Offset 570 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID569  ,Interrupt ID569  Priority/Priority Byte Offset 569 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID568  ,Interrupt ID568   Priority/Priority Byte Offset 568 "
group.long 0x63C++0x03
line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
hexmask.long.byte 0x00 24.--31. 1. " INTID575  ,Interrupt ID575  Priority/Priority Byte Offset 575 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID574  ,Interrupt ID574   Priority/Priority Byte Offset 574 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID573  ,Interrupt ID573  Priority/Priority Byte Offset 573 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID572  ,Interrupt ID572   Priority/Priority Byte Offset 572 "
else
rgroup.long 0x620++0x03
line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
rgroup.long 0x624++0x03
line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
rgroup.long 0x628++0x03
line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
rgroup.long 0x62C++0x03
line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
rgroup.long 0x630++0x03
line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
rgroup.long 0x634++0x03
line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
rgroup.long 0x638++0x03
line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
rgroup.long 0x63C++0x03
line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x12)
group.long 0x640++0x03
line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
hexmask.long.byte 0x00 24.--31. 1. " INTID579  ,Interrupt ID579  Priority/Priority Byte Offset 579 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID578  ,Interrupt ID578   Priority/Priority Byte Offset 578 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID577  ,Interrupt ID577  Priority/Priority Byte Offset 577 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID576  ,Interrupt ID576   Priority/Priority Byte Offset 576 "
group.long 0x644++0x03
line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
hexmask.long.byte 0x00 24.--31. 1. " INTID583  ,Interrupt ID583  Priority/Priority Byte Offset 583 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID582  ,Interrupt ID582   Priority/Priority Byte Offset 582 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID581  ,Interrupt ID581  Priority/Priority Byte Offset 581 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID580  ,Interrupt ID580   Priority/Priority Byte Offset 580 "
group.long 0x648++0x03
line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
hexmask.long.byte 0x00 24.--31. 1. " INTID587  ,Interrupt ID587  Priority/Priority Byte Offset 587 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID586  ,Interrupt ID586   Priority/Priority Byte Offset 586 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID585  ,Interrupt ID585  Priority/Priority Byte Offset 585 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID584  ,Interrupt ID584   Priority/Priority Byte Offset 584 "
group.long 0x64C++0x03
line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
hexmask.long.byte 0x00 24.--31. 1. " INTID591  ,Interrupt ID591  Priority/Priority Byte Offset 591 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID590  ,Interrupt ID590   Priority/Priority Byte Offset 590 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID589  ,Interrupt ID589  Priority/Priority Byte Offset 589 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID588  ,Interrupt ID588   Priority/Priority Byte Offset 588 "
group.long 0x650++0x03
line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
hexmask.long.byte 0x00 24.--31. 1. " INTID595  ,Interrupt ID595  Priority/Priority Byte Offset 595 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID594  ,Interrupt ID594   Priority/Priority Byte Offset 594 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID593  ,Interrupt ID593  Priority/Priority Byte Offset 593 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID592  ,Interrupt ID592   Priority/Priority Byte Offset 592 "
group.long 0x654++0x03
line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
hexmask.long.byte 0x00 24.--31. 1. " INTID599  ,Interrupt ID599  Priority/Priority Byte Offset 599 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID598  ,Interrupt ID598   Priority/Priority Byte Offset 598 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID597  ,Interrupt ID597  Priority/Priority Byte Offset 597 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID596  ,Interrupt ID596   Priority/Priority Byte Offset 596 "
group.long 0x658++0x03
line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
hexmask.long.byte 0x00 24.--31. 1. " INTID603  ,Interrupt ID603  Priority/Priority Byte Offset 603 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID602  ,Interrupt ID602   Priority/Priority Byte Offset 602 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID601  ,Interrupt ID601  Priority/Priority Byte Offset 601 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID600  ,Interrupt ID600   Priority/Priority Byte Offset 600 "
group.long 0x65C++0x03
line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
hexmask.long.byte 0x00 24.--31. 1. " INTID607  ,Interrupt ID607  Priority/Priority Byte Offset 607 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID606  ,Interrupt ID606   Priority/Priority Byte Offset 606 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID605  ,Interrupt ID605  Priority/Priority Byte Offset 605 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID604  ,Interrupt ID604   Priority/Priority Byte Offset 604 "
else
rgroup.long 0x640++0x03
line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
rgroup.long 0x644++0x03
line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
rgroup.long 0x648++0x03
line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
rgroup.long 0x64C++0x03
line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
rgroup.long 0x650++0x03
line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
rgroup.long 0x654++0x03
line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
rgroup.long 0x658++0x03
line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
rgroup.long 0x65C++0x03
line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x13)
group.long 0x660++0x03
line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
hexmask.long.byte 0x00 24.--31. 1. " INTID611  ,Interrupt ID611  Priority/Priority Byte Offset 611 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID610  ,Interrupt ID610   Priority/Priority Byte Offset 610 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID609  ,Interrupt ID609  Priority/Priority Byte Offset 609 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID608  ,Interrupt ID608   Priority/Priority Byte Offset 608 "
group.long 0x664++0x03
line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
hexmask.long.byte 0x00 24.--31. 1. " INTID615  ,Interrupt ID615  Priority/Priority Byte Offset 615 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID614  ,Interrupt ID614   Priority/Priority Byte Offset 614 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID613  ,Interrupt ID613  Priority/Priority Byte Offset 613 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID612  ,Interrupt ID612   Priority/Priority Byte Offset 612 "
group.long 0x668++0x03
line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
hexmask.long.byte 0x00 24.--31. 1. " INTID619  ,Interrupt ID619  Priority/Priority Byte Offset 619 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID618  ,Interrupt ID618   Priority/Priority Byte Offset 618 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID617  ,Interrupt ID617  Priority/Priority Byte Offset 617 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID616  ,Interrupt ID616   Priority/Priority Byte Offset 616 "
group.long 0x66C++0x03
line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
hexmask.long.byte 0x00 24.--31. 1. " INTID623  ,Interrupt ID623  Priority/Priority Byte Offset 623 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID622  ,Interrupt ID622   Priority/Priority Byte Offset 622 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID621  ,Interrupt ID621  Priority/Priority Byte Offset 621 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID620  ,Interrupt ID620   Priority/Priority Byte Offset 620 "
group.long 0x670++0x03
line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
hexmask.long.byte 0x00 24.--31. 1. " INTID627  ,Interrupt ID627  Priority/Priority Byte Offset 627 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID626  ,Interrupt ID626   Priority/Priority Byte Offset 626 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID625  ,Interrupt ID625  Priority/Priority Byte Offset 625 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID624  ,Interrupt ID624   Priority/Priority Byte Offset 624 "
group.long 0x674++0x03
line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
hexmask.long.byte 0x00 24.--31. 1. " INTID631  ,Interrupt ID631  Priority/Priority Byte Offset 631 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID630  ,Interrupt ID630   Priority/Priority Byte Offset 630 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID629  ,Interrupt ID629  Priority/Priority Byte Offset 629 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID628  ,Interrupt ID628   Priority/Priority Byte Offset 628 "
group.long 0x678++0x03
line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
hexmask.long.byte 0x00 24.--31. 1. " INTID635  ,Interrupt ID635  Priority/Priority Byte Offset 635 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID634  ,Interrupt ID634   Priority/Priority Byte Offset 634 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID633  ,Interrupt ID633  Priority/Priority Byte Offset 633 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID632  ,Interrupt ID632   Priority/Priority Byte Offset 632 "
group.long 0x67C++0x03
line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
hexmask.long.byte 0x00 24.--31. 1. " INTID639  ,Interrupt ID639  Priority/Priority Byte Offset 639 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID638  ,Interrupt ID638   Priority/Priority Byte Offset 638 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID637  ,Interrupt ID637  Priority/Priority Byte Offset 637 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID636  ,Interrupt ID636   Priority/Priority Byte Offset 636 "
else
rgroup.long 0x660++0x03
line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
rgroup.long 0x664++0x03
line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
rgroup.long 0x668++0x03
line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
rgroup.long 0x66C++0x03
line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
rgroup.long 0x670++0x03
line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
rgroup.long 0x674++0x03
line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
rgroup.long 0x678++0x03
line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
rgroup.long 0x67C++0x03
line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x14)
group.long 0x680++0x03
line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
hexmask.long.byte 0x00 24.--31. 1. " INTID643  ,Interrupt ID643  Priority/Priority Byte Offset 643 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID642  ,Interrupt ID642   Priority/Priority Byte Offset 642 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID641  ,Interrupt ID641  Priority/Priority Byte Offset 641 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID640  ,Interrupt ID640   Priority/Priority Byte Offset 640 "
group.long 0x684++0x03
line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
hexmask.long.byte 0x00 24.--31. 1. " INTID647  ,Interrupt ID647  Priority/Priority Byte Offset 647 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID646  ,Interrupt ID646   Priority/Priority Byte Offset 646 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID645  ,Interrupt ID645  Priority/Priority Byte Offset 645 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID644  ,Interrupt ID644   Priority/Priority Byte Offset 644 "
group.long 0x688++0x03
line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
hexmask.long.byte 0x00 24.--31. 1. " INTID651  ,Interrupt ID651  Priority/Priority Byte Offset 651 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID650  ,Interrupt ID650   Priority/Priority Byte Offset 650 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID649  ,Interrupt ID649  Priority/Priority Byte Offset 649 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID648  ,Interrupt ID648   Priority/Priority Byte Offset 648 "
group.long 0x68C++0x03
line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
hexmask.long.byte 0x00 24.--31. 1. " INTID655  ,Interrupt ID655  Priority/Priority Byte Offset 655 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID654  ,Interrupt ID654   Priority/Priority Byte Offset 654 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID653  ,Interrupt ID653  Priority/Priority Byte Offset 653 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID652  ,Interrupt ID652   Priority/Priority Byte Offset 652 "
group.long 0x690++0x03
line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
hexmask.long.byte 0x00 24.--31. 1. " INTID659  ,Interrupt ID659  Priority/Priority Byte Offset 659 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID658  ,Interrupt ID658   Priority/Priority Byte Offset 658 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID657  ,Interrupt ID657  Priority/Priority Byte Offset 657 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID656  ,Interrupt ID656   Priority/Priority Byte Offset 656 "
group.long 0x694++0x03
line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
hexmask.long.byte 0x00 24.--31. 1. " INTID663  ,Interrupt ID663  Priority/Priority Byte Offset 663 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID662  ,Interrupt ID662   Priority/Priority Byte Offset 662 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID661  ,Interrupt ID661  Priority/Priority Byte Offset 661 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID660  ,Interrupt ID660   Priority/Priority Byte Offset 660 "
group.long 0x698++0x03
line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
hexmask.long.byte 0x00 24.--31. 1. " INTID667  ,Interrupt ID667  Priority/Priority Byte Offset 667 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID666  ,Interrupt ID666   Priority/Priority Byte Offset 666 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID665  ,Interrupt ID665  Priority/Priority Byte Offset 665 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID664  ,Interrupt ID664   Priority/Priority Byte Offset 664 "
group.long 0x69C++0x03
line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
hexmask.long.byte 0x00 24.--31. 1. " INTID671  ,Interrupt ID671  Priority/Priority Byte Offset 671 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID670  ,Interrupt ID670   Priority/Priority Byte Offset 670 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID669  ,Interrupt ID669  Priority/Priority Byte Offset 669 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID668  ,Interrupt ID668   Priority/Priority Byte Offset 668 "
else
rgroup.long 0x680++0x03
line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
rgroup.long 0x684++0x03
line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
rgroup.long 0x688++0x03
line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
rgroup.long 0x68C++0x03
line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
rgroup.long 0x690++0x03
line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
rgroup.long 0x694++0x03
line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
rgroup.long 0x698++0x03
line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
rgroup.long 0x69C++0x03
line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x15)
group.long 0x6A0++0x03
line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
hexmask.long.byte 0x00 24.--31. 1. " INTID675  ,Interrupt ID675  Priority/Priority Byte Offset 675 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID674  ,Interrupt ID674   Priority/Priority Byte Offset 674 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID673  ,Interrupt ID673  Priority/Priority Byte Offset 673 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID672  ,Interrupt ID672   Priority/Priority Byte Offset 672 "
group.long 0x6A4++0x03
line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
hexmask.long.byte 0x00 24.--31. 1. " INTID679  ,Interrupt ID679  Priority/Priority Byte Offset 679 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID678  ,Interrupt ID678   Priority/Priority Byte Offset 678 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID677  ,Interrupt ID677  Priority/Priority Byte Offset 677 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID676  ,Interrupt ID676   Priority/Priority Byte Offset 676 "
group.long 0x6A8++0x03
line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
hexmask.long.byte 0x00 24.--31. 1. " INTID683  ,Interrupt ID683  Priority/Priority Byte Offset 683 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID682  ,Interrupt ID682   Priority/Priority Byte Offset 682 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID681  ,Interrupt ID681  Priority/Priority Byte Offset 681 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID680  ,Interrupt ID680   Priority/Priority Byte Offset 680 "
group.long 0x6AC++0x03
line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
hexmask.long.byte 0x00 24.--31. 1. " INTID687  ,Interrupt ID687  Priority/Priority Byte Offset 687 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID686  ,Interrupt ID686   Priority/Priority Byte Offset 686 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID685  ,Interrupt ID685  Priority/Priority Byte Offset 685 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID684  ,Interrupt ID684   Priority/Priority Byte Offset 684 "
group.long 0x6B0++0x03
line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
hexmask.long.byte 0x00 24.--31. 1. " INTID691  ,Interrupt ID691  Priority/Priority Byte Offset 691 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID690  ,Interrupt ID690   Priority/Priority Byte Offset 690 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID689  ,Interrupt ID689  Priority/Priority Byte Offset 689 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID688  ,Interrupt ID688   Priority/Priority Byte Offset 688 "
group.long 0x6B4++0x03
line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
hexmask.long.byte 0x00 24.--31. 1. " INTID695  ,Interrupt ID695  Priority/Priority Byte Offset 695 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID694  ,Interrupt ID694   Priority/Priority Byte Offset 694 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID693  ,Interrupt ID693  Priority/Priority Byte Offset 693 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID692  ,Interrupt ID692   Priority/Priority Byte Offset 692 "
group.long 0x6B8++0x03
line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
hexmask.long.byte 0x00 24.--31. 1. " INTID699  ,Interrupt ID699  Priority/Priority Byte Offset 699 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID698  ,Interrupt ID698   Priority/Priority Byte Offset 698 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID697  ,Interrupt ID697  Priority/Priority Byte Offset 697 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID696  ,Interrupt ID696   Priority/Priority Byte Offset 696 "
group.long 0x6BC++0x03
line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
hexmask.long.byte 0x00 24.--31. 1. " INTID703  ,Interrupt ID703  Priority/Priority Byte Offset 703 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID702  ,Interrupt ID702   Priority/Priority Byte Offset 702 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID701  ,Interrupt ID701  Priority/Priority Byte Offset 701 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID700  ,Interrupt ID700   Priority/Priority Byte Offset 700 "
else
rgroup.long 0x6A0++0x03
line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
rgroup.long 0x6A4++0x03
line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
rgroup.long 0x6A8++0x03
line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
rgroup.long 0x6AC++0x03
line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
rgroup.long 0x6B0++0x03
line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
rgroup.long 0x6B4++0x03
line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
rgroup.long 0x6B8++0x03
line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
rgroup.long 0x6BC++0x03
line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x16)
group.long 0x6C0++0x03
line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
hexmask.long.byte 0x00 24.--31. 1. " INTID707  ,Interrupt ID707  Priority/Priority Byte Offset 707 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID706  ,Interrupt ID706   Priority/Priority Byte Offset 706 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID705  ,Interrupt ID705  Priority/Priority Byte Offset 705 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID704  ,Interrupt ID704   Priority/Priority Byte Offset 704 "
group.long 0x6C4++0x03
line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
hexmask.long.byte 0x00 24.--31. 1. " INTID711  ,Interrupt ID711  Priority/Priority Byte Offset 711 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID710  ,Interrupt ID710   Priority/Priority Byte Offset 710 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID709  ,Interrupt ID709  Priority/Priority Byte Offset 709 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID708  ,Interrupt ID708   Priority/Priority Byte Offset 708 "
group.long 0x6C8++0x03
line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
hexmask.long.byte 0x00 24.--31. 1. " INTID715  ,Interrupt ID715  Priority/Priority Byte Offset 715 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID714  ,Interrupt ID714   Priority/Priority Byte Offset 714 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID713  ,Interrupt ID713  Priority/Priority Byte Offset 713 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID712  ,Interrupt ID712   Priority/Priority Byte Offset 712 "
group.long 0x6CC++0x03
line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
hexmask.long.byte 0x00 24.--31. 1. " INTID719  ,Interrupt ID719  Priority/Priority Byte Offset 719 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID718  ,Interrupt ID718   Priority/Priority Byte Offset 718 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID717  ,Interrupt ID717  Priority/Priority Byte Offset 717 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID716  ,Interrupt ID716   Priority/Priority Byte Offset 716 "
group.long 0x6D0++0x03
line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
hexmask.long.byte 0x00 24.--31. 1. " INTID723  ,Interrupt ID723  Priority/Priority Byte Offset 723 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID722  ,Interrupt ID722   Priority/Priority Byte Offset 722 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID721  ,Interrupt ID721  Priority/Priority Byte Offset 721 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID720  ,Interrupt ID720   Priority/Priority Byte Offset 720 "
group.long 0x6D4++0x03
line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
hexmask.long.byte 0x00 24.--31. 1. " INTID727  ,Interrupt ID727  Priority/Priority Byte Offset 727 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID726  ,Interrupt ID726   Priority/Priority Byte Offset 726 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID725  ,Interrupt ID725  Priority/Priority Byte Offset 725 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID724  ,Interrupt ID724   Priority/Priority Byte Offset 724 "
group.long 0x6D8++0x03
line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
hexmask.long.byte 0x00 24.--31. 1. " INTID731  ,Interrupt ID731  Priority/Priority Byte Offset 731 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID730  ,Interrupt ID730   Priority/Priority Byte Offset 730 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID729  ,Interrupt ID729  Priority/Priority Byte Offset 729 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID728  ,Interrupt ID728   Priority/Priority Byte Offset 728 "
group.long 0x6DC++0x03
line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
hexmask.long.byte 0x00 24.--31. 1. " INTID735  ,Interrupt ID735  Priority/Priority Byte Offset 735 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID734  ,Interrupt ID734   Priority/Priority Byte Offset 734 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID733  ,Interrupt ID733  Priority/Priority Byte Offset 733 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID732  ,Interrupt ID732   Priority/Priority Byte Offset 732 "
else
rgroup.long 0x6C0++0x03
line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
rgroup.long 0x6C4++0x03
line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
rgroup.long 0x6C8++0x03
line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
rgroup.long 0x6CC++0x03
line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
rgroup.long 0x6D0++0x03
line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
rgroup.long 0x6D4++0x03
line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
rgroup.long 0x6D8++0x03
line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
rgroup.long 0x6DC++0x03
line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x17)
group.long 0x6E0++0x03
line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
hexmask.long.byte 0x00 24.--31. 1. " INTID739  ,Interrupt ID739  Priority/Priority Byte Offset 739 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID738  ,Interrupt ID738   Priority/Priority Byte Offset 738 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID737  ,Interrupt ID737  Priority/Priority Byte Offset 737 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID736  ,Interrupt ID736   Priority/Priority Byte Offset 736 "
group.long 0x6E4++0x03
line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
hexmask.long.byte 0x00 24.--31. 1. " INTID743  ,Interrupt ID743  Priority/Priority Byte Offset 743 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID742  ,Interrupt ID742   Priority/Priority Byte Offset 742 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID741  ,Interrupt ID741  Priority/Priority Byte Offset 741 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID740  ,Interrupt ID740   Priority/Priority Byte Offset 740 "
group.long 0x6E8++0x03
line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
hexmask.long.byte 0x00 24.--31. 1. " INTID747  ,Interrupt ID747  Priority/Priority Byte Offset 747 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID746  ,Interrupt ID746   Priority/Priority Byte Offset 746 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID745  ,Interrupt ID745  Priority/Priority Byte Offset 745 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID744  ,Interrupt ID744   Priority/Priority Byte Offset 744 "
group.long 0x6EC++0x03
line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
hexmask.long.byte 0x00 24.--31. 1. " INTID751  ,Interrupt ID751  Priority/Priority Byte Offset 751 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID750  ,Interrupt ID750   Priority/Priority Byte Offset 750 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID749  ,Interrupt ID749  Priority/Priority Byte Offset 749 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID748  ,Interrupt ID748   Priority/Priority Byte Offset 748 "
group.long 0x6F0++0x03
line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
hexmask.long.byte 0x00 24.--31. 1. " INTID755  ,Interrupt ID755  Priority/Priority Byte Offset 755 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID754  ,Interrupt ID754   Priority/Priority Byte Offset 754 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID753  ,Interrupt ID753  Priority/Priority Byte Offset 753 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID752  ,Interrupt ID752   Priority/Priority Byte Offset 752 "
group.long 0x6F4++0x03
line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
hexmask.long.byte 0x00 24.--31. 1. " INTID759  ,Interrupt ID759  Priority/Priority Byte Offset 759 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID758  ,Interrupt ID758   Priority/Priority Byte Offset 758 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID757  ,Interrupt ID757  Priority/Priority Byte Offset 757 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID756  ,Interrupt ID756   Priority/Priority Byte Offset 756 "
group.long 0x6F8++0x03
line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
hexmask.long.byte 0x00 24.--31. 1. " INTID763  ,Interrupt ID763  Priority/Priority Byte Offset 763 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID762  ,Interrupt ID762   Priority/Priority Byte Offset 762 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID761  ,Interrupt ID761  Priority/Priority Byte Offset 761 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID760  ,Interrupt ID760   Priority/Priority Byte Offset 760 "
group.long 0x6FC++0x03
line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
hexmask.long.byte 0x00 24.--31. 1. " INTID767  ,Interrupt ID767  Priority/Priority Byte Offset 767 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID766  ,Interrupt ID766   Priority/Priority Byte Offset 766 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID765  ,Interrupt ID765  Priority/Priority Byte Offset 765 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID764  ,Interrupt ID764   Priority/Priority Byte Offset 764 "
else
rgroup.long 0x6E0++0x03
line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
rgroup.long 0x6E4++0x03
line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
rgroup.long 0x6E8++0x03
line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
rgroup.long 0x6EC++0x03
line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
rgroup.long 0x6F0++0x03
line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
rgroup.long 0x6F4++0x03
line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
rgroup.long 0x6F8++0x03
line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
rgroup.long 0x6FC++0x03
line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x18)
group.long 0x700++0x03
line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
hexmask.long.byte 0x00 24.--31. 1. " INTID771  ,Interrupt ID771  Priority/Priority Byte Offset 771 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID770  ,Interrupt ID770   Priority/Priority Byte Offset 770 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID769  ,Interrupt ID769  Priority/Priority Byte Offset 769 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID768  ,Interrupt ID768   Priority/Priority Byte Offset 768 "
group.long 0x704++0x03
line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
hexmask.long.byte 0x00 24.--31. 1. " INTID775  ,Interrupt ID775  Priority/Priority Byte Offset 775 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID774  ,Interrupt ID774   Priority/Priority Byte Offset 774 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID773  ,Interrupt ID773  Priority/Priority Byte Offset 773 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID772  ,Interrupt ID772   Priority/Priority Byte Offset 772 "
group.long 0x708++0x03
line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
hexmask.long.byte 0x00 24.--31. 1. " INTID779  ,Interrupt ID779  Priority/Priority Byte Offset 779 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID778  ,Interrupt ID778   Priority/Priority Byte Offset 778 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID777  ,Interrupt ID777  Priority/Priority Byte Offset 777 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID776  ,Interrupt ID776   Priority/Priority Byte Offset 776 "
group.long 0x70C++0x03
line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
hexmask.long.byte 0x00 24.--31. 1. " INTID783  ,Interrupt ID783  Priority/Priority Byte Offset 783 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID782  ,Interrupt ID782   Priority/Priority Byte Offset 782 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID781  ,Interrupt ID781  Priority/Priority Byte Offset 781 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID780  ,Interrupt ID780   Priority/Priority Byte Offset 780 "
group.long 0x710++0x03
line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
hexmask.long.byte 0x00 24.--31. 1. " INTID787  ,Interrupt ID787  Priority/Priority Byte Offset 787 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID786  ,Interrupt ID786   Priority/Priority Byte Offset 786 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID785  ,Interrupt ID785  Priority/Priority Byte Offset 785 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID784  ,Interrupt ID784   Priority/Priority Byte Offset 784 "
group.long 0x714++0x03
line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
hexmask.long.byte 0x00 24.--31. 1. " INTID791  ,Interrupt ID791  Priority/Priority Byte Offset 791 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID790  ,Interrupt ID790   Priority/Priority Byte Offset 790 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID789  ,Interrupt ID789  Priority/Priority Byte Offset 789 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID788  ,Interrupt ID788   Priority/Priority Byte Offset 788 "
group.long 0x718++0x03
line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
hexmask.long.byte 0x00 24.--31. 1. " INTID795  ,Interrupt ID795  Priority/Priority Byte Offset 795 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID794  ,Interrupt ID794   Priority/Priority Byte Offset 794 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID793  ,Interrupt ID793  Priority/Priority Byte Offset 793 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID792  ,Interrupt ID792   Priority/Priority Byte Offset 792 "
group.long 0x71C++0x03
line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
hexmask.long.byte 0x00 24.--31. 1. " INTID799  ,Interrupt ID799  Priority/Priority Byte Offset 799 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID798  ,Interrupt ID798   Priority/Priority Byte Offset 798 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID797  ,Interrupt ID797  Priority/Priority Byte Offset 797 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID796  ,Interrupt ID796   Priority/Priority Byte Offset 796 "
else
rgroup.long 0x700++0x03
line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
rgroup.long 0x704++0x03
line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
rgroup.long 0x708++0x03
line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
rgroup.long 0x70C++0x03
line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
rgroup.long 0x710++0x03
line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
rgroup.long 0x714++0x03
line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
rgroup.long 0x718++0x03
line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
rgroup.long 0x71C++0x03
line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x19)
group.long 0x720++0x03
line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
hexmask.long.byte 0x00 24.--31. 1. " INTID803  ,Interrupt ID803  Priority/Priority Byte Offset 803 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID802  ,Interrupt ID802   Priority/Priority Byte Offset 802 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID801  ,Interrupt ID801  Priority/Priority Byte Offset 801 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID800  ,Interrupt ID800   Priority/Priority Byte Offset 800 "
group.long 0x724++0x03
line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
hexmask.long.byte 0x00 24.--31. 1. " INTID807  ,Interrupt ID807  Priority/Priority Byte Offset 807 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID806  ,Interrupt ID806   Priority/Priority Byte Offset 806 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID805  ,Interrupt ID805  Priority/Priority Byte Offset 805 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID804  ,Interrupt ID804   Priority/Priority Byte Offset 804 "
group.long 0x728++0x03
line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
hexmask.long.byte 0x00 24.--31. 1. " INTID811  ,Interrupt ID811  Priority/Priority Byte Offset 811 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID810  ,Interrupt ID810   Priority/Priority Byte Offset 810 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID809  ,Interrupt ID809  Priority/Priority Byte Offset 809 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID808  ,Interrupt ID808   Priority/Priority Byte Offset 808 "
group.long 0x72C++0x03
line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
hexmask.long.byte 0x00 24.--31. 1. " INTID815  ,Interrupt ID815  Priority/Priority Byte Offset 815 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID814  ,Interrupt ID814   Priority/Priority Byte Offset 814 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID813  ,Interrupt ID813  Priority/Priority Byte Offset 813 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID812  ,Interrupt ID812   Priority/Priority Byte Offset 812 "
group.long 0x730++0x03
line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
hexmask.long.byte 0x00 24.--31. 1. " INTID819  ,Interrupt ID819  Priority/Priority Byte Offset 819 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID818  ,Interrupt ID818   Priority/Priority Byte Offset 818 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID817  ,Interrupt ID817  Priority/Priority Byte Offset 817 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID816  ,Interrupt ID816   Priority/Priority Byte Offset 816 "
group.long 0x734++0x03
line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
hexmask.long.byte 0x00 24.--31. 1. " INTID823  ,Interrupt ID823  Priority/Priority Byte Offset 823 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID822  ,Interrupt ID822   Priority/Priority Byte Offset 822 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID821  ,Interrupt ID821  Priority/Priority Byte Offset 821 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID820  ,Interrupt ID820   Priority/Priority Byte Offset 820 "
group.long 0x738++0x03
line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
hexmask.long.byte 0x00 24.--31. 1. " INTID827  ,Interrupt ID827  Priority/Priority Byte Offset 827 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID826  ,Interrupt ID826   Priority/Priority Byte Offset 826 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID825  ,Interrupt ID825  Priority/Priority Byte Offset 825 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID824  ,Interrupt ID824   Priority/Priority Byte Offset 824 "
group.long 0x73C++0x03
line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
hexmask.long.byte 0x00 24.--31. 1. " INTID831  ,Interrupt ID831  Priority/Priority Byte Offset 831 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID830  ,Interrupt ID830   Priority/Priority Byte Offset 830 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID829  ,Interrupt ID829  Priority/Priority Byte Offset 829 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID828  ,Interrupt ID828   Priority/Priority Byte Offset 828 "
else
rgroup.long 0x720++0x03
line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
rgroup.long 0x724++0x03
line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
rgroup.long 0x728++0x03
line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
rgroup.long 0x72C++0x03
line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
rgroup.long 0x730++0x03
line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
rgroup.long 0x734++0x03
line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
rgroup.long 0x738++0x03
line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
rgroup.long 0x73C++0x03
line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1A)
group.long 0x740++0x03
line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
hexmask.long.byte 0x00 24.--31. 1. " INTID835  ,Interrupt ID835  Priority/Priority Byte Offset 835 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID834  ,Interrupt ID834   Priority/Priority Byte Offset 834 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID833  ,Interrupt ID833  Priority/Priority Byte Offset 833 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID832  ,Interrupt ID832   Priority/Priority Byte Offset 832 "
group.long 0x744++0x03
line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
hexmask.long.byte 0x00 24.--31. 1. " INTID839  ,Interrupt ID839  Priority/Priority Byte Offset 839 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID838  ,Interrupt ID838   Priority/Priority Byte Offset 838 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID837  ,Interrupt ID837  Priority/Priority Byte Offset 837 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID836  ,Interrupt ID836   Priority/Priority Byte Offset 836 "
group.long 0x748++0x03
line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
hexmask.long.byte 0x00 24.--31. 1. " INTID843  ,Interrupt ID843  Priority/Priority Byte Offset 843 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID842  ,Interrupt ID842   Priority/Priority Byte Offset 842 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID841  ,Interrupt ID841  Priority/Priority Byte Offset 841 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID840  ,Interrupt ID840   Priority/Priority Byte Offset 840 "
group.long 0x74C++0x03
line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
hexmask.long.byte 0x00 24.--31. 1. " INTID847  ,Interrupt ID847  Priority/Priority Byte Offset 847 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID846  ,Interrupt ID846   Priority/Priority Byte Offset 846 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID845  ,Interrupt ID845  Priority/Priority Byte Offset 845 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID844  ,Interrupt ID844   Priority/Priority Byte Offset 844 "
group.long 0x750++0x03
line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
hexmask.long.byte 0x00 24.--31. 1. " INTID851  ,Interrupt ID851  Priority/Priority Byte Offset 851 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID850  ,Interrupt ID850   Priority/Priority Byte Offset 850 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID849  ,Interrupt ID849  Priority/Priority Byte Offset 849 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID848  ,Interrupt ID848   Priority/Priority Byte Offset 848 "
group.long 0x754++0x03
line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
hexmask.long.byte 0x00 24.--31. 1. " INTID855  ,Interrupt ID855  Priority/Priority Byte Offset 855 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID854  ,Interrupt ID854   Priority/Priority Byte Offset 854 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID853  ,Interrupt ID853  Priority/Priority Byte Offset 853 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID852  ,Interrupt ID852   Priority/Priority Byte Offset 852 "
group.long 0x758++0x03
line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
hexmask.long.byte 0x00 24.--31. 1. " INTID859  ,Interrupt ID859  Priority/Priority Byte Offset 859 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID858  ,Interrupt ID858   Priority/Priority Byte Offset 858 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID857  ,Interrupt ID857  Priority/Priority Byte Offset 857 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID856  ,Interrupt ID856   Priority/Priority Byte Offset 856 "
group.long 0x75C++0x03
line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
hexmask.long.byte 0x00 24.--31. 1. " INTID863  ,Interrupt ID863  Priority/Priority Byte Offset 863 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID862  ,Interrupt ID862   Priority/Priority Byte Offset 862 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID861  ,Interrupt ID861  Priority/Priority Byte Offset 861 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID860  ,Interrupt ID860   Priority/Priority Byte Offset 860 "
else
rgroup.long 0x740++0x03
line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
rgroup.long 0x744++0x03
line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
rgroup.long 0x748++0x03
line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
rgroup.long 0x74C++0x03
line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
rgroup.long 0x750++0x03
line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
rgroup.long 0x754++0x03
line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
rgroup.long 0x758++0x03
line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
rgroup.long 0x75C++0x03
line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1B)
group.long 0x760++0x03
line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
hexmask.long.byte 0x00 24.--31. 1. " INTID867  ,Interrupt ID867  Priority/Priority Byte Offset 867 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID866  ,Interrupt ID866   Priority/Priority Byte Offset 866 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID865  ,Interrupt ID865  Priority/Priority Byte Offset 865 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID864  ,Interrupt ID864   Priority/Priority Byte Offset 864 "
group.long 0x764++0x03
line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
hexmask.long.byte 0x00 24.--31. 1. " INTID871  ,Interrupt ID871  Priority/Priority Byte Offset 871 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID870  ,Interrupt ID870   Priority/Priority Byte Offset 870 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID869  ,Interrupt ID869  Priority/Priority Byte Offset 869 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID868  ,Interrupt ID868   Priority/Priority Byte Offset 868 "
group.long 0x768++0x03
line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
hexmask.long.byte 0x00 24.--31. 1. " INTID875  ,Interrupt ID875  Priority/Priority Byte Offset 875 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID874  ,Interrupt ID874   Priority/Priority Byte Offset 874 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID873  ,Interrupt ID873  Priority/Priority Byte Offset 873 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID872  ,Interrupt ID872   Priority/Priority Byte Offset 872 "
group.long 0x76C++0x03
line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
hexmask.long.byte 0x00 24.--31. 1. " INTID879  ,Interrupt ID879  Priority/Priority Byte Offset 879 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID878  ,Interrupt ID878   Priority/Priority Byte Offset 878 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID877  ,Interrupt ID877  Priority/Priority Byte Offset 877 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID876  ,Interrupt ID876   Priority/Priority Byte Offset 876 "
group.long 0x770++0x03
line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
hexmask.long.byte 0x00 24.--31. 1. " INTID883  ,Interrupt ID883  Priority/Priority Byte Offset 883 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID882  ,Interrupt ID882   Priority/Priority Byte Offset 882 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID881  ,Interrupt ID881  Priority/Priority Byte Offset 881 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID880  ,Interrupt ID880   Priority/Priority Byte Offset 880 "
group.long 0x774++0x03
line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
hexmask.long.byte 0x00 24.--31. 1. " INTID887  ,Interrupt ID887  Priority/Priority Byte Offset 887 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID886  ,Interrupt ID886   Priority/Priority Byte Offset 886 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID885  ,Interrupt ID885  Priority/Priority Byte Offset 885 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID884  ,Interrupt ID884   Priority/Priority Byte Offset 884 "
group.long 0x778++0x03
line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
hexmask.long.byte 0x00 24.--31. 1. " INTID891  ,Interrupt ID891  Priority/Priority Byte Offset 891 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID890  ,Interrupt ID890   Priority/Priority Byte Offset 890 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID889  ,Interrupt ID889  Priority/Priority Byte Offset 889 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID888  ,Interrupt ID888   Priority/Priority Byte Offset 888 "
group.long 0x77C++0x03
line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
hexmask.long.byte 0x00 24.--31. 1. " INTID895  ,Interrupt ID895  Priority/Priority Byte Offset 895 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID894  ,Interrupt ID894   Priority/Priority Byte Offset 894 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID893  ,Interrupt ID893  Priority/Priority Byte Offset 893 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID892  ,Interrupt ID892   Priority/Priority Byte Offset 892 "
else
rgroup.long 0x760++0x03
line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
rgroup.long 0x764++0x03
line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
rgroup.long 0x768++0x03
line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
rgroup.long 0x76C++0x03
line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
rgroup.long 0x770++0x03
line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
rgroup.long 0x774++0x03
line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
rgroup.long 0x778++0x03
line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
rgroup.long 0x77C++0x03
line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1C)
group.long 0x780++0x03
line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
hexmask.long.byte 0x00 24.--31. 1. " INTID899  ,Interrupt ID899  Priority/Priority Byte Offset 899 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID898  ,Interrupt ID898   Priority/Priority Byte Offset 898 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID897  ,Interrupt ID897  Priority/Priority Byte Offset 897 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID896  ,Interrupt ID896   Priority/Priority Byte Offset 896 "
group.long 0x784++0x03
line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
hexmask.long.byte 0x00 24.--31. 1. " INTID903  ,Interrupt ID903  Priority/Priority Byte Offset 903 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID902  ,Interrupt ID902   Priority/Priority Byte Offset 902 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID901  ,Interrupt ID901  Priority/Priority Byte Offset 901 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID900  ,Interrupt ID900   Priority/Priority Byte Offset 900 "
group.long 0x788++0x03
line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
hexmask.long.byte 0x00 24.--31. 1. " INTID907  ,Interrupt ID907  Priority/Priority Byte Offset 907 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID906  ,Interrupt ID906   Priority/Priority Byte Offset 906 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID905  ,Interrupt ID905  Priority/Priority Byte Offset 905 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID904  ,Interrupt ID904   Priority/Priority Byte Offset 904 "
group.long 0x78C++0x03
line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
hexmask.long.byte 0x00 24.--31. 1. " INTID911  ,Interrupt ID911  Priority/Priority Byte Offset 911 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID910  ,Interrupt ID910   Priority/Priority Byte Offset 910 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID909  ,Interrupt ID909  Priority/Priority Byte Offset 909 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID908  ,Interrupt ID908   Priority/Priority Byte Offset 908 "
group.long 0x790++0x03
line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
hexmask.long.byte 0x00 24.--31. 1. " INTID915  ,Interrupt ID915  Priority/Priority Byte Offset 915 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID914  ,Interrupt ID914   Priority/Priority Byte Offset 914 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID913  ,Interrupt ID913  Priority/Priority Byte Offset 913 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID912  ,Interrupt ID912   Priority/Priority Byte Offset 912 "
group.long 0x794++0x03
line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
hexmask.long.byte 0x00 24.--31. 1. " INTID919  ,Interrupt ID919  Priority/Priority Byte Offset 919 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID918  ,Interrupt ID918   Priority/Priority Byte Offset 918 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID917  ,Interrupt ID917  Priority/Priority Byte Offset 917 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID916  ,Interrupt ID916   Priority/Priority Byte Offset 916 "
group.long 0x798++0x03
line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
hexmask.long.byte 0x00 24.--31. 1. " INTID923  ,Interrupt ID923  Priority/Priority Byte Offset 923 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID922  ,Interrupt ID922   Priority/Priority Byte Offset 922 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID921  ,Interrupt ID921  Priority/Priority Byte Offset 921 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID920  ,Interrupt ID920   Priority/Priority Byte Offset 920 "
group.long 0x79C++0x03
line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
hexmask.long.byte 0x00 24.--31. 1. " INTID927  ,Interrupt ID927  Priority/Priority Byte Offset 927 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID926  ,Interrupt ID926   Priority/Priority Byte Offset 926 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID925  ,Interrupt ID925  Priority/Priority Byte Offset 925 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID924  ,Interrupt ID924   Priority/Priority Byte Offset 924 "
else
rgroup.long 0x780++0x03
line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
rgroup.long 0x784++0x03
line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
rgroup.long 0x788++0x03
line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
rgroup.long 0x78C++0x03
line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
rgroup.long 0x790++0x03
line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
rgroup.long 0x794++0x03
line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
rgroup.long 0x798++0x03
line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
rgroup.long 0x79C++0x03
line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1D)
group.long 0x7A0++0x03
line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
hexmask.long.byte 0x00 24.--31. 1. " INTID931  ,Interrupt ID931  Priority/Priority Byte Offset 931 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID930  ,Interrupt ID930   Priority/Priority Byte Offset 930 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID929  ,Interrupt ID929  Priority/Priority Byte Offset 929 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID928  ,Interrupt ID928   Priority/Priority Byte Offset 928 "
group.long 0x7A4++0x03
line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
hexmask.long.byte 0x00 24.--31. 1. " INTID935  ,Interrupt ID935  Priority/Priority Byte Offset 935 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID934  ,Interrupt ID934   Priority/Priority Byte Offset 934 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID933  ,Interrupt ID933  Priority/Priority Byte Offset 933 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID932  ,Interrupt ID932   Priority/Priority Byte Offset 932 "
group.long 0x7A8++0x03
line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
hexmask.long.byte 0x00 24.--31. 1. " INTID939  ,Interrupt ID939  Priority/Priority Byte Offset 939 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID938  ,Interrupt ID938   Priority/Priority Byte Offset 938 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID937  ,Interrupt ID937  Priority/Priority Byte Offset 937 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID936  ,Interrupt ID936   Priority/Priority Byte Offset 936 "
group.long 0x7AC++0x03
line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
hexmask.long.byte 0x00 24.--31. 1. " INTID943  ,Interrupt ID943  Priority/Priority Byte Offset 943 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID942  ,Interrupt ID942   Priority/Priority Byte Offset 942 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID941  ,Interrupt ID941  Priority/Priority Byte Offset 941 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID940  ,Interrupt ID940   Priority/Priority Byte Offset 940 "
group.long 0x7B0++0x03
line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
hexmask.long.byte 0x00 24.--31. 1. " INTID947  ,Interrupt ID947  Priority/Priority Byte Offset 947 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID946  ,Interrupt ID946   Priority/Priority Byte Offset 946 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID945  ,Interrupt ID945  Priority/Priority Byte Offset 945 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID944  ,Interrupt ID944   Priority/Priority Byte Offset 944 "
group.long 0x7B4++0x03
line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
hexmask.long.byte 0x00 24.--31. 1. " INTID951  ,Interrupt ID951  Priority/Priority Byte Offset 951 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID950  ,Interrupt ID950   Priority/Priority Byte Offset 950 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID949  ,Interrupt ID949  Priority/Priority Byte Offset 949 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID948  ,Interrupt ID948   Priority/Priority Byte Offset 948 "
group.long 0x7B8++0x03
line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
hexmask.long.byte 0x00 24.--31. 1. " INTID955  ,Interrupt ID955  Priority/Priority Byte Offset 955 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID954  ,Interrupt ID954   Priority/Priority Byte Offset 954 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID953  ,Interrupt ID953  Priority/Priority Byte Offset 953 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID952  ,Interrupt ID952   Priority/Priority Byte Offset 952 "
group.long 0x7BC++0x03
line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
hexmask.long.byte 0x00 24.--31. 1. " INTID959  ,Interrupt ID959  Priority/Priority Byte Offset 959 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID958  ,Interrupt ID958   Priority/Priority Byte Offset 958 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID957  ,Interrupt ID957  Priority/Priority Byte Offset 957 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID956  ,Interrupt ID956   Priority/Priority Byte Offset 956 "
else
rgroup.long 0x7A0++0x03
line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
rgroup.long 0x7A4++0x03
line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
rgroup.long 0x7A8++0x03
line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
rgroup.long 0x7AC++0x03
line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
rgroup.long 0x7B0++0x03
line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
rgroup.long 0x7B4++0x03
line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
rgroup.long 0x7B8++0x03
line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
rgroup.long 0x7BC++0x03
line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1E)
group.long 0x7C0++0x03
line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
hexmask.long.byte 0x00 24.--31. 1. " INTID963  ,Interrupt ID963  Priority/Priority Byte Offset 963 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID962  ,Interrupt ID962   Priority/Priority Byte Offset 962 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID961  ,Interrupt ID961  Priority/Priority Byte Offset 961 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID960  ,Interrupt ID960   Priority/Priority Byte Offset 960 "
group.long 0x7C4++0x03
line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
hexmask.long.byte 0x00 24.--31. 1. " INTID967  ,Interrupt ID967  Priority/Priority Byte Offset 967 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID966  ,Interrupt ID966   Priority/Priority Byte Offset 966 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID965  ,Interrupt ID965  Priority/Priority Byte Offset 965 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID964  ,Interrupt ID964   Priority/Priority Byte Offset 964 "
group.long 0x7C8++0x03
line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
hexmask.long.byte 0x00 24.--31. 1. " INTID971  ,Interrupt ID971  Priority/Priority Byte Offset 971 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID970  ,Interrupt ID970   Priority/Priority Byte Offset 970 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID969  ,Interrupt ID969  Priority/Priority Byte Offset 969 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID968  ,Interrupt ID968   Priority/Priority Byte Offset 968 "
group.long 0x7CC++0x03
line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
hexmask.long.byte 0x00 24.--31. 1. " INTID975  ,Interrupt ID975  Priority/Priority Byte Offset 975 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID974  ,Interrupt ID974   Priority/Priority Byte Offset 974 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID973  ,Interrupt ID973  Priority/Priority Byte Offset 973 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID972  ,Interrupt ID972   Priority/Priority Byte Offset 972 "
group.long 0x7D0++0x03
line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
hexmask.long.byte 0x00 24.--31. 1. " INTID979  ,Interrupt ID979  Priority/Priority Byte Offset 979 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID978  ,Interrupt ID978   Priority/Priority Byte Offset 978 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID977  ,Interrupt ID977  Priority/Priority Byte Offset 977 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID976  ,Interrupt ID976   Priority/Priority Byte Offset 976 "
group.long 0x7D4++0x03
line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
hexmask.long.byte 0x00 24.--31. 1. " INTID983  ,Interrupt ID983  Priority/Priority Byte Offset 983 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID982  ,Interrupt ID982   Priority/Priority Byte Offset 982 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID981  ,Interrupt ID981  Priority/Priority Byte Offset 981 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID980  ,Interrupt ID980   Priority/Priority Byte Offset 980 "
group.long 0x7D8++0x03
line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
hexmask.long.byte 0x00 24.--31. 1. " INTID987  ,Interrupt ID987  Priority/Priority Byte Offset 987 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID986  ,Interrupt ID986   Priority/Priority Byte Offset 986 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID985  ,Interrupt ID985  Priority/Priority Byte Offset 985 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID984  ,Interrupt ID984   Priority/Priority Byte Offset 984 "
group.long 0x7DC++0x03
line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
hexmask.long.byte 0x00 24.--31. 1. " INTID991  ,Interrupt ID991  Priority/Priority Byte Offset 991 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID990  ,Interrupt ID990   Priority/Priority Byte Offset 990 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID989  ,Interrupt ID989  Priority/Priority Byte Offset 989 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID988  ,Interrupt ID988   Priority/Priority Byte Offset 988 "
else
rgroup.long 0x7C0++0x03
line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
rgroup.long 0x7C4++0x03
line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
rgroup.long 0x7C8++0x03
line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
rgroup.long 0x7CC++0x03
line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
rgroup.long 0x7D0++0x03
line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
rgroup.long 0x7D4++0x03
line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
rgroup.long 0x7D8++0x03
line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
rgroup.long 0x7DC++0x03
line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1F)
group.long 0x7E0++0x03
line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248"
hexmask.long.byte 0x00 24.--31. 1. " INTID995  ,Interrupt ID995  Priority/Priority Byte Offset 995 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID994  ,Interrupt ID994   Priority/Priority Byte Offset 994 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID993  ,Interrupt ID993  Priority/Priority Byte Offset 993 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID992  ,Interrupt ID992   Priority/Priority Byte Offset 992 "
group.long 0x7E4++0x03
line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249"
hexmask.long.byte 0x00 24.--31. 1. " INTID999  ,Interrupt ID999  Priority/Priority Byte Offset 999 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID998  ,Interrupt ID998   Priority/Priority Byte Offset 998 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID997  ,Interrupt ID997  Priority/Priority Byte Offset 997 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID996  ,Interrupt ID996   Priority/Priority Byte Offset 996 "
group.long 0x7E8++0x03
line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250"
hexmask.long.byte 0x00 24.--31. 1. " INTID1003 ,Interrupt ID1003 Priority/Priority Byte Offset 1003"
hexmask.long.byte 0x00 16.--23. 1. "  INTID1002 ,Interrupt ID1002  Priority/Priority Byte Offset 1002"
hexmask.long.byte 0x00 8.--15. 1. "  INTID1001 ,Interrupt ID1001 Priority/Priority Byte Offset 1001"
hexmask.long.byte 0x00 0.--7. 1. "  INTID1000 ,Interrupt ID1000  Priority/Priority Byte Offset 1000"
group.long 0x7EC++0x03
line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251"
hexmask.long.byte 0x00 24.--31. 1. " INTID1007 ,Interrupt ID1007 Priority/Priority Byte Offset 1007"
hexmask.long.byte 0x00 16.--23. 1. "  INTID1006 ,Interrupt ID1006  Priority/Priority Byte Offset 1006"
hexmask.long.byte 0x00 8.--15. 1. "  INTID1005 ,Interrupt ID1005 Priority/Priority Byte Offset 1005"
hexmask.long.byte 0x00 0.--7. 1. "  INTID1004 ,Interrupt ID1004  Priority/Priority Byte Offset 1004"
group.long 0x7F0++0x03
line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252"
hexmask.long.byte 0x00 24.--31. 1. " INTID1011 ,Interrupt ID1011 Priority/Priority Byte Offset 1011"
hexmask.long.byte 0x00 16.--23. 1. "  INTID1010 ,Interrupt ID1010  Priority/Priority Byte Offset 1010"
hexmask.long.byte 0x00 8.--15. 1. "  INTID1009 ,Interrupt ID1009 Priority/Priority Byte Offset 1009"
hexmask.long.byte 0x00 0.--7. 1. "  INTID1008 ,Interrupt ID1008  Priority/Priority Byte Offset 1008"
group.long 0x7F4++0x03
line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253"
hexmask.long.byte 0x00 24.--31. 1. " INTID1015 ,Interrupt ID1015 Priority/Priority Byte Offset 1015"
hexmask.long.byte 0x00 16.--23. 1. "  INTID1014 ,Interrupt ID1014  Priority/Priority Byte Offset 1014"
hexmask.long.byte 0x00 8.--15. 1. "  INTID1013 ,Interrupt ID1013 Priority/Priority Byte Offset 1013"
hexmask.long.byte 0x00 0.--7. 1. "  INTID1012 ,Interrupt ID1012  Priority/Priority Byte Offset 1012"
group.long 0x7F8++0x03
line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254"
hexmask.long.byte 0x00 24.--31. 1. " INTID1019 ,Interrupt ID1019 Priority/Priority Byte Offset 1019"
hexmask.long.byte 0x00 16.--23. 1. "  INTID1018 ,Interrupt ID1018  Priority/Priority Byte Offset 1018"
hexmask.long.byte 0x00 8.--15. 1. "  INTID1017 ,Interrupt ID1017 Priority/Priority Byte Offset 1017"
hexmask.long.byte 0x00 0.--7. 1. "  INTID1016 ,Interrupt ID1016  Priority/Priority Byte Offset 1016"
else
rgroup.long 0x7E0++0x03
line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248"
rgroup.long 0x7E4++0x03
line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249"
rgroup.long 0x7E8++0x03
line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250"
rgroup.long 0x7EC++0x03
line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251"
rgroup.long 0x7F0++0x03
line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252"
rgroup.long 0x7F4++0x03
line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253"
rgroup.long 0x7F8++0x03
line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254"
endif
tree.end
width 19.
tree "Processor Targets Registers"
if (((per.l(ad:0xFFFC1000+0x04))&0x000000E0)>0x1)
rgroup.long 0x800++0x03
line.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3    ,CPU Targets Byte Offset 3   "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO2    ,CPU Targets Byte Offset 2   "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO1    ,CPU Targets Byte Offset 1   "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO0    ,CPU Targets Byte Offset 0   "
rgroup.long 0x804++0x03
line.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO7    ,CPU Targets Byte Offset 7   "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO6    ,CPU Targets Byte Offset 6   "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO5    ,CPU Targets Byte Offset 5   "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO4    ,CPU Targets Byte Offset 4   "
rgroup.long 0x808++0x03
line.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO11   ,CPU Targets Byte Offset 11  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO10   ,CPU Targets Byte Offset 10  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO9    ,CPU Targets Byte Offset 9   "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO8    ,CPU Targets Byte Offset 8   "
rgroup.long 0x80C++0x03
line.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO15   ,CPU Targets Byte Offset 15  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO14   ,CPU Targets Byte Offset 14  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO13   ,CPU Targets Byte Offset 13  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO12   ,CPU Targets Byte Offset 12  "
rgroup.long 0x810++0x03
line.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO19   ,CPU Targets Byte Offset 19  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO18   ,CPU Targets Byte Offset 18  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO17   ,CPU Targets Byte Offset 17  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO16   ,CPU Targets Byte Offset 16  "
rgroup.long 0x814++0x03
line.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO23   ,CPU Targets Byte Offset 23  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO22   ,CPU Targets Byte Offset 22  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO21   ,CPU Targets Byte Offset 21  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO20   ,CPU Targets Byte Offset 20  "
rgroup.long 0x818++0x03
line.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO27   ,CPU Targets Byte Offset 27  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO26   ,CPU Targets Byte Offset 26  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO25   ,CPU Targets Byte Offset 25  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO24   ,CPU Targets Byte Offset 24  "
rgroup.long 0x81C++0x03
line.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO31   ,CPU Targets Byte Offset 31  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO30   ,CPU Targets Byte Offset 30  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO29   ,CPU Targets Byte Offset 29  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO28   ,CPU Targets Byte Offset 28  "
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x01)
group.long 0x820++0x03
line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35   ,CPU Targets Byte Offset 35  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO34   ,CPU Targets Byte Offset 34  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO33   ,CPU Targets Byte Offset 33  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO32   ,CPU Targets Byte Offset 32  "
group.long 0x824++0x03
line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39   ,CPU Targets Byte Offset 39  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO38   ,CPU Targets Byte Offset 38  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO37   ,CPU Targets Byte Offset 37  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO36   ,CPU Targets Byte Offset 36  "
group.long 0x828++0x03
line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43   ,CPU Targets Byte Offset 43  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO42   ,CPU Targets Byte Offset 42  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO41   ,CPU Targets Byte Offset 41  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO40   ,CPU Targets Byte Offset 40  "
group.long 0x82C++0x03
line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47   ,CPU Targets Byte Offset 47  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO46   ,CPU Targets Byte Offset 46  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO45   ,CPU Targets Byte Offset 45  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO44   ,CPU Targets Byte Offset 44  "
group.long 0x830++0x03
line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51   ,CPU Targets Byte Offset 51  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO50   ,CPU Targets Byte Offset 50  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO49   ,CPU Targets Byte Offset 49  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO48   ,CPU Targets Byte Offset 48  "
group.long 0x834++0x03
line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55   ,CPU Targets Byte Offset 55  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO54   ,CPU Targets Byte Offset 54  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO53   ,CPU Targets Byte Offset 53  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO52   ,CPU Targets Byte Offset 52  "
group.long 0x838++0x03
line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59   ,CPU Targets Byte Offset 59  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO58   ,CPU Targets Byte Offset 58  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO57   ,CPU Targets Byte Offset 57  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO56   ,CPU Targets Byte Offset 56  "
group.long 0x83C++0x03
line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63   ,CPU Targets Byte Offset 63  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO62   ,CPU Targets Byte Offset 62  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO61   ,CPU Targets Byte Offset 61  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO60   ,CPU Targets Byte Offset 60  "
else
rgroup.long 0x820++0x03
line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
rgroup.long 0x824++0x03
line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
rgroup.long 0x828++0x03
line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
rgroup.long 0x82C++0x03
line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
rgroup.long 0x830++0x03
line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
rgroup.long 0x834++0x03
line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
rgroup.long 0x838++0x03
line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
rgroup.long 0x83C++0x03
line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x02)
group.long 0x840++0x03
line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67   ,CPU Targets Byte Offset 67  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO66   ,CPU Targets Byte Offset 66  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO65   ,CPU Targets Byte Offset 65  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO64   ,CPU Targets Byte Offset 64  "
group.long 0x844++0x03
line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71   ,CPU Targets Byte Offset 71  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO70   ,CPU Targets Byte Offset 70  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO69   ,CPU Targets Byte Offset 69  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO68   ,CPU Targets Byte Offset 68  "
group.long 0x848++0x03
line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75   ,CPU Targets Byte Offset 75  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO74   ,CPU Targets Byte Offset 74  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO73   ,CPU Targets Byte Offset 73  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO72   ,CPU Targets Byte Offset 72  "
group.long 0x84C++0x03
line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79   ,CPU Targets Byte Offset 79  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO78   ,CPU Targets Byte Offset 78  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO77   ,CPU Targets Byte Offset 77  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO76   ,CPU Targets Byte Offset 76  "
group.long 0x850++0x03
line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83   ,CPU Targets Byte Offset 83  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO82   ,CPU Targets Byte Offset 82  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO81   ,CPU Targets Byte Offset 81  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO80   ,CPU Targets Byte Offset 80  "
group.long 0x854++0x03
line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87   ,CPU Targets Byte Offset 87  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO86   ,CPU Targets Byte Offset 86  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO85   ,CPU Targets Byte Offset 85  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO84   ,CPU Targets Byte Offset 84  "
group.long 0x858++0x03
line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91   ,CPU Targets Byte Offset 91  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO90   ,CPU Targets Byte Offset 90  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO89   ,CPU Targets Byte Offset 89  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO88   ,CPU Targets Byte Offset 88  "
group.long 0x85C++0x03
line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95   ,CPU Targets Byte Offset 95  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO94   ,CPU Targets Byte Offset 94  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO93   ,CPU Targets Byte Offset 93  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO92   ,CPU Targets Byte Offset 92  "
else
rgroup.long 0x840++0x03
line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
rgroup.long 0x844++0x03
line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
rgroup.long 0x848++0x03
line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
rgroup.long 0x84C++0x03
line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
rgroup.long 0x850++0x03
line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
rgroup.long 0x854++0x03
line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
rgroup.long 0x858++0x03
line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
rgroup.long 0x85C++0x03
line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x03)
group.long 0x860++0x03
line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99   ,CPU Targets Byte Offset 99  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO98   ,CPU Targets Byte Offset 98  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO97   ,CPU Targets Byte Offset 97  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO96   ,CPU Targets Byte Offset 96  "
group.long 0x864++0x03
line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103  ,CPU Targets Byte Offset 103 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO102  ,CPU Targets Byte Offset 102 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO101  ,CPU Targets Byte Offset 101 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO100  ,CPU Targets Byte Offset 100 "
group.long 0x868++0x03
line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107  ,CPU Targets Byte Offset 107 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO106  ,CPU Targets Byte Offset 106 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO105  ,CPU Targets Byte Offset 105 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO104  ,CPU Targets Byte Offset 104 "
group.long 0x86C++0x03
line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111  ,CPU Targets Byte Offset 111 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO110  ,CPU Targets Byte Offset 110 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO109  ,CPU Targets Byte Offset 109 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO108  ,CPU Targets Byte Offset 108 "
group.long 0x870++0x03
line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115  ,CPU Targets Byte Offset 115 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO114  ,CPU Targets Byte Offset 114 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO113  ,CPU Targets Byte Offset 113 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO112  ,CPU Targets Byte Offset 112 "
group.long 0x874++0x03
line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119  ,CPU Targets Byte Offset 119 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO118  ,CPU Targets Byte Offset 118 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO117  ,CPU Targets Byte Offset 117 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO116  ,CPU Targets Byte Offset 116 "
group.long 0x878++0x03
line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123  ,CPU Targets Byte Offset 123 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO122  ,CPU Targets Byte Offset 122 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO121  ,CPU Targets Byte Offset 121 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO120  ,CPU Targets Byte Offset 120 "
group.long 0x87C++0x03
line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127  ,CPU Targets Byte Offset 127 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO126  ,CPU Targets Byte Offset 126 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO125  ,CPU Targets Byte Offset 125 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO124  ,CPU Targets Byte Offset 124 "
else
rgroup.long 0x860++0x03
line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
rgroup.long 0x864++0x03
line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
rgroup.long 0x868++0x03
line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
rgroup.long 0x86C++0x03
line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
rgroup.long 0x870++0x03
line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
rgroup.long 0x874++0x03
line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
rgroup.long 0x878++0x03
line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
rgroup.long 0x87C++0x03
line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x04)
group.long 0x880++0x03
line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131  ,CPU Targets Byte Offset 131 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO130  ,CPU Targets Byte Offset 130 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO129  ,CPU Targets Byte Offset 129 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO128  ,CPU Targets Byte Offset 128 "
group.long 0x884++0x03
line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135  ,CPU Targets Byte Offset 135 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO134  ,CPU Targets Byte Offset 134 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO133  ,CPU Targets Byte Offset 133 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO132  ,CPU Targets Byte Offset 132 "
group.long 0x888++0x03
line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139  ,CPU Targets Byte Offset 139 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO138  ,CPU Targets Byte Offset 138 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO137  ,CPU Targets Byte Offset 137 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO136  ,CPU Targets Byte Offset 136 "
group.long 0x88C++0x03
line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143  ,CPU Targets Byte Offset 143 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO142  ,CPU Targets Byte Offset 142 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO141  ,CPU Targets Byte Offset 141 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO140  ,CPU Targets Byte Offset 140 "
group.long 0x890++0x03
line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147  ,CPU Targets Byte Offset 147 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO146  ,CPU Targets Byte Offset 146 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO145  ,CPU Targets Byte Offset 145 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO144  ,CPU Targets Byte Offset 144 "
group.long 0x894++0x03
line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151  ,CPU Targets Byte Offset 151 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO150  ,CPU Targets Byte Offset 150 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO149  ,CPU Targets Byte Offset 149 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO148  ,CPU Targets Byte Offset 148 "
group.long 0x898++0x03
line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155  ,CPU Targets Byte Offset 155 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO154  ,CPU Targets Byte Offset 154 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO153  ,CPU Targets Byte Offset 153 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO152  ,CPU Targets Byte Offset 152 "
group.long 0x89C++0x03
line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159  ,CPU Targets Byte Offset 159 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO158  ,CPU Targets Byte Offset 158 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO157  ,CPU Targets Byte Offset 157 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO156  ,CPU Targets Byte Offset 156 "
else
rgroup.long 0x880++0x03
line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
rgroup.long 0x884++0x03
line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
rgroup.long 0x888++0x03
line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
rgroup.long 0x88C++0x03
line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
rgroup.long 0x890++0x03
line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
rgroup.long 0x894++0x03
line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
rgroup.long 0x898++0x03
line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
rgroup.long 0x89C++0x03
line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x05)
group.long 0x8A0++0x03
line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163  ,CPU Targets Byte Offset 163 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO162  ,CPU Targets Byte Offset 162 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO161  ,CPU Targets Byte Offset 161 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO160  ,CPU Targets Byte Offset 160 "
group.long 0x8A4++0x03
line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167  ,CPU Targets Byte Offset 167 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO166  ,CPU Targets Byte Offset 166 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO165  ,CPU Targets Byte Offset 165 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO164  ,CPU Targets Byte Offset 164 "
group.long 0x8A8++0x03
line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171  ,CPU Targets Byte Offset 171 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO170  ,CPU Targets Byte Offset 170 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO169  ,CPU Targets Byte Offset 169 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO168  ,CPU Targets Byte Offset 168 "
group.long 0x8AC++0x03
line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175  ,CPU Targets Byte Offset 175 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO174  ,CPU Targets Byte Offset 174 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO173  ,CPU Targets Byte Offset 173 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO172  ,CPU Targets Byte Offset 172 "
group.long 0x8B0++0x03
line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179  ,CPU Targets Byte Offset 179 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO178  ,CPU Targets Byte Offset 178 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO177  ,CPU Targets Byte Offset 177 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO176  ,CPU Targets Byte Offset 176 "
group.long 0x8B4++0x03
line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183  ,CPU Targets Byte Offset 183 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO182  ,CPU Targets Byte Offset 182 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO181  ,CPU Targets Byte Offset 181 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO180  ,CPU Targets Byte Offset 180 "
group.long 0x8B8++0x03
line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187  ,CPU Targets Byte Offset 187 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO186  ,CPU Targets Byte Offset 186 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO185  ,CPU Targets Byte Offset 185 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO184  ,CPU Targets Byte Offset 184 "
group.long 0x8BC++0x03
line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191  ,CPU Targets Byte Offset 191 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO190  ,CPU Targets Byte Offset 190 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO189  ,CPU Targets Byte Offset 189 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO188  ,CPU Targets Byte Offset 188 "
else
rgroup.long 0x8A0++0x03
line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
rgroup.long 0x8A4++0x03
line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
rgroup.long 0x8A8++0x03
line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
rgroup.long 0x8AC++0x03
line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
rgroup.long 0x8B0++0x03
line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
rgroup.long 0x8B4++0x03
line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
rgroup.long 0x8B8++0x03
line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
rgroup.long 0x8BC++0x03
line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x06)
group.long 0x8C0++0x03
line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195  ,CPU Targets Byte Offset 195 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO194  ,CPU Targets Byte Offset 194 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO193  ,CPU Targets Byte Offset 193 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO192  ,CPU Targets Byte Offset 192 "
group.long 0x8C4++0x03
line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199  ,CPU Targets Byte Offset 199 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO198  ,CPU Targets Byte Offset 198 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO197  ,CPU Targets Byte Offset 197 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO196  ,CPU Targets Byte Offset 196 "
group.long 0x8C8++0x03
line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203  ,CPU Targets Byte Offset 203 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO202  ,CPU Targets Byte Offset 202 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO201  ,CPU Targets Byte Offset 201 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO200  ,CPU Targets Byte Offset 200 "
group.long 0x8CC++0x03
line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207  ,CPU Targets Byte Offset 207 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO206  ,CPU Targets Byte Offset 206 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO205  ,CPU Targets Byte Offset 205 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO204  ,CPU Targets Byte Offset 204 "
group.long 0x8D0++0x03
line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211  ,CPU Targets Byte Offset 211 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO210  ,CPU Targets Byte Offset 210 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO209  ,CPU Targets Byte Offset 209 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO208  ,CPU Targets Byte Offset 208 "
group.long 0x8D4++0x03
line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215  ,CPU Targets Byte Offset 215 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO214  ,CPU Targets Byte Offset 214 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO213  ,CPU Targets Byte Offset 213 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO212  ,CPU Targets Byte Offset 212 "
group.long 0x8D8++0x03
line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219  ,CPU Targets Byte Offset 219 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO218  ,CPU Targets Byte Offset 218 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO217  ,CPU Targets Byte Offset 217 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO216  ,CPU Targets Byte Offset 216 "
group.long 0x8DC++0x03
line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223  ,CPU Targets Byte Offset 223 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO222  ,CPU Targets Byte Offset 222 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO221  ,CPU Targets Byte Offset 221 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO220  ,CPU Targets Byte Offset 220 "
else
rgroup.long 0x8C0++0x03
line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
rgroup.long 0x8C4++0x03
line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
rgroup.long 0x8C8++0x03
line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
rgroup.long 0x8CC++0x03
line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
rgroup.long 0x8D0++0x03
line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
rgroup.long 0x8D4++0x03
line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
rgroup.long 0x8D8++0x03
line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
rgroup.long 0x8DC++0x03
line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x07)
group.long 0x8E0++0x03
line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227  ,CPU Targets Byte Offset 227 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO226  ,CPU Targets Byte Offset 226 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO225  ,CPU Targets Byte Offset 225 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO224  ,CPU Targets Byte Offset 224 "
group.long 0x8E4++0x03
line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231  ,CPU Targets Byte Offset 231 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO230  ,CPU Targets Byte Offset 230 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO229  ,CPU Targets Byte Offset 229 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO228  ,CPU Targets Byte Offset 228 "
group.long 0x8E8++0x03
line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235  ,CPU Targets Byte Offset 235 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO234  ,CPU Targets Byte Offset 234 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO233  ,CPU Targets Byte Offset 233 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO232  ,CPU Targets Byte Offset 232 "
group.long 0x8EC++0x03
line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239  ,CPU Targets Byte Offset 239 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO238  ,CPU Targets Byte Offset 238 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO237  ,CPU Targets Byte Offset 237 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO236  ,CPU Targets Byte Offset 236 "
group.long 0x8F0++0x03
line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243  ,CPU Targets Byte Offset 243 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO242  ,CPU Targets Byte Offset 242 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO241  ,CPU Targets Byte Offset 241 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO240  ,CPU Targets Byte Offset 240 "
group.long 0x8F4++0x03
line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247  ,CPU Targets Byte Offset 247 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO246  ,CPU Targets Byte Offset 246 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO245  ,CPU Targets Byte Offset 245 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO244  ,CPU Targets Byte Offset 244 "
group.long 0x8F8++0x03
line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251  ,CPU Targets Byte Offset 251 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO250  ,CPU Targets Byte Offset 250 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO249  ,CPU Targets Byte Offset 249 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO248  ,CPU Targets Byte Offset 248 "
group.long 0x8FC++0x03
line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255  ,CPU Targets Byte Offset 255 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO254  ,CPU Targets Byte Offset 254 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO253  ,CPU Targets Byte Offset 253 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO252  ,CPU Targets Byte Offset 252 "
else
rgroup.long 0x8E0++0x03
line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
rgroup.long 0x8E4++0x03
line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
rgroup.long 0x8E8++0x03
line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
rgroup.long 0x8EC++0x03
line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
rgroup.long 0x8F0++0x03
line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
rgroup.long 0x8F4++0x03
line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
rgroup.long 0x8F8++0x03
line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
rgroup.long 0x8FC++0x03
line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x08)
group.long 0x900++0x03
line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259  ,CPU Targets Byte Offset 259 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO258  ,CPU Targets Byte Offset 258 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO257  ,CPU Targets Byte Offset 257 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO256  ,CPU Targets Byte Offset 256 "
group.long 0x904++0x03
line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263  ,CPU Targets Byte Offset 263 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO262  ,CPU Targets Byte Offset 262 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO261  ,CPU Targets Byte Offset 261 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO260  ,CPU Targets Byte Offset 260 "
group.long 0x908++0x03
line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267  ,CPU Targets Byte Offset 267 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO266  ,CPU Targets Byte Offset 266 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO265  ,CPU Targets Byte Offset 265 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO264  ,CPU Targets Byte Offset 264 "
group.long 0x90C++0x03
line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271  ,CPU Targets Byte Offset 271 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO270  ,CPU Targets Byte Offset 270 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO269  ,CPU Targets Byte Offset 269 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO268  ,CPU Targets Byte Offset 268 "
group.long 0x910++0x03
line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275  ,CPU Targets Byte Offset 275 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO274  ,CPU Targets Byte Offset 274 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO273  ,CPU Targets Byte Offset 273 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO272  ,CPU Targets Byte Offset 272 "
group.long 0x914++0x03
line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279  ,CPU Targets Byte Offset 279 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO278  ,CPU Targets Byte Offset 278 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO277  ,CPU Targets Byte Offset 277 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO276  ,CPU Targets Byte Offset 276 "
group.long 0x918++0x03
line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283  ,CPU Targets Byte Offset 283 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO282  ,CPU Targets Byte Offset 282 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO281  ,CPU Targets Byte Offset 281 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO280  ,CPU Targets Byte Offset 280 "
group.long 0x91C++0x03
line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287  ,CPU Targets Byte Offset 287 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO286  ,CPU Targets Byte Offset 286 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO285  ,CPU Targets Byte Offset 285 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO284  ,CPU Targets Byte Offset 284 "
else
rgroup.long 0x900++0x03
line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
rgroup.long 0x904++0x03
line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
rgroup.long 0x908++0x03
line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
rgroup.long 0x90C++0x03
line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
rgroup.long 0x910++0x03
line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
rgroup.long 0x914++0x03
line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
rgroup.long 0x918++0x03
line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
rgroup.long 0x91C++0x03
line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x09)
group.long 0x920++0x03
line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291  ,CPU Targets Byte Offset 291 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO290  ,CPU Targets Byte Offset 290 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO289  ,CPU Targets Byte Offset 289 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO288  ,CPU Targets Byte Offset 288 "
group.long 0x924++0x03
line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295  ,CPU Targets Byte Offset 295 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO294  ,CPU Targets Byte Offset 294 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO293  ,CPU Targets Byte Offset 293 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO292  ,CPU Targets Byte Offset 292 "
group.long 0x928++0x03
line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299  ,CPU Targets Byte Offset 299 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO298  ,CPU Targets Byte Offset 298 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO297  ,CPU Targets Byte Offset 297 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO296  ,CPU Targets Byte Offset 296 "
group.long 0x92C++0x03
line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303  ,CPU Targets Byte Offset 303 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO302  ,CPU Targets Byte Offset 302 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO301  ,CPU Targets Byte Offset 301 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO300  ,CPU Targets Byte Offset 300 "
group.long 0x930++0x03
line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307  ,CPU Targets Byte Offset 307 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO306  ,CPU Targets Byte Offset 306 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO305  ,CPU Targets Byte Offset 305 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO304  ,CPU Targets Byte Offset 304 "
group.long 0x934++0x03
line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311  ,CPU Targets Byte Offset 311 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO310  ,CPU Targets Byte Offset 310 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO309  ,CPU Targets Byte Offset 309 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO308  ,CPU Targets Byte Offset 308 "
group.long 0x938++0x03
line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315  ,CPU Targets Byte Offset 315 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO314  ,CPU Targets Byte Offset 314 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO313  ,CPU Targets Byte Offset 313 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO312  ,CPU Targets Byte Offset 312 "
group.long 0x93C++0x03
line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319  ,CPU Targets Byte Offset 319 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO318  ,CPU Targets Byte Offset 318 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO317  ,CPU Targets Byte Offset 317 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO316  ,CPU Targets Byte Offset 316 "
else
rgroup.long 0x920++0x03
line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
rgroup.long 0x924++0x03
line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
rgroup.long 0x928++0x03
line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
rgroup.long 0x92C++0x03
line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
rgroup.long 0x930++0x03
line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
rgroup.long 0x934++0x03
line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
rgroup.long 0x938++0x03
line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
rgroup.long 0x93C++0x03
line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0A)
group.long 0x940++0x03
line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323  ,CPU Targets Byte Offset 323 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO322  ,CPU Targets Byte Offset 322 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO321  ,CPU Targets Byte Offset 321 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO320  ,CPU Targets Byte Offset 320 "
group.long 0x944++0x03
line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327  ,CPU Targets Byte Offset 327 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO326  ,CPU Targets Byte Offset 326 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO325  ,CPU Targets Byte Offset 325 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO324  ,CPU Targets Byte Offset 324 "
group.long 0x948++0x03
line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331  ,CPU Targets Byte Offset 331 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO330  ,CPU Targets Byte Offset 330 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO329  ,CPU Targets Byte Offset 329 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO328  ,CPU Targets Byte Offset 328 "
group.long 0x94C++0x03
line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335  ,CPU Targets Byte Offset 335 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO334  ,CPU Targets Byte Offset 334 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO333  ,CPU Targets Byte Offset 333 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO332  ,CPU Targets Byte Offset 332 "
group.long 0x950++0x03
line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339  ,CPU Targets Byte Offset 339 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO338  ,CPU Targets Byte Offset 338 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO337  ,CPU Targets Byte Offset 337 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO336  ,CPU Targets Byte Offset 336 "
group.long 0x954++0x03
line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343  ,CPU Targets Byte Offset 343 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO342  ,CPU Targets Byte Offset 342 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO341  ,CPU Targets Byte Offset 341 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO340  ,CPU Targets Byte Offset 340 "
group.long 0x958++0x03
line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347  ,CPU Targets Byte Offset 347 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO346  ,CPU Targets Byte Offset 346 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO345  ,CPU Targets Byte Offset 345 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO344  ,CPU Targets Byte Offset 344 "
group.long 0x95C++0x03
line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351  ,CPU Targets Byte Offset 351 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO350  ,CPU Targets Byte Offset 350 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO349  ,CPU Targets Byte Offset 349 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO348  ,CPU Targets Byte Offset 348 "
else
rgroup.long 0x940++0x03
line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
rgroup.long 0x944++0x03
line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
rgroup.long 0x948++0x03
line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
rgroup.long 0x94C++0x03
line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
rgroup.long 0x950++0x03
line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
rgroup.long 0x954++0x03
line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
rgroup.long 0x958++0x03
line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
rgroup.long 0x95C++0x03
line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0B)
group.long 0x960++0x03
line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355  ,CPU Targets Byte Offset 355 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO354  ,CPU Targets Byte Offset 354 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO353  ,CPU Targets Byte Offset 353 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO352  ,CPU Targets Byte Offset 352 "
group.long 0x964++0x03
line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359  ,CPU Targets Byte Offset 359 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO358  ,CPU Targets Byte Offset 358 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO357  ,CPU Targets Byte Offset 357 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO356  ,CPU Targets Byte Offset 356 "
group.long 0x968++0x03
line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363  ,CPU Targets Byte Offset 363 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO362  ,CPU Targets Byte Offset 362 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO361  ,CPU Targets Byte Offset 361 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO360  ,CPU Targets Byte Offset 360 "
group.long 0x96C++0x03
line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367  ,CPU Targets Byte Offset 367 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO366  ,CPU Targets Byte Offset 366 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO365  ,CPU Targets Byte Offset 365 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO364  ,CPU Targets Byte Offset 364 "
group.long 0x970++0x03
line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371  ,CPU Targets Byte Offset 371 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO370  ,CPU Targets Byte Offset 370 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO369  ,CPU Targets Byte Offset 369 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO368  ,CPU Targets Byte Offset 368 "
group.long 0x974++0x03
line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375  ,CPU Targets Byte Offset 375 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO374  ,CPU Targets Byte Offset 374 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO373  ,CPU Targets Byte Offset 373 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO372  ,CPU Targets Byte Offset 372 "
group.long 0x978++0x03
line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379  ,CPU Targets Byte Offset 379 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO378  ,CPU Targets Byte Offset 378 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO377  ,CPU Targets Byte Offset 377 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO376  ,CPU Targets Byte Offset 376 "
group.long 0x97C++0x03
line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383  ,CPU Targets Byte Offset 383 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO382  ,CPU Targets Byte Offset 382 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO381  ,CPU Targets Byte Offset 381 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO380  ,CPU Targets Byte Offset 380 "
else
rgroup.long 0x960++0x03
line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
rgroup.long 0x964++0x03
line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
rgroup.long 0x968++0x03
line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
rgroup.long 0x96C++0x03
line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
rgroup.long 0x970++0x03
line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
rgroup.long 0x974++0x03
line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
rgroup.long 0x978++0x03
line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
rgroup.long 0x97C++0x03
line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0C)
group.long 0x980++0x03
line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387  ,CPU Targets Byte Offset 387 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO386  ,CPU Targets Byte Offset 386 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO385  ,CPU Targets Byte Offset 385 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO384  ,CPU Targets Byte Offset 384 "
group.long 0x984++0x03
line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391  ,CPU Targets Byte Offset 391 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO390  ,CPU Targets Byte Offset 390 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO389  ,CPU Targets Byte Offset 389 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO388  ,CPU Targets Byte Offset 388 "
group.long 0x988++0x03
line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395  ,CPU Targets Byte Offset 395 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO394  ,CPU Targets Byte Offset 394 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO393  ,CPU Targets Byte Offset 393 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO392  ,CPU Targets Byte Offset 392 "
group.long 0x98C++0x03
line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399  ,CPU Targets Byte Offset 399 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO398  ,CPU Targets Byte Offset 398 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO397  ,CPU Targets Byte Offset 397 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO396  ,CPU Targets Byte Offset 396 "
group.long 0x990++0x03
line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403  ,CPU Targets Byte Offset 403 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO402  ,CPU Targets Byte Offset 402 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO401  ,CPU Targets Byte Offset 401 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO400  ,CPU Targets Byte Offset 400 "
group.long 0x994++0x03
line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407  ,CPU Targets Byte Offset 407 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO406  ,CPU Targets Byte Offset 406 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO405  ,CPU Targets Byte Offset 405 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO404  ,CPU Targets Byte Offset 404 "
group.long 0x998++0x03
line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411  ,CPU Targets Byte Offset 411 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO410  ,CPU Targets Byte Offset 410 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO409  ,CPU Targets Byte Offset 409 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO408  ,CPU Targets Byte Offset 408 "
group.long 0x99C++0x03
line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415  ,CPU Targets Byte Offset 415 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO414  ,CPU Targets Byte Offset 414 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO413  ,CPU Targets Byte Offset 413 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO412  ,CPU Targets Byte Offset 412 "
else
rgroup.long 0x980++0x03
line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
rgroup.long 0x984++0x03
line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
rgroup.long 0x988++0x03
line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
rgroup.long 0x98C++0x03
line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
rgroup.long 0x990++0x03
line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
rgroup.long 0x994++0x03
line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
rgroup.long 0x998++0x03
line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
rgroup.long 0x99C++0x03
line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0D)
group.long 0x9A0++0x03
line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419  ,CPU Targets Byte Offset 419 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO418  ,CPU Targets Byte Offset 418 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO417  ,CPU Targets Byte Offset 417 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO416  ,CPU Targets Byte Offset 416 "
group.long 0x9A4++0x03
line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423  ,CPU Targets Byte Offset 423 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO422  ,CPU Targets Byte Offset 422 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO421  ,CPU Targets Byte Offset 421 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO420  ,CPU Targets Byte Offset 420 "
group.long 0x9A8++0x03
line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427  ,CPU Targets Byte Offset 427 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO426  ,CPU Targets Byte Offset 426 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO425  ,CPU Targets Byte Offset 425 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO424  ,CPU Targets Byte Offset 424 "
group.long 0x9AC++0x03
line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431  ,CPU Targets Byte Offset 431 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO430  ,CPU Targets Byte Offset 430 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO429  ,CPU Targets Byte Offset 429 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO428  ,CPU Targets Byte Offset 428 "
group.long 0x9B0++0x03
line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435  ,CPU Targets Byte Offset 435 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO434  ,CPU Targets Byte Offset 434 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO433  ,CPU Targets Byte Offset 433 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO432  ,CPU Targets Byte Offset 432 "
group.long 0x9B4++0x03
line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439  ,CPU Targets Byte Offset 439 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO438  ,CPU Targets Byte Offset 438 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO437  ,CPU Targets Byte Offset 437 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO436  ,CPU Targets Byte Offset 436 "
group.long 0x9B8++0x03
line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443  ,CPU Targets Byte Offset 443 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO442  ,CPU Targets Byte Offset 442 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO441  ,CPU Targets Byte Offset 441 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO440  ,CPU Targets Byte Offset 440 "
group.long 0x9BC++0x03
line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447  ,CPU Targets Byte Offset 447 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO446  ,CPU Targets Byte Offset 446 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO445  ,CPU Targets Byte Offset 445 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO444  ,CPU Targets Byte Offset 444 "
else
rgroup.long 0x9A0++0x03
line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
rgroup.long 0x9A4++0x03
line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
rgroup.long 0x9A8++0x03
line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
rgroup.long 0x9AC++0x03
line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
rgroup.long 0x9B0++0x03
line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
rgroup.long 0x9B4++0x03
line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
rgroup.long 0x9B8++0x03
line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
rgroup.long 0x9BC++0x03
line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0E)
group.long 0x9C0++0x03
line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451  ,CPU Targets Byte Offset 451 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO450  ,CPU Targets Byte Offset 450 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO449  ,CPU Targets Byte Offset 449 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO448  ,CPU Targets Byte Offset 448 "
group.long 0x9C4++0x03
line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455  ,CPU Targets Byte Offset 455 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO454  ,CPU Targets Byte Offset 454 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO453  ,CPU Targets Byte Offset 453 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO452  ,CPU Targets Byte Offset 452 "
group.long 0x9C8++0x03
line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459  ,CPU Targets Byte Offset 459 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO458  ,CPU Targets Byte Offset 458 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO457  ,CPU Targets Byte Offset 457 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO456  ,CPU Targets Byte Offset 456 "
group.long 0x9CC++0x03
line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463  ,CPU Targets Byte Offset 463 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO462  ,CPU Targets Byte Offset 462 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO461  ,CPU Targets Byte Offset 461 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO460  ,CPU Targets Byte Offset 460 "
group.long 0x9D0++0x03
line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467  ,CPU Targets Byte Offset 467 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO466  ,CPU Targets Byte Offset 466 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO465  ,CPU Targets Byte Offset 465 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO464  ,CPU Targets Byte Offset 464 "
group.long 0x9D4++0x03
line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471  ,CPU Targets Byte Offset 471 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO470  ,CPU Targets Byte Offset 470 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO469  ,CPU Targets Byte Offset 469 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO468  ,CPU Targets Byte Offset 468 "
group.long 0x9D8++0x03
line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475  ,CPU Targets Byte Offset 475 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO474  ,CPU Targets Byte Offset 474 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO473  ,CPU Targets Byte Offset 473 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO472  ,CPU Targets Byte Offset 472 "
group.long 0x9DC++0x03
line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479  ,CPU Targets Byte Offset 479 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO478  ,CPU Targets Byte Offset 478 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO477  ,CPU Targets Byte Offset 477 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO476  ,CPU Targets Byte Offset 476 "
else
rgroup.long 0x9C0++0x03
line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
rgroup.long 0x9C4++0x03
line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
rgroup.long 0x9C8++0x03
line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
rgroup.long 0x9CC++0x03
line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
rgroup.long 0x9D0++0x03
line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
rgroup.long 0x9D4++0x03
line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
rgroup.long 0x9D8++0x03
line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
rgroup.long 0x9DC++0x03
line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0F)
group.long 0x9E0++0x03
line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483  ,CPU Targets Byte Offset 483 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO482  ,CPU Targets Byte Offset 482 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO481  ,CPU Targets Byte Offset 481 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO480  ,CPU Targets Byte Offset 480 "
group.long 0x9E4++0x03
line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487  ,CPU Targets Byte Offset 487 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO486  ,CPU Targets Byte Offset 486 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO485  ,CPU Targets Byte Offset 485 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO484  ,CPU Targets Byte Offset 484 "
group.long 0x9E8++0x03
line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491  ,CPU Targets Byte Offset 491 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO490  ,CPU Targets Byte Offset 490 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO489  ,CPU Targets Byte Offset 489 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO488  ,CPU Targets Byte Offset 488 "
group.long 0x9EC++0x03
line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495  ,CPU Targets Byte Offset 495 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO494  ,CPU Targets Byte Offset 494 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO493  ,CPU Targets Byte Offset 493 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO492  ,CPU Targets Byte Offset 492 "
group.long 0x9F0++0x03
line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499  ,CPU Targets Byte Offset 499 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO498  ,CPU Targets Byte Offset 498 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO497  ,CPU Targets Byte Offset 497 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO496  ,CPU Targets Byte Offset 496 "
group.long 0x9F4++0x03
line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503  ,CPU Targets Byte Offset 503 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO502  ,CPU Targets Byte Offset 502 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO501  ,CPU Targets Byte Offset 501 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO500  ,CPU Targets Byte Offset 500 "
group.long 0x9F8++0x03
line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507  ,CPU Targets Byte Offset 507 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO506  ,CPU Targets Byte Offset 506 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO505  ,CPU Targets Byte Offset 505 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO504  ,CPU Targets Byte Offset 504 "
group.long 0x9FC++0x03
line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511  ,CPU Targets Byte Offset 511 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO510  ,CPU Targets Byte Offset 510 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO509  ,CPU Targets Byte Offset 509 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO508  ,CPU Targets Byte Offset 508 "
else
rgroup.long 0x9E0++0x03
line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
rgroup.long 0x9E4++0x03
line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
rgroup.long 0x9E8++0x03
line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
rgroup.long 0x9EC++0x03
line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
rgroup.long 0x9F0++0x03
line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
rgroup.long 0x9F4++0x03
line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
rgroup.long 0x9F8++0x03
line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
rgroup.long 0x9FC++0x03
line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x10)
group.long 0xA00++0x03
line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515  ,CPU Targets Byte Offset 515 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO514  ,CPU Targets Byte Offset 514 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO513  ,CPU Targets Byte Offset 513 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO512  ,CPU Targets Byte Offset 512 "
group.long 0xA04++0x03
line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519  ,CPU Targets Byte Offset 519 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO518  ,CPU Targets Byte Offset 518 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO517  ,CPU Targets Byte Offset 517 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO516  ,CPU Targets Byte Offset 516 "
group.long 0xA08++0x03
line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523  ,CPU Targets Byte Offset 523 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO522  ,CPU Targets Byte Offset 522 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO521  ,CPU Targets Byte Offset 521 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO520  ,CPU Targets Byte Offset 520 "
group.long 0xA0C++0x03
line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527  ,CPU Targets Byte Offset 527 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO526  ,CPU Targets Byte Offset 526 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO525  ,CPU Targets Byte Offset 525 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO524  ,CPU Targets Byte Offset 524 "
group.long 0xA10++0x03
line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531  ,CPU Targets Byte Offset 531 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO530  ,CPU Targets Byte Offset 530 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO529  ,CPU Targets Byte Offset 529 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO528  ,CPU Targets Byte Offset 528 "
group.long 0xA14++0x03
line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535  ,CPU Targets Byte Offset 535 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO534  ,CPU Targets Byte Offset 534 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO533  ,CPU Targets Byte Offset 533 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO532  ,CPU Targets Byte Offset 532 "
group.long 0xA18++0x03
line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539  ,CPU Targets Byte Offset 539 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO538  ,CPU Targets Byte Offset 538 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO537  ,CPU Targets Byte Offset 537 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO536  ,CPU Targets Byte Offset 536 "
group.long 0xA1C++0x03
line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543  ,CPU Targets Byte Offset 543 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO542  ,CPU Targets Byte Offset 542 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO541  ,CPU Targets Byte Offset 541 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO540  ,CPU Targets Byte Offset 540 "
else
rgroup.long 0xA00++0x03
line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
rgroup.long 0xA04++0x03
line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
rgroup.long 0xA08++0x03
line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
rgroup.long 0xA0C++0x03
line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
rgroup.long 0xA10++0x03
line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
rgroup.long 0xA14++0x03
line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
rgroup.long 0xA18++0x03
line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
rgroup.long 0xA1C++0x03
line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x11)
group.long 0xA20++0x03
line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547  ,CPU Targets Byte Offset 547 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO546  ,CPU Targets Byte Offset 546 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO545  ,CPU Targets Byte Offset 545 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO544  ,CPU Targets Byte Offset 544 "
group.long 0xA24++0x03
line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551  ,CPU Targets Byte Offset 551 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO550  ,CPU Targets Byte Offset 550 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO549  ,CPU Targets Byte Offset 549 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO548  ,CPU Targets Byte Offset 548 "
group.long 0xA28++0x03
line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555  ,CPU Targets Byte Offset 555 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO554  ,CPU Targets Byte Offset 554 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO553  ,CPU Targets Byte Offset 553 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO552  ,CPU Targets Byte Offset 552 "
group.long 0xA2C++0x03
line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559  ,CPU Targets Byte Offset 559 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO558  ,CPU Targets Byte Offset 558 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO557  ,CPU Targets Byte Offset 557 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO556  ,CPU Targets Byte Offset 556 "
group.long 0xA30++0x03
line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563  ,CPU Targets Byte Offset 563 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO562  ,CPU Targets Byte Offset 562 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO561  ,CPU Targets Byte Offset 561 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO560  ,CPU Targets Byte Offset 560 "
group.long 0xA34++0x03
line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567  ,CPU Targets Byte Offset 567 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO566  ,CPU Targets Byte Offset 566 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO565  ,CPU Targets Byte Offset 565 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO564  ,CPU Targets Byte Offset 564 "
group.long 0xA38++0x03
line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571  ,CPU Targets Byte Offset 571 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO570  ,CPU Targets Byte Offset 570 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO569  ,CPU Targets Byte Offset 569 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO568  ,CPU Targets Byte Offset 568 "
group.long 0xA3C++0x03
line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575  ,CPU Targets Byte Offset 575 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO574  ,CPU Targets Byte Offset 574 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO573  ,CPU Targets Byte Offset 573 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO572  ,CPU Targets Byte Offset 572 "
else
rgroup.long 0xA20++0x03
line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
rgroup.long 0xA24++0x03
line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
rgroup.long 0xA28++0x03
line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
rgroup.long 0xA2C++0x03
line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
rgroup.long 0xA30++0x03
line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
rgroup.long 0xA34++0x03
line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
rgroup.long 0xA38++0x03
line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
rgroup.long 0xA3C++0x03
line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x12)
group.long 0xA40++0x03
line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579  ,CPU Targets Byte Offset 579 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO578  ,CPU Targets Byte Offset 578 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO577  ,CPU Targets Byte Offset 577 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO576  ,CPU Targets Byte Offset 576 "
group.long 0xA44++0x03
line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583  ,CPU Targets Byte Offset 583 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO582  ,CPU Targets Byte Offset 582 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO581  ,CPU Targets Byte Offset 581 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO580  ,CPU Targets Byte Offset 580 "
group.long 0xA48++0x03
line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587  ,CPU Targets Byte Offset 587 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO586  ,CPU Targets Byte Offset 586 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO585  ,CPU Targets Byte Offset 585 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO584  ,CPU Targets Byte Offset 584 "
group.long 0xA4C++0x03
line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591  ,CPU Targets Byte Offset 591 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO590  ,CPU Targets Byte Offset 590 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO589  ,CPU Targets Byte Offset 589 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO588  ,CPU Targets Byte Offset 588 "
group.long 0xA50++0x03
line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595  ,CPU Targets Byte Offset 595 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO594  ,CPU Targets Byte Offset 594 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO593  ,CPU Targets Byte Offset 593 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO592  ,CPU Targets Byte Offset 592 "
group.long 0xA54++0x03
line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599  ,CPU Targets Byte Offset 599 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO598  ,CPU Targets Byte Offset 598 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO597  ,CPU Targets Byte Offset 597 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO596  ,CPU Targets Byte Offset 596 "
group.long 0xA58++0x03
line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603  ,CPU Targets Byte Offset 603 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO602  ,CPU Targets Byte Offset 602 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO601  ,CPU Targets Byte Offset 601 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO600  ,CPU Targets Byte Offset 600 "
group.long 0xA5C++0x03
line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607  ,CPU Targets Byte Offset 607 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO606  ,CPU Targets Byte Offset 606 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO605  ,CPU Targets Byte Offset 605 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO604  ,CPU Targets Byte Offset 604 "
else
rgroup.long 0xA40++0x03
line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
rgroup.long 0xA44++0x03
line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
rgroup.long 0xA48++0x03
line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
rgroup.long 0xA4C++0x03
line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
rgroup.long 0xA50++0x03
line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
rgroup.long 0xA54++0x03
line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
rgroup.long 0xA58++0x03
line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
rgroup.long 0xA5C++0x03
line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x13)
group.long 0xA60++0x03
line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611  ,CPU Targets Byte Offset 611 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO610  ,CPU Targets Byte Offset 610 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO609  ,CPU Targets Byte Offset 609 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO608  ,CPU Targets Byte Offset 608 "
group.long 0xA64++0x03
line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615  ,CPU Targets Byte Offset 615 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO614  ,CPU Targets Byte Offset 614 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO613  ,CPU Targets Byte Offset 613 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO612  ,CPU Targets Byte Offset 612 "
group.long 0xA68++0x03
line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619  ,CPU Targets Byte Offset 619 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO618  ,CPU Targets Byte Offset 618 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO617  ,CPU Targets Byte Offset 617 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO616  ,CPU Targets Byte Offset 616 "
group.long 0xA6C++0x03
line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623  ,CPU Targets Byte Offset 623 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO622  ,CPU Targets Byte Offset 622 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO621  ,CPU Targets Byte Offset 621 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO620  ,CPU Targets Byte Offset 620 "
group.long 0xA70++0x03
line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627  ,CPU Targets Byte Offset 627 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO626  ,CPU Targets Byte Offset 626 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO625  ,CPU Targets Byte Offset 625 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO624  ,CPU Targets Byte Offset 624 "
group.long 0xA74++0x03
line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631  ,CPU Targets Byte Offset 631 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO630  ,CPU Targets Byte Offset 630 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO629  ,CPU Targets Byte Offset 629 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO628  ,CPU Targets Byte Offset 628 "
group.long 0xA78++0x03
line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635  ,CPU Targets Byte Offset 635 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO634  ,CPU Targets Byte Offset 634 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO633  ,CPU Targets Byte Offset 633 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO632  ,CPU Targets Byte Offset 632 "
group.long 0xA7C++0x03
line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639  ,CPU Targets Byte Offset 639 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO638  ,CPU Targets Byte Offset 638 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO637  ,CPU Targets Byte Offset 637 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO636  ,CPU Targets Byte Offset 636 "
else
rgroup.long 0xA60++0x03
line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
rgroup.long 0xA64++0x03
line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
rgroup.long 0xA68++0x03
line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
rgroup.long 0xA6C++0x03
line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
rgroup.long 0xA70++0x03
line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
rgroup.long 0xA74++0x03
line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
rgroup.long 0xA78++0x03
line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
rgroup.long 0xA7C++0x03
line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x14)
group.long 0xA80++0x03
line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643  ,CPU Targets Byte Offset 643 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO642  ,CPU Targets Byte Offset 642 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO641  ,CPU Targets Byte Offset 641 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO640  ,CPU Targets Byte Offset 640 "
group.long 0xA84++0x03
line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647  ,CPU Targets Byte Offset 647 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO646  ,CPU Targets Byte Offset 646 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO645  ,CPU Targets Byte Offset 645 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO644  ,CPU Targets Byte Offset 644 "
group.long 0xA88++0x03
line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651  ,CPU Targets Byte Offset 651 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO650  ,CPU Targets Byte Offset 650 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO649  ,CPU Targets Byte Offset 649 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO648  ,CPU Targets Byte Offset 648 "
group.long 0xA8C++0x03
line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655  ,CPU Targets Byte Offset 655 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO654  ,CPU Targets Byte Offset 654 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO653  ,CPU Targets Byte Offset 653 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO652  ,CPU Targets Byte Offset 652 "
group.long 0xA90++0x03
line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659  ,CPU Targets Byte Offset 659 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO658  ,CPU Targets Byte Offset 658 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO657  ,CPU Targets Byte Offset 657 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO656  ,CPU Targets Byte Offset 656 "
group.long 0xA94++0x03
line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663  ,CPU Targets Byte Offset 663 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO662  ,CPU Targets Byte Offset 662 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO661  ,CPU Targets Byte Offset 661 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO660  ,CPU Targets Byte Offset 660 "
group.long 0xA98++0x03
line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667  ,CPU Targets Byte Offset 667 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO666  ,CPU Targets Byte Offset 666 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO665  ,CPU Targets Byte Offset 665 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO664  ,CPU Targets Byte Offset 664 "
group.long 0xA9C++0x03
line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671  ,CPU Targets Byte Offset 671 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO670  ,CPU Targets Byte Offset 670 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO669  ,CPU Targets Byte Offset 669 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO668  ,CPU Targets Byte Offset 668 "
else
rgroup.long 0xA80++0x03
line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
rgroup.long 0xA84++0x03
line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
rgroup.long 0xA88++0x03
line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
rgroup.long 0xA8C++0x03
line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
rgroup.long 0xA90++0x03
line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
rgroup.long 0xA94++0x03
line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
rgroup.long 0xA98++0x03
line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
rgroup.long 0xA9C++0x03
line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x15)
group.long 0xAA0++0x03
line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675  ,CPU Targets Byte Offset 675 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO674  ,CPU Targets Byte Offset 674 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO673  ,CPU Targets Byte Offset 673 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO672  ,CPU Targets Byte Offset 672 "
group.long 0xAA4++0x03
line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679  ,CPU Targets Byte Offset 679 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO678  ,CPU Targets Byte Offset 678 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO677  ,CPU Targets Byte Offset 677 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO676  ,CPU Targets Byte Offset 676 "
group.long 0xAA8++0x03
line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683  ,CPU Targets Byte Offset 683 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO682  ,CPU Targets Byte Offset 682 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO681  ,CPU Targets Byte Offset 681 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO680  ,CPU Targets Byte Offset 680 "
group.long 0xAAC++0x03
line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687  ,CPU Targets Byte Offset 687 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO686  ,CPU Targets Byte Offset 686 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO685  ,CPU Targets Byte Offset 685 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO684  ,CPU Targets Byte Offset 684 "
group.long 0xAB0++0x03
line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691  ,CPU Targets Byte Offset 691 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO690  ,CPU Targets Byte Offset 690 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO689  ,CPU Targets Byte Offset 689 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO688  ,CPU Targets Byte Offset 688 "
group.long 0xAB4++0x03
line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695  ,CPU Targets Byte Offset 695 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO694  ,CPU Targets Byte Offset 694 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO693  ,CPU Targets Byte Offset 693 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO692  ,CPU Targets Byte Offset 692 "
group.long 0xAB8++0x03
line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699  ,CPU Targets Byte Offset 699 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO698  ,CPU Targets Byte Offset 698 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO697  ,CPU Targets Byte Offset 697 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO696  ,CPU Targets Byte Offset 696 "
group.long 0xABC++0x03
line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703  ,CPU Targets Byte Offset 703 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO702  ,CPU Targets Byte Offset 702 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO701  ,CPU Targets Byte Offset 701 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO700  ,CPU Targets Byte Offset 700 "
else
rgroup.long 0xAA0++0x03
line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
rgroup.long 0xAA4++0x03
line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
rgroup.long 0xAA8++0x03
line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
rgroup.long 0xAAC++0x03
line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
rgroup.long 0xAB0++0x03
line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
rgroup.long 0xAB4++0x03
line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
rgroup.long 0xAB8++0x03
line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
rgroup.long 0xABC++0x03
line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x16)
group.long 0xAC0++0x03
line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707  ,CPU Targets Byte Offset 707 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO706  ,CPU Targets Byte Offset 706 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO705  ,CPU Targets Byte Offset 705 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO704  ,CPU Targets Byte Offset 704 "
group.long 0xAC4++0x03
line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711  ,CPU Targets Byte Offset 711 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO710  ,CPU Targets Byte Offset 710 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO709  ,CPU Targets Byte Offset 709 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO708  ,CPU Targets Byte Offset 708 "
group.long 0xAC8++0x03
line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715  ,CPU Targets Byte Offset 715 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO714  ,CPU Targets Byte Offset 714 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO713  ,CPU Targets Byte Offset 713 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO712  ,CPU Targets Byte Offset 712 "
group.long 0xACC++0x03
line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719  ,CPU Targets Byte Offset 719 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO718  ,CPU Targets Byte Offset 718 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO717  ,CPU Targets Byte Offset 717 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO716  ,CPU Targets Byte Offset 716 "
group.long 0xAD0++0x03
line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723  ,CPU Targets Byte Offset 723 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO722  ,CPU Targets Byte Offset 722 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO721  ,CPU Targets Byte Offset 721 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO720  ,CPU Targets Byte Offset 720 "
group.long 0xAD4++0x03
line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727  ,CPU Targets Byte Offset 727 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO726  ,CPU Targets Byte Offset 726 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO725  ,CPU Targets Byte Offset 725 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO724  ,CPU Targets Byte Offset 724 "
group.long 0xAD8++0x03
line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731  ,CPU Targets Byte Offset 731 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO730  ,CPU Targets Byte Offset 730 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO729  ,CPU Targets Byte Offset 729 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO728  ,CPU Targets Byte Offset 728 "
group.long 0xADC++0x03
line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735  ,CPU Targets Byte Offset 735 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO734  ,CPU Targets Byte Offset 734 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO733  ,CPU Targets Byte Offset 733 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO732  ,CPU Targets Byte Offset 732 "
else
rgroup.long 0xAC0++0x03
line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
rgroup.long 0xAC4++0x03
line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
rgroup.long 0xAC8++0x03
line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
rgroup.long 0xACC++0x03
line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
rgroup.long 0xAD0++0x03
line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
rgroup.long 0xAD4++0x03
line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
rgroup.long 0xAD8++0x03
line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
rgroup.long 0xADC++0x03
line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x17)
group.long 0xAE0++0x03
line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739  ,CPU Targets Byte Offset 739 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO738  ,CPU Targets Byte Offset 738 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO737  ,CPU Targets Byte Offset 737 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO736  ,CPU Targets Byte Offset 736 "
group.long 0xAE4++0x03
line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743  ,CPU Targets Byte Offset 743 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO742  ,CPU Targets Byte Offset 742 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO741  ,CPU Targets Byte Offset 741 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO740  ,CPU Targets Byte Offset 740 "
group.long 0xAE8++0x03
line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747  ,CPU Targets Byte Offset 747 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO746  ,CPU Targets Byte Offset 746 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO745  ,CPU Targets Byte Offset 745 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO744  ,CPU Targets Byte Offset 744 "
group.long 0xAEC++0x03
line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751  ,CPU Targets Byte Offset 751 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO750  ,CPU Targets Byte Offset 750 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO749  ,CPU Targets Byte Offset 749 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO748  ,CPU Targets Byte Offset 748 "
group.long 0xAF0++0x03
line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755  ,CPU Targets Byte Offset 755 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO754  ,CPU Targets Byte Offset 754 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO753  ,CPU Targets Byte Offset 753 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO752  ,CPU Targets Byte Offset 752 "
group.long 0xAF4++0x03
line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759  ,CPU Targets Byte Offset 759 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO758  ,CPU Targets Byte Offset 758 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO757  ,CPU Targets Byte Offset 757 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO756  ,CPU Targets Byte Offset 756 "
group.long 0xAF8++0x03
line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763  ,CPU Targets Byte Offset 763 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO762  ,CPU Targets Byte Offset 762 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO761  ,CPU Targets Byte Offset 761 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO760  ,CPU Targets Byte Offset 760 "
group.long 0xAFC++0x03
line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767  ,CPU Targets Byte Offset 767 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO766  ,CPU Targets Byte Offset 766 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO765  ,CPU Targets Byte Offset 765 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO764  ,CPU Targets Byte Offset 764 "
else
rgroup.long 0xAE0++0x03
line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
rgroup.long 0xAE4++0x03
line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
rgroup.long 0xAE8++0x03
line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
rgroup.long 0xAEC++0x03
line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
rgroup.long 0xAF0++0x03
line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
rgroup.long 0xAF4++0x03
line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
rgroup.long 0xAF8++0x03
line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
rgroup.long 0xAFC++0x03
line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x18)
group.long 0xB00++0x03
line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771  ,CPU Targets Byte Offset 771 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO770  ,CPU Targets Byte Offset 770 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO769  ,CPU Targets Byte Offset 769 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO768  ,CPU Targets Byte Offset 768 "
group.long 0xB04++0x03
line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775  ,CPU Targets Byte Offset 775 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO774  ,CPU Targets Byte Offset 774 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO773  ,CPU Targets Byte Offset 773 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO772  ,CPU Targets Byte Offset 772 "
group.long 0xB08++0x03
line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779  ,CPU Targets Byte Offset 779 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO778  ,CPU Targets Byte Offset 778 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO777  ,CPU Targets Byte Offset 777 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO776  ,CPU Targets Byte Offset 776 "
group.long 0xB0C++0x03
line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783  ,CPU Targets Byte Offset 783 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO782  ,CPU Targets Byte Offset 782 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO781  ,CPU Targets Byte Offset 781 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO780  ,CPU Targets Byte Offset 780 "
group.long 0xB10++0x03
line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787  ,CPU Targets Byte Offset 787 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO786  ,CPU Targets Byte Offset 786 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO785  ,CPU Targets Byte Offset 785 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO784  ,CPU Targets Byte Offset 784 "
group.long 0xB14++0x03
line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791  ,CPU Targets Byte Offset 791 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO790  ,CPU Targets Byte Offset 790 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO789  ,CPU Targets Byte Offset 789 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO788  ,CPU Targets Byte Offset 788 "
group.long 0xB18++0x03
line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795  ,CPU Targets Byte Offset 795 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO794  ,CPU Targets Byte Offset 794 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO793  ,CPU Targets Byte Offset 793 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO792  ,CPU Targets Byte Offset 792 "
group.long 0xB1C++0x03
line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799  ,CPU Targets Byte Offset 799 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO798  ,CPU Targets Byte Offset 798 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO797  ,CPU Targets Byte Offset 797 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO796  ,CPU Targets Byte Offset 796 "
else
rgroup.long 0xB00++0x03
line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
rgroup.long 0xB04++0x03
line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
rgroup.long 0xB08++0x03
line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
rgroup.long 0xB0C++0x03
line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
rgroup.long 0xB10++0x03
line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
rgroup.long 0xB14++0x03
line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
rgroup.long 0xB18++0x03
line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
rgroup.long 0xB1C++0x03
line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x19)
group.long 0xB20++0x03
line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803  ,CPU Targets Byte Offset 803 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO802  ,CPU Targets Byte Offset 802 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO801  ,CPU Targets Byte Offset 801 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO800  ,CPU Targets Byte Offset 800 "
group.long 0xB24++0x03
line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807  ,CPU Targets Byte Offset 807 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO806  ,CPU Targets Byte Offset 806 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO805  ,CPU Targets Byte Offset 805 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO804  ,CPU Targets Byte Offset 804 "
group.long 0xB28++0x03
line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811  ,CPU Targets Byte Offset 811 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO810  ,CPU Targets Byte Offset 810 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO809  ,CPU Targets Byte Offset 809 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO808  ,CPU Targets Byte Offset 808 "
group.long 0xB2C++0x03
line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815  ,CPU Targets Byte Offset 815 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO814  ,CPU Targets Byte Offset 814 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO813  ,CPU Targets Byte Offset 813 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO812  ,CPU Targets Byte Offset 812 "
group.long 0xB30++0x03
line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819  ,CPU Targets Byte Offset 819 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO818  ,CPU Targets Byte Offset 818 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO817  ,CPU Targets Byte Offset 817 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO816  ,CPU Targets Byte Offset 816 "
group.long 0xB34++0x03
line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823  ,CPU Targets Byte Offset 823 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO822  ,CPU Targets Byte Offset 822 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO821  ,CPU Targets Byte Offset 821 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO820  ,CPU Targets Byte Offset 820 "
group.long 0xB38++0x03
line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827  ,CPU Targets Byte Offset 827 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO826  ,CPU Targets Byte Offset 826 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO825  ,CPU Targets Byte Offset 825 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO824  ,CPU Targets Byte Offset 824 "
group.long 0xB3C++0x03
line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831  ,CPU Targets Byte Offset 831 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO830  ,CPU Targets Byte Offset 830 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO829  ,CPU Targets Byte Offset 829 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO828  ,CPU Targets Byte Offset 828 "
else
rgroup.long 0xB20++0x03
line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
rgroup.long 0xB24++0x03
line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
rgroup.long 0xB28++0x03
line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
rgroup.long 0xB2C++0x03
line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
rgroup.long 0xB30++0x03
line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
rgroup.long 0xB34++0x03
line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
rgroup.long 0xB38++0x03
line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
rgroup.long 0xB3C++0x03
line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1A)
group.long 0xB40++0x03
line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835  ,CPU Targets Byte Offset 835 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO834  ,CPU Targets Byte Offset 834 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO833  ,CPU Targets Byte Offset 833 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO832  ,CPU Targets Byte Offset 832 "
group.long 0xB44++0x03
line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839  ,CPU Targets Byte Offset 839 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO838  ,CPU Targets Byte Offset 838 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO837  ,CPU Targets Byte Offset 837 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO836  ,CPU Targets Byte Offset 836 "
group.long 0xB48++0x03
line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843  ,CPU Targets Byte Offset 843 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO842  ,CPU Targets Byte Offset 842 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO841  ,CPU Targets Byte Offset 841 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO840  ,CPU Targets Byte Offset 840 "
group.long 0xB4C++0x03
line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847  ,CPU Targets Byte Offset 847 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO846  ,CPU Targets Byte Offset 846 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO845  ,CPU Targets Byte Offset 845 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO844  ,CPU Targets Byte Offset 844 "
group.long 0xB50++0x03
line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851  ,CPU Targets Byte Offset 851 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO850  ,CPU Targets Byte Offset 850 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO849  ,CPU Targets Byte Offset 849 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO848  ,CPU Targets Byte Offset 848 "
group.long 0xB54++0x03
line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855  ,CPU Targets Byte Offset 855 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO854  ,CPU Targets Byte Offset 854 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO853  ,CPU Targets Byte Offset 853 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO852  ,CPU Targets Byte Offset 852 "
group.long 0xB58++0x03
line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859  ,CPU Targets Byte Offset 859 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO858  ,CPU Targets Byte Offset 858 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO857  ,CPU Targets Byte Offset 857 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO856  ,CPU Targets Byte Offset 856 "
group.long 0xB5C++0x03
line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863  ,CPU Targets Byte Offset 863 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO862  ,CPU Targets Byte Offset 862 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO861  ,CPU Targets Byte Offset 861 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO860  ,CPU Targets Byte Offset 860 "
else
rgroup.long 0xB40++0x03
line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
rgroup.long 0xB44++0x03
line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
rgroup.long 0xB48++0x03
line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
rgroup.long 0xB4C++0x03
line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
rgroup.long 0xB50++0x03
line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
rgroup.long 0xB54++0x03
line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
rgroup.long 0xB58++0x03
line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
rgroup.long 0xB5C++0x03
line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1B)
group.long 0xB60++0x03
line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867  ,CPU Targets Byte Offset 867 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO866  ,CPU Targets Byte Offset 866 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO865  ,CPU Targets Byte Offset 865 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO864  ,CPU Targets Byte Offset 864 "
group.long 0xB64++0x03
line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871  ,CPU Targets Byte Offset 871 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO870  ,CPU Targets Byte Offset 870 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO869  ,CPU Targets Byte Offset 869 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO868  ,CPU Targets Byte Offset 868 "
group.long 0xB68++0x03
line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875  ,CPU Targets Byte Offset 875 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO874  ,CPU Targets Byte Offset 874 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO873  ,CPU Targets Byte Offset 873 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO872  ,CPU Targets Byte Offset 872 "
group.long 0xB6C++0x03
line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879  ,CPU Targets Byte Offset 879 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO878  ,CPU Targets Byte Offset 878 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO877  ,CPU Targets Byte Offset 877 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO876  ,CPU Targets Byte Offset 876 "
group.long 0xB70++0x03
line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883  ,CPU Targets Byte Offset 883 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO882  ,CPU Targets Byte Offset 882 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO881  ,CPU Targets Byte Offset 881 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO880  ,CPU Targets Byte Offset 880 "
group.long 0xB74++0x03
line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887  ,CPU Targets Byte Offset 887 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO886  ,CPU Targets Byte Offset 886 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO885  ,CPU Targets Byte Offset 885 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO884  ,CPU Targets Byte Offset 884 "
group.long 0xB78++0x03
line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891  ,CPU Targets Byte Offset 891 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO890  ,CPU Targets Byte Offset 890 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO889  ,CPU Targets Byte Offset 889 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO888  ,CPU Targets Byte Offset 888 "
group.long 0xB7C++0x03
line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895  ,CPU Targets Byte Offset 895 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO894  ,CPU Targets Byte Offset 894 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO893  ,CPU Targets Byte Offset 893 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO892  ,CPU Targets Byte Offset 892 "
else
rgroup.long 0xB60++0x03
line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
rgroup.long 0xB64++0x03
line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
rgroup.long 0xB68++0x03
line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
rgroup.long 0xB6C++0x03
line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
rgroup.long 0xB70++0x03
line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
rgroup.long 0xB74++0x03
line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
rgroup.long 0xB78++0x03
line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
rgroup.long 0xB7C++0x03
line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1C)
group.long 0xB80++0x03
line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899  ,CPU Targets Byte Offset 899 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO898  ,CPU Targets Byte Offset 898 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO897  ,CPU Targets Byte Offset 897 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO896  ,CPU Targets Byte Offset 896 "
group.long 0xB84++0x03
line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903  ,CPU Targets Byte Offset 903 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO902  ,CPU Targets Byte Offset 902 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO901  ,CPU Targets Byte Offset 901 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO900  ,CPU Targets Byte Offset 900 "
group.long 0xB88++0x03
line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907  ,CPU Targets Byte Offset 907 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO906  ,CPU Targets Byte Offset 906 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO905  ,CPU Targets Byte Offset 905 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO904  ,CPU Targets Byte Offset 904 "
group.long 0xB8C++0x03
line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911  ,CPU Targets Byte Offset 911 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO910  ,CPU Targets Byte Offset 910 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO909  ,CPU Targets Byte Offset 909 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO908  ,CPU Targets Byte Offset 908 "
group.long 0xB90++0x03
line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915  ,CPU Targets Byte Offset 915 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO914  ,CPU Targets Byte Offset 914 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO913  ,CPU Targets Byte Offset 913 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO912  ,CPU Targets Byte Offset 912 "
group.long 0xB94++0x03
line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919  ,CPU Targets Byte Offset 919 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO918  ,CPU Targets Byte Offset 918 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO917  ,CPU Targets Byte Offset 917 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO916  ,CPU Targets Byte Offset 916 "
group.long 0xB98++0x03
line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923  ,CPU Targets Byte Offset 923 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO922  ,CPU Targets Byte Offset 922 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO921  ,CPU Targets Byte Offset 921 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO920  ,CPU Targets Byte Offset 920 "
group.long 0xB9C++0x03
line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927  ,CPU Targets Byte Offset 927 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO926  ,CPU Targets Byte Offset 926 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO925  ,CPU Targets Byte Offset 925 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO924  ,CPU Targets Byte Offset 924 "
else
rgroup.long 0xB80++0x03
line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
rgroup.long 0xB84++0x03
line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
rgroup.long 0xB88++0x03
line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
rgroup.long 0xB8C++0x03
line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
rgroup.long 0xB90++0x03
line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
rgroup.long 0xB94++0x03
line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
rgroup.long 0xB98++0x03
line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
rgroup.long 0xB9C++0x03
line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1D)
group.long 0xBA0++0x03
line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931  ,CPU Targets Byte Offset 931 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO930  ,CPU Targets Byte Offset 930 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO929  ,CPU Targets Byte Offset 929 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO928  ,CPU Targets Byte Offset 928 "
group.long 0xBA4++0x03
line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935  ,CPU Targets Byte Offset 935 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO934  ,CPU Targets Byte Offset 934 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO933  ,CPU Targets Byte Offset 933 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO932  ,CPU Targets Byte Offset 932 "
group.long 0xBA8++0x03
line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939  ,CPU Targets Byte Offset 939 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO938  ,CPU Targets Byte Offset 938 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO937  ,CPU Targets Byte Offset 937 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO936  ,CPU Targets Byte Offset 936 "
group.long 0xBAC++0x03
line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943  ,CPU Targets Byte Offset 943 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO942  ,CPU Targets Byte Offset 942 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO941  ,CPU Targets Byte Offset 941 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO940  ,CPU Targets Byte Offset 940 "
group.long 0xBB0++0x03
line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947  ,CPU Targets Byte Offset 947 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO946  ,CPU Targets Byte Offset 946 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO945  ,CPU Targets Byte Offset 945 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO944  ,CPU Targets Byte Offset 944 "
group.long 0xBB4++0x03
line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951  ,CPU Targets Byte Offset 951 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO950  ,CPU Targets Byte Offset 950 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO949  ,CPU Targets Byte Offset 949 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO948  ,CPU Targets Byte Offset 948 "
group.long 0xBB8++0x03
line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955  ,CPU Targets Byte Offset 955 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO954  ,CPU Targets Byte Offset 954 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO953  ,CPU Targets Byte Offset 953 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO952  ,CPU Targets Byte Offset 952 "
group.long 0xBBC++0x03
line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959  ,CPU Targets Byte Offset 959 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO958  ,CPU Targets Byte Offset 958 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO957  ,CPU Targets Byte Offset 957 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO956  ,CPU Targets Byte Offset 956 "
else
rgroup.long 0xBA0++0x03
line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
rgroup.long 0xBA4++0x03
line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
rgroup.long 0xBA8++0x03
line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
rgroup.long 0xBAC++0x03
line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
rgroup.long 0xBB0++0x03
line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
rgroup.long 0xBB4++0x03
line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
rgroup.long 0xBB8++0x03
line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
rgroup.long 0xBBC++0x03
line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1E)
group.long 0xBC0++0x03
line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963  ,CPU Targets Byte Offset 963 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO962  ,CPU Targets Byte Offset 962 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO961  ,CPU Targets Byte Offset 961 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO960  ,CPU Targets Byte Offset 960 "
group.long 0xBC4++0x03
line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967  ,CPU Targets Byte Offset 967 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO966  ,CPU Targets Byte Offset 966 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO965  ,CPU Targets Byte Offset 965 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO964  ,CPU Targets Byte Offset 964 "
group.long 0xBC8++0x03
line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971  ,CPU Targets Byte Offset 971 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO970  ,CPU Targets Byte Offset 970 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO969  ,CPU Targets Byte Offset 969 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO968  ,CPU Targets Byte Offset 968 "
group.long 0xBCC++0x03
line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975  ,CPU Targets Byte Offset 975 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO974  ,CPU Targets Byte Offset 974 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO973  ,CPU Targets Byte Offset 973 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO972  ,CPU Targets Byte Offset 972 "
group.long 0xBD0++0x03
line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979  ,CPU Targets Byte Offset 979 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO978  ,CPU Targets Byte Offset 978 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO977  ,CPU Targets Byte Offset 977 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO976  ,CPU Targets Byte Offset 976 "
group.long 0xBD4++0x03
line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983  ,CPU Targets Byte Offset 983 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO982  ,CPU Targets Byte Offset 982 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO981  ,CPU Targets Byte Offset 981 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO980  ,CPU Targets Byte Offset 980 "
group.long 0xBD8++0x03
line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987  ,CPU Targets Byte Offset 987 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO986  ,CPU Targets Byte Offset 986 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO985  ,CPU Targets Byte Offset 985 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO984  ,CPU Targets Byte Offset 984 "
group.long 0xBDC++0x03
line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991  ,CPU Targets Byte Offset 991 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO990  ,CPU Targets Byte Offset 990 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO989  ,CPU Targets Byte Offset 989 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO988  ,CPU Targets Byte Offset 988 "
else
rgroup.long 0xBC0++0x03
line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
rgroup.long 0xBC4++0x03
line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
rgroup.long 0xBC8++0x03
line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
rgroup.long 0xBCC++0x03
line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
rgroup.long 0xBD0++0x03
line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
rgroup.long 0xBD4++0x03
line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
rgroup.long 0xBD8++0x03
line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
rgroup.long 0xBDC++0x03
line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1F)
group.long 0xBE0++0x03
line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO995  ,CPU Targets Byte Offset 995 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO994  ,CPU Targets Byte Offset 994 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO993  ,CPU Targets Byte Offset 993 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO992  ,CPU Targets Byte Offset 992 "
group.long 0xBE4++0x03
line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO999  ,CPU Targets Byte Offset 999 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO998  ,CPU Targets Byte Offset 998 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO997  ,CPU Targets Byte Offset 997 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO996  ,CPU Targets Byte Offset 996 "
group.long 0xBE8++0x03
line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1003 ,CPU Targets Byte Offset 1003"
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO1002 ,CPU Targets Byte Offset 1002"
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO1001 ,CPU Targets Byte Offset 1001"
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO1000 ,CPU Targets Byte Offset 1000"
group.long 0xBEC++0x03
line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1007 ,CPU Targets Byte Offset 1007"
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO1006 ,CPU Targets Byte Offset 1006"
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO1005 ,CPU Targets Byte Offset 1005"
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO1004 ,CPU Targets Byte Offset 1004"
group.long 0xBF0++0x03
line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1011 ,CPU Targets Byte Offset 1011"
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO1010 ,CPU Targets Byte Offset 1010"
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO1009 ,CPU Targets Byte Offset 1009"
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO1008 ,CPU Targets Byte Offset 1008"
group.long 0xBF4++0x03
line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1015 ,CPU Targets Byte Offset 1015"
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO1014 ,CPU Targets Byte Offset 1014"
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO1013 ,CPU Targets Byte Offset 1013"
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO1012 ,CPU Targets Byte Offset 1012"
group.long 0xBF8++0x03
line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1019 ,CPU Targets Byte Offset 1019"
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO1018 ,CPU Targets Byte Offset 1018"
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO1017 ,CPU Targets Byte Offset 1017"
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO1016 ,CPU Targets Byte Offset 1016"
else
rgroup.long 0xBE0++0x03
line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248"
rgroup.long 0xBE4++0x03
line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249"
rgroup.long 0xBE8++0x03
line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250"
rgroup.long 0xBEC++0x03
line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251"
rgroup.long 0xBF0++0x03
line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252"
rgroup.long 0xBF4++0x03
line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253"
rgroup.long 0xBF8++0x03
line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254"
endif
else
rgroup.long 0x800++0x03
line.long 0x00 "GICD_ITARGETSR0  ,Interrupt Processor Targets Register 0  "
rgroup.long 0x804++0x03
line.long 0x00 "GICD_ITARGETSR1  ,Interrupt Processor Targets Register 1  "
rgroup.long 0x808++0x03
line.long 0x00 "GICD_ITARGETSR2  ,Interrupt Processor Targets Register 2  "
rgroup.long 0x80C++0x03
line.long 0x00 "GICD_ITARGETSR3  ,Interrupt Processor Targets Register 3  "
rgroup.long 0x810++0x03
line.long 0x00 "GICD_ITARGETSR4  ,Interrupt Processor Targets Register 4  "
rgroup.long 0x814++0x03
line.long 0x00 "GICD_ITARGETSR5  ,Interrupt Processor Targets Register 5  "
rgroup.long 0x818++0x03
line.long 0x00 "GICD_ITARGETSR6  ,Interrupt Processor Targets Register 6  "
rgroup.long 0x81C++0x03
line.long 0x00 "GICD_ITARGETSR7  ,Interrupt Processor Targets Register 7  "
rgroup.long 0x820++0x03
line.long 0x00 "GICD_ITARGETSR8  ,Interrupt Processor Targets Register 8  "
rgroup.long 0x824++0x03
line.long 0x00 "GICD_ITARGETSR9  ,Interrupt Processor Targets Register 9  "
rgroup.long 0x828++0x03
line.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 "
rgroup.long 0x82C++0x03
line.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 "
rgroup.long 0x830++0x03
line.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 "
rgroup.long 0x834++0x03
line.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 "
rgroup.long 0x838++0x03
line.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 "
rgroup.long 0x83C++0x03
line.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 "
rgroup.long 0x840++0x03
line.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 "
rgroup.long 0x844++0x03
line.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 "
rgroup.long 0x848++0x03
line.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 "
rgroup.long 0x84C++0x03
line.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 "
rgroup.long 0x850++0x03
line.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 "
rgroup.long 0x854++0x03
line.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 "
rgroup.long 0x858++0x03
line.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 "
rgroup.long 0x85C++0x03
line.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 "
rgroup.long 0x860++0x03
line.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 "
rgroup.long 0x864++0x03
line.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 "
rgroup.long 0x868++0x03
line.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 "
rgroup.long 0x86C++0x03
line.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 "
rgroup.long 0x870++0x03
line.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 "
rgroup.long 0x874++0x03
line.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 "
rgroup.long 0x878++0x03
line.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 "
rgroup.long 0x87C++0x03
line.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 "
rgroup.long 0x880++0x03
line.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 "
rgroup.long 0x884++0x03
line.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 "
rgroup.long 0x888++0x03
line.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 "
rgroup.long 0x88C++0x03
line.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 "
rgroup.long 0x890++0x03
line.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 "
rgroup.long 0x894++0x03
line.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 "
rgroup.long 0x898++0x03
line.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 "
rgroup.long 0x89C++0x03
line.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 "
rgroup.long 0x8A0++0x03
line.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 "
rgroup.long 0x8A4++0x03
line.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 "
rgroup.long 0x8A8++0x03
line.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 "
rgroup.long 0x8AC++0x03
line.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 "
rgroup.long 0x8B0++0x03
line.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 "
rgroup.long 0x8B4++0x03
line.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 "
rgroup.long 0x8B8++0x03
line.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 "
rgroup.long 0x8BC++0x03
line.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 "
rgroup.long 0x8C0++0x03
line.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 "
rgroup.long 0x8C4++0x03
line.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 "
rgroup.long 0x8C8++0x03
line.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 "
rgroup.long 0x8CC++0x03
line.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 "
rgroup.long 0x8D0++0x03
line.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 "
rgroup.long 0x8D4++0x03
line.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 "
rgroup.long 0x8D8++0x03
line.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 "
rgroup.long 0x8DC++0x03
line.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 "
rgroup.long 0x8E0++0x03
line.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 "
rgroup.long 0x8E4++0x03
line.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 "
rgroup.long 0x8E8++0x03
line.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 "
rgroup.long 0x8EC++0x03
line.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 "
rgroup.long 0x8F0++0x03
line.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 "
rgroup.long 0x8F4++0x03
line.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 "
rgroup.long 0x8F8++0x03
line.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 "
rgroup.long 0x8FC++0x03
line.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 "
rgroup.long 0x900++0x03
line.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 "
rgroup.long 0x904++0x03
line.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 "
rgroup.long 0x908++0x03
line.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 "
rgroup.long 0x90C++0x03
line.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 "
rgroup.long 0x910++0x03
line.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 "
rgroup.long 0x914++0x03
line.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 "
rgroup.long 0x918++0x03
line.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 "
rgroup.long 0x91C++0x03
line.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 "
rgroup.long 0x920++0x03
line.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 "
rgroup.long 0x924++0x03
line.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 "
rgroup.long 0x928++0x03
line.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 "
rgroup.long 0x92C++0x03
line.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 "
rgroup.long 0x930++0x03
line.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 "
rgroup.long 0x934++0x03
line.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 "
rgroup.long 0x938++0x03
line.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 "
rgroup.long 0x93C++0x03
line.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 "
rgroup.long 0x940++0x03
line.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 "
rgroup.long 0x944++0x03
line.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 "
rgroup.long 0x948++0x03
line.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 "
rgroup.long 0x94C++0x03
line.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 "
rgroup.long 0x950++0x03
line.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 "
rgroup.long 0x954++0x03
line.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 "
rgroup.long 0x958++0x03
line.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 "
rgroup.long 0x95C++0x03
line.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 "
rgroup.long 0x960++0x03
line.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 "
rgroup.long 0x964++0x03
line.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 "
rgroup.long 0x968++0x03
line.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 "
rgroup.long 0x96C++0x03
line.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 "
rgroup.long 0x970++0x03
line.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 "
rgroup.long 0x974++0x03
line.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 "
rgroup.long 0x978++0x03
line.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 "
rgroup.long 0x97C++0x03
line.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 "
rgroup.long 0x980++0x03
line.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 "
rgroup.long 0x984++0x03
line.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 "
rgroup.long 0x988++0x03
line.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 "
rgroup.long 0x98C++0x03
line.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 "
rgroup.long 0x990++0x03
line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
rgroup.long 0x994++0x03
line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
rgroup.long 0x998++0x03
line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
rgroup.long 0x99C++0x03
line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
rgroup.long 0x9A0++0x03
line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
rgroup.long 0x9A4++0x03
line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
rgroup.long 0x9A8++0x03
line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
rgroup.long 0x9AC++0x03
line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
rgroup.long 0x9B0++0x03
line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
rgroup.long 0x9B4++0x03
line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
rgroup.long 0x9B8++0x03
line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
rgroup.long 0x9BC++0x03
line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
rgroup.long 0x9C0++0x03
line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
rgroup.long 0x9C4++0x03
line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
rgroup.long 0x9C8++0x03
line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
rgroup.long 0x9CC++0x03
line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
rgroup.long 0x9D0++0x03
line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
rgroup.long 0x9D4++0x03
line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
rgroup.long 0x9D8++0x03
line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
rgroup.long 0x9DC++0x03
line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
rgroup.long 0x9E0++0x03
line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
rgroup.long 0x9E4++0x03
line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
rgroup.long 0x9E8++0x03
line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
rgroup.long 0x9EC++0x03
line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
rgroup.long 0x9F0++0x03
line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
rgroup.long 0x9F4++0x03
line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
rgroup.long 0x9F8++0x03
line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
rgroup.long 0x9FC++0x03
line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
rgroup.long 0xA00++0x03
line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
rgroup.long 0xA04++0x03
line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
rgroup.long 0xA08++0x03
line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
rgroup.long 0xA0C++0x03
line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
rgroup.long 0xA10++0x03
line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
rgroup.long 0xA14++0x03
line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
rgroup.long 0xA18++0x03
line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
rgroup.long 0xA1C++0x03
line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
rgroup.long 0xA20++0x03
line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
rgroup.long 0xA24++0x03
line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
rgroup.long 0xA28++0x03
line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
rgroup.long 0xA2C++0x03
line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
rgroup.long 0xA30++0x03
line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
rgroup.long 0xA34++0x03
line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
rgroup.long 0xA38++0x03
line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
rgroup.long 0xA3C++0x03
line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
rgroup.long 0xA40++0x03
line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
rgroup.long 0xA44++0x03
line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
rgroup.long 0xA48++0x03
line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
rgroup.long 0xA4C++0x03
line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
rgroup.long 0xA50++0x03
line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
rgroup.long 0xA54++0x03
line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
rgroup.long 0xA58++0x03
line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
rgroup.long 0xA5C++0x03
line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
rgroup.long 0xA60++0x03
line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
rgroup.long 0xA64++0x03
line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
rgroup.long 0xA68++0x03
line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
rgroup.long 0xA6C++0x03
line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
rgroup.long 0xA70++0x03
line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
rgroup.long 0xA74++0x03
line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
rgroup.long 0xA78++0x03
line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
rgroup.long 0xA7C++0x03
line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
rgroup.long 0xA80++0x03
line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
rgroup.long 0xA84++0x03
line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
rgroup.long 0xA88++0x03
line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
rgroup.long 0xA8C++0x03
line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
rgroup.long 0xA90++0x03
line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
rgroup.long 0xA94++0x03
line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
rgroup.long 0xA98++0x03
line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
rgroup.long 0xA9C++0x03
line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
rgroup.long 0xAA0++0x03
line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
rgroup.long 0xAA4++0x03
line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
rgroup.long 0xAA8++0x03
line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
rgroup.long 0xAAC++0x03
line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
rgroup.long 0xAB0++0x03
line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
rgroup.long 0xAB4++0x03
line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
rgroup.long 0xAB8++0x03
line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
rgroup.long 0xABC++0x03
line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
rgroup.long 0xAC0++0x03
line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
rgroup.long 0xAC4++0x03
line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
rgroup.long 0xAC8++0x03
line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
rgroup.long 0xACC++0x03
line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
rgroup.long 0xAD0++0x03
line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
rgroup.long 0xAD4++0x03
line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
rgroup.long 0xAD8++0x03
line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
rgroup.long 0xADC++0x03
line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
rgroup.long 0xAE0++0x03
line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
rgroup.long 0xAE4++0x03
line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
rgroup.long 0xAE8++0x03
line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
rgroup.long 0xAEC++0x03
line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
rgroup.long 0xAF0++0x03
line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
rgroup.long 0xAF4++0x03
line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
rgroup.long 0xAF8++0x03
line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
rgroup.long 0xAFC++0x03
line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
rgroup.long 0xB00++0x03
line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
rgroup.long 0xB04++0x03
line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
rgroup.long 0xB08++0x03
line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
rgroup.long 0xB0C++0x03
line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
rgroup.long 0xB10++0x03
line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
rgroup.long 0xB14++0x03
line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
rgroup.long 0xB18++0x03
line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
rgroup.long 0xB1C++0x03
line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
rgroup.long 0xB20++0x03
line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
rgroup.long 0xB24++0x03
line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
rgroup.long 0xB28++0x03
line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
rgroup.long 0xB2C++0x03
line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
rgroup.long 0xB30++0x03
line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
rgroup.long 0xB34++0x03
line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
rgroup.long 0xB38++0x03
line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
rgroup.long 0xB3C++0x03
line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
rgroup.long 0xB40++0x03
line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
rgroup.long 0xB44++0x03
line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
rgroup.long 0xB48++0x03
line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
rgroup.long 0xB4C++0x03
line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
rgroup.long 0xB50++0x03
line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
rgroup.long 0xB54++0x03
line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
rgroup.long 0xB58++0x03
line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
rgroup.long 0xB5C++0x03
line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
rgroup.long 0xB60++0x03
line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
rgroup.long 0xB64++0x03
line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
rgroup.long 0xB68++0x03
line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
rgroup.long 0xB6C++0x03
line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
rgroup.long 0xB70++0x03
line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
rgroup.long 0xB74++0x03
line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
rgroup.long 0xB78++0x03
line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
rgroup.long 0xB7C++0x03
line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
rgroup.long 0xB80++0x03
line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
rgroup.long 0xB84++0x03
line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
rgroup.long 0xB88++0x03
line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
rgroup.long 0xB8C++0x03
line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
rgroup.long 0xB90++0x03
line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
rgroup.long 0xB94++0x03
line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
rgroup.long 0xB98++0x03
line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
rgroup.long 0xB9C++0x03
line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
rgroup.long 0xBA0++0x03
line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
rgroup.long 0xBA4++0x03
line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
rgroup.long 0xBA8++0x03
line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
rgroup.long 0xBAC++0x03
line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
rgroup.long 0xBB0++0x03
line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
rgroup.long 0xBB4++0x03
line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
rgroup.long 0xBB8++0x03
line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
rgroup.long 0xBBC++0x03
line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
rgroup.long 0xBC0++0x03
line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
rgroup.long 0xBC4++0x03
line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
rgroup.long 0xBC8++0x03
line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
rgroup.long 0xBCC++0x03
line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
rgroup.long 0xBD0++0x03
line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
rgroup.long 0xBD4++0x03
line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
rgroup.long 0xBD8++0x03
line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
rgroup.long 0xBDC++0x03
line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
rgroup.long 0xBE0++0x03
line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248"
rgroup.long 0xBE4++0x03
line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249"
rgroup.long 0xBE8++0x03
line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250"
rgroup.long 0xBEC++0x03
line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251"
rgroup.long 0xBF0++0x03
line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252"
rgroup.long 0xBF4++0x03
line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253"
rgroup.long 0xBF8++0x03
line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254"
endif
tree.end
width 14.
tree "Configuration Registers"
rgroup.long 0xC00++0x03
line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register"
textline "                       "
rgroup.long 0xC04++0x03
line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1)
group.long 0xC08++0x03
line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC0C++0x03
line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC08++0x03
line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
rgroup.long 0xC0C++0x03
line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x2)
group.long 0xC10++0x03
line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC14++0x03
line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC10++0x03
line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
rgroup.long 0xC14++0x03
line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x3)
group.long 0xC18++0x03
line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC1C++0x03
line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC18++0x03
line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
rgroup.long 0xC1C++0x03
line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x4)
group.long 0xC20++0x03
line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC24++0x03
line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC20++0x03
line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
rgroup.long 0xC24++0x03
line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x5)
group.long 0xC28++0x03
line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC2C++0x03
line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC28++0x03
line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
rgroup.long 0xC2C++0x03
line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x6)
group.long 0xC30++0x03
line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC34++0x03
line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC30++0x03
line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
rgroup.long 0xC34++0x03
line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x7)
group.long 0xC38++0x03
line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC3C++0x03
line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC38++0x03
line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
rgroup.long 0xC3C++0x03
line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x8)
group.long 0xC40++0x03
line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC44++0x03
line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC40++0x03
line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
rgroup.long 0xC44++0x03
line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x9)
group.long 0xC48++0x03
line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC4C++0x03
line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC48++0x03
line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
rgroup.long 0xC4C++0x03
line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0xA)
group.long 0xC50++0x03
line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC54++0x03
line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC50++0x03
line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
rgroup.long 0xC54++0x03
line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0xB)
group.long 0xC58++0x03
line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC5C++0x03
line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC58++0x03
line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
rgroup.long 0xC5C++0x03
line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0xC)
group.long 0xC60++0x03
line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC64++0x03
line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC60++0x03
line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
rgroup.long 0xC64++0x03
line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0xD)
group.long 0xC68++0x03
line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC6C++0x03
line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC68++0x03
line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
rgroup.long 0xC6C++0x03
line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0xE)
group.long 0xC70++0x03
line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC74++0x03
line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC70++0x03
line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
rgroup.long 0xC74++0x03
line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0xF)
group.long 0xC78++0x03
line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC7C++0x03
line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC78++0x03
line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
rgroup.long 0xC7C++0x03
line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x10)
group.long 0xC80++0x03
line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC84++0x03
line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC80++0x03
line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
rgroup.long 0xC84++0x03
line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x11)
group.long 0xC88++0x03
line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC8C++0x03
line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC88++0x03
line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
rgroup.long 0xC8C++0x03
line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x12)
group.long 0xC90++0x03
line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC94++0x03
line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC90++0x03
line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
rgroup.long 0xC94++0x03
line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x13)
group.long 0xC98++0x03
line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xC9C++0x03
line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xC98++0x03
line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
rgroup.long 0xC9C++0x03
line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x14)
group.long 0xCA0++0x03
line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCA4++0x03
line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCA0++0x03
line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
rgroup.long 0xCA4++0x03
line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x15)
group.long 0xCA8++0x03
line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCAC++0x03
line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCA8++0x03
line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
rgroup.long 0xCAC++0x03
line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x16)
group.long 0xCB0++0x03
line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCB4++0x03
line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCB0++0x03
line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
rgroup.long 0xCB4++0x03
line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x17)
group.long 0xCB8++0x03
line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCBC++0x03
line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCB8++0x03
line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
rgroup.long 0xCBC++0x03
line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x18)
group.long 0xCC0++0x03
line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCC4++0x03
line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCC0++0x03
line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
rgroup.long 0xCC4++0x03
line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x19)
group.long 0xCC8++0x03
line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCCC++0x03
line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCC8++0x03
line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
rgroup.long 0xCCC++0x03
line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1A)
group.long 0xCD0++0x03
line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCD4++0x03
line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCD0++0x03
line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
rgroup.long 0xCD4++0x03
line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1B)
group.long 0xCD8++0x03
line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCDC++0x03
line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCD8++0x03
line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
rgroup.long 0xCDC++0x03
line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1C)
group.long 0xCE0++0x03
line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCE4++0x03
line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCE0++0x03
line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
rgroup.long 0xCE4++0x03
line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1D)
group.long 0xCE8++0x03
line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCEC++0x03
line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCE8++0x03
line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
rgroup.long 0xCEC++0x03
line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1E)
group.long 0xCF0++0x03
line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCF4++0x03
line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCF0++0x03
line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
rgroup.long 0xCF4++0x03
line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1F)
group.long 0xCF8++0x03
line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
group.long 0xCFC++0x03
line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0" "Level,Edge"
else
rgroup.long 0xCF8++0x03
line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62"
rgroup.long 0xCFC++0x03
line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63"
endif
tree.end
width 12.
tree "Peripheral Interrupt Status Registers"
rgroup.long 0x0D00++0x03
line.long 0x00 "GICD_PPISR,Private Peripheral Interrupt Status Register"
bitfld.long 0x00 15. " PPI3S     ,nIRQ pin status" "No interrupt,Interrupt"
bitfld.long 0x00 14. "  PPI2S     ,Non-secure Physical Timer event status" "No interrupt,Interrupt"
textline "                     "
bitfld.long 0x00 13. " PPI1S     ,Secure Physical Timer event status" "No interrupt,Interrupt"
bitfld.long 0x00 12. "  PPI0S     ,nFIQ pin status" "No interrupt,Interrupt"
textline "                     "
bitfld.long 0x00 11. " PPI4S     ,Virtual Timer event status" "No interrupt,Interrupt"
bitfld.long 0x00 10. "  PPI5S     ,Hypervisor Timer event status" "No interrupt,Interrupt"
textline "                     "
bitfld.long 0x00 9. " PPI6S     ,Virtual Maintenance Status" "No interrupt,Interrupt"
textline "                               "
width 22.
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x01)
rgroup.long 0x0D04++0x03
line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0"
bitfld.long 0x00 31. " IRQS31  ,IRQS Status Bit 31" "Low,High"
bitfld.long 0x00 30. "  IRQS30  ,IRQS Status Bit 30" "Low,High"
bitfld.long 0x00 29. "  IRQS29  ,IRQS Status Bit 29" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS28  ,IRQS Status Bit 28" "Low,High"
bitfld.long 0x00 27. "  IRQS27  ,IRQS Status Bit 27" "Low,High"
bitfld.long 0x00 26. "  IRQS26  ,IRQS Status Bit 26" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS25  ,IRQS Status Bit 25" "Low,High"
bitfld.long 0x00 24. "  IRQS24  ,IRQS Status Bit 24" "Low,High"
bitfld.long 0x00 23. "  IRQS23  ,IRQS Status Bit 23" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS22  ,IRQS Status Bit 22" "Low,High"
bitfld.long 0x00 21. "  IRQS21  ,IRQS Status Bit 21" "Low,High"
bitfld.long 0x00 20. "  IRQS20  ,IRQS Status Bit 20" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS19  ,IRQS Status Bit 19" "Low,High"
bitfld.long 0x00 18. "  IRQS18  ,IRQS Status Bit 18" "Low,High"
bitfld.long 0x00 17. "  IRQS17  ,IRQS Status Bit 17" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS16  ,IRQS Status Bit 16" "Low,High"
bitfld.long 0x00 15. "  IRQS15  ,IRQS Status Bit 15" "Low,High"
bitfld.long 0x00 14. "  IRQS14  ,IRQS Status Bit 14" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS13  ,IRQS Status Bit 13" "Low,High"
bitfld.long 0x00 12. "  IRQS12  ,IRQS Status Bit 12" "Low,High"
bitfld.long 0x00 11. "  IRQS11  ,IRQS Status Bit 11" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS10  ,IRQS Status Bit 10" "Low,High"
bitfld.long 0x00 9. "  IRQS9   ,IRQS Status Bit 9" "Low,High"
bitfld.long 0x00 8. "  IRQS8   ,IRQS Status Bit 8" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS7   ,IRQS Status Bit 7" "Low,High"
bitfld.long 0x00 6. "  IRQS6   ,IRQS Status Bit 6" "Low,High"
bitfld.long 0x00 5. "  IRQS5   ,IRQS Status Bit 5" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS4   ,IRQS Status Bit 4" "Low,High"
bitfld.long 0x00 3. "  IRQS3   ,IRQS Status Bit 3" "Low,High"
bitfld.long 0x00 2. "  IRQS2   ,IRQS Status Bit 2" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS1   ,IRQS Status Bit 1" "Low,High"
bitfld.long 0x00 0. "  IRQS0   ,IRQS Status Bit 0" "Low,High"
else
rgroup.long 0x0D04++0x03
line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 1"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x02)
rgroup.long 0x0D08++0x03
line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
bitfld.long 0x00 31. " IRQS63  ,IRQS Status Bit 63" "Low,High"
bitfld.long 0x00 30. "  IRQS62  ,IRQS Status Bit 62" "Low,High"
bitfld.long 0x00 29. "  IRQS61  ,IRQS Status Bit 61" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS60  ,IRQS Status Bit 60" "Low,High"
bitfld.long 0x00 27. "  IRQS59  ,IRQS Status Bit 59" "Low,High"
bitfld.long 0x00 26. "  IRQS58  ,IRQS Status Bit 58" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS57  ,IRQS Status Bit 57" "Low,High"
bitfld.long 0x00 24. "  IRQS56  ,IRQS Status Bit 56" "Low,High"
bitfld.long 0x00 23. "  IRQS55  ,IRQS Status Bit 55" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS54  ,IRQS Status Bit 54" "Low,High"
bitfld.long 0x00 21. "  IRQS53  ,IRQS Status Bit 53" "Low,High"
bitfld.long 0x00 20. "  IRQS52  ,IRQS Status Bit 52" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS51  ,IRQS Status Bit 51" "Low,High"
bitfld.long 0x00 18. "  IRQS50  ,IRQS Status Bit 50" "Low,High"
bitfld.long 0x00 17. "  IRQS49  ,IRQS Status Bit 49" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS48  ,IRQS Status Bit 48" "Low,High"
bitfld.long 0x00 15. "  IRQS47  ,IRQS Status Bit 47" "Low,High"
bitfld.long 0x00 14. "  IRQS46  ,IRQS Status Bit 46" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS45  ,IRQS Status Bit 45" "Low,High"
bitfld.long 0x00 12. "  IRQS44  ,IRQS Status Bit 44" "Low,High"
bitfld.long 0x00 11. "  IRQS43  ,IRQS Status Bit 43" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS42  ,IRQS Status Bit 42" "Low,High"
bitfld.long 0x00 9. "  IRQS41  ,IRQS Status Bit 41" "Low,High"
bitfld.long 0x00 8. "  IRQS40  ,IRQS Status Bit 40" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS39  ,IRQS Status Bit 39" "Low,High"
bitfld.long 0x00 6. "  IRQS38  ,IRQS Status Bit 38" "Low,High"
bitfld.long 0x00 5. "  IRQS37  ,IRQS Status Bit 37" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS36  ,IRQS Status Bit 36" "Low,High"
bitfld.long 0x00 3. "  IRQS35  ,IRQS Status Bit 35" "Low,High"
bitfld.long 0x00 2. "  IRQS34  ,IRQS Status Bit 34" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS33  ,IRQS Status Bit 33" "Low,High"
bitfld.long 0x00 0. "  IRQS32  ,IRQS Status Bit 32" "Low,High"
else
rgroup.long 0x0D08++0x03
line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x03)
rgroup.long 0x0D0C++0x03
line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
bitfld.long 0x00 31. " IRQS95  ,IRQS Status Bit 95" "Low,High"
bitfld.long 0x00 30. "  IRQS94  ,IRQS Status Bit 94" "Low,High"
bitfld.long 0x00 29. "  IRQS93  ,IRQS Status Bit 93" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS92  ,IRQS Status Bit 92" "Low,High"
bitfld.long 0x00 27. "  IRQS91  ,IRQS Status Bit 91" "Low,High"
bitfld.long 0x00 26. "  IRQS90  ,IRQS Status Bit 90" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS89  ,IRQS Status Bit 89" "Low,High"
bitfld.long 0x00 24. "  IRQS88  ,IRQS Status Bit 88" "Low,High"
bitfld.long 0x00 23. "  IRQS87  ,IRQS Status Bit 87" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS86  ,IRQS Status Bit 86" "Low,High"
bitfld.long 0x00 21. "  IRQS85  ,IRQS Status Bit 85" "Low,High"
bitfld.long 0x00 20. "  IRQS84  ,IRQS Status Bit 84" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS83  ,IRQS Status Bit 83" "Low,High"
bitfld.long 0x00 18. "  IRQS82  ,IRQS Status Bit 82" "Low,High"
bitfld.long 0x00 17. "  IRQS81  ,IRQS Status Bit 81" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS80  ,IRQS Status Bit 80" "Low,High"
bitfld.long 0x00 15. "  IRQS79  ,IRQS Status Bit 79" "Low,High"
bitfld.long 0x00 14. "  IRQS78  ,IRQS Status Bit 78" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS77  ,IRQS Status Bit 77" "Low,High"
bitfld.long 0x00 12. "  IRQS76  ,IRQS Status Bit 76" "Low,High"
bitfld.long 0x00 11. "  IRQS75  ,IRQS Status Bit 75" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS74  ,IRQS Status Bit 74" "Low,High"
bitfld.long 0x00 9. "  IRQS73  ,IRQS Status Bit 73" "Low,High"
bitfld.long 0x00 8. "  IRQS72  ,IRQS Status Bit 72" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS71  ,IRQS Status Bit 71" "Low,High"
bitfld.long 0x00 6. "  IRQS70  ,IRQS Status Bit 70" "Low,High"
bitfld.long 0x00 5. "  IRQS69  ,IRQS Status Bit 69" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS68  ,IRQS Status Bit 68" "Low,High"
bitfld.long 0x00 3. "  IRQS67  ,IRQS Status Bit 67" "Low,High"
bitfld.long 0x00 2. "  IRQS66  ,IRQS Status Bit 66" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS65  ,IRQS Status Bit 65" "Low,High"
bitfld.long 0x00 0. "  IRQS64  ,IRQS Status Bit 64" "Low,High"
else
rgroup.long 0x0D0C++0x03
line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x04)
rgroup.long 0x0D10++0x03
line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
bitfld.long 0x00 31. " IRQS127 ,IRQS Status Bit 127" "Low,High"
bitfld.long 0x00 30. "  IRQS126 ,IRQS Status Bit 126" "Low,High"
bitfld.long 0x00 29. "  IRQS125 ,IRQS Status Bit 125" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS124 ,IRQS Status Bit 124" "Low,High"
bitfld.long 0x00 27. "  IRQS123 ,IRQS Status Bit 123" "Low,High"
bitfld.long 0x00 26. "  IRQS122 ,IRQS Status Bit 122" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS121 ,IRQS Status Bit 121" "Low,High"
bitfld.long 0x00 24. "  IRQS120 ,IRQS Status Bit 120" "Low,High"
bitfld.long 0x00 23. "  IRQS119 ,IRQS Status Bit 119" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS118 ,IRQS Status Bit 118" "Low,High"
bitfld.long 0x00 21. "  IRQS117 ,IRQS Status Bit 117" "Low,High"
bitfld.long 0x00 20. "  IRQS116 ,IRQS Status Bit 116" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS115 ,IRQS Status Bit 115" "Low,High"
bitfld.long 0x00 18. "  IRQS114 ,IRQS Status Bit 114" "Low,High"
bitfld.long 0x00 17. "  IRQS113 ,IRQS Status Bit 113" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS112 ,IRQS Status Bit 112" "Low,High"
bitfld.long 0x00 15. "  IRQS111 ,IRQS Status Bit 111" "Low,High"
bitfld.long 0x00 14. "  IRQS110 ,IRQS Status Bit 110" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS109 ,IRQS Status Bit 109" "Low,High"
bitfld.long 0x00 12. "  IRQS108 ,IRQS Status Bit 108" "Low,High"
bitfld.long 0x00 11. "  IRQS107 ,IRQS Status Bit 107" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS106 ,IRQS Status Bit 106" "Low,High"
bitfld.long 0x00 9. "  IRQS105 ,IRQS Status Bit 105" "Low,High"
bitfld.long 0x00 8. "  IRQS104 ,IRQS Status Bit 104" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS103 ,IRQS Status Bit 103" "Low,High"
bitfld.long 0x00 6. "  IRQS102 ,IRQS Status Bit 102" "Low,High"
bitfld.long 0x00 5. "  IRQS101 ,IRQS Status Bit 101" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS100 ,IRQS Status Bit 100" "Low,High"
bitfld.long 0x00 3. "  IRQS99  ,IRQS Status Bit 99" "Low,High"
bitfld.long 0x00 2. "  IRQS98  ,IRQS Status Bit 98" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS97  ,IRQS Status Bit 97" "Low,High"
bitfld.long 0x00 0. "  IRQS96  ,IRQS Status Bit 96" "Low,High"
else
rgroup.long 0x0D10++0x03
line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x05)
rgroup.long 0x0D14++0x03
line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
bitfld.long 0x00 31. " IRQS159 ,IRQS Status Bit 159" "Low,High"
bitfld.long 0x00 30. "  IRQS158 ,IRQS Status Bit 158" "Low,High"
bitfld.long 0x00 29. "  IRQS157 ,IRQS Status Bit 157" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS156 ,IRQS Status Bit 156" "Low,High"
bitfld.long 0x00 27. "  IRQS155 ,IRQS Status Bit 155" "Low,High"
bitfld.long 0x00 26. "  IRQS154 ,IRQS Status Bit 154" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS153 ,IRQS Status Bit 153" "Low,High"
bitfld.long 0x00 24. "  IRQS152 ,IRQS Status Bit 152" "Low,High"
bitfld.long 0x00 23. "  IRQS151 ,IRQS Status Bit 151" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS150 ,IRQS Status Bit 150" "Low,High"
bitfld.long 0x00 21. "  IRQS149 ,IRQS Status Bit 149" "Low,High"
bitfld.long 0x00 20. "  IRQS148 ,IRQS Status Bit 148" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS147 ,IRQS Status Bit 147" "Low,High"
bitfld.long 0x00 18. "  IRQS146 ,IRQS Status Bit 146" "Low,High"
bitfld.long 0x00 17. "  IRQS145 ,IRQS Status Bit 145" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS144 ,IRQS Status Bit 144" "Low,High"
bitfld.long 0x00 15. "  IRQS143 ,IRQS Status Bit 143" "Low,High"
bitfld.long 0x00 14. "  IRQS142 ,IRQS Status Bit 142" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS141 ,IRQS Status Bit 141" "Low,High"
bitfld.long 0x00 12. "  IRQS140 ,IRQS Status Bit 140" "Low,High"
bitfld.long 0x00 11. "  IRQS139 ,IRQS Status Bit 139" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS138 ,IRQS Status Bit 138" "Low,High"
bitfld.long 0x00 9. "  IRQS137 ,IRQS Status Bit 137" "Low,High"
bitfld.long 0x00 8. "  IRQS136 ,IRQS Status Bit 136" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS135 ,IRQS Status Bit 135" "Low,High"
bitfld.long 0x00 6. "  IRQS134 ,IRQS Status Bit 134" "Low,High"
bitfld.long 0x00 5. "  IRQS133 ,IRQS Status Bit 133" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS132 ,IRQS Status Bit 132" "Low,High"
bitfld.long 0x00 3. "  IRQS131 ,IRQS Status Bit 131" "Low,High"
bitfld.long 0x00 2. "  IRQS130 ,IRQS Status Bit 130" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS129 ,IRQS Status Bit 129" "Low,High"
bitfld.long 0x00 0. "  IRQS128 ,IRQS Status Bit 128" "Low,High"
else
rgroup.long 0x0D14++0x03
line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x06)
rgroup.long 0x0D18++0x03
line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
bitfld.long 0x00 31. " IRQS191 ,IRQS Status Bit 191" "Low,High"
bitfld.long 0x00 30. "  IRQS190 ,IRQS Status Bit 190" "Low,High"
bitfld.long 0x00 29. "  IRQS189 ,IRQS Status Bit 189" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS188 ,IRQS Status Bit 188" "Low,High"
bitfld.long 0x00 27. "  IRQS187 ,IRQS Status Bit 187" "Low,High"
bitfld.long 0x00 26. "  IRQS186 ,IRQS Status Bit 186" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS185 ,IRQS Status Bit 185" "Low,High"
bitfld.long 0x00 24. "  IRQS184 ,IRQS Status Bit 184" "Low,High"
bitfld.long 0x00 23. "  IRQS183 ,IRQS Status Bit 183" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS182 ,IRQS Status Bit 182" "Low,High"
bitfld.long 0x00 21. "  IRQS181 ,IRQS Status Bit 181" "Low,High"
bitfld.long 0x00 20. "  IRQS180 ,IRQS Status Bit 180" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS179 ,IRQS Status Bit 179" "Low,High"
bitfld.long 0x00 18. "  IRQS178 ,IRQS Status Bit 178" "Low,High"
bitfld.long 0x00 17. "  IRQS177 ,IRQS Status Bit 177" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS176 ,IRQS Status Bit 176" "Low,High"
bitfld.long 0x00 15. "  IRQS175 ,IRQS Status Bit 175" "Low,High"
bitfld.long 0x00 14. "  IRQS174 ,IRQS Status Bit 174" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS173 ,IRQS Status Bit 173" "Low,High"
bitfld.long 0x00 12. "  IRQS172 ,IRQS Status Bit 172" "Low,High"
bitfld.long 0x00 11. "  IRQS171 ,IRQS Status Bit 171" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS170 ,IRQS Status Bit 170" "Low,High"
bitfld.long 0x00 9. "  IRQS169 ,IRQS Status Bit 169" "Low,High"
bitfld.long 0x00 8. "  IRQS168 ,IRQS Status Bit 168" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS167 ,IRQS Status Bit 167" "Low,High"
bitfld.long 0x00 6. "  IRQS166 ,IRQS Status Bit 166" "Low,High"
bitfld.long 0x00 5. "  IRQS165 ,IRQS Status Bit 165" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS164 ,IRQS Status Bit 164" "Low,High"
bitfld.long 0x00 3. "  IRQS163 ,IRQS Status Bit 163" "Low,High"
bitfld.long 0x00 2. "  IRQS162 ,IRQS Status Bit 162" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS161 ,IRQS Status Bit 161" "Low,High"
bitfld.long 0x00 0. "  IRQS160 ,IRQS Status Bit 160" "Low,High"
else
rgroup.long 0x0D18++0x03
line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x07)
rgroup.long 0x0D1C++0x03
line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
bitfld.long 0x00 31. " IRQS223 ,IRQS Status Bit 223" "Low,High"
bitfld.long 0x00 30. "  IRQS222 ,IRQS Status Bit 222" "Low,High"
bitfld.long 0x00 29. "  IRQS221 ,IRQS Status Bit 221" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS220 ,IRQS Status Bit 220" "Low,High"
bitfld.long 0x00 27. "  IRQS219 ,IRQS Status Bit 219" "Low,High"
bitfld.long 0x00 26. "  IRQS218 ,IRQS Status Bit 218" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS217 ,IRQS Status Bit 217" "Low,High"
bitfld.long 0x00 24. "  IRQS216 ,IRQS Status Bit 216" "Low,High"
bitfld.long 0x00 23. "  IRQS215 ,IRQS Status Bit 215" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS214 ,IRQS Status Bit 214" "Low,High"
bitfld.long 0x00 21. "  IRQS213 ,IRQS Status Bit 213" "Low,High"
bitfld.long 0x00 20. "  IRQS212 ,IRQS Status Bit 212" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS211 ,IRQS Status Bit 211" "Low,High"
bitfld.long 0x00 18. "  IRQS210 ,IRQS Status Bit 210" "Low,High"
bitfld.long 0x00 17. "  IRQS209 ,IRQS Status Bit 209" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS208 ,IRQS Status Bit 208" "Low,High"
bitfld.long 0x00 15. "  IRQS207 ,IRQS Status Bit 207" "Low,High"
bitfld.long 0x00 14. "  IRQS206 ,IRQS Status Bit 206" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS205 ,IRQS Status Bit 205" "Low,High"
bitfld.long 0x00 12. "  IRQS204 ,IRQS Status Bit 204" "Low,High"
bitfld.long 0x00 11. "  IRQS203 ,IRQS Status Bit 203" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS202 ,IRQS Status Bit 202" "Low,High"
bitfld.long 0x00 9. "  IRQS201 ,IRQS Status Bit 201" "Low,High"
bitfld.long 0x00 8. "  IRQS200 ,IRQS Status Bit 200" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS199 ,IRQS Status Bit 199" "Low,High"
bitfld.long 0x00 6. "  IRQS198 ,IRQS Status Bit 198" "Low,High"
bitfld.long 0x00 5. "  IRQS197 ,IRQS Status Bit 197" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS196 ,IRQS Status Bit 196" "Low,High"
bitfld.long 0x00 3. "  IRQS195 ,IRQS Status Bit 195" "Low,High"
bitfld.long 0x00 2. "  IRQS194 ,IRQS Status Bit 194" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS193 ,IRQS Status Bit 193" "Low,High"
bitfld.long 0x00 0. "  IRQS192 ,IRQS Status Bit 192" "Low,High"
else
rgroup.long 0x0D1C++0x03
line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x08)
rgroup.long 0x0D20++0x03
line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
bitfld.long 0x00 31. " IRQS255 ,IRQS Status Bit 255" "Low,High"
bitfld.long 0x00 30. "  IRQS254 ,IRQS Status Bit 254" "Low,High"
bitfld.long 0x00 29. "  IRQS253 ,IRQS Status Bit 253" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS252 ,IRQS Status Bit 252" "Low,High"
bitfld.long 0x00 27. "  IRQS251 ,IRQS Status Bit 251" "Low,High"
bitfld.long 0x00 26. "  IRQS250 ,IRQS Status Bit 250" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS249 ,IRQS Status Bit 249" "Low,High"
bitfld.long 0x00 24. "  IRQS248 ,IRQS Status Bit 248" "Low,High"
bitfld.long 0x00 23. "  IRQS247 ,IRQS Status Bit 247" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS246 ,IRQS Status Bit 246" "Low,High"
bitfld.long 0x00 21. "  IRQS245 ,IRQS Status Bit 245" "Low,High"
bitfld.long 0x00 20. "  IRQS244 ,IRQS Status Bit 244" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS243 ,IRQS Status Bit 243" "Low,High"
bitfld.long 0x00 18. "  IRQS242 ,IRQS Status Bit 242" "Low,High"
bitfld.long 0x00 17. "  IRQS241 ,IRQS Status Bit 241" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS240 ,IRQS Status Bit 240" "Low,High"
bitfld.long 0x00 15. "  IRQS239 ,IRQS Status Bit 239" "Low,High"
bitfld.long 0x00 14. "  IRQS238 ,IRQS Status Bit 238" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS237 ,IRQS Status Bit 237" "Low,High"
bitfld.long 0x00 12. "  IRQS236 ,IRQS Status Bit 236" "Low,High"
bitfld.long 0x00 11. "  IRQS235 ,IRQS Status Bit 235" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS234 ,IRQS Status Bit 234" "Low,High"
bitfld.long 0x00 9. "  IRQS233 ,IRQS Status Bit 233" "Low,High"
bitfld.long 0x00 8. "  IRQS232 ,IRQS Status Bit 232" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS231 ,IRQS Status Bit 231" "Low,High"
bitfld.long 0x00 6. "  IRQS230 ,IRQS Status Bit 230" "Low,High"
bitfld.long 0x00 5. "  IRQS229 ,IRQS Status Bit 229" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS228 ,IRQS Status Bit 228" "Low,High"
bitfld.long 0x00 3. "  IRQS227 ,IRQS Status Bit 227" "Low,High"
bitfld.long 0x00 2. "  IRQS226 ,IRQS Status Bit 226" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS225 ,IRQS Status Bit 225" "Low,High"
bitfld.long 0x00 0. "  IRQS224 ,IRQS Status Bit 224" "Low,High"
else
rgroup.long 0x0D20++0x03
line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x09)
rgroup.long 0x0D24++0x03
line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
bitfld.long 0x00 31. " IRQS287 ,IRQS Status Bit 287" "Low,High"
bitfld.long 0x00 30. "  IRQS286 ,IRQS Status Bit 286" "Low,High"
bitfld.long 0x00 29. "  IRQS285 ,IRQS Status Bit 285" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS284 ,IRQS Status Bit 284" "Low,High"
bitfld.long 0x00 27. "  IRQS283 ,IRQS Status Bit 283" "Low,High"
bitfld.long 0x00 26. "  IRQS282 ,IRQS Status Bit 282" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS281 ,IRQS Status Bit 281" "Low,High"
bitfld.long 0x00 24. "  IRQS280 ,IRQS Status Bit 280" "Low,High"
bitfld.long 0x00 23. "  IRQS279 ,IRQS Status Bit 279" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS278 ,IRQS Status Bit 278" "Low,High"
bitfld.long 0x00 21. "  IRQS277 ,IRQS Status Bit 277" "Low,High"
bitfld.long 0x00 20. "  IRQS276 ,IRQS Status Bit 276" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS275 ,IRQS Status Bit 275" "Low,High"
bitfld.long 0x00 18. "  IRQS274 ,IRQS Status Bit 274" "Low,High"
bitfld.long 0x00 17. "  IRQS273 ,IRQS Status Bit 273" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS272 ,IRQS Status Bit 272" "Low,High"
bitfld.long 0x00 15. "  IRQS271 ,IRQS Status Bit 271" "Low,High"
bitfld.long 0x00 14. "  IRQS270 ,IRQS Status Bit 270" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS269 ,IRQS Status Bit 269" "Low,High"
bitfld.long 0x00 12. "  IRQS268 ,IRQS Status Bit 268" "Low,High"
bitfld.long 0x00 11. "  IRQS267 ,IRQS Status Bit 267" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS266 ,IRQS Status Bit 266" "Low,High"
bitfld.long 0x00 9. "  IRQS265 ,IRQS Status Bit 265" "Low,High"
bitfld.long 0x00 8. "  IRQS264 ,IRQS Status Bit 264" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS263 ,IRQS Status Bit 263" "Low,High"
bitfld.long 0x00 6. "  IRQS262 ,IRQS Status Bit 262" "Low,High"
bitfld.long 0x00 5. "  IRQS261 ,IRQS Status Bit 261" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS260 ,IRQS Status Bit 260" "Low,High"
bitfld.long 0x00 3. "  IRQS259 ,IRQS Status Bit 259" "Low,High"
bitfld.long 0x00 2. "  IRQS258 ,IRQS Status Bit 258" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS257 ,IRQS Status Bit 257" "Low,High"
bitfld.long 0x00 0. "  IRQS256 ,IRQS Status Bit 256" "Low,High"
else
rgroup.long 0x0D24++0x03
line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0A)
rgroup.long 0x0D28++0x03
line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
bitfld.long 0x00 31. " IRQS319 ,IRQS Status Bit 319" "Low,High"
bitfld.long 0x00 30. "  IRQS318 ,IRQS Status Bit 318" "Low,High"
bitfld.long 0x00 29. "  IRQS317 ,IRQS Status Bit 317" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS316 ,IRQS Status Bit 316" "Low,High"
bitfld.long 0x00 27. "  IRQS315 ,IRQS Status Bit 315" "Low,High"
bitfld.long 0x00 26. "  IRQS314 ,IRQS Status Bit 314" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS313 ,IRQS Status Bit 313" "Low,High"
bitfld.long 0x00 24. "  IRQS312 ,IRQS Status Bit 312" "Low,High"
bitfld.long 0x00 23. "  IRQS311 ,IRQS Status Bit 311" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS310 ,IRQS Status Bit 310" "Low,High"
bitfld.long 0x00 21. "  IRQS309 ,IRQS Status Bit 309" "Low,High"
bitfld.long 0x00 20. "  IRQS308 ,IRQS Status Bit 308" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS307 ,IRQS Status Bit 307" "Low,High"
bitfld.long 0x00 18. "  IRQS306 ,IRQS Status Bit 306" "Low,High"
bitfld.long 0x00 17. "  IRQS305 ,IRQS Status Bit 305" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS304 ,IRQS Status Bit 304" "Low,High"
bitfld.long 0x00 15. "  IRQS303 ,IRQS Status Bit 303" "Low,High"
bitfld.long 0x00 14. "  IRQS302 ,IRQS Status Bit 302" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS301 ,IRQS Status Bit 301" "Low,High"
bitfld.long 0x00 12. "  IRQS300 ,IRQS Status Bit 300" "Low,High"
bitfld.long 0x00 11. "  IRQS299 ,IRQS Status Bit 299" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS298 ,IRQS Status Bit 298" "Low,High"
bitfld.long 0x00 9. "  IRQS297 ,IRQS Status Bit 297" "Low,High"
bitfld.long 0x00 8. "  IRQS296 ,IRQS Status Bit 296" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS295 ,IRQS Status Bit 295" "Low,High"
bitfld.long 0x00 6. "  IRQS294 ,IRQS Status Bit 294" "Low,High"
bitfld.long 0x00 5. "  IRQS293 ,IRQS Status Bit 293" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS292 ,IRQS Status Bit 292" "Low,High"
bitfld.long 0x00 3. "  IRQS291 ,IRQS Status Bit 291" "Low,High"
bitfld.long 0x00 2. "  IRQS290 ,IRQS Status Bit 290" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS289 ,IRQS Status Bit 289" "Low,High"
bitfld.long 0x00 0. "  IRQS288 ,IRQS Status Bit 288" "Low,High"
else
rgroup.long 0x0D28++0x03
line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0B)
rgroup.long 0x0D2C++0x03
line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
bitfld.long 0x00 31. " IRQS351 ,IRQS Status Bit 351" "Low,High"
bitfld.long 0x00 30. "  IRQS350 ,IRQS Status Bit 350" "Low,High"
bitfld.long 0x00 29. "  IRQS349 ,IRQS Status Bit 349" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS348 ,IRQS Status Bit 348" "Low,High"
bitfld.long 0x00 27. "  IRQS347 ,IRQS Status Bit 347" "Low,High"
bitfld.long 0x00 26. "  IRQS346 ,IRQS Status Bit 346" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS345 ,IRQS Status Bit 345" "Low,High"
bitfld.long 0x00 24. "  IRQS344 ,IRQS Status Bit 344" "Low,High"
bitfld.long 0x00 23. "  IRQS343 ,IRQS Status Bit 343" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS342 ,IRQS Status Bit 342" "Low,High"
bitfld.long 0x00 21. "  IRQS341 ,IRQS Status Bit 341" "Low,High"
bitfld.long 0x00 20. "  IRQS340 ,IRQS Status Bit 340" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS339 ,IRQS Status Bit 339" "Low,High"
bitfld.long 0x00 18. "  IRQS338 ,IRQS Status Bit 338" "Low,High"
bitfld.long 0x00 17. "  IRQS337 ,IRQS Status Bit 337" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS336 ,IRQS Status Bit 336" "Low,High"
bitfld.long 0x00 15. "  IRQS335 ,IRQS Status Bit 335" "Low,High"
bitfld.long 0x00 14. "  IRQS334 ,IRQS Status Bit 334" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS333 ,IRQS Status Bit 333" "Low,High"
bitfld.long 0x00 12. "  IRQS332 ,IRQS Status Bit 332" "Low,High"
bitfld.long 0x00 11. "  IRQS331 ,IRQS Status Bit 331" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS330 ,IRQS Status Bit 330" "Low,High"
bitfld.long 0x00 9. "  IRQS329 ,IRQS Status Bit 329" "Low,High"
bitfld.long 0x00 8. "  IRQS328 ,IRQS Status Bit 328" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS327 ,IRQS Status Bit 327" "Low,High"
bitfld.long 0x00 6. "  IRQS326 ,IRQS Status Bit 326" "Low,High"
bitfld.long 0x00 5. "  IRQS325 ,IRQS Status Bit 325" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS324 ,IRQS Status Bit 324" "Low,High"
bitfld.long 0x00 3. "  IRQS323 ,IRQS Status Bit 323" "Low,High"
bitfld.long 0x00 2. "  IRQS322 ,IRQS Status Bit 322" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS321 ,IRQS Status Bit 321" "Low,High"
bitfld.long 0x00 0. "  IRQS320 ,IRQS Status Bit 320" "Low,High"
else
rgroup.long 0x0D2C++0x03
line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0C)
rgroup.long 0x0D30++0x03
line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
bitfld.long 0x00 31. " IRQS383 ,IRQS Status Bit 383" "Low,High"
bitfld.long 0x00 30. "  IRQS382 ,IRQS Status Bit 382" "Low,High"
bitfld.long 0x00 29. "  IRQS381 ,IRQS Status Bit 381" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS380 ,IRQS Status Bit 380" "Low,High"
bitfld.long 0x00 27. "  IRQS379 ,IRQS Status Bit 379" "Low,High"
bitfld.long 0x00 26. "  IRQS378 ,IRQS Status Bit 378" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS377 ,IRQS Status Bit 377" "Low,High"
bitfld.long 0x00 24. "  IRQS376 ,IRQS Status Bit 376" "Low,High"
bitfld.long 0x00 23. "  IRQS375 ,IRQS Status Bit 375" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS374 ,IRQS Status Bit 374" "Low,High"
bitfld.long 0x00 21. "  IRQS373 ,IRQS Status Bit 373" "Low,High"
bitfld.long 0x00 20. "  IRQS372 ,IRQS Status Bit 372" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS371 ,IRQS Status Bit 371" "Low,High"
bitfld.long 0x00 18. "  IRQS370 ,IRQS Status Bit 370" "Low,High"
bitfld.long 0x00 17. "  IRQS369 ,IRQS Status Bit 369" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS368 ,IRQS Status Bit 368" "Low,High"
bitfld.long 0x00 15. "  IRQS367 ,IRQS Status Bit 367" "Low,High"
bitfld.long 0x00 14. "  IRQS366 ,IRQS Status Bit 366" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS365 ,IRQS Status Bit 365" "Low,High"
bitfld.long 0x00 12. "  IRQS364 ,IRQS Status Bit 364" "Low,High"
bitfld.long 0x00 11. "  IRQS363 ,IRQS Status Bit 363" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS362 ,IRQS Status Bit 362" "Low,High"
bitfld.long 0x00 9. "  IRQS361 ,IRQS Status Bit 361" "Low,High"
bitfld.long 0x00 8. "  IRQS360 ,IRQS Status Bit 360" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS359 ,IRQS Status Bit 359" "Low,High"
bitfld.long 0x00 6. "  IRQS358 ,IRQS Status Bit 358" "Low,High"
bitfld.long 0x00 5. "  IRQS357 ,IRQS Status Bit 357" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS356 ,IRQS Status Bit 356" "Low,High"
bitfld.long 0x00 3. "  IRQS355 ,IRQS Status Bit 355" "Low,High"
bitfld.long 0x00 2. "  IRQS354 ,IRQS Status Bit 354" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS353 ,IRQS Status Bit 353" "Low,High"
bitfld.long 0x00 0. "  IRQS352 ,IRQS Status Bit 352" "Low,High"
else
rgroup.long 0x0D30++0x03
line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0D)
rgroup.long 0x0D34++0x03
line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
bitfld.long 0x00 31. " IRQS415 ,IRQS Status Bit 415" "Low,High"
bitfld.long 0x00 30. "  IRQS414 ,IRQS Status Bit 414" "Low,High"
bitfld.long 0x00 29. "  IRQS413 ,IRQS Status Bit 413" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS412 ,IRQS Status Bit 412" "Low,High"
bitfld.long 0x00 27. "  IRQS411 ,IRQS Status Bit 411" "Low,High"
bitfld.long 0x00 26. "  IRQS410 ,IRQS Status Bit 410" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS409 ,IRQS Status Bit 409" "Low,High"
bitfld.long 0x00 24. "  IRQS408 ,IRQS Status Bit 408" "Low,High"
bitfld.long 0x00 23. "  IRQS407 ,IRQS Status Bit 407" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS406 ,IRQS Status Bit 406" "Low,High"
bitfld.long 0x00 21. "  IRQS405 ,IRQS Status Bit 405" "Low,High"
bitfld.long 0x00 20. "  IRQS404 ,IRQS Status Bit 404" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS403 ,IRQS Status Bit 403" "Low,High"
bitfld.long 0x00 18. "  IRQS402 ,IRQS Status Bit 402" "Low,High"
bitfld.long 0x00 17. "  IRQS401 ,IRQS Status Bit 401" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS400 ,IRQS Status Bit 400" "Low,High"
bitfld.long 0x00 15. "  IRQS399 ,IRQS Status Bit 399" "Low,High"
bitfld.long 0x00 14. "  IRQS398 ,IRQS Status Bit 398" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS397 ,IRQS Status Bit 397" "Low,High"
bitfld.long 0x00 12. "  IRQS396 ,IRQS Status Bit 396" "Low,High"
bitfld.long 0x00 11. "  IRQS395 ,IRQS Status Bit 395" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS394 ,IRQS Status Bit 394" "Low,High"
bitfld.long 0x00 9. "  IRQS393 ,IRQS Status Bit 393" "Low,High"
bitfld.long 0x00 8. "  IRQS392 ,IRQS Status Bit 392" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS391 ,IRQS Status Bit 391" "Low,High"
bitfld.long 0x00 6. "  IRQS390 ,IRQS Status Bit 390" "Low,High"
bitfld.long 0x00 5. "  IRQS389 ,IRQS Status Bit 389" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS388 ,IRQS Status Bit 388" "Low,High"
bitfld.long 0x00 3. "  IRQS387 ,IRQS Status Bit 387" "Low,High"
bitfld.long 0x00 2. "  IRQS386 ,IRQS Status Bit 386" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS385 ,IRQS Status Bit 385" "Low,High"
bitfld.long 0x00 0. "  IRQS384 ,IRQS Status Bit 384" "Low,High"
else
rgroup.long 0x0D34++0x03
line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0E)
rgroup.long 0x0D38++0x03
line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
bitfld.long 0x00 31. " IRQS447 ,IRQS Status Bit 447" "Low,High"
bitfld.long 0x00 30. "  IRQS446 ,IRQS Status Bit 446" "Low,High"
bitfld.long 0x00 29. "  IRQS445 ,IRQS Status Bit 445" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS444 ,IRQS Status Bit 444" "Low,High"
bitfld.long 0x00 27. "  IRQS443 ,IRQS Status Bit 443" "Low,High"
bitfld.long 0x00 26. "  IRQS442 ,IRQS Status Bit 442" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS441 ,IRQS Status Bit 441" "Low,High"
bitfld.long 0x00 24. "  IRQS440 ,IRQS Status Bit 440" "Low,High"
bitfld.long 0x00 23. "  IRQS439 ,IRQS Status Bit 439" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS438 ,IRQS Status Bit 438" "Low,High"
bitfld.long 0x00 21. "  IRQS437 ,IRQS Status Bit 437" "Low,High"
bitfld.long 0x00 20. "  IRQS436 ,IRQS Status Bit 436" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS435 ,IRQS Status Bit 435" "Low,High"
bitfld.long 0x00 18. "  IRQS434 ,IRQS Status Bit 434" "Low,High"
bitfld.long 0x00 17. "  IRQS433 ,IRQS Status Bit 433" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS432 ,IRQS Status Bit 432" "Low,High"
bitfld.long 0x00 15. "  IRQS431 ,IRQS Status Bit 431" "Low,High"
bitfld.long 0x00 14. "  IRQS430 ,IRQS Status Bit 430" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS429 ,IRQS Status Bit 429" "Low,High"
bitfld.long 0x00 12. "  IRQS428 ,IRQS Status Bit 428" "Low,High"
bitfld.long 0x00 11. "  IRQS427 ,IRQS Status Bit 427" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS426 ,IRQS Status Bit 426" "Low,High"
bitfld.long 0x00 9. "  IRQS425 ,IRQS Status Bit 425" "Low,High"
bitfld.long 0x00 8. "  IRQS424 ,IRQS Status Bit 424" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS423 ,IRQS Status Bit 423" "Low,High"
bitfld.long 0x00 6. "  IRQS422 ,IRQS Status Bit 422" "Low,High"
bitfld.long 0x00 5. "  IRQS421 ,IRQS Status Bit 421" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS420 ,IRQS Status Bit 420" "Low,High"
bitfld.long 0x00 3. "  IRQS419 ,IRQS Status Bit 419" "Low,High"
bitfld.long 0x00 2. "  IRQS418 ,IRQS Status Bit 418" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS417 ,IRQS Status Bit 417" "Low,High"
bitfld.long 0x00 0. "  IRQS416 ,IRQS Status Bit 416" "Low,High"
else
rgroup.long 0x0D38++0x03
line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x0F)
rgroup.long 0x0D3C++0x03
line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
bitfld.long 0x00 31. " IRQS479 ,IRQS Status Bit 479" "Low,High"
bitfld.long 0x00 30. "  IRQS478 ,IRQS Status Bit 478" "Low,High"
bitfld.long 0x00 29. "  IRQS477 ,IRQS Status Bit 477" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS476 ,IRQS Status Bit 476" "Low,High"
bitfld.long 0x00 27. "  IRQS475 ,IRQS Status Bit 475" "Low,High"
bitfld.long 0x00 26. "  IRQS474 ,IRQS Status Bit 474" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS473 ,IRQS Status Bit 473" "Low,High"
bitfld.long 0x00 24. "  IRQS472 ,IRQS Status Bit 472" "Low,High"
bitfld.long 0x00 23. "  IRQS471 ,IRQS Status Bit 471" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS470 ,IRQS Status Bit 470" "Low,High"
bitfld.long 0x00 21. "  IRQS469 ,IRQS Status Bit 469" "Low,High"
bitfld.long 0x00 20. "  IRQS468 ,IRQS Status Bit 468" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS467 ,IRQS Status Bit 467" "Low,High"
bitfld.long 0x00 18. "  IRQS466 ,IRQS Status Bit 466" "Low,High"
bitfld.long 0x00 17. "  IRQS465 ,IRQS Status Bit 465" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS464 ,IRQS Status Bit 464" "Low,High"
bitfld.long 0x00 15. "  IRQS463 ,IRQS Status Bit 463" "Low,High"
bitfld.long 0x00 14. "  IRQS462 ,IRQS Status Bit 462" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS461 ,IRQS Status Bit 461" "Low,High"
bitfld.long 0x00 12. "  IRQS460 ,IRQS Status Bit 460" "Low,High"
bitfld.long 0x00 11. "  IRQS459 ,IRQS Status Bit 459" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS458 ,IRQS Status Bit 458" "Low,High"
bitfld.long 0x00 9. "  IRQS457 ,IRQS Status Bit 457" "Low,High"
bitfld.long 0x00 8. "  IRQS456 ,IRQS Status Bit 456" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS455 ,IRQS Status Bit 455" "Low,High"
bitfld.long 0x00 6. "  IRQS454 ,IRQS Status Bit 454" "Low,High"
bitfld.long 0x00 5. "  IRQS453 ,IRQS Status Bit 453" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS452 ,IRQS Status Bit 452" "Low,High"
bitfld.long 0x00 3. "  IRQS451 ,IRQS Status Bit 451" "Low,High"
bitfld.long 0x00 2. "  IRQS450 ,IRQS Status Bit 450" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS449 ,IRQS Status Bit 449" "Low,High"
bitfld.long 0x00 0. "  IRQS448 ,IRQS Status Bit 448" "Low,High"
else
rgroup.long 0x0D3C++0x03
line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x10)
rgroup.long 0x0D40++0x03
line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
bitfld.long 0x00 31. " IRQS511 ,IRQS Status Bit 511" "Low,High"
bitfld.long 0x00 30. "  IRQS510 ,IRQS Status Bit 510" "Low,High"
bitfld.long 0x00 29. "  IRQS509 ,IRQS Status Bit 509" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS508 ,IRQS Status Bit 508" "Low,High"
bitfld.long 0x00 27. "  IRQS507 ,IRQS Status Bit 507" "Low,High"
bitfld.long 0x00 26. "  IRQS506 ,IRQS Status Bit 506" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS505 ,IRQS Status Bit 505" "Low,High"
bitfld.long 0x00 24. "  IRQS504 ,IRQS Status Bit 504" "Low,High"
bitfld.long 0x00 23. "  IRQS503 ,IRQS Status Bit 503" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS502 ,IRQS Status Bit 502" "Low,High"
bitfld.long 0x00 21. "  IRQS501 ,IRQS Status Bit 501" "Low,High"
bitfld.long 0x00 20. "  IRQS500 ,IRQS Status Bit 500" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS499 ,IRQS Status Bit 499" "Low,High"
bitfld.long 0x00 18. "  IRQS498 ,IRQS Status Bit 498" "Low,High"
bitfld.long 0x00 17. "  IRQS497 ,IRQS Status Bit 497" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS496 ,IRQS Status Bit 496" "Low,High"
bitfld.long 0x00 15. "  IRQS495 ,IRQS Status Bit 495" "Low,High"
bitfld.long 0x00 14. "  IRQS494 ,IRQS Status Bit 494" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS493 ,IRQS Status Bit 493" "Low,High"
bitfld.long 0x00 12. "  IRQS492 ,IRQS Status Bit 492" "Low,High"
bitfld.long 0x00 11. "  IRQS491 ,IRQS Status Bit 491" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS490 ,IRQS Status Bit 490" "Low,High"
bitfld.long 0x00 9. "  IRQS489 ,IRQS Status Bit 489" "Low,High"
bitfld.long 0x00 8. "  IRQS488 ,IRQS Status Bit 488" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS487 ,IRQS Status Bit 487" "Low,High"
bitfld.long 0x00 6. "  IRQS486 ,IRQS Status Bit 486" "Low,High"
bitfld.long 0x00 5. "  IRQS485 ,IRQS Status Bit 485" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS484 ,IRQS Status Bit 484" "Low,High"
bitfld.long 0x00 3. "  IRQS483 ,IRQS Status Bit 483" "Low,High"
bitfld.long 0x00 2. "  IRQS482 ,IRQS Status Bit 482" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS481 ,IRQS Status Bit 481" "Low,High"
bitfld.long 0x00 0. "  IRQS480 ,IRQS Status Bit 480" "Low,High"
else
rgroup.long 0x0D40++0x03
line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x11)
rgroup.long 0x0D44++0x03
line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
bitfld.long 0x00 31. " IRQS543 ,IRQS Status Bit 543" "Low,High"
bitfld.long 0x00 30. "  IRQS542 ,IRQS Status Bit 542" "Low,High"
bitfld.long 0x00 29. "  IRQS541 ,IRQS Status Bit 541" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS540 ,IRQS Status Bit 540" "Low,High"
bitfld.long 0x00 27. "  IRQS539 ,IRQS Status Bit 539" "Low,High"
bitfld.long 0x00 26. "  IRQS538 ,IRQS Status Bit 538" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS537 ,IRQS Status Bit 537" "Low,High"
bitfld.long 0x00 24. "  IRQS536 ,IRQS Status Bit 536" "Low,High"
bitfld.long 0x00 23. "  IRQS535 ,IRQS Status Bit 535" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS534 ,IRQS Status Bit 534" "Low,High"
bitfld.long 0x00 21. "  IRQS533 ,IRQS Status Bit 533" "Low,High"
bitfld.long 0x00 20. "  IRQS532 ,IRQS Status Bit 532" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS531 ,IRQS Status Bit 531" "Low,High"
bitfld.long 0x00 18. "  IRQS530 ,IRQS Status Bit 530" "Low,High"
bitfld.long 0x00 17. "  IRQS529 ,IRQS Status Bit 529" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS528 ,IRQS Status Bit 528" "Low,High"
bitfld.long 0x00 15. "  IRQS527 ,IRQS Status Bit 527" "Low,High"
bitfld.long 0x00 14. "  IRQS526 ,IRQS Status Bit 526" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS525 ,IRQS Status Bit 525" "Low,High"
bitfld.long 0x00 12. "  IRQS524 ,IRQS Status Bit 524" "Low,High"
bitfld.long 0x00 11. "  IRQS523 ,IRQS Status Bit 523" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS522 ,IRQS Status Bit 522" "Low,High"
bitfld.long 0x00 9. "  IRQS521 ,IRQS Status Bit 521" "Low,High"
bitfld.long 0x00 8. "  IRQS520 ,IRQS Status Bit 520" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS519 ,IRQS Status Bit 519" "Low,High"
bitfld.long 0x00 6. "  IRQS518 ,IRQS Status Bit 518" "Low,High"
bitfld.long 0x00 5. "  IRQS517 ,IRQS Status Bit 517" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS516 ,IRQS Status Bit 516" "Low,High"
bitfld.long 0x00 3. "  IRQS515 ,IRQS Status Bit 515" "Low,High"
bitfld.long 0x00 2. "  IRQS514 ,IRQS Status Bit 514" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS513 ,IRQS Status Bit 513" "Low,High"
bitfld.long 0x00 0. "  IRQS512 ,IRQS Status Bit 512" "Low,High"
else
rgroup.long 0x0D44++0x03
line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x12)
rgroup.long 0x0D48++0x03
line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
bitfld.long 0x00 31. " IRQS575 ,IRQS Status Bit 575" "Low,High"
bitfld.long 0x00 30. "  IRQS574 ,IRQS Status Bit 574" "Low,High"
bitfld.long 0x00 29. "  IRQS573 ,IRQS Status Bit 573" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS572 ,IRQS Status Bit 572" "Low,High"
bitfld.long 0x00 27. "  IRQS571 ,IRQS Status Bit 571" "Low,High"
bitfld.long 0x00 26. "  IRQS570 ,IRQS Status Bit 570" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS569 ,IRQS Status Bit 569" "Low,High"
bitfld.long 0x00 24. "  IRQS568 ,IRQS Status Bit 568" "Low,High"
bitfld.long 0x00 23. "  IRQS567 ,IRQS Status Bit 567" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS566 ,IRQS Status Bit 566" "Low,High"
bitfld.long 0x00 21. "  IRQS565 ,IRQS Status Bit 565" "Low,High"
bitfld.long 0x00 20. "  IRQS564 ,IRQS Status Bit 564" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS563 ,IRQS Status Bit 563" "Low,High"
bitfld.long 0x00 18. "  IRQS562 ,IRQS Status Bit 562" "Low,High"
bitfld.long 0x00 17. "  IRQS561 ,IRQS Status Bit 561" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS560 ,IRQS Status Bit 560" "Low,High"
bitfld.long 0x00 15. "  IRQS559 ,IRQS Status Bit 559" "Low,High"
bitfld.long 0x00 14. "  IRQS558 ,IRQS Status Bit 558" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS557 ,IRQS Status Bit 557" "Low,High"
bitfld.long 0x00 12. "  IRQS556 ,IRQS Status Bit 556" "Low,High"
bitfld.long 0x00 11. "  IRQS555 ,IRQS Status Bit 555" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS554 ,IRQS Status Bit 554" "Low,High"
bitfld.long 0x00 9. "  IRQS553 ,IRQS Status Bit 553" "Low,High"
bitfld.long 0x00 8. "  IRQS552 ,IRQS Status Bit 552" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS551 ,IRQS Status Bit 551" "Low,High"
bitfld.long 0x00 6. "  IRQS550 ,IRQS Status Bit 550" "Low,High"
bitfld.long 0x00 5. "  IRQS549 ,IRQS Status Bit 549" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS548 ,IRQS Status Bit 548" "Low,High"
bitfld.long 0x00 3. "  IRQS547 ,IRQS Status Bit 547" "Low,High"
bitfld.long 0x00 2. "  IRQS546 ,IRQS Status Bit 546" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS545 ,IRQS Status Bit 545" "Low,High"
bitfld.long 0x00 0. "  IRQS544 ,IRQS Status Bit 544" "Low,High"
else
rgroup.long 0x0D48++0x03
line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x13)
rgroup.long 0x0D4C++0x03
line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
bitfld.long 0x00 31. " IRQS607 ,IRQS Status Bit 607" "Low,High"
bitfld.long 0x00 30. "  IRQS606 ,IRQS Status Bit 606" "Low,High"
bitfld.long 0x00 29. "  IRQS605 ,IRQS Status Bit 605" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS604 ,IRQS Status Bit 604" "Low,High"
bitfld.long 0x00 27. "  IRQS603 ,IRQS Status Bit 603" "Low,High"
bitfld.long 0x00 26. "  IRQS602 ,IRQS Status Bit 602" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS601 ,IRQS Status Bit 601" "Low,High"
bitfld.long 0x00 24. "  IRQS600 ,IRQS Status Bit 600" "Low,High"
bitfld.long 0x00 23. "  IRQS599 ,IRQS Status Bit 599" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS598 ,IRQS Status Bit 598" "Low,High"
bitfld.long 0x00 21. "  IRQS597 ,IRQS Status Bit 597" "Low,High"
bitfld.long 0x00 20. "  IRQS596 ,IRQS Status Bit 596" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS595 ,IRQS Status Bit 595" "Low,High"
bitfld.long 0x00 18. "  IRQS594 ,IRQS Status Bit 594" "Low,High"
bitfld.long 0x00 17. "  IRQS593 ,IRQS Status Bit 593" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS592 ,IRQS Status Bit 592" "Low,High"
bitfld.long 0x00 15. "  IRQS591 ,IRQS Status Bit 591" "Low,High"
bitfld.long 0x00 14. "  IRQS590 ,IRQS Status Bit 590" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS589 ,IRQS Status Bit 589" "Low,High"
bitfld.long 0x00 12. "  IRQS588 ,IRQS Status Bit 588" "Low,High"
bitfld.long 0x00 11. "  IRQS587 ,IRQS Status Bit 587" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS586 ,IRQS Status Bit 586" "Low,High"
bitfld.long 0x00 9. "  IRQS585 ,IRQS Status Bit 585" "Low,High"
bitfld.long 0x00 8. "  IRQS584 ,IRQS Status Bit 584" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS583 ,IRQS Status Bit 583" "Low,High"
bitfld.long 0x00 6. "  IRQS582 ,IRQS Status Bit 582" "Low,High"
bitfld.long 0x00 5. "  IRQS581 ,IRQS Status Bit 581" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS580 ,IRQS Status Bit 580" "Low,High"
bitfld.long 0x00 3. "  IRQS579 ,IRQS Status Bit 579" "Low,High"
bitfld.long 0x00 2. "  IRQS578 ,IRQS Status Bit 578" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS577 ,IRQS Status Bit 577" "Low,High"
bitfld.long 0x00 0. "  IRQS576 ,IRQS Status Bit 576" "Low,High"
else
rgroup.long 0x0D4C++0x03
line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x14)
rgroup.long 0x0D50++0x03
line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
bitfld.long 0x00 31. " IRQS639 ,IRQS Status Bit 639" "Low,High"
bitfld.long 0x00 30. "  IRQS638 ,IRQS Status Bit 638" "Low,High"
bitfld.long 0x00 29. "  IRQS637 ,IRQS Status Bit 637" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS636 ,IRQS Status Bit 636" "Low,High"
bitfld.long 0x00 27. "  IRQS635 ,IRQS Status Bit 635" "Low,High"
bitfld.long 0x00 26. "  IRQS634 ,IRQS Status Bit 634" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS633 ,IRQS Status Bit 633" "Low,High"
bitfld.long 0x00 24. "  IRQS632 ,IRQS Status Bit 632" "Low,High"
bitfld.long 0x00 23. "  IRQS631 ,IRQS Status Bit 631" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS630 ,IRQS Status Bit 630" "Low,High"
bitfld.long 0x00 21. "  IRQS629 ,IRQS Status Bit 629" "Low,High"
bitfld.long 0x00 20. "  IRQS628 ,IRQS Status Bit 628" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS627 ,IRQS Status Bit 627" "Low,High"
bitfld.long 0x00 18. "  IRQS626 ,IRQS Status Bit 626" "Low,High"
bitfld.long 0x00 17. "  IRQS625 ,IRQS Status Bit 625" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS624 ,IRQS Status Bit 624" "Low,High"
bitfld.long 0x00 15. "  IRQS623 ,IRQS Status Bit 623" "Low,High"
bitfld.long 0x00 14. "  IRQS622 ,IRQS Status Bit 622" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS621 ,IRQS Status Bit 621" "Low,High"
bitfld.long 0x00 12. "  IRQS620 ,IRQS Status Bit 620" "Low,High"
bitfld.long 0x00 11. "  IRQS619 ,IRQS Status Bit 619" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS618 ,IRQS Status Bit 618" "Low,High"
bitfld.long 0x00 9. "  IRQS617 ,IRQS Status Bit 617" "Low,High"
bitfld.long 0x00 8. "  IRQS616 ,IRQS Status Bit 616" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS615 ,IRQS Status Bit 615" "Low,High"
bitfld.long 0x00 6. "  IRQS614 ,IRQS Status Bit 614" "Low,High"
bitfld.long 0x00 5. "  IRQS613 ,IRQS Status Bit 613" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS612 ,IRQS Status Bit 612" "Low,High"
bitfld.long 0x00 3. "  IRQS611 ,IRQS Status Bit 611" "Low,High"
bitfld.long 0x00 2. "  IRQS610 ,IRQS Status Bit 610" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS609 ,IRQS Status Bit 609" "Low,High"
bitfld.long 0x00 0. "  IRQS608 ,IRQS Status Bit 608" "Low,High"
else
rgroup.long 0x0D50++0x03
line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x15)
rgroup.long 0x0D54++0x03
line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
bitfld.long 0x00 31. " IRQS671 ,IRQS Status Bit 671" "Low,High"
bitfld.long 0x00 30. "  IRQS670 ,IRQS Status Bit 670" "Low,High"
bitfld.long 0x00 29. "  IRQS669 ,IRQS Status Bit 669" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS668 ,IRQS Status Bit 668" "Low,High"
bitfld.long 0x00 27. "  IRQS667 ,IRQS Status Bit 667" "Low,High"
bitfld.long 0x00 26. "  IRQS666 ,IRQS Status Bit 666" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS665 ,IRQS Status Bit 665" "Low,High"
bitfld.long 0x00 24. "  IRQS664 ,IRQS Status Bit 664" "Low,High"
bitfld.long 0x00 23. "  IRQS663 ,IRQS Status Bit 663" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS662 ,IRQS Status Bit 662" "Low,High"
bitfld.long 0x00 21. "  IRQS661 ,IRQS Status Bit 661" "Low,High"
bitfld.long 0x00 20. "  IRQS660 ,IRQS Status Bit 660" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS659 ,IRQS Status Bit 659" "Low,High"
bitfld.long 0x00 18. "  IRQS658 ,IRQS Status Bit 658" "Low,High"
bitfld.long 0x00 17. "  IRQS657 ,IRQS Status Bit 657" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS656 ,IRQS Status Bit 656" "Low,High"
bitfld.long 0x00 15. "  IRQS655 ,IRQS Status Bit 655" "Low,High"
bitfld.long 0x00 14. "  IRQS654 ,IRQS Status Bit 654" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS653 ,IRQS Status Bit 653" "Low,High"
bitfld.long 0x00 12. "  IRQS652 ,IRQS Status Bit 652" "Low,High"
bitfld.long 0x00 11. "  IRQS651 ,IRQS Status Bit 651" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS650 ,IRQS Status Bit 650" "Low,High"
bitfld.long 0x00 9. "  IRQS649 ,IRQS Status Bit 649" "Low,High"
bitfld.long 0x00 8. "  IRQS648 ,IRQS Status Bit 648" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS647 ,IRQS Status Bit 647" "Low,High"
bitfld.long 0x00 6. "  IRQS646 ,IRQS Status Bit 646" "Low,High"
bitfld.long 0x00 5. "  IRQS645 ,IRQS Status Bit 645" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS644 ,IRQS Status Bit 644" "Low,High"
bitfld.long 0x00 3. "  IRQS643 ,IRQS Status Bit 643" "Low,High"
bitfld.long 0x00 2. "  IRQS642 ,IRQS Status Bit 642" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS641 ,IRQS Status Bit 641" "Low,High"
bitfld.long 0x00 0. "  IRQS640 ,IRQS Status Bit 640" "Low,High"
else
rgroup.long 0x0D54++0x03
line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x16)
rgroup.long 0x0D58++0x03
line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
bitfld.long 0x00 31. " IRQS703 ,IRQS Status Bit 703" "Low,High"
bitfld.long 0x00 30. "  IRQS702 ,IRQS Status Bit 702" "Low,High"
bitfld.long 0x00 29. "  IRQS701 ,IRQS Status Bit 701" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS700 ,IRQS Status Bit 700" "Low,High"
bitfld.long 0x00 27. "  IRQS699 ,IRQS Status Bit 699" "Low,High"
bitfld.long 0x00 26. "  IRQS698 ,IRQS Status Bit 698" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS697 ,IRQS Status Bit 697" "Low,High"
bitfld.long 0x00 24. "  IRQS696 ,IRQS Status Bit 696" "Low,High"
bitfld.long 0x00 23. "  IRQS695 ,IRQS Status Bit 695" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS694 ,IRQS Status Bit 694" "Low,High"
bitfld.long 0x00 21. "  IRQS693 ,IRQS Status Bit 693" "Low,High"
bitfld.long 0x00 20. "  IRQS692 ,IRQS Status Bit 692" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS691 ,IRQS Status Bit 691" "Low,High"
bitfld.long 0x00 18. "  IRQS690 ,IRQS Status Bit 690" "Low,High"
bitfld.long 0x00 17. "  IRQS689 ,IRQS Status Bit 689" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS688 ,IRQS Status Bit 688" "Low,High"
bitfld.long 0x00 15. "  IRQS687 ,IRQS Status Bit 687" "Low,High"
bitfld.long 0x00 14. "  IRQS686 ,IRQS Status Bit 686" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS685 ,IRQS Status Bit 685" "Low,High"
bitfld.long 0x00 12. "  IRQS684 ,IRQS Status Bit 684" "Low,High"
bitfld.long 0x00 11. "  IRQS683 ,IRQS Status Bit 683" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS682 ,IRQS Status Bit 682" "Low,High"
bitfld.long 0x00 9. "  IRQS681 ,IRQS Status Bit 681" "Low,High"
bitfld.long 0x00 8. "  IRQS680 ,IRQS Status Bit 680" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS679 ,IRQS Status Bit 679" "Low,High"
bitfld.long 0x00 6. "  IRQS678 ,IRQS Status Bit 678" "Low,High"
bitfld.long 0x00 5. "  IRQS677 ,IRQS Status Bit 677" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS676 ,IRQS Status Bit 676" "Low,High"
bitfld.long 0x00 3. "  IRQS675 ,IRQS Status Bit 675" "Low,High"
bitfld.long 0x00 2. "  IRQS674 ,IRQS Status Bit 674" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS673 ,IRQS Status Bit 673" "Low,High"
bitfld.long 0x00 0. "  IRQS672 ,IRQS Status Bit 672" "Low,High"
else
rgroup.long 0x0D58++0x03
line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x17)
rgroup.long 0x0D5C++0x03
line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
bitfld.long 0x00 31. " IRQS735 ,IRQS Status Bit 735" "Low,High"
bitfld.long 0x00 30. "  IRQS734 ,IRQS Status Bit 734" "Low,High"
bitfld.long 0x00 29. "  IRQS733 ,IRQS Status Bit 733" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS732 ,IRQS Status Bit 732" "Low,High"
bitfld.long 0x00 27. "  IRQS731 ,IRQS Status Bit 731" "Low,High"
bitfld.long 0x00 26. "  IRQS730 ,IRQS Status Bit 730" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS729 ,IRQS Status Bit 729" "Low,High"
bitfld.long 0x00 24. "  IRQS728 ,IRQS Status Bit 728" "Low,High"
bitfld.long 0x00 23. "  IRQS727 ,IRQS Status Bit 727" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS726 ,IRQS Status Bit 726" "Low,High"
bitfld.long 0x00 21. "  IRQS725 ,IRQS Status Bit 725" "Low,High"
bitfld.long 0x00 20. "  IRQS724 ,IRQS Status Bit 724" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS723 ,IRQS Status Bit 723" "Low,High"
bitfld.long 0x00 18. "  IRQS722 ,IRQS Status Bit 722" "Low,High"
bitfld.long 0x00 17. "  IRQS721 ,IRQS Status Bit 721" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS720 ,IRQS Status Bit 720" "Low,High"
bitfld.long 0x00 15. "  IRQS719 ,IRQS Status Bit 719" "Low,High"
bitfld.long 0x00 14. "  IRQS718 ,IRQS Status Bit 718" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS717 ,IRQS Status Bit 717" "Low,High"
bitfld.long 0x00 12. "  IRQS716 ,IRQS Status Bit 716" "Low,High"
bitfld.long 0x00 11. "  IRQS715 ,IRQS Status Bit 715" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS714 ,IRQS Status Bit 714" "Low,High"
bitfld.long 0x00 9. "  IRQS713 ,IRQS Status Bit 713" "Low,High"
bitfld.long 0x00 8. "  IRQS712 ,IRQS Status Bit 712" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS711 ,IRQS Status Bit 711" "Low,High"
bitfld.long 0x00 6. "  IRQS710 ,IRQS Status Bit 710" "Low,High"
bitfld.long 0x00 5. "  IRQS709 ,IRQS Status Bit 709" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS708 ,IRQS Status Bit 708" "Low,High"
bitfld.long 0x00 3. "  IRQS707 ,IRQS Status Bit 707" "Low,High"
bitfld.long 0x00 2. "  IRQS706 ,IRQS Status Bit 706" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS705 ,IRQS Status Bit 705" "Low,High"
bitfld.long 0x00 0. "  IRQS704 ,IRQS Status Bit 704" "Low,High"
else
rgroup.long 0x0D5C++0x03
line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x18)
rgroup.long 0x060++0x03
line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
bitfld.long 0x00 31. " IRQS767 ,IRQS Status Bit 767" "Low,High"
bitfld.long 0x00 30. "  IRQS766 ,IRQS Status Bit 766" "Low,High"
bitfld.long 0x00 29. "  IRQS765 ,IRQS Status Bit 765" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS764 ,IRQS Status Bit 764" "Low,High"
bitfld.long 0x00 27. "  IRQS763 ,IRQS Status Bit 763" "Low,High"
bitfld.long 0x00 26. "  IRQS762 ,IRQS Status Bit 762" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS761 ,IRQS Status Bit 761" "Low,High"
bitfld.long 0x00 24. "  IRQS760 ,IRQS Status Bit 760" "Low,High"
bitfld.long 0x00 23. "  IRQS759 ,IRQS Status Bit 759" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS758 ,IRQS Status Bit 758" "Low,High"
bitfld.long 0x00 21. "  IRQS757 ,IRQS Status Bit 757" "Low,High"
bitfld.long 0x00 20. "  IRQS756 ,IRQS Status Bit 756" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS755 ,IRQS Status Bit 755" "Low,High"
bitfld.long 0x00 18. "  IRQS754 ,IRQS Status Bit 754" "Low,High"
bitfld.long 0x00 17. "  IRQS753 ,IRQS Status Bit 753" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS752 ,IRQS Status Bit 752" "Low,High"
bitfld.long 0x00 15. "  IRQS751 ,IRQS Status Bit 751" "Low,High"
bitfld.long 0x00 14. "  IRQS750 ,IRQS Status Bit 750" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS749 ,IRQS Status Bit 749" "Low,High"
bitfld.long 0x00 12. "  IRQS748 ,IRQS Status Bit 748" "Low,High"
bitfld.long 0x00 11. "  IRQS747 ,IRQS Status Bit 747" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS746 ,IRQS Status Bit 746" "Low,High"
bitfld.long 0x00 9. "  IRQS745 ,IRQS Status Bit 745" "Low,High"
bitfld.long 0x00 8. "  IRQS744 ,IRQS Status Bit 744" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS743 ,IRQS Status Bit 743" "Low,High"
bitfld.long 0x00 6. "  IRQS742 ,IRQS Status Bit 742" "Low,High"
bitfld.long 0x00 5. "  IRQS741 ,IRQS Status Bit 741" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS740 ,IRQS Status Bit 740" "Low,High"
bitfld.long 0x00 3. "  IRQS739 ,IRQS Status Bit 739" "Low,High"
bitfld.long 0x00 2. "  IRQS738 ,IRQS Status Bit 738" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS737 ,IRQS Status Bit 737" "Low,High"
bitfld.long 0x00 0. "  IRQS736 ,IRQS Status Bit 736" "Low,High"
else
rgroup.long 0x0D60++0x03
line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x19)
rgroup.long 0x0D64++0x03
line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
bitfld.long 0x00 31. " IRQS799 ,IRQS Status Bit 799" "Low,High"
bitfld.long 0x00 30. "  IRQS798 ,IRQS Status Bit 798" "Low,High"
bitfld.long 0x00 29. "  IRQS797 ,IRQS Status Bit 797" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS796 ,IRQS Status Bit 796" "Low,High"
bitfld.long 0x00 27. "  IRQS795 ,IRQS Status Bit 795" "Low,High"
bitfld.long 0x00 26. "  IRQS794 ,IRQS Status Bit 794" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS793 ,IRQS Status Bit 793" "Low,High"
bitfld.long 0x00 24. "  IRQS792 ,IRQS Status Bit 792" "Low,High"
bitfld.long 0x00 23. "  IRQS791 ,IRQS Status Bit 791" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS790 ,IRQS Status Bit 790" "Low,High"
bitfld.long 0x00 21. "  IRQS789 ,IRQS Status Bit 789" "Low,High"
bitfld.long 0x00 20. "  IRQS788 ,IRQS Status Bit 788" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS787 ,IRQS Status Bit 787" "Low,High"
bitfld.long 0x00 18. "  IRQS786 ,IRQS Status Bit 786" "Low,High"
bitfld.long 0x00 17. "  IRQS785 ,IRQS Status Bit 785" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS784 ,IRQS Status Bit 784" "Low,High"
bitfld.long 0x00 15. "  IRQS783 ,IRQS Status Bit 783" "Low,High"
bitfld.long 0x00 14. "  IRQS782 ,IRQS Status Bit 782" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS781 ,IRQS Status Bit 781" "Low,High"
bitfld.long 0x00 12. "  IRQS780 ,IRQS Status Bit 780" "Low,High"
bitfld.long 0x00 11. "  IRQS779 ,IRQS Status Bit 779" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS778 ,IRQS Status Bit 778" "Low,High"
bitfld.long 0x00 9. "  IRQS777 ,IRQS Status Bit 777" "Low,High"
bitfld.long 0x00 8. "  IRQS776 ,IRQS Status Bit 776" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS775 ,IRQS Status Bit 775" "Low,High"
bitfld.long 0x00 6. "  IRQS774 ,IRQS Status Bit 774" "Low,High"
bitfld.long 0x00 5. "  IRQS773 ,IRQS Status Bit 773" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS772 ,IRQS Status Bit 772" "Low,High"
bitfld.long 0x00 3. "  IRQS771 ,IRQS Status Bit 771" "Low,High"
bitfld.long 0x00 2. "  IRQS770 ,IRQS Status Bit 770" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS769 ,IRQS Status Bit 769" "Low,High"
bitfld.long 0x00 0. "  IRQS768 ,IRQS Status Bit 768" "Low,High"
else
rgroup.long 0x0D64++0x03
line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1A)
rgroup.long 0x0D68++0x03
line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
bitfld.long 0x00 31. " IRQS831 ,IRQS Status Bit 831" "Low,High"
bitfld.long 0x00 30. "  IRQS830 ,IRQS Status Bit 830" "Low,High"
bitfld.long 0x00 29. "  IRQS829 ,IRQS Status Bit 829" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS828 ,IRQS Status Bit 828" "Low,High"
bitfld.long 0x00 27. "  IRQS827 ,IRQS Status Bit 827" "Low,High"
bitfld.long 0x00 26. "  IRQS826 ,IRQS Status Bit 826" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS825 ,IRQS Status Bit 825" "Low,High"
bitfld.long 0x00 24. "  IRQS824 ,IRQS Status Bit 824" "Low,High"
bitfld.long 0x00 23. "  IRQS823 ,IRQS Status Bit 823" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS822 ,IRQS Status Bit 822" "Low,High"
bitfld.long 0x00 21. "  IRQS821 ,IRQS Status Bit 821" "Low,High"
bitfld.long 0x00 20. "  IRQS820 ,IRQS Status Bit 820" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS819 ,IRQS Status Bit 819" "Low,High"
bitfld.long 0x00 18. "  IRQS818 ,IRQS Status Bit 818" "Low,High"
bitfld.long 0x00 17. "  IRQS817 ,IRQS Status Bit 817" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS816 ,IRQS Status Bit 816" "Low,High"
bitfld.long 0x00 15. "  IRQS815 ,IRQS Status Bit 815" "Low,High"
bitfld.long 0x00 14. "  IRQS814 ,IRQS Status Bit 814" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS813 ,IRQS Status Bit 813" "Low,High"
bitfld.long 0x00 12. "  IRQS812 ,IRQS Status Bit 812" "Low,High"
bitfld.long 0x00 11. "  IRQS811 ,IRQS Status Bit 811" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS810 ,IRQS Status Bit 810" "Low,High"
bitfld.long 0x00 9. "  IRQS809 ,IRQS Status Bit 809" "Low,High"
bitfld.long 0x00 8. "  IRQS808 ,IRQS Status Bit 808" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS807 ,IRQS Status Bit 807" "Low,High"
bitfld.long 0x00 6. "  IRQS806 ,IRQS Status Bit 806" "Low,High"
bitfld.long 0x00 5. "  IRQS805 ,IRQS Status Bit 805" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS804 ,IRQS Status Bit 804" "Low,High"
bitfld.long 0x00 3. "  IRQS803 ,IRQS Status Bit 803" "Low,High"
bitfld.long 0x00 2. "  IRQS802 ,IRQS Status Bit 802" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS801 ,IRQS Status Bit 801" "Low,High"
bitfld.long 0x00 0. "  IRQS800 ,IRQS Status Bit 800" "Low,High"
else
rgroup.long 0x0D68++0x03
line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1B)
rgroup.long 0x0D6C++0x03
line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
bitfld.long 0x00 31. " IRQS863 ,IRQS Status Bit 863" "Low,High"
bitfld.long 0x00 30. "  IRQS862 ,IRQS Status Bit 862" "Low,High"
bitfld.long 0x00 29. "  IRQS861 ,IRQS Status Bit 861" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS860 ,IRQS Status Bit 860" "Low,High"
bitfld.long 0x00 27. "  IRQS859 ,IRQS Status Bit 859" "Low,High"
bitfld.long 0x00 26. "  IRQS858 ,IRQS Status Bit 858" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS857 ,IRQS Status Bit 857" "Low,High"
bitfld.long 0x00 24. "  IRQS856 ,IRQS Status Bit 856" "Low,High"
bitfld.long 0x00 23. "  IRQS855 ,IRQS Status Bit 855" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS854 ,IRQS Status Bit 854" "Low,High"
bitfld.long 0x00 21. "  IRQS853 ,IRQS Status Bit 853" "Low,High"
bitfld.long 0x00 20. "  IRQS852 ,IRQS Status Bit 852" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS851 ,IRQS Status Bit 851" "Low,High"
bitfld.long 0x00 18. "  IRQS850 ,IRQS Status Bit 850" "Low,High"
bitfld.long 0x00 17. "  IRQS849 ,IRQS Status Bit 849" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS848 ,IRQS Status Bit 848" "Low,High"
bitfld.long 0x00 15. "  IRQS847 ,IRQS Status Bit 847" "Low,High"
bitfld.long 0x00 14. "  IRQS846 ,IRQS Status Bit 846" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS845 ,IRQS Status Bit 845" "Low,High"
bitfld.long 0x00 12. "  IRQS844 ,IRQS Status Bit 844" "Low,High"
bitfld.long 0x00 11. "  IRQS843 ,IRQS Status Bit 843" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS842 ,IRQS Status Bit 842" "Low,High"
bitfld.long 0x00 9. "  IRQS841 ,IRQS Status Bit 841" "Low,High"
bitfld.long 0x00 8. "  IRQS840 ,IRQS Status Bit 840" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS839 ,IRQS Status Bit 839" "Low,High"
bitfld.long 0x00 6. "  IRQS838 ,IRQS Status Bit 838" "Low,High"
bitfld.long 0x00 5. "  IRQS837 ,IRQS Status Bit 837" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS836 ,IRQS Status Bit 836" "Low,High"
bitfld.long 0x00 3. "  IRQS835 ,IRQS Status Bit 835" "Low,High"
bitfld.long 0x00 2. "  IRQS834 ,IRQS Status Bit 834" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS833 ,IRQS Status Bit 833" "Low,High"
bitfld.long 0x00 0. "  IRQS832 ,IRQS Status Bit 832" "Low,High"
else
rgroup.long 0x0D6C++0x03
line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1C)
rgroup.long 0x0D70++0x03
line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
bitfld.long 0x00 31. " IRQS895 ,IRQS Status Bit 895" "Low,High"
bitfld.long 0x00 30. "  IRQS894 ,IRQS Status Bit 894" "Low,High"
bitfld.long 0x00 29. "  IRQS893 ,IRQS Status Bit 893" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS892 ,IRQS Status Bit 892" "Low,High"
bitfld.long 0x00 27. "  IRQS891 ,IRQS Status Bit 891" "Low,High"
bitfld.long 0x00 26. "  IRQS890 ,IRQS Status Bit 890" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS889 ,IRQS Status Bit 889" "Low,High"
bitfld.long 0x00 24. "  IRQS888 ,IRQS Status Bit 888" "Low,High"
bitfld.long 0x00 23. "  IRQS887 ,IRQS Status Bit 887" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS886 ,IRQS Status Bit 886" "Low,High"
bitfld.long 0x00 21. "  IRQS885 ,IRQS Status Bit 885" "Low,High"
bitfld.long 0x00 20. "  IRQS884 ,IRQS Status Bit 884" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS883 ,IRQS Status Bit 883" "Low,High"
bitfld.long 0x00 18. "  IRQS882 ,IRQS Status Bit 882" "Low,High"
bitfld.long 0x00 17. "  IRQS881 ,IRQS Status Bit 881" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS880 ,IRQS Status Bit 880" "Low,High"
bitfld.long 0x00 15. "  IRQS879 ,IRQS Status Bit 879" "Low,High"
bitfld.long 0x00 14. "  IRQS878 ,IRQS Status Bit 878" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS877 ,IRQS Status Bit 877" "Low,High"
bitfld.long 0x00 12. "  IRQS876 ,IRQS Status Bit 876" "Low,High"
bitfld.long 0x00 11. "  IRQS875 ,IRQS Status Bit 875" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS874 ,IRQS Status Bit 874" "Low,High"
bitfld.long 0x00 9. "  IRQS873 ,IRQS Status Bit 873" "Low,High"
bitfld.long 0x00 8. "  IRQS872 ,IRQS Status Bit 872" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS871 ,IRQS Status Bit 871" "Low,High"
bitfld.long 0x00 6. "  IRQS870 ,IRQS Status Bit 870" "Low,High"
bitfld.long 0x00 5. "  IRQS869 ,IRQS Status Bit 869" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS868 ,IRQS Status Bit 868" "Low,High"
bitfld.long 0x00 3. "  IRQS867 ,IRQS Status Bit 867" "Low,High"
bitfld.long 0x00 2. "  IRQS866 ,IRQS Status Bit 866" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS865 ,IRQS Status Bit 865" "Low,High"
bitfld.long 0x00 0. "  IRQS864 ,IRQS Status Bit 864" "Low,High"
else
rgroup.long 0x0D70++0x03
line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1D)
rgroup.long 0x0D74++0x03
line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
bitfld.long 0x00 31. " IRQS927 ,IRQS Status Bit 927" "Low,High"
bitfld.long 0x00 30. "  IRQS926 ,IRQS Status Bit 926" "Low,High"
bitfld.long 0x00 29. "  IRQS925 ,IRQS Status Bit 925" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS924 ,IRQS Status Bit 924" "Low,High"
bitfld.long 0x00 27. "  IRQS923 ,IRQS Status Bit 923" "Low,High"
bitfld.long 0x00 26. "  IRQS922 ,IRQS Status Bit 922" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS921 ,IRQS Status Bit 921" "Low,High"
bitfld.long 0x00 24. "  IRQS920 ,IRQS Status Bit 920" "Low,High"
bitfld.long 0x00 23. "  IRQS919 ,IRQS Status Bit 919" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS918 ,IRQS Status Bit 918" "Low,High"
bitfld.long 0x00 21. "  IRQS917 ,IRQS Status Bit 917" "Low,High"
bitfld.long 0x00 20. "  IRQS916 ,IRQS Status Bit 916" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS915 ,IRQS Status Bit 915" "Low,High"
bitfld.long 0x00 18. "  IRQS914 ,IRQS Status Bit 914" "Low,High"
bitfld.long 0x00 17. "  IRQS913 ,IRQS Status Bit 913" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS912 ,IRQS Status Bit 912" "Low,High"
bitfld.long 0x00 15. "  IRQS911 ,IRQS Status Bit 911" "Low,High"
bitfld.long 0x00 14. "  IRQS910 ,IRQS Status Bit 910" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS909 ,IRQS Status Bit 909" "Low,High"
bitfld.long 0x00 12. "  IRQS908 ,IRQS Status Bit 908" "Low,High"
bitfld.long 0x00 11. "  IRQS907 ,IRQS Status Bit 907" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS906 ,IRQS Status Bit 906" "Low,High"
bitfld.long 0x00 9. "  IRQS905 ,IRQS Status Bit 905" "Low,High"
bitfld.long 0x00 8. "  IRQS904 ,IRQS Status Bit 904" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS903 ,IRQS Status Bit 903" "Low,High"
bitfld.long 0x00 6. "  IRQS902 ,IRQS Status Bit 902" "Low,High"
bitfld.long 0x00 5. "  IRQS901 ,IRQS Status Bit 901" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS900 ,IRQS Status Bit 900" "Low,High"
bitfld.long 0x00 3. "  IRQS899 ,IRQS Status Bit 899" "Low,High"
bitfld.long 0x00 2. "  IRQS898 ,IRQS Status Bit 898" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS897 ,IRQS Status Bit 897" "Low,High"
bitfld.long 0x00 0. "  IRQS896 ,IRQS Status Bit 896" "Low,High"
else
rgroup.long 0x0D74++0x03
line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1E)
rgroup.long 0x0D78++0x03
line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
bitfld.long 0x00 31. " IRQS959 ,IRQS Status Bit 959" "Low,High"
bitfld.long 0x00 30. "  IRQS958 ,IRQS Status Bit 958" "Low,High"
bitfld.long 0x00 29. "  IRQS957 ,IRQS Status Bit 957" "Low,High"
textline "                               "
bitfld.long 0x00 28. " IRQS956 ,IRQS Status Bit 956" "Low,High"
bitfld.long 0x00 27. "  IRQS955 ,IRQS Status Bit 955" "Low,High"
bitfld.long 0x00 26. "  IRQS954 ,IRQS Status Bit 954" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS953 ,IRQS Status Bit 953" "Low,High"
bitfld.long 0x00 24. "  IRQS952 ,IRQS Status Bit 952" "Low,High"
bitfld.long 0x00 23. "  IRQS951 ,IRQS Status Bit 951" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS950 ,IRQS Status Bit 950" "Low,High"
bitfld.long 0x00 21. "  IRQS949 ,IRQS Status Bit 949" "Low,High"
bitfld.long 0x00 20. "  IRQS948 ,IRQS Status Bit 948" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS947 ,IRQS Status Bit 947" "Low,High"
bitfld.long 0x00 18. "  IRQS946 ,IRQS Status Bit 946" "Low,High"
bitfld.long 0x00 17. "  IRQS945 ,IRQS Status Bit 945" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS944 ,IRQS Status Bit 944" "Low,High"
bitfld.long 0x00 15. "  IRQS943 ,IRQS Status Bit 943" "Low,High"
bitfld.long 0x00 14. "  IRQS942 ,IRQS Status Bit 942" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS941 ,IRQS Status Bit 941" "Low,High"
bitfld.long 0x00 12. "  IRQS940 ,IRQS Status Bit 940" "Low,High"
bitfld.long 0x00 11. "  IRQS939 ,IRQS Status Bit 939" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS938 ,IRQS Status Bit 938" "Low,High"
bitfld.long 0x00 9. "  IRQS937 ,IRQS Status Bit 937" "Low,High"
bitfld.long 0x00 8. "  IRQS936 ,IRQS Status Bit 936" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS935 ,IRQS Status Bit 935" "Low,High"
bitfld.long 0x00 6. "  IRQS934 ,IRQS Status Bit 934" "Low,High"
bitfld.long 0x00 5. "  IRQS933 ,IRQS Status Bit 933" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS932 ,IRQS Status Bit 932" "Low,High"
bitfld.long 0x00 3. "  IRQS931 ,IRQS Status Bit 931" "Low,High"
bitfld.long 0x00 2. "  IRQS930 ,IRQS Status Bit 930" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS929 ,IRQS Status Bit 929" "Low,High"
bitfld.long 0x00 0. "  IRQS928 ,IRQS Status Bit 928" "Low,High"
else
rgroup.long 0x0D78++0x03
line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(ad:0xFFFC1000+0x04))&0x0000001F)>=0x1F)
rgroup.long 0x0D7C++0x03
line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30"
bitfld.long 0x00 27. " IRQS987 ,IRQS Status Bit 987" "Low,High"
bitfld.long 0x00 26. "  IRQS986 ,IRQS Status Bit 986" "Low,High"
textline "                               "
bitfld.long 0x00 25. " IRQS985 ,IRQS Status Bit 985" "Low,High"
bitfld.long 0x00 24. "  IRQS984 ,IRQS Status Bit 984" "Low,High"
bitfld.long 0x00 23. "  IRQS983 ,IRQS Status Bit 983" "Low,High"
textline "                               "
bitfld.long 0x00 22. " IRQS982 ,IRQS Status Bit 982" "Low,High"
bitfld.long 0x00 21. "  IRQS981 ,IRQS Status Bit 981" "Low,High"
bitfld.long 0x00 20. "  IRQS980 ,IRQS Status Bit 980" "Low,High"
textline "                               "
bitfld.long 0x00 19. " IRQS979 ,IRQS Status Bit 979" "Low,High"
bitfld.long 0x00 18. "  IRQS978 ,IRQS Status Bit 978" "Low,High"
bitfld.long 0x00 17. "  IRQS977 ,IRQS Status Bit 977" "Low,High"
textline "                               "
bitfld.long 0x00 16. " IRQS976 ,IRQS Status Bit 976" "Low,High"
bitfld.long 0x00 15. "  IRQS975 ,IRQS Status Bit 975" "Low,High"
bitfld.long 0x00 14. "  IRQS974 ,IRQS Status Bit 974" "Low,High"
textline "                               "
bitfld.long 0x00 13. " IRQS973 ,IRQS Status Bit 973" "Low,High"
bitfld.long 0x00 12. "  IRQS972 ,IRQS Status Bit 972" "Low,High"
bitfld.long 0x00 11. "  IRQS971 ,IRQS Status Bit 971" "Low,High"
textline "                               "
bitfld.long 0x00 10. " IRQS970 ,IRQS Status Bit 970" "Low,High"
bitfld.long 0x00 9. "  IRQS969 ,IRQS Status Bit 969" "Low,High"
bitfld.long 0x00 8. "  IRQS968 ,IRQS Status Bit 968" "Low,High"
textline "                               "
bitfld.long 0x00 7. " IRQS967 ,IRQS Status Bit 967" "Low,High"
bitfld.long 0x00 6. "  IRQS966 ,IRQS Status Bit 966" "Low,High"
bitfld.long 0x00 5. "  IRQS965 ,IRQS Status Bit 965" "Low,High"
textline "                               "
bitfld.long 0x00 4. " IRQS964 ,IRQS Status Bit 964" "Low,High"
bitfld.long 0x00 3. "  IRQS963 ,IRQS Status Bit 963" "Low,High"
bitfld.long 0x00 2. "  IRQS962 ,IRQS Status Bit 962" "Low,High"
textline "                               "
bitfld.long 0x00 1. " IRQS961 ,IRQS Status Bit 961" "Low,High"
bitfld.long 0x00 0. "  IRQS960 ,IRQS Status Bit 960" "Low,High"
else
rgroup.long 0x0D7C++0x03
line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
tree.end
width 25.
tree "Software Generated Interrupt"
if (((per.l(ad:0xFFFC1000+0x04))&0x400)==0x400)
wgroup.long 0x0F00++0x03
line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
bitfld.long 0x00 24.--25. " TLF           ,Target List Filter" "TargetList,All CPUs,Request CPU,?..."
hexmask.long.byte 0x00 16.--23. 1. "  CPUTL         ,CPU Target List"
textline "                                  "
bitfld.long 0x00 15. " NSATT         ,NSATT" "Secure,Non-secure"
bitfld.long 0x00 0.--3. "   SGINTID       ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
wgroup.long 0x0F00++0x03
line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
bitfld.long 0x00 24.--25. " TLF           ,Target List Filter" "TargetList,All CPUs,Request CPU,?..."
hexmask.long.byte 0x00 16.--23. 1. "  CPUTL         ,CPU Target List"
textline "                                  "
bitfld.long 0x00 0.--3. " SGINTID       ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.long 0x0F20++0x03
line.long 0x00 "GICD_SET/CLR_PENDSGIR0,SGI Set/Clear Pending Register 0"
setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI0  ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. -0x10 30. "     SET/CLR_SGI0  ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. -0x10 29. "  SET/CLR_SGI0  ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI0  ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. -0x10 27. "     SET/CLR_SGI0  ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. -0x10 26. "  SET/CLR_SGI0  ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI0  ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. -0x10 24. "     SET/CLR_SGI0  ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. -0x10 23. "  SET/CLR_SGI1  ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI1  ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. -0x10 21. "     SET/CLR_SGI1  ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. -0x10 20. "  SET/CLR_SGI1  ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI1  ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. -0x10 18. "     SET/CLR_SGI1  ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. -0x10 17. "  SET/CLR_SGI1  ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI1  ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. -0x10 15. "     SET/CLR_SGI2  ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. -0x10 14. "  SET/CLR_SGI2  ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI2  ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. -0x10 12. "     SET/CLR_SGI2  ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. -0x10 11. "  SET/CLR_SGI2  ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI2  ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. -0x10 9. "     SET/CLR_SGI2  ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. -0x10 8. "  SET/CLR_SGI2  ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI3  ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. -0x10 6. "     SET/CLR_SGI3  ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. -0x10 5. "  SET/CLR_SGI3  ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI3  ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. -0x10 3. "     SET/CLR_SGI3  ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. -0x10 2. "  SET/CLR_SGI3  ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI3  ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. -0x10 0. "     SET/CLR_SGI3  ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled"
group.long 0x0F24++0x03
line.long 0x00 "GICD_SET/CLR_PENDSGIR1,SGI Set/Clear Pending Register 1"
setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI4  ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. -0x10 30. "     SET/CLR_SGI4  ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. -0x10 29. "  SET/CLR_SGI4  ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI4  ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. -0x10 27. "     SET/CLR_SGI4  ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. -0x10 26. "  SET/CLR_SGI4  ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI4  ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. -0x10 24. "     SET/CLR_SGI4  ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. -0x10 23. "  SET/CLR_SGI5  ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI5  ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. -0x10 21. "     SET/CLR_SGI5  ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. -0x10 20. "  SET/CLR_SGI5  ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI5  ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. -0x10 18. "     SET/CLR_SGI5  ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. -0x10 17. "  SET/CLR_SGI5  ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI5  ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. -0x10 15. "     SET/CLR_SGI6  ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. -0x10 14. "  SET/CLR_SGI6  ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI6  ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. -0x10 12. "     SET/CLR_SGI6  ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. -0x10 11. "  SET/CLR_SGI6  ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI6  ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. -0x10 9. "     SET/CLR_SGI6  ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. -0x10 8. "  SET/CLR_SGI6  ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI7  ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. -0x10 6. "     SET/CLR_SGI7  ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. -0x10 5. "  SET/CLR_SGI7  ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI7  ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. -0x10 3. "     SET/CLR_SGI7  ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. -0x10 2. "  SET/CLR_SGI7  ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI7  ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. -0x10 0. "     SET/CLR_SGI7  ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled"
group.long 0x0F28++0x03
line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 2"
setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI8  ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. -0x10 30. "     SET/CLR_SGI8  ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. -0x10 29. "  SET/CLR_SGI8  ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI8  ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. -0x10 27. "     SET/CLR_SGI8  ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. -0x10 26. "  SET/CLR_SGI8  ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI8  ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. -0x10 24. "     SET/CLR_SGI8  ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. -0x10 23. "  SET/CLR_SGI9  ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI9  ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. -0x10 21. "     SET/CLR_SGI9  ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. -0x10 20. "  SET/CLR_SGI9  ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI9  ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. -0x10 18. "     SET/CLR_SGI9  ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. -0x10 17. "  SET/CLR_SGI9  ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI9  ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. -0x10 15. "     SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. -0x10 14. "  SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. -0x10 12. "     SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. -0x10 11. "  SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. -0x10 9. "     SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. -0x10 8. "  SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. -0x10 6. "     SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. -0x10 5. "  SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. -0x10 3. "     SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. -0x10 2. "  SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. -0x10 0. "     SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled"
group.long 0x0F2C++0x03
line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 3"
setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. -0x10 30. "     SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. -0x10 29. "  SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. -0x10 27. "     SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. -0x10 26. "  SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. -0x10 24. "     SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. -0x10 23. "  SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. -0x10 21. "     SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. -0x10 20. "  SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. -0x10 18. "     SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. -0x10 17. "  SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. -0x10 15. "     SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. -0x10 14. "  SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. -0x10 12. "     SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. -0x10 11. "  SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. -0x10 9. "     SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. -0x10 8. "  SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. -0x10 6. "     SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. -0x10 5. "  SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. -0x10 3. "     SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. -0x10 2. "  SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
textline "                                  "
setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. -0x10 0. "     SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled"
tree.end
width 12.
tree "Peripheral/Component ID Registers"
rgroup.byte 0x0FE0++0x00
line.byte 0x00 "GICD_PIDR0,Peripheral ID0 Register"
hexmask.byte 0x00 0.--7. 1. " DEVID         ,DevID field"
rgroup.byte 0x0FE4++0x00
line.byte 0x00 "GICD_PIDR1,Peripheral ID1 Register"
bitfld.byte 0x00 4.--7. " ARCHID        ,ArchID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "             DEVID         ,DevID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x0FE8++0x00
line.byte 0x00 "GICD_PIDR2,Peripheral ID2 Register"
bitfld.byte 0x00 4.--7. " ARCHREV       ,ArchRev field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 3. "             UJEPCODE      ,UsesJEPcode field" "Low,High"
bitfld.byte 0x00 0.--2. "           ARCHID         ,ArchID field" "0,1,2,3,4,5,6,7"
rgroup.byte 0x0FEC++0x00
line.byte 0x00 "GICD_PIDR3,Peripheral ID3 Register"
bitfld.byte 0x00 4.--7. " REVID         ,Revision field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x0FD0++0x00
line.byte 0x00 "GICD_PIDR4,Peripheral ID4 Register"
bitfld.byte 0x00 0.--3. " CC            ,ContinuationCode field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0xFD4++0x00
line.byte 0x00 "GICD_PIDR5,Peripheral ID5 Register"
rgroup.byte 0xFD8++0x00
line.byte 0x00 "GICD_PIDR6,Peripheral ID6 Register"
rgroup.byte 0xFDC++0x00
line.byte 0x00 "GICD_PIDR7,Peripheral ID7 Register"
textline "                 "
rgroup.byte 0xFF0++0x00
line.byte 0x00 "GICD_CIDR0,Component ID0 Register"
hexmask.byte 0x00 0.--7. 1. " FIXVAL        ,ARM-defined fixed values for the preamble for component discovery"
rgroup.byte 0xFF4++0x00
line.byte 0x00 "GICD_CIDR1,Component ID1 Register"
hexmask.byte 0x00 0.--7. 1. " FIXVAL        ,ARM-defined fixed values for the preamble for component discovery"
rgroup.byte 0xFF8++0x00
line.byte 0x00 "GICD_CIDR2,Component ID2 Register"
hexmask.byte 0x00 0.--7. 1. " FIXVAL        ,ARM-defined fixed values for the preamble for component discovery"
rgroup.byte 0xFFC++0x00
line.byte 0x00 "GICD_CIDR3,Component ID3 Register"
hexmask.byte 0x00 0.--7. 1. " FIXVAL        ,ARM-defined fixed values for the preamble for component discovery"
textline "                 "
tree.end
tree.end
width 0x0B
base ad:0xFFFC2000
width 17.
tree "CPU Interface"
if (((per.l(ad:0xFFFC1000+0x04))&0x400)==0x0)
group.long 0x0000++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
bitfld.long 0x00 9. " EOIMODENS     ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop"
bitfld.long 0x00 6. "  IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled"
bitfld.long 0x00 5. "              FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled"
textline "                          "
bitfld.long 0x00 0. " ENABLEGRP1    ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled"
textline "                          "
textline "                          "
else
if PER.ADDRESS.isSECUREEX(ad:0xFFFC2000)
group.long 0x0000++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register (Secure access)"
bitfld.long 0x00 10. " EOIMODENS     ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop"
bitfld.long 0x00 9. "  EOIMODES      ,Controls the behavior of accesses to GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop"
bitfld.long 0x00 8. "  IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled"
textline "                          "
bitfld.long 0x00 7. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled"
bitfld.long 0x00 6. "              IRQBYPDISGRP0 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled"
bitfld.long 0x00 5. "              FIQBYPDISGRP0 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled"
textline "                          "
bitfld.long 0x00 4. " CBPR          ,Controls whether the GICC_BPR provides common control to Group 0 and Group 1 interrupts" "BPR/ABPR split,BPR common"
bitfld.long 0x00 3. "            FIQEN         ,Controls whether the CPU interface signals Group 0 interrupts to a target processor using the FIQ or the IRQ signal" "IRQ,FIQ"
bitfld.long 0x00 2. "                       ACKCTL        ,Acknowledge Control" "ID 1022 interrupt,Corresponding interrupt"
textline "                          "
bitfld.long 0x00 1. " ENABLEGRP1    ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled"
bitfld.long 0x00 0. "                  ENABLEGRP0    ,Enable for the signaling of Group 0 interrupts by the CPU interface to the connected processor" "Disabled,Enabled"
else
group.long 0x0000++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register  (Non-secure access)"
bitfld.long 0x00 9. " EOIMODENS     ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop"
bitfld.long 0x00 6. "  IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled"
bitfld.long 0x00 5. "              FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled"
textline "                          "
bitfld.long 0x00 0. " ENABLEGRP1    ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled"
textline "                          "
textline "                          "
endif
endif
group.long 0x0004++0x03
line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY      ,Priority mask level for CPU interface"
if (((per.l(ad:0xFFFC1000+0x04))&0x400)==0x400)
if PER.ADDRESS.isSECUREEX(ad:0xFFFC2000+0x0008)
group.long 0x0008++0x03
line.long 0x00 "GICC_BPR,Binary Point Register (Secure access)"
bitfld.long 0x00 0.--2. " BINARY_POINT  ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
else
group.long 0x0008++0x03
line.long 0x00 "GICC_BPR,Binary Point Register (Non-secure access)"
bitfld.long 0x00 0.--2. " BINARY_POINT  ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
endif
else
group.long 0x0008++0x03
line.long 0x00 "GICC_BPR,Binary Point Register"
bitfld.long 0x00 0.--2. " BINARY_POINT  ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
endif
hgroup.long 0x000C++0x03
hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register"
in
wgroup.long 0x0010++0x03
line.long 0x00 "GICC_EOIR,End Of Interrupt Register"
bitfld.long 0x00 10.--12. " CPUID         ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "                         EOIINTID      ,The Interrupt ID value from the corresponding GICC_IAR access"
rgroup.long 0x0014++0x03
line.long 0x00 "GICC_RPR,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY      ,The current running priority on the CPU interface"
rgroup.long 0x0018++0x03
line.long 0x00 "GICC_HPIR,Highest Priority Pending Interrupt Register"
bitfld.long 0x00 10.--12. " CPUID         ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "                         PENDINTID     ,The interrupt ID of the highest priority pending interrupt"
if (((per.l(ad:0xFFFC1000+0x04))&0x400)==0x400)
group.long 0x001C++0x03
line.long 0x00 "GICC_ABPR,Aliased Binary Point Register"
bitfld.long 0x00 0.--2. " BINARY_POINT  ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
else
hgroup.long 0x001C++0x03
hide.long 0x00 "GICC_ABPR,Aliased Binary Point Register"
endif
hgroup.long 0x0020++0x003
hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register"
in
if (((per.l(ad:0xFFFC1000+0x04))&0x400)==0x400)
wgroup.long 0x0024++0x03
line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register"
bitfld.long 0x00 10.--12. " CPUID         ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "                         EOIINTID      ,The Interrupt ID value from the corresponding GICC_IAR access"
rgroup.long 0x0028++0x03
line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register"
bitfld.long 0x00 10.--12. " CPUID         ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "                         PENDINTID     ,The interrupt ID of the highest priority pending interrupt"
else
hgroup.long 0x0024++0x03
hide.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register"
hgroup.long 0x0028++0x03
hide.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register"
endif
group.long 0x00D0++0x03
line.long 0x00 "GICC_APR0,Active Priorities Register"
if (((per.l(ad:0xFFFC1000+0x04))&0x400)==0x400)
group.long 0x00E0++0x03
line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register"
else
hgroup.long 0x00E0++0x03
hide.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register"
endif
rgroup.long 0x00FC++0x03
line.long 0x00 "GICC_IIDR,CPU and Virtual CPU Interface Identification Register"
hexmask.long.word 0x00 20.--31. 1. " PRODID        ,Product ID"
bitfld.long 0x00 16.--19. "  ARCH_VER        ,Identifies the architecture version of the GIC" "GICv1,GICv1,GICv2,GICv2,?..."
textline "                     "
bitfld.long 0x00 12.--15. "      REV           ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "    IMP             ,Implementer"
wgroup.long 0x1000++0x03
line.long 0x00 "GICC_DIR,Deactivate Interrupt Register"
bitfld.long 0x00 10.--12. " CPUID         ,On a multiprocessor implementation this field identifies the processor that requested the interrupt" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "     INTID         ,The interrupt ID"
tree.end
sif CPU.FEATURE(hypervisor)
base ad:0xFFFC4000
width 12.
tree "Virtual CPU Control Interface"
group.long 0x0000++0x03
line.long 0x00 "GICH_HCR,Hypervisor Control Register"
bitfld.long 0x00 27.--31. " EOICOUNT  ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 7. "                    VGRP1DIE   ,VM Disable Group 1 Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "      VGRP1EIE  ,VM Enable Group 1 Interrupt Enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 5. " VGRP0DIE  ,VM Disable Group 0 Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "              VGRP0EIE   ,VM Disable Group 0 Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "      NPIE      ,No Pending Interrupt Enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 2. " LRENPIE   ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "              UIE        ,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "      EN        ,Enable" "Disabled,Enabled"
rgroup.long 0x0004++0x03
line.long 0x00 "GICH_VTR,VGIC Type Register"
bitfld.long 0x00 29.--31. " PRIBITS   ,Number of priority bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRI levels,?..."
textline "                     "
bitfld.long 0x00 26.--28. " PREBITS   ,Number of pre-emption bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRE levels,?..."
textline "                     "
bitfld.long 0x00 0.--5. " LISTREGS  ,List regs number" "Reserved,Reserved,Reserved,4 lists,?..."
group.long 0x008++0x03
line.long 0x00 "GICH_VMCR,Virtual Machine Control Register"
bitfld.long 0x00 27.--31. " VMPRIMASK ,Alias of GICV_PMR.Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 21.--23. "                    VMBP       ,Alias of GICV_BPR.Binary point" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "             VMABP     ,Alias of GICV_ABPR.Binary point" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 9. " VEM       ,Alias of GICV_CTLR.EOImode" "0,1"
bitfld.long 0x00 4. "                     VMCBPR     ,Alias of GICV_CTLR.CBPR" "0,1"
bitfld.long 0x00 3. "             VMFIQEN   ,Alias of GICV_CTLR.FIQEn" "0,1"
textline "                     "
bitfld.long 0x00 2. " VMACKCTL  ,Alias of GICV_CTLR.AckCtl" "0,1"
bitfld.long 0x00 1. "                     VMGRP1EN   ,Alias of GICV_CTLR.EnableGrp1" "0,1"
bitfld.long 0x00 0. "             VMGRP0EN  ,Alias of GICV_CTLR.EnableGrp0" "0,1"
rgroup.long 0x0010++0x03
line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register"
bitfld.long 0x00 7. " VGRP1D    ,Disabled Group 1 maintenance interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 6. "          VGRP1E     ,Enabled Group 1 maintenance interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 5. "  VGRP0D    ,Disabled Group 0 maintenance interrupt" "No interrupt,Interrupt"
textline "                     "
bitfld.long 0x00 4. " VGRP0E    ,Enabled Group 0 maintenance interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 3. "          NP         ,No Pending maintenance interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 2. "  LRENP     ,List Register Entry Not Present maintenance interrupt" "No interrupt,Interrupt"
textline "                     "
bitfld.long 0x00 1. " U         ,Underflow maintenance interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 0. "          EOI        ,EOI maintenance interrupt" "No interrupt,Interrupt"
rgroup.long 0x020++0x03
line.long 0x00 "GICH_EISR0,End of Interrupt Status Register"
bitfld.long 0x00 3. " STATUS3   ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "          STATUS2    ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "  STATUS1   ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt"
textline "                     "
bitfld.long 0x00 0. " STATUS0   ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt"
rgroup.long 0x0030++0x03
line.long 0x00 "GICH_ELSR0,Empty List register Status Register"
bitfld.long 0x00 3. " STATUS3   ,Emptiness status bit for List register 3" "Not empty,Empty"
bitfld.long 0x00 2. "             STATUS2    ,Emptiness status bit for List register 2" "Not empty,Empty"
bitfld.long 0x00 1. "     STATUS1   ,Emptiness status bit for List register 1" "Not empty,Empty"
textline "                     "
bitfld.long 0x00 0. " STATUS0   ,Emptiness status bit for List register 0" "Not empty,Empty"
group.long 0x00F0++0x03
line.long 0x00 "GICH_APR0,Active Priorities Register"
bitfld.long 0x00 31. " APB31     ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 30. "            APB30      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 29. "    APB29     ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 28. " APB28     ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 27. "            APB27      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 26. "    APB26     ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 25. " APB25     ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 24. "            APB24      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 23. "    APB23     ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 22. " APB22     ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 21. "            APB21      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 20. "    APB20     ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 19. " APB19     ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 18. "            APB18      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 17. "    APB17     ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 16. " APB16     ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 15. "            APB15      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 14. "    APB14     ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 13. " APB13     ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 12. "            APB12      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 11. "    APB11     ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 10. " APB10     ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 9. "            APB9       ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 8. "    APB8      ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 7. " APB7      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 6. "            APB6       ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 5. "    APB5      ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 4. " APB4      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 3. "            APB3       ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 2. "    APB2      ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 1. " APB1      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 0. "            APB0       ,Determines whether the corresponding preemption level is active" "Not active,Active"
if (((per.l(ad:0xFFFC4000+0x100))&0x80000000)==0x80000000)
group.long 0x100++0x03
line.long 0x00 "GICH_LR0,List Register 0"
bitfld.long 0x00 31. " HW        ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "              GRP1       ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "       STATE     ,The state of the interrupt" "Invalid,Pending,Active,Pending and active"
textline "                     "
bitfld.long 0x00 23.--27. " PRIORITY  ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "                    PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor"
hexmask.long.word 0x00 0.--9. 1. "          VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR"
else
group.long 0x100++0x03
line.long 0x00 "GICH_LR0,List Register 0"
bitfld.long 0x00 31. " HW        ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "              GRP1       ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "       STATE     ,The state of the interrupt" "Invalid,Pending,Active,Pending and active"
textline "                     "
bitfld.long 0x00 23.--27. " PRIORITY  ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 19. "                    EOI        ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted"
bitfld.long 0x00 10.--12. "  CPUID     ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7"
textline "                     "
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR"
endif
if (((per.l(ad:0xFFFC4000+0x104))&0x80000000)==0x80000000)
group.long 0x104++0x03
line.long 0x00 "GICH_LR1,List Register 1"
bitfld.long 0x00 31. " HW        ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "              GRP1       ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "       STATE     ,The state of the interrupt" "Invalid,Pending,Active,Pending and active"
textline "                     "
bitfld.long 0x00 23.--27. " PRIORITY  ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "                    PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor"
hexmask.long.word 0x00 0.--9. 1. "          VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR"
else
group.long 0x104++0x03
line.long 0x00 "GICH_LR1,List Register 1"
bitfld.long 0x00 31. " HW        ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "              GRP1       ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "       STATE     ,The state of the interrupt" "Invalid,Pending,Active,Pending and active"
textline "                     "
bitfld.long 0x00 23.--27. " PRIORITY  ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 19. "                    EOI        ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted"
bitfld.long 0x00 10.--12. "  CPUID     ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7"
textline "                     "
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR"
endif
if (((per.l(ad:0xFFFC4000+0x108))&0x80000000)==0x80000000)
group.long 0x108++0x03
line.long 0x00 "GICH_LR2,List Register 2"
bitfld.long 0x00 31. " HW        ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "              GRP1       ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "       STATE     ,The state of the interrupt" "Invalid,Pending,Active,Pending and active"
textline "                     "
bitfld.long 0x00 23.--27. " PRIORITY  ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "                    PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor"
hexmask.long.word 0x00 0.--9. 1. "          VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR"
else
group.long 0x108++0x03
line.long 0x00 "GICH_LR2,List Register 2"
bitfld.long 0x00 31. " HW        ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "              GRP1       ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "       STATE     ,The state of the interrupt" "Invalid,Pending,Active,Pending and active"
textline "                     "
bitfld.long 0x00 23.--27. " PRIORITY  ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 19. "                    EOI        ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted"
bitfld.long 0x00 10.--12. "  CPUID     ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7"
textline "                     "
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR"
endif
if (((per.l(ad:0xFFFC4000+0x10C))&0x80000000)==0x80000000)
group.long 0x10C++0x03
line.long 0x00 "GICH_LR3,List Register 3"
bitfld.long 0x00 31. " HW        ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "              GRP1       ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "       STATE     ,The state of the interrupt" "Invalid,Pending,Active,Pending and active"
textline "                     "
bitfld.long 0x00 23.--27. " PRIORITY  ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "                    PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor"
hexmask.long.word 0x00 0.--9. 1. "          VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR"
else
group.long 0x10C++0x03
line.long 0x00 "GICH_LR3,List Register 3"
bitfld.long 0x00 31. " HW        ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "              GRP1       ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "       STATE     ,The state of the interrupt" "Invalid,Pending,Active,Pending and active"
textline "                     "
bitfld.long 0x00 23.--27. " PRIORITY  ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 19. "                    EOI        ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted"
bitfld.long 0x00 10.--12. "  CPUID     ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7"
textline "                     "
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR"
endif
tree.end
base ad:0xFFFC6000
width 12.
tree "Virtual CPU Interface"
group.long 0x0000++0x03
line.long 0x00 "GICV_CTLR,Virtual Machine Control Register"
bitfld.long 0x00 9. " EOIMODE      ,Controls the behavior associated with the GICV_EOIR GICV_AEOIR and GICV_DIR registers" "Priority drop/Deactivate,Priority drop"
bitfld.long 0x00 4. "  CBPR       ,Controls whether the GICV_BPR controls both Group 0 and Group 1 virtual interrupts" "BPR/ABPR split,BPR common"
bitfld.long 0x00 3. "  FIQEN      ,Controls whether interrupts marked as Group 0 are presented as virtual FIQs" "IRQs,FIQs"
textline "                     "
bitfld.long 0x00 2. " ACKCTL       ,Acknowledge Control" "ID 1022 interrupt,Corresponding interrupt"
bitfld.long 0x00 1. "   ENABLEGRP1 ,Enables the signaling of Group 1 virtual interrupts by the virtual CPU interface to the virtual machine" "Disabled,Enabled"
bitfld.long 0x00 0. "        ENABLEGRP0 ,Enables the signaling of Group 0 virtual interrupts by the virtual CPU interface to the virtual machine" "Disabled,Enabled"
group.long 0x0004++0x03
line.long 0x00 "GICV_PMR,VM Priority Mask Register"
bitfld.long 0x00 3.--7. " PRIORITY     ,Priority mask level for CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x0008++0x03
line.long 0x00 "GICV_BPR,VM Binary Point Register"
bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
hgroup.long 0x000C++0x03
hide.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register"
in
wgroup.long 0x0010++0x03
line.long 0x00 "GICV_EOIR,VM End of Interrupt Register"
bitfld.long 0x00 10.--12. " CPUID        ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "                         EOIINTID   ,The Interrupt ID value from the corresponding GICC_IAR access"
rgroup.long 0x0014++0x03
line.long 0x00 "GICV_RPR,VM Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY     ,The current running priority on the Virtual CPU interface"
rgroup.long 0x0018++0x03
line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register"
bitfld.long 0x00 10.--12. " CPUID        ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "                         PENDINTID  ,The interrupt ID of the highest priority pending interrupt"
group.long 0x001C++0x03
line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register"
bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
hgroup.long 0x0020++0x03
hide.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register"
in
wgroup.long 0x0024++0x03
line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register"
bitfld.long 0x00 10.--12. " CPUID        ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "                         EOIINTID   ,The Interrupt ID value from the corresponding GICC_IAR access"
rgroup.long 0x0028++0x03
line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register"
bitfld.long 0x00 10.--12. " CPUID        ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "                         PENDINTID  ,The interrupt ID of the highest priority pending interrupt"
group.long 0x00D0++0x03
line.long 0x00 "GICV_APR0,VM Active Priority Register"
bitfld.long 0x00 31. " APB31        ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 30. "                APB30      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 29. "  APB29      ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 28. " APB28        ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 27. "                APB27      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 26. "  APB26      ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 25. " APB25        ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 24. "                APB24      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 23. "  APB23      ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 22. " APB22        ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 21. "                APB21      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 20. "  APB20      ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 19. " APB19        ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 18. "                APB18      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 17. "  APB17      ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 16. " APB16        ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 15. "                APB15      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 14. "  APB14      ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 13. " APB13        ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 12. "                APB12      ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 11. "  APB11      ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 10. " APB10        ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 9. "                APB9       ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 8. "  APB8       ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 7. " APB7         ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 6. "                APB6       ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 5. "  APB5       ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 4. " APB4         ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 3. "                APB3       ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 2. "  APB2       ,Determines whether the corresponding preemption level is active" "Not active,Active"
textline "                     "
bitfld.long 0x00 1. " APB1         ,Determines whether the corresponding preemption level is active" "Not active,Active"
bitfld.long 0x00 0. "                APB0       ,Determines whether the corresponding preemption level is active" "Not active,Active"
rgroup.long 0x00FC++0x03
line.long 0x00 "GICV_IIDR,VM CPU Interface Identification Register"
hexmask.long.word 0x00 20.--31. 1. " PRODID       ,Product ID"
bitfld.long 0x00 16.--19. "                      ARCH_VER   ,Identifies the architecture version of the GIC" "GICv1,GICv2,?..."
textline "                     "
bitfld.long 0x00 12.--15. " REV          ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "                        IMP        ,Implementer"
wgroup.long 0x1000++0x03
line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register"
bitfld.long 0x00 10.--12. " CPUID        ,On a multiprocessor implementation this field identifies the processor that requested the interrupt" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--9. 1. "                         INTID      ,The interrupt ID"
tree.end
endif
width 0x0B
tree.end
tree.end
tree "CCU (Cache Coherency Unit Register Bus)"
base ad:0x0
group.long 0xFFFFFFFFF7000000++0x3
line.long 0x0 "CAIUTCR,CAIU Transaction Control Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "IsolEn,Agent Isolation Enable" "0,1"
newline
bitfld.long 0x0 0. "TransEn,Agent Transaction Enable" "0,1"
rgroup.long 0xFFFFFFFFF7000004++0x3
line.long 0x0 "CAIUTAR,CAIU Transaction Activity Register"
hexmask.long 0x0 3.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 2. "CohActv,Coherent Transaction Active" "0,1"
newline
bitfld.long 0x0 1. "SnpActv,Snoop Transaction Active" "0,1"
newline
bitfld.long 0x0 0. "TransActv,Transaction Active" "0,1"
group.long 0xFFFFFFFFF7000008++0x3
line.long 0x0 "CAIUTTR,CAIU Transaction Throttle Register"
bitfld.long 0x0 31. "TransThrottleEn,Transaction table throttle feature enable" "0,1"
newline
bitfld.long 0x0 30. "TransThrottleMask,Transaction table throttle input mask" "0,1"
newline
hexmask.long.byte 0x0 24.--29. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "TransDelta,Transaction table delta"
newline
hexmask.long.byte 0x0 8.--15. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--7. 1. "TransLimit,Transaction table limit"
group.long 0xFFFFFFFFF7000100++0xF
line.long 0x0 "CAIUCECR,CAIU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Correctable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Correctable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Correctable Error Detection Enable" "0,1"
line.long 0x4 "CAIUCESR,CAIU Correctable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "CAIUCELR0,CAIU Correctable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
line.long 0xC "CAIUCELR1,CAIU Correctable Error Location Register 1"
hexmask.long.tbyte 0xC 12.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.word 0xC 0.--11. 1. "ErrAddr,Error Address"
group.long 0xFFFFFFFFF7000124++0x3
line.long 0x0 "CAIUCESAR,CAIU Correctable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF7000140++0xF
line.long 0x0 "CAIUUECR,CAIU Uncorrectable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Uncorrectable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Uncorrectable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Uncorrectable Error Detection Enable" "0,1"
line.long 0x4 "CAIUUESR,CAIU Uncorrectable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "CAIUUELR0,CAIU Uncorrectable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
line.long 0xC "CAIUUELR1,CAIU Uncorrectable Error Location Register 1"
hexmask.long.tbyte 0xC 12.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.word 0xC 0.--11. 1. "ErrAddr,Error Address"
group.long 0xFFFFFFFFF7000164++0x3
line.long 0x0 "CAIUUESAR,CAIU Uncorrectable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF7000F00++0x3
line.long 0x0 "CAIUDCR,CAIU Debug Control Register"
hexmask.long 0x0 4.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "DbgOp,Debug Operation"
rgroup.long 0xFFFFFFFFF7000F04++0x3
line.long 0x0 "CAIUDAR,CAIU Debug Activity Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "DbgOpFail,Debug Operation Failure" "0,1"
newline
bitfld.long 0x0 0. "DbgOpActv,Debug Operation Active" "0,1"
group.long 0xFFFFFFFFF7000F08++0x3
line.long 0x0 "CAIUDLR,CAIU Debug Location Register"
hexmask.long.byte 0x0 26.--31. 1. "DbgWord,Debug Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "DbgStruct,Debug Structure"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "DbgEntry,Debug Entry"
rgroup.long 0xFFFFFFFFF7000F10++0x3
line.long 0x0 "CAIUDDR,CAIU Debug Data Register"
hexmask.long 0x0 0.--31. 1. "DbgData,Debug Operation Data"
rgroup.long 0xFFFFFFFFF7000FFC++0x3
line.long 0x0 "CAIUIDR,CAIU Identification Register"
hexmask.long.byte 0x0 25.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 20.--24. 1. "SfId,Snoop Filter Identifier"
newline
hexmask.long.byte 0x0 16.--19. 1. "Type,Type"
newline
bitfld.long 0x0 15. "Ca,Caching Agent" "0,1"
newline
hexmask.long.byte 0x0 8.--14. 1. "CaiId,Coherent Agent Interface Identifier"
newline
hexmask.long.byte 0x0 0.--7. 1. "ImplVer,Implementation Version"
group.long 0xFFFFFFFFF7001000++0x3
line.long 0x0 "CAIUTCR,CAIU Transaction Control Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "IsolEn,Agent Isolation Enable" "0,1"
newline
bitfld.long 0x0 0. "TransEn,Agent Transaction Enable" "0,1"
rgroup.long 0xFFFFFFFFF7001004++0x3
line.long 0x0 "CAIUTAR,CAIU Transaction Activity Register"
hexmask.long 0x0 3.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 2. "CohActv,Coherent Transaction Active" "0,1"
newline
bitfld.long 0x0 1. "SnpActv,Snoop Transaction Active" "0,1"
newline
bitfld.long 0x0 0. "TransActv,Transaction Active" "0,1"
group.long 0xFFFFFFFFF7001008++0x3
line.long 0x0 "CAIUTTR,CAIU Transaction Throttle Register"
bitfld.long 0x0 31. "TransThrottleEn,Transaction table throttle feature enable" "0,1"
newline
bitfld.long 0x0 30. "TransThrottleMask,Transaction table throttle input mask" "0,1"
newline
hexmask.long.byte 0x0 24.--29. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "TransDelta,Transaction table delta"
newline
hexmask.long.byte 0x0 8.--15. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--7. 1. "TransLimit,Transaction table limit"
group.long 0xFFFFFFFFF7001100++0xF
line.long 0x0 "CAIUCECR,CAIU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Correctable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Correctable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Correctable Error Detection Enable" "0,1"
line.long 0x4 "CAIUCESR,CAIU Correctable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "CAIUCELR0,CAIU Correctable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
line.long 0xC "CAIUCELR1,CAIU Correctable Error Location Register 1"
hexmask.long.tbyte 0xC 12.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.word 0xC 0.--11. 1. "ErrAddr,Error Address"
group.long 0xFFFFFFFFF7001124++0x3
line.long 0x0 "CAIUCESAR,CAIU Correctable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF7001140++0xF
line.long 0x0 "CAIUUECR,CAIU Uncorrectable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Uncorrectable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Uncorrectable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Uncorrectable Error Detection Enable" "0,1"
line.long 0x4 "CAIUUESR,CAIU Uncorrectable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "CAIUUELR0,CAIU Uncorrectable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
line.long 0xC "CAIUUELR1,CAIU Uncorrectable Error Location Register 1"
hexmask.long.tbyte 0xC 12.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.word 0xC 0.--11. 1. "ErrAddr,Error Address"
group.long 0xFFFFFFFFF7001164++0x3
line.long 0x0 "CAIUUESAR,CAIU Uncorrectable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF7001F00++0x3
line.long 0x0 "CAIUDCR,CAIU Debug Control Register"
hexmask.long 0x0 4.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "DbgOp,Debug Operation"
rgroup.long 0xFFFFFFFFF7001F04++0x3
line.long 0x0 "CAIUDAR,CAIU Debug Activity Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "DbgOpFail,Debug Operation Failure" "0,1"
newline
bitfld.long 0x0 0. "DbgOpActv,Debug Operation Active" "0,1"
group.long 0xFFFFFFFFF7001F08++0x3
line.long 0x0 "CAIUDLR,CAIU Debug Location Register"
hexmask.long.byte 0x0 26.--31. 1. "DbgWord,Debug Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "DbgStruct,Debug Structure"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "DbgEntry,Debug Entry"
rgroup.long 0xFFFFFFFFF7001F10++0x3
line.long 0x0 "CAIUDDR,CAIU Debug Data Register"
hexmask.long 0x0 0.--31. 1. "DbgData,Debug Operation Data"
rgroup.long 0xFFFFFFFFF7001FFC++0x3
line.long 0x0 "CAIUIDR,CAIU Identification Register"
hexmask.long.byte 0x0 25.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 20.--24. 1. "SfId,Snoop Filter Identifier"
newline
hexmask.long.byte 0x0 16.--19. 1. "Type,Type"
newline
bitfld.long 0x0 15. "Ca,Caching Agent" "0,1"
newline
hexmask.long.byte 0x0 8.--14. 1. "CaiId,Coherent Agent Interface Identifier"
newline
hexmask.long.byte 0x0 0.--7. 1. "ImplVer,Implementation Version"
group.long 0xFFFFFFFFF7002000++0x3
line.long 0x0 "CAIUTCR,CAIU Transaction Control Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "IsolEn,Agent Isolation Enable" "0,1"
newline
bitfld.long 0x0 0. "TransEn,Agent Transaction Enable" "0,1"
rgroup.long 0xFFFFFFFFF7002004++0x3
line.long 0x0 "CAIUTAR,CAIU Transaction Activity Register"
hexmask.long 0x0 3.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 2. "CohActv,Coherent Transaction Active" "0,1"
newline
bitfld.long 0x0 1. "SnpActv,Snoop Transaction Active" "0,1"
newline
bitfld.long 0x0 0. "TransActv,Transaction Active" "0,1"
group.long 0xFFFFFFFFF7002008++0x3
line.long 0x0 "CAIUTTR,CAIU Transaction Throttle Register"
bitfld.long 0x0 31. "TransThrottleEn,Transaction table throttle feature enable" "0,1"
newline
bitfld.long 0x0 30. "TransThrottleMask,Transaction table throttle input mask" "0,1"
newline
hexmask.long.byte 0x0 24.--29. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "TransDelta,Transaction table delta"
newline
hexmask.long.byte 0x0 8.--15. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--7. 1. "TransLimit,Transaction table limit"
group.long 0xFFFFFFFFF7002100++0xF
line.long 0x0 "CAIUCECR,CAIU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Correctable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Correctable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Correctable Error Detection Enable" "0,1"
line.long 0x4 "CAIUCESR,CAIU Correctable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "CAIUCELR0,CAIU Correctable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
line.long 0xC "CAIUCELR1,CAIU Correctable Error Location Register 1"
hexmask.long.tbyte 0xC 12.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.word 0xC 0.--11. 1. "ErrAddr,Error Address"
group.long 0xFFFFFFFFF7002124++0x3
line.long 0x0 "CAIUCESAR,CAIU Correctable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF7002140++0xF
line.long 0x0 "CAIUUECR,CAIU Uncorrectable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Uncorrectable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Uncorrectable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Uncorrectable Error Detection Enable" "0,1"
line.long 0x4 "CAIUUESR,CAIU Uncorrectable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "CAIUUELR0,CAIU Uncorrectable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
line.long 0xC "CAIUUELR1,CAIU Uncorrectable Error Location Register 1"
hexmask.long.tbyte 0xC 12.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.word 0xC 0.--11. 1. "ErrAddr,Error Address"
group.long 0xFFFFFFFFF7002164++0x3
line.long 0x0 "CAIUUESAR,CAIU Uncorrectable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF7002F00++0x3
line.long 0x0 "CAIUDCR,CAIU Debug Control Register"
hexmask.long 0x0 4.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "DbgOp,Debug Operation"
rgroup.long 0xFFFFFFFFF7002F04++0x3
line.long 0x0 "CAIUDAR,CAIU Debug Activity Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "DbgOpFail,Debug Operation Failure" "0,1"
newline
bitfld.long 0x0 0. "DbgOpActv,Debug Operation Active" "0,1"
group.long 0xFFFFFFFFF7002F08++0x3
line.long 0x0 "CAIUDLR,CAIU Debug Location Register"
hexmask.long.byte 0x0 26.--31. 1. "DbgWord,Debug Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "DbgStruct,Debug Structure"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "DbgEntry,Debug Entry"
rgroup.long 0xFFFFFFFFF7002F10++0x3
line.long 0x0 "CAIUDDR,CAIU Debug Data Register"
hexmask.long 0x0 0.--31. 1. "DbgData,Debug Operation Data"
rgroup.long 0xFFFFFFFFF7002FFC++0x3
line.long 0x0 "CAIUIDR,CAIU Identification Register"
hexmask.long.byte 0x0 25.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 20.--24. 1. "SfId,Snoop Filter Identifier"
newline
hexmask.long.byte 0x0 16.--19. 1. "Type,Type"
newline
bitfld.long 0x0 15. "Ca,Caching Agent" "0,1"
newline
hexmask.long.byte 0x0 8.--14. 1. "CaiId,Coherent Agent Interface Identifier"
newline
hexmask.long.byte 0x0 0.--7. 1. "ImplVer,Implementation Version"
group.long 0xFFFFFFFFF7003000++0x3
line.long 0x0 "CAIUTCR,CAIU Transaction Control Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "IsolEn,Agent Isolation Enable" "0,1"
newline
bitfld.long 0x0 0. "TransEn,Agent Transaction Enable" "0,1"
rgroup.long 0xFFFFFFFFF7003004++0x3
line.long 0x0 "CAIUTAR,CAIU Transaction Activity Register"
hexmask.long 0x0 3.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 2. "CohActv,Coherent Transaction Active" "0,1"
newline
bitfld.long 0x0 1. "SnpActv,Snoop Transaction Active" "0,1"
newline
bitfld.long 0x0 0. "TransActv,Transaction Active" "0,1"
group.long 0xFFFFFFFFF7003008++0x3
line.long 0x0 "CAIUTTR,CAIU Transaction Throttle Register"
bitfld.long 0x0 31. "TransThrottleEn,Transaction table throttle feature enable" "0,1"
newline
bitfld.long 0x0 30. "TransThrottleMask,Transaction table throttle input mask" "0,1"
newline
hexmask.long.byte 0x0 24.--29. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "TransDelta,Transaction table delta"
newline
hexmask.long.byte 0x0 8.--15. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--7. 1. "TransLimit,Transaction table limit"
group.long 0xFFFFFFFFF7003100++0xF
line.long 0x0 "CAIUCECR,CAIU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Correctable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Correctable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Correctable Error Detection Enable" "0,1"
line.long 0x4 "CAIUCESR,CAIU Correctable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "CAIUCELR0,CAIU Correctable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
line.long 0xC "CAIUCELR1,CAIU Correctable Error Location Register 1"
hexmask.long.tbyte 0xC 12.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.word 0xC 0.--11. 1. "ErrAddr,Error Address"
group.long 0xFFFFFFFFF7003124++0x3
line.long 0x0 "CAIUCESAR,CAIU Correctable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF7003140++0xF
line.long 0x0 "CAIUUECR,CAIU Uncorrectable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Uncorrectable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Uncorrectable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Uncorrectable Error Detection Enable" "0,1"
line.long 0x4 "CAIUUESR,CAIU Uncorrectable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "CAIUUELR0,CAIU Uncorrectable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
line.long 0xC "CAIUUELR1,CAIU Uncorrectable Error Location Register 1"
hexmask.long.tbyte 0xC 12.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.word 0xC 0.--11. 1. "ErrAddr,Error Address"
group.long 0xFFFFFFFFF7003164++0x3
line.long 0x0 "CAIUUESAR,CAIU Uncorrectable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF7003F00++0x3
line.long 0x0 "CAIUDCR,CAIU Debug Control Register"
hexmask.long 0x0 4.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "DbgOp,Debug Operation"
rgroup.long 0xFFFFFFFFF7003F04++0x3
line.long 0x0 "CAIUDAR,CAIU Debug Activity Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "DbgOpFail,Debug Operation Failure" "0,1"
newline
bitfld.long 0x0 0. "DbgOpActv,Debug Operation Active" "0,1"
group.long 0xFFFFFFFFF7003F08++0x3
line.long 0x0 "CAIUDLR,CAIU Debug Location Register"
hexmask.long.byte 0x0 26.--31. 1. "DbgWord,Debug Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "DbgStruct,Debug Structure"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "DbgEntry,Debug Entry"
rgroup.long 0xFFFFFFFFF7003F10++0x3
line.long 0x0 "CAIUDDR,CAIU Debug Data Register"
hexmask.long 0x0 0.--31. 1. "DbgData,Debug Operation Data"
rgroup.long 0xFFFFFFFFF7003FFC++0x3
line.long 0x0 "CAIUIDR,CAIU Identification Register"
hexmask.long.byte 0x0 25.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 20.--24. 1. "SfId,Snoop Filter Identifier"
newline
hexmask.long.byte 0x0 16.--19. 1. "Type,Type"
newline
bitfld.long 0x0 15. "Ca,Caching Agent" "0,1"
newline
hexmask.long.byte 0x0 8.--14. 1. "CaiId,Coherent Agent Interface Identifier"
newline
hexmask.long.byte 0x0 0.--7. 1. "ImplVer,Implementation Version"
rgroup.long 0xFFFFFFFFF7080004++0x3
line.long 0x0 "DIRUTAR,DIRU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 0. "TransActv,Transaction Active" "0,1"
group.long 0xFFFFFFFFF7080010++0x3
line.long 0x0 "DIRUSFER,DIRU Snoop Filtering Enable Register"
hexmask.long 0x0 1.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
bitfld.long 0x0 0. "SfEn,Snoop Filter Enable" "0,1"
group.long 0xFFFFFFFFF7080040++0x3
line.long 0x0 "DIRUCASER0,DIRU Caching Agent Snoop Enable Register 0"
hexmask.long 0x0 4.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "CaSnpEn,Caching Agent Snoop Enable"
rgroup.long 0xFFFFFFFFF7080050++0x3
line.long 0x0 "DIRUCASAR0,DIRU Caching Agent Snoop Activity Register 0"
hexmask.long 0x0 4.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "CaSnpActv,Caching Agent Snoop Active"
group.long 0xFFFFFFFFF7080080++0x3
line.long 0x0 "DIRUSFMCR,DIRU Snoop Filter Maintenance Control Register"
hexmask.long.word 0x0 22.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 21. "SfSecAttr,Snoop Filter Security Attribute" "0,1"
newline
hexmask.long.byte 0x0 16.--20. 1. "SfId,Snoop Filter Identifier"
newline
hexmask.long.word 0x0 4.--15. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "SfMntOp,Snoop Filter Maintenance Operation"
rgroup.long 0xFFFFFFFFF7080084++0x3
line.long 0x0 "DIRUSFMAR,DIRU Snoop Filter Maintenance Activity Register"
hexmask.long 0x0 1.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 0. "MntOpActv,Maintenance Operation Active" "0,1"
group.long 0xFFFFFFFFF7080088++0x3
line.long 0x0 "DIRUSFMLR0,DIRU Snoop Filter Maintenance Location Register 0"
hexmask.long.byte 0x0 26.--31. 1. "MntWord,Maintenance Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "MntWay,Maintenance Way"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "MntSet,Maintenance Set"
group.long 0xFFFFFFFFF7080090++0x3
line.long 0x0 "DIRUSFMDR,DIRU Snoop Filter Maintenance Data Register"
hexmask.long 0x0 0.--31. 1. "MntData,Maintenance Operation Data"
group.long 0xFFFFFFFFF7080100++0xF
line.long 0x0 "DIRUCECR,DIRU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Correctable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Correctable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Correctable Error Detection Enable" "0,1"
line.long 0x4 "DIRUCESR,DIRU Correctable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "DIRUCELR0,DIRU Correctable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
line.long 0xC "DIRUCELR1,DIRU Correctable Error Location Register 1"
hexmask.long.tbyte 0xC 12.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.word 0xC 0.--11. 1. "ErrAddr,Error Address"
group.long 0xFFFFFFFFF7080124++0x3
line.long 0x0 "DIRUCESAR,DIRU Correctable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF7080140++0xF
line.long 0x0 "DIRUUECR,DIRU Uncorrectable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Uncorrectable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Uncorrectable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Uncorrectable Error Detection Enable" "0,1"
line.long 0x4 "DIRUUESR,DIRU Uncorrectable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "DIRUUELR0,DIRU Uncorrectable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
line.long 0xC "DIRUUELR1,DIRU Uncorrectable Error Location Register 1"
hexmask.long.tbyte 0xC 12.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.word 0xC 0.--11. 1. "ErrAddr,Error Address"
group.long 0xFFFFFFFFF7080164++0x3
line.long 0x0 "DIRUUESAR,DIRU Uncorrectable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF7080F00++0x3
line.long 0x0 "DIRUDCR,DIRU Debug Control Register"
hexmask.long 0x0 4.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "DbgOp,Debug Operation"
rgroup.long 0xFFFFFFFFF7080F04++0x3
line.long 0x0 "DIRUDAR,DIRU Debug Activity Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "DbgOpFail,Debug Operation Failure" "0,1"
newline
bitfld.long 0x0 0. "DbgOpActv,Debug Operation Active" "0,1"
group.long 0xFFFFFFFFF7080F08++0x3
line.long 0x0 "DIRUDLR,DIRU Debug Location Register"
hexmask.long.byte 0x0 26.--31. 1. "DbgWord,Debug Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "DbgStruct,Debug Structure"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "DbgEntry,Debug Entry"
rgroup.long 0xFFFFFFFFF7080F10++0x3
line.long 0x0 "DIRUDDR,DIRU Debug Data Register"
hexmask.long 0x0 0.--31. 1. "DbgData,Debug Operation Data"
rgroup.long 0xFFFFFFFFF7080FFC++0x3
line.long 0x0 "DIRUIDR,DIRU Identification Register"
hexmask.long.tbyte 0x0 8.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--7. 1. "ImplVer,Implementation Version"
rgroup.long 0xFFFFFFFFF7081004++0x3
line.long 0x0 "DIRUTAR,DIRU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 0. "TransActv,Transaction Active" "0,1"
group.long 0xFFFFFFFFF7081010++0x3
line.long 0x0 "DIRUSFER,DIRU Snoop Filtering Enable Register"
hexmask.long 0x0 1.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
bitfld.long 0x0 0. "SfEn,Snoop Filter Enable" "0,1"
group.long 0xFFFFFFFFF7081040++0x3
line.long 0x0 "DIRUCASER0,DIRU Caching Agent Snoop Enable Register 0"
hexmask.long 0x0 4.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "CaSnpEn,Caching Agent Snoop Enable"
rgroup.long 0xFFFFFFFFF7081050++0x3
line.long 0x0 "DIRUCASAR0,DIRU Caching Agent Snoop Activity Register 0"
hexmask.long 0x0 4.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "CaSnpActv,Caching Agent Snoop Active"
group.long 0xFFFFFFFFF7081080++0x3
line.long 0x0 "DIRUSFMCR,DIRU Snoop Filter Maintenance Control Register"
hexmask.long.word 0x0 22.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 21. "SfSecAttr,Snoop Filter Security Attribute" "0,1"
newline
hexmask.long.byte 0x0 16.--20. 1. "SfId,Snoop Filter Identifier"
newline
hexmask.long.word 0x0 4.--15. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "SfMntOp,Snoop Filter Maintenance Operation"
rgroup.long 0xFFFFFFFFF7081084++0x3
line.long 0x0 "DIRUSFMAR,DIRU Snoop Filter Maintenance Activity Register"
hexmask.long 0x0 1.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 0. "MntOpActv,Maintenance Operation Active" "0,1"
group.long 0xFFFFFFFFF7081088++0x3
line.long 0x0 "DIRUSFMLR0,DIRU Snoop Filter Maintenance Location Register 0"
hexmask.long.byte 0x0 26.--31. 1. "MntWord,Maintenance Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "MntWay,Maintenance Way"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "MntSet,Maintenance Set"
group.long 0xFFFFFFFFF7081090++0x3
line.long 0x0 "DIRUSFMDR,DIRU Snoop Filter Maintenance Data Register"
hexmask.long 0x0 0.--31. 1. "MntData,Maintenance Operation Data"
group.long 0xFFFFFFFFF7081100++0xF
line.long 0x0 "DIRUCECR,DIRU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Correctable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Correctable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Correctable Error Detection Enable" "0,1"
line.long 0x4 "DIRUCESR,DIRU Correctable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "DIRUCELR0,DIRU Correctable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
line.long 0xC "DIRUCELR1,DIRU Correctable Error Location Register 1"
hexmask.long.tbyte 0xC 12.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.word 0xC 0.--11. 1. "ErrAddr,Error Address"
group.long 0xFFFFFFFFF7081124++0x3
line.long 0x0 "DIRUCESAR,DIRU Correctable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF7081140++0xF
line.long 0x0 "DIRUUECR,DIRU Uncorrectable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Uncorrectable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Uncorrectable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Uncorrectable Error Detection Enable" "0,1"
line.long 0x4 "DIRUUESR,DIRU Uncorrectable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "DIRUUELR0,DIRU Uncorrectable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
line.long 0xC "DIRUUELR1,DIRU Uncorrectable Error Location Register 1"
hexmask.long.tbyte 0xC 12.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.word 0xC 0.--11. 1. "ErrAddr,Error Address"
group.long 0xFFFFFFFFF7081164++0x3
line.long 0x0 "DIRUUESAR,DIRU Uncorrectable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF7081F00++0x3
line.long 0x0 "DIRUDCR,DIRU Debug Control Register"
hexmask.long 0x0 4.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "DbgOp,Debug Operation"
rgroup.long 0xFFFFFFFFF7081F04++0x3
line.long 0x0 "DIRUDAR,DIRU Debug Activity Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "DbgOpFail,Debug Operation Failure" "0,1"
newline
bitfld.long 0x0 0. "DbgOpActv,Debug Operation Active" "0,1"
group.long 0xFFFFFFFFF7081F08++0x3
line.long 0x0 "DIRUDLR,DIRU Debug Location Register"
hexmask.long.byte 0x0 26.--31. 1. "DbgWord,Debug Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "DbgStruct,Debug Structure"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "DbgEntry,Debug Entry"
rgroup.long 0xFFFFFFFFF7081F10++0x3
line.long 0x0 "DIRUDDR,DIRU Debug Data Register"
hexmask.long 0x0 0.--31. 1. "DbgData,Debug Operation Data"
rgroup.long 0xFFFFFFFFF7081FFC++0x3
line.long 0x0 "DIRUIDR,DIRU Identification Register"
hexmask.long.tbyte 0x0 8.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--7. 1. "ImplVer,Implementation Version"
rgroup.long 0xFFFFFFFFF7082004++0x3
line.long 0x0 "DIRUTAR,DIRU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 0. "TransActv,Transaction Active" "0,1"
group.long 0xFFFFFFFFF7082010++0x3
line.long 0x0 "DIRUSFER,DIRU Snoop Filtering Enable Register"
hexmask.long 0x0 1.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
bitfld.long 0x0 0. "SfEn,Snoop Filter Enable" "0,1"
group.long 0xFFFFFFFFF7082040++0x3
line.long 0x0 "DIRUCASER0,DIRU Caching Agent Snoop Enable Register 0"
hexmask.long 0x0 4.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "CaSnpEn,Caching Agent Snoop Enable"
rgroup.long 0xFFFFFFFFF7082050++0x3
line.long 0x0 "DIRUCASAR0,DIRU Caching Agent Snoop Activity Register 0"
hexmask.long 0x0 4.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "CaSnpActv,Caching Agent Snoop Active"
group.long 0xFFFFFFFFF7082080++0x3
line.long 0x0 "DIRUSFMCR,DIRU Snoop Filter Maintenance Control Register"
hexmask.long.word 0x0 22.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 21. "SfSecAttr,Snoop Filter Security Attribute" "0,1"
newline
hexmask.long.byte 0x0 16.--20. 1. "SfId,Snoop Filter Identifier"
newline
hexmask.long.word 0x0 4.--15. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "SfMntOp,Snoop Filter Maintenance Operation"
rgroup.long 0xFFFFFFFFF7082084++0x3
line.long 0x0 "DIRUSFMAR,DIRU Snoop Filter Maintenance Activity Register"
hexmask.long 0x0 1.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 0. "MntOpActv,Maintenance Operation Active" "0,1"
group.long 0xFFFFFFFFF7082088++0x3
line.long 0x0 "DIRUSFMLR0,DIRU Snoop Filter Maintenance Location Register 0"
hexmask.long.byte 0x0 26.--31. 1. "MntWord,Maintenance Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "MntWay,Maintenance Way"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "MntSet,Maintenance Set"
group.long 0xFFFFFFFFF7082090++0x3
line.long 0x0 "DIRUSFMDR,DIRU Snoop Filter Maintenance Data Register"
hexmask.long 0x0 0.--31. 1. "MntData,Maintenance Operation Data"
group.long 0xFFFFFFFFF7082100++0xF
line.long 0x0 "DIRUCECR,DIRU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Correctable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Correctable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Correctable Error Detection Enable" "0,1"
line.long 0x4 "DIRUCESR,DIRU Correctable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "DIRUCELR0,DIRU Correctable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
line.long 0xC "DIRUCELR1,DIRU Correctable Error Location Register 1"
hexmask.long.tbyte 0xC 12.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.word 0xC 0.--11. 1. "ErrAddr,Error Address"
group.long 0xFFFFFFFFF7082124++0x3
line.long 0x0 "DIRUCESAR,DIRU Correctable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF7082140++0xF
line.long 0x0 "DIRUUECR,DIRU Uncorrectable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Uncorrectable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Uncorrectable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Uncorrectable Error Detection Enable" "0,1"
line.long 0x4 "DIRUUESR,DIRU Uncorrectable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "DIRUUELR0,DIRU Uncorrectable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
line.long 0xC "DIRUUELR1,DIRU Uncorrectable Error Location Register 1"
hexmask.long.tbyte 0xC 12.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.word 0xC 0.--11. 1. "ErrAddr,Error Address"
group.long 0xFFFFFFFFF7082164++0x3
line.long 0x0 "DIRUUESAR,DIRU Uncorrectable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF7082F00++0x3
line.long 0x0 "DIRUDCR,DIRU Debug Control Register"
hexmask.long 0x0 4.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "DbgOp,Debug Operation"
rgroup.long 0xFFFFFFFFF7082F04++0x3
line.long 0x0 "DIRUDAR,DIRU Debug Activity Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "DbgOpFail,Debug Operation Failure" "0,1"
newline
bitfld.long 0x0 0. "DbgOpActv,Debug Operation Active" "0,1"
group.long 0xFFFFFFFFF7082F08++0x3
line.long 0x0 "DIRUDLR,DIRU Debug Location Register"
hexmask.long.byte 0x0 26.--31. 1. "DbgWord,Debug Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "DbgStruct,Debug Structure"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "DbgEntry,Debug Entry"
rgroup.long 0xFFFFFFFFF7082F10++0x3
line.long 0x0 "DIRUDDR,DIRU Debug Data Register"
hexmask.long 0x0 0.--31. 1. "DbgData,Debug Operation Data"
rgroup.long 0xFFFFFFFFF7082FFC++0x3
line.long 0x0 "DIRUIDR,DIRU Identification Register"
hexmask.long.tbyte 0x0 8.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--7. 1. "ImplVer,Implementation Version"
rgroup.long 0xFFFFFFFFF7083004++0x3
line.long 0x0 "DIRUTAR,DIRU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 0. "TransActv,Transaction Active" "0,1"
group.long 0xFFFFFFFFF7083010++0x3
line.long 0x0 "DIRUSFER,DIRU Snoop Filtering Enable Register"
hexmask.long 0x0 1.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
bitfld.long 0x0 0. "SfEn,Snoop Filter Enable" "0,1"
group.long 0xFFFFFFFFF7083040++0x3
line.long 0x0 "DIRUCASER0,DIRU Caching Agent Snoop Enable Register 0"
hexmask.long 0x0 4.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "CaSnpEn,Caching Agent Snoop Enable"
rgroup.long 0xFFFFFFFFF7083050++0x3
line.long 0x0 "DIRUCASAR0,DIRU Caching Agent Snoop Activity Register 0"
hexmask.long 0x0 4.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "CaSnpActv,Caching Agent Snoop Active"
group.long 0xFFFFFFFFF7083080++0x3
line.long 0x0 "DIRUSFMCR,DIRU Snoop Filter Maintenance Control Register"
hexmask.long.word 0x0 22.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 21. "SfSecAttr,Snoop Filter Security Attribute" "0,1"
newline
hexmask.long.byte 0x0 16.--20. 1. "SfId,Snoop Filter Identifier"
newline
hexmask.long.word 0x0 4.--15. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "SfMntOp,Snoop Filter Maintenance Operation"
rgroup.long 0xFFFFFFFFF7083084++0x3
line.long 0x0 "DIRUSFMAR,DIRU Snoop Filter Maintenance Activity Register"
hexmask.long 0x0 1.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 0. "MntOpActv,Maintenance Operation Active" "0,1"
group.long 0xFFFFFFFFF7083088++0x3
line.long 0x0 "DIRUSFMLR0,DIRU Snoop Filter Maintenance Location Register 0"
hexmask.long.byte 0x0 26.--31. 1. "MntWord,Maintenance Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "MntWay,Maintenance Way"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "MntSet,Maintenance Set"
group.long 0xFFFFFFFFF7083090++0x3
line.long 0x0 "DIRUSFMDR,DIRU Snoop Filter Maintenance Data Register"
hexmask.long 0x0 0.--31. 1. "MntData,Maintenance Operation Data"
group.long 0xFFFFFFFFF7083100++0xF
line.long 0x0 "DIRUCECR,DIRU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Correctable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Correctable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Correctable Error Detection Enable" "0,1"
line.long 0x4 "DIRUCESR,DIRU Correctable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "DIRUCELR0,DIRU Correctable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
line.long 0xC "DIRUCELR1,DIRU Correctable Error Location Register 1"
hexmask.long.tbyte 0xC 12.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.word 0xC 0.--11. 1. "ErrAddr,Error Address"
group.long 0xFFFFFFFFF7083124++0x3
line.long 0x0 "DIRUCESAR,DIRU Correctable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF7083140++0xF
line.long 0x0 "DIRUUECR,DIRU Uncorrectable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Uncorrectable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Uncorrectable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Uncorrectable Error Detection Enable" "0,1"
line.long 0x4 "DIRUUESR,DIRU Uncorrectable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "DIRUUELR0,DIRU Uncorrectable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
line.long 0xC "DIRUUELR1,DIRU Uncorrectable Error Location Register 1"
hexmask.long.tbyte 0xC 12.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.word 0xC 0.--11. 1. "ErrAddr,Error Address"
group.long 0xFFFFFFFFF7083164++0x3
line.long 0x0 "DIRUUESAR,DIRU Uncorrectable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF7083F00++0x3
line.long 0x0 "DIRUDCR,DIRU Debug Control Register"
hexmask.long 0x0 4.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "DbgOp,Debug Operation"
rgroup.long 0xFFFFFFFFF7083F04++0x3
line.long 0x0 "DIRUDAR,DIRU Debug Activity Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "DbgOpFail,Debug Operation Failure" "0,1"
newline
bitfld.long 0x0 0. "DbgOpActv,Debug Operation Active" "0,1"
group.long 0xFFFFFFFFF7083F08++0x3
line.long 0x0 "DIRUDLR,DIRU Debug Location Register"
hexmask.long.byte 0x0 26.--31. 1. "DbgWord,Debug Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "DbgStruct,Debug Structure"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "DbgEntry,Debug Entry"
rgroup.long 0xFFFFFFFFF7083F10++0x3
line.long 0x0 "DIRUDDR,DIRU Debug Data Register"
hexmask.long 0x0 0.--31. 1. "DbgData,Debug Operation Data"
rgroup.long 0xFFFFFFFFF7083FFC++0x3
line.long 0x0 "DIRUIDR,DIRU Identification Register"
hexmask.long.tbyte 0x0 8.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--7. 1. "ImplVer,Implementation Version"
rgroup.long 0xFFFFFFFFF70C0004++0x3
line.long 0x0 "CMIUTAR,CMIU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 0. "TransActv,Transaction Active" "0,1"
group.long 0xFFFFFFFFF70C0100++0xB
line.long 0x0 "CMIUCECR,CMIU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Correctable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Correctable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Correctable Error Detection Enable" "0,1"
line.long 0x4 "CMIUCESR,CMIU Correctable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "CMIUCELR0,CMIU Correctable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
group.long 0xFFFFFFFFF70C0124++0x3
line.long 0x0 "CMIUCESAR,CMIU Correctable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF70C0F00++0x3
line.long 0x0 "CMIUDCR,CMIU Debug Control Register"
hexmask.long 0x0 4.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "DbgOp,Debug Operation"
rgroup.long 0xFFFFFFFFF70C0F04++0x3
line.long 0x0 "CMIUDAR,CMIU Debug Activity Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "DbgOpFail,Debug Operation Failure" "0,1"
newline
bitfld.long 0x0 0. "DbgOpActv,Debug Operation Active" "0,1"
group.long 0xFFFFFFFFF70C0F08++0x3
line.long 0x0 "CMIUDLR,CMIU Debug Location Register"
hexmask.long.byte 0x0 26.--31. 1. "DbgWord,Debug Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "DbgStruct,Debug Structure"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "DbgEntry,Debug Entry"
rgroup.long 0xFFFFFFFFF70C0F10++0x3
line.long 0x0 "CMIUDDR,CMIU Debug Data Register"
hexmask.long 0x0 0.--31. 1. "DbgData,Debug Operation Data"
rgroup.long 0xFFFFFFFFF70C0FF8++0x7
line.long 0x0 "CMIUCMCIDR,CMIU Coherent Memory Cache Identification Register"
bitfld.long 0x0 29.--31. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 26.--28. "Type,Coherent Memory Cache Type" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 20.--25. 1. "NumWays,Number of Coherent Memory Cache Ways"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "NumSets,Number of Coherent Memory Cache Sets"
line.long 0x4 "CMIUIDR,CMIU Identification Register"
bitfld.long 0x4 31. "Cmc,Coherent Memory Cache" "0,1"
newline
hexmask.long.tbyte 0x4 14.--30. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x4 13. "HntCap,Hint Capable" "0,1"
newline
hexmask.long.byte 0x4 8.--12. 1. "CmiId,Coherent Memory Interface Identifier"
newline
hexmask.long.byte 0x4 0.--7. 1. "ImplVer,Implementation Version"
rgroup.long 0xFFFFFFFFF70C1004++0x3
line.long 0x0 "CMIUTAR,CMIU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 0. "TransActv,Transaction Active" "0,1"
group.long 0xFFFFFFFFF70C1100++0xB
line.long 0x0 "CMIUCECR,CMIU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Correctable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Correctable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Correctable Error Detection Enable" "0,1"
line.long 0x4 "CMIUCESR,CMIU Correctable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "CMIUCELR0,CMIU Correctable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
group.long 0xFFFFFFFFF70C1124++0x3
line.long 0x0 "CMIUCESAR,CMIU Correctable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF70C1F00++0x3
line.long 0x0 "CMIUDCR,CMIU Debug Control Register"
hexmask.long 0x0 4.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "DbgOp,Debug Operation"
rgroup.long 0xFFFFFFFFF70C1F04++0x3
line.long 0x0 "CMIUDAR,CMIU Debug Activity Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "DbgOpFail,Debug Operation Failure" "0,1"
newline
bitfld.long 0x0 0. "DbgOpActv,Debug Operation Active" "0,1"
group.long 0xFFFFFFFFF70C1F08++0x3
line.long 0x0 "CMIUDLR,CMIU Debug Location Register"
hexmask.long.byte 0x0 26.--31. 1. "DbgWord,Debug Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "DbgStruct,Debug Structure"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "DbgEntry,Debug Entry"
rgroup.long 0xFFFFFFFFF70C1F10++0x3
line.long 0x0 "CMIUDDR,CMIU Debug Data Register"
hexmask.long 0x0 0.--31. 1. "DbgData,Debug Operation Data"
rgroup.long 0xFFFFFFFFF70C1FF8++0x7
line.long 0x0 "CMIUCMCIDR,CMIU Coherent Memory Cache Identification Register"
bitfld.long 0x0 29.--31. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 26.--28. "Type,Coherent Memory Cache Type" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 20.--25. 1. "NumWays,Number of Coherent Memory Cache Ways"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "NumSets,Number of Coherent Memory Cache Sets"
line.long 0x4 "CMIUIDR,CMIU Identification Register"
bitfld.long 0x4 31. "Cmc,Coherent Memory Cache" "0,1"
newline
hexmask.long.tbyte 0x4 14.--30. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x4 13. "HntCap,Hint Capable" "0,1"
newline
hexmask.long.byte 0x4 8.--12. 1. "CmiId,Coherent Memory Interface Identifier"
newline
hexmask.long.byte 0x4 0.--7. 1. "ImplVer,Implementation Version"
rgroup.long 0xFFFFFFFFF70C2004++0x3
line.long 0x0 "CMIUTAR,CMIU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 0. "TransActv,Transaction Active" "0,1"
group.long 0xFFFFFFFFF70C2100++0xB
line.long 0x0 "CMIUCECR,CMIU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Correctable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Correctable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Correctable Error Detection Enable" "0,1"
line.long 0x4 "CMIUCESR,CMIU Correctable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "CMIUCELR0,CMIU Correctable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
group.long 0xFFFFFFFFF70C2124++0x3
line.long 0x0 "CMIUCESAR,CMIU Correctable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF70C2F00++0x3
line.long 0x0 "CMIUDCR,CMIU Debug Control Register"
hexmask.long 0x0 4.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "DbgOp,Debug Operation"
rgroup.long 0xFFFFFFFFF70C2F04++0x3
line.long 0x0 "CMIUDAR,CMIU Debug Activity Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "DbgOpFail,Debug Operation Failure" "0,1"
newline
bitfld.long 0x0 0. "DbgOpActv,Debug Operation Active" "0,1"
group.long 0xFFFFFFFFF70C2F08++0x3
line.long 0x0 "CMIUDLR,CMIU Debug Location Register"
hexmask.long.byte 0x0 26.--31. 1. "DbgWord,Debug Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "DbgStruct,Debug Structure"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "DbgEntry,Debug Entry"
rgroup.long 0xFFFFFFFFF70C2F10++0x3
line.long 0x0 "CMIUDDR,CMIU Debug Data Register"
hexmask.long 0x0 0.--31. 1. "DbgData,Debug Operation Data"
rgroup.long 0xFFFFFFFFF70C2FF8++0x7
line.long 0x0 "CMIUCMCIDR,CMIU Coherent Memory Cache Identification Register"
bitfld.long 0x0 29.--31. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 26.--28. "Type,Coherent Memory Cache Type" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 20.--25. 1. "NumWays,Number of Coherent Memory Cache Ways"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "NumSets,Number of Coherent Memory Cache Sets"
line.long 0x4 "CMIUIDR,CMIU Identification Register"
bitfld.long 0x4 31. "Cmc,Coherent Memory Cache" "0,1"
newline
hexmask.long.tbyte 0x4 14.--30. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x4 13. "HntCap,Hint Capable" "0,1"
newline
hexmask.long.byte 0x4 8.--12. 1. "CmiId,Coherent Memory Interface Identifier"
newline
hexmask.long.byte 0x4 0.--7. 1. "ImplVer,Implementation Version"
rgroup.long 0xFFFFFFFFF70C3004++0x3
line.long 0x0 "CMIUTAR,CMIU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 0. "TransActv,Transaction Active" "0,1"
group.long 0xFFFFFFFFF70C3100++0xB
line.long 0x0 "CMIUCECR,CMIU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Correctable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Correctable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Correctable Error Detection Enable" "0,1"
line.long 0x4 "CMIUCESR,CMIU Correctable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "CMIUCELR0,CMIU Correctable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
group.long 0xFFFFFFFFF70C3124++0x3
line.long 0x0 "CMIUCESAR,CMIU Correctable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF70C3F00++0x3
line.long 0x0 "CMIUDCR,CMIU Debug Control Register"
hexmask.long 0x0 4.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "DbgOp,Debug Operation"
rgroup.long 0xFFFFFFFFF70C3F04++0x3
line.long 0x0 "CMIUDAR,CMIU Debug Activity Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "DbgOpFail,Debug Operation Failure" "0,1"
newline
bitfld.long 0x0 0. "DbgOpActv,Debug Operation Active" "0,1"
group.long 0xFFFFFFFFF70C3F08++0x3
line.long 0x0 "CMIUDLR,CMIU Debug Location Register"
hexmask.long.byte 0x0 26.--31. 1. "DbgWord,Debug Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "DbgStruct,Debug Structure"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "DbgEntry,Debug Entry"
rgroup.long 0xFFFFFFFFF70C3F10++0x3
line.long 0x0 "CMIUDDR,CMIU Debug Data Register"
hexmask.long 0x0 0.--31. 1. "DbgData,Debug Operation Data"
rgroup.long 0xFFFFFFFFF70C3FF8++0x7
line.long 0x0 "CMIUCMCIDR,CMIU Coherent Memory Cache Identification Register"
bitfld.long 0x0 29.--31. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 26.--28. "Type,Coherent Memory Cache Type" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 20.--25. 1. "NumWays,Number of Coherent Memory Cache Ways"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "NumSets,Number of Coherent Memory Cache Sets"
line.long 0x4 "CMIUIDR,CMIU Identification Register"
bitfld.long 0x4 31. "Cmc,Coherent Memory Cache" "0,1"
newline
hexmask.long.tbyte 0x4 14.--30. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x4 13. "HntCap,Hint Capable" "0,1"
newline
hexmask.long.byte 0x4 8.--12. 1. "CmiId,Coherent Memory Interface Identifier"
newline
hexmask.long.byte 0x4 0.--7. 1. "ImplVer,Implementation Version"
rgroup.long 0xFFFFFFFFF70C4004++0x3
line.long 0x0 "CMIUTAR,CMIU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 0. "TransActv,Transaction Active" "0,1"
group.long 0xFFFFFFFFF70C4100++0xB
line.long 0x0 "CMIUCECR,CMIU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Correctable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Correctable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Correctable Error Detection Enable" "0,1"
line.long 0x4 "CMIUCESR,CMIU Correctable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "CMIUCELR0,CMIU Correctable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
group.long 0xFFFFFFFFF70C4124++0x3
line.long 0x0 "CMIUCESAR,CMIU Correctable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF70C4F00++0x3
line.long 0x0 "CMIUDCR,CMIU Debug Control Register"
hexmask.long 0x0 4.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "DbgOp,Debug Operation"
rgroup.long 0xFFFFFFFFF70C4F04++0x3
line.long 0x0 "CMIUDAR,CMIU Debug Activity Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "DbgOpFail,Debug Operation Failure" "0,1"
newline
bitfld.long 0x0 0. "DbgOpActv,Debug Operation Active" "0,1"
group.long 0xFFFFFFFFF70C4F08++0x3
line.long 0x0 "CMIUDLR,CMIU Debug Location Register"
hexmask.long.byte 0x0 26.--31. 1. "DbgWord,Debug Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "DbgStruct,Debug Structure"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "DbgEntry,Debug Entry"
rgroup.long 0xFFFFFFFFF70C4F10++0x3
line.long 0x0 "CMIUDDR,CMIU Debug Data Register"
hexmask.long 0x0 0.--31. 1. "DbgData,Debug Operation Data"
rgroup.long 0xFFFFFFFFF70C4FF8++0x7
line.long 0x0 "CMIUCMCIDR,CMIU Coherent Memory Cache Identification Register"
bitfld.long 0x0 29.--31. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 26.--28. "Type,Coherent Memory Cache Type" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 20.--25. 1. "NumWays,Number of Coherent Memory Cache Ways"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "NumSets,Number of Coherent Memory Cache Sets"
line.long 0x4 "CMIUIDR,CMIU Identification Register"
bitfld.long 0x4 31. "Cmc,Coherent Memory Cache" "0,1"
newline
hexmask.long.tbyte 0x4 14.--30. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x4 13. "HntCap,Hint Capable" "0,1"
newline
hexmask.long.byte 0x4 8.--12. 1. "CmiId,Coherent Memory Interface Identifier"
newline
hexmask.long.byte 0x4 0.--7. 1. "ImplVer,Implementation Version"
rgroup.long 0xFFFFFFFFF70C5004++0x3
line.long 0x0 "CMIUTAR,CMIU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 0. "TransActv,Transaction Active" "0,1"
group.long 0xFFFFFFFFF70C5100++0xB
line.long 0x0 "CMIUCECR,CMIU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,Correctable Error Threshold"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,Correctable Error Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,Correctable Error Detection Enable" "0,1"
line.long 0x4 "CMIUCESR,CMIU Correctable Error Status Register"
hexmask.long.byte 0x4 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x4 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x4 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
eventfld.long 0x4 1. "ErrOvf,Error Overflow" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,Error Valid" "0,1"
line.long 0x8 "CMIUCELR0,CMIU Correctable Error Location Register 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,Error Word"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,Error Way"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,Error Entry (or Set)"
group.long 0xFFFFFFFFF70C5124++0x3
line.long 0x0 "CMIUCESAR,CMIU Correctable Error Status Alias Register"
hexmask.long.byte 0x0 24.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 16.--23. 1. "ErrInfo,Error Info"
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,Error Type"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrCount,Error Count"
newline
rbitfld.long 0x0 2.--3. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrOvf,Error Overflow" "0,1"
newline
bitfld.long 0x0 0. "ErrVld,Error Valid" "0,1"
group.long 0xFFFFFFFFF70C5F00++0x3
line.long 0x0 "CMIUDCR,CMIU Debug Control Register"
hexmask.long 0x0 4.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "DbgOp,Debug Operation"
rgroup.long 0xFFFFFFFFF70C5F04++0x3
line.long 0x0 "CMIUDAR,CMIU Debug Activity Register"
hexmask.long 0x0 2.--31. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x0 1. "DbgOpFail,Debug Operation Failure" "0,1"
newline
bitfld.long 0x0 0. "DbgOpActv,Debug Operation Active" "0,1"
group.long 0xFFFFFFFFF70C5F08++0x3
line.long 0x0 "CMIUDLR,CMIU Debug Location Register"
hexmask.long.byte 0x0 26.--31. 1. "DbgWord,Debug Word"
newline
hexmask.long.byte 0x0 20.--25. 1. "DbgStruct,Debug Structure"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "DbgEntry,Debug Entry"
rgroup.long 0xFFFFFFFFF70C5F10++0x3
line.long 0x0 "CMIUDDR,CMIU Debug Data Register"
hexmask.long 0x0 0.--31. 1. "DbgData,Debug Operation Data"
rgroup.long 0xFFFFFFFFF70C5FF8++0x7
line.long 0x0 "CMIUCMCIDR,CMIU Coherent Memory Cache Identification Register"
bitfld.long 0x0 29.--31. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 26.--28. "Type,Coherent Memory Cache Type" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 20.--25. 1. "NumWays,Number of Coherent Memory Cache Ways"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "NumSets,Number of Coherent Memory Cache Sets"
line.long 0x4 "CMIUIDR,CMIU Identification Register"
bitfld.long 0x4 31. "Cmc,Coherent Memory Cache" "0,1"
newline
hexmask.long.tbyte 0x4 14.--30. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x4 13. "HntCap,Hint Capable" "0,1"
newline
hexmask.long.byte 0x4 8.--12. 1. "CmiId,Coherent Memory Interface Identifier"
newline
hexmask.long.byte 0x4 0.--7. 1. "ImplVer,Implementation Version"
group.long 0xFFFFFFFFF70FF040++0x3
line.long 0x0 "CSADSER0,Coherent Subsystem ACE DVM Snoop Enable Register 0"
hexmask.long 0x0 4.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "DvmSnpEn,ACE DVM Snoop Enable"
rgroup.long 0xFFFFFFFFF70FF050++0x3
line.long 0x0 "CSADSAR0,Coherent Subsystem ACE DVM Snoop Activity Register 0"
hexmask.long 0x0 4.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "DvmSnpActv,ACE DVM Snoop Active"
rgroup.long 0xFFFFFFFFF70FF100++0x3
line.long 0x0 "CSCEISR0,Coherent Subsystem Correctable Error Interrupt Status Register 0"
hexmask.long 0x0 4.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "ErrIntVld,Error Interrupt Valid"
rgroup.long 0xFFFFFFFFF70FF110++0x3
line.long 0x0 "CSCEISR4,Coherent Subsystem Correctable Error Interrupt Status Register 4"
hexmask.long 0x0 4.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "ErrIntVld,Error Interrupt Valid"
rgroup.long 0xFFFFFFFFF70FF118++0x3
line.long 0x0 "CSCEISR6,Coherent Subsystem Correctable Error Interrupt Status Register 6"
hexmask.long 0x0 6.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--5. 1. "ErrIntVld,Error Interrupt Valid"
rgroup.long 0xFFFFFFFFF70FF140++0x3
line.long 0x0 "CSUEISR0,Coherent Subsystem Uncorrectable Error Interrupt Status Register 0"
hexmask.long 0x0 4.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "ErrIntVld,Error Interrupt Valid"
rgroup.long 0xFFFFFFFFF70FF150++0x3
line.long 0x0 "CSUEISR4,Coherent Subsystem Uncorrectable Error Interrupt Status Register 4"
hexmask.long 0x0 4.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--3. 1. "ErrIntVld,Error Interrupt Valid"
rgroup.long 0xFFFFFFFFF70FF158++0x3
line.long 0x0 "CSUEISR6,Coherent Subsystem Uncorrectable Error Interrupt Status Register 6"
hexmask.long 0x0 6.--31. 1. "Rsvd,Reserved / (RAZ/WI)"
newline
hexmask.long.byte 0x0 0.--5. 1. "ErrIntVld,Error Interrupt Valid"
rgroup.long 0xFFFFFFFFF70FFF00++0x3
line.long 0x0 "CSSFIDR0,Coherent Subsystem Snoop Filter Identification Registers"
bitfld.long 0x0 29.--31. "rsvd1,Reserved (RAZ/WI)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 26.--28. "Type,Snoop Filter Type" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 20.--25. 1. "NumWays,Number of Snoop Filter Ways"
newline
hexmask.long.tbyte 0x0 0.--19. 1. "NumSets,Number of Snoop Filter Sets"
rgroup.long 0xFFFFFFFFF70FFFF8++0x7
line.long 0x0 "CSUIDR,Coherent Subsystem Unit Identification Register"
bitfld.long 0x0 30.--31. "rsvd4,Reserved (RAZ/WI)" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "NumCmius,Number of Coherent Memory Interface Units"
newline
bitfld.long 0x0 22.--23. "rsvd3,Reserved (RAZ/WI)" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "NumDirus,Number of Directory Units"
newline
bitfld.long 0x0 14.--15. "rsvd2,Reserved (RAZ/WI)" "0,1,2,3"
newline
hexmask.long.byte 0x0 8.--13. 1. "NumNcbus,Number of Non-coherent Bridge Units"
newline
bitfld.long 0x0 7. "rsvd1,Reserved (RAZ/WI)" "0,1"
newline
hexmask.long.byte 0x0 0.--6. 1. "NumCaius,Number of Coherent Agent Interface Units"
line.long 0x4 "CSIDR,Coherent Subsystem Identification Register"
hexmask.long.word 0x4 23.--31. 1. "rsvd2,Reserved (RAZ/WI)"
newline
hexmask.long.byte 0x4 18.--22. 1. "NumSfs,Number of Snoop Filters (-1)"
newline
hexmask.long.byte 0x4 11.--17. 1. "rsvd1,Reserved (RAZ/WI)"
newline
bitfld.long 0x4 8.--10. "DirClOffset,Directory Cache Line Offset (-5)" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 0.--7. 1. "RelVer,Release Version"
rgroup.long 0xFFFFFFFFF7100100++0x7
line.long 0x0 "coh_cpu0_bypass_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "coh_cpu0_bypass_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0xFFFFFFFFF7100108++0x77
line.long 0x0 "coh_cpu0_bypass_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--10. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7"
line.long 0x4 "coh_cpu0_bypass_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "coh_cpu0_bypass_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--12. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "coh_cpu0_bypass_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "coh_cpu0_bypass_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
line.long 0x14 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_00,"
hexmask.long 0x14 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_00,"
line.long 0x18 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_01,"
hexmask.long 0x18 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_01,"
line.long 0x1C "coh_cpu0_bypass_I_main_QosGenerator_Reserved_02,"
hexmask.long 0x1C 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_02,"
line.long 0x20 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_03,"
hexmask.long 0x20 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_03,"
line.long 0x24 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_04,"
hexmask.long 0x24 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_04,"
line.long 0x28 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_05,"
hexmask.long 0x28 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_05,"
line.long 0x2C "coh_cpu0_bypass_I_main_QosGenerator_Reserved_06,"
hexmask.long 0x2C 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_06,"
line.long 0x30 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_07,"
hexmask.long 0x30 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_07,"
line.long 0x34 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_08,"
hexmask.long 0x34 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_08,"
line.long 0x38 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_09,"
hexmask.long 0x38 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_09,"
line.long 0x3C "coh_cpu0_bypass_I_main_QosGenerator_Reserved_10,"
hexmask.long 0x3C 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_10,"
line.long 0x40 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_11,"
hexmask.long 0x40 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_11,"
line.long 0x44 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_12,"
hexmask.long 0x44 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_12,"
line.long 0x48 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_13,"
hexmask.long 0x48 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_13,"
line.long 0x4C "coh_cpu0_bypass_I_main_QosGenerator_Reserved_14,"
hexmask.long 0x4C 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_14,"
line.long 0x50 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_15,"
hexmask.long 0x50 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_15,"
line.long 0x54 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_16,"
hexmask.long 0x54 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_16,"
line.long 0x58 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_17,"
hexmask.long 0x58 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_17,"
line.long 0x5C "coh_cpu0_bypass_I_main_QosGenerator_Reserved_18,"
hexmask.long 0x5C 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_18,"
line.long 0x60 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_19,"
hexmask.long 0x60 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_19,"
line.long 0x64 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_20,"
hexmask.long 0x64 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_20,"
line.long 0x68 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_21,"
hexmask.long 0x68 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_21,"
line.long 0x6C "coh_cpu0_bypass_I_main_QosGenerator_Reserved_22,"
hexmask.long 0x6C 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_22,"
line.long 0x70 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_23,"
hexmask.long 0x70 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_23,"
line.long 0x74 "coh_cpu0_bypass_I_main_QosGenerator_Reserved_24,"
hexmask.long 0x74 0.--31. 1. "coh_cpu0_bypass_I_main_QosGenerator_Reserved_24,"
group.long 0xFFFFFFFFF7100200++0x13
line.long 0x0 "coh_cpu0_bypass_OC_Firewall_main_Firewall_Reserved_00,"
hexmask.long 0x0 0.--31. 1. "coh_cpu0_bypass_OC_Firewall_main_Firewall_Reserved_00,"
line.long 0x4 "coh_cpu0_bypass_OC_Firewall_main_Firewall_OCRAM_BLK_CGF_01,OCRAM BLK1 FW Settings"
bitfld.long 0x4 31. "VALID,Set for Valid OCRAM Block" "0,1"
newline
bitfld.long 0x4 30. "SECURE,Set for allowing only secure access" "0,1"
newline
bitfld.long 0x4 29. "PRIVILEGED,Set for allowing only privileged access" "0,1"
newline
hexmask.long.tbyte 0x4 0.--17. 1. "MEMBLKSIZE,OCRAM BLK SIZE"
line.long 0x8 "coh_cpu0_bypass_OC_Firewall_main_Firewall_OCRAM_BLK_CGF_02,OCRAM BLK2 FW Settings"
bitfld.long 0x8 31. "VALID,Set for Valid OCRAM Block" "0,1"
newline
bitfld.long 0x8 30. "SECURE,Set for allowing only secure access" "0,1"
newline
bitfld.long 0x8 29. "PRIVILEGED,Set for allowing only privileged access" "0,1"
newline
hexmask.long.tbyte 0x8 0.--17. 1. "MEMBLKSIZE,OCRAM BLK SIZE"
line.long 0xC "coh_cpu0_bypass_OC_Firewall_main_Firewall_OCRAM_BLK_CGF_03,OCRAM BLK3 FW Settings"
bitfld.long 0xC 31. "VALID,Set for Valid OCRAM Block" "0,1"
newline
bitfld.long 0xC 30. "SECURE,Set for allowing only secure access" "0,1"
newline
bitfld.long 0xC 29. "PRIVILEGED,Set for allowing only privileged access" "0,1"
newline
hexmask.long.tbyte 0xC 0.--17. 1. "MEMBLKSIZE,OCRAM BLK SIZE"
line.long 0x10 "coh_cpu0_bypass_OC_Firewall_main_Firewall_OCRAM_BLK_CGF_04,OCRAM BLK4 FW Settings"
bitfld.long 0x10 31. "VALID,Set for Valid OCRAM Block" "0,1"
newline
bitfld.long 0x10 30. "SECURE,Set for allowing only secure access" "0,1"
newline
bitfld.long 0x10 29. "PRIVILEGED,Set for allowing only privileged access" "0,1"
newline
hexmask.long.tbyte 0x10 0.--17. 1. "MEMBLKSIZE,OCRAM BLK SIZE"
rgroup.long 0xFFFFFFFFF7100300++0x7
line.long 0x0 "coh_fpga10_bypass_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "coh_fpga10_bypass_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0xFFFFFFFFF7100308++0x77
line.long 0x0 "coh_fpga10_bypass_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--10. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7"
line.long 0x4 "coh_fpga10_bypass_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "coh_fpga10_bypass_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--13. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "coh_fpga10_bypass_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "coh_fpga10_bypass_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
line.long 0x14 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_00,"
hexmask.long 0x14 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_00,"
line.long 0x18 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_01,"
hexmask.long 0x18 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_01,"
line.long 0x1C "coh_fpga10_bypass_I_main_QosGenerator_Reserved_02,"
hexmask.long 0x1C 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_02,"
line.long 0x20 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_03,"
hexmask.long 0x20 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_03,"
line.long 0x24 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_04,"
hexmask.long 0x24 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_04,"
line.long 0x28 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_05,"
hexmask.long 0x28 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_05,"
line.long 0x2C "coh_fpga10_bypass_I_main_QosGenerator_Reserved_06,"
hexmask.long 0x2C 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_06,"
line.long 0x30 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_07,"
hexmask.long 0x30 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_07,"
line.long 0x34 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_08,"
hexmask.long 0x34 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_08,"
line.long 0x38 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_09,"
hexmask.long 0x38 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_09,"
line.long 0x3C "coh_fpga10_bypass_I_main_QosGenerator_Reserved_10,"
hexmask.long 0x3C 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_10,"
line.long 0x40 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_11,"
hexmask.long 0x40 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_11,"
line.long 0x44 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_12,"
hexmask.long 0x44 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_12,"
line.long 0x48 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_13,"
hexmask.long 0x48 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_13,"
line.long 0x4C "coh_fpga10_bypass_I_main_QosGenerator_Reserved_14,"
hexmask.long 0x4C 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_14,"
line.long 0x50 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_15,"
hexmask.long 0x50 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_15,"
line.long 0x54 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_16,"
hexmask.long 0x54 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_16,"
line.long 0x58 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_17,"
hexmask.long 0x58 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_17,"
line.long 0x5C "coh_fpga10_bypass_I_main_QosGenerator_Reserved_18,"
hexmask.long 0x5C 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_18,"
line.long 0x60 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_19,"
hexmask.long 0x60 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_19,"
line.long 0x64 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_20,"
hexmask.long 0x64 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_20,"
line.long 0x68 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_21,"
hexmask.long 0x68 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_21,"
line.long 0x6C "coh_fpga10_bypass_I_main_QosGenerator_Reserved_22,"
hexmask.long 0x6C 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_22,"
line.long 0x70 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_23,"
hexmask.long 0x70 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_23,"
line.long 0x74 "coh_fpga10_bypass_I_main_QosGenerator_Reserved_24,"
hexmask.long 0x74 0.--31. 1. "coh_fpga10_bypass_I_main_QosGenerator_Reserved_24,"
rgroup.long 0xFFFFFFFFF7100380++0x7
line.long 0x0 "coh_iom0_bypass_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "coh_iom0_bypass_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0xFFFFFFFFF7100388++0x77
line.long 0x0 "coh_iom0_bypass_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--10. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7"
line.long 0x4 "coh_iom0_bypass_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "coh_iom0_bypass_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "coh_iom0_bypass_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "coh_iom0_bypass_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
line.long 0x14 "coh_iom0_bypass_I_main_QosGenerator_Reserved_00,"
hexmask.long 0x14 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_00,"
line.long 0x18 "coh_iom0_bypass_I_main_QosGenerator_Reserved_01,"
hexmask.long 0x18 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_01,"
line.long 0x1C "coh_iom0_bypass_I_main_QosGenerator_Reserved_02,"
hexmask.long 0x1C 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_02,"
line.long 0x20 "coh_iom0_bypass_I_main_QosGenerator_Reserved_03,"
hexmask.long 0x20 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_03,"
line.long 0x24 "coh_iom0_bypass_I_main_QosGenerator_Reserved_04,"
hexmask.long 0x24 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_04,"
line.long 0x28 "coh_iom0_bypass_I_main_QosGenerator_Reserved_05,"
hexmask.long 0x28 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_05,"
line.long 0x2C "coh_iom0_bypass_I_main_QosGenerator_Reserved_06,"
hexmask.long 0x2C 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_06,"
line.long 0x30 "coh_iom0_bypass_I_main_QosGenerator_Reserved_07,"
hexmask.long 0x30 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_07,"
line.long 0x34 "coh_iom0_bypass_I_main_QosGenerator_Reserved_08,"
hexmask.long 0x34 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_08,"
line.long 0x38 "coh_iom0_bypass_I_main_QosGenerator_Reserved_09,"
hexmask.long 0x38 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_09,"
line.long 0x3C "coh_iom0_bypass_I_main_QosGenerator_Reserved_10,"
hexmask.long 0x3C 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_10,"
line.long 0x40 "coh_iom0_bypass_I_main_QosGenerator_Reserved_11,"
hexmask.long 0x40 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_11,"
line.long 0x44 "coh_iom0_bypass_I_main_QosGenerator_Reserved_12,"
hexmask.long 0x44 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_12,"
line.long 0x48 "coh_iom0_bypass_I_main_QosGenerator_Reserved_13,"
hexmask.long 0x48 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_13,"
line.long 0x4C "coh_iom0_bypass_I_main_QosGenerator_Reserved_14,"
hexmask.long 0x4C 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_14,"
line.long 0x50 "coh_iom0_bypass_I_main_QosGenerator_Reserved_15,"
hexmask.long 0x50 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_15,"
line.long 0x54 "coh_iom0_bypass_I_main_QosGenerator_Reserved_16,"
hexmask.long 0x54 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_16,"
line.long 0x58 "coh_iom0_bypass_I_main_QosGenerator_Reserved_17,"
hexmask.long 0x58 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_17,"
line.long 0x5C "coh_iom0_bypass_I_main_QosGenerator_Reserved_18,"
hexmask.long 0x5C 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_18,"
line.long 0x60 "coh_iom0_bypass_I_main_QosGenerator_Reserved_19,"
hexmask.long 0x60 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_19,"
line.long 0x64 "coh_iom0_bypass_I_main_QosGenerator_Reserved_20,"
hexmask.long 0x64 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_20,"
line.long 0x68 "coh_iom0_bypass_I_main_QosGenerator_Reserved_21,"
hexmask.long 0x68 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_21,"
line.long 0x6C "coh_iom0_bypass_I_main_QosGenerator_Reserved_22,"
hexmask.long 0x6C 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_22,"
line.long 0x70 "coh_iom0_bypass_I_main_QosGenerator_Reserved_23,"
hexmask.long 0x70 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_23,"
line.long 0x74 "coh_iom0_bypass_I_main_QosGenerator_Reserved_24,"
hexmask.long 0x74 0.--31. 1. "coh_iom0_bypass_I_main_QosGenerator_Reserved_24,"
rgroup.long 0xFFFFFFFFF7100400++0x7
line.long 0x0 "coh_iospace10_bypass_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "coh_iospace10_bypass_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0xFFFFFFFFF7100408++0x77
line.long 0x0 "coh_iospace10_bypass_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--10. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7"
line.long 0x4 "coh_iospace10_bypass_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "coh_iospace10_bypass_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--12. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "coh_iospace10_bypass_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "coh_iospace10_bypass_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
line.long 0x14 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_00,"
hexmask.long 0x14 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_00,"
line.long 0x18 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_01,"
hexmask.long 0x18 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_01,"
line.long 0x1C "coh_iospace10_bypass_I_main_QosGenerator_Reserved_02,"
hexmask.long 0x1C 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_02,"
line.long 0x20 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_03,"
hexmask.long 0x20 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_03,"
line.long 0x24 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_04,"
hexmask.long 0x24 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_04,"
line.long 0x28 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_05,"
hexmask.long 0x28 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_05,"
line.long 0x2C "coh_iospace10_bypass_I_main_QosGenerator_Reserved_06,"
hexmask.long 0x2C 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_06,"
line.long 0x30 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_07,"
hexmask.long 0x30 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_07,"
line.long 0x34 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_08,"
hexmask.long 0x34 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_08,"
line.long 0x38 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_09,"
hexmask.long 0x38 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_09,"
line.long 0x3C "coh_iospace10_bypass_I_main_QosGenerator_Reserved_10,"
hexmask.long 0x3C 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_10,"
line.long 0x40 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_11,"
hexmask.long 0x40 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_11,"
line.long 0x44 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_12,"
hexmask.long 0x44 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_12,"
line.long 0x48 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_13,"
hexmask.long 0x48 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_13,"
line.long 0x4C "coh_iospace10_bypass_I_main_QosGenerator_Reserved_14,"
hexmask.long 0x4C 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_14,"
line.long 0x50 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_15,"
hexmask.long 0x50 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_15,"
line.long 0x54 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_16,"
hexmask.long 0x54 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_16,"
line.long 0x58 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_17,"
hexmask.long 0x58 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_17,"
line.long 0x5C "coh_iospace10_bypass_I_main_QosGenerator_Reserved_18,"
hexmask.long 0x5C 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_18,"
line.long 0x60 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_19,"
hexmask.long 0x60 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_19,"
line.long 0x64 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_20,"
hexmask.long 0x64 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_20,"
line.long 0x68 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_21,"
hexmask.long 0x68 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_21,"
line.long 0x6C "coh_iospace10_bypass_I_main_QosGenerator_Reserved_22,"
hexmask.long 0x6C 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_22,"
line.long 0x70 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_23,"
hexmask.long 0x70 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_23,"
line.long 0x74 "coh_iospace10_bypass_I_main_QosGenerator_Reserved_24,"
hexmask.long 0x74 0.--31. 1. "coh_iospace10_bypass_I_main_QosGenerator_Reserved_24,"
rgroup.long 0xFFFFFFFFF7100480++0x7
line.long 0x0 "coh_mem00_bypass_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "coh_mem00_bypass_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0xFFFFFFFFF7100488++0x77
line.long 0x0 "coh_mem00_bypass_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--10. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7"
line.long 0x4 "coh_mem00_bypass_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "coh_mem00_bypass_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--13. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "coh_mem00_bypass_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "coh_mem00_bypass_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
line.long 0x14 "coh_mem00_bypass_I_main_QosGenerator_Reserved_00,"
hexmask.long 0x14 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_00,"
line.long 0x18 "coh_mem00_bypass_I_main_QosGenerator_Reserved_01,"
hexmask.long 0x18 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_01,"
line.long 0x1C "coh_mem00_bypass_I_main_QosGenerator_Reserved_02,"
hexmask.long 0x1C 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_02,"
line.long 0x20 "coh_mem00_bypass_I_main_QosGenerator_Reserved_03,"
hexmask.long 0x20 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_03,"
line.long 0x24 "coh_mem00_bypass_I_main_QosGenerator_Reserved_04,"
hexmask.long 0x24 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_04,"
line.long 0x28 "coh_mem00_bypass_I_main_QosGenerator_Reserved_05,"
hexmask.long 0x28 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_05,"
line.long 0x2C "coh_mem00_bypass_I_main_QosGenerator_Reserved_06,"
hexmask.long 0x2C 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_06,"
line.long 0x30 "coh_mem00_bypass_I_main_QosGenerator_Reserved_07,"
hexmask.long 0x30 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_07,"
line.long 0x34 "coh_mem00_bypass_I_main_QosGenerator_Reserved_08,"
hexmask.long 0x34 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_08,"
line.long 0x38 "coh_mem00_bypass_I_main_QosGenerator_Reserved_09,"
hexmask.long 0x38 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_09,"
line.long 0x3C "coh_mem00_bypass_I_main_QosGenerator_Reserved_10,"
hexmask.long 0x3C 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_10,"
line.long 0x40 "coh_mem00_bypass_I_main_QosGenerator_Reserved_11,"
hexmask.long 0x40 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_11,"
line.long 0x44 "coh_mem00_bypass_I_main_QosGenerator_Reserved_12,"
hexmask.long 0x44 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_12,"
line.long 0x48 "coh_mem00_bypass_I_main_QosGenerator_Reserved_13,"
hexmask.long 0x48 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_13,"
line.long 0x4C "coh_mem00_bypass_I_main_QosGenerator_Reserved_14,"
hexmask.long 0x4C 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_14,"
line.long 0x50 "coh_mem00_bypass_I_main_QosGenerator_Reserved_15,"
hexmask.long 0x50 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_15,"
line.long 0x54 "coh_mem00_bypass_I_main_QosGenerator_Reserved_16,"
hexmask.long 0x54 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_16,"
line.long 0x58 "coh_mem00_bypass_I_main_QosGenerator_Reserved_17,"
hexmask.long 0x58 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_17,"
line.long 0x5C "coh_mem00_bypass_I_main_QosGenerator_Reserved_18,"
hexmask.long 0x5C 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_18,"
line.long 0x60 "coh_mem00_bypass_I_main_QosGenerator_Reserved_19,"
hexmask.long 0x60 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_19,"
line.long 0x64 "coh_mem00_bypass_I_main_QosGenerator_Reserved_20,"
hexmask.long 0x64 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_20,"
line.long 0x68 "coh_mem00_bypass_I_main_QosGenerator_Reserved_21,"
hexmask.long 0x68 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_21,"
line.long 0x6C "coh_mem00_bypass_I_main_QosGenerator_Reserved_22,"
hexmask.long 0x6C 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_22,"
line.long 0x70 "coh_mem00_bypass_I_main_QosGenerator_Reserved_23,"
hexmask.long 0x70 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_23,"
line.long 0x74 "coh_mem00_bypass_I_main_QosGenerator_Reserved_24,"
hexmask.long 0x74 0.--31. 1. "coh_mem00_bypass_I_main_QosGenerator_Reserved_24,"
rgroup.long 0xFFFFFFFFF7100500++0x7
line.long 0x0 "coh_mem10_bypass_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "coh_mem10_bypass_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0xFFFFFFFFF7100508++0x77
line.long 0x0 "coh_mem10_bypass_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--10. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7"
line.long 0x4 "coh_mem10_bypass_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "coh_mem10_bypass_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--13. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "coh_mem10_bypass_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "coh_mem10_bypass_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
line.long 0x14 "coh_mem10_bypass_I_main_QosGenerator_Reserved_00,"
hexmask.long 0x14 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_00,"
line.long 0x18 "coh_mem10_bypass_I_main_QosGenerator_Reserved_01,"
hexmask.long 0x18 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_01,"
line.long 0x1C "coh_mem10_bypass_I_main_QosGenerator_Reserved_02,"
hexmask.long 0x1C 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_02,"
line.long 0x20 "coh_mem10_bypass_I_main_QosGenerator_Reserved_03,"
hexmask.long 0x20 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_03,"
line.long 0x24 "coh_mem10_bypass_I_main_QosGenerator_Reserved_04,"
hexmask.long 0x24 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_04,"
line.long 0x28 "coh_mem10_bypass_I_main_QosGenerator_Reserved_05,"
hexmask.long 0x28 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_05,"
line.long 0x2C "coh_mem10_bypass_I_main_QosGenerator_Reserved_06,"
hexmask.long 0x2C 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_06,"
line.long 0x30 "coh_mem10_bypass_I_main_QosGenerator_Reserved_07,"
hexmask.long 0x30 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_07,"
line.long 0x34 "coh_mem10_bypass_I_main_QosGenerator_Reserved_08,"
hexmask.long 0x34 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_08,"
line.long 0x38 "coh_mem10_bypass_I_main_QosGenerator_Reserved_09,"
hexmask.long 0x38 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_09,"
line.long 0x3C "coh_mem10_bypass_I_main_QosGenerator_Reserved_10,"
hexmask.long 0x3C 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_10,"
line.long 0x40 "coh_mem10_bypass_I_main_QosGenerator_Reserved_11,"
hexmask.long 0x40 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_11,"
line.long 0x44 "coh_mem10_bypass_I_main_QosGenerator_Reserved_12,"
hexmask.long 0x44 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_12,"
line.long 0x48 "coh_mem10_bypass_I_main_QosGenerator_Reserved_13,"
hexmask.long 0x48 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_13,"
line.long 0x4C "coh_mem10_bypass_I_main_QosGenerator_Reserved_14,"
hexmask.long 0x4C 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_14,"
line.long 0x50 "coh_mem10_bypass_I_main_QosGenerator_Reserved_15,"
hexmask.long 0x50 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_15,"
line.long 0x54 "coh_mem10_bypass_I_main_QosGenerator_Reserved_16,"
hexmask.long 0x54 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_16,"
line.long 0x58 "coh_mem10_bypass_I_main_QosGenerator_Reserved_17,"
hexmask.long 0x58 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_17,"
line.long 0x5C "coh_mem10_bypass_I_main_QosGenerator_Reserved_18,"
hexmask.long 0x5C 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_18,"
line.long 0x60 "coh_mem10_bypass_I_main_QosGenerator_Reserved_19,"
hexmask.long 0x60 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_19,"
line.long 0x64 "coh_mem10_bypass_I_main_QosGenerator_Reserved_20,"
hexmask.long 0x64 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_20,"
line.long 0x68 "coh_mem10_bypass_I_main_QosGenerator_Reserved_21,"
hexmask.long 0x68 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_21,"
line.long 0x6C "coh_mem10_bypass_I_main_QosGenerator_Reserved_22,"
hexmask.long 0x6C 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_22,"
line.long 0x70 "coh_mem10_bypass_I_main_QosGenerator_Reserved_23,"
hexmask.long 0x70 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_23,"
line.long 0x74 "coh_mem10_bypass_I_main_QosGenerator_Reserved_24,"
hexmask.long 0x74 0.--31. 1. "coh_mem10_bypass_I_main_QosGenerator_Reserved_24,"
rgroup.long 0xFFFFFFFFF7100580++0x7
line.long 0x0 "coh_mem20_bypass_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "coh_mem20_bypass_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0xFFFFFFFFF7100588++0x77
line.long 0x0 "coh_mem20_bypass_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--10. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7"
line.long 0x4 "coh_mem20_bypass_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "coh_mem20_bypass_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--13. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "coh_mem20_bypass_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "coh_mem20_bypass_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
line.long 0x14 "coh_mem20_bypass_I_main_QosGenerator_Reserved_00,"
hexmask.long 0x14 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_00,"
line.long 0x18 "coh_mem20_bypass_I_main_QosGenerator_Reserved_01,"
hexmask.long 0x18 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_01,"
line.long 0x1C "coh_mem20_bypass_I_main_QosGenerator_Reserved_02,"
hexmask.long 0x1C 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_02,"
line.long 0x20 "coh_mem20_bypass_I_main_QosGenerator_Reserved_03,"
hexmask.long 0x20 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_03,"
line.long 0x24 "coh_mem20_bypass_I_main_QosGenerator_Reserved_04,"
hexmask.long 0x24 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_04,"
line.long 0x28 "coh_mem20_bypass_I_main_QosGenerator_Reserved_05,"
hexmask.long 0x28 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_05,"
line.long 0x2C "coh_mem20_bypass_I_main_QosGenerator_Reserved_06,"
hexmask.long 0x2C 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_06,"
line.long 0x30 "coh_mem20_bypass_I_main_QosGenerator_Reserved_07,"
hexmask.long 0x30 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_07,"
line.long 0x34 "coh_mem20_bypass_I_main_QosGenerator_Reserved_08,"
hexmask.long 0x34 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_08,"
line.long 0x38 "coh_mem20_bypass_I_main_QosGenerator_Reserved_09,"
hexmask.long 0x38 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_09,"
line.long 0x3C "coh_mem20_bypass_I_main_QosGenerator_Reserved_10,"
hexmask.long 0x3C 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_10,"
line.long 0x40 "coh_mem20_bypass_I_main_QosGenerator_Reserved_11,"
hexmask.long 0x40 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_11,"
line.long 0x44 "coh_mem20_bypass_I_main_QosGenerator_Reserved_12,"
hexmask.long 0x44 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_12,"
line.long 0x48 "coh_mem20_bypass_I_main_QosGenerator_Reserved_13,"
hexmask.long 0x48 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_13,"
line.long 0x4C "coh_mem20_bypass_I_main_QosGenerator_Reserved_14,"
hexmask.long 0x4C 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_14,"
line.long 0x50 "coh_mem20_bypass_I_main_QosGenerator_Reserved_15,"
hexmask.long 0x50 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_15,"
line.long 0x54 "coh_mem20_bypass_I_main_QosGenerator_Reserved_16,"
hexmask.long 0x54 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_16,"
line.long 0x58 "coh_mem20_bypass_I_main_QosGenerator_Reserved_17,"
hexmask.long 0x58 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_17,"
line.long 0x5C "coh_mem20_bypass_I_main_QosGenerator_Reserved_18,"
hexmask.long 0x5C 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_18,"
line.long 0x60 "coh_mem20_bypass_I_main_QosGenerator_Reserved_19,"
hexmask.long 0x60 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_19,"
line.long 0x64 "coh_mem20_bypass_I_main_QosGenerator_Reserved_20,"
hexmask.long 0x64 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_20,"
line.long 0x68 "coh_mem20_bypass_I_main_QosGenerator_Reserved_21,"
hexmask.long 0x68 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_21,"
line.long 0x6C "coh_mem20_bypass_I_main_QosGenerator_Reserved_22,"
hexmask.long 0x6C 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_22,"
line.long 0x70 "coh_mem20_bypass_I_main_QosGenerator_Reserved_23,"
hexmask.long 0x70 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_23,"
line.long 0x74 "coh_mem20_bypass_I_main_QosGenerator_Reserved_24,"
hexmask.long 0x74 0.--31. 1. "coh_mem20_bypass_I_main_QosGenerator_Reserved_24,"
rgroup.long 0xFFFFFFFFF7100600++0x7
line.long 0x0 "coh_mem30_bypass_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "coh_mem30_bypass_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0xFFFFFFFFF7100608++0x77
line.long 0x0 "coh_mem30_bypass_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--10. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7"
line.long 0x4 "coh_mem30_bypass_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "coh_mem30_bypass_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--13. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "coh_mem30_bypass_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "coh_mem30_bypass_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
line.long 0x14 "coh_mem30_bypass_I_main_QosGenerator_Reserved_00,"
hexmask.long 0x14 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_00,"
line.long 0x18 "coh_mem30_bypass_I_main_QosGenerator_Reserved_01,"
hexmask.long 0x18 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_01,"
line.long 0x1C "coh_mem30_bypass_I_main_QosGenerator_Reserved_02,"
hexmask.long 0x1C 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_02,"
line.long 0x20 "coh_mem30_bypass_I_main_QosGenerator_Reserved_03,"
hexmask.long 0x20 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_03,"
line.long 0x24 "coh_mem30_bypass_I_main_QosGenerator_Reserved_04,"
hexmask.long 0x24 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_04,"
line.long 0x28 "coh_mem30_bypass_I_main_QosGenerator_Reserved_05,"
hexmask.long 0x28 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_05,"
line.long 0x2C "coh_mem30_bypass_I_main_QosGenerator_Reserved_06,"
hexmask.long 0x2C 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_06,"
line.long 0x30 "coh_mem30_bypass_I_main_QosGenerator_Reserved_07,"
hexmask.long 0x30 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_07,"
line.long 0x34 "coh_mem30_bypass_I_main_QosGenerator_Reserved_08,"
hexmask.long 0x34 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_08,"
line.long 0x38 "coh_mem30_bypass_I_main_QosGenerator_Reserved_09,"
hexmask.long 0x38 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_09,"
line.long 0x3C "coh_mem30_bypass_I_main_QosGenerator_Reserved_10,"
hexmask.long 0x3C 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_10,"
line.long 0x40 "coh_mem30_bypass_I_main_QosGenerator_Reserved_11,"
hexmask.long 0x40 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_11,"
line.long 0x44 "coh_mem30_bypass_I_main_QosGenerator_Reserved_12,"
hexmask.long 0x44 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_12,"
line.long 0x48 "coh_mem30_bypass_I_main_QosGenerator_Reserved_13,"
hexmask.long 0x48 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_13,"
line.long 0x4C "coh_mem30_bypass_I_main_QosGenerator_Reserved_14,"
hexmask.long 0x4C 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_14,"
line.long 0x50 "coh_mem30_bypass_I_main_QosGenerator_Reserved_15,"
hexmask.long 0x50 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_15,"
line.long 0x54 "coh_mem30_bypass_I_main_QosGenerator_Reserved_16,"
hexmask.long 0x54 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_16,"
line.long 0x58 "coh_mem30_bypass_I_main_QosGenerator_Reserved_17,"
hexmask.long 0x58 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_17,"
line.long 0x5C "coh_mem30_bypass_I_main_QosGenerator_Reserved_18,"
hexmask.long 0x5C 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_18,"
line.long 0x60 "coh_mem30_bypass_I_main_QosGenerator_Reserved_19,"
hexmask.long 0x60 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_19,"
line.long 0x64 "coh_mem30_bypass_I_main_QosGenerator_Reserved_20,"
hexmask.long 0x64 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_20,"
line.long 0x68 "coh_mem30_bypass_I_main_QosGenerator_Reserved_21,"
hexmask.long 0x68 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_21,"
line.long 0x6C "coh_mem30_bypass_I_main_QosGenerator_Reserved_22,"
hexmask.long 0x6C 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_22,"
line.long 0x70 "coh_mem30_bypass_I_main_QosGenerator_Reserved_23,"
hexmask.long 0x70 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_23,"
line.long 0x74 "coh_mem30_bypass_I_main_QosGenerator_Reserved_24,"
hexmask.long 0x74 0.--31. 1. "coh_mem30_bypass_I_main_QosGenerator_Reserved_24,"
rgroup.long 0xFFFFFFFFF7100680++0x7
line.long 0x0 "coh_ocram0_bypass_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "coh_ocram0_bypass_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0xFFFFFFFFF7100688++0x77
line.long 0x0 "coh_ocram0_bypass_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--10. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7"
line.long 0x4 "coh_ocram0_bypass_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "coh_ocram0_bypass_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--12. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "coh_ocram0_bypass_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "coh_ocram0_bypass_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
line.long 0x14 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_00,"
hexmask.long 0x14 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_00,"
line.long 0x18 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_01,"
hexmask.long 0x18 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_01,"
line.long 0x1C "coh_ocram0_bypass_I_main_QosGenerator_Reserved_02,"
hexmask.long 0x1C 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_02,"
line.long 0x20 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_03,"
hexmask.long 0x20 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_03,"
line.long 0x24 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_04,"
hexmask.long 0x24 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_04,"
line.long 0x28 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_05,"
hexmask.long 0x28 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_05,"
line.long 0x2C "coh_ocram0_bypass_I_main_QosGenerator_Reserved_06,"
hexmask.long 0x2C 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_06,"
line.long 0x30 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_07,"
hexmask.long 0x30 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_07,"
line.long 0x34 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_08,"
hexmask.long 0x34 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_08,"
line.long 0x38 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_09,"
hexmask.long 0x38 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_09,"
line.long 0x3C "coh_ocram0_bypass_I_main_QosGenerator_Reserved_10,"
hexmask.long 0x3C 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_10,"
line.long 0x40 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_11,"
hexmask.long 0x40 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_11,"
line.long 0x44 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_12,"
hexmask.long 0x44 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_12,"
line.long 0x48 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_13,"
hexmask.long 0x48 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_13,"
line.long 0x4C "coh_ocram0_bypass_I_main_QosGenerator_Reserved_14,"
hexmask.long 0x4C 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_14,"
line.long 0x50 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_15,"
hexmask.long 0x50 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_15,"
line.long 0x54 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_16,"
hexmask.long 0x54 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_16,"
line.long 0x58 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_17,"
hexmask.long 0x58 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_17,"
line.long 0x5C "coh_ocram0_bypass_I_main_QosGenerator_Reserved_18,"
hexmask.long 0x5C 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_18,"
line.long 0x60 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_19,"
hexmask.long 0x60 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_19,"
line.long 0x64 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_20,"
hexmask.long 0x64 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_20,"
line.long 0x68 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_21,"
hexmask.long 0x68 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_21,"
line.long 0x6C "coh_ocram0_bypass_I_main_QosGenerator_Reserved_22,"
hexmask.long 0x6C 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_22,"
line.long 0x70 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_23,"
hexmask.long 0x70 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_23,"
line.long 0x74 "coh_ocram0_bypass_I_main_QosGenerator_Reserved_24,"
hexmask.long 0x74 0.--31. 1. "coh_ocram0_bypass_I_main_QosGenerator_Reserved_24,"
rgroup.long 0xFFFFFFFFF7100700++0x7
line.long 0x0 "coh_tcu0_bypass_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "coh_tcu0_bypass_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0xFFFFFFFFF7100708++0x77
line.long 0x0 "coh_tcu0_bypass_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--10. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3,4,5,6,7"
line.long 0x4 "coh_tcu0_bypass_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "coh_tcu0_bypass_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "coh_tcu0_bypass_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "coh_tcu0_bypass_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
line.long 0x14 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_00,"
hexmask.long 0x14 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_00,"
line.long 0x18 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_01,"
hexmask.long 0x18 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_01,"
line.long 0x1C "coh_tcu0_bypass_I_main_QosGenerator_Reserved_02,"
hexmask.long 0x1C 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_02,"
line.long 0x20 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_03,"
hexmask.long 0x20 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_03,"
line.long 0x24 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_04,"
hexmask.long 0x24 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_04,"
line.long 0x28 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_05,"
hexmask.long 0x28 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_05,"
line.long 0x2C "coh_tcu0_bypass_I_main_QosGenerator_Reserved_06,"
hexmask.long 0x2C 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_06,"
line.long 0x30 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_07,"
hexmask.long 0x30 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_07,"
line.long 0x34 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_08,"
hexmask.long 0x34 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_08,"
line.long 0x38 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_09,"
hexmask.long 0x38 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_09,"
line.long 0x3C "coh_tcu0_bypass_I_main_QosGenerator_Reserved_10,"
hexmask.long 0x3C 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_10,"
line.long 0x40 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_11,"
hexmask.long 0x40 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_11,"
line.long 0x44 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_12,"
hexmask.long 0x44 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_12,"
line.long 0x48 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_13,"
hexmask.long 0x48 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_13,"
line.long 0x4C "coh_tcu0_bypass_I_main_QosGenerator_Reserved_14,"
hexmask.long 0x4C 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_14,"
line.long 0x50 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_15,"
hexmask.long 0x50 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_15,"
line.long 0x54 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_16,"
hexmask.long 0x54 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_16,"
line.long 0x58 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_17,"
hexmask.long 0x58 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_17,"
line.long 0x5C "coh_tcu0_bypass_I_main_QosGenerator_Reserved_18,"
hexmask.long 0x5C 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_18,"
line.long 0x60 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_19,"
hexmask.long 0x60 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_19,"
line.long 0x64 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_20,"
hexmask.long 0x64 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_20,"
line.long 0x68 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_21,"
hexmask.long 0x68 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_21,"
line.long 0x6C "coh_tcu0_bypass_I_main_QosGenerator_Reserved_22,"
hexmask.long 0x6C 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_22,"
line.long 0x70 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_23,"
hexmask.long 0x70 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_23,"
line.long 0x74 "coh_tcu0_bypass_I_main_QosGenerator_Reserved_24,"
hexmask.long 0x74 0.--31. 1. "coh_tcu0_bypass_I_main_QosGenerator_Reserved_24,"
rgroup.long 0xFFFFFFFFF7100780++0x7
line.long 0x0 "observer_main_ErrorLogger_0_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "observer_main_ErrorLogger_0_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0xFFFFFFFFF7100788++0x3
line.long 0x0 "observer_main_ErrorLogger_0_FaultEn,"
bitfld.long 0x0 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1"
rgroup.long 0xFFFFFFFFF710078C++0x3
line.long 0x0 "observer_main_ErrorLogger_0_ErrVld,"
bitfld.long 0x0 0. "ERRVLD,1 indicates an error has been logged" "0,1"
group.long 0xFFFFFFFFF7100790++0x3
line.long 0x0 "observer_main_ErrorLogger_0_ErrClr,"
eventfld.long 0x0 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1"
rgroup.long 0xFFFFFFFFF7100794++0x7
line.long 0x0 "observer_main_ErrorLogger_0_ErrLog0,Stores NTTP packet header fields Lock. Opc. ErrCode. Len1 and indicates version of NTTP transport protocol"
bitfld.long 0x0 31. "FORMAT,NTTP transport protocol version" "0,1"
newline
hexmask.long.word 0x0 16.--27. 1. "LEN1,Len1"
newline
bitfld.long 0x0 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 1.--4. 1. "OPC,Opc"
newline
bitfld.long 0x0 0. "LOCK,Lock" "0,1"
line.long 0x4 "observer_main_ErrorLogger_0_ErrLog1,"
hexmask.long.word 0x4 0.--15. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error"
group.long 0xFFFFFFFFF710079C++0x3
line.long 0x0 "observer_main_ErrorLogger_0_Reserved_00,"
hexmask.long 0x0 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_00,"
rgroup.long 0xFFFFFFFFF71007A0++0x7
line.long 0x0 "observer_main_ErrorLogger_0_ErrLog3,"
hexmask.long 0x0 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error"
line.long 0x4 "observer_main_ErrorLogger_0_ErrLog4,"
hexmask.long.word 0x4 0.--11. 1. "ERRLOG4,Stores NTTP packet header field Addr (MSBs) of the logged error"
group.long 0xFFFFFFFFF71007A8++0x7
line.long 0x0 "observer_main_ErrorLogger_0_Reserved_01,"
hexmask.long 0x0 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_01,"
line.long 0x4 "observer_main_ErrorLogger_0_Reserved_02,"
hexmask.long 0x4 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_02,"
rgroup.long 0xFFFFFFFFF71007B0++0x3
line.long 0x0 "observer_main_ErrorLogger_0_ErrLog7,"
bitfld.long 0x0 0.--1. "ERRLOG7,Stores NTTP packet header field Security of the logged error" "0,1,2,3"
group.long 0xFFFFFFFFF71007B4++0x4B
line.long 0x0 "observer_main_ErrorLogger_0_Reserved_03,"
hexmask.long 0x0 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_03,"
line.long 0x4 "observer_main_ErrorLogger_0_StallEn,"
bitfld.long 0x4 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1"
line.long 0x8 "observer_main_ErrorLogger_0_Reserved_04,"
hexmask.long 0x8 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_04,"
line.long 0xC "observer_main_ErrorLogger_0_Reserved_05,"
hexmask.long 0xC 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_05,"
line.long 0x10 "observer_main_ErrorLogger_0_Reserved_06,"
hexmask.long 0x10 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_06,"
line.long 0x14 "observer_main_ErrorLogger_0_Reserved_07,"
hexmask.long 0x14 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_07,"
line.long 0x18 "observer_main_ErrorLogger_0_Reserved_08,"
hexmask.long 0x18 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_08,"
line.long 0x1C "observer_main_ErrorLogger_0_Reserved_09,"
hexmask.long 0x1C 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_09,"
line.long 0x20 "observer_main_ErrorLogger_0_Reserved_10,"
hexmask.long 0x20 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_10,"
line.long 0x24 "observer_main_ErrorLogger_0_Reserved_11,"
hexmask.long 0x24 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_11,"
line.long 0x28 "observer_main_ErrorLogger_0_Reserved_12,"
hexmask.long 0x28 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_12,"
line.long 0x2C "observer_main_ErrorLogger_0_Reserved_13,"
hexmask.long 0x2C 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_13,"
line.long 0x30 "observer_main_ErrorLogger_0_Reserved_14,"
hexmask.long 0x30 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_14,"
line.long 0x34 "observer_main_ErrorLogger_0_Reserved_15,"
hexmask.long 0x34 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_15,"
line.long 0x38 "observer_main_ErrorLogger_0_Reserved_16,"
hexmask.long 0x38 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_16,"
line.long 0x3C "observer_main_ErrorLogger_0_Reserved_17,"
hexmask.long 0x3C 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_17,"
line.long 0x40 "observer_main_ErrorLogger_0_Reserved_18,"
hexmask.long 0x40 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_18,"
line.long 0x44 "observer_main_ErrorLogger_0_Reserved_19,"
hexmask.long 0x44 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_19,"
line.long 0x48 "observer_main_ErrorLogger_0_Reserved_20,"
hexmask.long 0x48 0.--31. 1. "observer_main_ErrorLogger_0_Reserved_20,"
rgroup.long 0xFFFFFFFFF7100800++0x7
line.long 0x0 "observer_main_ErrorLogger_1_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "observer_main_ErrorLogger_1_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0xFFFFFFFFF7100808++0x3
line.long 0x0 "observer_main_ErrorLogger_1_FaultEn,"
bitfld.long 0x0 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1"
rgroup.long 0xFFFFFFFFF710080C++0x3
line.long 0x0 "observer_main_ErrorLogger_1_ErrVld,"
bitfld.long 0x0 0. "ERRVLD,1 indicates an error has been logged" "0,1"
group.long 0xFFFFFFFFF7100810++0x3
line.long 0x0 "observer_main_ErrorLogger_1_ErrClr,"
eventfld.long 0x0 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1"
rgroup.long 0xFFFFFFFFF7100814++0x7
line.long 0x0 "observer_main_ErrorLogger_1_ErrLog0,Stores NTTP packet header fields Lock. Opc. ErrCode. Len1 and indicates version of NTTP transport protocol"
bitfld.long 0x0 31. "FORMAT,NTTP transport protocol version" "0,1"
newline
hexmask.long.word 0x0 16.--27. 1. "LEN1,Len1"
newline
bitfld.long 0x0 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 1.--4. 1. "OPC,Opc"
newline
bitfld.long 0x0 0. "LOCK,Lock" "0,1"
line.long 0x4 "observer_main_ErrorLogger_1_ErrLog1,"
hexmask.long.word 0x4 0.--15. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error"
group.long 0xFFFFFFFFF710081C++0x3
line.long 0x0 "observer_main_ErrorLogger_1_Reserved_00,"
hexmask.long 0x0 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_00,"
rgroup.long 0xFFFFFFFFF7100820++0x7
line.long 0x0 "observer_main_ErrorLogger_1_ErrLog3,"
hexmask.long 0x0 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error"
line.long 0x4 "observer_main_ErrorLogger_1_ErrLog4,"
hexmask.long.word 0x4 0.--11. 1. "ERRLOG4,Stores NTTP packet header field Addr (MSBs) of the logged error"
group.long 0xFFFFFFFFF7100828++0x7
line.long 0x0 "observer_main_ErrorLogger_1_Reserved_01,"
hexmask.long 0x0 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_01,"
line.long 0x4 "observer_main_ErrorLogger_1_Reserved_02,"
hexmask.long 0x4 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_02,"
rgroup.long 0xFFFFFFFFF7100830++0x3
line.long 0x0 "observer_main_ErrorLogger_1_ErrLog7,"
bitfld.long 0x0 0.--1. "ERRLOG7,Stores NTTP packet header field Security of the logged error" "0,1,2,3"
group.long 0xFFFFFFFFF7100834++0x4B
line.long 0x0 "observer_main_ErrorLogger_1_Reserved_03,"
hexmask.long 0x0 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_03,"
line.long 0x4 "observer_main_ErrorLogger_1_StallEn,"
bitfld.long 0x4 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1"
line.long 0x8 "observer_main_ErrorLogger_1_Reserved_04,"
hexmask.long 0x8 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_04,"
line.long 0xC "observer_main_ErrorLogger_1_Reserved_05,"
hexmask.long 0xC 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_05,"
line.long 0x10 "observer_main_ErrorLogger_1_Reserved_06,"
hexmask.long 0x10 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_06,"
line.long 0x14 "observer_main_ErrorLogger_1_Reserved_07,"
hexmask.long 0x14 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_07,"
line.long 0x18 "observer_main_ErrorLogger_1_Reserved_08,"
hexmask.long 0x18 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_08,"
line.long 0x1C "observer_main_ErrorLogger_1_Reserved_09,"
hexmask.long 0x1C 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_09,"
line.long 0x20 "observer_main_ErrorLogger_1_Reserved_10,"
hexmask.long 0x20 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_10,"
line.long 0x24 "observer_main_ErrorLogger_1_Reserved_11,"
hexmask.long 0x24 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_11,"
line.long 0x28 "observer_main_ErrorLogger_1_Reserved_12,"
hexmask.long 0x28 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_12,"
line.long 0x2C "observer_main_ErrorLogger_1_Reserved_13,"
hexmask.long 0x2C 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_13,"
line.long 0x30 "observer_main_ErrorLogger_1_Reserved_14,"
hexmask.long 0x30 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_14,"
line.long 0x34 "observer_main_ErrorLogger_1_Reserved_15,"
hexmask.long 0x34 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_15,"
line.long 0x38 "observer_main_ErrorLogger_1_Reserved_16,"
hexmask.long 0x38 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_16,"
line.long 0x3C "observer_main_ErrorLogger_1_Reserved_17,"
hexmask.long 0x3C 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_17,"
line.long 0x40 "observer_main_ErrorLogger_1_Reserved_18,"
hexmask.long 0x40 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_18,"
line.long 0x44 "observer_main_ErrorLogger_1_Reserved_19,"
hexmask.long 0x44 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_19,"
line.long 0x48 "observer_main_ErrorLogger_1_Reserved_20,"
hexmask.long 0x48 0.--31. 1. "observer_main_ErrorLogger_1_Reserved_20,"
rgroup.long 0xFFFFFFFFF7100880++0x7
line.long 0x0 "observer_main_ErrorLogger_2_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "observer_main_ErrorLogger_2_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0xFFFFFFFFF7100888++0x3
line.long 0x0 "observer_main_ErrorLogger_2_FaultEn,"
bitfld.long 0x0 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1"
rgroup.long 0xFFFFFFFFF710088C++0x3
line.long 0x0 "observer_main_ErrorLogger_2_ErrVld,"
bitfld.long 0x0 0. "ERRVLD,1 indicates an error has been logged" "0,1"
group.long 0xFFFFFFFFF7100890++0x3
line.long 0x0 "observer_main_ErrorLogger_2_ErrClr,"
eventfld.long 0x0 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1"
rgroup.long 0xFFFFFFFFF7100894++0x7
line.long 0x0 "observer_main_ErrorLogger_2_ErrLog0,Stores NTTP packet header fields Lock. Opc. ErrCode. Len1 and indicates version of NTTP transport protocol"
bitfld.long 0x0 31. "FORMAT,NTTP transport protocol version" "0,1"
newline
hexmask.long.word 0x0 16.--27. 1. "LEN1,Len1"
newline
bitfld.long 0x0 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 1.--4. 1. "OPC,Opc"
newline
bitfld.long 0x0 0. "LOCK,Lock" "0,1"
line.long 0x4 "observer_main_ErrorLogger_2_ErrLog1,"
hexmask.long.word 0x4 0.--15. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error"
group.long 0xFFFFFFFFF710089C++0x3
line.long 0x0 "observer_main_ErrorLogger_2_Reserved_00,"
hexmask.long 0x0 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_00,"
rgroup.long 0xFFFFFFFFF71008A0++0x7
line.long 0x0 "observer_main_ErrorLogger_2_ErrLog3,"
hexmask.long 0x0 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error"
line.long 0x4 "observer_main_ErrorLogger_2_ErrLog4,"
hexmask.long.word 0x4 0.--11. 1. "ERRLOG4,Stores NTTP packet header field Addr (MSBs) of the logged error"
group.long 0xFFFFFFFFF71008A8++0x7
line.long 0x0 "observer_main_ErrorLogger_2_Reserved_01,"
hexmask.long 0x0 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_01,"
line.long 0x4 "observer_main_ErrorLogger_2_Reserved_02,"
hexmask.long 0x4 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_02,"
rgroup.long 0xFFFFFFFFF71008B0++0x3
line.long 0x0 "observer_main_ErrorLogger_2_ErrLog7,"
bitfld.long 0x0 0.--1. "ERRLOG7,Stores NTTP packet header field Security of the logged error" "0,1,2,3"
group.long 0xFFFFFFFFF71008B4++0x4B
line.long 0x0 "observer_main_ErrorLogger_2_Reserved_03,"
hexmask.long 0x0 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_03,"
line.long 0x4 "observer_main_ErrorLogger_2_StallEn,"
bitfld.long 0x4 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1"
line.long 0x8 "observer_main_ErrorLogger_2_Reserved_04,"
hexmask.long 0x8 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_04,"
line.long 0xC "observer_main_ErrorLogger_2_Reserved_05,"
hexmask.long 0xC 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_05,"
line.long 0x10 "observer_main_ErrorLogger_2_Reserved_06,"
hexmask.long 0x10 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_06,"
line.long 0x14 "observer_main_ErrorLogger_2_Reserved_07,"
hexmask.long 0x14 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_07,"
line.long 0x18 "observer_main_ErrorLogger_2_Reserved_08,"
hexmask.long 0x18 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_08,"
line.long 0x1C "observer_main_ErrorLogger_2_Reserved_09,"
hexmask.long 0x1C 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_09,"
line.long 0x20 "observer_main_ErrorLogger_2_Reserved_10,"
hexmask.long 0x20 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_10,"
line.long 0x24 "observer_main_ErrorLogger_2_Reserved_11,"
hexmask.long 0x24 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_11,"
line.long 0x28 "observer_main_ErrorLogger_2_Reserved_12,"
hexmask.long 0x28 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_12,"
line.long 0x2C "observer_main_ErrorLogger_2_Reserved_13,"
hexmask.long 0x2C 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_13,"
line.long 0x30 "observer_main_ErrorLogger_2_Reserved_14,"
hexmask.long 0x30 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_14,"
line.long 0x34 "observer_main_ErrorLogger_2_Reserved_15,"
hexmask.long 0x34 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_15,"
line.long 0x38 "observer_main_ErrorLogger_2_Reserved_16,"
hexmask.long 0x38 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_16,"
line.long 0x3C "observer_main_ErrorLogger_2_Reserved_17,"
hexmask.long 0x3C 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_17,"
line.long 0x40 "observer_main_ErrorLogger_2_Reserved_18,"
hexmask.long 0x40 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_18,"
line.long 0x44 "observer_main_ErrorLogger_2_Reserved_19,"
hexmask.long 0x44 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_19,"
line.long 0x48 "observer_main_ErrorLogger_2_Reserved_20,"
hexmask.long 0x48 0.--31. 1. "observer_main_ErrorLogger_2_Reserved_20,"
tree.end
tree "CLKMGR (Clock Manager Module)"
base ad:0xFFD10000
group.long 0x0++0x3
line.long 0x0 "ctrl,Contains fields that control the entire Clock Manager."
bitfld.long 0x0 9. "swctrlbtclksel,This bit is only used if swctrlbtclken is set." "0,1"
newline
bitfld.long 0x0 8. "swctrlbtclken,If set  then Software will take control of the boot_clk mux select. If set  then swctrlbtclksel will determine the mux setting. If not set  the security features will determine the fuse settings." "0,1"
newline
bitfld.long 0x0 0. "bootmode,When set the Clock Manager is in Boot Mode." "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "stat,Provides status for Clock Manager including PLL lock and HW Managed Clock State Machine busy."
bitfld.long 0x0 25. "bootclksrc,If 1  the source of boot_clk is cb_intosc_hs_div2_clk. . If 0  the boot_clk source is the external oscillator (EOSC1)." "0,1"
newline
bitfld.long 0x0 24. "bootmode,If 1  the clocks are currently in Boot Mode. If 0  the clocks are not in Boot Mode." "0,1"
newline
bitfld.long 0x0 17. "perf_trans,HP PLL disconnect state transition status. This status is delegated for power state transition between PD and Disconnect for Peripheral PLL." "0,1"
newline
bitfld.long 0x0 16. "perplllocked,PLL lock status which indicates if the HP PLL IP is locked to incoming reference clock within the PPM threshold programmed in the memory registers." "0,1"
newline
bitfld.long 0x0 9. "main_trans,HP PLL disconnect state transition status. This status is delegated for power state transition between PD and Disconnect for Main PLL." "0,1"
newline
bitfld.long 0x0 8. "mainplllocked,PLL lock status which indicates if the HP PLL IP is locked to incoming reference clock within the PPM threshold programmed in the memory registers." "0,1"
newline
bitfld.long 0x0 0. "busy,This read only bit indicates that the Hardware Managed clock's state machine is active. If the state machine is active  then the clocks are in transition. Software should poll this bit after changing the source of internal clocks when changing.." "0,1"
group.long 0x8++0xB
line.long 0x0 "testioctrl,Contains fields setting the IO output select for Test Clock and Debug outputs."
bitfld.long 0x0 16. "debugclksel,Selects the source of PLL_lock for debug purpose." "0,1"
newline
bitfld.long 0x0 8.--9. "periclksel,Selects between Channel 0  Channel 1  Channel2 and Channel 3 of the peripheral PLL." "0: periph PLL C0,1: periph PLL C1,2: periph PLL C2,3: periph PLL C3"
newline
bitfld.long 0x0 0.--1. "mainclksel,Selects between Channel 0  Channel 1  Channel 2 and Channel 3 of the main PLL." "0: main PLL C0,1: main PLL C1,2: main PLL C2,3: main PLL C3"
line.long 0x4 "intrgen,Global Interrupt Enable"
bitfld.long 0x4 0. "en," "0,1"
line.long 0x8 "intrmsk,Interrupt Mask"
bitfld.long 0x8 3. "perlocklost,To mask lock lost interrupt from periph PLL" "0,1"
newline
bitfld.long 0x8 2. "mainlocklost,To mask lock lost interrupt from main PLL" "0,1"
newline
bitfld.long 0x8 1. "perlockachieved,To mask lock achieved interrupt from periph PLL" "0,1"
newline
bitfld.long 0x8 0. "mainlockachieved,To mask lock achieved interrupt from main PLL" "0,1"
wgroup.long 0x14++0x3
line.long 0x0 "intrclr,Interrupt Clear."
eventfld.long 0x0 3. "perlocklost,This is used to clear sticky periph PLL lock lost signal." "0,1"
newline
eventfld.long 0x0 2. "mainlocklost,This is used to clear sticky main PLL lock lost signal." "0,1"
newline
eventfld.long 0x0 1. "perlockachieved,This is used to clear sticky periph PLL lock achieved signal." "0,1"
newline
eventfld.long 0x0 0. "mainlockachieved,This is used to clear sticky main PLL lock achieved signal." "0,1"
rgroup.long 0x18++0xB
line.long 0x0 "intrsts,Interrupt Pending Status after the interrupt masks."
bitfld.long 0x0 3. "perlocklost,Pending status for periph PLL lock lost interrupt after intr mask" "0,1"
newline
bitfld.long 0x0 2. "mainlocklost,Pending status for main PLL lock lost interrupt after intr mask" "0,1"
newline
bitfld.long 0x0 1. "perlockachieved,Pending status for periph PLL lock achieved interrupt after intr mask" "0,1"
newline
bitfld.long 0x0 0. "mainlockachieved,Pending status for main PLL lock achieved interrupt after intr mask" "0,1"
line.long 0x4 "intrstk,Interrupt Pending Status without considering the interrupt masks."
bitfld.long 0x4 3. "perlocklost,Pending status for periph PLL lock lost interrupt before intr mask" "0,1"
newline
bitfld.long 0x4 2. "mainlocklost,Pending status for main PLL lock lost interrupt before intr mask" "0,1"
newline
bitfld.long 0x4 1. "perlockachieved,Pending status for periph PLL lock achieved interrupt before intr mask" "0,1"
newline
bitfld.long 0x4 0. "mainlockachieved,Pending status for main PLL lock achieved interrupt before intr mask" "0,1"
line.long 0x8 "intrraw,Realtime Status of the bits which could have caused interrupt."
bitfld.long 0x8 3. "perlocklost,Raw signal (before masking) for periph PLL lock lost. It comed from clock manager" "0,1"
newline
bitfld.long 0x8 2. "mainlocklost,Raw signal (before masking) for main PLL lock lost. It comed from clock manager" "0,1"
newline
bitfld.long 0x8 1. "perlockachieved,Raw signal (before masking) for periph PLL lock achieved. It comed from clock manager" "0,1"
newline
bitfld.long 0x8 0. "mainlockachieved,Raw signal (before masking) for main PLL lock achieved. It comed from clock manager" "0,1"
group.long 0x24++0x2F
line.long 0x0 "en,Contains fields that control clock enables for Main Clocks."
bitfld.long 0x0 6. "s2fuser0clken,Enables clock s2f_user0_clk output" "0,1"
newline
bitfld.long 0x0 5. "cstimerclken,Enables Debug Timer Clock output (cs_timer_clk)" "0,1"
newline
bitfld.long 0x0 4. "csclken,Enables Debug Clock outputs (cs_at_clk  cs_pdbg_clk  and cs_trace_clk)" "0,1"
newline
bitfld.long 0x0 3. "l4spclken,Enables clock l4_sp_clk output" "0,1"
newline
bitfld.long 0x0 2. "l4mpclken,Enables clock l4_mp_clk output" "0,1"
newline
bitfld.long 0x0 1. "l4mainclken,Enables clock l4_main_clk output" "0,1"
newline
bitfld.long 0x0 0. "mpuclken,Enable for MPU Clock Group (mpu_clk  mpu_l2ram_clk and mpu_periph_clk)." "0,1"
line.long 0x4 "ens,Write One to Set correspondng fields in the Enable Register."
bitfld.long 0x4 6. "s2fuser0clken,Enables clock s2f_user0_clk output" "0,1"
newline
bitfld.long 0x4 5. "cstimerclken,Enables Debug Timer Clock output (cs_timer_clk)" "0,1"
newline
bitfld.long 0x4 4. "csclken,Enables Debug Clock outputs (cs_at_clk  cs_pdbg_clk and cs_trace_clk)" "0,1"
newline
bitfld.long 0x4 3. "l4spclken,Enables clock l4_sp_clk output" "0,1"
newline
bitfld.long 0x4 2. "l4mpclken,Enables clock l4_mp_clk output" "0,1"
newline
bitfld.long 0x4 1. "l4mainclken,Enables clock l4_main_clk output" "0,1"
newline
bitfld.long 0x4 0. "mpuclken,Enable for MPU Clock Group (mpu_clk  mpu_l2ram_clk and mpu_periph_clk)." "0,1"
line.long 0x8 "enr,Write One to Clear corresponding fields in Enable Register."
eventfld.long 0x8 6. "s2fuser0clken,Enables clock s2f_user0_clk output" "0,1"
newline
eventfld.long 0x8 5. "cstimerclken,Enables Debug Timer Clock output (cs_timer_clk)" "0,1"
newline
eventfld.long 0x8 4. "csclken,Enables Debug Clock outputs (cs_at_clk  cs_pdbg_clk and cs_trace_clk)" "0,1"
newline
eventfld.long 0x8 3. "l4spclken,Enables clock l4_sp_clk output" "0,1"
newline
eventfld.long 0x8 2. "l4mpclken,Enables clock l4_mp_clk output" "0,1"
newline
eventfld.long 0x8 1. "l4mainclken,Enables clock l4_main_clk output" "0,1"
newline
eventfld.long 0x8 0. "mpuclken,Enable for MPU Clock Group (mpu_clk  mpu_l2ram_clk and mpu_periph_clk)." "0,1"
line.long 0xC "bypass,Contains fields that control bypass for clocks derived from the Main PLL."
bitfld.long 0xC 2. "s2fuser0,If set  the s2f_user0_clk will be bypassed to the boot_clk." "0,1"
newline
bitfld.long 0xC 1. "noc,If set  the NOC clock group will be bypassed to boot_clk." "0,1"
newline
bitfld.long 0xC 0. "mpu,If set  the MPU clock group will be bypassed to the boot_clk." "0,1"
line.long 0x10 "bypasss,Write One to Set corresponding fields in Bypass Register."
bitfld.long 0x10 2. "s2fuser0,If set  the s2f_user0_clk will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
bitfld.long 0x10 1. "noc,If set  the NOC clock group will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
bitfld.long 0x10 0. "mpu,If set  the MPU clock group will be bypassed to the input clock reference of the Main PLL." "0,1"
line.long 0x14 "bypassr,Write One to Clear corresponding fields in Bypass Register."
eventfld.long 0x14 2. "s2fuser0,If set  the s2f_user0_clk will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
eventfld.long 0x14 1. "noc,If set  the NOC clock group will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
eventfld.long 0x14 0. "mpu,If set  the MPU clock group will be bypassed to the input clock reference of the Main PLL." "0,1"
line.long 0x18 "mpuclk,Contains settings that control clock mpu_clk generated from the Main PLL VCO clock."
bitfld.long 0x18 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
newline
hexmask.long.word 0x18 0.--10. 1. "cnt,Divides the VCO/2 frequency by the value+1 in this field."
line.long 0x1C "nocclk,Contains settings that control clock main_clk generated from the Main PLL VCO clock."
bitfld.long 0x1C 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
line.long 0x20 "nocdiv,Contains fields that control clock dividers for NoC Clocks."
bitfld.long 0x20 28. "cspdbgclk,The external cs_pdbg_clk divider is specified in this field. This divider is cascaded after the cs_at_clk external divider." "0,1"
newline
bitfld.long 0x20 26.--27. "cstraceclk,The external cs_trace_clk divider is specified in this field. The cs_trace_clk is used by the actual trace interface to the debugger. This divider is cascaded after the cs_at_clk external divider." "0,1,2,3"
newline
bitfld.long 0x20 24.--25. "csclk,The external cs_at_clk divider is specified in this field." "0,1,2,3"
newline
bitfld.long 0x20 16.--17. "l4spclk,The external l4_sp_clk divider is specified in this field." "0,1,2,3"
newline
bitfld.long 0x20 8.--9. "l4mpclk,The external l4_mp_clk divider is specified in this field." "0,1,2,3"
newline
bitfld.long 0x20 0.--1. "l4mainclk,The external l4_main_clk divider is specified in this field." "0,1,2,3"
line.long 0x24 "pllglob,This refects register settings for all the channels of the main PLL"
bitfld.long 0x24 29. "clr_lostlock_bypass,if lostlock_bypass_en is set and the PLL looses lock  channel bypass signal is asserted by HW." "0: no effect on PLL lostlock bypass mode,1: Clear PLL's lostlock bypass mode"
newline
bitfld.long 0x24 28. "lostlock_bypass_en,When PLL looses lock  the PLL output clocks are muted. Clock manager will not have any clock to recover or even process lostlock interrupt. This bit when set will enable the main PLL to give keepalive clock at the output upon loosing.." "0: Turns OFF bypass to keepalive clock feature upon..,1: Turns on bypass to keepalive clock feature upon.."
newline
hexmask.long.byte 0x24 24.--27. 1. "modclkdiv,Reference clock divider control; the decimal value of this register will be the divider settings. Setting 0 will"
newline
bitfld.long 0x24 21. "fastrefclk,HP PLL fast reference clock mode control." "0,1"
newline
bitfld.long 0x24 20. "disctrl,Disconnect clock disable control. It is used to glitchlessly disable all keepalive clock in disconnect state." "0,1"
newline
bitfld.long 0x24 19. "clksync,Clock slice output synchronization request control. Once asserted  the positive edge of all enabled clock slices will be aligned." "0,1"
newline
bitfld.long 0x24 18. "pwrgatectrl,HP PLL Internal Power-gated State Control" "0,1"
newline
bitfld.long 0x24 16.--17. "psrc,Controls the VCO input clock source." "0,1,2,3"
newline
bitfld.long 0x24 12.--13. "drefclkdiv,Reference clock divider control used by the DPLL. The effective divider value is 2^(ictl_pll_drefdiv_nt_[1:0])." "0,1,2,3"
newline
hexmask.long.byte 0x24 8.--11. 1. "arefclkdiv,Reference clock divider control; the decimal value of this register will be the divider settings. Setting 0 will"
newline
bitfld.long 0x24 1. "rst_n,Power-On Reset. Used to initialize memory and reset the Power Management Unit (PMU). The minimum POR assertion time required is 0.5 us." "0,1"
newline
bitfld.long 0x24 0. "pd_n,Keepalive clock power down control" "0,1"
line.long 0x28 "fdbck,VCO freq register counters"
hexmask.long.tbyte 0x28 0.--23. 1. "fdiv,Fractional synthesizer center frequency control word."
line.long 0x2C "mem,Registers dealing with PLL internal memory access."
rbitfld.long 0x2C 26. "err,Memory Error Status Signal." "0,1"
newline
bitfld.long 0x2C 25. "wr,Memory Read/Write Operation." "0,1"
newline
bitfld.long 0x2C 24. "req,Memory Request Signal" "0,1"
newline
hexmask.long.byte 0x2C 16.--23. 1. "wdat,Memory 'Write' Data bus."
newline
hexmask.long.word 0x2C 0.--15. 1. "addr,PLL Memory Address"
rgroup.long 0x54++0x3
line.long 0x0 "memstat,Main PLL memstatus register. contains memory read data"
hexmask.long.byte 0x0 0.--7. 1. "rdata,Memory Read Data Bus"
group.long 0x58++0x4F
line.long 0x0 "pllc0,Channel C0 frequency settings for the main PLL"
rbitfld.long 0x0 29. "stat,HP PLL state transition status for clk_slice_0." "0,1"
newline
bitfld.long 0x0 28. "mute,Mutes PLL clock_slice_0 outputs without any glitch:" "0,1"
newline
bitfld.long 0x0 27. "en,PLL channel 0 output enable;" "0,1"
newline
bitfld.long 0x0 26. "bypas,PLL channel 0 output bypass. Before lock  it is muted  regardless of its value." "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "div,The ock_pll_clkslice_0 divider ratio in binary code."
line.long 0x4 "pllc1,Channel C1 frequency settings for the main PLL"
rbitfld.long 0x4 29. "stat,HP PLL state transition status for clk_slice_1." "0,1"
newline
bitfld.long 0x4 28. "mute,Mutes PLL clock_slice_1 outputs without any glitch:" "0,1"
newline
bitfld.long 0x4 27. "en,PLL channel 1 output enable;" "0,1"
newline
bitfld.long 0x4 26. "bypas,PLL channel 1 output bypass. Before lock  it is muted  regardless of its value." "0,1"
newline
hexmask.long.word 0x4 0.--10. 1. "div,The ock_pll_clkslice_1 divider ratio in binary code."
line.long 0x8 "vcocalib,VCO calibration control registers."
bitfld.long 0x8 27. "clr,HP PLL calibration clear control." "0,1"
newline
bitfld.long 0x8 25.--26. "banksel,Controls the calibration bank that will be used to store  restore or clear HP PLL calibration code." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--23. 1. "mscnt,ictl_pll_calvcomeascount_nt_[7:0] = 100/(Fvco/Fref_ effective_digital)"
newline
hexmask.long.word 0x8 0.--9. 1. "hscnt,VCO calibration parameter:"
line.long 0xC "pllc2,Channel C2 frequency settings for the main PLL"
rbitfld.long 0xC 29. "stat,HP PLL state transition status for clk_slice_2." "0,1"
newline
bitfld.long 0xC 28. "mute,Mutes PLL clock_slice_2 outputs without any glitch:" "0,1"
newline
bitfld.long 0xC 27. "en,PLL channel 2 output enable;" "0,1"
newline
bitfld.long 0xC 26. "bypas,PLL channel 2 output bypass. Before lock  it is muted  regardless of its value." "0,1"
newline
hexmask.long.word 0xC 0.--10. 1. "div,The ock_pll_clkslice_2 divider ratio in binary code."
line.long 0x10 "pllc3,Channel C3 frequency settings for the main PLL"
rbitfld.long 0x10 29. "stat,HP PLL state transition status for clk_slice_3." "0,1"
newline
bitfld.long 0x10 28. "mute,Mutes PLL clock_slice_3 outputs without any glitch:" "0,1"
newline
bitfld.long 0x10 27. "en,PLL channel 3 output enable;" "0,1"
newline
bitfld.long 0x10 26. "bypas,PLL channel 3 output bypass. Before lock  it is muted  regardless of its value." "0,1"
newline
hexmask.long.word 0x10 0.--10. 1. "div,The ock_pll_clkslice_3 divider ratio in binary code."
line.long 0x14 "pllm,Feedback Clock Divider Control (VCO Frequency Register Counters)"
hexmask.long.word 0x14 0.--9. 1. "mdiv,Feedback clock divider. The HP PLL IP will initial operate at the frequency based on the Mdiv and Fdiv values set at PD state. It can be only set while the HP PLL IP is at Reset or PD state."
line.long 0x18 "fhop,Frequency Hopping (FHOP)/Dynamic Frequency Scaling(DFS) Control and status register."
rbitfld.long 0x18 16. "ack,Asynchronous output. Acknowledge signal for the frequency ramp." "0,1"
newline
bitfld.long 0x18 8. "req,Request the HP PLL IP to perform the configured FHOP." "0,1"
newline
bitfld.long 0x18 0.--1. "dir,One-hot encoded." "0,1,2,3"
line.long 0x1C "ssc,Spread Spectrum Clocking (SSC) Control and Status Registers."
rbitfld.long 0x1C 8. "stat,Indicates whether SSC is running." "0,1"
newline
bitfld.long 0x1C 0. "en,Enables/Disables SSC." "0,1"
line.long 0x20 "lostlock,"
eventfld.long 0x20 0. "bypass_cleared,When all the bypass_en asserted due to loss of PLL lock from all the channels go low this bit gets set to 1." "0,1"
line.long 0x24 "en,Contains fields that control clock enables for clocks derived from the Peripheral PLL."
bitfld.long 0x24 10. "nandclken,Enables NAND peripheral clock. This enable goes outside of the Clock Manger to the NAND directly." "0,1"
newline
bitfld.long 0x24 9. "spimclken,Enables SPI Master peripheral clock. This enable goes outside of the Clock Manger to the SPIM directly." "0,1"
newline
bitfld.long 0x24 8. "usbclken,Enables USB peripheral clock. This enable goes outside of the Clock Manger to the USB directly." "0,1"
newline
bitfld.long 0x24 7. "psiclken,Enables psi_ref clock." "0,1"
newline
bitfld.long 0x24 6. "s2fuser1clken,Enables clock s2f_user1_clk output" "0,1"
newline
bitfld.long 0x24 5. "sdmmcclken,Enables SDMMC peripheral clock. This enable goes outside of the Clock Manger to the SDMMC directly." "0,1"
newline
bitfld.long 0x24 4. "gpiodben,Enables clock gpio_db_clk output" "0,1"
newline
bitfld.long 0x24 3. "emacptpen,Enables clock emac_ptp_clk output" "0,1"
newline
bitfld.long 0x24 2. "emac2en,Enables clock emac2_clk output" "0,1"
newline
bitfld.long 0x24 1. "emac1en,Enables clock emac1_clk output" "0,1"
newline
bitfld.long 0x24 0. "emac0en,Enables clock emac0_clk output" "0,1"
line.long 0x28 "ens,Write One to Set corresonding fields in Enable Register."
bitfld.long 0x28 10. "nandclken,Enables NAND peripheral clock. This enable goes outside of the Clock Manger to the NAND directly." "0,1"
newline
bitfld.long 0x28 9. "spimclken,Enables SPI Master peripheral clock. This enable goes outside of the Clock Manger to the SPIM directly." "0,1"
newline
bitfld.long 0x28 8. "usbclken,Enables USB peripheral clock. This enable goes outside of the Clock Manger to the USB directly." "0,1"
newline
bitfld.long 0x28 7. "psiclken,Enables psi_ref clock." "0,1"
newline
bitfld.long 0x28 6. "s2fuser1clken,Enables clock s2f_user1_clk output" "0,1"
newline
bitfld.long 0x28 5. "sdmmcclken,Enables SDMMC peripheral clock. This enable goes outside of the Clock Manger to the SDMMC directly." "0,1"
newline
bitfld.long 0x28 4. "gpiodben,Enables clock gpio_db_clk output" "0,1"
newline
bitfld.long 0x28 3. "emacptpen,Enables clock emac_ptp_clk output" "0,1"
newline
bitfld.long 0x28 2. "emac2en,Enables clock emac2_clk output" "0,1"
newline
bitfld.long 0x28 1. "emac1en,Enables clock emac1_clk output" "0,1"
newline
bitfld.long 0x28 0. "emac0en,Enables clock emac0_clk output" "0,1"
line.long 0x2C "enr,Write One to Clear corresponding fields in Enable Register."
eventfld.long 0x2C 10. "nandclken,Enables NAND peripheral clock. This enable goes outside of the Clock Manger to the NAND directly." "0,1"
newline
eventfld.long 0x2C 9. "spimclken,Enables SPI Master peripheral clock. This enable goes outside of the Clock Manger to the SPIM directly." "0,1"
newline
eventfld.long 0x2C 8. "usbclken,Enables USB peripheral clock. This enable goes outside of the Clock Manger to the USB directly." "0,1"
newline
eventfld.long 0x2C 7. "psiclken,Enables psi_ref clock." "0,1"
newline
eventfld.long 0x2C 6. "s2fuser1clken,Enables clock s2f_user1_clk output" "0,1"
newline
eventfld.long 0x2C 5. "sdmmcclken,Enables SDMMC peripheral clock. This enable goes outside of the Clock Manger to the SDMMC directly." "0,1"
newline
eventfld.long 0x2C 4. "gpiodben,Enables clock gpio_db_clk output" "0,1"
newline
eventfld.long 0x2C 3. "emacptpen,Enables clock emac_ptp_clk output" "0,1"
newline
eventfld.long 0x2C 2. "emac2en,Enables clock emac2_clk output" "0,1"
newline
eventfld.long 0x2C 1. "emac1en,Enables clock emac1_clk output" "0,1"
newline
eventfld.long 0x2C 0. "emac0en,Enables clock emac0_clk output" "0,1"
line.long 0x30 "bypass,Contains fields that control bypass for clocks derived from the Peripheral PLL."
bitfld.long 0x30 6. "psiref,If set  the psi_ref_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x30 5. "s2fuser1,If set  the s2f_user1_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x30 4. "sdmmc,If set  the sdmmc_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x30 3. "gpiodb,If set  the gpio_db_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x30 2. "emacptp,If set  the emac_ptp_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x30 1. "emacb,If set  the emacb_free_clk will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
bitfld.long 0x30 0. "emaca,If set  the emaca_free_clk will be bypassed to the input clock reference of the Main PLL." "0,1"
line.long 0x34 "bypasss,Write One to Set corresponding fields in Bypass Register."
bitfld.long 0x34 6. "psiref,If set  the psi_ref_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x34 5. "s2fuser1,If set  the s2f_user1_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x34 4. "sdmmc,If set  the sdmmc_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x34 3. "gpiodb,If set  the gpio_db_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x34 2. "emacptp,If set  the emac_ptp_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x34 1. "emacb,If set  the emacb_free_clk will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
bitfld.long 0x34 0. "emaca,If set  the emaca_free_clk will be bypassed to the input clock reference of the Periphal PLL." "0,1"
line.long 0x38 "bypassr,Write One to Clear corresponding fields in Bypass Register."
eventfld.long 0x38 6. "psiref,If set  the psi_ref_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
eventfld.long 0x38 5. "s2fuser1,If set  the s2f_user1_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
eventfld.long 0x38 4. "sdmmc,If set  the sdmmc_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
eventfld.long 0x38 3. "gpiodb,If set  the gpio_db_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
eventfld.long 0x38 2. "emacptp,If set  the emac_ptp_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
eventfld.long 0x38 1. "emacb,If set  the emacb_free_clk will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
eventfld.long 0x38 0. "emaca,If set  the emaca_free_clk will be bypassed to the input clock reference of the Periphal PLL." "0,1"
line.long 0x3C "emacctl,Contains fields that control clock dividers for main clocks derived from the Main PLL"
bitfld.long 0x3C 28. "emac2sel,Selects the source for emac2_clk as either emaca_free_clk or emacb_free_clk." "0,1"
newline
bitfld.long 0x3C 27. "emac1sel,Selects the source for emac1_clk as either emaca_free_clk or emacb_free_clk." "0,1"
newline
bitfld.long 0x3C 26. "emac0sel,Selects the source for emac0_clk as either emaca_free_clk or emacb_free_clk." "0,1"
line.long 0x40 "gpiodiv,Contains a field that controls the clock divider for the GPIO De-bounce clock."
hexmask.long.word 0x40 0.--15. 1. "gpiodbclk,The gpio_db_clk is divided down from the periph_base_clk by the value plus one specified in this field. The value 0 (divide by 1) is illegal. A value of 1 indicates divide by 2  2 divide by 3  etc."
line.long 0x44 "pllglob,This refects register settings for all clock channels of peripheral PLL."
bitfld.long 0x44 29. "clr_lostlock_bypass,if lostlock_bypass_en is set and the PLL looses lock  channel bypass signal is asserted by HW." "0: no effect on PLL lostlock bypass mode,1: Clear PLL's lostlock bypass mode"
newline
bitfld.long 0x44 28. "lostlock_bypass_en,When PLL looses lock  the PLL output clocks are muted." "0: Turns OFF bypass to keepalive clock feature upon..,1: Turns on bypass to keepalive clock feature upon.."
newline
hexmask.long.byte 0x44 24.--27. 1. "modclkdiv,Reference clock divider control; the decimal value of this register will be the divider settings. Setting 0 will"
newline
bitfld.long 0x44 21. "fastrefclk,HP PLL fast reference clock mode control." "0,1"
newline
bitfld.long 0x44 20. "disctrl,Disconnect clock disable control. It is used to glitchlessly disable all keepalive clock in disconnect state." "0,1"
newline
bitfld.long 0x44 19. "clksync,Clock slice output synchronization request control. Once asserted  the positive edge of all enabled clock slices will be aligned." "0,1"
newline
bitfld.long 0x44 18. "pwrgatectrl,HP PLL Internal Power-gated State Control" "0,1"
newline
bitfld.long 0x44 16.--17. "psrc,Controls the VCO input clock source." "0,1,2,3"
newline
bitfld.long 0x44 12.--13. "drefclkdiv,Reference clock divider control used by the DPLL. The effective divider value is 2^(ictl_pll_drefdiv_nt_[1:0])." "0,1,2,3"
newline
hexmask.long.byte 0x44 8.--11. 1. "arefclkdiv,Reference clock divider control; the decimal value of this register will be the divider settings. Setting 0 will gate the clock coming out from the divider."
newline
bitfld.long 0x44 1. "rst_n,Power-On Reset. Used to initialize memory and reset the Power Management Unit (PMU). The minimum POR assertion time required is 0.5 us." "0,1"
newline
bitfld.long 0x44 0. "pd_n,Keepalive clock power down control" "0,1"
line.long 0x48 "fdbck,VCO freq register counters"
hexmask.long.tbyte 0x48 0.--23. 1. "fdiv,Fractional synthesizer center frequency control word."
line.long 0x4C "mem,Registers dealing with PLL internal memory access."
rbitfld.long 0x4C 26. "err,Memory Error Status Signal. It will be asserted if invalid address is accessed" "0,1"
newline
bitfld.long 0x4C 25. "wr,Memory Read/Write Operation." "0,1"
newline
bitfld.long 0x4C 24. "req,Memory Request Signal" "0,1"
newline
hexmask.long.byte 0x4C 16.--23. 1. "wdat,Memory 'Write' Data bus."
newline
hexmask.long.word 0x4C 0.--15. 1. "addr,PLL Memory Address"
rgroup.long 0xA8++0x3
line.long 0x0 "memstat,Periph PLL memstatus register. contains ack and memory read data"
hexmask.long.byte 0x0 0.--7. 1. "rdata,Memory Read Data"
group.long 0xAC++0x4B
line.long 0x0 "pllc0,Channel C0 frequency settings for the peri PLL"
rbitfld.long 0x0 29. "stat,HP PLL state transition status for clk_slice_0." "0,1"
newline
bitfld.long 0x0 28. "mute,Mutes PLL clock_slice_0 outputs without any glitch:" "0,1"
newline
bitfld.long 0x0 27. "en,PLL channel 0 output enable;" "0,1"
newline
bitfld.long 0x0 26. "bypas,PLL channel 0 output bypass. Before lock  it is muted  regardless of its value." "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "div,The ock_pll_clkslice_0 divider ratio in binary code."
line.long 0x4 "pllc1,Channel C1 frequency settings for the peri PLL"
rbitfld.long 0x4 29. "stat,HP PLL state transition status for clk_slice_1." "0,1"
newline
bitfld.long 0x4 28. "mute,Mutes PLL clock_slice_1 outputs without any glitch:" "0,1"
newline
bitfld.long 0x4 27. "en,PLL channel 1 output enable;" "0,1"
newline
bitfld.long 0x4 26. "bypas,PLL channel 1 output bypass. Before lock  it is muted  regardless of its value." "0,1"
newline
hexmask.long.word 0x4 0.--10. 1. "div,The ock_pll_clkslice_1 divider ratio in binary code."
line.long 0x8 "vcocalib,VCO calibration control registers."
bitfld.long 0x8 27. "clr,HP PLL calibration clear control." "0,1"
newline
bitfld.long 0x8 25.--26. "banksel,Controls the calibration bank that will be used to store  restore or clear HP PLL calibration code." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--23. 1. "mscnt,ictl_pll_calvcomeascount_nt_[7:0] = 100/(Fvco/Fref_ effective_digital)"
newline
hexmask.long.word 0x8 0.--9. 1. "hscnt,VCO calibration parameter:"
line.long 0xC "pllc2,Channel C2 frequency settings for the peri PLL"
rbitfld.long 0xC 29. "stat,HP PLL state transition status for clk_slice_2." "0,1"
newline
bitfld.long 0xC 28. "mute,Mutes PLL clock_slice_2 outputs without any glitch:" "0,1"
newline
bitfld.long 0xC 27. "en,PLL channel 2 output enable." "0,1"
newline
bitfld.long 0xC 26. "bypas,PLL channel 2 output bypass. Before lock  it is muted  regardless of its value." "0,1"
newline
hexmask.long.word 0xC 0.--10. 1. "div,The ock_pll_clkslice_2 divider ratio in binary code."
line.long 0x10 "pllc3,Channel C3 frequency settings for the peri PLL"
rbitfld.long 0x10 29. "stat,HP PLL state transition status for clk_slice_3." "0,1"
newline
bitfld.long 0x10 28. "mute,Mutes PLL clock_slice_3 outputs without any glitch:" "0,1"
newline
bitfld.long 0x10 27. "en,PLL channel 3 output enable;" "0,1"
newline
bitfld.long 0x10 26. "bypas,PLL channel 3 output bypass. Before lock  it is muted  regardless of its value." "0,1"
newline
hexmask.long.word 0x10 0.--10. 1. "div,The ock_pll_clkslice_3 divider ratio in binary code."
line.long 0x14 "pllm,Feedback Clock Divider Control (VCO Frequency Register Counters)"
hexmask.long.word 0x14 0.--9. 1. "mdiv,Feedback clock divider. The HP PLL IP will initial operate at the frequency based on the Mdiv and Fdiv values set at PD state. It can be only set while the HP PLL IP is at Reset or PD state."
line.long 0x18 "fhop,Frequency Hopping (FHOP)/Dynamic Frequency Scaling(DFS) Control and status register."
rbitfld.long 0x18 16. "ack,Asynchronous output. Acknowledge signal for the frequency ramp." "0,1"
newline
bitfld.long 0x18 8. "req,Request the HP PLL IP to perform the configured FHOP." "0,1"
newline
bitfld.long 0x18 0.--1. "dir,One-hot encoded." "0,1,2,3"
line.long 0x1C "ssc,Spread Spectrum Clocking (SSC) Control and Status Registers."
rbitfld.long 0x1C 8. "stat,Indicates whether SSC is running." "0,1"
newline
bitfld.long 0x1C 0. "en,Enables/Disables SSC." "0,1"
line.long 0x20 "lostlock,"
eventfld.long 0x20 0. "bypass_cleared,When all the bypass_en asserted due to loss of PLL lock from all the channels go low this bit gets set to 1." "0,1"
line.long 0x24 "jtag,Jtag control registers for the PLLs - Testing Access"
bitfld.long 0x24 8. "rst,Jtag rst signal." "0,1"
newline
hexmask.long.byte 0x24 0.--7. 1. "id,JTAG ID used to provide each HP PLL IP a unique ID."
line.long 0x28 "emacactr,Contains settings that control emaca_free_clk generated from the Main PLL VCO clock."
bitfld.long 0x28 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
newline
hexmask.long.word 0x28 0.--10. 1. "cnt,Divides the VCO frequency by the value+1 in this field."
line.long 0x2C "emacbctr,Contains settings that control emacb_free_clk generated from the Main PLL VCO clock."
bitfld.long 0x2C 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
newline
hexmask.long.word 0x2C 0.--10. 1. "cnt,Divides the VCO frequency by the value+1 in this field."
line.long 0x30 "emacptpctr,Contains settings that control emac_ptp_free_clk generated from the Main PLL VCO clock."
bitfld.long 0x30 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
newline
hexmask.long.word 0x30 0.--10. 1. "cnt,Divides the VCO frequency by the value+1 in this field."
line.long 0x34 "gpiodbctr,Contains settings that control gpio_db_free_clk generated from the Peripheral PLL VCO clock."
bitfld.long 0x34 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
newline
hexmask.long.word 0x34 0.--10. 1. "cnt,Divides the VCO frequency by the value+1 in this field."
line.long 0x38 "sdmmcctr,Contains settings that control sdmmc_free_clk generated from the Peripheral PLL VCO clock."
bitfld.long 0x38 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
newline
hexmask.long.word 0x38 0.--10. 1. "cnt,Divides the VCO frequency by the value+1 in this field."
line.long 0x3C "s2fuser0ctr,Contains settings that control s2f_user0_free_clk generated from Main PLL VCO Clock."
bitfld.long 0x3C 16.--18. "src,Selects the source for the active 5:1 clock for s2f clock slice when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock for s2f clock slice when the PLL is not..,?,?"
newline
hexmask.long.word 0x3C 0.--10. 1. "cnt,Division setting for ping pong counter in clock slice. Divides the s2f_free_clk frequence by this value + 1."
line.long 0x40 "s2fuser1ctr,Contains settings that control s2f_user1_free_clk generated from Main PLL VCO Clock."
bitfld.long 0x40 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
newline
hexmask.long.word 0x40 0.--10. 1. "cnt,Divides the VCO frequency by the value+1 in this field."
line.long 0x44 "psirefctr,Contains settings that control psi_ref_free_clk generated from the Main PLL VCO clock."
bitfld.long 0x44 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
newline
hexmask.long.word 0x44 0.--10. 1. "cnt,Divides the VCO frequency by the value+1 in this field."
line.long 0x48 "extcntrst,Used to hold associated pingpong counter in reset while PLL and 5:1 mux configuration is changed."
bitfld.long 0x48 7. "psirefcntrst,This bit holds the associated psi_ref external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
newline
bitfld.long 0x48 6. "s2fuser1cntrst,This bit holds the associated s2f_user1 external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
newline
bitfld.long 0x48 5. "s2fuser0cntrst,This bit holds the associated s2f_user0 external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
newline
bitfld.long 0x48 4. "sdmmccntrst,This bit holds the associated sdmmc external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
newline
bitfld.long 0x48 3. "gpiodbcntrst,This bit holds the associated gpio_db external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
newline
bitfld.long 0x48 2. "emacptpcntrst,This bit holds the associated emac_ptp external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
newline
bitfld.long 0x48 1. "emacbcntrst,This bit holds the associated emacb external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
newline
bitfld.long 0x48 0. "emacacntrst,This bit holds the associated emaca external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
tree.end
tree "DDRREG (DDR Scheduler and Hard Memory Controller Configuration Register)"
base ad:0x0
tree "FPGA2SDRAM_FIREWALL"
base ad:0xF8020100
group.long 0x0++0x3
line.long 0x0 "enable,Enable"
bitfld.long 0x0 3. "region3enable,Region 3 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 2. "region2enable,Region 2 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 1. "region1enable,Region 1 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 0. "region0enable,Region 0 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
wgroup.long 0x4++0x7
line.long 0x0 "enable_set,Sets Master Region Enable field when written with 1"
bitfld.long 0x0 3. "region3enable,Region 3 Enable Set." "0,1"
bitfld.long 0x0 2. "region2enable,Region 2 Enable Set." "0,1"
bitfld.long 0x0 1. "region1enable,Region 1 Enable Set." "0,1"
bitfld.long 0x0 0. "region0enable,Region 0 Enable Set." "0,1"
line.long 0x4 "enable_clear,Clears Master Region Enable field when written with 1"
eventfld.long 0x4 3. "region3enable,Region 3 Enable Clear." "0,1"
eventfld.long 0x4 2. "region2enable,Region 2 Enable Clear." "0,1"
eventfld.long 0x4 1. "region1enable,Region 1 Enable Clear." "0,1"
eventfld.long 0x4 0. "region0enable,Region 0 Enable Clear." "0,1"
group.long 0x10++0x3F
line.long 0x0 "region0addr_base,Base definition for Region 0"
hexmask.long.word 0x0 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x0 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x4 "region0addr_baseext,base extended definition for Region 0"
hexmask.long.byte 0x4 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0x8 "region0addr_limit,Limit definition for Region 0"
hexmask.long.word 0x8 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0x8 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0xC "region0addr_limitext,limit extended definition for Region 0"
hexmask.long.byte 0xC 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0x10 "region1addr_base,Base definition for Region 1"
hexmask.long.word 0x10 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x10 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x14 "region1addr_baseext,base extended definition for Region 1"
hexmask.long.byte 0x14 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0x18 "region1addr_limit,Limit definition for Region 1"
hexmask.long.word 0x18 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0x18 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0x1C "region1addr_limitext,limit extended definition for Region 1"
hexmask.long.byte 0x1C 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0x20 "region2addr_base,Base definition for Region 2"
hexmask.long.word 0x20 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x20 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x24 "region2addr_baseext,base extended definition for Region 2"
hexmask.long.byte 0x24 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0x28 "region2addr_limit,Limit definition for Region 2"
hexmask.long.word 0x28 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0x28 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0x2C "region2addr_limitext,limit extended definition for Region 2"
hexmask.long.byte 0x2C 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0x30 "region3addr_base,Base definition for Region 3"
hexmask.long.word 0x30 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x30 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x34 "region3addr_baseext,base extended definition for Region 3"
hexmask.long.byte 0x34 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0x38 "region3addr_limit,Limit definition for Region 3"
hexmask.long.word 0x38 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0x38 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0x3C "region3addr_limitext,limit extended definition for Region 3"
hexmask.long.byte 0x3C 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
tree.end
tree "HMC_ADP"
base ad:0xF8011000
rgroup.long 0x0++0x3
line.long 0x0 "IP_REV_ID,IDO Register"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev #These bits indicate the silicon revision number"
group.long 0x8++0x3
line.long 0x0 "DDRIOCTRL,DDR IO Control Register"
bitfld.long 0x0 2. "MPFE_HMCA_DATA_RATE,Configuration of MPFE-HMCA operating clock/data-rate relative to DDR Clock/Data rate. Clock is driven from IO96/IOHMC PLL into MPFE." "0: MPFE-HMCA Half-rate mode [256b AvST data packet..,1: MPFE-HMCA Quarter-rate mode [512b AvST data.."
newline
bitfld.long 0x0 0.--1. "IO_SIZE,External Configuration of DDR IO size." "0: DDR IO x16,1: DDR IO x32,2: DDR IO x64,?"
rgroup.long 0xC++0x4B
line.long 0x0 "DDRCALSTAT,DDR Calibration Status Register"
bitfld.long 0x0 1. "FAIL,DDR calibration failure status." "0: Calibration is in progress or did not fail,1: Calibration failed"
newline
bitfld.long 0x0 0. "CAL,DDR calibration status." "0: When set to 0,1: When set to 1"
line.long 0x4 "MPR_0BEAT1,MPR register [31:0] for first beat"
hexmask.long 0x4 0.--31. 1. "MPR0,MPR reg[31:0] for first beat"
line.long 0x8 "MPR_1BEAT1,MPR register [63:32] for first beat"
hexmask.long 0x8 0.--31. 1. "MPR32,MPR reg[63:32] for first beat"
line.long 0xC "MPR_2BEAT1,MPR register [95:64] for first beat"
hexmask.long 0xC 0.--31. 1. "MPR64,MPR reg[95:64] for first beat"
line.long 0x10 "MPR_3BEAT1,MPR register [127:96] for first beat"
hexmask.long 0x10 0.--31. 1. "MPR96,MPR reg[127:96] for first beat"
line.long 0x14 "MPR_4BEAT1,MPR register [159:128] for first beat"
hexmask.long 0x14 0.--31. 1. "MPR128,MPR reg[159:128] for first beat"
line.long 0x18 "MPR_5BEAT1,MPR register [191:160] for first beat"
hexmask.long 0x18 0.--31. 1. "MPR160,MPR reg[191:160] for first beat"
line.long 0x1C "MPR_6BEAT1,MPR register [223:192] for first beat"
hexmask.long 0x1C 0.--31. 1. "MPR192,MPR reg[223:192] for first beat"
line.long 0x20 "MPR_7BEAT1,MPR register [255:224] for first beat"
hexmask.long 0x20 0.--31. 1. "MPR224,MPR reg[255:224] for first beat"
line.long 0x24 "MPR_8BEAT1,MPR register [287:256] for first beat"
hexmask.long 0x24 0.--31. 1. "MPR256,MPR reg[287:256] for first beat"
line.long 0x28 "MPR_0BEAT2,MPR register [31:0] for second beat"
hexmask.long 0x28 0.--31. 1. "MPR0,MPR reg[31:0] for second beat"
line.long 0x2C "MPR_1BEAT2,MPR register [63:32] for second beat"
hexmask.long 0x2C 0.--31. 1. "MPR32,MPR reg[63:32] for second beat"
line.long 0x30 "MPR_2BEAT2,MPR register [95:64] for second beat"
hexmask.long 0x30 0.--31. 1. "MPR64,MPR reg[95:64] for second beat"
line.long 0x34 "MPR_3BEAT2,MPR register [127:96] for second beat"
hexmask.long 0x34 0.--31. 1. "MPR96,MPR reg[127:96] for second beat"
line.long 0x38 "MPR_4BEAT2,MPR register [159:128] for second beat"
hexmask.long 0x38 0.--31. 1. "MPR128,MPR reg[159:128] for second beat"
line.long 0x3C "MPR_5BEAT2,MPR register [191:160] for second beat"
hexmask.long 0x3C 0.--31. 1. "MPR160,MPR reg[191:160] for second beat"
line.long 0x40 "MPR_6BEAT2,MPR register [223:192] for second beat"
hexmask.long 0x40 0.--31. 1. "MPR192,MPR reg[223:192] for second beat"
line.long 0x44 "MPR_7BEAT2,MPR register [255:224] for second beat"
hexmask.long 0x44 0.--31. 1. "MPR224,MPR reg[255:224] for second beat"
line.long 0x48 "MPR_8BEAT2,MPR register [287:256] for second beat"
hexmask.long 0x48 0.--31. 1. "MPR256,MPR reg[287:256] for second beat"
group.long 0x60++0x3
line.long 0x0 "AUTO_PRECHARGE,auto-precharge bit"
bitfld.long 0x0 0. "CTRL,Drive bit 43 of core2ctl_cmd_data0 bus to HMC." "0: Default value after reset,1: Every read/write command sent to HMC has the.."
group.long 0xE0++0x3
line.long 0x0 "MPFE_HMCA_SPARE1,spare configuration register"
bitfld.long 0x0 16.--18. "CFG_0,spare" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 14.--15. "CFG_1,spare" "0,1,2,3"
newline
hexmask.long.byte 0x0 10.--13. 1. "CFG_2,"
newline
hexmask.long.byte 0x0 5.--9. 1. "CFG_3,spare"
newline
hexmask.long.byte 0x0 0.--4. 1. "CFG_4,spare"
group.long 0x100++0x7
line.long 0x0 "ECCCTRL1,ECC control 1."
bitfld.long 0x0 16. "AUTOWB_CNT_RST,Reset the autoWB internal counter to zero." "0: No effect on autoWB internal counter,1: Reset the autoWB internal counter to zero"
newline
bitfld.long 0x0 8. "CNT_RST,Reset of internal counter." "0: No effect on internal counter,1: Reset the internal counter to zero"
newline
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0: ECC block is disabled,1: ECC block is enabled"
line.long 0x4 "ECCCTRL2,ECC control 2."
bitfld.long 0x4 16. "OVRW_RB_ECC_EN,Overwrite the read-back ecc code during RMW process if DBE is detected." "0: write the read-back ECC from RMW process if derr..,1: write of 1 will overwrite the ECC overwrite.."
newline
bitfld.long 0x4 8. "RMW_EN,Enable read modify write logic." "0: disable RMW logic,1: enable RMW logic"
newline
bitfld.long 0x4 0. "AUTOWB_EN,Enable auto write back correction feature." "0: disable auto WB drop correction,1: enable auto WB drop correction"
group.long 0x110++0x1B
line.long 0x0 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x0 3. "SEQ2CORE_INTREN,Enables seq2core interrupt." "0: seq2core interrupt generation logic is disabled,1: seq2core interrupt generation logic is enabled"
newline
bitfld.long 0x0 2. "HMI_INTREN,Enables GP HMI interrupt." "0: hmi interrupt generation logic is disabled,1: hmi interrupt generation logic is enabled"
newline
bitfld.long 0x0 1. "DERRINTEN,This bit is used to enable the double bit error interrupt to system" "0: DBE interrupt generation logic is disabled,1: DBE interrupt generation logic is enabled"
newline
bitfld.long 0x0 0. "SERRINTEN,This bit is used to enable the single bit error to system manager. It enables the interrupt modes (sbe request compare match)" "0: SBE interrupt generation logic is disabled,1: SBE interrupt generation logic is enabled"
line.long 0x4 "ERRINTENS,Error Interrupt set"
bitfld.long 0x4 3. "SEQ2CORE_INTRS,This bit is used to set the seq2core interrupt." "0: writing of zero has no effect,1: writing one"
newline
bitfld.long 0x4 2. "HMI_INTRS,This bit is used to set the general purposes HMI interrupt error." "0: writing of zero has no effect,1: writing one"
newline
bitfld.long 0x4 1. "DERRINTS,This bit is used to set the double-bit error interrupt bit." "0: writing of zero has no effect,1: writing one"
newline
bitfld.long 0x4 0. "SERRINTS,This bit is used to set the single-bit error interrupt bit." "0: writing of zero has no effect,1: writing one"
line.long 0x8 "ERRINTENR,Error Interrupt reset."
eventfld.long 0x8 3. "SEQ2CORE_INTRR,This bit is used to reset the seq2core interrupt bit." "0: Writing of zero has no effect,1: By writing one"
newline
eventfld.long 0x8 2. "HMI_INTRR,This bit is used to reset the general purpose HMI interrupt error interrupt to system manager" "0: Writing of zero has no effect,1: By writing one"
newline
eventfld.long 0x8 1. "DERRINTR,This bit is used to reset the double-bit error interrupt bit." "0: Writing of zero has no effect,1: By writing one"
newline
eventfld.long 0x8 0. "SERRINTR,This bit is used to reset the single-bit error interrupt bit." "0: Writing of zero has no effect,1: By writing one"
line.long 0xC "INTMODE,Interrupt mode"
bitfld.long 0xC 24. "AFICAL_EN,Enable interrupt of AFI Cal success." "0: HMI interrupts on compare match is disabled,1: HMI interrupts on compare matched is enabled"
newline
bitfld.long 0xC 16. "INTONCMP,Enable interrupt on compare match." "0: SERR interrupt on compare match is disabled,1: SERR interrupt on compare match is enabled"
newline
bitfld.long 0xC 8. "EXT_ADDRPARITY_EN,Enable address parity for DDR4 memories." "0: disable address parity on DERR interrupt,1: enable address parity on DERR interrupt"
newline
bitfld.long 0xC 0. "INTMODE,Interrupt mode for single-bit error.This is disabled when SERRINTEN is disabled." "0: interrupt disbaled,1: generate interrupt on every SERR"
line.long 0x10 "INTSTAT,Interrupt status"
eventfld.long 0x10 18. "DERRBUSFLG,This bit is used to flag the last transaction was flagged with double-bit error." "0: no effect,1: indicates double-bit error has occured"
newline
eventfld.long 0x10 17. "ADDRPARFLG,External address parity flag for DDR4 memory." "0: No Effect,1: Read of one indicates double-bit interrupt has.."
newline
eventfld.long 0x10 16. "ADDRMTCFLG,Address mismatch error flag." "0: No effect,1: indicates address mismatch error has occured"
newline
eventfld.long 0x10 3. "SEQ2CORE_PENA,SEQ2CORE pending" "0: No effect,1: indicates seq2core interrupt is pending"
newline
eventfld.long 0x10 2. "HMI_PENA,HMI interrupt pending" "0: No effect,1: indicates hmi interrupt is pending"
newline
eventfld.long 0x10 1. "DERRPENA,Double bit error pending" "0: No effect,1: indicates DBE is pending"
newline
eventfld.long 0x10 0. "SERRPENA,Single-bit error pending" "0: No effect,1: indicates SBE is pending"
line.long 0x14 "DIAGINTTEST,Enable diagnostic errors"
bitfld.long 0x14 24. "TADDRPAR,Diagnostic of address parity of DDR4." "0: Disables generating address match bus error as..,1: When this bit is set to 1"
newline
bitfld.long 0x14 16. "TADDRMTC,Diagnostic enable of Address mismatch error." "0: Disables generating address match bus error as..,1: When this bit is set to 1"
newline
bitfld.long 0x14 8. "TDERRA,Diagnostic enable of Double-bit error." "0: Write of zero has no effect,1: When this bit is set to 1"
newline
bitfld.long 0x14 0. "TSERRA,This bit is used to test a single-bit error." "0: Write of zero has no effect,1: When this bit is set to 1"
line.long 0x18 "MODSTAT,Counter feature status flag"
eventfld.long 0x18 8. "AUTOWB_DROP_FLG,Auto writeback counter match flag." "0: read indicates match check of hmi_intr interrupt..,1: read indicates compare has matched"
newline
eventfld.long 0x18 0. "CMPFLGA,Counter Match occurred flag." "0: read indicates match check of SERR interrupt on..,1: read indicates compare has matched"
rgroup.long 0x12C++0x7
line.long 0x0 "DERRADDRA,Double-bit error address"
hexmask.long 0x0 0.--31. 1. "DADDRESS,Recent DBE address."
line.long 0x4 "SERRADDRA,Single-bit error address"
hexmask.long 0x4 0.--31. 1. "SADDRESS,Recent single-bit error address."
rgroup.long 0x138++0x3
line.long 0x0 "AUTOWB_CORRADDR,This register shows the address of the current autoWB correction SBE."
hexmask.long 0x0 0.--31. 1. "SWBADDRESS,recent autoWB correction address."
group.long 0x13C++0xB
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Compare value for the internal single-bit errors."
line.long 0x4 "AUTOWB_DROP_CNTREG,Maximum counter value for AUTOWB correction interrupt"
hexmask.long 0x4 0.--31. 1. "CNT,Compare value for the internal autoWB correction count."
line.long 0x8 "ECC_REG2AWRECCDATABUS,ECC [Lower] from register associated to data which will be written to the RAM"
hexmask.long.byte 0x8 24.--31. 1. "ECC3BUS,ECC from register associated to data [255:192] which will be written to the RAM"
newline
hexmask.long.byte 0x8 16.--23. 1. "ECC2BUS,ECC from register associated to data [191:128] which will be written to the RAM"
newline
hexmask.long.byte 0x8 8.--15. 1. "ECC1BUS,ECC from register associated to data [127:64] which will be written to the RAM"
newline
hexmask.long.byte 0x8 0.--7. 1. "ECC0BUS,ECC from register associated to data [63:0] which will be written to the RAM"
rgroup.long 0x148++0x3
line.long 0x0 "MPFE_HMCA_SPARE2,spare status register"
hexmask.long.byte 0x0 24.--31. 1. "STAT_3,"
newline
hexmask.long.byte 0x0 16.--23. 1. "STAT_2,"
newline
hexmask.long.byte 0x0 8.--15. 1. "STAT_1,"
newline
hexmask.long.byte 0x0 0.--7. 1. "STAT_0,"
group.long 0x14C++0xB
line.long 0x0 "ECC_REG2ARDECCDATABUS,ECC [Lower] from register associated to RD data which will be written to hmc ecc"
hexmask.long.byte 0x0 24.--31. 1. "ECC3BUS,ECC from register associated to RD data [255:192] which will be written to hmc ecc."
newline
hexmask.long.byte 0x0 16.--23. 1. "ECC2BUS,ECC from register associated to RD data [191:128] which will be written to hmc ecc."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC1BUS,ECC from register associated to RD data [127:64] which will be written to hmc ecc."
newline
hexmask.long.byte 0x0 0.--7. 1. "ECC0BUS,ECC from register associated to RD data [63:0] which will be written to hmc ecc."
line.long 0x4 "ECC_DIAGON,Enable diagnostics access"
bitfld.long 0x4 16. "ECCDIAGON,ECC diagnostics mode." "0: ECC diagnostics logic is disabled,1: ECC diagnostics logic is enabled"
newline
bitfld.long 0x4 1. "RDDIAGON,Read diagnostics mux enabled." "0: Read diagnostics path via the ecc_rdata2regbus..,1: Read diagnostics path via the ecc_rdata2regbus.."
newline
bitfld.long 0x4 0. "WRDIAGON,Write diagnostics mux enabled." "0: Write diagnostics path via the ecc_reg2wdatabus..,1: Write diagnostics path via the ecc_reg2wdatabus.."
line.long 0x8 "ECC_DECSTAT,Diagnostic decoder status"
eventfld.long 0x8 27. "DEC7DERRFLG,indicates decoder for data [511:448] has detected DBE." "0: No error has been captured with this flag,1: Decoder 0 detected a double-bit error"
newline
eventfld.long 0x8 26. "DEC6DERRFLG,indicates decoder for data [447:384] has detected DBE." "0: No error has been captured with this flag,1: Decoder 0 detected a double-bit error"
newline
eventfld.long 0x8 25. "DEC5DERRFLG,indicates decoder for data [383:320] has detected DBE." "0: No error has been captured with this flag,1: Decoder 0 detected a double-bit error"
newline
eventfld.long 0x8 24. "DEC4DERRFLG,indicates decoder for data [319:256] has detected DBE." "0: No error has been captured with this flag,1: Decoder 0 detected a double-bit error"
newline
eventfld.long 0x8 23. "DEC7ADDRFLG,indicates decoder for data [511:448] has detected address error." "0: No error has been captured with this flag,1: Decoder 0 detected an address mismatch error"
newline
eventfld.long 0x8 22. "DEC6ADDRFLG,indicates decoder for data [447:384] has detected address error." "0: No error has been captured with this flag,1: Decoder 0 detected an address mismatch error"
newline
eventfld.long 0x8 21. "DEC5ADDRFLG,indicates decoder for data [383:320] has detected address error." "0: No error has been captured with this flag,1: Decoder 0 detected an address mismatch error"
newline
eventfld.long 0x8 20. "DEC4ADDRFLG,indicates decoder for data [319:256] has detected address error." "0: No error has been captured with this flag,1: Decoder 0 detected an address mismatch error"
newline
eventfld.long 0x8 19. "DEC7SERRFLG,indicates decoder for data [511:448] has detected SBE." "0: No error has been captured with this flag,1: Decoder 0 detected a single bit error"
newline
eventfld.long 0x8 18. "DEC6SERRFLG,indicates decoder for data [447:384] has detected SBE." "0: No error has been captured with this flag,1: Decoder 0 detected a single bit error"
newline
eventfld.long 0x8 17. "DEC5SERRFLG,indicates decoder for data [383:320] has detected SBE." "0: No error has been captured with this flag,1: Decoder 0 detected a single bit error"
newline
eventfld.long 0x8 16. "DEC4SERRFLG,indicates decoder for data [319:256] has detected SBE." "0: No error has been captured with this flag,1: Decoder 0 detected a single bit error"
newline
eventfld.long 0x8 11. "DEC3DERRFLG,indicates decoder for data [255:192] has detected DBE." "0: No error has been captured with this flag,1: Decoder 0 detected a double-bit error"
newline
eventfld.long 0x8 10. "DEC2DERRFLG,indicates decoder for data [191:128] has detected DBE." "0: No error has been captured with this flag,1: Decoder 0 detected a double-bit error"
newline
eventfld.long 0x8 9. "DEC1DERRFLG,indicates decoder for data [127:64] has detected DBE." "0: No error has been captured with this flag,1: Decoder 0 detected a double-bit error"
newline
eventfld.long 0x8 8. "DEC0DERRFLG,indicates decoder for data [63:0] has detected DBE." "0: No error has been captured with this flag,1: Decoder 0 detected a double-bit error"
newline
eventfld.long 0x8 7. "DEC3ADDRFLG,indicates decoder for data [255:192] has detected address error." "0: No error has been captured with this flag,1: Decoder 0 detected an address mismatch error"
newline
eventfld.long 0x8 6. "DEC2ADDRFLG,indicates decoder for data [191:128] has detected address error." "0: No error has been captured with this flag,1: Decoder 0 detected an address mismatch error"
newline
eventfld.long 0x8 5. "DEC1ADDRFLG,indicates decoder for data [127:64] has detected address error." "0: No error has been captured with this flag,1: Decoder 0 detected an address mismatch error"
newline
eventfld.long 0x8 4. "DEC0ADDRFLG,indicates decoder for data [63:0] has detected address error." "0: No error has been captured with this flag,1: Decoder 0 detected an address mismatch error"
newline
eventfld.long 0x8 3. "DEC3SERRFLG,indicates decoder for data [255:192] has detected SBE." "0: No error has been captured with this flag,1: Decoder 0 detected a single bit error"
newline
eventfld.long 0x8 2. "DEC2SERRFLG,indicates decoder for data [191:128] has detected SBE." "0: No error has been captured with this flag,1: Decoder 0 detected a single bit error"
newline
eventfld.long 0x8 1. "DEC1SERRFLG,indicates decoder for data [127:64] has detected SBE." "0: No error has been captured with this flag,1: Decoder 0 detected a single bit error"
newline
eventfld.long 0x8 0. "DEC0SERRFLG,indicates decoder for data [63:0] has detected SBE." "0: No error has been captured with this flag,1: Decoder 0 detected a single bit error"
rgroup.long 0x160++0xF
line.long 0x0 "ECC_ERRGENADDR_0,Error address register"
hexmask.long 0x0 0.--31. 1. "ADDR,For decoder 0."
line.long 0x4 "ECC_ERRGENADDR_1,Error address register"
hexmask.long 0x4 0.--31. 1. "ADDR,For decoder 1."
line.long 0x8 "ECC_ERRGENADDR_2,Error address register"
hexmask.long 0x8 0.--31. 1. "ADDR,For decoder 2."
line.long 0xC "ECC_ERRGENADDR_3,Error address register"
hexmask.long 0xC 0.--31. 1. "ADDR,For decoder 3."
group.long 0x170++0xF
line.long 0x0 "ECC_REG2ARDDATABUS_BEAT0,ECC Reg2aRddatabus_beat0"
hexmask.long.byte 0x0 24.--31. 1. "ECC3BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x0 16.--23. 1. "ECC2BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC1BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x0 0.--7. 1. "ECC0BUS,Data ECC from the register will be written to the RAM"
line.long 0x4 "ECC_REG2ARDDATABUS_BEAT1,ECC Reg2Rddatabus_beat1"
hexmask.long.byte 0x4 24.--31. 1. "ECC3BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x4 16.--23. 1. "ECC2BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC1BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x4 0.--7. 1. "ECC0BUS,Data ECC from the register will be written to the RAM"
line.long 0x8 "ECC_REG2ARDDATABUS_BEAT2,ECC Reg2Rddatabus_beat2"
hexmask.long.byte 0x8 24.--31. 1. "ECC3BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x8 16.--23. 1. "ECC2BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x8 8.--15. 1. "ECC1BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x8 0.--7. 1. "ECC0BUS,Data ECC from the register will be written to the RAM"
line.long 0xC "ECC_REG2ARDDATABUS_BEAT3,ECC Reg2Rddatabus_beat3"
hexmask.long.byte 0xC 24.--31. 1. "ECC3BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0xC 16.--23. 1. "ECC2BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0xC 8.--15. 1. "ECC1BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0xC 0.--7. 1. "ECC0BUS,Data ECC from the register will be written to the RAM"
rgroup.long 0x180++0xF
line.long 0x0 "ECC_ERRGENHADDR_0,Error address register"
hexmask.long.byte 0x0 0.--4. 1. "ADDR,For decoder 0."
line.long 0x4 "ECC_ERRGENHADDR_1,Error address register"
hexmask.long.byte 0x4 0.--4. 1. "ADDR,For decoder 1."
line.long 0x8 "ECC_ERRGENHADDR_2,Error address register"
hexmask.long.byte 0x8 0.--4. 1. "ADDR,For decoder 2."
line.long 0xC "ECC_ERRGENHADDR_3,Error address register"
hexmask.long.byte 0xC 0.--4. 1. "ADDR,For decoder 3."
rgroup.long 0x1B0++0x7
line.long 0x0 "DERRHADDR,Double-bit error high address"
hexmask.long.byte 0x0 0.--4. 1. "DADDRESS,Recent DBE High address."
line.long 0x4 "SERRHADDR,Single-bit error address"
hexmask.long.byte 0x4 0.--4. 1. "SADDRESS,Recent SBE High address."
rgroup.long 0x1BC++0x3
line.long 0x0 "AUTOWB_CORRHADDR,This register shows the high address of the current autoWB correction SBE."
hexmask.long.byte 0x0 0.--4. 1. "SWBADDRESS,recent autoWB correction high address."
group.long 0x210++0x7
line.long 0x0 "MPFE_HMCA_CTRL,MPFE-HMCA-CTRL config+status register"
hexmask.long.byte 0x0 16.--23. 1. "status,spare status registers"
newline
bitfld.long 0x0 8. "DISABLE_WR_ECC_INFO_RMW_OPT,1'b1: [When set] Disable WR_ECC_INFO modification for RMW performance optimization" "0: [Default] Enable WR_ECC_INFO modification for..,1: [When set] Disable WR_ECC_INFO modification for.."
newline
hexmask.long.byte 0x0 0.--7. 1. "config,spare config registers"
line.long 0x4 "RSTHANDSHAKECTRL,reset handshaking from MPFE or ARM"
hexmask.long.byte 0x4 0.--7. 1. "CORE2SEQ,core2seq register"
rgroup.long 0x218++0x27
line.long 0x0 "RSTHANDSHAKESTAT,Reset handshaking from IO48 or Nios"
hexmask.long.byte 0x0 0.--7. 1. "SEQ2CORE,seq2core register"
line.long 0x4 "MPR_9BEAT1,MPR register [319:288] for first beat"
hexmask.long 0x4 0.--31. 1. "MPR288,MPR reg[319:288] for first beat"
line.long 0x8 "MPR_10BEAT1,MPR register [351:320] for first beat"
hexmask.long 0x8 0.--31. 1. "MPR320,MPR reg[351:320] for first beat"
line.long 0xC "MPR_11BEAT1,MPR register [383:352] for first beat"
hexmask.long 0xC 0.--31. 1. "MPR352,MPR reg[383:352] for first beat"
line.long 0x10 "MPR_12BEAT1,MPR register [415:384] for first beat"
hexmask.long 0x10 0.--31. 1. "MPR384,MPR reg[415:384] for first beat"
line.long 0x14 "MPR_13BEAT1,MPR register [447:416] for first beat"
hexmask.long 0x14 0.--31. 1. "MPR416,MPR reg[447:416] for first beat"
line.long 0x18 "MPR_14BEAT1,MPR register [479:448] for first beat"
hexmask.long 0x18 0.--31. 1. "MPR448,MPR reg[479:448] for first beat"
line.long 0x1C "MPR_15BEAT1,MPR register [511:480] for first beat"
hexmask.long 0x1C 0.--31. 1. "MPR480,MPR reg[511:480] for first beat"
line.long 0x20 "MPR_16BEAT1,MPR register [543:512] for first beat"
hexmask.long 0x20 0.--31. 1. "MPR512,MPR reg[543:512] for first beat"
line.long 0x24 "MPR_17BEAT1,MPR register [575:544] for first beat"
hexmask.long 0x24 0.--31. 1. "MPR544,MPR reg[575:544] for first beat"
group.long 0x264++0x7
line.long 0x0 "ECC_REG2BWRECCDATABUS,ECC [Upper] from register associated to data which will be written to the RAM"
hexmask.long.byte 0x0 24.--31. 1. "ECC7BUS,ECC from register associated to data [255:192] which will be written to the RAM"
newline
hexmask.long.byte 0x0 16.--23. 1. "ECC6BUS,ECC from register associated to data [191:128] which will be written to the RAM"
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC5BUS,ECC from register associated to data [127:64] which will be written to the RAM"
newline
hexmask.long.byte 0x0 0.--7. 1. "ECC4BUS,ECC from register associated to data [63:0] which will be written to the RAM"
line.long 0x4 "ECC_REG2BRDECCDATABUS,ECC [Upper] from register associated to RD data which will be written to hmc ecc"
hexmask.long.byte 0x4 24.--31. 1. "ECC7BUS,ECC from register associated to RD data [255:192] which will be written to hmc ecc."
newline
hexmask.long.byte 0x4 16.--23. 1. "ECC6BUS,ECC from register associated to RD data [191:128] which will be written to hmc ecc."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC5BUS,ECC from register associated to RD data [127:64] which will be written to hmc ecc."
newline
hexmask.long.byte 0x4 0.--7. 1. "ECC4BUS,ECC from register associated to RD data [63:0] which will be written to hmc ecc."
rgroup.long 0x26C++0xF
line.long 0x0 "ECC_ERRGENADDR_4,Error address register"
hexmask.long 0x0 0.--31. 1. "ADDR,For decoder 4."
line.long 0x4 "ECC_ERRGENADDR_5,Error address register"
hexmask.long 0x4 0.--31. 1. "ADDR,For decoder 5."
line.long 0x8 "ECC_ERRGENADDR_6,Error address register"
hexmask.long 0x8 0.--31. 1. "ADDR,For decoder 6."
line.long 0xC "ECC_ERRGENADDR_7,Error address register"
hexmask.long 0xC 0.--31. 1. "ADDR,For decoder 7."
group.long 0x27C++0xF
line.long 0x0 "ECC_REG2BRDDATABUS_BEAT0,ECC Reg2bRddatabus_beat0"
hexmask.long.byte 0x0 24.--31. 1. "ECC7BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x0 16.--23. 1. "ECC6BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC5BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x0 0.--7. 1. "ECC4BUS,Data ECC from the register will be written to the RAM"
line.long 0x4 "ECC_REG2BRDDATABUS_BEAT1,ECC Reg2Rddatabus_beat1"
hexmask.long.byte 0x4 24.--31. 1. "ECC7BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x4 16.--23. 1. "ECC6BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC5BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x4 0.--7. 1. "ECC4BUS,Data ECC from the register will be written to the RAM"
line.long 0x8 "ECC_REG2BRDDATABUS_BEAT2,ECC Reg2Rddatabus_beat2"
hexmask.long.byte 0x8 24.--31. 1. "ECC7BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x8 16.--23. 1. "ECC6BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x8 8.--15. 1. "ECC5BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0x8 0.--7. 1. "ECC4BUS,Data ECC from the register will be written to the RAM"
line.long 0xC "ECC_REG2BRDDATABUS_BEAT3,ECC Reg2Rddatabus_beat3"
hexmask.long.byte 0xC 24.--31. 1. "ECC7BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0xC 16.--23. 1. "ECC6BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0xC 8.--15. 1. "ECC5BUS,Data ECC from the register will be written to the RAM"
newline
hexmask.long.byte 0xC 0.--7. 1. "ECC4BUS,Data ECC from the register will be written to the RAM"
rgroup.long 0x28C++0x57
line.long 0x0 "ECC_ERRGENHADDR_4,Error address register"
hexmask.long.byte 0x0 0.--4. 1. "ADDR,For decoder 4."
line.long 0x4 "ECC_ERRGENHADDR_5,Error address register"
hexmask.long.byte 0x4 0.--4. 1. "ADDR,For decoder 5."
line.long 0x8 "ECC_ERRGENHADDR_6,Error address register"
hexmask.long.byte 0x8 0.--4. 1. "ADDR,For decoder 6."
line.long 0xC "ECC_ERRGENHADDR_7,Error address register"
hexmask.long.byte 0xC 0.--4. 1. "ADDR,For decoder 7."
line.long 0x10 "MPR_9BEAT2,MPR register [319:288] for second beat"
hexmask.long 0x10 0.--31. 1. "MPR288,MPR reg[319:288] for second beat"
line.long 0x14 "MPR_10BEAT2,MPR register [351:320] for second beat"
hexmask.long 0x14 0.--31. 1. "MPR320,MPR reg[351:320] for second beat"
line.long 0x18 "MPR_11BEAT2,MPR register [383:352] for second beat"
hexmask.long 0x18 0.--31. 1. "MPR352,MPR reg[383:352] for second beat"
line.long 0x1C "MPR_12BEAT2,MPR register [415:384] for second beat"
hexmask.long 0x1C 0.--31. 1. "MPR384,MPR reg[415:384] for second beat"
line.long 0x20 "MPR_13BEAT2,MPR register [447:416] for second beat"
hexmask.long 0x20 0.--31. 1. "MPR416,MPR reg[447:416] for second beat"
line.long 0x24 "MPR_14BEAT2,MPR register [479:448] for second beat"
hexmask.long 0x24 0.--31. 1. "MPR448,MPR reg[479:448] for second beat"
line.long 0x28 "MPR_15BEAT2,MPR register [511:480] for second beat"
hexmask.long 0x28 0.--31. 1. "MPR480,MPR reg[511:480] for second beat"
line.long 0x2C "MPR_16BEAT2,MPR register [543:512] for second beat"
hexmask.long 0x2C 0.--31. 1. "MPR512,MPR reg[543:512] for second beat"
line.long 0x30 "MPR_17BEAT2,MPR register [575:544] for second beat"
hexmask.long 0x30 0.--31. 1. "MPR544,MPR reg[575:544] for second beat"
line.long 0x34 "IOHMC_STAT,IOHMC status register"
bitfld.long 0x34 0. "IDLE,IOHMC idle status indication" "0: When set to 0,1: When set to 1"
line.long 0x38 "ECC_RDECCDATA2AREGBUS_BEAT0,ECC of data[Lower] from DRAM will be written to register"
hexmask.long.byte 0x38 24.--31. 1. "ECC3BUS,ECC of data [255:192] from RAM which will be written to register."
newline
hexmask.long.byte 0x38 16.--23. 1. "ECC2BUS,ECC of data [191:128] from RAM which will be written to register."
newline
hexmask.long.byte 0x38 8.--15. 1. "ECC1BUS,ECC of data [127:64] from RAM which will be written to register."
newline
hexmask.long.byte 0x38 0.--7. 1. "ECC0BUS,ECC of data [63:0] from RAM which will be written to register."
line.long 0x3C "ECC_RDECCDATA2AREGBUS_BEAT1,ECC of data[Lower] from DRAM will be written to register"
hexmask.long.byte 0x3C 24.--31. 1. "ECC3BUS,ECC of data [255:192] from RAM which will be written to register."
newline
hexmask.long.byte 0x3C 16.--23. 1. "ECC2BUS,ECC of data [191:128] from RAM which will be written to register."
newline
hexmask.long.byte 0x3C 8.--15. 1. "ECC1BUS,ECC of data [127:64] from RAM which will be written to register."
newline
hexmask.long.byte 0x3C 0.--7. 1. "ECC0BUS,ECC of data [63:0] from RAM which will be written to register."
line.long 0x40 "ECC_RDECCDATA2AREGBUS_BEAT2,ECC of data[Lower] from DRAM will be written to register"
hexmask.long.byte 0x40 24.--31. 1. "ECC3BUS,ECC of data [255:192] from RAM which will be written to register."
newline
hexmask.long.byte 0x40 16.--23. 1. "ECC2BUS,ECC of data [191:128] from RAM which will be written to register."
newline
hexmask.long.byte 0x40 8.--15. 1. "ECC1BUS,ECC of data [127:64] from RAM which will be written to register."
newline
hexmask.long.byte 0x40 0.--7. 1. "ECC0BUS,ECC of data [63:0] from RAM which will be written to register."
line.long 0x44 "ECC_RDECCDATA2AREGBUS_BEAT3,ECC of data[Lower] from DRAM will be written to register"
hexmask.long.byte 0x44 24.--31. 1. "ECC3BUS,ECC of data [255:192] from RAM which will be written to register."
newline
hexmask.long.byte 0x44 16.--23. 1. "ECC2BUS,ECC of data [191:128] from RAM which will be written to register."
newline
hexmask.long.byte 0x44 8.--15. 1. "ECC1BUS,ECC of data [127:64] from RAM which will be written to register."
newline
hexmask.long.byte 0x44 0.--7. 1. "ECC0BUS,ECC of data [63:0] from RAM which will be written to register."
line.long 0x48 "ECC_RDECCDATA2BREGBUS_BEAT0,ECC of data[Upper] from DRAM will be written to register"
hexmask.long.byte 0x48 24.--31. 1. "ECC7BUS,ECC of data [511:448] from RAM which will be written to register."
newline
hexmask.long.byte 0x48 16.--23. 1. "ECC6BUS,ECC of data [447:384] from RAM which will be written to register."
newline
hexmask.long.byte 0x48 8.--15. 1. "ECC5BUS,ECC of data [383:320] from RAM which will be written to register."
newline
hexmask.long.byte 0x48 0.--7. 1. "ECC4BUS,ECC of data [319:256] from RAM which will be written to register."
line.long 0x4C "ECC_RDECCDATA2BREGBUS_BEAT1,ECC of data[Upper] from DRAM will be written to register"
hexmask.long.byte 0x4C 24.--31. 1. "ECC7BUS,ECC of data [511:448] from RAM which will be written to register."
newline
hexmask.long.byte 0x4C 16.--23. 1. "ECC6BUS,ECC of data [447:384] from RAM which will be written to register."
newline
hexmask.long.byte 0x4C 8.--15. 1. "ECC5BUS,ECC of data [383:320] from RAM which will be written to register."
newline
hexmask.long.byte 0x4C 0.--7. 1. "ECC4BUS,ECC of data [319:256] from RAM which will be written to register."
line.long 0x50 "ECC_RDECCDATA2BREGBUS_BEAT2,ECC of data[Upper] from DRAM will be written to register"
hexmask.long.byte 0x50 24.--31. 1. "ECC7BUS,ECC of data [511:448] from RAM which will be written to register."
newline
hexmask.long.byte 0x50 16.--23. 1. "ECC6BUS,ECC of data [447:384] from RAM which will be written to register."
newline
hexmask.long.byte 0x50 8.--15. 1. "ECC5BUS,ECC of data [383:320] from RAM which will be written to register."
newline
hexmask.long.byte 0x50 0.--7. 1. "ECC4BUS,ECC of data [319:256] from RAM which will be written to register."
line.long 0x54 "ECC_RDECCDATA2BREGBUS_BEAT3,ECC of data[Upper] from DRAM will be written to register"
hexmask.long.byte 0x54 24.--31. 1. "ECC7BUS,ECC of data [511:448] from RAM which will be written to register."
newline
hexmask.long.byte 0x54 16.--23. 1. "ECC6BUS,ECC of data [447:384] from RAM which will be written to register."
newline
hexmask.long.byte 0x54 8.--15. 1. "ECC5BUS,ECC of data [383:320] from RAM which will be written to register."
newline
hexmask.long.byte 0x54 0.--7. 1. "ECC4BUS,ECC of data [319:256] from RAM which will be written to register."
tree.end
tree "IOHMC_CTRL"
base ad:0xF8010000
group.long 0x0++0xC3
line.long 0x0 "reg_dbgcfg0,"
hexmask.long.byte 0x0 5.--8. 1. "cfg_dbg_mode,iohmc_ctrl_mmr_top_inst.cfg_dbg_mode[3:0]"
newline
bitfld.long 0x0 4. "cfg_cmd_driver_sel,iohmc_ctrl_mmr_top_inst.cfg_cmd_driver_sel" "0,1"
newline
bitfld.long 0x0 3. "cfg_loopback_en,iohmc_ctrl_mmr_top_inst.cfg_loopback_en" "0,1"
newline
bitfld.long 0x0 2. "cfg_cb_seq_en_fix_en_n,iohmc_ctrl_mmr_top_inst.cfg_cb_seq_en_fix_en_n" "0,1"
newline
bitfld.long 0x0 1. "cfg_prbs_ctrl_sel,iohmc_ctrl_mmr_top_inst.cfg_prbs_ctrl_sel" "0,1"
newline
bitfld.long 0x0 0. "cfg_wdata_driver_sel,iohmc_ctrl_mmr_top_inst.cfg_wdata_driver_sel" "0,1"
line.long 0x4 "reg_dbgcfg1,"
hexmask.long 0x4 0.--31. 1. "cfg_dbg_ctrl,iohmc_ctrl_mmr_top_inst.cfg_dbg_ctrl[31:0]"
line.long 0x8 "reg_dbgcfg2,"
hexmask.long 0x8 0.--31. 1. "cfg_bist_cmd0_u,iohmc_ctrl_mmr_top_inst.cfg_bist_cmd0_u[31:0]"
line.long 0xC "reg_dbgcfg3,"
hexmask.long 0xC 0.--31. 1. "cfg_bist_cmd0_l,iohmc_ctrl_mmr_top_inst.cfg_bist_cmd0_l[31:0]"
line.long 0x10 "reg_dbgcfg4,"
hexmask.long 0x10 0.--31. 1. "cfg_bist_cmd1_u,iohmc_ctrl_mmr_top_inst.cfg_bist_cmd1_u[31:0]"
line.long 0x14 "reg_dbgcfg5,"
hexmask.long 0x14 0.--31. 1. "cfg_bist_cmd1_l,iohmc_ctrl_mmr_top_inst.cfg_bist_cmd1_l[31:0]"
line.long 0x18 "reg_dbgcfg6,"
hexmask.long.word 0x18 0.--15. 1. "cfg_dbg_out_sel,iohmc_ctrl_mmr_top_inst.cfg_dbg_out_sel[15:0]"
line.long 0x1C "reg_reserve0,"
hexmask.long.word 0x1C 0.--15. 1. "cfg_reserve0,iohmc_ctrl_mmr_top_inst.cfg_reserve0[15:0]"
line.long 0x20 "reg_reserve1,"
hexmask.long.word 0x20 0.--15. 1. "cfg_reserve1,iohmc_ctrl_mmr_top_inst.cfg_reserve1[15:0]"
line.long 0x24 "reg_reserve2,"
hexmask.long.word 0x24 0.--15. 1. "cfg_reserve2,iohmc_ctrl_mmr_top_inst.cfg_reserve2[15:0]"
line.long 0x28 "reg_ctrlcfg0,"
hexmask.long.byte 0x28 24.--28. 1. "cfg_dbc2_burst_length,iohmc_ctrl_mmr_top_inst.cfg_dbc2_burst_length[4:0]"
newline
hexmask.long.byte 0x28 19.--23. 1. "cfg_dbc1_burst_length,iohmc_ctrl_mmr_top_inst.cfg_dbc1_burst_length[4:0]"
newline
hexmask.long.byte 0x28 14.--18. 1. "cfg_dbc0_burst_length,iohmc_ctrl_mmr_top_inst.cfg_dbc0_burst_length[4:0]"
newline
hexmask.long.byte 0x28 9.--13. 1. "cfg_ctrl_burst_length,iohmc_ctrl_mmr_top_inst.cfg_ctrl_burst_length[4:0]"
newline
bitfld.long 0x28 7.--8. "cfg_ac_pos,iohmc_ctrl_mmr_top_inst.cfg_ac_pos[1:0]" "0,1,2,3"
newline
bitfld.long 0x28 4.--6. "cfg_dimm_type,iohmc_ctrl_mmr_top_inst.cfg_dimm_type[2:0]" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x28 0.--3. 1. "cfg_mem_type,iohmc_ctrl_mmr_top_inst.cfg_mem_type[3:0]"
line.long 0x2C "reg_ctrlcfg1,"
bitfld.long 0x2C 30. "cfg_dbc3_enable_dm,iohmc_ctrl_mmr_top_inst.cfg_dbc3_enable_dm" "0,1"
newline
bitfld.long 0x2C 29. "cfg_dbc2_enable_dm,iohmc_ctrl_mmr_top_inst.cfg_dbc2_enable_dm" "0,1"
newline
bitfld.long 0x2C 28. "cfg_dbc1_enable_dm,iohmc_ctrl_mmr_top_inst.cfg_dbc1_enable_dm" "0,1"
newline
bitfld.long 0x2C 27. "cfg_dbc0_enable_dm,iohmc_ctrl_mmr_top_inst.cfg_dbc0_enable_dm" "0,1"
newline
bitfld.long 0x2C 26. "cfg_ctrl_enable_dm,iohmc_ctrl_mmr_top_inst.cfg_ctrl_enable_dm" "0,1"
newline
bitfld.long 0x2C 25. "cfg_dqstrk_en,iohmc_ctrl_mmr_top_inst.cfg_dqstrk_en" "0,1"
newline
hexmask.long.byte 0x2C 19.--24. 1. "cfg_starve_limit,iohmc_ctrl_mmr_top_inst.cfg_starve_limit[5:0]"
newline
bitfld.long 0x2C 18. "cfg_reorder_read,iohmc_ctrl_mmr_top_inst.cfg_reorder_read" "0,1"
newline
bitfld.long 0x2C 17. "cfg_dbc3_reorder_rdata,iohmc_ctrl_mmr_top_inst.cfg_dbc3_reorder_rdata" "0,1"
newline
bitfld.long 0x2C 16. "cfg_dbc2_reorder_rdata,iohmc_ctrl_mmr_top_inst.cfg_dbc2_reorder_rdata" "0,1"
newline
bitfld.long 0x2C 15. "cfg_dbc1_reorder_rdata,iohmc_ctrl_mmr_top_inst.cfg_dbc1_reorder_rdata" "0,1"
newline
bitfld.long 0x2C 14. "cfg_dbc0_reorder_rdata,iohmc_ctrl_mmr_top_inst.cfg_dbc0_reorder_rdata" "0,1"
newline
bitfld.long 0x2C 13. "cfg_ctrl_reorder_rdata,iohmc_ctrl_mmr_top_inst.cfg_ctrl_reorder_rdata" "0,1"
newline
bitfld.long 0x2C 12. "cfg_reorder_data,iohmc_ctrl_mmr_top_inst.cfg_reorder_data" "0,1"
newline
bitfld.long 0x2C 11. "cfg_dbc3_enable_ecc,iohmc_ctrl_mmr_top_inst.cfg_dbc3_enable_ecc" "0,1"
newline
bitfld.long 0x2C 10. "cfg_dbc2_enable_ecc,iohmc_ctrl_mmr_top_inst.cfg_dbc2_enable_ecc" "0,1"
newline
bitfld.long 0x2C 9. "cfg_dbc1_enable_ecc,iohmc_ctrl_mmr_top_inst.cfg_dbc1_enable_ecc" "0,1"
newline
bitfld.long 0x2C 8. "cfg_dbc0_enable_ecc,iohmc_ctrl_mmr_top_inst.cfg_dbc0_enable_ecc" "0,1"
newline
bitfld.long 0x2C 7. "cfg_ctrl_enable_ecc,iohmc_ctrl_mmr_top_inst.cfg_ctrl_enable_ecc" "0,1"
newline
bitfld.long 0x2C 5.--6. "cfg_addr_order,iohmc_ctrl_mmr_top_inst.cfg_addr_order[1:0]" "0,1,2,3"
newline
hexmask.long.byte 0x2C 0.--4. 1. "cfg_dbc3_burst_length,iohmc_ctrl_mmr_top_inst.cfg_dbc3_burst_length[4:0]"
line.long 0x30 "reg_ctrlcfg2,"
bitfld.long 0x30 24.--26. "cfg_dbc3_pipe_lat,iohmc_ctrl_mmr_top_inst.cfg_dbc3_pipe_lat[2:0]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 21.--23. "cfg_dbc2_pipe_lat,iohmc_ctrl_mmr_top_inst.cfg_dbc2_pipe_lat[2:0]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 18.--20. "cfg_dbc1_pipe_lat,iohmc_ctrl_mmr_top_inst.cfg_dbc1_pipe_lat[2:0]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 15.--17. "cfg_dbc0_pipe_lat,iohmc_ctrl_mmr_top_inst.cfg_dbc0_pipe_lat[2:0]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 13.--14. "cfg_dbc2ctrl_sel,iohmc_ctrl_mmr_top_inst.cfg_dbc2ctrl_sel[1:0]" "0: DBC0,1: DBC1,2: DBC2,3: DBC3"
newline
bitfld.long 0x30 12. "cfg_dbc3_ctrl_sel,iohmc_ctrl_mmr_top_inst.cfg_dbc3_ctrl_sel" "0: The upper MUX in io_hmc_dbc_switch is selected,1: The lower mux is selected"
newline
bitfld.long 0x30 11. "cfg_dbc2_ctrl_sel,iohmc_ctrl_mmr_top_inst.cfg_dbc2_ctrl_sel" "0: The upper MUX in io_hmc_dbc_switch is selected,1: The lower mux is selected"
newline
bitfld.long 0x30 10. "cfg_dbc1_ctrl_sel,iohmc_ctrl_mmr_top_inst.cfg_dbc1_ctrl_sel" "0: The upper MUX in io_hmc_dbc_switch is selected,1: The lower mux is selected"
newline
bitfld.long 0x30 9. "cfg_dbc0_ctrl_sel,iohmc_ctrl_mmr_top_inst.cfg_dbc0_ctrl_sel" "0: The upper MUX in io_hmc_dbc_switch is selected,1: The lower mux is selected"
newline
bitfld.long 0x30 7.--8. "cfg_ctrl2dbc_switch1,iohmc_ctrl_mmr_top_inst.cfg_ctrl2dbc_switch1[1:0]" "0,1,2,3"
newline
bitfld.long 0x30 5.--6. "cfg_ctrl2dbc_switch0,iohmc_ctrl_mmr_top_inst.cfg_ctrl2dbc_switch0[1:0]" "0,1,2,3"
newline
bitfld.long 0x30 4. "cfg_dbc3_output_regd,iohmc_ctrl_mmr_top_inst.cfg_dbc3_output_regd" "0,1"
newline
bitfld.long 0x30 3. "cfg_dbc2_output_regd,iohmc_ctrl_mmr_top_inst.cfg_dbc2_output_regd" "0,1"
newline
bitfld.long 0x30 2. "cfg_dbc1_output_regd,iohmc_ctrl_mmr_top_inst.cfg_dbc1_output_regd" "0,1"
newline
bitfld.long 0x30 1. "cfg_dbc0_output_regd,iohmc_ctrl_mmr_top_inst.cfg_dbc0_output_regd" "0,1"
newline
bitfld.long 0x30 0. "cfg_ctrl_output_regd,iohmc_ctrl_mmr_top_inst.cfg_ctrl_output_regd" "0,1"
line.long 0x34 "reg_ctrlcfg3,"
bitfld.long 0x34 30. "cfg_cb_memclk_gate_default,iohmc_ctrl_mmr_top_inst.cfg_cb_memclk_gate_default" "0,1"
newline
bitfld.long 0x34 28. "cfg_3dsref_ack_on_done,iohmc_ctrl_mmr_top_inst.cfg_3dsref_ack_on_done" "0,1"
newline
bitfld.long 0x34 27. "cfg_geardn_en,iohmc_ctrl_mmr_top_inst.cfg_geardn_en" "0,1"
newline
bitfld.long 0x34 26. "cfg_open_page_en,iohmc_ctrl_mmr_top_inst.cfg_open_page_en" "0,1"
newline
bitfld.long 0x34 25. "cfg_arbiter_type,iohmc_ctrl_mmr_top_inst.cfg_arbiter_type" "0,1"
newline
bitfld.long 0x34 24. "cfg_dbc3_dualport_en,iohmc_ctrl_mmr_top_inst.cfg_dbc3_dualport_en" "0,1"
newline
bitfld.long 0x34 23. "cfg_dbc2_dualport_en,iohmc_ctrl_mmr_top_inst.cfg_dbc2_dualport_en" "0,1"
newline
bitfld.long 0x34 22. "cfg_dbc1_dualport_en,iohmc_ctrl_mmr_top_inst.cfg_dbc1_dualport_en" "0,1"
newline
bitfld.long 0x34 21. "cfg_dbc0_dualport_en,iohmc_ctrl_mmr_top_inst.cfg_dbc0_dualport_en" "0,1"
newline
bitfld.long 0x34 20. "cfg_ctrl_dualport_en,iohmc_ctrl_mmr_top_inst.cfg_ctrl_dualport_en" "0,1"
newline
bitfld.long 0x34 19. "cfg_dbc3_in_protocol,iohmc_ctrl_mmr_top_inst.cfg_dbc3_in_protocol" "0,1"
newline
bitfld.long 0x34 18. "cfg_dbc2_in_protocol,iohmc_ctrl_mmr_top_inst.cfg_dbc2_in_protocol" "0,1"
newline
bitfld.long 0x34 17. "cfg_dbc1_in_protocol,iohmc_ctrl_mmr_top_inst.cfg_dbc1_in_protocol" "0,1"
newline
bitfld.long 0x34 16. "cfg_dbc0_in_protocol,iohmc_ctrl_mmr_top_inst.cfg_dbc0_in_protocol" "0,1"
newline
bitfld.long 0x34 15. "cfg_ctrl_in_protocol,iohmc_ctrl_mmr_top_inst.cfg_ctrl_in_protocol" "0,1"
newline
bitfld.long 0x34 12.--14. "cfg_dbc3_cmd_rate,iohmc_ctrl_mmr_top_inst.cfg_dbc3_cmd_rate[2:0]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 9.--11. "cfg_dbc2_cmd_rate,iohmc_ctrl_mmr_top_inst.cfg_dbc2_cmd_rate[2:0]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 6.--8. "cfg_dbc1_cmd_rate,iohmc_ctrl_mmr_top_inst.cfg_dbc1_cmd_rate[2:0]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 3.--5. "cfg_dbc0_cmd_rate,iohmc_ctrl_mmr_top_inst.cfg_dbc0_cmd_rate[2:0]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 0.--2. "cfg_ctrl_cmd_rate,iohmc_ctrl_mmr_top_inst.cfg_ctrl_cmd_rate[2:0]" "0,1,2,3,4,5,6,7"
line.long 0x38 "reg_ctrlcfg4,"
bitfld.long 0x38 30.--31. "cfg_dbc3_slot_offset,iohmc_ctrl_mmr_top_inst.cfg_dbc3_slot_offset[1:0]" "0,1,2,3"
newline
bitfld.long 0x38 28.--29. "cfg_dbc2_slot_offset,iohmc_ctrl_mmr_top_inst.cfg_dbc2_slot_offset[1:0]" "0,1,2,3"
newline
bitfld.long 0x38 26.--27. "cfg_dbc1_slot_offset,iohmc_ctrl_mmr_top_inst.cfg_dbc1_slot_offset[1:0]" "0,1,2,3"
newline
bitfld.long 0x38 24.--25. "cfg_dbc0_slot_offset,iohmc_ctrl_mmr_top_inst.cfg_dbc0_slot_offset[1:0]" "0,1,2,3"
newline
bitfld.long 0x38 22.--23. "cfg_ctrl_slot_offset,iohmc_ctrl_mmr_top_inst.cfg_ctrl_slot_offset[1:0]" "0,1,2,3"
newline
bitfld.long 0x38 19.--21. "cfg_dbc3_slot_rotate_en,iohmc_ctrl_mmr_top_inst.cfg_dbc3_slot_rotate_en[2:0]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 16.--18. "cfg_dbc2_slot_rotate_en,iohmc_ctrl_mmr_top_inst.cfg_dbc2_slot_rotate_en[2:0]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 13.--15. "cfg_dbc1_slot_rotate_en,iohmc_ctrl_mmr_top_inst.cfg_dbc1_slot_rotate_en[2:0]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 10.--12. "cfg_dbc0_slot_rotate_en,iohmc_ctrl_mmr_top_inst.cfg_dbc0_slot_rotate_en[2:0]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 7.--9. "cfg_ctrl_slot_rotate_en,iohmc_ctrl_mmr_top_inst.cfg_ctrl_slot_rotate_en[2:0]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 5.--6. "cfg_pingpong_mode,iohmc_ctrl_mmr_top_inst.cfg_pingpong_mode[1:0]" "0,1,2,3"
newline
hexmask.long.byte 0x38 0.--4. 1. "cfg_tile_id,iohmc_ctrl_mmr_top_inst.cfg_tile_id[4:0]"
line.long 0x3C "reg_ctrlcfg5,"
bitfld.long 0x3C 12. "cfg_dbc3_rc_en,iohmc_ctrl_mmr_top_inst.cfg_dbc3_rc_en" "0,1"
newline
bitfld.long 0x3C 11. "cfg_dbc2_rc_en,iohmc_ctrl_mmr_top_inst.cfg_dbc2_rc_en" "0,1"
newline
bitfld.long 0x3C 10. "cfg_dbc1_rc_en,iohmc_ctrl_mmr_top_inst.cfg_dbc1_rc_en" "0,1"
newline
bitfld.long 0x3C 9. "cfg_dbc0_rc_en,iohmc_ctrl_mmr_top_inst.cfg_dbc0_rc_en" "0,1"
newline
bitfld.long 0x3C 8. "cfg_ctrl_rc_en,iohmc_ctrl_mmr_top_inst.cfg_ctrl_rc_en" "0,1"
newline
hexmask.long.byte 0x3C 4.--7. 1. "cfg_row_cmd_slot,iohmc_ctrl_mmr_top_inst.cfg_row_cmd_slot[3:0]"
newline
hexmask.long.byte 0x3C 0.--3. 1. "cfg_col_cmd_slot,iohmc_ctrl_mmr_top_inst.cfg_col_cmd_slot[3:0]"
line.long 0x40 "reg_ctrlcfg6,"
hexmask.long.word 0x40 0.--15. 1. "cfg_cs_chip,iohmc_ctrl_mmr_top_inst.cfg_cs_chip[15:0]"
line.long 0x44 "reg_ctrlcfg7,"
hexmask.long.byte 0x44 8.--14. 1. "cfg_wb_backup_entry,iohmc_ctrl_mmr_top_inst.cfg_wb_reserved_entry[6:0]"
newline
hexmask.long.byte 0x44 1.--7. 1. "cfg_rb_backup_entry,iohmc_ctrl_mmr_top_inst.cfg_rb_reserved_entry[6:0]"
line.long 0x48 "reg_ctrlcfg8,"
bitfld.long 0x48 1. "cfg_ck_inv,iohmc_ctrl_mmr_top_inst.cfg_ck_inv" "0: 10101010,1: 01010101"
newline
bitfld.long 0x48 0. "cfg_3ds_en,iohmc_ctrl_mmr_top_inst.cfg_3ds_en" "0: Disable 3DS Logic,1: Enable 3DS Logic"
line.long 0x4C "reg_ctrlcfg9,"
bitfld.long 0x4C 0. "cfg_dfx_bypass_en,iohmc_ctrl_mmr_top_inst.cfg_dfx_bypass_en" "0: Normal functional mode,1: DFX bypass mode"
line.long 0x50 "reg_dramtiming0,"
hexmask.long.byte 0x50 13.--18. 1. "cfg_mem_clk_disable_entry_cycles,iohmc_ctrl_mmr_top_inst.cfg_mem_clk_disable_entry_cycles[5:0]"
newline
hexmask.long.byte 0x50 7.--12. 1. "cfg_power_saving_exit_cycles,iohmc_ctrl_mmr_top_inst.cfg_power_saving_exit_cycles[5:0]"
newline
hexmask.long.byte 0x50 0.--6. 1. "cfg_tcl,iohmc_ctrl_mmr_top_inst.cfg_tcl[6:0]"
line.long 0x54 "reg_dramodt0,"
hexmask.long.word 0x54 16.--31. 1. "cfg_read_odt_chip,iohmc_ctrl_mmr_top_inst.cfg_read_odt_chip[15:0]"
newline
hexmask.long.word 0x54 0.--15. 1. "cfg_write_odt_chip,iohmc_ctrl_mmr_top_inst.cfg_write_odt_chip[15:0]"
line.long 0x58 "reg_dramodt1,"
hexmask.long.byte 0x58 18.--23. 1. "cfg_rd_odt_period,iohmc_ctrl_mmr_top_inst.cfg_rd_odt_period[5:0]"
newline
hexmask.long.byte 0x58 12.--17. 1. "cfg_wr_odt_period,iohmc_ctrl_mmr_top_inst.cfg_wr_odt_period[5:0]"
newline
hexmask.long.byte 0x58 6.--11. 1. "cfg_rd_odt_on,iohmc_ctrl_mmr_top_inst.cfg_rd_odt_on[5:0]"
newline
hexmask.long.byte 0x58 0.--5. 1. "cfg_wr_odt_on,iohmc_ctrl_mmr_top_inst.cfg_wr_odt_on[5:0]"
line.long 0x5C "reg_sbcfg0,"
hexmask.long.word 0x5C 16.--31. 1. "cfg_rld3_refresh_seq1,iohmc_ctrl_mmr_top_inst.cfg_rld3_refresh_seq1[15:0]"
newline
hexmask.long.byte 0x5C 12.--15. 1. "cfg_rld3_refresh_seq0,iohmc_ctrl_mmr_top_inst.cfg_rld3_refresh_seq0[3:0]"
newline
bitfld.long 0x5C 11. "cfg_self_rfsh_dqstrk_en,iohmc_ctrl_mmr_top_inst.cfg_self_rfsh_dqstrk_en" "0,1"
newline
bitfld.long 0x5C 10. "cfg_cb_pdqs_perf_fix_disable,iohmc_ctrl_mmr_top_inst.cfg_cb_pdqs_perf_fix_disable" "0,1"
newline
bitfld.long 0x5C 9. "cfg_cb_3ds_mixed_height_req_fix,iohmc_ctrl_mmr_top_inst.cfg_cb_3ds_mixed_height_req_fix" "0,1"
newline
bitfld.long 0x5C 8. "cfg_cb_en_mrnk_rd_fix,iohmc_ctrl_mmr_top_inst.cfg_cb_en_mrnk_rd_fix" "0,1"
newline
bitfld.long 0x5C 7. "cfg_cb_3ds_mixed_height_ref_ack_disable,iohmc_ctrl_mmr_top_inst.cfg_cb_3ds_mixed_height_ref_ack_disable" "0,1"
newline
bitfld.long 0x5C 6. "cfg_cb_en_cmd_valid_ungate_fix,iohmc_ctrl_mmr_top_inst.cfg_cb_en_cmd_valid_ungate_fix" "0,1"
newline
bitfld.long 0x5C 5. "cfg_cb_revert_ref_qual,iohmc_ctrl_mmr_top_inst.cfg_cb_revert_ref_qual" "0,1"
newline
bitfld.long 0x5C 4. "cfg_exit_pdn_for_dqstrk,iohmc_ctrl_mmr_top_inst.cfg_exit_pdn_for_dqstrk" "0,1"
newline
hexmask.long.byte 0x5C 0.--3. 1. "cfg_no_of_ref_for_self_rfsh,iohmc_ctrl_mmr_top_inst.cfg_no_of_ref_for_self_rfsh[3:0]"
line.long 0x60 "reg_sbcfg1,"
hexmask.long.word 0x60 16.--31. 1. "cfg_rld3_refresh_seq3,iohmc_ctrl_mmr_top_inst.cfg_rld3_refresh_seq3[15:0]"
newline
hexmask.long.word 0x60 0.--15. 1. "cfg_rld3_refresh_seq2,iohmc_ctrl_mmr_top_inst.cfg_rld3_refresh_seq2[15:0]"
line.long 0x64 "reg_sbcfg2,"
bitfld.long 0x64 6.--7. "cfg_srf_entry_exit_block,iohmc_ctrl_mmr_top_inst.cfg_srf_entry_exit_block[1:0]" "0,1,2,3"
newline
bitfld.long 0x64 5. "cfg_srf_autoexit_en,iohmc_ctrl_mmr_top_inst.cfg_srf_autoexit_en" "0,1"
newline
bitfld.long 0x64 4. "cfg_user_rfsh_en,iohmc_ctrl_mmr_top_inst.cfg_user_rfsh_en" "0,1"
newline
bitfld.long 0x64 3. "cfg_sb_cg_disable,iohmc_ctrl_mmr_top_inst.cfg_sb_cg_disable" "0,1"
newline
bitfld.long 0x64 2. "cfg_mps_dqstrk_disable,iohmc_ctrl_mmr_top_inst.cfg_mps_dqstrk_disable" "0,1"
newline
bitfld.long 0x64 1. "cfg_mps_zqcal_disable,iohmc_ctrl_mmr_top_inst.cfg_mps_zqcal_disable" "0,1"
newline
bitfld.long 0x64 0. "cfg_srf_zqcal_disable,iohmc_ctrl_mmr_top_inst.cfg_srf_zqcal_disable" "0,1"
line.long 0x68 "reg_sbcfg3,"
hexmask.long.tbyte 0x68 0.--19. 1. "cfg_sb_ddr4_mr3,iohmc_ctrl_mmr_top_inst.cfg_sb_ddr4_mr3[19:0]"
line.long 0x6C "reg_sbcfg4,"
hexmask.long.tbyte 0x6C 0.--19. 1. "cfg_sb_ddr4_mr4,iohmc_ctrl_mmr_top_inst.cfg_sb_ddr4_mr4[19:0]"
line.long 0x70 "reg_sbcfg5,"
bitfld.long 0x70 1. "cfg_period_dqstrk_ctrl_en,iohmc_ctrl_mmr_top_inst.cfg_period_dqstrk_ctrl_en" "0,1"
newline
bitfld.long 0x70 0. "cfg_short_dqstrk_ctrl_en,iohmc_ctrl_mmr_top_inst.cfg_short_dqstrk_ctrl_en" "0,1"
line.long 0x74 "reg_sbcfg6,"
hexmask.long.byte 0x74 24.--31. 1. "cfg_t_param_dqstrk_to_valid,iohmc_ctrl_mmr_top_inst.cfg_t_param_dqstrk_to_valid[7:0]"
newline
hexmask.long.byte 0x74 16.--23. 1. "cfg_t_param_dqstrk_to_valid_last,iohmc_ctrl_mmr_top_inst.cfg_t_param_dqstrk_to_valid_last[7:0]"
newline
hexmask.long.word 0x74 0.--15. 1. "cfg_period_dqstrk_interval,iohmc_ctrl_mmr_top_inst.cfg_period_dqstrk_interval[15:0]"
line.long 0x78 "reg_sbcfg7,"
hexmask.long.byte 0x78 0.--6. 1. "cfg_rfsh_warn_threshold,iohmc_ctrl_mmr_top_inst.cfg_rfsh_warn_threshold[6:0]"
line.long 0x7C "reg_caltiming0,"
hexmask.long.byte 0x7C 24.--29. 1. "cfg_t_param_act_to_act_diff_bg,iohmc_ctrl_mmr_top_inst.cfg_t_param_act_to_act_diff_bg[5:0]"
newline
hexmask.long.byte 0x7C 18.--23. 1. "cfg_t_param_act_to_act_diff_bank,iohmc_ctrl_mmr_top_inst.cfg_t_param_act_to_act_diff_bank[5:0]"
newline
hexmask.long.byte 0x7C 12.--17. 1. "cfg_t_param_act_to_act,iohmc_ctrl_mmr_top_inst.cfg_t_param_act_to_act[5:0]"
newline
hexmask.long.byte 0x7C 6.--11. 1. "cfg_t_param_act_to_pch,iohmc_ctrl_mmr_top_inst.cfg_t_param_act_to_pch[5:0]"
newline
hexmask.long.byte 0x7C 0.--5. 1. "cfg_t_param_act_to_rdwr,iohmc_ctrl_mmr_top_inst.cfg_t_param_act_to_rdwr[5:0]"
line.long 0x80 "reg_caltiming1,"
hexmask.long.byte 0x80 24.--29. 1. "cfg_t_param_rd_to_wr_diff_chip,iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_wr_diff_chip[5:0]"
newline
hexmask.long.byte 0x80 18.--23. 1. "cfg_t_param_rd_to_wr,iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_wr[5:0]"
newline
hexmask.long.byte 0x80 12.--17. 1. "cfg_t_param_rd_to_rd_diff_bg,iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_rd_diff_bg[5:0]"
newline
hexmask.long.byte 0x80 6.--11. 1. "cfg_t_param_rd_to_rd_diff_chip,iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_rd_diff_chip[5:0]"
newline
hexmask.long.byte 0x80 0.--5. 1. "cfg_t_param_rd_to_rd,iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_rd[5:0]"
line.long 0x84 "reg_caltiming2,"
hexmask.long.byte 0x84 24.--29. 1. "cfg_t_param_wr_to_wr_diff_chip,iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_wr_diff_chip[5:0]"
newline
hexmask.long.byte 0x84 18.--23. 1. "cfg_t_param_wr_to_wr,iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_wr[5:0]"
newline
hexmask.long.byte 0x84 12.--17. 1. "cfg_t_param_rd_ap_to_valid,iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_ap_to_valid[5:0]"
newline
hexmask.long.byte 0x84 6.--11. 1. "cfg_t_param_rd_to_pch,iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_pch[5:0]"
newline
hexmask.long.byte 0x84 0.--5. 1. "cfg_t_param_rd_to_wr_diff_bg,iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_wr_diff_bg[5:0]"
line.long 0x88 "reg_caltiming3,"
hexmask.long.byte 0x88 24.--29. 1. "cfg_t_param_wr_to_pch,iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_pch[5:0]"
newline
hexmask.long.byte 0x88 18.--23. 1. "cfg_t_param_wr_to_rd_diff_bg,iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_rd_diff_bg[5:0]"
newline
hexmask.long.byte 0x88 12.--17. 1. "cfg_t_param_wr_to_rd_diff_chip,iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_rd_diff_chip[5:0]"
newline
hexmask.long.byte 0x88 6.--11. 1. "cfg_t_param_wr_to_rd,iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_rd[5:0]"
newline
hexmask.long.byte 0x88 0.--5. 1. "cfg_t_param_wr_to_wr_diff_bg,iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_wr_diff_bg[5:0]"
line.long 0x8C "reg_caltiming4,"
hexmask.long.byte 0x8C 26.--31. 1. "cfg_t_param_pdn_to_valid,iohmc_ctrl_mmr_top_inst.cfg_t_param_pdn_to_valid[5:0]"
newline
hexmask.long.byte 0x8C 18.--25. 1. "cfg_t_param_arf_to_valid,iohmc_ctrl_mmr_top_inst.cfg_t_param_arf_to_valid[7:0]"
newline
hexmask.long.byte 0x8C 12.--17. 1. "cfg_t_param_pch_all_to_valid,iohmc_ctrl_mmr_top_inst.cfg_t_param_pch_all_to_valid[5:0]"
newline
hexmask.long.byte 0x8C 6.--11. 1. "cfg_t_param_pch_to_valid,iohmc_ctrl_mmr_top_inst.cfg_t_param_pch_to_valid[5:0]"
newline
hexmask.long.byte 0x8C 0.--5. 1. "cfg_t_param_wr_ap_to_valid,iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_ap_to_valid[5:0]"
line.long 0x90 "reg_caltiming5,"
hexmask.long.word 0x90 10.--19. 1. "cfg_t_param_srf_to_zq_cal,iohmc_ctrl_mmr_top_inst.cfg_t_param_srf_to_zq_cal[9:0]"
newline
hexmask.long.word 0x90 0.--9. 1. "cfg_t_param_srf_to_valid,iohmc_ctrl_mmr_top_inst.cfg_t_param_srf_to_valid[9:0]"
line.long 0x94 "reg_caltiming6,"
hexmask.long.word 0x94 13.--28. 1. "cfg_t_param_pdn_period,iohmc_ctrl_mmr_top_inst.cfg_t_param_pdn_period[15:0]"
newline
hexmask.long.word 0x94 0.--12. 1. "cfg_t_param_arf_period,iohmc_ctrl_mmr_top_inst.cfg_t_param_arf_period[12:0]"
line.long 0x98 "reg_caltiming7,"
hexmask.long.word 0x98 20.--29. 1. "cfg_t_param_mps_to_valid,iohmc_ctrl_mmr_top_inst.cfg_t_param_mps_to_valid[9:0]"
newline
hexmask.long.byte 0x98 16.--19. 1. "cfg_t_param_mrs_to_valid,iohmc_ctrl_mmr_top_inst.cfg_t_param_mrs_to_valid[3:0]"
newline
hexmask.long.byte 0x98 9.--15. 1. "cfg_t_param_zqcs_to_valid,iohmc_ctrl_mmr_top_inst.cfg_t_param_zqcs_to_valid[6:0]"
newline
hexmask.long.word 0x98 0.--8. 1. "cfg_t_param_zqcl_to_valid,iohmc_ctrl_mmr_top_inst.cfg_t_param_zqcl_to_valid[8:0]"
line.long 0x9C "reg_caltiming8,"
hexmask.long.byte 0x9C 20.--27. 1. "cfg_t_param_mmr_cmd_to_valid,iohmc_ctrl_mmr_top_inst.cfg_t_param_mmr_cmd_to_valid[7:0]"
newline
bitfld.long 0x9C 17.--19. "cfg_t_param_rld3_multibank_ref_delay,iohmc_ctrl_mmr_top_inst.cfg_t_param_rld3_multibank_ref_delay[2:0]" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x9C 13.--16. 1. "cfg_t_param_mps_exit_cke_to_cs,iohmc_ctrl_mmr_top_inst.cfg_t_param_mps_exit_cke_to_cs[3:0]"
newline
hexmask.long.byte 0x9C 9.--12. 1. "cfg_t_param_mps_exit_cs_to_cke,iohmc_ctrl_mmr_top_inst.cfg_t_param_mps_exit_cs_to_cke[3:0]"
newline
hexmask.long.byte 0x9C 4.--8. 1. "cfg_t_param_mpr_to_valid,iohmc_ctrl_mmr_top_inst.cfg_t_param_mpr_to_valid[4:0]"
newline
hexmask.long.byte 0x9C 0.--3. 1. "cfg_t_param_mrr_to_valid,iohmc_ctrl_mmr_top_inst.cfg_t_param_mrr_to_valid[3:0]"
line.long 0xA0 "reg_caltiming9,"
hexmask.long.byte 0xA0 0.--7. 1. "cfg_t_param_4_act_to_act,iohmc_ctrl_mmr_top_inst.cfg_t_param_4_act_to_act[7:0]"
line.long 0xA4 "reg_caltiming10,"
hexmask.long.byte 0xA4 0.--7. 1. "cfg_t_param_16_act_to_act,iohmc_ctrl_mmr_top_inst.cfg_t_param_16_act_to_act[7:0]"
line.long 0xA8 "reg_dramaddrw,"
bitfld.long 0xA8 16.--18. "cfg_cs_addr_width,iohmc_ctrl_mmr_top_inst.cfg_cs_addr_width[2:0]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xA8 14.--15. "cfg_bank_group_addr_width,iohmc_ctrl_mmr_top_inst.cfg_bank_group_addr_width[1:0]" "0,1,2,3"
newline
hexmask.long.byte 0xA8 10.--13. 1. "cfg_bank_addr_width,iohmc_ctrl_mmr_top_inst.cfg_bank_addr_width[3:0]"
newline
hexmask.long.byte 0xA8 5.--9. 1. "cfg_row_addr_width,iohmc_ctrl_mmr_top_inst.cfg_row_addr_width[4:0]"
newline
hexmask.long.byte 0xA8 0.--4. 1. "cfg_col_addr_width,iohmc_ctrl_mmr_top_inst.cfg_col_addr_width[4:0]"
line.long 0xAC "reg_sideband0,"
bitfld.long 0xAC 0. "mr_cmd_trigger,iohmc_ctrl_mmr_top_inst.mr_cmd_trigger" "0,1"
line.long 0xB0 "reg_sideband1,"
hexmask.long.byte 0xB0 0.--3. 1. "mmr_refresh_req,iohmc_ctrl_mmr_top_inst.mmr_refresh_req[3:0]"
line.long 0xB4 "reg_sideband2,"
bitfld.long 0xB4 0. "mmr_zqcal_long_req,iohmc_ctrl_mmr_top_inst.mmr_zqcal_long_req" "0,1"
line.long 0xB8 "reg_sideband3,"
bitfld.long 0xB8 0. "mmr_zqcal_short_req,iohmc_ctrl_mmr_top_inst.mmr_zqcal_short_req" "0,1"
line.long 0xBC "reg_sideband4,"
hexmask.long.byte 0xBC 0.--3. 1. "mmr_self_rfsh_req,iohmc_ctrl_mmr_top_inst.mmr_self_rfsh_req[3:0]"
line.long 0xC0 "reg_sideband5,"
bitfld.long 0xC0 0. "mmr_dpd_mps_req,iohmc_ctrl_mmr_top_inst.mmr_dpd_mps_req" "0,1"
rgroup.long 0xC4++0x17
line.long 0x0 "reg_sideband6,"
bitfld.long 0x0 0. "mr_cmd_ack,iohmc_ctrl_mmr_top_inst.mr_cmd_ack" "0,1"
line.long 0x4 "reg_sideband7,"
bitfld.long 0x4 0. "mmr_refresh_ack,iohmc_ctrl_mmr_top_inst.mmr_refresh_ack" "0,1"
line.long 0x8 "reg_sideband8,"
bitfld.long 0x8 0. "mmr_zqcal_ack,iohmc_ctrl_mmr_top_inst.mmr_zqcal_ack" "0,1"
line.long 0xC "reg_sideband9,"
bitfld.long 0xC 0. "mmr_self_rfsh_ack,iohmc_ctrl_mmr_top_inst.mmr_self_rfsh_ack" "0,1"
line.long 0x10 "reg_sideband10,"
bitfld.long 0x10 0. "mmr_dpd_mps_ack,iohmc_ctrl_mmr_top_inst.mmr_dpd_mps_ack" "0,1"
line.long 0x14 "reg_sideband11,"
bitfld.long 0x14 0. "mmr_auto_pd_ack,iohmc_ctrl_mmr_top_inst.mmr_auto_pd_ack" "0,1"
group.long 0xDC++0xF
line.long 0x0 "reg_sideband12,"
hexmask.long.byte 0x0 3.--6. 1. "mr_cmd_rank,iohmc_ctrl_mmr_top_inst.mr_cmd_rank[3:0]"
newline
bitfld.long 0x0 0.--2. "mr_cmd_type,iohmc_ctrl_mmr_top_inst.mr_cmd_type[2:0]" "0,1,2,3,4,5,6,7"
line.long 0x4 "reg_sideband13,"
hexmask.long 0x4 0.--31. 1. "mr_cmd_opcode,iohmc_ctrl_mmr_top_inst.mr_cmd_opcode[31:0]"
line.long 0x8 "reg_sideband14,"
hexmask.long.word 0x8 0.--15. 1. "mmr_refresh_bank,iohmc_ctrl_mmr_top_inst.mmr_refresh_bank[15:0]"
line.long 0xC "reg_sideband15,"
hexmask.long.byte 0xC 0.--3. 1. "mmr_stall_rank,iohmc_ctrl_mmr_top_inst.mmr_stall_rank[3:0]"
rgroup.long 0xEC++0xB
line.long 0x0 "reg_dramsts,"
bitfld.long 0x0 1. "phy_cal_fail,iohmc_ctrl_mmr_top_inst.phy_cal_fail" "0,1"
newline
bitfld.long 0x0 0. "phy_cal_success,iohmc_ctrl_mmr_top_inst.phy_cal_success" "0,1"
line.long 0x4 "reg_dbgdone,"
bitfld.long 0x4 0. "dbg_done,iohmc_ctrl_mmr_top_inst.dbg_done" "0,1"
line.long 0x8 "reg_dbgsignals,"
hexmask.long 0x8 0.--31. 1. "dbg_signals_out,iohmc_ctrl_mmr_top_inst.dbg_signals_out[31:0]"
group.long 0xF8++0x3
line.long 0x0 "reg_dbgreset,"
bitfld.long 0x0 1. "counter_one_reset,iohmc_ctrl_mmr_top_inst.counter_one_reset" "0,1"
newline
bitfld.long 0x0 0. "counter_zero_reset,iohmc_ctrl_mmr_top_inst.counter_zero_reset" "0,1"
rgroup.long 0xFC++0x3
line.long 0x0 "reg_dbgmatch,"
hexmask.long 0x0 0.--31. 1. "counter_one,iohmc_ctrl_mmr_top_inst.counter_one[31:0]"
group.long 0x100++0x33
line.long 0x0 "reg_counter0mask,"
hexmask.long 0x0 0.--31. 1. "counter_zero_mask,iohmc_ctrl_mmr_top_inst.counter_zero_mask[31:0]"
line.long 0x4 "reg_counter1mask,"
hexmask.long 0x4 0.--31. 1. "counter_one_mask,iohmc_ctrl_mmr_top_inst.counter_one_mask[31:0]"
line.long 0x8 "reg_counter0match,"
hexmask.long 0x8 0.--31. 1. "counter_zero_match,iohmc_ctrl_mmr_top_inst.counter_zero_match[31:0]"
line.long 0xC "reg_counter1match,"
hexmask.long 0xC 0.--31. 1. "counter_one_match,iohmc_ctrl_mmr_top_inst.counter_one_match[31:0]"
line.long 0x10 "reg_niosreserve0,"
hexmask.long.word 0x10 0.--15. 1. "nios_reserve0,iohmc_ctrl_mmr_top_inst.nios_reserve0[15:0]"
line.long 0x14 "reg_niosreserve1,"
hexmask.long.word 0x14 0.--15. 1. "nios_reserve1,iohmc_ctrl_mmr_top_inst.nios_reserve1[15:0]"
line.long 0x18 "reg_niosreserve2,"
hexmask.long.word 0x18 0.--15. 1. "nios_reserve2,iohmc_ctrl_mmr_top_inst.nios_reserve2[15:0]"
line.long 0x1C "reg_sbcfg8,"
hexmask.long.tbyte 0x1C 0.--19. 1. "cfg_sb_ddr4_mr5,iohmc_ctrl_mmr_top_inst.cfg_sb_ddr4_mr5[19:0]"
line.long 0x20 "reg_sbcfg9,"
bitfld.long 0x20 0. "cfg_ddr4_mps_addrmirror,iohmc_ctrl_mmr_top_inst.cfg_ddr4_mps_addrmirror" "0,1"
line.long 0x24 "reg_3ds0,"
bitfld.long 0x24 18. "cfg_3ds_pr_stag_enable,iohmc_ctrl_mmr_top_inst.cfg_3ds_pr_stag_enable" "0,1"
newline
bitfld.long 0x24 16.--17. "cfg_cid_addr_width,iohmc_ctrl_mmr_top_inst.cfg_cid_addr_width[1:0]" "0,1,2,3"
newline
hexmask.long.byte 0x24 12.--15. 1. "cfg_3ds_lr_num3,iohmc_ctrl_mmr_top_inst.cfg_3ds_lr_num3[3:0]"
newline
hexmask.long.byte 0x24 8.--11. 1. "cfg_3ds_lr_num2,iohmc_ctrl_mmr_top_inst.cfg_3ds_lr_num2[3:0]"
newline
hexmask.long.byte 0x24 4.--7. 1. "cfg_3ds_lr_num1,iohmc_ctrl_mmr_top_inst.cfg_3ds_lr_num1[3:0]"
newline
hexmask.long.byte 0x24 0.--3. 1. "cfg_3ds_lr_num0,iohmc_ctrl_mmr_top_inst.cfg_3ds_lr_num0[3:0]"
line.long 0x28 "reg_3ds1,"
hexmask.long.byte 0x28 0.--6. 1. "cfg_3ds_ref2ref_dlr,iohmc_ctrl_mmr_top_inst.cfg_3ds_ref2ref_dlr[6:0]"
line.long 0x2C "reg_3ds2,"
hexmask.long.word 0x2C 0.--8. 1. "cfg_chip_id,iohmc_ctrl_mmr_top_inst.cfg_chip_id[8:0]"
line.long 0x30 "reg_pipeline0,"
bitfld.long 0x30 7. "cfg_cmd_fifo_pipeline_en,iohmc_ctrl_mmr_top_inst.cfg_cmd_fifo_reserve_en" "0,1"
newline
bitfld.long 0x30 6. "cfg_ac_tile_reg_ena,iohmc_ctrl_mmr_top_inst.cfg_ac_tile_reg_ena" "0,1"
newline
bitfld.long 0x30 5. "cfg_ctl2dbc_tile_reg_ena,iohmc_ctrl_mmr_top_inst.cfg_ctl2dbc_tile_reg_ena" "0,1"
newline
bitfld.long 0x30 3. "cfg_ctl2dbc_reg_ena,iohmc_ctrl_mmr_top_inst.cfg_ctl2dbc_reg_ena" "0,1"
newline
bitfld.long 0x30 2. "cfg_rb_ptr_reg_ena,iohmc_ctrl_mmr_top_inst.cfg_rb_ptr_reg_ena" "0,1"
newline
bitfld.long 0x30 1. "cfg_wb_ptr_reg_ena,iohmc_ctrl_mmr_top_inst.cfg_wb_ptr_reg_ena" "0,1"
newline
bitfld.long 0x30 0. "cfg_arbiter_reg_ena,iohmc_ctrl_mmr_top_inst.cfg_arbiter_reg_ena" "0,1"
group.long 0x138++0x3
line.long 0x0 "reg_memclockgating0,"
hexmask.long.byte 0x0 0.--7. 1. "cfg_memclkgate_setting,iohmc_ctrl_mmr_top_inst.cfg_memclkgate_setting"
rgroup.long 0x13C++0x3
line.long 0x0 "reg_sideband16,"
hexmask.long 0x0 0.--31. 1. "mmr_3ds_refresh_ack,iohmc_ctrl_mmr_top_inst.mmr_3ds_refresh_ack[31:0]"
tree.end
tree "MPFE"
base ad:0xF8020000
rgroup.long 0x1000++0x7
line.long 0x0 "cs_obs_at_main_AtbEndPoint_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "cs_obs_at_main_AtbEndPoint_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x1008++0xB
line.long 0x0 "cs_obs_at_main_AtbEndPoint_AtbId,"
hexmask.long.byte 0x0 0.--6. 1. "ATBID,ATB AtId"
line.long 0x4 "cs_obs_at_main_AtbEndPoint_AtbEn,"
bitfld.long 0x4 0. "ATBEN,ATB Unit Enable" "0,1"
line.long 0x8 "cs_obs_at_main_AtbEndPoint_SyncPeriod,"
hexmask.long.byte 0x8 0.--4. 1. "SYNCPERIOD,ATB Synchro Period"
rgroup.long 0x1080++0x7
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "cs_obs_at_main_ErrorLogger_0_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x1088++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_FaultEn,"
bitfld.long 0x0 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1"
rgroup.long 0x108C++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_ErrVld,"
bitfld.long 0x0 0. "ERRVLD,1 indicates an error has been logged" "0,1"
group.long 0x1090++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_ErrClr,"
eventfld.long 0x0 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1"
rgroup.long 0x1094++0x7
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_ErrLog0,Stores NTTP packet header fields Lock. Opc. ErrCode. Len1 and indicates version of NTTP transport protocol"
bitfld.long 0x0 31. "FORMAT,NTTP transport protocol version" "0,1"
newline
hexmask.long.word 0x0 16.--27. 1. "LEN1,Len1"
newline
bitfld.long 0x0 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 1.--4. 1. "OPC,Opc"
newline
bitfld.long 0x0 0. "LOCK,Lock" "0,1"
line.long 0x4 "cs_obs_at_main_ErrorLogger_0_ErrLog1,"
hexmask.long.word 0x4 0.--14. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error"
rgroup.long 0x10A0++0x13
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_ErrLog3,"
hexmask.long 0x0 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error"
line.long 0x4 "cs_obs_at_main_ErrorLogger_0_ErrLog4,"
hexmask.long.word 0x4 0.--8. 1. "ERRLOG4,Stores NTTP packet header field Addr (MSBs) of the logged error"
line.long 0x8 "cs_obs_at_main_ErrorLogger_0_ErrLog5,"
hexmask.long 0x8 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error"
line.long 0xC "cs_obs_at_main_ErrorLogger_0_ErrLog6,"
hexmask.long.byte 0xC 0.--7. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error"
line.long 0x10 "cs_obs_at_main_ErrorLogger_0_ErrLog7,"
bitfld.long 0x10 0.--1. "ERRLOG7,Stores NTTP packet header field Security of the logged error" "0,1,2,3"
group.long 0x10B8++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_StallEn,"
bitfld.long 0x0 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1"
rgroup.long 0x1100++0x7
line.long 0x0 "cs_obs_at_main_ErrorLogger_1_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "cs_obs_at_main_ErrorLogger_1_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x1108++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_1_FaultEn,"
bitfld.long 0x0 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1"
rgroup.long 0x110C++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_1_ErrVld,"
bitfld.long 0x0 0. "ERRVLD,1 indicates an error has been logged" "0,1"
group.long 0x1110++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_1_ErrClr,"
eventfld.long 0x0 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1"
rgroup.long 0x1114++0x7
line.long 0x0 "cs_obs_at_main_ErrorLogger_1_ErrLog0,Stores NTTP packet header fields Lock. Opc. ErrCode. Len1 and indicates version of NTTP transport protocol"
bitfld.long 0x0 31. "FORMAT,NTTP transport protocol version" "0,1"
newline
hexmask.long.word 0x0 16.--27. 1. "LEN1,Len1"
newline
bitfld.long 0x0 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 1.--4. 1. "OPC,Opc"
newline
bitfld.long 0x0 0. "LOCK,Lock" "0,1"
line.long 0x4 "cs_obs_at_main_ErrorLogger_1_ErrLog1,"
hexmask.long.word 0x4 0.--14. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error"
rgroup.long 0x1120++0x13
line.long 0x0 "cs_obs_at_main_ErrorLogger_1_ErrLog3,"
hexmask.long 0x0 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error"
line.long 0x4 "cs_obs_at_main_ErrorLogger_1_ErrLog4,"
hexmask.long.word 0x4 0.--8. 1. "ERRLOG4,Stores NTTP packet header field Addr (MSBs) of the logged error"
line.long 0x8 "cs_obs_at_main_ErrorLogger_1_ErrLog5,"
hexmask.long 0x8 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error"
line.long 0xC "cs_obs_at_main_ErrorLogger_1_ErrLog6,"
hexmask.long.byte 0xC 0.--7. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error"
line.long 0x10 "cs_obs_at_main_ErrorLogger_1_ErrLog7,"
bitfld.long 0x10 0.--1. "ERRLOG7,Stores NTTP packet header field Security of the logged error" "0,1,2,3"
group.long 0x1138++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_1_StallEn,"
bitfld.long 0x0 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1"
rgroup.long 0x1800++0x7
line.long 0x0 "fc2sdram_probe_main_Probe_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "fc2sdram_probe_main_Probe_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x1808++0x7
line.long 0x0 "fc2sdram_probe_main_Probe_MainCtl,Register MainCtl contains probe global control bits. The register has seven bit fields:"
bitfld.long 0x0 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0  filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore  only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1  filters are.." "0,1"
newline
rbitfld.long 0x0 6. "INTRUSIVEMODE,When set to 1  register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0  the register enables trace operation in Overflow flow-control mode" "0,1"
newline
bitfld.long 0x0 5. "STATCONDDUMP,When set  register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin  StatAlarmMax  and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1"
newline
bitfld.long 0x0 4. "ALARMEN,When set  register field AlarmEn enables the probe to collect alarm-related information. When the register field bit is null  both TraceAlarm and StatAlarm outputs are driven to 0." "0,1"
newline
bitfld.long 0x0 3. "STATEN,When set to 1  register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0  counters are disabled." "0,1"
newline
bitfld.long 0x0 2. "PAYLOADEN,Register field PayloadEn  when set to 1  enables traces to contain headers and payload. When set ot 0  only headers are reported." "0,1"
newline
bitfld.long 0x0 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1"
newline
bitfld.long 0x0 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status  independently of filtering mechanisms  thus constituting a simple supplementary global filter." "0,1"
line.long 0x4 "fc2sdram_probe_main_Probe_CfgCtl,"
rbitfld.long 0x4 1. "ACTIVE," "0,1"
newline
bitfld.long 0x4 0. "GLOBALEN," "0,1"
group.long 0x1814++0x7
line.long 0x0 "fc2sdram_probe_main_Probe_FilterLut,"
hexmask.long.word 0x0 0.--15. 1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.."
line.long 0x4 "fc2sdram_probe_main_Probe_TraceAlarmEn,"
hexmask.long.byte 0x4 0.--4. 1. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.."
rgroup.long 0x181C++0x3
line.long 0x0 "fc2sdram_probe_main_Probe_TraceAlarmStatus,"
hexmask.long.byte 0x0 0.--4. 1. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet  independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.."
group.long 0x1820++0x13
line.long 0x0 "fc2sdram_probe_main_Probe_TraceAlarmClr,"
hexmask.long.byte 0x0 0.--4. 1. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0  TraceAlarmClr is reserved.NOTE The.."
line.long 0x4 "fc2sdram_probe_main_Probe_StatPeriod,"
hexmask.long.byte 0x4 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period  within a range of 2 cycles to 2 gigacycles  during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.."
line.long 0x8 "fc2sdram_probe_main_Probe_StatGo,"
eventfld.long 0x8 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode  that is  when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1"
line.long 0xC "fc2sdram_probe_main_Probe_StatAlarmMin,"
hexmask.long 0xC 0.--31. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .."
line.long 0x10 "fc2sdram_probe_main_Probe_StatAlarmMax,"
hexmask.long 0x10 0.--31. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .."
rgroup.long 0x1834++0x3
line.long 0x0 "fc2sdram_probe_main_Probe_StatAlarmStatus,"
bitfld.long 0x0 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1"
group.long 0x1838++0x7
line.long 0x0 "fc2sdram_probe_main_Probe_StatAlarmClr,"
eventfld.long 0x0 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False  StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1"
line.long 0x4 "fc2sdram_probe_main_Probe_StatAlarmEn,"
bitfld.long 0x4 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1"
group.long 0x1844++0xEF
line.long 0x0 "fc2sdram_probe_main_Probe_Filters_0_RouteIdBase,"
hexmask.long.word 0x0 0.--14. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x4 "fc2sdram_probe_main_Probe_Filters_0_RouteIdMask,"
hexmask.long.word 0x4 0.--14. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &RouteIdMask = RouteIdBase &RouteIdMask."
line.long 0x8 "fc2sdram_probe_main_Probe_Filters_0_AddrBase_Low,"
hexmask.long 0x8 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register."
line.long 0xC "fc2sdram_probe_main_Probe_Filters_0_AddrBase_High,"
hexmask.long.word 0xC 0.--8. 1. "FILTERS_0_ADDRBASE_HIGH,Address MSB register."
line.long 0x10 "fc2sdram_probe_main_Probe_Filters_0_WindowSize,"
hexmask.long.byte 0x10 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr &Mask = AddrBase &Mask. This allows.."
line.long 0x14 "fc2sdram_probe_main_Probe_Filters_0_SecurityBase,"
bitfld.long 0x14 0.--1. "FILTERS_0_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x18 "fc2sdram_probe_main_Probe_Filters_0_SecurityMask,"
bitfld.long 0x18 0.--1. "FILTERS_0_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security &SecurityMask = SecurityBase &SecurityMasks." "0,1,2,3"
line.long 0x1C "fc2sdram_probe_main_Probe_Filters_0_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
bitfld.long 0x1C 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x1C 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x1C 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x1C 0. "RDEN,Selects RD packets." "0,1"
line.long 0x20 "fc2sdram_probe_main_Probe_Filters_0_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
bitfld.long 0x20 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x20 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x24 "fc2sdram_probe_main_Probe_Filters_0_Length,"
hexmask.long.byte 0x24 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0x28 "fc2sdram_probe_main_Probe_Filters_0_Urgency,"
bitfld.long 0x28 0.--1. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
line.long 0x2C "fc2sdram_probe_main_Probe_Filters_0_UserBase,"
hexmask.long 0x2C 0.--31. 1. "FILTERS_0_USERBASE,Register UserBase is available when parameter useUserFilter is set to True. Register size is determined by parameter wUser. The register stores a user base value that is employed in filtering packets."
line.long 0x30 "fc2sdram_probe_main_Probe_Filters_0_UserMask,"
hexmask.long 0x30 0.--31. 1. "FILTERS_0_USERMASK,Register UserMask is available when parameter useUserFilter is set to True.Register size is determined by parameter wUser. The register stores a user mask that is employed in filtering packets. A packet is a candidate for trace or.."
line.long 0x34 "fc2sdram_probe_main_Probe_Filters_0_UserBaseHigh,"
hexmask.long.byte 0x34 0.--7. 1. "FILTERS_0_USERBASEHIGH,Register UserBaseHigh is available when parameter useUserFilter is set to True and wUser>32. Register size is determined by parameter wUser. The register stores a user base value that is employed in filtering packets."
line.long 0x38 "fc2sdram_probe_main_Probe_Filters_0_UserMaskHigh,"
hexmask.long.byte 0x38 0.--7. 1. "FILTERS_0_USERMASKHIGH,Register UserMask is available when parameter useUserFilter is set to True.Register size is determined by parameter wUser. The register stores the msb user bits mask that is employed in filtering packets. A packet is a candidate.."
line.long 0x3C "fc2sdram_probe_main_Probe_Filters_1_RouteIdBase,"
hexmask.long.word 0x3C 0.--14. 1. "FILTERS_1_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x40 "fc2sdram_probe_main_Probe_Filters_1_RouteIdMask,"
hexmask.long.word 0x40 0.--14. 1. "FILTERS_1_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &RouteIdMask = RouteIdBase &RouteIdMask."
line.long 0x44 "fc2sdram_probe_main_Probe_Filters_1_AddrBase_Low,"
hexmask.long 0x44 0.--31. 1. "FILTERS_1_ADDRBASE_LOW,Address LSB register."
line.long 0x48 "fc2sdram_probe_main_Probe_Filters_1_AddrBase_High,"
hexmask.long.word 0x48 0.--8. 1. "FILTERS_1_ADDRBASE_HIGH,Address MSB register."
line.long 0x4C "fc2sdram_probe_main_Probe_Filters_1_WindowSize,"
hexmask.long.byte 0x4C 0.--5. 1. "FILTERS_1_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr &Mask = AddrBase &Mask. This allows.."
line.long 0x50 "fc2sdram_probe_main_Probe_Filters_1_SecurityBase,"
bitfld.long 0x50 0.--1. "FILTERS_1_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x54 "fc2sdram_probe_main_Probe_Filters_1_SecurityMask,"
bitfld.long 0x54 0.--1. "FILTERS_1_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security &SecurityMask = SecurityBase &SecurityMasks." "0,1,2,3"
line.long 0x58 "fc2sdram_probe_main_Probe_Filters_1_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
bitfld.long 0x58 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x58 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x58 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x58 0. "RDEN,Selects RD packets." "0,1"
line.long 0x5C "fc2sdram_probe_main_Probe_Filters_1_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
bitfld.long 0x5C 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x5C 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x60 "fc2sdram_probe_main_Probe_Filters_1_Length,"
hexmask.long.byte 0x60 0.--3. 1. "FILTERS_1_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0x64 "fc2sdram_probe_main_Probe_Filters_1_Urgency,"
bitfld.long 0x64 0.--1. "FILTERS_1_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
line.long 0x68 "fc2sdram_probe_main_Probe_Filters_1_UserBase,"
hexmask.long 0x68 0.--31. 1. "FILTERS_1_USERBASE,Register UserBase is available when parameter useUserFilter is set to True. Register size is determined by parameter wUser. The register stores a user base value that is employed in filtering packets."
line.long 0x6C "fc2sdram_probe_main_Probe_Filters_1_UserMask,"
hexmask.long 0x6C 0.--31. 1. "FILTERS_1_USERMASK,Register UserMask is available when parameter useUserFilter is set to True.Register size is determined by parameter wUser. The register stores a user mask that is employed in filtering packets. A packet is a candidate for trace or.."
line.long 0x70 "fc2sdram_probe_main_Probe_Filters_1_UserBaseHigh,"
hexmask.long.byte 0x70 0.--7. 1. "FILTERS_1_USERBASEHIGH,Register UserBaseHigh is available when parameter useUserFilter is set to True and wUser>32. Register size is determined by parameter wUser. The register stores a user base value that is employed in filtering packets."
line.long 0x74 "fc2sdram_probe_main_Probe_Filters_1_UserMaskHigh,"
hexmask.long.byte 0x74 0.--7. 1. "FILTERS_1_USERMASKHIGH,Register UserMask is available when parameter useUserFilter is set to True.Register size is determined by parameter wUser. The register stores the msb user bits mask that is employed in filtering packets. A packet is a candidate.."
line.long 0x78 "fc2sdram_probe_main_Probe_Filters_2_RouteIdBase,"
hexmask.long.word 0x78 0.--14. 1. "FILTERS_2_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x7C "fc2sdram_probe_main_Probe_Filters_2_RouteIdMask,"
hexmask.long.word 0x7C 0.--14. 1. "FILTERS_2_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &RouteIdMask = RouteIdBase &RouteIdMask."
line.long 0x80 "fc2sdram_probe_main_Probe_Filters_2_AddrBase_Low,"
hexmask.long 0x80 0.--31. 1. "FILTERS_2_ADDRBASE_LOW,Address LSB register."
line.long 0x84 "fc2sdram_probe_main_Probe_Filters_2_AddrBase_High,"
hexmask.long.word 0x84 0.--8. 1. "FILTERS_2_ADDRBASE_HIGH,Address MSB register."
line.long 0x88 "fc2sdram_probe_main_Probe_Filters_2_WindowSize,"
hexmask.long.byte 0x88 0.--5. 1. "FILTERS_2_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr &Mask = AddrBase &Mask. This allows.."
line.long 0x8C "fc2sdram_probe_main_Probe_Filters_2_SecurityBase,"
bitfld.long 0x8C 0.--1. "FILTERS_2_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x90 "fc2sdram_probe_main_Probe_Filters_2_SecurityMask,"
bitfld.long 0x90 0.--1. "FILTERS_2_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security &SecurityMask = SecurityBase &SecurityMasks." "0,1,2,3"
line.long 0x94 "fc2sdram_probe_main_Probe_Filters_2_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
bitfld.long 0x94 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x94 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x94 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x94 0. "RDEN,Selects RD packets." "0,1"
line.long 0x98 "fc2sdram_probe_main_Probe_Filters_2_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
bitfld.long 0x98 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x98 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x9C "fc2sdram_probe_main_Probe_Filters_2_Length,"
hexmask.long.byte 0x9C 0.--3. 1. "FILTERS_2_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0xA0 "fc2sdram_probe_main_Probe_Filters_2_Urgency,"
bitfld.long 0xA0 0.--1. "FILTERS_2_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
line.long 0xA4 "fc2sdram_probe_main_Probe_Filters_2_UserBase,"
hexmask.long 0xA4 0.--31. 1. "FILTERS_2_USERBASE,Register UserBase is available when parameter useUserFilter is set to True. Register size is determined by parameter wUser. The register stores a user base value that is employed in filtering packets."
line.long 0xA8 "fc2sdram_probe_main_Probe_Filters_2_UserMask,"
hexmask.long 0xA8 0.--31. 1. "FILTERS_2_USERMASK,Register UserMask is available when parameter useUserFilter is set to True.Register size is determined by parameter wUser. The register stores a user mask that is employed in filtering packets. A packet is a candidate for trace or.."
line.long 0xAC "fc2sdram_probe_main_Probe_Filters_2_UserBaseHigh,"
hexmask.long.byte 0xAC 0.--7. 1. "FILTERS_2_USERBASEHIGH,Register UserBaseHigh is available when parameter useUserFilter is set to True and wUser>32. Register size is determined by parameter wUser. The register stores a user base value that is employed in filtering packets."
line.long 0xB0 "fc2sdram_probe_main_Probe_Filters_2_UserMaskHigh,"
hexmask.long.byte 0xB0 0.--7. 1. "FILTERS_2_USERMASKHIGH,Register UserMask is available when parameter useUserFilter is set to True.Register size is determined by parameter wUser. The register stores the msb user bits mask that is employed in filtering packets. A packet is a candidate.."
line.long 0xB4 "fc2sdram_probe_main_Probe_Filters_3_RouteIdBase,"
hexmask.long.word 0xB4 0.--14. 1. "FILTERS_3_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0xB8 "fc2sdram_probe_main_Probe_Filters_3_RouteIdMask,"
hexmask.long.word 0xB8 0.--14. 1. "FILTERS_3_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &RouteIdMask = RouteIdBase &RouteIdMask."
line.long 0xBC "fc2sdram_probe_main_Probe_Filters_3_AddrBase_Low,"
hexmask.long 0xBC 0.--31. 1. "FILTERS_3_ADDRBASE_LOW,Address LSB register."
line.long 0xC0 "fc2sdram_probe_main_Probe_Filters_3_AddrBase_High,"
hexmask.long.word 0xC0 0.--8. 1. "FILTERS_3_ADDRBASE_HIGH,Address MSB register."
line.long 0xC4 "fc2sdram_probe_main_Probe_Filters_3_WindowSize,"
hexmask.long.byte 0xC4 0.--5. 1. "FILTERS_3_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr &Mask = AddrBase &Mask. This allows.."
line.long 0xC8 "fc2sdram_probe_main_Probe_Filters_3_SecurityBase,"
bitfld.long 0xC8 0.--1. "FILTERS_3_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0xCC "fc2sdram_probe_main_Probe_Filters_3_SecurityMask,"
bitfld.long 0xCC 0.--1. "FILTERS_3_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security &SecurityMask = SecurityBase &SecurityMasks." "0,1,2,3"
line.long 0xD0 "fc2sdram_probe_main_Probe_Filters_3_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
bitfld.long 0xD0 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0xD0 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0xD0 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0xD0 0. "RDEN,Selects RD packets." "0,1"
line.long 0xD4 "fc2sdram_probe_main_Probe_Filters_3_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
bitfld.long 0xD4 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0xD4 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0xD8 "fc2sdram_probe_main_Probe_Filters_3_Length,"
hexmask.long.byte 0xD8 0.--3. 1. "FILTERS_3_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0xDC "fc2sdram_probe_main_Probe_Filters_3_Urgency,"
bitfld.long 0xDC 0.--1. "FILTERS_3_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
line.long 0xE0 "fc2sdram_probe_main_Probe_Filters_3_UserBase,"
hexmask.long 0xE0 0.--31. 1. "FILTERS_3_USERBASE,Register UserBase is available when parameter useUserFilter is set to True. Register size is determined by parameter wUser. The register stores a user base value that is employed in filtering packets."
line.long 0xE4 "fc2sdram_probe_main_Probe_Filters_3_UserMask,"
hexmask.long 0xE4 0.--31. 1. "FILTERS_3_USERMASK,Register UserMask is available when parameter useUserFilter is set to True.Register size is determined by parameter wUser. The register stores a user mask that is employed in filtering packets. A packet is a candidate for trace or.."
line.long 0xE8 "fc2sdram_probe_main_Probe_Filters_3_UserBaseHigh,"
hexmask.long.byte 0xE8 0.--7. 1. "FILTERS_3_USERBASEHIGH,Register UserBaseHigh is available when parameter useUserFilter is set to True and wUser>32. Register size is determined by parameter wUser. The register stores a user base value that is employed in filtering packets."
line.long 0xEC "fc2sdram_probe_main_Probe_Filters_3_UserMaskHigh,"
hexmask.long.byte 0xEC 0.--7. 1. "FILTERS_3_USERMASKHIGH,Register UserMask is available when parameter useUserFilter is set to True.Register size is determined by parameter wUser. The register stores the msb user bits mask that is employed in filtering packets. A packet is a candidate.."
group.long 0x1938++0x7
line.long 0x0 "fc2sdram_probe_main_Probe_Counters_0_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "fc2sdram_probe_main_Probe_Counters_0_AlarmMode,"
bitfld.long 0x4 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0x1940++0x3
line.long 0x0 "fc2sdram_probe_main_Probe_Counters_0_Val,"
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0x194C++0x7
line.long 0x0 "fc2sdram_probe_main_Probe_Counters_1_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "fc2sdram_probe_main_Probe_Counters_1_AlarmMode,"
bitfld.long 0x4 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0x1954++0x3
line.long 0x0 "fc2sdram_probe_main_Probe_Counters_1_Val,"
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
rgroup.long 0x2080++0x7
line.long 0x0 "ccu_mem0_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "ccu_mem0_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x2088++0x13
line.long 0x0 "ccu_mem0_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--9. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3"
line.long 0x4 "ccu_mem0_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "ccu_mem0_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--14. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "ccu_mem0_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "ccu_mem0_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
rgroup.long 0x2280++0x7
line.long 0x0 "tbu2noc_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "tbu2noc_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x2288++0x13
line.long 0x0 "tbu2noc_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--9. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3"
line.long 0x4 "tbu2noc_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "tbu2noc_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--14. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "tbu2noc_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "tbu2noc_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
rgroup.long 0x4000++0x7
line.long 0x0 "fpga2sdram_manager_main_SidebandManager_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "fpga2sdram_manager_main_SidebandManager_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x4008++0x3
line.long 0x0 "fpga2sdram_manager_main_SidebandManager_FaultEn,"
bitfld.long 0x0 0. "FAULTEN,Global Fault Enable register" "0,1"
rgroup.long 0x400C++0x3
line.long 0x0 "fpga2sdram_manager_main_SidebandManager_FaultStatus,"
bitfld.long 0x0 0. "FAULTSTATUS,Global Fault Status register" "0,1"
group.long 0x4010++0x3
line.long 0x0 "fpga2sdram_manager_main_SidebandManager_FlagInEn0,"
hexmask.long.word 0x0 0.--11. 1. "FLAGINEN0,FlagIn Enable register #0"
rgroup.long 0x4014++0x3
line.long 0x0 "fpga2sdram_manager_main_SidebandManager_FlagInStatus0,"
hexmask.long.word 0x0 0.--11. 1. "FLAGINSTATUS0,FlagIn Status register #0"
group.long 0x4050++0x7
line.long 0x0 "fpga2sdram_manager_main_SidebandManager_FlagOutSet0,"
hexmask.long.word 0x0 0.--8. 1. "FLAGOUTSET0,FlagOut Set register #0"
line.long 0x4 "fpga2sdram_manager_main_SidebandManager_FlagOutClr0,"
hexmask.long.word 0x4 0.--8. 1. "FLAGOUTCLR0,FlagOut Clr register #0"
rgroup.long 0x4058++0x3
line.long 0x0 "fpga2sdram_manager_main_SidebandManager_FlagOutStatus0,"
hexmask.long.word 0x0 0.--8. 1. "FLAGOUTSTATUS0,FlagOut Status register #0"
tree.end
tree "MPFE_FIREWALL"
base ad:0xF8020000
group.long 0x0++0xB
line.long 0x0 "hmc_register,Per-Master Security bit for hmc_register"
bitfld.long 0x0 16. "axi_ap,Security bit configuration for transactions from axi_ap to hmc_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 8. "fpga2soc,Security bit configuration for transactions from fpga2soc to hmc_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to hmc_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "hmc_adaptor_register,Per-Master Security bit for hmc_adaptor_register"
bitfld.long 0x4 16. "axi_ap,Security bit configuration for transactions from axi_ap to hmc_adaptor_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 8. "fpga2soc,Security bit configuration for transactions from fpga2soc to hmc_adaptor_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to hmc_adaptor_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x8 "noc_scheduler_csr,Per-Master Security bit for ddr_scheduler_register"
bitfld.long 0x8 16. "axi_ap,Security bit configuration for transactions from axi_ap to ddr_scheduler_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 8. "fpga2soc,Security bit configuration for transactions from fpga2soc to ddr_scheduler_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 0. "mpu,Security bit configuration for transactions from mpu to ddr_scheduler_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0x10++0xB
line.long 0x0 "noc_qos,Per-Master Security bit for noc_qos_register"
bitfld.long 0x0 16. "axi_ap,Security bit configuration for transactions from axi_ap to noc_qos. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 8. "fpga2soc,Security bit configuration for transactions from fpga2soc to noc_qos. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to noc_qos. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "noc_probes,Per-Master Security bit for noc_probes_register"
bitfld.long 0x4 16. "axi_ap,Security bit configuration for transactions from axi_ap to noc_probes. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 8. "fpga2soc,Security bit configuration for transactions from mpu to noc_probes. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to noc_probes. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x8 "fpga2sdram_sidebandmgr,Per-Master Security bit for fpga2sdram_sidebandmgr"
bitfld.long 0x8 16. "axi_ap,Security bit configuration for transactions from axi_ap to fpga2sdram_sidebandmgr. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 8. "fpga2soc,Security bit configuration for transactions from fpga2soc to fpga2sdram_sidebandmgr. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 0. "mpu,Security bit configuration for transactions from mpu to fpga2sdram_sidebandmgr. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
tree.end
tree "MPU_FIREWALL"
base ad:0xF8020200
group.long 0x0++0x3
line.long 0x0 "enable,Enable"
bitfld.long 0x0 15. "nonmpuregion7enable,non MPU Region 7 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 14. "nonmpuregion6enable,non MPU Region 6 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 13. "nonmpuregion5enable,non MPU Region 5 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 12. "nonmpuregion4enable,non MPU Region 4 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
newline
bitfld.long 0x0 11. "nonmpuregion3enable,non MPU Region 3 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 10. "nonmpuregion2enable,non MPU Region 2 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 9. "nonmpuregion1enable,non MPU Region 1 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 8. "nonmpuregion0enable,non MPU Region 0 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
newline
bitfld.long 0x0 7. "mpuregion7enable,MPU Region 7 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 6. "mpuregion6enable,MPU Region 6 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 5. "mpuregion5enable,MPURegion 5 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 4. "mpuregion4enable,MPURegion 4 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
newline
bitfld.long 0x0 3. "mpuregion3enable,MPU Region 3 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 2. "mpuregion2enable,MPU Region 2 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 1. "mpuregion1enable,MPU Region 1 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 0. "mpuregion0enable,MPU Region 0 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
wgroup.long 0x4++0x7
line.long 0x0 "enable_set,Sets Master Region Enable field when written with 1"
bitfld.long 0x0 15. "nonmpuregion7enable,non MPU Region 7 Enable Set." "0,1"
bitfld.long 0x0 14. "nonmpuregion6enable,non MPU Region 6 Enable Set." "0,1"
bitfld.long 0x0 13. "nonmpuregion5enable,non MPU Region 5 Enable Set." "0,1"
bitfld.long 0x0 12. "nonmpuregion4enable,non MPU Region 4 Enable Set." "0,1"
newline
bitfld.long 0x0 11. "nonmpuregion3enable,non MPU Region 3 Enable Set." "0,1"
bitfld.long 0x0 10. "nonmpuregion2enable,non MPU Region 2 Enable Set." "0,1"
bitfld.long 0x0 9. "nonmpuregion1enable,non MPU Region 1 Enable Set." "0,1"
bitfld.long 0x0 8. "nonmpuregion0enable,non MPU Region 0 Enable Set." "0,1"
newline
bitfld.long 0x0 7. "mpuregion7enable,MPU Region 7 Enable Set." "0,1"
bitfld.long 0x0 6. "mpuregion6enable,MPU Region 6 Enable Set." "0,1"
bitfld.long 0x0 5. "mpuregion5enable,MPU Region 5 Enable Set." "0,1"
bitfld.long 0x0 4. "mpuregion4enable,MPU Region 4 Enable Set." "0,1"
newline
bitfld.long 0x0 3. "mpuregion3enable,MPU Region 3 Enable Set." "0,1"
bitfld.long 0x0 2. "mpuregion2enable,MPU Region 2 Enable Set." "0,1"
bitfld.long 0x0 1. "mpuregion1enable,MPU Region 1 Enable Set." "0,1"
bitfld.long 0x0 0. "mpuregion0enable,MPU Region 0 Enable Set." "0,1"
line.long 0x4 "enable_clear,Clears Master Region Enable field when written with 1"
eventfld.long 0x4 15. "nonmpuregion7enable,non MPU Region 7 Enable Clear." "0,1"
eventfld.long 0x4 14. "nonmpuregion6enable,non MPU Region 6 Enable Clear." "0,1"
eventfld.long 0x4 13. "nonmpuregion5enable,non MPU Region 5 Enable Clear." "0,1"
eventfld.long 0x4 12. "nonmpuregion4enable,non MPU Region 4 Enable Clear." "0,1"
newline
eventfld.long 0x4 11. "nonmpuregion3enable,non MPU Region 3 Enable Clear." "0,1"
eventfld.long 0x4 10. "nonmpuregion2enable,non MPU Region 2 Enable Clear." "0,1"
eventfld.long 0x4 9. "nonmpuregion1enable,non MPU Region 1 Enable Clear." "0,1"
eventfld.long 0x4 8. "nonmpuregion0enable,non MPU Region 0 Enable Clear." "0,1"
newline
eventfld.long 0x4 7. "mpuregion7enable,MPU Region 7 Enable Clear." "0,1"
eventfld.long 0x4 6. "mpuregion6enable,MPU Region 6 Enable Clear." "0,1"
eventfld.long 0x4 5. "mpuregion5enable,MPU Region 5 Enable Clear." "0,1"
eventfld.long 0x4 4. "mpuregion4enable,MPU Region 4 Enable Clear." "0,1"
newline
eventfld.long 0x4 3. "mpuregion3enable,MPU Region 3 Enable Clear." "0,1"
eventfld.long 0x4 2. "mpuregion2enable,MPU Region 2 Enable Clear." "0,1"
eventfld.long 0x4 1. "mpuregion1enable,MPU Region 1 Enable Clear." "0,1"
eventfld.long 0x4 0. "mpuregion0enable,MPU Region 0 Enable Clear." "0,1"
group.long 0x10++0xFF
line.long 0x0 "mpuregion0addr_base,Base definition for MPU Region 0"
hexmask.long.word 0x0 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x0 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x4 "mpuregion0addr_baseext,base extended definition for MPU Region 0"
hexmask.long.byte 0x4 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0x8 "mpuregion0addr_limit,Limit definition for MPU Region 0"
hexmask.long.word 0x8 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0x8 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0xC "mpuregion0addr_limitext,limit extended definition for MPU Region 0"
hexmask.long.byte 0xC 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0x10 "mpuregion1addr_base,Base definition for MPU Region 1"
hexmask.long.word 0x10 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x10 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x14 "mpuregion1addr_baseext,base extended definition for MPU Region 1"
hexmask.long.byte 0x14 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0x18 "mpuregion1addr_limit,Limit definition for MPU Region 1"
hexmask.long.word 0x18 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0x18 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0x1C "mpuregion1addr_limitext,limit extended definition for MPU Region 1"
hexmask.long.byte 0x1C 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0x20 "mpuregion2addr_base,Base definition for MPU Region 2"
hexmask.long.word 0x20 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x20 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x24 "mpuregion2addr_baseext,base extended definition for MPU Region 2"
hexmask.long.byte 0x24 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0x28 "mpuregion2addr_limit,Limit definition for MPU Region 2"
hexmask.long.word 0x28 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0x28 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0x2C "mpuregion2addr_limitext,limit extended definition for MPU Region 2"
hexmask.long.byte 0x2C 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0x30 "mpuregion3addr_base,Base definition for MPU Region 3"
hexmask.long.word 0x30 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x30 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x34 "mpuregion3addr_baseext,base extended definition for MPU Region 3"
hexmask.long.byte 0x34 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0x38 "mpuregion3addr_limit,Limit definition for MPU Region 3"
hexmask.long.word 0x38 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0x38 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0x3C "mpuregion3addr_limitext,limit extended definition for MPU Region 3"
hexmask.long.byte 0x3C 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0x40 "mpuregion4addr_base,Base definition for MPU Region 4"
hexmask.long.word 0x40 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x40 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x44 "mpuregion4addr_baseext,base extended definition for MPU Region 4"
hexmask.long.byte 0x44 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0x48 "mpuregion4addr_limit,Limit definition for MPU Region 4"
hexmask.long.word 0x48 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0x48 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0x4C "mpuregion4addr_limitext,limit extended definition for MPU Region 4"
hexmask.long.byte 0x4C 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0x50 "mpuregion5addr_base,Base definition for MPU Region 5"
hexmask.long.word 0x50 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x50 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x54 "mpuregion5addr_baseext,base extended definition for MPU Region 5"
hexmask.long.byte 0x54 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0x58 "mpuregion5addr_limit,Limit definition for MPU Region 5"
hexmask.long.word 0x58 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0x58 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0x5C "mpuregion5addr_limitext,limit extended definition for MPU Region 5"
hexmask.long.byte 0x5C 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0x60 "mpuregion6addr_base,Base definition for MPU Region 6"
hexmask.long.word 0x60 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x60 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x64 "mpuregion6addr_baseext,base extended definition for MPU Region 6"
hexmask.long.byte 0x64 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0x68 "mpuregion6addr_limit,Limit definition for MPU Region 6"
hexmask.long.word 0x68 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0x68 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0x6C "mpuregion6addr_limitext,limit extended definition for MPU Region 6"
hexmask.long.byte 0x6C 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0x70 "mpuregion7addr_base,Base definition for MPU Region 7"
hexmask.long.word 0x70 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x70 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x74 "mpuregion7addr_baseext,base extended definition for MPU Region 7"
hexmask.long.byte 0x74 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0x78 "mpuregion7addr_limit,Limit definition for MPU Region 7"
hexmask.long.word 0x78 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0x78 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0x7C "mpuregion7addr_limitext,limit extended definition for MPU Region 7"
hexmask.long.byte 0x7C 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0x80 "nonmpuregion0addr_base,Base definition for non MPU Region 0"
hexmask.long.word 0x80 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x80 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x84 "nonmpuregion0addr_baseext,base extended definition for non MPU Region 0"
hexmask.long.byte 0x84 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0x88 "nonmpuregion0addr_limit,Limit definition for non MPU Region 0"
hexmask.long.word 0x88 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0x88 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0x8C "nonmpuregion0addr_limitext,limit extended definition for non MPU Region 0"
hexmask.long.byte 0x8C 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0x90 "nonmpuregion1addr_base,Base definition for non MPU Region 1"
hexmask.long.word 0x90 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x90 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x94 "nonmpuregion1addr_baseext,base extended definition for non MPU Region 1"
hexmask.long.byte 0x94 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0x98 "nonmpuregion1addr_limit,Limit definition for non MPU Region 1"
hexmask.long.word 0x98 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0x98 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0x9C "nonmpuregion1addr_limitext,limit extended definition for non MPU Region 1"
hexmask.long.byte 0x9C 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0xA0 "nonmpuregion2addr_base,Base definition for non MPU Region 2"
hexmask.long.word 0xA0 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0xA0 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0xA4 "nonmpuregion2addr_baseext,base extended definition for non MPU Region 2"
hexmask.long.byte 0xA4 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0xA8 "nonmpuregion2addr_limit,Limit definition for non MPU Region 2"
hexmask.long.word 0xA8 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0xA8 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0xAC "nonmpuregion2addr_limitext,limit extended definition for non MPU Region 2"
hexmask.long.byte 0xAC 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0xB0 "nonmpuregion3addr_base,Base definition for non MPU Region 3"
hexmask.long.word 0xB0 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0xB0 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0xB4 "nonmpuregion3addr_baseext,base extended definition for non MPU Region 3"
hexmask.long.byte 0xB4 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0xB8 "nonmpuregion3addr_limit,Limit definition for non MPU Region 3"
hexmask.long.word 0xB8 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0xB8 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0xBC "nonmpuregion3addr_limitext,limit extended definition for non MPU Region 3"
hexmask.long.byte 0xBC 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0xC0 "nonmpuregion4addr_base,Base definition for non MPU Region 4"
hexmask.long.word 0xC0 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0xC0 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0xC4 "nonmpuregion4addr_baseext,base extended definition for non MPU Region 4"
hexmask.long.byte 0xC4 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0xC8 "nonmpuregion4addr_limit,Limit definition for non MPU Region 4"
hexmask.long.word 0xC8 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0xC8 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0xCC "nonmpuregion4addr_limitext,limit extended definition for non MPU Region 4"
hexmask.long.byte 0xCC 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0xD0 "nonmpuregion5addr_base,Base definition for non MPU Region 5"
hexmask.long.word 0xD0 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0xD0 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0xD4 "nonmpuregion5addr_baseext,base extended definition for non MPU Region 5"
hexmask.long.byte 0xD4 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0xD8 "nonmpuregion5addr_limit,Limit definition for non MPU Region 5"
hexmask.long.word 0xD8 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0xD8 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0xDC "nonmpuregion5addr_limitext,limit extended definition for non MPU Region 5"
hexmask.long.byte 0xDC 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0xE0 "nonmpuregion6addr_base,Base definition for non MPU Region 6"
hexmask.long.word 0xE0 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0xE0 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0xE4 "nonmpuregion6addr_baseext,base extended definition for non MPU Region 6"
hexmask.long.byte 0xE4 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0xE8 "nonmpuregion6addr_limit,Limit definition for non MPU Region 6"
hexmask.long.word 0xE8 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0xE8 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0xEC "nonmpuregion6addr_limitext,limit extended definition for non MPU Region 6"
hexmask.long.byte 0xEC 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
line.long 0xF0 "nonmpuregion7addr_base,Base definition for non MPU Region 7"
hexmask.long.word 0xF0 16.--31. 1. "high,defines the 16 bit MSB of the base address field."
hexmask.long.word 0xF0 0.--15. 1. "low,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0xF4 "nonmpuregion7addr_baseext,base extended definition for non MPU Region 7"
hexmask.long.byte 0xF4 0.--7. 1. "low,defines the 8 bit LSB of the base extended address field."
line.long 0xF8 "nonmpuregion7addr_limit,Limit definition for non MPU Region 7"
hexmask.long.word 0xF8 16.--31. 1. "high,defines the 16 bit MSB of the limit address field."
hexmask.long.word 0xF8 0.--15. 1. "low,LSB field is all one. Region end address is {limitext limit  16'hFFFF}"
line.long 0xFC "nonmpuregion7addr_limitext,limit extended definition for non MPU Region 7"
hexmask.long.byte 0xFC 0.--7. 1. "low,defines the 8 bit LSB of the limit extended address field."
tree.end
tree.end
tree "DMA (Direct Memory Access Controller)"
base ad:0x0
tree "DMANONSECURE (DMAC Non-Secure Module Registers)"
base ad:0xFFDA0000
group.long 0x0++0x3
line.long 0x0 "Data,Placeholder"
hexmask.long 0x0 0.--31. 1. "Field,Empty"
tree.end
tree "DMASECURE (DMAC Secure Module Registers)"
base ad:0xFFDA1000
group.long 0x0++0x3
line.long 0x0 "Data,Placeholder"
hexmask.long 0x0 0.--31. 1. "Field,"
tree.end
tree.end
tree "ECC (Error Checking and Correction Controller)"
base ad:0x0
tree "DMAECC (DMAC ECC)"
base ad:0xFF8C9000
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "EMAC0RXECC (EMAC0 RX ECC)"
base ad:0xFF8C0000
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "EMAC0TXECC (EMAC0 TX ECC)"
base ad:0xFF8C0400
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "EMAC1RXECC (EMAC1 RX ECC)"
base ad:0xFF8C0800
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "EMAC1TXECC (EMAC1 TX ECC)"
base ad:0xFF8C0C00
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "EMAC2RXECC (EMAC2 RX ECC)"
base ad:0xFF8C1000
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "EMAC2TXECC (EMAC2 TX ECC)"
base ad:0xFF8C1400
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "NANDECC (NAND ECC)"
base ad:0xFF8C8000
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "NANDREADECC (NAND READ ECC)"
base ad:0xFF8C8400
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "NANDWRITEECC (NAND WRITE ECC)"
base ad:0xFF8C8800
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "OCRAMECC (OCRAM ECC)"
base ad:0xFF8CC000
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "SDMMCECC"
base ad:0xFF8C8C00
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev #"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size. Total number of ECC bits is dependent on the number of encoder/decoder implemented. This is specifying the width of the ECC syndrome." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)  Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "USB0ECC (USB0 ECC)"
base ad:0xFF8C4000
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "USB1ECC (USB1 ECC)"
base ad:0xFF8C4400
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree.end
tree "EMAC (Ethernet MAC)"
base ad:0x0
tree "EMAC0 (EMAC0 Module)"
base ad:0xFF800000
group.long 0x0++0x7
line.long 0x0 "gmacgrp_mac_configuration,Register 0 (MAC Configuration Register)"
rbitfld.long 0x0 31. "reserved_31,Reserved" "0,1"
newline
bitfld.long 0x0 28.--30. "sarc,Source Address Insertion or Replacement Control" "?,?,2: ,3: ,?,?,?,?"
newline
bitfld.long 0x0 27. "twokpe,IEEE 802.3as Support for 2K Packets" "0,1"
newline
rbitfld.long 0x0 26. "sfterr,SMII Force Transmit Error" "0,1"
newline
bitfld.long 0x0 25. "cst,CRC Stripping for Type Frames" "0,1"
newline
rbitfld.long 0x0 24. "tc,Transmit Configuration in RGMII  SGMII  or SMII" "0,1"
newline
bitfld.long 0x0 23. "wd,Watchdog Disable" "0,1"
newline
bitfld.long 0x0 22. "jd,Jabber Disable" "0,1"
newline
bitfld.long 0x0 21. "be,Frame Burst Enable" "0,1"
newline
bitfld.long 0x0 20. "je,Jumbo Frame Enable" "0,1"
newline
bitfld.long 0x0 17.--19. "ifg,Inter-Frame Gap" "0: 96 bit times,1: 88 bit times,?,?,?,?,?,?"
newline
bitfld.long 0x0 16. "dcrs,Disable Carrier Sense During Transmission" "0,1"
newline
bitfld.long 0x0 15. "ps,Port Select" "0: For 1000 Mbps operations,1: For 10 or 100 Mbps operations"
newline
bitfld.long 0x0 14. "fes,Speed" "0: 10 Mbps,1: 100 Mbps"
newline
bitfld.long 0x0 13. "do,Disable Receive Own" "0,1"
newline
bitfld.long 0x0 12. "lm,Loopback Mode" "0,1"
newline
bitfld.long 0x0 11. "dm,Duplex Mode" "0,1"
newline
bitfld.long 0x0 10. "ipc,Checksum Offload" "0,1"
newline
bitfld.long 0x0 9. "dr,Disable Retry" "0,1"
newline
rbitfld.long 0x0 8. "lud,Link Up or Down" "0: Link Down,1: Link Up"
newline
bitfld.long 0x0 7. "acs,Automatic Pad or CRC Stripping" "0,1"
newline
bitfld.long 0x0 5.--6. "bl,Back-Off Limit" "0: k = min,1: k = min,?,?"
newline
bitfld.long 0x0 4. "dc,Deferral Check" "0,1"
newline
bitfld.long 0x0 3. "te,Transmitter Enable" "0,1"
newline
bitfld.long 0x0 2. "re,Receiver Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "prelen,Preamble Length for Transmit Frames" "0: 7 bytes of preamble,1: 5 byte of preamble,2: 3 bytes of preamble,3: 1 byte of preamble"
line.long 0x4 "gmacgrp_mac_frame_filter,Register 1 (MAC Frame Filter)"
bitfld.long 0x4 31. "ra,Receive All" "0,1"
newline
hexmask.long.word 0x4 22.--30. 1. "reserved_30_22,Reserved"
newline
bitfld.long 0x4 21. "dntu,Drop non-TCP/UDP over IP Frames" "0,1"
newline
bitfld.long 0x4 20. "ipfe,Layer 3 and Layer 4 Filter Enable" "0,1"
newline
rbitfld.long 0x4 17.--19. "reserved_19_17,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 16. "vtfe,VLAN Tag Filter Enable" "0,1"
newline
hexmask.long.byte 0x4 11.--15. 1. "reserved_15_11,Reserved"
newline
rbitfld.long 0x4 10. "hpf,Hash or Perfect Filter" "0,1"
newline
bitfld.long 0x4 9. "saf,Source Address Filter Enable" "0,1"
newline
bitfld.long 0x4 8. "saif,SA Inverse Filtering" "0,1"
newline
bitfld.long 0x4 6.--7. "pcf,Pass Control Frames" "0: MAC filters all control frames from reaching the..,1: The MAC is in the full-duplex mode and flow..,2: The destination address,3: The Type field of the received frame is 0x8808.."
newline
bitfld.long 0x4 5. "dbf,Disable Broadcast Frames" "0,1"
newline
bitfld.long 0x4 4. "pm,Pass All Multicast" "0,1"
newline
bitfld.long 0x4 3. "daif,DA Inverse Filtering" "0,1"
newline
rbitfld.long 0x4 2. "hmc,Hash Multicast" "0,1"
newline
rbitfld.long 0x4 1. "huc,Hash Unicast" "0,1"
newline
bitfld.long 0x4 0. "pr,Promiscuous Mode" "0,1"
group.long 0x10++0xF
line.long 0x0 "gmacgrp_gmii_address,Register 4 (GMII Address Register)"
hexmask.long.word 0x0 16.--31. 1. "reserved_31_16,Reserved"
newline
hexmask.long.byte 0x0 11.--15. 1. "pa,Physical Layer Address"
newline
hexmask.long.byte 0x0 6.--10. 1. "gr,GMII Register"
newline
hexmask.long.byte 0x0 2.--5. 1. "cr,CSR Clock Range"
newline
bitfld.long 0x0 1. "gw,GMII Write" "0,1"
newline
bitfld.long 0x0 0. "gb,GMII Busy" "0,1"
line.long 0x4 "gmacgrp_gmii_data,Register 5 (GMII Data Register)"
hexmask.long.word 0x4 16.--31. 1. "reserved_31_16,Reserved"
newline
hexmask.long.word 0x4 0.--15. 1. "gd,GMII Data"
line.long 0x8 "gmacgrp_flow_control,Register 6 (Flow Control Register)"
hexmask.long.word 0x8 16.--31. 1. "pt,Pause Time"
newline
hexmask.long.byte 0x8 8.--15. 1. "reserved_15_8,Reserved"
newline
bitfld.long 0x8 7. "dzpq,Disable Zero-Quanta Pause" "0,1"
newline
rbitfld.long 0x8 6. "reserved_6,Reserved" "0,1"
newline
bitfld.long 0x8 4.--5. "plt,Pause Low Threshold" "0: The threshold is Pause time minus 4 slot times,1: The threshold is Pause time minus 28 slot times,?,?"
newline
bitfld.long 0x8 3. "up,Unicast Pause Frame Detect" "0,1"
newline
bitfld.long 0x8 2. "rfe,Receive Flow Control Enable" "0,1"
newline
bitfld.long 0x8 1. "tfe,Transmit Flow Control Enable" "0,1"
newline
bitfld.long 0x8 0. "fca_bpa,Flow Control Busy or Backpressure Activate" "0,1"
line.long 0xC "gmacgrp_vlan_tag,Register 7 (VLAN Tag Register)"
hexmask.long.word 0xC 20.--31. 1. "reserved_31_20,Reserved"
newline
rbitfld.long 0xC 19. "vthm,VLAN Tag Hash Table Match Enable" "0,1"
newline
bitfld.long 0xC 18. "esvl,Enable S-VLAN" "0,1"
newline
bitfld.long 0xC 17. "vtim,VLAN Tag Inverse Match Enable" "0,1"
newline
bitfld.long 0xC 16. "etv,Enable 12-Bit VLAN Tag Comparison" "0,1"
newline
hexmask.long.word 0xC 0.--15. 1. "vl,VLAN Tag Identifier for Receive Frames"
rgroup.long 0x20++0x7
line.long 0x0 "gmacgrp_version,Register 8 (Version Register)"
hexmask.long.word 0x0 16.--31. 1. "reserved_31_16,Reserved"
newline
hexmask.long.byte 0x0 8.--15. 1. "userver,User-defined Version (Configured with the coreConsultant)"
newline
hexmask.long.byte 0x0 0.--7. 1. "snpsver,Synopsys-defined Version (3.7)"
line.long 0x4 "gmacgrp_debug,Register 9 (Debug Register)"
hexmask.long.byte 0x4 26.--31. 1. "reserved_31_26,Reserved"
newline
bitfld.long 0x4 25. "txstsfsts,MTL TxStatus FIFO Full Status" "0,1"
newline
bitfld.long 0x4 24. "txfsts,MTL Tx FIFO Not Empty Status" "0,1"
newline
bitfld.long 0x4 23. "reserved_23,Reserved" "0,1"
newline
bitfld.long 0x4 22. "twcsts,MTL Tx FIFO Write Controller Active Status" "0,1"
newline
bitfld.long 0x4 20.--21. "trcsts,MTL Tx FIFO Read Controller Status" "0: IDLE state,1: READ state,?,?"
newline
bitfld.long 0x4 19. "txpaused,MAC transmitter in PAUSE" "0,1"
newline
bitfld.long 0x4 17.--18. "tfcsts,MAC Transmit Frame Controller Status" "0: IDLE state,1: Waiting for Status of previous frame or IFG or..,?,?"
newline
bitfld.long 0x4 16. "tpests,MAC GMII or MII Transmit Protocol Engine Status" "0,1"
newline
hexmask.long.byte 0x4 10.--15. 1. "reserved_15_10,Reserved"
newline
bitfld.long 0x4 8.--9. "rxfsts,MTL Rx FIFO Fill-level Status" "0: Rx FIFO Empty,1: Rx FIFO fill level is below the flow-control..,?,?"
newline
bitfld.long 0x4 7. "reserved_7,Reserved" "0,1"
newline
bitfld.long 0x4 5.--6. "rrcsts,MTL Rx FIFO Read Controller State" "0: IDLE state,1: Reading frame data,?,?"
newline
bitfld.long 0x4 4. "rwcsts,MTL Rx FIFO Write Controller Active Status" "0,1"
newline
bitfld.long 0x4 3. "reserved_3,Reserved" "0,1"
newline
bitfld.long 0x4 1.--2. "rfcfcsts,MAC Receive Frame Controller FIFO Status" "0,1,2,3"
newline
bitfld.long 0x4 0. "rpests,MAC GMII or MII Receive Protocol Engine Status" "0,1"
group.long 0x30++0x7
line.long 0x0 "gmacgrp_lpi_control_status,Register 12 (LPI Control and Status Register)"
hexmask.long.word 0x0 20.--31. 1. "reserved_31_20,Reserved"
newline
bitfld.long 0x0 19. "lpitxa,LPI TX Automate" "0,1"
newline
rbitfld.long 0x0 18. "plsen,PHY Link Status Enable" "0,1"
newline
bitfld.long 0x0 17. "pls,PHY Link Status" "0,1"
newline
bitfld.long 0x0 16. "lpien,LPI Enable" "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "reserved_15_10,Reserved"
newline
rbitfld.long 0x0 9. "rlpist,Receive LPI State" "0,1"
newline
rbitfld.long 0x0 8. "tlpist,Transmit LPI State" "0,1"
newline
hexmask.long.byte 0x0 4.--7. 1. "reserved_7_4,Reserved"
newline
rbitfld.long 0x0 3. "rlpiex,Receive LPI Exit" "0,1"
newline
rbitfld.long 0x0 2. "rlpien,Receive LPI Entry" "0,1"
newline
rbitfld.long 0x0 1. "tlpiex,Transmit LPI Exit" "0,1"
newline
rbitfld.long 0x0 0. "tlpien,Transmit LPI Entry" "0,1"
line.long 0x4 "gmacgrp_lpi_timers_control,Register 13 (LPI Timers Control Register)"
hexmask.long.byte 0x4 26.--31. 1. "reserved_31_26,Reserved"
newline
hexmask.long.word 0x4 16.--25. 1. "lst,LPI LS Timer"
newline
hexmask.long.word 0x4 0.--15. 1. "twt,LPI TW Timer"
rgroup.long 0x38++0x3
line.long 0x0 "gmacgrp_interrupt_status,Register 14 (Interrupt Register)"
hexmask.long.tbyte 0x0 12.--31. 1. "reserved_31_12,Reserved"
newline
bitfld.long 0x0 11. "gpiis,GPI Interrupt Status" "0,1"
newline
bitfld.long 0x0 10. "lpiis,LPI Interrupt Status" "0,1"
newline
bitfld.long 0x0 9. "tsis,Timestamp Interrupt Status" "0,1"
newline
bitfld.long 0x0 8. "reserved_8,Reserved" "0,1"
newline
bitfld.long 0x0 7. "mmcrxipis,MMC Receive Checksum Offload Interrupt Status" "0,1"
newline
bitfld.long 0x0 6. "mmctxis,MMC Transmit Interrupt Status" "0,1"
newline
bitfld.long 0x0 5. "mmcrxis,MMC Receive Interrupt Status" "0,1"
newline
bitfld.long 0x0 4. "mmcis,MMC Interrupt Status" "0,1"
newline
bitfld.long 0x0 3. "pmtis,PMT Interrupt Status" "0,1"
newline
bitfld.long 0x0 2. "pcsancis,PCS Auto-Negotiation Complete" "0,1"
newline
bitfld.long 0x0 1. "pcslchgis,PCS Link Status Changed" "0,1"
newline
bitfld.long 0x0 0. "rgsmiiis,RGMII or SMII Interrupt Status" "0,1"
group.long 0x3C++0x83
line.long 0x0 "gmacgrp_interrupt_mask,Register 15 (Interrupt Mask Register)"
hexmask.long.tbyte 0x0 11.--31. 1. "reserved_31_11,Reserved"
newline
bitfld.long 0x0 10. "lpiim,LPI Interrupt Mask" "0,1"
newline
rbitfld.long 0x0 9. "tsim,Timestamp Interrupt Mask" "0,1"
newline
hexmask.long.byte 0x0 4.--8. 1. "reserved_8_4,Reserved"
newline
bitfld.long 0x0 3. "pmtim,PMT Interrupt Mask" "0,1"
newline
rbitfld.long 0x0 2. "pcsancim,PCS AN Completion Interrupt Mask" "0,1"
newline
rbitfld.long 0x0 1. "pcslchgim,PCS Link Status Interrupt Mask" "0,1"
newline
rbitfld.long 0x0 0. "rgsmiiim,RGMII or SMII Interrupt Mask" "0,1"
line.long 0x4 "gmacgrp_mac_address0_high,Register 16 (MAC Address0 High Register)"
rbitfld.long 0x4 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x4 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x4 0.--15. 1. "addrhi,MAC Address0 [47:32]"
line.long 0x8 "gmacgrp_mac_address0_low,Register 17 (MAC Address0 Low Register)"
hexmask.long 0x8 0.--31. 1. "addrlo,MAC Address0 [31:0]"
line.long 0xC "gmacgrp_mac_address1_high,Register 18 (MAC Address1 High Register)"
bitfld.long 0xC 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0xC 30. "sa,Source Address" "0,1"
newline
bitfld.long 0xC 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0xC 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0xC 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0xC 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0xC 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0xC 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0xC 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0xC 0.--15. 1. "addrhi,MAC Address1 [47:32]"
line.long 0x10 "gmacgrp_mac_address1_low,Register 19 (MAC Address1 Low Register)"
hexmask.long 0x10 0.--31. 1. "addrlo,MAC Address1 [31:0]"
line.long 0x14 "gmacgrp_mac_address2_high,Register 20 (MAC Address2 High Register)"
bitfld.long 0x14 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x14 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x14 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x14 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x14 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x14 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x14 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x14 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x14 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x14 0.--15. 1. "addrhi,MAC Address2 [47:32]"
line.long 0x18 "gmacgrp_mac_address2_low,Register 21 (MAC Address2 Low Register)"
hexmask.long 0x18 0.--31. 1. "addrlo,MAC Address2 [31:0]"
line.long 0x1C "gmacgrp_mac_address3_high,Register 22 (MAC Address3 High Register)"
bitfld.long 0x1C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x1C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x1C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x1C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x1C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x1C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x1C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x1C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x1C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x1C 0.--15. 1. "addrhi,MAC Address3 [47:32]"
line.long 0x20 "gmacgrp_mac_address3_low,Register 23 (MAC Address3 Low Register)"
hexmask.long 0x20 0.--31. 1. "addrlo,MAC Address3 [31:0]"
line.long 0x24 "gmacgrp_mac_address4_high,Register 24 (MAC Address4 High Register)"
bitfld.long 0x24 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x24 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x24 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x24 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x24 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x24 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x24 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x24 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x24 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x24 0.--15. 1. "addrhi,MAC Address4 [47:32]"
line.long 0x28 "gmacgrp_mac_address4_low,Register 25 (MAC Address4 Low Register)"
hexmask.long 0x28 0.--31. 1. "addrlo,MAC Address4 [31:0]"
line.long 0x2C "gmacgrp_mac_address5_high,Register 26 (MAC Address5 High Register)"
bitfld.long 0x2C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x2C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x2C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x2C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x2C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x2C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x2C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x2C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x2C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x2C 0.--15. 1. "addrhi,MAC Address5 [47:32]"
line.long 0x30 "gmacgrp_mac_address5_low,Register 27 (MAC Address5 Low Register)"
hexmask.long 0x30 0.--31. 1. "addrlo,MAC Address5 [31:0]"
line.long 0x34 "gmacgrp_mac_address6_high,Register 28 (MAC Address6 High Register)"
bitfld.long 0x34 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x34 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x34 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x34 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x34 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x34 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x34 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x34 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x34 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x34 0.--15. 1. "addrhi,MAC Address6 [47:32]"
line.long 0x38 "gmacgrp_mac_address6_low,Register 29 (MAC Address6 Low Register)"
hexmask.long 0x38 0.--31. 1. "addrlo,MAC Address6 [31:0]"
line.long 0x3C "gmacgrp_mac_address7_high,Register 30 (MAC Address7 High Register)"
bitfld.long 0x3C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x3C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x3C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x3C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x3C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x3C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x3C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x3C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x3C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x3C 0.--15. 1. "addrhi,MAC Address7 [47:32]"
line.long 0x40 "gmacgrp_mac_address7_low,Register 31 (MAC Address7 Low Register)"
hexmask.long 0x40 0.--31. 1. "addrlo,MAC Address7 [31:0]"
line.long 0x44 "gmacgrp_mac_address8_high,Register 32 (MAC Address8 High Register)"
bitfld.long 0x44 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x44 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x44 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x44 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x44 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x44 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x44 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x44 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x44 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x44 0.--15. 1. "addrhi,MAC Address8 [47:32]"
line.long 0x48 "gmacgrp_mac_address8_low,Register 33 (MAC Address8 Low Register)"
hexmask.long 0x48 0.--31. 1. "addrlo,MAC Address8 [31:0]"
line.long 0x4C "gmacgrp_mac_address9_high,Register 34 (MAC Address9 High Register)"
bitfld.long 0x4C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x4C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x4C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x4C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x4C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x4C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x4C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x4C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x4C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x4C 0.--15. 1. "addrhi,MAC Address9 [47:32]"
line.long 0x50 "gmacgrp_mac_address9_low,Register 35 (MAC Address9 Low Register)"
hexmask.long 0x50 0.--31. 1. "addrlo,MAC Address9 [31:0]"
line.long 0x54 "gmacgrp_mac_address10_high,Register 36 (MAC Address10 High Register)"
bitfld.long 0x54 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x54 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x54 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x54 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x54 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x54 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x54 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x54 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x54 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x54 0.--15. 1. "addrhi,MAC Address10 [47:32]"
line.long 0x58 "gmacgrp_mac_address10_low,Register 37 (MAC Address10 Low Register)"
hexmask.long 0x58 0.--31. 1. "addrlo,MAC Address10 [31:0]"
line.long 0x5C "gmacgrp_mac_address11_high,Register 38 (MAC Address11 High Register)"
bitfld.long 0x5C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x5C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x5C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x5C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x5C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x5C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x5C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x5C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x5C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x5C 0.--15. 1. "addrhi,MAC Address11 [47:32]"
line.long 0x60 "gmacgrp_mac_address11_low,Register 39 (MAC Address1 Low Register)"
hexmask.long 0x60 0.--31. 1. "addrlo,MAC Address11 [31:0]"
line.long 0x64 "gmacgrp_mac_address12_high,Register 40 (MAC Address12 High Register )"
bitfld.long 0x64 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x64 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x64 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x64 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x64 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x64 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x64 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x64 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x64 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x64 0.--15. 1. "addrhi,MAC Address12 [47:32]"
line.long 0x68 "gmacgrp_mac_address12_low,Register 41 (MAC Address12 Low Register)"
hexmask.long 0x68 0.--31. 1. "addrlo,MAC Address12 [31:0]"
line.long 0x6C "gmacgrp_mac_address13_high,Register 42 (MAC Address13 High Register)"
bitfld.long 0x6C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x6C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x6C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x6C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x6C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x6C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x6C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x6C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x6C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x6C 0.--15. 1. "addrhi,MAC Address13 [47:32]"
line.long 0x70 "gmacgrp_mac_address13_low,Register 43 (MAC Address13 Low Register)"
hexmask.long 0x70 0.--31. 1. "addrlo,MAC Address13 [31:0]"
line.long 0x74 "gmacgrp_mac_address14_high,Register 44 (MAC Address14 High Register)"
bitfld.long 0x74 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x74 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x74 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x74 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x74 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x74 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x74 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x74 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x74 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x74 0.--15. 1. "addrhi,MAC Address14 [47:32]"
line.long 0x78 "gmacgrp_mac_address14_low,Register 45 (MAC Address14 Low Register)"
hexmask.long 0x78 0.--31. 1. "addrlo,MAC Address14 [31:0]"
line.long 0x7C "gmacgrp_mac_address15_high,Register 46 (MAC Address15 High Register)"
bitfld.long 0x7C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x7C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x7C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x7C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x7C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x7C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x7C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x7C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x7C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x7C 0.--15. 1. "addrhi,MAC Address15 [47:32] This field contains the upper 16 bits (47:32) of the 16th 6-byte MAC address."
line.long 0x80 "gmacgrp_mac_address15_low,Register 47 (MAC Address15 Low Register)"
hexmask.long 0x80 0.--31. 1. "addrlo,MAC Address15 [31:0]"
rgroup.long 0xD8++0x3
line.long 0x0 "gmacgrp_sgmii_rgmii_smii_control_status,The SGMII/RGMII/SMII Status register indicates the status signals received by the RGMII interface (selected at reset) from the PHY."
bitfld.long 0x0 3. "lnksts,This bit indicates whether the link is up (1'b1) or down (1'b0)." "0,1"
newline
bitfld.long 0x0 1.--2. "lnkspeed,This bit indicates the current speed of the link. Bit 2 is reserved when the MAC is configured for the SMII PHY interface." "0,1,2,3"
newline
bitfld.long 0x0 0. "lnkmod,This bit indicates the current mode of operation of the link" "0,1"
group.long 0xDC++0x7
line.long 0x0 "gmacgrp_wdog_timeout,Register 55 (Watchdog Timeout Register)"
hexmask.long.word 0x0 17.--31. 1. "reserved_31_17,Reserved"
newline
bitfld.long 0x0 16. "pwe,Programmable Watchdog Enable" "0,1"
newline
rbitfld.long 0x0 14.--15. "reserved_15_14,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "wto,Watchdog Timeout"
line.long 0x4 "gmacgrp_genpio,Register 56 (General Purpose IO Register)"
hexmask.long.byte 0x4 25.--31. 1. "reserved_31_x,Reserved"
newline
bitfld.long 0x4 24. "gpit,GPI Type" "0,1"
newline
hexmask.long.byte 0x4 17.--23. 1. "reserved_23_x,Reserved"
newline
bitfld.long 0x4 16. "gpie,GPI Interrupt Enable" "0,1"
newline
hexmask.long.byte 0x4 9.--15. 1. "reserved_15_x,Reserved"
newline
bitfld.long 0x4 8. "gpo,General Purpose Output" "0,1"
newline
hexmask.long.byte 0x4 1.--7. 1. "reserved_7_x,Reserved"
newline
rbitfld.long 0x4 0. "gpis,General Purpose Input Status" "0,1"
group.long 0x100++0x3
line.long 0x0 "gmacgrp_mmc_control,Register 64 (MMC Control Register)"
hexmask.long.tbyte 0x0 9.--31. 1. "reserved_31_9,Reserved"
newline
bitfld.long 0x0 8. "ucdbc,Update MMC Counters for Dropped Broadcast Frames" "0,1"
newline
rbitfld.long 0x0 6.--7. "reserved_7_6,Reserved" "0,1,2,3"
newline
bitfld.long 0x0 5. "cntprstlvl,Full-Half Preset" "0,1"
newline
bitfld.long 0x0 4. "cntprst,Counters Preset" "0,1"
newline
bitfld.long 0x0 3. "cntfreez,MMC Counter Freeze" "0,1"
newline
bitfld.long 0x0 2. "rstonrd,Reset on Read" "0,1"
newline
bitfld.long 0x0 1. "cntstopro,Counters Stop Rollover" "0,1"
newline
bitfld.long 0x0 0. "cntrst,Counters Reset" "0,1"
rgroup.long 0x104++0x7
line.long 0x0 "gmacgrp_mmc_receive_interrupt,Register 65 (MMC Receive Interrupt Register)"
hexmask.long.byte 0x0 26.--31. 1. "reserved_31_26,Reserved"
newline
bitfld.long 0x0 25. "rxctrlfis,MMC Receive Control Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 24. "rxrcverrfis,MMC Receive Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 23. "rxwdogfis,MMC Receive Watchdog Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 22. "rxvlangbfis,MMC Receive VLAN Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 21. "rxfovfis,MMC Receive FIFO Overflow Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 20. "rxpausfis,MMC Receive Pause Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 19. "rxorangefis,MMC Receive Out Of Range Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 18. "rxlenerfis,MMC Receive Length Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 17. "rxucgfis,MMC Receive Unicast Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 16. "rx1024tmaxoctgbfis,MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 15. "rx512t1023octgbfis,MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 14. "rx256t511octgbfis,MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 13. "rx128t255octgbfis,MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 12. "rx65t127octgbfis,MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 11. "rx64octgbfis,MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 10. "rxosizegfis,MMC Receive Oversize Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 9. "rxusizegfis,MMC Receive Undersize Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 8. "rxjaberfis,MMC Receive Jabber Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 7. "rxruntfis,MMC Receive Runt Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 6. "rxalgnerfis,MMC Receive Alignment Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 5. "rxcrcerfis,MMC Receive CRC Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 4. "rxmcgfis,MMC Receive Multicast Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 3. "rxbcgfis,MMC Receive Broadcast Good Frame Counter Interrupt Status." "0,1"
newline
bitfld.long 0x0 2. "rxgoctis,MMC Receive Good Octet Counter Interrupt Status." "0,1"
newline
bitfld.long 0x0 1. "rxgboctis,MMC Receive Good Bad Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "rxgbfrmis,MMC Receive Good Bad Frame Counter Interrupt Status" "0,1"
line.long 0x4 "gmacgrp_mmc_transmit_interrupt,Register 66 (MMC Transmit Interrupt Register)"
hexmask.long.byte 0x4 26.--31. 1. "reserved_31_26,Reserved"
newline
bitfld.long 0x4 25. "txosizegfis,MMC Transmit Oversize Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 24. "txvlangfis,MMC Transmit VLAN Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 23. "txpausfis,MMC Transmit Pause Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 22. "txexdeffis,MMC Transmit Excessive Deferral Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 21. "txgfrmis,MMC Transmit Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 20. "txgoctis,MMC Transmit Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 19. "txcarerfis,MMC Transmit Carrier Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 18. "txexcolfis,MMC Transmit Excessive Collision Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 17. "txlatcolfis,MMC Transmit Late Collision Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 16. "txdeffis,MMC Transmit Deferred Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 15. "txmcolgfis,MMC Transmit Multiple Collision Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 14. "txscolgfis,MMC Transmit Single Collision Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 13. "txuflowerfis,MMC Transmit Underflow Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 12. "txbcgbfis,MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 11. "txmcgbfis,MMC Transmit Multicast Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 10. "txucgbfis,MMC Transmit Unicast Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 9. "tx1024tmaxoctgbfis,MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 8. "tx512t1023octgbfis,MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 7. "tx256t511octgbfis,MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 6. "tx128t255octgbfis,MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 5. "tx65t127octgbfis,MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 4. "tx64octgbfis,MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status." "0,1"
newline
bitfld.long 0x4 3. "txmcgfis,MMC Transmit Multicast Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 2. "txbcgfis,MMC Transmit Broadcast Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 1. "txgbfrmis,MMC Transmit Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 0. "txgboctis,MMC Transmit Good Bad Octet Counter Interrupt Status" "0,1"
group.long 0x10C++0x7
line.long 0x0 "gmacgrp_mmc_receive_interrupt_mask,Regsiter 67 (MMC Receive Interrupt Mask Register)"
hexmask.long.byte 0x0 26.--31. 1. "reserved_31_26,Reserved"
newline
bitfld.long 0x0 25. "rxctrlfim,MMC Receive Control Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 24. "rxrcverrfim,MMC Receive Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 23. "rxwdogfim,MMC Receive Watchdog Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 22. "rxvlangbfim,MMC Receive VLAN Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 21. "rxfovfim,MMC Receive FIFO Overflow Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 20. "rxpausfim,MMC Receive Pause Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 19. "rxorangefim,MMC Receive Out Of Range Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 18. "rxlenerfim,MMC Receive Length Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 17. "rxucgfim,MMC Receive Unicast Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 16. "rx1024tmaxoctgbfim,MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 15. "rx512t1023octgbfim,MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 14. "rx256t511octgbfim,MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 13. "rx128t255octgbfim,MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 12. "rx65t127octgbfim,MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 11. "rx64octgbfim,MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 10. "rxosizegfim,MMC Receive Oversize Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 9. "rxusizegfim,MMC Receive Undersize Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 8. "rxjaberfim,MMC Receive Jabber Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 7. "rxruntfim,MMC Receive Runt Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 6. "rxalgnerfim,MMC Receive Alignment Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 5. "rxcrcerfim,MMC Receive CRC Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 4. "rxmcgfim,MMC Receive Multicast Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 3. "rxbcgfim,MMC Receive Broadcast Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "rxgoctim,MMC Receive Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "rxgboctim,MMC Receive Good Bad Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "rxgbfrmim,MMC Receive Good Bad Frame Counter Interrupt Mask" "0,1"
line.long 0x4 "gmacgrp_mmc_transmit_interrupt_mask,Register 68 (MMC Transmit Interrupt Mask Register)"
hexmask.long.byte 0x4 26.--31. 1. "reserved_31_26,Reserved"
newline
bitfld.long 0x4 25. "txosizegfim,MMC Transmit Oversize Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 24. "txvlangfim,MMC Transmit VLAN Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 23. "txpausfim,MMC Transmit Pause Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 22. "txexdeffim,MMC Transmit Excessive Deferral Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 21. "txgfrmim,MMC Transmit Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 20. "txgoctim,MMC Transmit Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 19. "txcarerfim,MMC Transmit Carrier Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 18. "txexcolfim,MMC Transmit Excessive Collision Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 17. "txlatcolfim,MMC Transmit Late Collision Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 16. "txdeffim,MMC Transmit Deferred Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 15. "txmcolgfim,MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 14. "txscolgfim,MMC Transmit Single Collision Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 13. "txuflowerfim,MMC Transmit Underflow Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 12. "txbcgbfim,MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 11. "txmcgbfim,MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 10. "txucgbfim,MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 9. "tx1024tmaxoctgbfim,MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 8. "tx512t1023octgbfim,MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 7. "tx256t511octgbfim,MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 6. "tx128t255octgbfim,MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 5. "tx65t127octgbfim,MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 4. "tx64octgbfim,MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 3. "txmcgfim,MMC Transmit Multicast Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 2. "txbcgfim,MMC Transmit Broadcast Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 1. "txgbfrmim,MMC Transmit Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 0. "txgboctim,MMC Transmit Good Bad Octet Counter Interrupt Mask" "0,1"
rgroup.long 0x114++0x67
line.long 0x0 "gmacgrp_txoctetcount_gb,Register 69 (Transmit Octet Count for Good and Bad Frames)"
hexmask.long 0x0 0.--31. 1. "cnt,This field indicates the number of bytes transmitted in good and bad frames exclusive of preamble and retried bytes."
line.long 0x4 "gmacgrp_txframecount_gb,Register 70 (Transmit Frame Count for Good and Bad Frames)"
hexmask.long 0x4 0.--31. 1. "cnt,This field indicates the number of good and bad frames transmitted  exclusive of retried frames"
line.long 0x8 "gmacgrp_txbroadcastframes_g,Register 71 (Transmit Frame Count for Good Broadcast Frames)"
hexmask.long 0x8 0.--31. 1. "cnt,This field indicates the number of transmitted good broadcast frames."
line.long 0xC "gmacgrp_txmulticastframes_g,Register 72 (Transmit Frame Count for Good Multicast Frames)"
hexmask.long 0xC 0.--31. 1. "cnt,This field indicates the number of transmitted good multicast frames."
line.long 0x10 "gmacgrp_tx64octets_gb,Register 73 (Transmit Octet Count for Good and Bad 64 Byte Frames)"
hexmask.long 0x10 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad frames with length of 64 bytes  exclusive of preamble and retried frames."
line.long 0x14 "gmacgrp_tx65to127octets_gb,Register 74 (Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames)"
hexmask.long 0x14 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad frames with length between 65 and 127 (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x18 "gmacgrp_tx128to255octets_gb,Register 75 (Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames)"
hexmask.long 0x18 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad frames with length between 128 and 255 (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x1C "gmacgrp_tx256to511octets_gb,Register 76 (Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames)"
hexmask.long 0x1C 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad frames with length between 256 and 511 (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x20 "gmacgrp_tx512to1023octets_gb,Register 77 (Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames)"
hexmask.long 0x20 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad frames with length between 512 and 1 023 (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x24 "gmacgrp_tx1024tomaxoctets_gb,Register 78 (Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames)"
hexmask.long 0x24 0.--31. 1. "cnt,This field indicates the number of good and bad frames transmitted with length between 1 024 and maxsize (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x28 "gmacgrp_txunicastframes_gb,Register 79 (Transmit Frame Count for Good and Bad Unicast Frames)"
hexmask.long 0x28 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad unicast frames."
line.long 0x2C "gmacgrp_txmulticastframes_gb,Register 80 (Transmit Frame Count for Good and Bad Multicast Frames)"
hexmask.long 0x2C 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad multicast frames."
line.long 0x30 "gmacgrp_txbroadcastframes_gb,Register 81 (Transmit Frame Count for Good and Bad Broadcast Frames)"
hexmask.long 0x30 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad broadcast frames."
line.long 0x34 "gmacgrp_txunderflowerror,Register 82 (Transmit Frame Count for Underflow Error Frames)"
hexmask.long 0x34 0.--31. 1. "cnt,This field indicates the number of frames aborted because of frame underflow error."
line.long 0x38 "gmacgrp_txsinglecol_g,Register 83 (Transmit Frame Count for Frames Transmitted after Single Collision)"
hexmask.long 0x38 0.--31. 1. "cnt,This field indicates the number of successfully transmitted frames after a single collision in the half-duplex mode."
line.long 0x3C "gmacgrp_txmulticol_g,Register 84 (Transmit Frame Count for Frames Transmitted after Multiple Collision)"
hexmask.long 0x3C 0.--31. 1. "cnt,This field indicates the number of successfully transmitted frames after multiple collisions in the half-duplex mode."
line.long 0x40 "gmacgrp_txdeferred,Register 85 (Transmit Frame Count for Deferred Frames)"
hexmask.long 0x40 0.--31. 1. "cnt,This field indicates the number of successfully transmitted frames after a deferral in the half-duplex mode."
line.long 0x44 "gmacgrp_txlatecol,Register 86 (Transmit Frame Count for Late Collision Error Frames)"
hexmask.long 0x44 0.--31. 1. "cnt,This field indicates the number of frames aborted because of late collision error."
line.long 0x48 "gmacgrp_txexesscol,Register 87 (Transmit Frame Count for Excessive Collision Error Frames)"
hexmask.long 0x48 0.--31. 1. "cnt,This field indicates the number of frames aborted because of excessive (16) collision error."
line.long 0x4C "gmacgrp_txcarriererr,Register 88 (Transmit Frame Count for Carrier Sense Error Frames)"
hexmask.long 0x4C 0.--31. 1. "cnt,This field indicates the number of frames aborted because of carrier sense error (no carrier or loss of carrier)."
line.long 0x50 "gmacgrp_txoctetcnt,Register 89 (Transmit Octet Count for Good Frames)"
hexmask.long 0x50 0.--31. 1. "txoctetcount_g,This field indicates the number of bytes transmitted  exclusive of preamble  in good frames."
line.long 0x54 "gmacgrp_txframecount_g,Register 90 (Transmit Frame Count for Good Frames)"
hexmask.long 0x54 0.--31. 1. "cnt,This field indicates the number of transmitted good frames  exclusive of preamble."
line.long 0x58 "gmacgrp_txexcessdef,Register 91 (Transmit Frame Count for Excessive Deferral Error Frames)"
hexmask.long 0x58 0.--31. 1. "cnt,This field indicates the number of frames aborted because of excessive deferral error  that is  frames deferred for more than two max-sized frame times."
line.long 0x5C "gmacgrp_txpauseframes,Register 92 (Transmit Frame Count for Good PAUSE Frames)"
hexmask.long 0x5C 0.--31. 1. "cnt,This field indicates the number of transmitted good PAUSE frames."
line.long 0x60 "gmacgrp_txvlanframes_g,Register 93 (Transmit Frame Count for Good VLAN Frames)"
hexmask.long 0x60 0.--31. 1. "cnt,This register maintains the number of transmitted good VLAN frames  exclusive of retried frames."
line.long 0x64 "gmacgrp_txoversize_g,Register 94 (Transmit Frame Count for Good Oversize Frames)"
hexmask.long 0x64 0.--31. 1. "cnt,This field indicates the number of frames transmitted without errors and with length greater than the maxsize (1 518 or 1 522 bytes for VLAN tagged frames; 2000 bytes if enabled in bit 27 of Register 0 (MAC Configuration Register))."
rgroup.long 0x180++0x67
line.long 0x0 "gmacgrp_rxframecount_gb,Register 96 (Receive Frame Count for Good and Bad Frames)"
hexmask.long 0x0 0.--31. 1. "cnt,This field indicates the number of received good and bad frames."
line.long 0x4 "gmacgrp_rxoctetcount_gb,Register 97 (Receive Octet Count for Good and Bad Frames)"
hexmask.long 0x4 0.--31. 1. "cnt,This field indicates the number of bytes received  exclusive of preamble  in good and bad frames."
line.long 0x8 "gmacgrp_rxoctetcount_g,Register 98 (Receive Octet Count for Good Frames)"
hexmask.long 0x8 0.--31. 1. "cnt,This field indicates the number of bytes received  exclusive of preamble  only in good frames."
line.long 0xC "gmacgrp_rxbroadcastframes_g,Register 99 (Receive Frame Count for Good Broadcast Frames)"
hexmask.long 0xC 0.--31. 1. "cnt,This field indicates the number of received good broadcast frames."
line.long 0x10 "gmacgrp_rxmulticastframes_g,Register 100 (Receive Frame Count for Good Multicast Frames)"
hexmask.long 0x10 0.--31. 1. "cnt,This field indicates the number of received good multicast frames."
line.long 0x14 "gmacgrp_rxcrcerror,Register 101 (Receive Frame Count for CRC Error Frames)"
hexmask.long 0x14 0.--31. 1. "cnt,This field indicates the number of frames received with CRC error."
line.long 0x18 "gmacgrp_rxalignmenterror,Register 102 (Receive Frame Count for Alignment Error Frames)"
hexmask.long 0x18 0.--31. 1. "cnt,This field indicates the number of frames received with alignment (dribble) error. This field is valid only in the 10 or 100 Mbps mode."
line.long 0x1C "gmacgrp_rxrunterror,Register 103 (Receive Frame Count for Runt Error Frames)"
hexmask.long 0x1C 0.--31. 1. "cnt,This field indicates the number of frames received with runt error(< bytes and CRC error)."
line.long 0x20 "gmacgrp_rxjabbererror,Register 104 (Receive Frame Count for Jabber Error Frames)"
hexmask.long 0x20 0.--31. 1. "cnt,This field indicates the number of giant frames received with length (including CRC) greater than 1 518 bytes (1 522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled  then frames of length greater than 9 018 bytes (9 022 for.."
line.long 0x24 "gmacgrp_rxundersize_g,Register 105 (Receive Frame Count for Undersize Frames)"
hexmask.long 0x24 0.--31. 1. "cnt,This field indicates the number of frames received with length less than 64 bytes and without errors."
line.long 0x28 "gmacgrp_rxoversize_g,Register 106 (Receive Frame Count for Oversize Frames)"
hexmask.long 0x28 0.--31. 1. "cnt,This field indicates the number of frames received without errors  with length greater than the maxsize (1 518 or 1 522 for VLAN tagged frames; 2 000 bytes if enabled in bit 27 of Register 0 (MAC Configuration Register))."
line.long 0x2C "gmacgrp_rx64octets_gb,Register 107 (Receive Frame Count for Good and Bad 64 Byte Frames)"
hexmask.long 0x2C 0.--31. 1. "cnt,This field indicates the number of received good and bad frames with length 64 bytes  exclusive of preamble."
line.long 0x30 "gmacgrp_rx65to127octets_gb,Register 108 (Receive Frame Count for Good and Bad 65 to 127 Bytes Frames)"
hexmask.long 0x30 0.--31. 1. "cnt,This field indicates the number of received good and bad frames received with length between 65 and 127 (inclusive) bytes  exclusive of preamble."
line.long 0x34 "gmacgrp_rx128to255octets_gb,Register 109 (Receive Frame Count for Good and Bad 128 to 255 Bytes Frames)"
hexmask.long 0x34 0.--31. 1. "cnt,This field indicates the number of received good and bad frames with length between 128 and 255 (inclusive) bytes  exclusive of preamble."
line.long 0x38 "gmacgrp_rx256to511octets_gb,Register 110 (Receive Frame Count for Good and Bad 256 to 511 Bytes Frames)"
hexmask.long 0x38 0.--31. 1. "cnt,This field indicates the number of received good and bad frames with length between 256 and 511 (inclusive) bytes  exclusive of preamble."
line.long 0x3C "gmacgrp_rx512to1023octets_gb,Register 111 (Receive Frame Count for Good and Bad 512 to 1.023 Bytes Frames)"
hexmask.long 0x3C 0.--31. 1. "cnt,This field indicates the number of received good and bad frames with length between 512 and 1 023 (inclusive) bytes  exclusive of preamble."
line.long 0x40 "gmacgrp_rx1024tomaxoctets_gb,Register 112 (Receive Frame Count for Good and Bad 1.024 to Maxsize Bytes Frames)"
hexmask.long 0x40 0.--31. 1. "cnt,This field indicates the number of received good and bad frames with length between 1 024 and maxsize (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x44 "gmacgrp_rxunicastframes_g,Register 113 (Receive Frame Count for Good Unicast Frames)"
hexmask.long 0x44 0.--31. 1. "cnt,This field indicates the number of received good unicast frames."
line.long 0x48 "gmacgrp_rxlengtherror,Register 114 (Receive Frame Count for Length Error Frames)"
hexmask.long 0x48 0.--31. 1. "cnt,This field indicates the number of frames received with length error (Length type field not equal to frame size) for all frames with valid length field."
line.long 0x4C "gmacgrp_rxoutofrangetype,Register 115 (Receive Frame Count for Out of Range Frames)"
hexmask.long 0x4C 0.--31. 1. "cnt,This field indicates the number of received frames with length field not equal to the valid frame size (greater than 1 500 but less than 1 536)."
line.long 0x50 "gmacgrp_rxpauseframes,Register 116 (Receive Frame Count for PAUSE Frames)"
hexmask.long 0x50 0.--31. 1. "cnt,This field indicates the number of received good and valid PAUSE frames."
line.long 0x54 "gmacgrp_rxfifooverflow,Register 117 (Receive Frame Count for FIFO Overflow Frames)"
hexmask.long 0x54 0.--31. 1. "cnt,This field indicates the number of received frames missed because of FIFO overflow."
line.long 0x58 "gmacgrp_rxvlanframes_gb,Register 118 (Receive Frame Count for Good and Bad VLAN Frames)"
hexmask.long 0x58 0.--31. 1. "cnt,This field indicates the number of received good and bad VLAN frames."
line.long 0x5C "gmacgrp_rxwatchdogerror,Register 119 (Receive Frame Count for Watchdog Error Frames)"
hexmask.long 0x5C 0.--31. 1. "cnt,This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2 048 bytes or value programmed in Register 55 (Watchdog Timeout Register))."
line.long 0x60 "gmacgrp_rxrcverror,Register 120 (Receive Frame Count for Receive Error Frames)"
hexmask.long 0x60 0.--31. 1. "cnt,This field indicates the number of frames received with error because of the GMII/MII RXER error or Frame Extension error on GMII."
line.long 0x64 "gmacgrp_rxctrlframes_g,Register 121 (Receive Frame Count for Good Control Frames Frames)"
hexmask.long 0x64 0.--31. 1. "cnt,This field indicates the number of good control frames received."
group.long 0x200++0x3
line.long 0x0 "gmacgrp_mmc_ipc_receive_interrupt_mask,This register maintains the mask for the interrupt generated from the receive IPC statistic"
bitfld.long 0x0 29. "rxicmperoim,Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 28. "rxicmpgoim,Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 27. "rxtcperoim,Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 26. "rxtcpgoim,Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 25. "rxudperoim,Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 24. "rxudpgoim,Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 23. "rxipv6nopayoim,Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 22. "rxipv6heroim,Setting this bit masks interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 21. "rxipv6goim,Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 20. "rxipv4udsbloim,Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 19. "rxipv4fragoim,Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 18. "rxipv4nopayoim,Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 17. "rxipv4heroim,Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 16. "rxipv4goim,Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 13. "rxicmperfim,Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 12. "rxicmpgfim,Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 11. "rxtcperfim,Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 10. "rxtcpgfim,Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 9. "rxudperfim,Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 8. "rxudpgfim,Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 7. "rxipv6nopayfim,Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 6. "rxipv6herfim,Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 5. "rxipv6gfim,Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 4. "rxipv4udsblfim,Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 3. "rxipv4fragfim,Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 2. "rxipv4nopayfim,Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 1. "rxipv4herfim,Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 0. "rxipv4gfim,Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
rgroup.long 0x208++0x3
line.long 0x0 "gmacgrp_mmc_ipc_receive_interrupt,This register maintains the interrupts generated when receive IPC statistic counters reach half their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter). and when they cross their maximum.."
bitfld.long 0x0 29. "rxicmperois,This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 28. "rxicmpgois,This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 27. "rxtcperois,This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 26. "rxtcpgois,This bit is set when the rxtcp_gd_octets counter reaches half the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 25. "rxudperois,This bit is set when the rxudp_err_octets counter reaches half the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 24. "rxudpgois,This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 23. "rxipv6nopayois,This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 22. "rxipv6herois,This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 21. "rxipv6gois,This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 20. "rxipv4udsblois,This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 19. "rxipv4fragois,This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 18. "rxipv4nopayois,This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 17. "rxipv4herois,This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 16. "rxipv4gois,This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 13. "rxicmperfis,This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 12. "rxicmpgfis,This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 11. "rxtcperfis,This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 10. "rxtcpgfis,This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 9. "rxudperfis,This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 8. "rxudpgfis,This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 7. "rxipv6nopayfis,This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 6. "rxipv6herfis,This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 5. "rxipv6gfis,This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 4. "rxipv4udsblfis,This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 3. "rxipv4fragfis,This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 2. "rxipv4nopayfis,This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 1. "rxipv4herfis,This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 0. "rxipv4gfis,This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
rgroup.long 0x210++0x37
line.long 0x0 "gmacgrp_rxipv4_gd_frms,Number of good IPv4 datagrams received with the TCP. UDP. or ICMP payload"
hexmask.long 0x0 0.--31. 1. "cnt,Number of good IPv4 datagrams received with the TCP  UDP  or ICMP payload"
line.long 0x4 "gmacgrp_rxipv4_hdrerr_frms,Number of IPv4 datagrams received with header (checksum. length. or version mismatch) errors"
hexmask.long 0x4 0.--31. 1. "cnt,Number of IPv4 datagrams received with header (checksum  length  or version mismatch) errors"
line.long 0x8 "gmacgrp_rxipv4_nopay_frms,Number of IPv4 datagram frames received that did not have a TCP. UDP. or ICMP payload processed by the Checksum engine"
hexmask.long 0x8 0.--31. 1. "cnt,Number of IPv4 datagram frames received that did not have a TCP  UDP  or ICMP payload processed by the Checksum engine"
line.long 0xC "gmacgrp_rxipv4_frag_frms,Number of good IPv4 datagrams with fragmentation"
hexmask.long 0xC 0.--31. 1. "cnt,Number of good IPv4 datagrams with fragmentation"
line.long 0x10 "gmacgrp_rxipv4_udsbl_frms,Number of good IPv4 datagrams received that had a UDP payload with checksum disabled"
hexmask.long 0x10 0.--31. 1. "cnt,Number of good IPv4 datagrams received that had a UDP payload with checksum disabled"
line.long 0x14 "gmacgrp_rxipv6_gd_frms,Number of good IPv6 datagrams received with TCP. UDP. or ICMP payloads"
hexmask.long 0x14 0.--31. 1. "cnt,Number of good IPv6 datagrams received with TCP  UDP  or ICMP payloads"
line.long 0x18 "gmacgrp_rxipv6_hdrerr_frms,Number of IPv6 datagrams received with header errors (length or version mismatch)"
hexmask.long 0x18 0.--31. 1. "cnt,Number of IPv6 datagrams received with header errors (length or version mismatch)"
line.long 0x1C "gmacgrp_rxipv6_nopay_frms,Number of IPv6 datagram frames received that did not have a TCP. UDP. or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers"
hexmask.long 0x1C 0.--31. 1. "cnt,Number of IPv6 datagram frames received that did not have a TCP  UDP  or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers"
line.long 0x20 "gmacgrp_rxudp_gd_frms,Number of good IP datagrams with a good UDP payload. This counter is not updated when the counter is incremented"
hexmask.long 0x20 0.--31. 1. "cnt,Number of good IP datagrams with a good UDP payload. This counter is not updated when the counter is incremented"
line.long 0x24 "gmacgrp_rxudp_err_frms,Number of good IP datagrams whose UDP payload has a checksum error"
hexmask.long 0x24 0.--31. 1. "cnt,Number of good IP datagrams whose UDP payload has a checksum error"
line.long 0x28 "gmacgrp_rxtcp_gd_frms,Number of good IP datagrams with a good TCP payload"
hexmask.long 0x28 0.--31. 1. "cnt,Number of good IP datagrams with a good TCP payload"
line.long 0x2C "gmacgrp_rxtcp_err_frms,Number of good IP datagrams whose TCP payload has a checksum error"
hexmask.long 0x2C 0.--31. 1. "cnt,Number of good IP datagrams whose TCP payload has a checksum error"
line.long 0x30 "gmacgrp_rxicmp_gd_frms,Number of good IP datagrams with a good ICMP payload"
hexmask.long 0x30 0.--31. 1. "cnt,Number of good IP datagrams with a good ICMP payload"
line.long 0x34 "gmacgrp_rxicmp_err_frms,Number of good IP datagrams whose ICMP payload has a checksum error"
hexmask.long 0x34 0.--31. 1. "cnt,Number of good IP datagrams whose ICMP payload has a checksum error"
rgroup.long 0x250++0x37
line.long 0x0 "gmacgrp_rxipv4_gd_octets,Number of bytes received in good IPv4 datagrams encapsulating TCP. UDP. or ICMP data"
hexmask.long 0x0 0.--31. 1. "cnt,Number of bytes received in good IPv4 datagrams encapsulating TCP  UDP  or ICMP data"
line.long 0x4 "gmacgrp_rxipv4_hdrerr_octets,Number of bytes received in IPv4 datagrams with header errors (checksum. length. version mismatch). The value in the Length field of IPv4 header is used to update this counter"
hexmask.long 0x4 0.--31. 1. "cnt,Number of bytes received in IPv4 datagrams with header errors (checksum  length  version mismatch). The value in the Length field of IPv4 header is used to update this counter"
line.long 0x8 "gmacgrp_rxipv4_nopay_octets,Number of bytes received in IPv4 datagrams that did not have a TCP. UDP. or ICMP payload. The value in the IPv4 headers Length field is used to update this counter"
hexmask.long 0x8 0.--31. 1. "cnt,Number of bytes received in IPv4 datagrams that did not have a TCP  UDP  or ICMP payload. The value in the IPv4 headers Length field is used to update this counter"
line.long 0xC "gmacgrp_rxipv4_frag_octets,Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 headers Length field is used to update this counter"
hexmask.long 0xC 0.--31. 1. "cnt,Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 headers Length field is used to update this counter"
line.long 0x10 "gmacgrp_rxipv4_udsbl_octets,Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes"
hexmask.long 0x10 0.--31. 1. "cnt,Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes"
line.long 0x14 "gmacgrp_rxipv6_gd_octets,Number of bytes received in good IPv6 datagrams encapsulating TCP. UDP or ICMPv6 data"
hexmask.long 0x14 0.--31. 1. "cnt,Number of bytes received in good IPv6 datagrams encapsulating TCP  UDP or ICMPv6 data"
line.long 0x18 "gmacgrp_rxipv6_hdrerr_octets,Number of bytes received in IPv6 datagrams with header errors (length. version mismatch). The value in the IPv6 headers Length field is used to update this counter"
hexmask.long 0x18 0.--31. 1. "cnt,Number of bytes received in IPv6 datagrams with header errors (length  version mismatch). The value in the IPv6 headers Length field is used to update this counter"
line.long 0x1C "gmacgrp_rxipv6_nopay_octets,Number of bytes received in IPv6 datagrams that did not have a TCP. UDP. or ICMP payload. The value in the IPv6 headers Length field is used to update this counter"
hexmask.long 0x1C 0.--31. 1. "cnt,Number of bytes received in IPv6 datagrams that did not have a TCP  UDP  or ICMP payload. The value in the IPv6 headers Length field is used to update this counter"
line.long 0x20 "gmacgrp_rxudp_gd_octets,Number of bytes received in a good UDP segment. This counter does not count IP header bytes"
hexmask.long 0x20 0.--31. 1. "cnt,Number of bytes received in a good UDP segment. This counter does not count IP header bytes"
line.long 0x24 "gmacgrp_rxudp_err_octets,Number of bytes received in a UDP segment that had checksum errors"
hexmask.long 0x24 0.--31. 1. "cnt,Number of bytes received in a UDP segment that had checksum errors"
line.long 0x28 "gmacgrp_rxtcp_gd_octets,Number of bytes received in a good TCP segment"
hexmask.long 0x28 0.--31. 1. "cnt,Number of bytes received in a good TCP segment"
line.long 0x2C "gmacgrp_rxtcperroctets,Number of bytes received in a TCP segment with checksum errors"
hexmask.long 0x2C 0.--31. 1. "rxtcp_err_octets,Number of bytes received in a TCP segment with checksum errors"
line.long 0x30 "gmacgrp_rxicmp_gd_octets,Number of bytes received in a good ICMP segment"
hexmask.long 0x30 0.--31. 1. "cnt,Number of bytes received in a good ICMP segment"
line.long 0x34 "gmacgrp_rxicmp_err_octets,Number of bytes received in an ICMP segment with checksum errors"
hexmask.long 0x34 0.--31. 1. "cnt,Number of bytes received in an ICMP segment with checksum errors"
group.long 0x400++0x7
line.long 0x0 "gmacgrp_l3_l4_control0,Register 256 (Layer 3 and Layer 4 Control Register 0)"
hexmask.long.word 0x0 22.--31. 1. "reserved_31_22,Reserved"
newline
bitfld.long 0x0 21. "l4dpim0,Layer 4 Destination Port Inverse Match Enable" "0,1"
newline
bitfld.long 0x0 20. "l4dpm0,Layer 4 Destination Port Match Enable" "0,1"
newline
bitfld.long 0x0 19. "l4spim0,Layer 4 Source Port Inverse Match Enable" "0,1"
newline
bitfld.long 0x0 18. "l4spm0,Layer 4 Source Port Match Enable" "0,1"
newline
rbitfld.long 0x0 17. "reserved_17,Reserved" "0,1"
newline
bitfld.long 0x0 16. "l4pen0,Layer 4 Protocol Enable" "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "l3hdbm0,Layer 3 IP DA Higher Bits Match"
newline
hexmask.long.byte 0x0 6.--10. 1. "l3hsbm0,Layer 3 IP SA Higher Bits Match"
newline
bitfld.long 0x0 5. "l3daim0,Layer 3 IP DA Inverse Match Enable" "0,1"
newline
bitfld.long 0x0 4. "l3dam0,Layer 3 IP DA Match Enable" "0,1"
newline
bitfld.long 0x0 3. "l3saim0,Layer 3 IP SA Inverse Match Enable" "0,1"
newline
bitfld.long 0x0 2. "l3sam0,Layer 3 IP SA Match Enable" "0,1"
newline
rbitfld.long 0x0 1. "reserved_1,Reserved" "0,1"
newline
bitfld.long 0x0 0. "l3pen0,Layer 3 Protocol Enable" "0,1"
line.long 0x4 "gmacgrp_layer4_address0,Register 257 (Layer 4 Address Register 0)"
hexmask.long.word 0x4 16.--31. 1. "l4dp0,Layer 4 Destination Port Number Field"
newline
hexmask.long.word 0x4 0.--15. 1. "l4sp0,Layer 4 Source Port Number Field"
group.long 0x410++0xF
line.long 0x0 "gmacgrp_layer3_addr0_reg0,Register 260 (Layer 3 Address 0 Register 0)"
hexmask.long 0x0 0.--31. 1. "l3a00,Layer 3 Address 0 Field"
line.long 0x4 "gmacgrp_layer3_addr1_reg0,Register 261 (Layer 3 Address 1 Register 0)"
hexmask.long 0x4 0.--31. 1. "l3a10,Layer 3 Address 1 Field"
line.long 0x8 "gmacgrp_layer3_addr2_reg0,Register 262 (Layer 3 Address 2 Register 0)"
hexmask.long 0x8 0.--31. 1. "l3a20,Layer 3 Address 2 Field"
line.long 0xC "gmacgrp_layer3_addr3_reg0,Register 263 (Layer 3 Address 3 Register 0)"
hexmask.long 0xC 0.--31. 1. "l3a30,Layer 3 Address 3 Field"
group.long 0x430++0x7
line.long 0x0 "gmacgrp_l3_l4_control1,This register controls the operations of the filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 21. "l4dpim1,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching." "0,1"
newline
bitfld.long 0x0 20. "l4dpm1,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for matching." "0,1"
newline
bitfld.long 0x0 19. "l4spim1,When set  this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching." "0,1"
newline
bitfld.long 0x0 18. "l4spm1,When set  this bit indicates that the Layer 4 Source Port number field is enabled for matching." "0,1"
newline
bitfld.long 0x0 16. "l4pen1,When set  this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset  this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "l3hdbm1,IPv4 Frames:"
newline
hexmask.long.byte 0x0 6.--10. 1. "l3hsbm1,IPv4 Frames:"
newline
bitfld.long 0x0 5. "l3daim1,When set  this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching." "0,1"
newline
bitfld.long 0x0 4. "l3dam1,When set  this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Destination Address field for matching." "0,1"
newline
bitfld.long 0x0 3. "l3saim1,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching." "0,1"
newline
bitfld.long 0x0 2. "l3sam1,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Source Address field for matching." "0,1"
newline
bitfld.long 0x0 0. "l3pen1,When set  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames." "0,1"
line.long 0x4 "gmacgrp_layer4_address1,Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains. then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer.."
hexmask.long.word 0x4 16.--31. 1. "l4dp1,When Bit 16 (L4PEN1) is reset and Bit 20 (L4DPM1) is set in Register 268 (Layer 3 and Layer 4 Control Register 0)  this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames."
newline
hexmask.long.word 0x4 0.--15. 1. "l4sp1,When Bit 16 (L4PEN1) is reset and Bit 20 (L4DPM1) is set in Register 268 (Layer 3 and Layer 4 Control Register 1)  this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames."
group.long 0x440++0xF
line.long 0x0 "gmacgrp_layer3_addr0_reg1,For IPv4 frames. the Layer 3 Address 0 Register 1 contains the 32-bit IP Source Address field. For IPv6 frames. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "l3a01,When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and Layer 4 Control Register 1)  this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 frames."
line.long 0x4 "gmacgrp_layer3_addr1_reg1,For IPv4 frames. the Layer 3 Address 1 Register 1 contains the 32-bit IP Destination Address field. For IPv6 frames. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field"
hexmask.long 0x4 0.--31. 1. "l3a11,When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and Layer 4 Control Register 1)  this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames."
line.long 0x8 "gmacgrp_layer3_addr2_reg1,For IPv4 frames. the Layer 3 Address 2 Register 1 is reserved. For IPv6 frames. it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x8 0.--31. 1. "l3a21,When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and Layer 4 Control Register 1)  this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames."
line.long 0xC "gmacgrp_layer3_addr3_reg1,For IPv4 frames. the Layer 3 Address 3 Register 1 is reserved. For IPv6 frames. it contains Bits [127:96] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0xC 0.--31. 1. "l3a31,When Bit 1 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and Layer 4 Control Register 1)  this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames."
group.long 0x460++0x7
line.long 0x0 "gmacgrp_l3_l4_control2,This register controls the operations of the filter 2 of Layer 3 and Layer 4."
bitfld.long 0x0 21. "l4dpim2,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset  this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching." "0,1"
newline
bitfld.long 0x0 20. "l4dpm2,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset  the MAC ignores the Layer 4 Destination Port number field for matching." "0,1"
newline
bitfld.long 0x0 19. "l4spim2,When set  this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset  this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching." "0,1"
newline
bitfld.long 0x0 18. "l4spm2,When set  this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset  the MAC ignores the Layer 4 Source Port number field for matching." "0,1"
newline
bitfld.long 0x0 16. "l4pen2,When set  this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset  this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "l3hdbm2,IPv4 Frames:"
newline
hexmask.long.byte 0x0 6.--10. 1. "l3hsbm2,Layer 3 IP SA Higher Bits Match"
newline
bitfld.long 0x0 5. "l3daim2,When set  this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching." "0,1"
newline
bitfld.long 0x0 4. "l3dam2,When set  this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Destination Address field for matching." "0,1"
newline
bitfld.long 0x0 3. "l3saim2,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching." "0,1"
newline
bitfld.long 0x0 2. "l3sam2,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Source Address field for matching." "0,1"
newline
bitfld.long 0x0 0. "l3pen2,When set  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames." "0,1"
line.long 0x4 "gmacgrp_layer4_address2,Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains. then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer.."
hexmask.long.word 0x4 16.--31. 1. "l4dp2,When Bit 16 (L4PEN2) is reset and Bit 20 (L4DPM2) is set in Register 280 (Layer 3 and Layer 4 Control Register 2)  this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames."
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hexmask.long.word 0x4 0.--15. 1. "l4sp2,When Bit 16 (L4PEN2) is reset and Bit 20 (L4DPM2) is set in Register 280 (Layer 3 and Layer 4 Control Register 2)  this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames."
group.long 0x470++0xF
line.long 0x0 "gmacgrp_layer3_addr0_reg2,For IPv4 frames. the Layer 3 Address 0 Register 2 contains the 32-bit IP Source Address field. For IPv6 frames. it contains Bits [31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "l3a02,When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and Layer 4 Control Register 2)  this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames."
line.long 0x4 "gmacgrp_layer3_addr1_reg2,For IPv4 frames. the Layer 3 Address 1 Register 2 contains the 32-bit IP Destination Address field. For IPv6 frames. it contains Bits [63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x4 0.--31. 1. "l3a12,Layer 3 Address 1 Field"
line.long 0x8 "gmacgrp_layer3_addr2_reg2,For IPv4 frames. the Layer 3 Address 2 Register 2 is reserved. For IPv6 frames. it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x8 0.--31. 1. "l3a22,When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and Layer 4 Control Register 2)  this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames."
line.long 0xC "gmacgrp_layer3_addr3_reg2,For IPv4 frames. the Layer 3 Address 3 Register 2 is reserved. For IPv6 frames. it contains Bits [127:96] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0xC 0.--31. 1. "l3a32,When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and Layer 4 Control Register 2)  this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames."
group.long 0x490++0x7
line.long 0x0 "gmacgrp_l3_l4_control3,This register controls the operations of the filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 21. "l4dpim3,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset  this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 20. "l4dpm3,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset  the MAC ignores the Layer 4 Destination Port number field for matching." "0,1"
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bitfld.long 0x0 19. "l4spim3,When set  this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset  this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 18. "l4spm3,When set  this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset  the MAC ignores the Layer 4 Source Port number field for matching." "0,1"
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bitfld.long 0x0 16. "l4pen3,When set  this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset  this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching." "0,1"
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hexmask.long.byte 0x0 11.--15. 1. "l3hdbm3,Layer 3 IP DA Higher Bits Match"
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hexmask.long.byte 0x0 6.--10. 1. "l3hsbm3,IPv4 Frames:"
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bitfld.long 0x0 5. "l3daim3,When set  this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 4. "l3dam3,When set  this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Destination Address field for matching." "0,1"
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bitfld.long 0x0 3. "l3saim3,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 2. "l3sam3,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Source Address field for matching." "0,1"
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bitfld.long 0x0 0. "l3pen3,When set  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames." "0,1"
line.long 0x4 "gmacgrp_layer4_address3,Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains. then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer.."
hexmask.long.word 0x4 16.--31. 1. "l4dp3,When Bit 16 (L4PEN3) is reset and Bit 20 (L4DPM3) is set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames."
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hexmask.long.word 0x4 0.--15. 1. "l4sp3,When Bit 16 (L4PEN3) is reset and Bit 20 (L4DPM3) is set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames."
group.long 0x4A0++0xF
line.long 0x0 "gmacgrp_layer3_addr0_reg3,For IPv4 frames. the Layer 3 Address 0 Register 3 contains the 32-bit IP Source Address field. For IPv6 frames. it contains Bits [31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "l3a03,When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames."
line.long 0x4 "gmacgrp_layer3_addr1_reg3,For IPv4 frames. the Layer 3 Address 1 Register 3 contains the 32-bit IP Destination Address field. For IPv6 frames. it contains Bits [63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x4 0.--31. 1. "l3a13,When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames."
line.long 0x8 "gmacgrp_layer3_addr2_reg3,For IPv4 frames. the Layer 3 Address 2 Register 3 is reserved. For IPv6 frames. it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x8 0.--31. 1. "l3a23,When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames."
line.long 0xC "gmacgrp_layer3_addr3_reg3,For IPv4 frames. the Layer 3 Address 3 Register 3 is reserved. For IPv6 frames. it contains Bits [127:96] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0xC 0.--31. 1. "l3a33,When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames."
group.long 0x500++0x1F
line.long 0x0 "gmacgrp_hash_table_reg0,This register contains the first 32 bits of the hash table."
hexmask.long 0x0 0.--31. 1. "ht31t0,This field contains the first 32 Bits (31:0) of the Hash table."
line.long 0x4 "gmacgrp_hash_table_reg1,This register contains the second 32 bits of the hash table."
hexmask.long 0x4 0.--31. 1. "ht63t32,This field contains the second 32 Bits (63:32) of the Hash table."
line.long 0x8 "gmacgrp_hash_table_reg2,This register contains the third 32 bits of the hash table."
hexmask.long 0x8 0.--31. 1. "ht95t64,This field contains the third 32 Bits (95:64) of the Hash table."
line.long 0xC "gmacgrp_hash_table_reg3,This register contains the fourth 32 bits of the hash table."
hexmask.long 0xC 0.--31. 1. "ht127t96,This field contains the fourth 32 Bits (127:96) of the Hash table."
line.long 0x10 "gmacgrp_hash_table_reg4,This register contains the fifth 32 bits of the hash table."
hexmask.long 0x10 0.--31. 1. "ht159t128,This field contains the fifth 32 Bits (159:128) of the Hash table."
line.long 0x14 "gmacgrp_hash_table_reg5,This register contains the sixth 32 bits of the hash table."
hexmask.long 0x14 0.--31. 1. "ht191t160,This field contains the sixth 32 Bits (191:160) of the Hash table."
line.long 0x18 "gmacgrp_hash_table_reg6,This register contains the seventh 32 bits of the hash table."
hexmask.long 0x18 0.--31. 1. "ht223t196,This field contains the seventh 32 Bits (223:196) of the Hash table."
line.long 0x1C "gmacgrp_hash_table_reg7,This register contains the eighth 32 bits of the hash table."
hexmask.long 0x1C 0.--31. 1. "ht255t224,This field contains the eighth 32 Bits (255:224) of the Hash table."
group.long 0x584++0x7
line.long 0x0 "gmacgrp_vlan_incl_reg,Register 353 (VLAN Tag Inclusion or Replacement Register)"
hexmask.long.word 0x0 20.--31. 1. "reserved_31_20,Reserved"
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bitfld.long 0x0 19. "csvl,C-VLAN or S-VLAN" "0,1"
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bitfld.long 0x0 18. "vlp,VLAN Priority Control" "0,1"
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bitfld.long 0x0 16.--17. "vlc,VLAN Tag Control in Transmit Frames" "0: No VLAN tag deletion,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
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hexmask.long.word 0x0 0.--15. 1. "vlt,VLAN Tag for Transmit Frames"
line.long 0x4 "gmacgrp_vlan_hash_table_reg,The 16-bit Hash table is used for group address filtering based on VLAN tag when Bit 18 (VTHM) of Register 7 (VLAN Tag Register) is set. For hash filtering. the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on Bit 16.."
hexmask.long.word 0x4 0.--15. 1. "vlht,This field contains the 16-bit VLAN Hash Table."
group.long 0x700++0x7
line.long 0x0 "gmacgrp_timestamp_control,Register 448 (Timestamp Control Register)"
rbitfld.long 0x0 29.--31. "reserved_31_29,Reserved" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 28. "atsen3,Auxiliary Snapshot 3 Enable" "0,1"
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rbitfld.long 0x0 27. "atsen2,Auxiliary Snapshot 2 Enable" "0,1"
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rbitfld.long 0x0 26. "atsen1,Auxiliary Snapshot 1 Enable" "0,1"
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rbitfld.long 0x0 25. "atsen0,Auxiliary Snapshot 0 Enable" "0,1"
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rbitfld.long 0x0 24. "atsfc,Auxiliary Snapshot FIFO Clear" "0,1"
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hexmask.long.byte 0x0 19.--23. 1. "reserved_23_19,Reserved"
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bitfld.long 0x0 18. "tsenmacaddr,Enable MAC address for PTP Frame Filtering" "0,1"
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bitfld.long 0x0 16.--17. "snaptypsel,Select PTP packets for Taking Snapshots" "0,1,2,3"
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bitfld.long 0x0 15. "tsmstrena,Enable Snapshot for Messages Relevant to Master" "0,1"
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bitfld.long 0x0 14. "tsevntena,Enable Timestamp Snapshot for Event Messages" "0,1"
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bitfld.long 0x0 13. "tsipv4ena,Enable Processing of PTP Frames Sent over IPv4-UDP" "0,1"
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bitfld.long 0x0 12. "tsipv6ena,Enable Processing of PTP Frames Sent Over IPv6-UDP" "0,1"
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bitfld.long 0x0 11. "tsipena,Enable Processing of PTP over Ethernet Frames" "0,1"
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bitfld.long 0x0 10. "tsver2ena,Enable PTP packet Processing for Version 2 Format" "0,1"
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bitfld.long 0x0 9. "tsctrlssr,Timestamp Digital or Binary Rollover Control" "0,1"
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bitfld.long 0x0 8. "tsenall,Enable Timestamp for All Frames" "0,1"
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rbitfld.long 0x0 6.--7. "reserved_7_6,Reserved" "0,1,2,3"
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rbitfld.long 0x0 5. "tsaddreg,Addend Reg Update" "0,1"
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rbitfld.long 0x0 4. "tstrig,Timestamp Interrupt Trigger Enable" "0,1"
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rbitfld.long 0x0 3. "tsupdt,Timestamp Update" "0,1"
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rbitfld.long 0x0 2. "tsinit,Timestamp Initialize" "0,1"
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rbitfld.long 0x0 1. "tscfupdt,Timestamp Fine or Coarse Update" "0,1"
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bitfld.long 0x0 0. "tsena,Timestamp Enable" "0,1"
line.long 0x4 "gmacgrp_sub_second_increment,In the Coarse Update mode (TSCFUPDT bit in Register 448). the value in this register is added to the system time every clock cycle of clk_ptp_ref_i. In the Fine Update mode. the value in this register is added to the system.."
hexmask.long.byte 0x4 0.--7. 1. "ssinc,The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example  when PTP clock is 50 MHz (period is 20 ns)  you should program 20 (0x14) when the System Time-Nanoseconds.."
rgroup.long 0x708++0x7
line.long 0x0 "gmacgrp_system_time_seconds,The System Time -Seconds register. along with System-TimeNanoseconds register. indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis. there is some delay from the.."
hexmask.long 0x0 0.--31. 1. "tss,The value in this field indicates the current value in seconds of the System Time maintained by the MAC."
line.long 0x4 "gmacgrp_system_time_nanoseconds,The value in this field has the sub second representation of time. with an accuracy of 0.46 ns. When TSCTRLSSR is set. each bit represents 1 ns and the maximum value is 0x3B9A_C9FF. after which it rolls-over to zero."
hexmask.long 0x4 0.--30. 1. "tsss,The value in this field has the sub second representation of time  with an accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)  each bit represents 1 ns and the maximum value is 0x3B9A_C9FF  after which it.."
group.long 0x710++0x17
line.long 0x0 "gmacgrp_system_time_seconds_update,The System Time - Seconds Update register. along with the System Time - Nanoseconds Update register. initializes or updates the system time maintained by the MAC. You must write both of these registers before setting.."
hexmask.long 0x0 0.--31. 1. "tss,The value in this field indicates the time in seconds to be initialized or added to the system time."
line.long 0x4 "gmacgrp_system_time_nanoseconds_update,Update system time"
bitfld.long 0x4 31. "addsub,When this bit is set  the time value is subtracted with the contents of the update register. When this bit is reset  the time value is added with the contents of the update register." "0,1"
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hexmask.long 0x4 0.--30. 1. "tsss,The value in this field has the sub second representation of time  with an accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)  each bit represents 1 ns and the programmed value should not exceed.."
line.long 0x8 "gmacgrp_timestamp_addend,This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in Register 448). This register content is added to a 32-bit accumulator in every clock cycle (of clk_ptp_ref_i) and the.."
hexmask.long 0x8 0.--31. 1. "tsar,This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization."
line.long 0xC "gmacgrp_target_time_seconds,The Target Time Seconds register. along with Target Time Nanoseconds register. is used to schedule an interrupt event (Register 458[1] when Advanced Timestamping is enabled; otherwise. TS interrupt bit in Register14[9]) when.."
hexmask.long 0xC 0.--31. 1. "tstr,This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers  then based on Bits [6:5] of Register 459 (PPS Control Register)  the MAC starts or stops the PPS signal output and generates an.."
line.long 0x10 "gmacgrp_target_time_nanoseconds,Target time"
rbitfld.long 0x10 31. "trgtbusy,The MAC sets this bit when the PPSCMD field (Bits[3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD field to 010 or 011  instructs the MAC to synchronize the Target Time Registers to the PTP clock.." "0,1"
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hexmask.long 0x10 0.--30. 1. "ttslo,This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers  then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register)  the MAC starts or stops the.."
line.long 0x14 "gmacgrp_system_time_higher_word_seconds,System time higher word"
hexmask.long.word 0x14 0.--15. 1. "tshwr,This field contains the most significant 16-bits of the timestamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register."
rgroup.long 0x728++0x3
line.long 0x0 "gmacgrp_timestamp_status,Timestamp status. All bits except Bits[27:25] get cleared when the host reads this register."
hexmask.long.byte 0x0 25.--29. 1. "atsns,This field indicates the number of Snapshots available in the FIFO. A value of 16 (equal to the depth of the FIFO) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is.."
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bitfld.long 0x0 24. "atsstm,This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO." "0,1"
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hexmask.long.byte 0x0 16.--19. 1. "atsstn,These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time  it means that corresponding auxiliary triggers were sampled at the.."
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bitfld.long 0x0 3. "tstrgterr,This bit is set when the target time  being programmed in Target Time Registers  is already elapsed. This bit is cleared when read by the application." "0,1"
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bitfld.long 0x0 2. "auxtstrig,This bit is set high when the auxiliary snapshot is written to the FIFO." "0,1"
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bitfld.long 0x0 1. "tstargt,When set  this bit indicates that the value of system time is greater or equal to the value specified in the Register 455 (Target Time Seconds Register) and Register 456 (Target Time Nanoseconds Register)." "0,1"
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bitfld.long 0x0 0. "tssovf,When set  this bit indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF." "0,1"
group.long 0x72C++0x3
line.long 0x0 "gmacgrp_pps_control,Controls timestamp Pulse-Per-Second output"
bitfld.long 0x0 5.--6. "trgtmodsel0,This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal" "0,1,2,3"
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bitfld.long 0x0 4. "ppsen0,When set low  Bits[3:0] function as PPSCTRL (backward compatible). When set high  Bits[3:0] function as PPSCMD." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "ppsctrl_ppscmd,PPSCTRL0: PPS0 Output Frequency Control"
rgroup.long 0x730++0x7
line.long 0x0 "gmacgrp_auxiliary_timestamp_nanoseconds,This register. along with Register 461 (Auxiliary Timestamp Seconds Register). gives the 64-bit timestamp stored as auxiliary snapshot. The two registers together form the read port of a 64-bit wide FIFO with a.."
hexmask.long 0x0 0.--30. 1. "auxtslo,Contains the lower 32 bits (nano-seconds field) of the auxiliary timestamp."
line.long 0x4 "gmacgrp_auxiliary_timestamp_seconds,Contains the higher 32 bits (Seconds field) of the auxiliary timestamp."
hexmask.long 0x4 0.--31. 1. "auxtshi,Contains the higher 32 bits (Seconds field) of the auxiliary timestamp."
group.long 0x760++0x7
line.long 0x0 "gmacgrp_pps0_interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])."
hexmask.long 0x0 0.--31. 1. "ppsint,These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value."
line.long 0x4 "gmacgrp_pps0_width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of the PPS0 signal output (ptp_pps_o[0])."
hexmask.long 0x4 0.--31. 1. "ppswidth,These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value."
group.long 0x800++0x37F
line.long 0x0 "gmacgrp_mac_address16_high,Register 512 (MAC Address16 High Register)"
bitfld.long 0x0 31. "ae,Address Enable" "0,1"
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bitfld.long 0x0 30. "sa,Source Address" "0,1"
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bitfld.long 0x0 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x0 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x0 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x0 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x0 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x0 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "reserved_23_16,Reserved"
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hexmask.long.word 0x0 0.--15. 1. "addrhi,MAC Address16 [47:32]"
line.long 0x4 "gmacgrp_mac_address16_low,Register 513 (MAC Address16 Low Register)"
hexmask.long 0x4 0.--31. 1. "addrlo,MAC Address16 [31:0]"
line.long 0x8 "gmacgrp_mac_address17_high,Register 514 (MAC Address17 High Register)"
bitfld.long 0x8 31. "ae,Address Enable" "0,1"
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bitfld.long 0x8 30. "sa,Source Address" "0,1"
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bitfld.long 0x8 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x8 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x8 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x8 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x8 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x8 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
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hexmask.long.byte 0x8 16.--23. 1. "reserved_23_16,Reserved"
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hexmask.long.word 0x8 0.--15. 1. "addrhi,MAC Address18 [47:32]"
line.long 0xC "gmacgrp_mac_address17_low,Register 515 (MAC Address17 Low Register)"
hexmask.long 0xC 0.--31. 1. "addrlo,MAC Address17 [31:0]"
line.long 0x10 "gmacgrp_mac_address18_high,Register 516 (MAC Address18 High Register)"
bitfld.long 0x10 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x10 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x10 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x10 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x10 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x10 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x10 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x10 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x10 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x10 0.--15. 1. "addrhi,MAC Address18 [47:32]"
line.long 0x14 "gmacgrp_mac_address18_low,Register 517 (MAC Address18 Low Register)"
hexmask.long 0x14 0.--31. 1. "addrlo,MAC Address18 [31:0]"
line.long 0x18 "gmacgrp_mac_address19_high,Register 518 (MAC Address19 High Register)"
bitfld.long 0x18 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x18 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x18 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x18 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x18 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x18 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x18 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x18 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x18 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x18 0.--15. 1. "addrhi,MAC Address19 [47:32]"
line.long 0x1C "gmacgrp_mac_address19_low,Register 519 (MAC Address19 Low Register)"
hexmask.long 0x1C 0.--31. 1. "addrlo,MAC Address19 [31:0]"
line.long 0x20 "gmacgrp_mac_address20_high,Register 520 (MAC Address20 High Register)"
bitfld.long 0x20 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x20 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x20 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x20 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x20 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x20 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x20 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x20 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x20 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x20 0.--15. 1. "addrhi,MAC Address20 [47:32]"
line.long 0x24 "gmacgrp_mac_address20_low,Register 521 (MAC Address20 Low Register)"
hexmask.long 0x24 0.--31. 1. "addrlo,MAC Address20 [31:0]"
line.long 0x28 "gmacgrp_mac_address21_high,Register 522 (MAC Address21 High Register)"
bitfld.long 0x28 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x28 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x28 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x28 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x28 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x28 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x28 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x28 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x28 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x28 0.--15. 1. "addrhi,MAC Address21 [47:32]"
line.long 0x2C "gmacgrp_mac_address21_low,Register 523 (MAC Address21 Low Register)"
hexmask.long 0x2C 0.--31. 1. "addrlo,MAC Address21 [31:0]"
line.long 0x30 "gmacgrp_mac_address22_high,Register 524 (MAC Address22 High Register)"
bitfld.long 0x30 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x30 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x30 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x30 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x30 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x30 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x30 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x30 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x30 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x30 0.--15. 1. "addrhi,MAC Address22 [47:32]"
line.long 0x34 "gmacgrp_mac_address22_low,Register 525 (MAC Address22 Low Register)"
hexmask.long 0x34 0.--31. 1. "addrlo,MAC Address22 [31:0]"
line.long 0x38 "gmacgrp_mac_address23_high,Register 526 (MAC Address23 High Register"
bitfld.long 0x38 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x38 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x38 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x38 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x38 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x38 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x38 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x38 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x38 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x38 0.--15. 1. "addrhi,MAC Address23 [47:32]"
line.long 0x3C "gmacgrp_mac_address23_low,Register 527 (MAC Address23 Low Register)"
hexmask.long 0x3C 0.--31. 1. "addrlo,MAC Address23 [31:0]"
line.long 0x40 "gmacgrp_mac_address24_high,Register 528 (MAC Address24 High Register)"
bitfld.long 0x40 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x40 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x40 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x40 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x40 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x40 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x40 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x40 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x40 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x40 0.--15. 1. "addrhi,MAC Address1 [47:32]"
line.long 0x44 "gmacgrp_mac_address24_low,Register 529 (MAC Address24 Low Register)"
hexmask.long 0x44 0.--31. 1. "addrlo,MAC Address24 [31:0]"
line.long 0x48 "gmacgrp_mac_address25_high,Register 530 (MAC Address25 High Register)"
bitfld.long 0x48 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x48 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x48 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x48 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x48 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x48 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x48 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x48 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x48 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x48 0.--15. 1. "addrhi,MAC Address25 [47:32]"
line.long 0x4C "gmacgrp_mac_address25_low,Register 531 (MAC Address25 Low Register)"
hexmask.long 0x4C 0.--31. 1. "addrlo,MAC Address25 [31:0]"
line.long 0x50 "gmacgrp_mac_address26_high,Register 532 (MAC Address26 High Register)"
bitfld.long 0x50 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x50 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x50 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x50 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x50 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x50 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x50 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x50 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x50 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x50 0.--15. 1. "addrhi,MAC Address26 [47:32]"
line.long 0x54 "gmacgrp_mac_address26_low,Register 533 (MAC Address26 Low Register)"
hexmask.long 0x54 0.--31. 1. "addrlo,MAC Address26 [31:0]"
line.long 0x58 "gmacgrp_mac_address27_high,Register 534 (MAC Address27 High Register)"
bitfld.long 0x58 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x58 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x58 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x58 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x58 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x58 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x58 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x58 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x58 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x58 0.--15. 1. "addrhi,MAC Address27 [47:32]"
line.long 0x5C "gmacgrp_mac_address27_low,Register 535 (MAC Address27 Low Register)"
hexmask.long 0x5C 0.--31. 1. "addrlo,MAC Address27 [31:0]"
line.long 0x60 "gmacgrp_mac_address28_high,Register 536 (MAC Address28 High Register)"
bitfld.long 0x60 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x60 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x60 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x60 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x60 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x60 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x60 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x60 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x60 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x60 0.--15. 1. "addrhi,MAC Address28 [47:32]"
line.long 0x64 "gmacgrp_mac_address28_low,Register 537 (MAC Address28 Low Register)"
hexmask.long 0x64 0.--31. 1. "addrlo,MAC Address28 [31:0]"
line.long 0x68 "gmacgrp_mac_address29_high,Register 538 (MAC Address29 High Register)"
bitfld.long 0x68 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x68 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x68 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x68 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x68 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x68 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x68 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x68 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x68 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x68 0.--15. 1. "addrhi,MAC Address29 [47:32]"
line.long 0x6C "gmacgrp_mac_address29_low,Register 539 (MAC Address29 Low Register)"
hexmask.long 0x6C 0.--31. 1. "addrlo,MAC Address29 [31:0]"
line.long 0x70 "gmacgrp_mac_address30_high,Register 540 (MAC Address30 High Register)"
bitfld.long 0x70 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x70 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x70 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x70 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x70 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x70 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x70 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x70 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x70 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x70 0.--15. 1. "addrhi,MAC Address30 [47:32]"
line.long 0x74 "gmacgrp_mac_address30_low,Register 541 (MAC Address30 Low Register)"
hexmask.long 0x74 0.--31. 1. "addrlo,MAC Address30 [31:0]"
line.long 0x78 "gmacgrp_mac_address31_high,Register 542 (MAC Address31 High Register)"
bitfld.long 0x78 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x78 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x78 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x78 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x78 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x78 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x78 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x78 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x78 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x78 0.--15. 1. "addrhi,MAC Address31 [47:32]"
line.long 0x7C "gmacgrp_mac_address31_low,Register 543 (MAC Address31 Low Register)"
hexmask.long 0x7C 0.--31. 1. "addrlo,MAC Address31 [31:0]"
line.long 0x80 "gmacgrp_mac_address32_high,Register 544 (MAC Address32 High Register)"
bitfld.long 0x80 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x80 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x80 0.--15. 1. "addrhi,MAC Address32 [47:32]"
line.long 0x84 "gmacgrp_mac_address32_low,Register 545 (MAC Address32 Low Register)"
hexmask.long 0x84 0.--31. 1. "addrlo,MAC Address32 [31:0]"
line.long 0x88 "gmacgrp_mac_address33_high,Register 546 (MAC Address33 High Register)"
bitfld.long 0x88 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x88 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x88 0.--15. 1. "addrhi,MAC Address33 [47:32]"
line.long 0x8C "gmacgrp_mac_address33_low,Register 547 (MAC Address33 Low Register)"
hexmask.long 0x8C 0.--31. 1. "addrlo,MAC Address33 [31:0]"
line.long 0x90 "gmacgrp_mac_address34_high,Register 548 (MAC Address34 High Register)"
bitfld.long 0x90 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x90 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x90 0.--15. 1. "addrhi,MAC Address34 [47:32]"
line.long 0x94 "gmacgrp_mac_address34_low,Register 549 (MAC Address34 Low Register)"
hexmask.long 0x94 0.--31. 1. "addrlo,MAC Address34 [31:0]"
line.long 0x98 "gmacgrp_mac_address35_high,Register 550 (MAC Address35 High Register)"
bitfld.long 0x98 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x98 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x98 0.--15. 1. "addrhi,MAC Address35 [47:32]"
line.long 0x9C "gmacgrp_mac_address35_low,Register 551 (MAC Address35 Low Register)"
hexmask.long 0x9C 0.--31. 1. "addrlo,MAC Address35 [31:0]"
line.long 0xA0 "gmacgrp_mac_address36_high,Register 552 (MAC Address36 High Register)"
bitfld.long 0xA0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xA0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xA0 0.--15. 1. "addrhi,MAC Address36 [47:32]"
line.long 0xA4 "gmacgrp_mac_address36_low,Register 553 (MAC Address36 Low Register)"
hexmask.long 0xA4 0.--31. 1. "addrlo,MAC Address36 [31:0]"
line.long 0xA8 "gmacgrp_mac_address37_high,Register 554 (MAC Address37 High Register)"
bitfld.long 0xA8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xA8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xA8 0.--15. 1. "addrhi,MAC Address37 [47:32]"
line.long 0xAC "gmacgrp_mac_address37_low,Register 555 (MAC Address37 Low Register)"
hexmask.long 0xAC 0.--31. 1. "addrlo,MAC Address37 [31:0]"
line.long 0xB0 "gmacgrp_mac_address38_high,Register 556 (MAC Address38 High Register)"
bitfld.long 0xB0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xB0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xB0 0.--15. 1. "addrhi,MAC Address38 [47:32]"
line.long 0xB4 "gmacgrp_mac_address38_low,Register 557 (MAC Address38 Low Register)"
hexmask.long 0xB4 0.--31. 1. "addrlo,MAC Address38 [31:0]"
line.long 0xB8 "gmacgrp_mac_address39_high,Register 558 (MAC Address39 High Register)"
bitfld.long 0xB8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xB8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xB8 0.--15. 1. "addrhi,MAC Address39 [47:32]"
line.long 0xBC "gmacgrp_mac_address39_low,Register 559 (MAC Address39 Low Register)"
hexmask.long 0xBC 0.--31. 1. "addrlo,MAC Address39 [31:0]"
line.long 0xC0 "gmacgrp_mac_address40_high,Register 560 (MAC Address40 High Register)"
bitfld.long 0xC0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xC0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xC0 0.--15. 1. "addrhi,MAC Address40 [47:32]"
line.long 0xC4 "gmacgrp_mac_address40_low,Register 561 (MAC Address40 Low Register)"
hexmask.long 0xC4 0.--31. 1. "addrlo,MAC Address40 [31:0]"
line.long 0xC8 "gmacgrp_mac_address41_high,Register 562 (MAC Address41 High Register)"
bitfld.long 0xC8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xC8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xC8 0.--15. 1. "addrhi,MAC Address41 [47:32]"
line.long 0xCC "gmacgrp_mac_address41_low,Register 563 (MAC Address41 Low Register)"
hexmask.long 0xCC 0.--31. 1. "addrlo,MAC Address41 [31:0]"
line.long 0xD0 "gmacgrp_mac_address42_high,Register 564 (MAC Address42 High Register)"
bitfld.long 0xD0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xD0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xD0 0.--15. 1. "addrhi,MAC Address42 [47:32]"
line.long 0xD4 "gmacgrp_mac_address42_low,Register 565 (MAC Address42 Low Register)"
hexmask.long 0xD4 0.--31. 1. "addrlo,MAC Address42 [31:0]"
line.long 0xD8 "gmacgrp_mac_address43_high,Register 566 (MAC Address43 High Register)"
bitfld.long 0xD8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xD8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xD8 0.--15. 1. "addrhi,MAC Address43 [47:32]"
line.long 0xDC "gmacgrp_mac_address43_low,Register 567 (MAC Address43 Low Register)"
hexmask.long 0xDC 0.--31. 1. "addrlo,MAC Address43 [31:0]"
line.long 0xE0 "gmacgrp_mac_address44_high,Register 568 (MAC Address44 High Register)"
bitfld.long 0xE0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xE0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xE0 0.--15. 1. "addrhi,MAC Address44 [47:32]"
line.long 0xE4 "gmacgrp_mac_address44_low,Register 569 (MAC Address44 Low Register)"
hexmask.long 0xE4 0.--31. 1. "addrlo,MAC Address44 [31:0]"
line.long 0xE8 "gmacgrp_mac_address45_high,Register 570 (MAC Address45 High Register)"
bitfld.long 0xE8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xE8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xE8 0.--15. 1. "addrhi,MAC Address45 [47:32]"
line.long 0xEC "gmacgrp_mac_address45_low,Register 571 (MAC Address45 Low Register)"
hexmask.long 0xEC 0.--31. 1. "addrlo,MAC Address45 [31:0]"
line.long 0xF0 "gmacgrp_mac_address46_high,Register 572 (MAC Address46 High Register)"
bitfld.long 0xF0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xF0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xF0 0.--15. 1. "addrhi,MAC Address46 [47:32]"
line.long 0xF4 "gmacgrp_mac_address46_low,Register 573 (MAC Address46 Low Register)"
hexmask.long 0xF4 0.--31. 1. "addrlo,MAC Address46 [31:0]"
line.long 0xF8 "gmacgrp_mac_address47_high,Register 574 (MAC Address47 High Register)"
bitfld.long 0xF8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xF8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xF8 0.--15. 1. "addrhi,MAC Address47 [47:32]"
line.long 0xFC "gmacgrp_mac_address47_low,Register 575 (MAC Address47 Low Register)"
hexmask.long 0xFC 0.--31. 1. "addrlo,MAC Address47 [31:0]"
line.long 0x100 "gmacgrp_mac_address48_high,Register 576 (MAC Address48 High Register)"
bitfld.long 0x100 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x100 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x100 0.--15. 1. "addrhi,MAC Address48 [47:32]"
line.long 0x104 "gmacgrp_mac_address48_low,Register 577 (MAC Address48 Low Register)"
hexmask.long 0x104 0.--31. 1. "addrlo,MAC Address48 [31:0]"
line.long 0x108 "gmacgrp_mac_address49_high,Register 578 (MAC Address49 High Register)"
bitfld.long 0x108 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x108 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x108 0.--15. 1. "addrhi,MAC Address49 [47:32]"
line.long 0x10C "gmacgrp_mac_address49_low,Register 579 (MAC Address49 Low Register)"
hexmask.long 0x10C 0.--31. 1. "addrlo,MAC Address49 [31:0]"
line.long 0x110 "gmacgrp_mac_address50_high,Register 580 (MAC Address50 High Register)"
bitfld.long 0x110 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x110 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x110 0.--15. 1. "addrhi,MAC Address50 [47:32]"
line.long 0x114 "gmacgrp_mac_address50_low,Register 581 (MAC Address50 Low Register)"
hexmask.long 0x114 0.--31. 1. "addrlo,MAC Address50 [31:0]"
line.long 0x118 "gmacgrp_mac_address51_high,Register 582 (MAC Address51 High Register)"
bitfld.long 0x118 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x118 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x118 0.--15. 1. "addrhi,MAC Address51 [47:32]"
line.long 0x11C "gmacgrp_mac_address51_low,Register 583 (MAC Address51 Low Register)"
hexmask.long 0x11C 0.--31. 1. "addrlo,MAC Address51 [31:0]"
line.long 0x120 "gmacgrp_mac_address52_high,Register 584 (MAC Address52 High Register)"
bitfld.long 0x120 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x120 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x120 0.--15. 1. "addrhi,MAC Address52 [47:32]"
line.long 0x124 "gmacgrp_mac_address52_low,Register 585 (MAC Address52 Low Register)"
hexmask.long 0x124 0.--31. 1. "addrlo,MAC Address52 [31:0]"
line.long 0x128 "gmacgrp_mac_address53_high,Register 586 (MAC Address53 High Register)"
bitfld.long 0x128 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x128 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x128 0.--15. 1. "addrhi,MAC Address53 [47:32]"
line.long 0x12C "gmacgrp_mac_address53_low,Register 587 (MAC Address53 Low Register)"
hexmask.long 0x12C 0.--31. 1. "addrlo,MAC Address53 [31:0]"
line.long 0x130 "gmacgrp_mac_address54_high,Register 588 (MAC Address54 High Register)"
bitfld.long 0x130 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x130 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x130 0.--15. 1. "addrhi,MAC Address54 [47:32]"
line.long 0x134 "gmacgrp_mac_address54_low,Register 589 (MAC Address54 Low Register)"
hexmask.long 0x134 0.--31. 1. "addrlo,MAC Address54 [31:0]"
line.long 0x138 "gmacgrp_mac_address55_high,Register 590 (MAC Address55 High Register)"
bitfld.long 0x138 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x138 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x138 0.--15. 1. "addrhi,MAC Address55 [47:32]"
line.long 0x13C "gmacgrp_mac_address55_low,Register 591 (MAC Address55 Low Register)"
hexmask.long 0x13C 0.--31. 1. "addrlo,MAC Address55 [31:0]"
line.long 0x140 "gmacgrp_mac_address56_high,Register 592 (MAC Address56 High Register)"
bitfld.long 0x140 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x140 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x140 0.--15. 1. "addrhi,MAC Address56 [47:32]"
line.long 0x144 "gmacgrp_mac_address56_low,Register 593 (MAC Address56 Low Register)"
hexmask.long 0x144 0.--31. 1. "addrlo,MAC Address56 [31:0]"
line.long 0x148 "gmacgrp_mac_address57_high,Register 594 (MAC Address57 High Register)"
bitfld.long 0x148 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x148 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x148 0.--15. 1. "addrhi,MAC Address57 [47:32]"
line.long 0x14C "gmacgrp_mac_address57_low,Register 595 (MAC Address57 Low Register)"
hexmask.long 0x14C 0.--31. 1. "addrlo,MAC Address57 [31:0]"
line.long 0x150 "gmacgrp_mac_address58_high,Register 596 (MAC Address58 High Register)"
bitfld.long 0x150 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x150 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x150 0.--15. 1. "addrhi,MAC Address58 [47:32]"
line.long 0x154 "gmacgrp_mac_address58_low,Register 597 (MAC Address58 Low Register)"
hexmask.long 0x154 0.--31. 1. "addrlo,MAC Address58 [31:0]"
line.long 0x158 "gmacgrp_mac_address59_high,Register 598 (MAC Address59 High Register)"
bitfld.long 0x158 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x158 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x158 0.--15. 1. "addrhi,MAC Address59 [47:32]"
line.long 0x15C "gmacgrp_mac_address59_low,Register 599 (MAC Address59 Low Register)"
hexmask.long 0x15C 0.--31. 1. "addrlo,MAC Address59 [31:0]"
line.long 0x160 "gmacgrp_mac_address60_high,Register 600 (MAC Address60 High Register)"
bitfld.long 0x160 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x160 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x160 0.--15. 1. "addrhi,MAC Address60 [47:32]"
line.long 0x164 "gmacgrp_mac_address60_low,Register 601 (MAC Address60 Low Register)"
hexmask.long 0x164 0.--31. 1. "addrlo,MAC Address60 [31:0]"
line.long 0x168 "gmacgrp_mac_address61_high,Register 602 (MAC Address61 High Register)"
bitfld.long 0x168 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x168 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x168 0.--15. 1. "addrhi,MAC Address61 [47:32]"
line.long 0x16C "gmacgrp_mac_address61_low,Register 603 (MAC Address61 Low Register)"
hexmask.long 0x16C 0.--31. 1. "addrlo,MAC Address61 [31:0]"
line.long 0x170 "gmacgrp_mac_address62_high,Register 604 (MAC Address62 High Register)"
bitfld.long 0x170 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x170 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x170 0.--15. 1. "addrhi,MAC Address62 [47:32]"
line.long 0x174 "gmacgrp_mac_address62_low,Register 605 (MAC Address62 Low Register)"
hexmask.long 0x174 0.--31. 1. "addrlo,MAC Address62 [31:0]"
line.long 0x178 "gmacgrp_mac_address63_high,Register 606 (MAC Address63 High Register)"
bitfld.long 0x178 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x178 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x178 0.--15. 1. "addrhi,MAC Address63 [47:32]"
line.long 0x17C "gmacgrp_mac_address63_low,Register 607 (MAC Address63 Low Register)"
hexmask.long 0x17C 0.--31. 1. "addrlo,MAC Address63 [31:0]"
line.long 0x180 "gmacgrp_mac_address64_high,Register 608 (MAC Address64 High Register)"
bitfld.long 0x180 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x180 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x180 0.--15. 1. "addrhi,MAC Address64 [47:32]"
line.long 0x184 "gmacgrp_mac_address64_low,Register 609 (MAC Address64 Low Register)"
hexmask.long 0x184 0.--31. 1. "addrlo,MAC Address64 [31:0]"
line.long 0x188 "gmacgrp_mac_address65_high,Register 610 (MAC Address65 High Register)"
bitfld.long 0x188 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x188 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x188 0.--15. 1. "addrhi,MAC Address65 [47:32]"
line.long 0x18C "gmacgrp_mac_address65_low,Register 611 (MAC Address65 Low Register)"
hexmask.long 0x18C 0.--31. 1. "addrlo,MAC Address65 [31:0]"
line.long 0x190 "gmacgrp_mac_address66_high,Register 612 (MAC Address66 High Register)"
bitfld.long 0x190 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x190 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x190 0.--15. 1. "addrhi,MAC Address66 [47:32]"
line.long 0x194 "gmacgrp_mac_address66_low,Register 613 (MAC Address66 Low Register)"
hexmask.long 0x194 0.--31. 1. "addrlo,MAC Address66 [31:0]"
line.long 0x198 "gmacgrp_mac_address67_high,Register 614 (MAC Address67 High Register)"
bitfld.long 0x198 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x198 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x198 0.--15. 1. "addrhi,MAC Address67 [47:32]"
line.long 0x19C "gmacgrp_mac_address67_low,Register 615 (MAC Address67 Low Register)"
hexmask.long 0x19C 0.--31. 1. "addrlo,MAC Address67 [31:0]"
line.long 0x1A0 "gmacgrp_mac_address68_high,Register 616 (MAC Address68 High Register)"
bitfld.long 0x1A0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1A0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1A0 0.--15. 1. "addrhi,MAC Address68 [47:32]"
line.long 0x1A4 "gmacgrp_mac_address68_low,Register 617 (MAC Address68 Low Register)"
hexmask.long 0x1A4 0.--31. 1. "addrlo,MAC Address68 [31:0]"
line.long 0x1A8 "gmacgrp_mac_address69_high,Register 618 (MAC Address69 High Register)"
bitfld.long 0x1A8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1A8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1A8 0.--15. 1. "addrhi,MAC Address69 [47:32]"
line.long 0x1AC "gmacgrp_mac_address69_low,Register 619 (MAC Address69 Low Register)"
hexmask.long 0x1AC 0.--31. 1. "addrlo,MAC Address69 [31:0]"
line.long 0x1B0 "gmacgrp_mac_address70_high,Register 620 (MAC Address70 High Register)"
bitfld.long 0x1B0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1B0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1B0 0.--15. 1. "addrhi,MAC Address70 [47:32]"
line.long 0x1B4 "gmacgrp_mac_address70_low,Register 621 (MAC Address70 Low Register)"
hexmask.long 0x1B4 0.--31. 1. "addrlo,MAC Address70 [31:0]"
line.long 0x1B8 "gmacgrp_mac_address71_high,Register 622 (MAC Address71 High Register)"
bitfld.long 0x1B8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1B8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1B8 0.--15. 1. "addrhi,MAC Address71 [47:32]"
line.long 0x1BC "gmacgrp_mac_address71_low,Register 623 (MAC Address71 Low Register)"
hexmask.long 0x1BC 0.--31. 1. "addrlo,MAC Address71 [31:0]"
line.long 0x1C0 "gmacgrp_mac_address72_high,Register 624 (MAC Address72 High Register)"
bitfld.long 0x1C0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1C0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1C0 0.--15. 1. "addrhi,MAC Address72 [47:32]"
line.long 0x1C4 "gmacgrp_mac_address72_low,Register 625 (MAC Address72 Low Register)"
hexmask.long 0x1C4 0.--31. 1. "addrlo,MAC Address72 [31:0]"
line.long 0x1C8 "gmacgrp_mac_address73_high,Register 626 (MAC Address73 High Register)"
bitfld.long 0x1C8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1C8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1C8 0.--15. 1. "addrhi,MAC Address73 [47:32]"
line.long 0x1CC "gmacgrp_mac_address73_low,Register 627 (MAC Address73 Low Register)"
hexmask.long 0x1CC 0.--31. 1. "addrlo,MAC Address73 [31:0]"
line.long 0x1D0 "gmacgrp_mac_address74_high,Register 628 (MAC Address74 High Register)"
bitfld.long 0x1D0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1D0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1D0 0.--15. 1. "addrhi,MAC Address74 [47:32]"
line.long 0x1D4 "gmacgrp_mac_address74_low,Register 629 (MAC Address74 Low Register)"
hexmask.long 0x1D4 0.--31. 1. "addrlo,MAC Address74 [31:0]"
line.long 0x1D8 "gmacgrp_mac_address75_high,Register 630 (MAC Address75 High Register)"
bitfld.long 0x1D8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1D8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1D8 0.--15. 1. "addrhi,MAC Address75 [47:32]"
line.long 0x1DC "gmacgrp_mac_address75_low,Register 631 (MAC Address75 Low Register)"
hexmask.long 0x1DC 0.--31. 1. "addrlo,MAC Address75 [31:0]"
line.long 0x1E0 "gmacgrp_mac_address76_high,Register 632 (MAC Address76 High Register)"
bitfld.long 0x1E0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1E0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1E0 0.--15. 1. "addrhi,MAC Address76 [47:32]"
line.long 0x1E4 "gmacgrp_mac_address76_low,Register 633 (MAC Address76 Low Register)"
hexmask.long 0x1E4 0.--31. 1. "addrlo,MAC Address76 [31:0]"
line.long 0x1E8 "gmacgrp_mac_address77_high,Register 634 (MAC Address77 High Register)"
bitfld.long 0x1E8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1E8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1E8 0.--15. 1. "addrhi,MAC Address77 [47:32]"
line.long 0x1EC "gmacgrp_mac_address77_low,Register 635 (MAC Address77 Low Register)"
hexmask.long 0x1EC 0.--31. 1. "addrlo,MAC Address77 [31:0]"
line.long 0x1F0 "gmacgrp_mac_address78_high,Register 636 (MAC Address78 High Register)"
bitfld.long 0x1F0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1F0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1F0 0.--15. 1. "addrhi,MAC Address78 [47:32]"
line.long 0x1F4 "gmacgrp_mac_address78_low,Register 637 (MAC Address78 Low Register)"
hexmask.long 0x1F4 0.--31. 1. "addrlo,MAC Address78 [31:0]"
line.long 0x1F8 "gmacgrp_mac_address79_high,Register 638 (MAC Address79 High Register)"
bitfld.long 0x1F8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1F8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1F8 0.--15. 1. "addrhi,MAC Address79 [47:32]"
line.long 0x1FC "gmacgrp_mac_address79_low,Register 639 (MAC Address79 Low Register)"
hexmask.long 0x1FC 0.--31. 1. "addrlo,MAC Address79 [31:0]"
line.long 0x200 "gmacgrp_mac_address80_high,Register 640 (MAC Address80 High Register)"
bitfld.long 0x200 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x200 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x200 0.--15. 1. "addrhi,MAC Address80 [47:32]"
line.long 0x204 "gmacgrp_mac_address80_low,Register 641 (MAC Address80 Low Register)"
hexmask.long 0x204 0.--31. 1. "addrlo,MAC Address80 [31:0]"
line.long 0x208 "gmacgrp_mac_address81_high,Register 642 (MAC Address81 High Register)"
bitfld.long 0x208 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x208 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x208 0.--15. 1. "addrhi,MAC Address81 [47:32]"
line.long 0x20C "gmacgrp_mac_address81_low,Register 643 (MAC Address81 Low Register)"
hexmask.long 0x20C 0.--31. 1. "addrlo,MAC Address81 [31:0]"
line.long 0x210 "gmacgrp_mac_address82_high,Register 644 (MAC Address82 High Register)"
bitfld.long 0x210 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x210 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x210 0.--15. 1. "addrhi,MAC Address82 [47:32]"
line.long 0x214 "gmacgrp_mac_address82_low,Register 645 (MAC Address82 Low Register)"
hexmask.long 0x214 0.--31. 1. "addrlo,MAC Address82 [31:0]"
line.long 0x218 "gmacgrp_mac_address83_high,Register 646 (MAC Address83 High Register)"
bitfld.long 0x218 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x218 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x218 0.--15. 1. "addrhi,MAC Address83 [47:32]"
line.long 0x21C "gmacgrp_mac_address83_low,Register 647 (MAC Address83 Low Register)"
hexmask.long 0x21C 0.--31. 1. "addrlo,MAC Address83 [31:0]"
line.long 0x220 "gmacgrp_mac_address84_high,Register 648 (MAC Address84 High Register)"
bitfld.long 0x220 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x220 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x220 0.--15. 1. "addrhi,MAC Address84 [47:32]"
line.long 0x224 "gmacgrp_mac_address84_low,Register 649 (MAC Address84 Low Register)"
hexmask.long 0x224 0.--31. 1. "addrlo,MAC Address84 [31:0]"
line.long 0x228 "gmacgrp_mac_address85_high,Register 650 (MAC Address85 High Register)"
bitfld.long 0x228 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x228 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x228 0.--15. 1. "addrhi,MAC Address85 [47:32]"
line.long 0x22C "gmacgrp_mac_address85_low,Register 651 (MAC Address85 Low Register)"
hexmask.long 0x22C 0.--31. 1. "addrlo,MAC Address85 [31:0]"
line.long 0x230 "gmacgrp_mac_address86_high,Register 652 (MAC Address86 High Register)"
bitfld.long 0x230 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x230 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x230 0.--15. 1. "addrhi,MAC Address86 [47:32]"
line.long 0x234 "gmacgrp_mac_address86_low,Register 653 (MAC Address86 Low Register)"
hexmask.long 0x234 0.--31. 1. "addrlo,MAC Address86 [31:0]"
line.long 0x238 "gmacgrp_mac_address87_high,Register 654 (MAC Address87 High Register)"
bitfld.long 0x238 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x238 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x238 0.--15. 1. "addrhi,MAC Address87 [47:32]"
line.long 0x23C "gmacgrp_mac_address87_low,Register 655 (MAC Address87 Low Register)"
hexmask.long 0x23C 0.--31. 1. "addrlo,MAC Address87 [31:0]"
line.long 0x240 "gmacgrp_mac_address88_high,Register 656 (MAC Address88 High Register)"
bitfld.long 0x240 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x240 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x240 0.--15. 1. "addrhi,MAC Address88 [47:32]"
line.long 0x244 "gmacgrp_mac_address88_low,Register 657 (MAC Address88 Low Register)"
hexmask.long 0x244 0.--31. 1. "addrlo,MAC Address88 [31:0]"
line.long 0x248 "gmacgrp_mac_address89_high,Register 658 (MAC Address89 High Register)"
bitfld.long 0x248 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x248 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x248 0.--15. 1. "addrhi,MAC Address89 [47:32]"
line.long 0x24C "gmacgrp_mac_address89_low,Register 659 (MAC Address89 Low Register)"
hexmask.long 0x24C 0.--31. 1. "addrlo,MAC Address89 [31:0]"
line.long 0x250 "gmacgrp_mac_address90_high,Register 660 (MAC Address90 High Register)"
bitfld.long 0x250 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x250 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x250 0.--15. 1. "addrhi,MAC Address90 [47:32]"
line.long 0x254 "gmacgrp_mac_address90_low,Register 661 (MAC Address90 Low Register)"
hexmask.long 0x254 0.--31. 1. "addrlo,MAC Address90 [31:0]"
line.long 0x258 "gmacgrp_mac_address91_high,Register 662 (MAC Address91 High Register)"
bitfld.long 0x258 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x258 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x258 0.--15. 1. "addrhi,MAC Address91 [47:32]"
line.long 0x25C "gmacgrp_mac_address91_low,Register 663 (MAC Address91 Low Register)"
hexmask.long 0x25C 0.--31. 1. "addrlo,MAC Address91 [31:0]"
line.long 0x260 "gmacgrp_mac_address92_high,Register 664 (MAC Address92 High Register)"
bitfld.long 0x260 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x260 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x260 0.--15. 1. "addrhi,MAC Address92 [47:32]"
line.long 0x264 "gmacgrp_mac_address92_low,Register 665 (MAC Address92 Low Register)"
hexmask.long 0x264 0.--31. 1. "addrlo,MAC Address92 [31:0]"
line.long 0x268 "gmacgrp_mac_address93_high,Register 666 (MAC Address93 High Register)"
bitfld.long 0x268 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x268 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x268 0.--15. 1. "addrhi,MAC Address93 [47:32]"
line.long 0x26C "gmacgrp_mac_address93_low,Register 667 (MAC Address93 Low Register)"
hexmask.long 0x26C 0.--31. 1. "addrlo,MAC Address93 [31:0]"
line.long 0x270 "gmacgrp_mac_address94_high,Register 668 (MAC Address94 High Register)"
bitfld.long 0x270 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x270 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x270 0.--15. 1. "addrhi,MAC Address94 [47:32]"
line.long 0x274 "gmacgrp_mac_address94_low,Register 669 (MAC Address94 Low Register)"
hexmask.long 0x274 0.--31. 1. "addrlo,MAC Address94 [31:0]"
line.long 0x278 "gmacgrp_mac_address95_high,Register 670 (MAC Address95 High Register)"
bitfld.long 0x278 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x278 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x278 0.--15. 1. "addrhi,MAC Address95 [47:32]"
line.long 0x27C "gmacgrp_mac_address95_low,Register 671 (MAC Address95 Low Register)"
hexmask.long 0x27C 0.--31. 1. "addrlo,MAC Address95 [31:0]"
line.long 0x280 "gmacgrp_mac_address96_high,Register 672 (MAC Address96 High Register)"
bitfld.long 0x280 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x280 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x280 0.--15. 1. "addrhi,MAC Address96 [47:32]"
line.long 0x284 "gmacgrp_mac_address96_low,Register 673 (MAC Address96 Low Register)"
hexmask.long 0x284 0.--31. 1. "addrlo,MAC Address96 [31:0]"
line.long 0x288 "gmacgrp_mac_address97_high,Register 674 (MAC Address97 High Register)"
bitfld.long 0x288 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x288 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x288 0.--15. 1. "addrhi,MAC Address97 [47:32]"
line.long 0x28C "gmacgrp_mac_address97_low,Register 675 (MAC Address97 Low Register)"
hexmask.long 0x28C 0.--31. 1. "addrlo,MAC Address97 [31:0]"
line.long 0x290 "gmacgrp_mac_address98_high,Register 676 (MAC Address98 High Register)"
bitfld.long 0x290 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x290 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x290 0.--15. 1. "addrhi,MAC Address98 [47:32]"
line.long 0x294 "gmacgrp_mac_address98_low,Register 677 (MAC Address98 Low Register)"
hexmask.long 0x294 0.--31. 1. "addrlo,MAC Address98 [31:0]"
line.long 0x298 "gmacgrp_mac_address99_high,Register 678 (MAC Address99 High Register)"
bitfld.long 0x298 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x298 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x298 0.--15. 1. "addrhi,MAC Address99 [47:32]"
line.long 0x29C "gmacgrp_mac_address99_low,Register 679 (MAC Address99 Low Register)"
hexmask.long 0x29C 0.--31. 1. "addrlo,MAC Address99 [31:0]"
line.long 0x2A0 "gmacgrp_mac_address100_high,Register 680 (MAC Address100 High Register)"
bitfld.long 0x2A0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2A0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2A0 0.--15. 1. "addrhi,MAC Address100 [47:32]"
line.long 0x2A4 "gmacgrp_mac_address100_low,Register 681 (MAC Address100 Low Register)"
hexmask.long 0x2A4 0.--31. 1. "addrlo,MAC Address100 [31:0]"
line.long 0x2A8 "gmacgrp_mac_address101_high,Register 682 (MAC Address101 High Register)"
bitfld.long 0x2A8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2A8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2A8 0.--15. 1. "addrhi,MAC Address101 [47:32]"
line.long 0x2AC "gmacgrp_mac_address101_low,Register 683 (MAC Address101 Low Register)"
hexmask.long 0x2AC 0.--31. 1. "addrlo,MAC Address101 [31:0]"
line.long 0x2B0 "gmacgrp_mac_address102_high,Register 684 (MAC Address102 High Register)"
bitfld.long 0x2B0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2B0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2B0 0.--15. 1. "addrhi,MAC Address102 [47:32]"
line.long 0x2B4 "gmacgrp_mac_address102_low,Register 685 (MAC Address102 Low Register)"
hexmask.long 0x2B4 0.--31. 1. "addrlo,MAC Address102 [31:0]"
line.long 0x2B8 "gmacgrp_mac_address103_high,Register 686 (MAC Address103 High Register)"
bitfld.long 0x2B8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2B8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2B8 0.--15. 1. "addrhi,MAC Address103 [47:32]"
line.long 0x2BC "gmacgrp_mac_address103_low,Register 687 (MAC Address103 Low Register)"
hexmask.long 0x2BC 0.--31. 1. "addrlo,MAC Address103 [31:0]"
line.long 0x2C0 "gmacgrp_mac_address104_high,Register 688 (MAC Address104 High Register)"
bitfld.long 0x2C0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2C0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2C0 0.--15. 1. "addrhi,MAC Address104 [47:32]"
line.long 0x2C4 "gmacgrp_mac_address104_low,Register 689 (MAC Address104 Low Register)"
hexmask.long 0x2C4 0.--31. 1. "addrlo,MAC Address104 [31:0]"
line.long 0x2C8 "gmacgrp_mac_address105_high,Register 690 (MAC Address105 High Register)"
bitfld.long 0x2C8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2C8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2C8 0.--15. 1. "addrhi,MAC Address105 [47:32]"
line.long 0x2CC "gmacgrp_mac_address105_low,Register 691 (MAC Address105 Low Register)"
hexmask.long 0x2CC 0.--31. 1. "addrlo,MAC Address105 [31:0]"
line.long 0x2D0 "gmacgrp_mac_address106_high,Register 692 (MAC Address106 High Register)"
bitfld.long 0x2D0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2D0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2D0 0.--15. 1. "addrhi,MAC Address106 [47:32]"
line.long 0x2D4 "gmacgrp_mac_address106_low,Register 693 (MAC Address106 Low Register)"
hexmask.long 0x2D4 0.--31. 1. "addrlo,MAC Address106 [31:0]"
line.long 0x2D8 "gmacgrp_mac_address107_high,Register 694 (MAC Address107 High Register)"
bitfld.long 0x2D8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2D8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2D8 0.--15. 1. "addrhi,MAC Address107 [47:32]"
line.long 0x2DC "gmacgrp_mac_address107_low,Register 695 (MAC Address107 Low Register)"
hexmask.long 0x2DC 0.--31. 1. "addrlo,MAC Address107 [31:0]"
line.long 0x2E0 "gmacgrp_mac_address108_high,Register 696 (MAC Address108 High Register)"
bitfld.long 0x2E0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2E0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2E0 0.--15. 1. "addrhi,MAC Address108 [47:32]"
line.long 0x2E4 "gmacgrp_mac_address108_low,Register 697 (MAC Address108 Low Register)"
hexmask.long 0x2E4 0.--31. 1. "addrlo,MAC Address108 [31:0]"
line.long 0x2E8 "gmacgrp_mac_address109_high,Register 698 (MAC Address109 High Register)"
bitfld.long 0x2E8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2E8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2E8 0.--15. 1. "addrhi,MAC Address109 [47:32]"
line.long 0x2EC "gmacgrp_mac_address109_low,Register 699 (MAC Address109 Low Register)"
hexmask.long 0x2EC 0.--31. 1. "addrlo,MAC Address109 [31:0]"
line.long 0x2F0 "gmacgrp_mac_address110_high,Register XXX (MAC AddressXX High Register)"
bitfld.long 0x2F0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2F0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2F0 0.--15. 1. "addrhi,MAC Address110 [47:32]"
line.long 0x2F4 "gmacgrp_mac_address110_low,Register 700 (MAC Address110 Low Register)"
hexmask.long 0x2F4 0.--31. 1. "addrlo,MAC Address110 [31:0]"
line.long 0x2F8 "gmacgrp_mac_address111_high,Register 701 (MAC Address111 High Register)"
bitfld.long 0x2F8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2F8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2F8 0.--15. 1. "addrhi,MAC Address111 [47:32]"
line.long 0x2FC "gmacgrp_mac_address111_low,Register 702 (MAC Address111 Low Register)"
hexmask.long 0x2FC 0.--31. 1. "addrlo,MAC Address111 [31:0]"
line.long 0x300 "gmacgrp_mac_address112_high,Register 703 (MAC Address112 High Register)"
bitfld.long 0x300 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x300 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x300 0.--15. 1. "addrhi,MAC Address112 [47:32]"
line.long 0x304 "gmacgrp_mac_address112_low,Register 704 (MAC Address112 Low Register)"
hexmask.long 0x304 0.--31. 1. "addrlo,MAC Address112 [31:0]"
line.long 0x308 "gmacgrp_mac_address113_high,Register 705 (MAC Address113 High Register)"
bitfld.long 0x308 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x308 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x308 0.--15. 1. "addrhi,MAC Address113 [47:32]"
line.long 0x30C "gmacgrp_mac_address113_low,Register 706 (MAC Address113 Low Register)"
hexmask.long 0x30C 0.--31. 1. "addrlo,MAC Address113 [31:0]"
line.long 0x310 "gmacgrp_mac_address114_high,Register 707 (MAC Address114 High Register)"
bitfld.long 0x310 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x310 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x310 0.--15. 1. "addrhi,MAC Address114 [47:32]"
line.long 0x314 "gmacgrp_mac_address114_low,Register 708 (MAC Address114 Low Register)"
hexmask.long 0x314 0.--31. 1. "addrlo,MAC Address114 [31:0]"
line.long 0x318 "gmacgrp_mac_address115_high,Register 709 (MAC Address115 High Register)"
bitfld.long 0x318 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x318 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x318 0.--15. 1. "addrhi,MAC Address115 [47:32]"
line.long 0x31C "gmacgrp_mac_address115_low,Register 710 (MAC Address115 Low Register)"
hexmask.long 0x31C 0.--31. 1. "addrlo,MAC Address115 [31:0]"
line.long 0x320 "gmacgrp_mac_address116_high,Register 711 (MAC Address116 High Register)"
bitfld.long 0x320 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x320 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x320 0.--15. 1. "addrhi,MAC Address116 [47:32]"
line.long 0x324 "gmacgrp_mac_address116_low,Register 712 (MAC Address116 Low Register)"
hexmask.long 0x324 0.--31. 1. "addrlo,MAC Address116 [31:0]"
line.long 0x328 "gmacgrp_mac_address117_high,Register 713 (MAC Address117 High Register)"
bitfld.long 0x328 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x328 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x328 0.--15. 1. "addrhi,MAC Address117 [47:32]"
line.long 0x32C "gmacgrp_mac_address117_low,Register 714 (MAC Address117 Low Register)"
hexmask.long 0x32C 0.--31. 1. "addrlo,MAC Address117 [31:0]"
line.long 0x330 "gmacgrp_mac_address118_high,Register 715 (MAC Address118 High Register)"
bitfld.long 0x330 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x330 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x330 0.--15. 1. "addrhi,MAC Address118 [47:32]"
line.long 0x334 "gmacgrp_mac_address118_low,Register 716 (MAC Address118 Low Register)"
hexmask.long 0x334 0.--31. 1. "addrlo,MAC Address118 [31:0]"
line.long 0x338 "gmacgrp_mac_address119_high,Register 717 (MAC Address119 High Register)"
bitfld.long 0x338 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x338 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x338 0.--15. 1. "addrhi,MAC Address119 [47:32]"
line.long 0x33C "gmacgrp_mac_address119_low,Register 718 (MAC Address119 Low Register)"
hexmask.long 0x33C 0.--31. 1. "addrlo,MAC Address119 [31:0]"
line.long 0x340 "gmacgrp_mac_address120_high,Register 719 (MAC Address120 High Register)"
bitfld.long 0x340 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x340 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x340 0.--15. 1. "addrhi,MAC Address120 [47:32]"
line.long 0x344 "gmacgrp_mac_address120_low,Register 720 (MAC Address120 Low Register)"
hexmask.long 0x344 0.--31. 1. "addrlo,MAC Address120 [31:0]"
line.long 0x348 "gmacgrp_mac_address121_high,Register 721 (MAC Address121 High Register)"
bitfld.long 0x348 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x348 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x348 0.--15. 1. "addrhi,MAC Address121 [47:32]"
line.long 0x34C "gmacgrp_mac_address121_low,Register 722 (MAC Address121 Low Register)"
hexmask.long 0x34C 0.--31. 1. "addrlo,MAC Address121 [31:0]"
line.long 0x350 "gmacgrp_mac_address122_high,Register 723 (MAC Address122 High Register)"
bitfld.long 0x350 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x350 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x350 0.--15. 1. "addrhi,MAC Address122 [47:32]"
line.long 0x354 "gmacgrp_mac_address122_low,Register 724 (MAC Address122 Low Register)"
hexmask.long 0x354 0.--31. 1. "addrlo,MAC Address122 [31:0]"
line.long 0x358 "gmacgrp_mac_address123_high,Register 725 (MAC Address123 High Register)"
bitfld.long 0x358 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x358 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x358 0.--15. 1. "addrhi,MAC Address123 [47:32]"
line.long 0x35C "gmacgrp_mac_address123_low,Register 726 (MAC AddressXX 123 Register)"
hexmask.long 0x35C 0.--31. 1. "addrlo,MAC Address123 [31:0]"
line.long 0x360 "gmacgrp_mac_address124_high,Register 727 (MAC Address124 High Register)"
bitfld.long 0x360 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x360 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x360 0.--15. 1. "addrhi,MAC Address124 [47:32]"
line.long 0x364 "gmacgrp_mac_address124_low,Register 728 (MAC Address124 Low Register)"
hexmask.long 0x364 0.--31. 1. "addrlo,MAC Address124 [31:0]"
line.long 0x368 "gmacgrp_mac_address125_high,Register 729 (MAC Address125 High Register)"
bitfld.long 0x368 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x368 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x368 0.--15. 1. "addrhi,MAC Address125 [47:32]"
line.long 0x36C "gmacgrp_mac_address125_low,Register 730 (MAC Address125 Low Register)"
hexmask.long 0x36C 0.--31. 1. "addrlo,MAC Address125 [31:0]"
line.long 0x370 "gmacgrp_mac_address126_high,Register 731 (MAC Address126 High Register)"
bitfld.long 0x370 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x370 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x370 0.--15. 1. "addrhi,MAC Address126 [47:32]"
line.long 0x374 "gmacgrp_mac_address126_low,Register 732 (MAC Address126 Low Register)"
hexmask.long 0x374 0.--31. 1. "addrlo,MAC Address126 [31:0]"
line.long 0x378 "gmacgrp_mac_address127_high,Register 733 (MAC Address127 High Register)"
bitfld.long 0x378 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x378 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x378 0.--15. 1. "addrhi,MAC Address127 [47:32]"
line.long 0x37C "gmacgrp_mac_address127_low,Register 734 (MAC Address127 Low Register)"
hexmask.long 0x37C 0.--31. 1. "addrlo,MAC Address127 [31:0]"
group.long 0x1000++0x1F
line.long 0x0 "dmagrp_bus_mode,Register 0 (Bus Mode Register)"
bitfld.long 0x0 31. "rib,Rebuild INCRx Burst" "0,1"
newline
rbitfld.long 0x0 30. "reserved_30,Reserved" "0,1"
newline
bitfld.long 0x0 28.--29. "prwg,Channel Priority Weights" "0: The priority weight is 1,1: The priority weight is 2,?,?"
newline
bitfld.long 0x0 27. "txpr,Transmit Priority" "0,1"
newline
bitfld.long 0x0 26. "mb,Mixed Burst" "0,1"
newline
bitfld.long 0x0 25. "aal,Address Aligned Beats" "0,1"
newline
bitfld.long 0x0 24. "eightxpbl,PBLx8 Mode" "0,1"
newline
bitfld.long 0x0 23. "usp,Use Seperate PBL" "0,1"
newline
hexmask.long.byte 0x0 17.--22. 1. "rpbl,Rx DMA PBL"
newline
bitfld.long 0x0 16. "fb,Fixed Burst" "0,1"
newline
bitfld.long 0x0 14.--15. "pr,Priority Ratio" "0: The Priority Ratio is,1: The Priority Ratio is,2: 1,3: 1"
newline
hexmask.long.byte 0x0 8.--13. 1. "pbl,Programmable Burst Length"
newline
bitfld.long 0x0 7. "atds,Alternate Descriptor Size" "0,1"
newline
hexmask.long.byte 0x0 2.--6. 1. "dsl,Descriptor Skip Length"
newline
bitfld.long 0x0 1. "da,DMA Arbitration Scheme" "0: Weighted round-robin with Rx:Tx or Tx:Rx,1: Fixed priority"
newline
bitfld.long 0x0 0. "swr,Software Reset" "0,1"
line.long 0x4 "dmagrp_transmit_poll_demand,Register 1 (Transmit Poll Demand Register)"
hexmask.long 0x4 0.--31. 1. "tpd,Transmit Poll Demand"
line.long 0x8 "dmagrp_receive_poll_demand,Register 2 (Receive Poll Demand Register)"
hexmask.long 0x8 0.--31. 1. "rpd,Receive Poll Demand"
line.long 0xC "dmagrp_receive_descriptor_list_address,Register 3 (Receive Descriptor List Address Register)"
hexmask.long 0xC 2.--31. 1. "rdesla_32bit,This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB bits (1:0) are ignored (32-bit wide bus) and internally taken as all-zero by the DMA. Therefore  these LSB bits are read-only (RO)."
line.long 0x10 "dmagrp_transmit_descriptor_list_address,Register 4 (Transmit Descriptor List Address Register)"
hexmask.long 0x10 2.--31. 1. "tdesla_32bit,This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (1:0) are ignored (32-bit wide bus) and are internally taken as all-zero by the DMA. Therefore  these LSB bits are read-only (RO)."
line.long 0x14 "dmagrp_status,Register 5 (Status Register)"
rbitfld.long 0x14 31. "reserved_31,Reserved" "0,1"
newline
rbitfld.long 0x14 30. "glpii,GMAC LPI Interrupt (for Channel 0)" "0,1"
newline
rbitfld.long 0x14 29. "tti,Timestamp Trigger Interrupt" "0,1"
newline
rbitfld.long 0x14 28. "gpi,GMAC PMT Interrupt" "0,1"
newline
rbitfld.long 0x14 27. "gmi,GMAC MMC Interrupt" "0,1"
newline
rbitfld.long 0x14 26. "gli,GMAC Line interface Interrupt" "0,1"
newline
rbitfld.long 0x14 23.--25. "eb,Error Bits" "0: Error during Rx DMA Descriptor Read Access,1: Error during Tx DMA Descriptor Read Access,?,?,?,?,?,?"
newline
rbitfld.long 0x14 20.--22. "ts,Transmit Process State" "0: Stopped,1: Running,2: Running,3: Running,4: TIME_STAMP write state,5: Reserved for future use,6: Suspended,7: Running"
newline
rbitfld.long 0x14 17.--19. "rs,Received Process State" "0: Stopped: Reset or Stop Receive Command issued,1: Running: Fetching Receive Transfer Descriptor,2: Reserved for future use,3: Running: Waiting for receive packet,4: Suspended: Receive Descriptor Unavailable,5: Running: Closing Receive Descriptor,6: TIME_STAMP write state,7: Running: Transferring the receive packet data.."
newline
bitfld.long 0x14 16. "nis,Normal Interrupt Summary" "0,1"
newline
bitfld.long 0x14 15. "ais,Abnormal Interrupt Summary" "0,1"
newline
bitfld.long 0x14 14. "eri,Early Receive Interrupt" "0,1"
newline
bitfld.long 0x14 13. "fbi,Fatal Bus Error Interrupt" "0,1"
newline
rbitfld.long 0x14 11.--12. "reserved_12_11,Reserved" "0,1,2,3"
newline
bitfld.long 0x14 10. "eti,Early Transmit Interrupt" "0,1"
newline
bitfld.long 0x14 9. "rwt,Receive Watchdog Timeout" "0,1"
newline
bitfld.long 0x14 8. "rps,Receive Process Stopped" "0,1"
newline
bitfld.long 0x14 7. "ru,Receive Buffer Unavailable" "0,1"
newline
bitfld.long 0x14 6. "ri,Receive Interrupt" "0,1"
newline
bitfld.long 0x14 5. "unf,Transmit Underflow" "0,1"
newline
bitfld.long 0x14 4. "ovf,Receive Overflow" "0,1"
newline
bitfld.long 0x14 3. "tjt,Transmit Jabber Timeout" "0,1"
newline
bitfld.long 0x14 2. "tu,Transmit Buffer Unavailable" "0,1"
newline
bitfld.long 0x14 1. "tps,Transmit Process Stopped" "0,1"
newline
bitfld.long 0x14 0. "ti,Transmit Interrupt" "0,1"
line.long 0x18 "dmagrp_operation_mode,Register 6 (Operation Mode Register)"
hexmask.long.byte 0x18 27.--31. 1. "reserved_31_27,Reserved"
newline
bitfld.long 0x18 26. "dt,Disable Dropping of TCP/IP Checksum Error Frames" "0,1"
newline
bitfld.long 0x18 25. "rsf,Receive Store and Forward" "0,1"
newline
bitfld.long 0x18 24. "dff,Disable Flushing of Received Frames" "0,1"
newline
rbitfld.long 0x18 23. "rfa_2,MSB of Threshold for Activating Flow Control" "0,1"
newline
rbitfld.long 0x18 22. "rfd_2,MSB of Threshold for Deactivating Flow Control" "0,1"
newline
bitfld.long 0x18 21. "tsf,Transmit Store and Forward" "0,1"
newline
bitfld.long 0x18 20. "ftf,Flush Transmit FIFO" "0,1"
newline
rbitfld.long 0x18 17.--19. "reserved_19_17,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 14.--16. "ttc,Transmit Threshold Control" "0: 64,1: 128,?,?,?,?,?,?"
newline
bitfld.long 0x18 13. "st,Start or Stop Transmission Command" "0,1"
newline
rbitfld.long 0x18 11.--12. "rfd,Threshold for Deactivating Flow Control (in half-duplex and full-duplex)" "0: Full minus 1 KB,1: Full minus 2 KB,?,?"
newline
rbitfld.long 0x18 9.--10. "rfa,Threshold for Activating Flow Control (in half-duplex and full-duplex)" "0: Full minus 1 KB,1: Full minus 2 KB,?,?"
newline
rbitfld.long 0x18 8. "efc,Reserved" "0,1"
newline
bitfld.long 0x18 7. "fef,Forward Error Frames" "0,1"
newline
bitfld.long 0x18 6. "fuf,Forward Undersized Good Frames" "0,1"
newline
bitfld.long 0x18 5. "dgf,Drop Giant Frames" "0,1"
newline
bitfld.long 0x18 3.--4. "rtc,Receive Threshold Control" "0: 64,1: 32,?,?"
newline
bitfld.long 0x18 2. "osf,Operate on Second Frame" "0,1"
newline
bitfld.long 0x18 1. "sr,Start or Stop Receive" "0,1"
newline
rbitfld.long 0x18 0. "reserved_0,Reserved" "0,1"
line.long 0x1C "dmagrp_interrupt_enable,Register 7 (Interrupt Enable Register)"
hexmask.long.word 0x1C 17.--31. 1. "reserved_31_17,Reserved"
newline
bitfld.long 0x1C 16. "nie,Normal Interrupt Summary Enable" "0,1"
newline
bitfld.long 0x1C 15. "aie,Abnormal Interrupt Summary Enable" "0,1"
newline
bitfld.long 0x1C 14. "ere,Early Receive Interrupt Enable" "0,1"
newline
bitfld.long 0x1C 13. "fbe,Fatal Bus Error Enable" "0,1"
newline
rbitfld.long 0x1C 11.--12. "reserved_12_11,Reserved" "0,1,2,3"
newline
bitfld.long 0x1C 10. "ete,Early Transmit Interrupt Enable" "0,1"
newline
bitfld.long 0x1C 9. "rwe,Receive Watchdog Timeout Enable" "0,1"
newline
bitfld.long 0x1C 8. "rse,Receive Stopped Enable" "0,1"
newline
bitfld.long 0x1C 7. "rue,Receive Buffer Unavailable Enable" "0,1"
newline
bitfld.long 0x1C 6. "rie,Receive Interrupt Enable" "0,1"
newline
bitfld.long 0x1C 5. "une,Underflow Interrupt Enable" "0,1"
newline
bitfld.long 0x1C 4. "ove,Overflow Interrupt Enable" "0,1"
newline
bitfld.long 0x1C 3. "tje,Transmit Jabber Timeout Enable" "0,1"
newline
bitfld.long 0x1C 2. "tue,Transmit Buffer Unavailable Enable" "0,1"
newline
bitfld.long 0x1C 1. "tse,Transmit Stopped Enable" "0,1"
newline
bitfld.long 0x1C 0. "tie,Transmit Interrupt Enable" "0,1"
rgroup.long 0x1020++0x3
line.long 0x0 "dmagrp_missed_frame_and_buffer_overflow_counter,Register 8 (Missed Frame and Buffer Overflow Counter Register)"
bitfld.long 0x0 29.--31. "reserved_31_29,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 28. "ovfcntovf,Overflow Bit for FIFO Overflow Counter" "0,1"
newline
hexmask.long.word 0x0 17.--27. 1. "ovffrmcnt,Overflow Frame Counter"
newline
bitfld.long 0x0 16. "miscntovf,Overflow Bit for Missed Frame Counter" "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "misfrmcnt,Missed Frame Counter"
group.long 0x1024++0x7
line.long 0x0 "dmagrp_receive_interrupt_watchdog_timer,Register 9 (Receive Interrupt Watchdog Timer Register)"
hexmask.long.tbyte 0x0 8.--31. 1. "reserved_31_8,Reserved"
newline
hexmask.long.byte 0x0 0.--7. 1. "riwt,RI Watchdog Timer Count"
line.long 0x4 "dmagrp_axi_bus_mode,The AXI Bus Mode Register controls the behavior of the AXI master. It is mainly used to control the burst splitting and the number of outstanding requests."
bitfld.long 0x4 31. "en_lpi,When set to 1  this bit enables the LPI mode supported by the AXI master and accepts the LPI request from the AXI System Clock controller." "0,1"
newline
bitfld.long 0x4 30. "lpi_xit_frm,When set to 1  this bit enables the GMAC-AXI to come out of the LPI mode only when the Magic Packet or Remote Wake Up Packet is received." "0,1"
newline
hexmask.long.byte 0x4 20.--23. 1. "wr_osr_lmt,AXI Maximum Write OutStanding Request Limit"
newline
hexmask.long.byte 0x4 16.--19. 1. "rd_osr_lmt,This value limits the maximum outstanding request on the AXI read interface."
newline
bitfld.long 0x4 13. "onekbbe,1 KB Boundary Crossing Enable for the GMAC-AXI Master" "0,1"
newline
rbitfld.long 0x4 12. "axi_aal,This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register)." "0,1"
newline
bitfld.long 0x4 3. "blen16,When this bit is set to 1 or UNDEFINED is set to 1  the GMAC-AXI is allowed to select a burst length of 16 on the AXI Master interface." "0,1"
newline
bitfld.long 0x4 2. "blen8,When this bit is set to 1  the GMAC-AXI is allowed to select a burst length of 8 on the AXI Master interface." "0,1"
newline
bitfld.long 0x4 1. "blen4,When this bit is set to 1  the GMAC-AXI is allowed to select a burst length of 4 on the AXI Master interface." "0,1"
newline
rbitfld.long 0x4 0. "undefined,This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register[16])." "0,1"
rgroup.long 0x102C++0x3
line.long 0x0 "dmagrp_ahb_or_axi_status,Register 11 (AHB or AXI Status Register)"
hexmask.long 0x0 2.--31. 1. "reserved_31_2,Reserved"
newline
bitfld.long 0x0 1. "axirdsts,AXI Master Read Channel Status" "0,1"
newline
bitfld.long 0x0 0. "axwhsts,AXI Master Write Channel or AHB Master Status" "0,1"
rgroup.long 0x1048++0x13
line.long 0x0 "dmagrp_current_host_transmit_descriptor,Register 18 (Current Host Transmit Descriptor Register)"
hexmask.long 0x0 0.--31. 1. "curtdesaptr,Host Transmit Descriptor Address Pointer"
line.long 0x4 "dmagrp_current_host_receive_descriptor,Register 19 (Current Host Receive Descriptor Register)"
hexmask.long 0x4 0.--31. 1. "currdesaptr,Host Receive Descriptor Address Pointer"
line.long 0x8 "dmagrp_current_host_transmit_buffer_address,Register 20 (Current Host Transmit Buffer Address Register)"
hexmask.long 0x8 0.--31. 1. "curtbufaptr,Host Transmit Buffer Address Pointer"
line.long 0xC "dmagrp_current_host_receive_buffer_address,Register 21 (Current Host Receive Buffer Address Register)"
hexmask.long 0xC 0.--31. 1. "currbufaptr,Host Receive Buffer Address Pointer"
line.long 0x10 "dmagrp_hw_feature,Register 22 (HW Feature Register)"
bitfld.long 0x10 31. "reserved_31,Reserved" "0,1"
newline
bitfld.long 0x10 28.--30. "actphyif,Active or Selected PHY interface" "0: GMII or MII,1: RGMII,?,?,?,?,?,?"
newline
bitfld.long 0x10 27. "SAVLANINS,Source Address or VLAN Insertion" "0,1"
newline
bitfld.long 0x10 26. "FLEXIPPSEN,Flexible Pulse-Per-Second Output" "0,1"
newline
bitfld.long 0x10 25. "INTTSEN,Timestamping with Internal System Time" "0,1"
newline
bitfld.long 0x10 24. "enhdessel,Alternate (Enhanced Descriptor)" "0,1"
newline
bitfld.long 0x10 22.--23. "txchcnt,Number of additional Tx channels" "0,1,2,3"
newline
bitfld.long 0x10 20.--21. "rxchcnt,Number of additional Rx channels" "0,1,2,3"
newline
bitfld.long 0x10 19. "rxfifosize,Rx FIFO > 2 048 Bytes" "0,1"
newline
bitfld.long 0x10 18. "rxtyp2coe,IP Checksum Offload (Type 2) in Rx" "0,1"
newline
bitfld.long 0x10 17. "rxtyp1coe,IP Checksum Offload (Type 1) in Rx" "0,1"
newline
bitfld.long 0x10 16. "txoesel,Checksum Offload in Tx" "0,1"
newline
bitfld.long 0x10 15. "avsel,AV Feature" "0,1"
newline
bitfld.long 0x10 14. "eeesel,Energy Efficient Ethernet" "0,1"
newline
bitfld.long 0x10 13. "tsver2sel,IEEE 1588-2008 Advanced Timestamp" "0,1"
newline
bitfld.long 0x10 12. "tsver1sel,Only IEEE 1588-2002 Timestamp" "0,1"
newline
bitfld.long 0x10 11. "mmcsel,RMON Module" "0,1"
newline
bitfld.long 0x10 10. "mgksel,PMT Magic Packet" "0,1"
newline
bitfld.long 0x10 9. "rwksel,PMT Remote Wakeup" "0,1"
newline
bitfld.long 0x10 8. "smasel,SMA (MDIO) Interface" "0,1"
newline
bitfld.long 0x10 7. "l3l4fltren,Layer 3 and Layer 4 Filter Feature" "0,1"
newline
bitfld.long 0x10 6. "pcssel,PCS registers (TBI  SGMII  or RTBI PHY interface)" "0,1"
newline
bitfld.long 0x10 5. "addmacadrsel,Multiple MAC Address Registers" "0,1"
newline
bitfld.long 0x10 4. "hashsel,HASH Filter" "0,1"
newline
bitfld.long 0x10 3. "exthashen,Expanded DA Hash Filter" "0,1"
newline
bitfld.long 0x10 2. "hdsel,Half-Duplex support" "0,1"
newline
bitfld.long 0x10 1. "gmiisel,1000 Mbps support" "0,1"
newline
bitfld.long 0x10 0. "miisel,10 or 100 Mbps support" "0,1"
tree.end
tree "EMAC1 (EMAC1 Module)"
base ad:0xFF802000
group.long 0x0++0x7
line.long 0x0 "gmacgrp_mac_configuration,Register 0 (MAC Configuration Register)"
rbitfld.long 0x0 31. "reserved_31,Reserved" "0,1"
newline
bitfld.long 0x0 28.--30. "sarc,Source Address Insertion or Replacement Control" "?,?,2: ,3: ,?,?,?,?"
newline
bitfld.long 0x0 27. "twokpe,IEEE 802.3as Support for 2K Packets" "0,1"
newline
rbitfld.long 0x0 26. "sfterr,SMII Force Transmit Error" "0,1"
newline
bitfld.long 0x0 25. "cst,CRC Stripping for Type Frames" "0,1"
newline
rbitfld.long 0x0 24. "tc,Transmit Configuration in RGMII  SGMII  or SMII" "0,1"
newline
bitfld.long 0x0 23. "wd,Watchdog Disable" "0,1"
newline
bitfld.long 0x0 22. "jd,Jabber Disable" "0,1"
newline
bitfld.long 0x0 21. "be,Frame Burst Enable" "0,1"
newline
bitfld.long 0x0 20. "je,Jumbo Frame Enable" "0,1"
newline
bitfld.long 0x0 17.--19. "ifg,Inter-Frame Gap" "0: 96 bit times,1: 88 bit times,?,?,?,?,?,?"
newline
bitfld.long 0x0 16. "dcrs,Disable Carrier Sense During Transmission" "0,1"
newline
bitfld.long 0x0 15. "ps,Port Select" "0: For 1000 Mbps operations,1: For 10 or 100 Mbps operations"
newline
bitfld.long 0x0 14. "fes,Speed" "0: 10 Mbps,1: 100 Mbps"
newline
bitfld.long 0x0 13. "do,Disable Receive Own" "0,1"
newline
bitfld.long 0x0 12. "lm,Loopback Mode" "0,1"
newline
bitfld.long 0x0 11. "dm,Duplex Mode" "0,1"
newline
bitfld.long 0x0 10. "ipc,Checksum Offload" "0,1"
newline
bitfld.long 0x0 9. "dr,Disable Retry" "0,1"
newline
rbitfld.long 0x0 8. "lud,Link Up or Down" "0: Link Down,1: Link Up"
newline
bitfld.long 0x0 7. "acs,Automatic Pad or CRC Stripping" "0,1"
newline
bitfld.long 0x0 5.--6. "bl,Back-Off Limit" "0: k = min,1: k = min,?,?"
newline
bitfld.long 0x0 4. "dc,Deferral Check" "0,1"
newline
bitfld.long 0x0 3. "te,Transmitter Enable" "0,1"
newline
bitfld.long 0x0 2. "re,Receiver Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "prelen,Preamble Length for Transmit Frames" "0: 7 bytes of preamble,1: 5 byte of preamble,2: 3 bytes of preamble,3: 1 byte of preamble"
line.long 0x4 "gmacgrp_mac_frame_filter,Register 1 (MAC Frame Filter)"
bitfld.long 0x4 31. "ra,Receive All" "0,1"
newline
hexmask.long.word 0x4 22.--30. 1. "reserved_30_22,Reserved"
newline
bitfld.long 0x4 21. "dntu,Drop non-TCP/UDP over IP Frames" "0,1"
newline
bitfld.long 0x4 20. "ipfe,Layer 3 and Layer 4 Filter Enable" "0,1"
newline
rbitfld.long 0x4 17.--19. "reserved_19_17,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 16. "vtfe,VLAN Tag Filter Enable" "0,1"
newline
hexmask.long.byte 0x4 11.--15. 1. "reserved_15_11,Reserved"
newline
rbitfld.long 0x4 10. "hpf,Hash or Perfect Filter" "0,1"
newline
bitfld.long 0x4 9. "saf,Source Address Filter Enable" "0,1"
newline
bitfld.long 0x4 8. "saif,SA Inverse Filtering" "0,1"
newline
bitfld.long 0x4 6.--7. "pcf,Pass Control Frames" "0: MAC filters all control frames from reaching the..,1: The MAC is in the full-duplex mode and flow..,2: The destination address,3: The Type field of the received frame is 0x8808.."
newline
bitfld.long 0x4 5. "dbf,Disable Broadcast Frames" "0,1"
newline
bitfld.long 0x4 4. "pm,Pass All Multicast" "0,1"
newline
bitfld.long 0x4 3. "daif,DA Inverse Filtering" "0,1"
newline
rbitfld.long 0x4 2. "hmc,Hash Multicast" "0,1"
newline
rbitfld.long 0x4 1. "huc,Hash Unicast" "0,1"
newline
bitfld.long 0x4 0. "pr,Promiscuous Mode" "0,1"
group.long 0x10++0xF
line.long 0x0 "gmacgrp_gmii_address,Register 4 (GMII Address Register)"
hexmask.long.word 0x0 16.--31. 1. "reserved_31_16,Reserved"
newline
hexmask.long.byte 0x0 11.--15. 1. "pa,Physical Layer Address"
newline
hexmask.long.byte 0x0 6.--10. 1. "gr,GMII Register"
newline
hexmask.long.byte 0x0 2.--5. 1. "cr,CSR Clock Range"
newline
bitfld.long 0x0 1. "gw,GMII Write" "0,1"
newline
bitfld.long 0x0 0. "gb,GMII Busy" "0,1"
line.long 0x4 "gmacgrp_gmii_data,Register 5 (GMII Data Register)"
hexmask.long.word 0x4 16.--31. 1. "reserved_31_16,Reserved"
newline
hexmask.long.word 0x4 0.--15. 1. "gd,GMII Data"
line.long 0x8 "gmacgrp_flow_control,Register 6 (Flow Control Register)"
hexmask.long.word 0x8 16.--31. 1. "pt,Pause Time"
newline
hexmask.long.byte 0x8 8.--15. 1. "reserved_15_8,Reserved"
newline
bitfld.long 0x8 7. "dzpq,Disable Zero-Quanta Pause" "0,1"
newline
rbitfld.long 0x8 6. "reserved_6,Reserved" "0,1"
newline
bitfld.long 0x8 4.--5. "plt,Pause Low Threshold" "0: The threshold is Pause time minus 4 slot times,1: The threshold is Pause time minus 28 slot times,?,?"
newline
bitfld.long 0x8 3. "up,Unicast Pause Frame Detect" "0,1"
newline
bitfld.long 0x8 2. "rfe,Receive Flow Control Enable" "0,1"
newline
bitfld.long 0x8 1. "tfe,Transmit Flow Control Enable" "0,1"
newline
bitfld.long 0x8 0. "fca_bpa,Flow Control Busy or Backpressure Activate" "0,1"
line.long 0xC "gmacgrp_vlan_tag,Register 7 (VLAN Tag Register)"
hexmask.long.word 0xC 20.--31. 1. "reserved_31_20,Reserved"
newline
rbitfld.long 0xC 19. "vthm,VLAN Tag Hash Table Match Enable" "0,1"
newline
bitfld.long 0xC 18. "esvl,Enable S-VLAN" "0,1"
newline
bitfld.long 0xC 17. "vtim,VLAN Tag Inverse Match Enable" "0,1"
newline
bitfld.long 0xC 16. "etv,Enable 12-Bit VLAN Tag Comparison" "0,1"
newline
hexmask.long.word 0xC 0.--15. 1. "vl,VLAN Tag Identifier for Receive Frames"
rgroup.long 0x20++0x7
line.long 0x0 "gmacgrp_version,Register 8 (Version Register)"
hexmask.long.word 0x0 16.--31. 1. "reserved_31_16,Reserved"
newline
hexmask.long.byte 0x0 8.--15. 1. "userver,User-defined Version (Configured with the coreConsultant)"
newline
hexmask.long.byte 0x0 0.--7. 1. "snpsver,Synopsys-defined Version (3.7)"
line.long 0x4 "gmacgrp_debug,Register 9 (Debug Register)"
hexmask.long.byte 0x4 26.--31. 1. "reserved_31_26,Reserved"
newline
bitfld.long 0x4 25. "txstsfsts,MTL TxStatus FIFO Full Status" "0,1"
newline
bitfld.long 0x4 24. "txfsts,MTL Tx FIFO Not Empty Status" "0,1"
newline
bitfld.long 0x4 23. "reserved_23,Reserved" "0,1"
newline
bitfld.long 0x4 22. "twcsts,MTL Tx FIFO Write Controller Active Status" "0,1"
newline
bitfld.long 0x4 20.--21. "trcsts,MTL Tx FIFO Read Controller Status" "0: IDLE state,1: READ state,?,?"
newline
bitfld.long 0x4 19. "txpaused,MAC transmitter in PAUSE" "0,1"
newline
bitfld.long 0x4 17.--18. "tfcsts,MAC Transmit Frame Controller Status" "0: IDLE state,1: Waiting for Status of previous frame or IFG or..,?,?"
newline
bitfld.long 0x4 16. "tpests,MAC GMII or MII Transmit Protocol Engine Status" "0,1"
newline
hexmask.long.byte 0x4 10.--15. 1. "reserved_15_10,Reserved"
newline
bitfld.long 0x4 8.--9. "rxfsts,MTL Rx FIFO Fill-level Status" "0: Rx FIFO Empty,1: Rx FIFO fill level is below the flow-control..,?,?"
newline
bitfld.long 0x4 7. "reserved_7,Reserved" "0,1"
newline
bitfld.long 0x4 5.--6. "rrcsts,MTL Rx FIFO Read Controller State" "0: IDLE state,1: Reading frame data,?,?"
newline
bitfld.long 0x4 4. "rwcsts,MTL Rx FIFO Write Controller Active Status" "0,1"
newline
bitfld.long 0x4 3. "reserved_3,Reserved" "0,1"
newline
bitfld.long 0x4 1.--2. "rfcfcsts,MAC Receive Frame Controller FIFO Status" "0,1,2,3"
newline
bitfld.long 0x4 0. "rpests,MAC GMII or MII Receive Protocol Engine Status" "0,1"
group.long 0x30++0x7
line.long 0x0 "gmacgrp_lpi_control_status,Register 12 (LPI Control and Status Register)"
hexmask.long.word 0x0 20.--31. 1. "reserved_31_20,Reserved"
newline
bitfld.long 0x0 19. "lpitxa,LPI TX Automate" "0,1"
newline
rbitfld.long 0x0 18. "plsen,PHY Link Status Enable" "0,1"
newline
bitfld.long 0x0 17. "pls,PHY Link Status" "0,1"
newline
bitfld.long 0x0 16. "lpien,LPI Enable" "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "reserved_15_10,Reserved"
newline
rbitfld.long 0x0 9. "rlpist,Receive LPI State" "0,1"
newline
rbitfld.long 0x0 8. "tlpist,Transmit LPI State" "0,1"
newline
hexmask.long.byte 0x0 4.--7. 1. "reserved_7_4,Reserved"
newline
rbitfld.long 0x0 3. "rlpiex,Receive LPI Exit" "0,1"
newline
rbitfld.long 0x0 2. "rlpien,Receive LPI Entry" "0,1"
newline
rbitfld.long 0x0 1. "tlpiex,Transmit LPI Exit" "0,1"
newline
rbitfld.long 0x0 0. "tlpien,Transmit LPI Entry" "0,1"
line.long 0x4 "gmacgrp_lpi_timers_control,Register 13 (LPI Timers Control Register)"
hexmask.long.byte 0x4 26.--31. 1. "reserved_31_26,Reserved"
newline
hexmask.long.word 0x4 16.--25. 1. "lst,LPI LS Timer"
newline
hexmask.long.word 0x4 0.--15. 1. "twt,LPI TW Timer"
rgroup.long 0x38++0x3
line.long 0x0 "gmacgrp_interrupt_status,Register 14 (Interrupt Register)"
hexmask.long.tbyte 0x0 12.--31. 1. "reserved_31_12,Reserved"
newline
bitfld.long 0x0 11. "gpiis,GPI Interrupt Status" "0,1"
newline
bitfld.long 0x0 10. "lpiis,LPI Interrupt Status" "0,1"
newline
bitfld.long 0x0 9. "tsis,Timestamp Interrupt Status" "0,1"
newline
bitfld.long 0x0 8. "reserved_8,Reserved" "0,1"
newline
bitfld.long 0x0 7. "mmcrxipis,MMC Receive Checksum Offload Interrupt Status" "0,1"
newline
bitfld.long 0x0 6. "mmctxis,MMC Transmit Interrupt Status" "0,1"
newline
bitfld.long 0x0 5. "mmcrxis,MMC Receive Interrupt Status" "0,1"
newline
bitfld.long 0x0 4. "mmcis,MMC Interrupt Status" "0,1"
newline
bitfld.long 0x0 3. "pmtis,PMT Interrupt Status" "0,1"
newline
bitfld.long 0x0 2. "pcsancis,PCS Auto-Negotiation Complete" "0,1"
newline
bitfld.long 0x0 1. "pcslchgis,PCS Link Status Changed" "0,1"
newline
bitfld.long 0x0 0. "rgsmiiis,RGMII or SMII Interrupt Status" "0,1"
group.long 0x3C++0x83
line.long 0x0 "gmacgrp_interrupt_mask,Register 15 (Interrupt Mask Register)"
hexmask.long.tbyte 0x0 11.--31. 1. "reserved_31_11,Reserved"
newline
bitfld.long 0x0 10. "lpiim,LPI Interrupt Mask" "0,1"
newline
rbitfld.long 0x0 9. "tsim,Timestamp Interrupt Mask" "0,1"
newline
hexmask.long.byte 0x0 4.--8. 1. "reserved_8_4,Reserved"
newline
bitfld.long 0x0 3. "pmtim,PMT Interrupt Mask" "0,1"
newline
rbitfld.long 0x0 2. "pcsancim,PCS AN Completion Interrupt Mask" "0,1"
newline
rbitfld.long 0x0 1. "pcslchgim,PCS Link Status Interrupt Mask" "0,1"
newline
rbitfld.long 0x0 0. "rgsmiiim,RGMII or SMII Interrupt Mask" "0,1"
line.long 0x4 "gmacgrp_mac_address0_high,Register 16 (MAC Address0 High Register)"
rbitfld.long 0x4 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x4 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x4 0.--15. 1. "addrhi,MAC Address0 [47:32]"
line.long 0x8 "gmacgrp_mac_address0_low,Register 17 (MAC Address0 Low Register)"
hexmask.long 0x8 0.--31. 1. "addrlo,MAC Address0 [31:0]"
line.long 0xC "gmacgrp_mac_address1_high,Register 18 (MAC Address1 High Register)"
bitfld.long 0xC 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0xC 30. "sa,Source Address" "0,1"
newline
bitfld.long 0xC 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0xC 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0xC 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0xC 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0xC 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0xC 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0xC 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0xC 0.--15. 1. "addrhi,MAC Address1 [47:32]"
line.long 0x10 "gmacgrp_mac_address1_low,Register 19 (MAC Address1 Low Register)"
hexmask.long 0x10 0.--31. 1. "addrlo,MAC Address1 [31:0]"
line.long 0x14 "gmacgrp_mac_address2_high,Register 20 (MAC Address2 High Register)"
bitfld.long 0x14 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x14 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x14 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x14 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x14 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x14 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x14 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x14 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x14 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x14 0.--15. 1. "addrhi,MAC Address2 [47:32]"
line.long 0x18 "gmacgrp_mac_address2_low,Register 21 (MAC Address2 Low Register)"
hexmask.long 0x18 0.--31. 1. "addrlo,MAC Address2 [31:0]"
line.long 0x1C "gmacgrp_mac_address3_high,Register 22 (MAC Address3 High Register)"
bitfld.long 0x1C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x1C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x1C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x1C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x1C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x1C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x1C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x1C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x1C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x1C 0.--15. 1. "addrhi,MAC Address3 [47:32]"
line.long 0x20 "gmacgrp_mac_address3_low,Register 23 (MAC Address3 Low Register)"
hexmask.long 0x20 0.--31. 1. "addrlo,MAC Address3 [31:0]"
line.long 0x24 "gmacgrp_mac_address4_high,Register 24 (MAC Address4 High Register)"
bitfld.long 0x24 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x24 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x24 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x24 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x24 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x24 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x24 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x24 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x24 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x24 0.--15. 1. "addrhi,MAC Address4 [47:32]"
line.long 0x28 "gmacgrp_mac_address4_low,Register 25 (MAC Address4 Low Register)"
hexmask.long 0x28 0.--31. 1. "addrlo,MAC Address4 [31:0]"
line.long 0x2C "gmacgrp_mac_address5_high,Register 26 (MAC Address5 High Register)"
bitfld.long 0x2C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x2C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x2C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x2C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x2C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x2C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x2C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x2C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x2C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x2C 0.--15. 1. "addrhi,MAC Address5 [47:32]"
line.long 0x30 "gmacgrp_mac_address5_low,Register 27 (MAC Address5 Low Register)"
hexmask.long 0x30 0.--31. 1. "addrlo,MAC Address5 [31:0]"
line.long 0x34 "gmacgrp_mac_address6_high,Register 28 (MAC Address6 High Register)"
bitfld.long 0x34 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x34 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x34 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x34 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x34 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x34 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x34 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x34 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x34 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x34 0.--15. 1. "addrhi,MAC Address6 [47:32]"
line.long 0x38 "gmacgrp_mac_address6_low,Register 29 (MAC Address6 Low Register)"
hexmask.long 0x38 0.--31. 1. "addrlo,MAC Address6 [31:0]"
line.long 0x3C "gmacgrp_mac_address7_high,Register 30 (MAC Address7 High Register)"
bitfld.long 0x3C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x3C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x3C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x3C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x3C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x3C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x3C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x3C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x3C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x3C 0.--15. 1. "addrhi,MAC Address7 [47:32]"
line.long 0x40 "gmacgrp_mac_address7_low,Register 31 (MAC Address7 Low Register)"
hexmask.long 0x40 0.--31. 1. "addrlo,MAC Address7 [31:0]"
line.long 0x44 "gmacgrp_mac_address8_high,Register 32 (MAC Address8 High Register)"
bitfld.long 0x44 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x44 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x44 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x44 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x44 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x44 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x44 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x44 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x44 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x44 0.--15. 1. "addrhi,MAC Address8 [47:32]"
line.long 0x48 "gmacgrp_mac_address8_low,Register 33 (MAC Address8 Low Register)"
hexmask.long 0x48 0.--31. 1. "addrlo,MAC Address8 [31:0]"
line.long 0x4C "gmacgrp_mac_address9_high,Register 34 (MAC Address9 High Register)"
bitfld.long 0x4C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x4C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x4C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x4C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x4C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x4C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x4C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x4C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x4C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x4C 0.--15. 1. "addrhi,MAC Address9 [47:32]"
line.long 0x50 "gmacgrp_mac_address9_low,Register 35 (MAC Address9 Low Register)"
hexmask.long 0x50 0.--31. 1. "addrlo,MAC Address9 [31:0]"
line.long 0x54 "gmacgrp_mac_address10_high,Register 36 (MAC Address10 High Register)"
bitfld.long 0x54 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x54 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x54 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x54 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x54 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x54 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x54 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x54 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x54 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x54 0.--15. 1. "addrhi,MAC Address10 [47:32]"
line.long 0x58 "gmacgrp_mac_address10_low,Register 37 (MAC Address10 Low Register)"
hexmask.long 0x58 0.--31. 1. "addrlo,MAC Address10 [31:0]"
line.long 0x5C "gmacgrp_mac_address11_high,Register 38 (MAC Address11 High Register)"
bitfld.long 0x5C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x5C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x5C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x5C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x5C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x5C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x5C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x5C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x5C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x5C 0.--15. 1. "addrhi,MAC Address11 [47:32]"
line.long 0x60 "gmacgrp_mac_address11_low,Register 39 (MAC Address1 Low Register)"
hexmask.long 0x60 0.--31. 1. "addrlo,MAC Address11 [31:0]"
line.long 0x64 "gmacgrp_mac_address12_high,Register 40 (MAC Address12 High Register )"
bitfld.long 0x64 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x64 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x64 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x64 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x64 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x64 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x64 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x64 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x64 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x64 0.--15. 1. "addrhi,MAC Address12 [47:32]"
line.long 0x68 "gmacgrp_mac_address12_low,Register 41 (MAC Address12 Low Register)"
hexmask.long 0x68 0.--31. 1. "addrlo,MAC Address12 [31:0]"
line.long 0x6C "gmacgrp_mac_address13_high,Register 42 (MAC Address13 High Register)"
bitfld.long 0x6C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x6C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x6C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x6C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x6C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x6C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x6C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x6C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x6C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x6C 0.--15. 1. "addrhi,MAC Address13 [47:32]"
line.long 0x70 "gmacgrp_mac_address13_low,Register 43 (MAC Address13 Low Register)"
hexmask.long 0x70 0.--31. 1. "addrlo,MAC Address13 [31:0]"
line.long 0x74 "gmacgrp_mac_address14_high,Register 44 (MAC Address14 High Register)"
bitfld.long 0x74 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x74 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x74 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x74 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x74 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x74 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x74 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x74 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x74 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x74 0.--15. 1. "addrhi,MAC Address14 [47:32]"
line.long 0x78 "gmacgrp_mac_address14_low,Register 45 (MAC Address14 Low Register)"
hexmask.long 0x78 0.--31. 1. "addrlo,MAC Address14 [31:0]"
line.long 0x7C "gmacgrp_mac_address15_high,Register 46 (MAC Address15 High Register)"
bitfld.long 0x7C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x7C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x7C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x7C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x7C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x7C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x7C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x7C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x7C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x7C 0.--15. 1. "addrhi,MAC Address15 [47:32] This field contains the upper 16 bits (47:32) of the 16th 6-byte MAC address."
line.long 0x80 "gmacgrp_mac_address15_low,Register 47 (MAC Address15 Low Register)"
hexmask.long 0x80 0.--31. 1. "addrlo,MAC Address15 [31:0]"
rgroup.long 0xD8++0x3
line.long 0x0 "gmacgrp_sgmii_rgmii_smii_control_status,The SGMII/RGMII/SMII Status register indicates the status signals received by the RGMII interface (selected at reset) from the PHY."
bitfld.long 0x0 3. "lnksts,This bit indicates whether the link is up (1'b1) or down (1'b0)." "0,1"
newline
bitfld.long 0x0 1.--2. "lnkspeed,This bit indicates the current speed of the link. Bit 2 is reserved when the MAC is configured for the SMII PHY interface." "0,1,2,3"
newline
bitfld.long 0x0 0. "lnkmod,This bit indicates the current mode of operation of the link" "0,1"
group.long 0xDC++0x7
line.long 0x0 "gmacgrp_wdog_timeout,Register 55 (Watchdog Timeout Register)"
hexmask.long.word 0x0 17.--31. 1. "reserved_31_17,Reserved"
newline
bitfld.long 0x0 16. "pwe,Programmable Watchdog Enable" "0,1"
newline
rbitfld.long 0x0 14.--15. "reserved_15_14,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "wto,Watchdog Timeout"
line.long 0x4 "gmacgrp_genpio,Register 56 (General Purpose IO Register)"
hexmask.long.byte 0x4 25.--31. 1. "reserved_31_x,Reserved"
newline
bitfld.long 0x4 24. "gpit,GPI Type" "0,1"
newline
hexmask.long.byte 0x4 17.--23. 1. "reserved_23_x,Reserved"
newline
bitfld.long 0x4 16. "gpie,GPI Interrupt Enable" "0,1"
newline
hexmask.long.byte 0x4 9.--15. 1. "reserved_15_x,Reserved"
newline
bitfld.long 0x4 8. "gpo,General Purpose Output" "0,1"
newline
hexmask.long.byte 0x4 1.--7. 1. "reserved_7_x,Reserved"
newline
rbitfld.long 0x4 0. "gpis,General Purpose Input Status" "0,1"
group.long 0x100++0x3
line.long 0x0 "gmacgrp_mmc_control,Register 64 (MMC Control Register)"
hexmask.long.tbyte 0x0 9.--31. 1. "reserved_31_9,Reserved"
newline
bitfld.long 0x0 8. "ucdbc,Update MMC Counters for Dropped Broadcast Frames" "0,1"
newline
rbitfld.long 0x0 6.--7. "reserved_7_6,Reserved" "0,1,2,3"
newline
bitfld.long 0x0 5. "cntprstlvl,Full-Half Preset" "0,1"
newline
bitfld.long 0x0 4. "cntprst,Counters Preset" "0,1"
newline
bitfld.long 0x0 3. "cntfreez,MMC Counter Freeze" "0,1"
newline
bitfld.long 0x0 2. "rstonrd,Reset on Read" "0,1"
newline
bitfld.long 0x0 1. "cntstopro,Counters Stop Rollover" "0,1"
newline
bitfld.long 0x0 0. "cntrst,Counters Reset" "0,1"
rgroup.long 0x104++0x7
line.long 0x0 "gmacgrp_mmc_receive_interrupt,Register 65 (MMC Receive Interrupt Register)"
hexmask.long.byte 0x0 26.--31. 1. "reserved_31_26,Reserved"
newline
bitfld.long 0x0 25. "rxctrlfis,MMC Receive Control Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 24. "rxrcverrfis,MMC Receive Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 23. "rxwdogfis,MMC Receive Watchdog Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 22. "rxvlangbfis,MMC Receive VLAN Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 21. "rxfovfis,MMC Receive FIFO Overflow Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 20. "rxpausfis,MMC Receive Pause Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 19. "rxorangefis,MMC Receive Out Of Range Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 18. "rxlenerfis,MMC Receive Length Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 17. "rxucgfis,MMC Receive Unicast Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 16. "rx1024tmaxoctgbfis,MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 15. "rx512t1023octgbfis,MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 14. "rx256t511octgbfis,MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 13. "rx128t255octgbfis,MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 12. "rx65t127octgbfis,MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 11. "rx64octgbfis,MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 10. "rxosizegfis,MMC Receive Oversize Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 9. "rxusizegfis,MMC Receive Undersize Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 8. "rxjaberfis,MMC Receive Jabber Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 7. "rxruntfis,MMC Receive Runt Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 6. "rxalgnerfis,MMC Receive Alignment Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 5. "rxcrcerfis,MMC Receive CRC Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 4. "rxmcgfis,MMC Receive Multicast Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 3. "rxbcgfis,MMC Receive Broadcast Good Frame Counter Interrupt Status." "0,1"
newline
bitfld.long 0x0 2. "rxgoctis,MMC Receive Good Octet Counter Interrupt Status." "0,1"
newline
bitfld.long 0x0 1. "rxgboctis,MMC Receive Good Bad Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "rxgbfrmis,MMC Receive Good Bad Frame Counter Interrupt Status" "0,1"
line.long 0x4 "gmacgrp_mmc_transmit_interrupt,Register 66 (MMC Transmit Interrupt Register)"
hexmask.long.byte 0x4 26.--31. 1. "reserved_31_26,Reserved"
newline
bitfld.long 0x4 25. "txosizegfis,MMC Transmit Oversize Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 24. "txvlangfis,MMC Transmit VLAN Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 23. "txpausfis,MMC Transmit Pause Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 22. "txexdeffis,MMC Transmit Excessive Deferral Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 21. "txgfrmis,MMC Transmit Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 20. "txgoctis,MMC Transmit Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 19. "txcarerfis,MMC Transmit Carrier Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 18. "txexcolfis,MMC Transmit Excessive Collision Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 17. "txlatcolfis,MMC Transmit Late Collision Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 16. "txdeffis,MMC Transmit Deferred Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 15. "txmcolgfis,MMC Transmit Multiple Collision Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 14. "txscolgfis,MMC Transmit Single Collision Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 13. "txuflowerfis,MMC Transmit Underflow Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 12. "txbcgbfis,MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 11. "txmcgbfis,MMC Transmit Multicast Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 10. "txucgbfis,MMC Transmit Unicast Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 9. "tx1024tmaxoctgbfis,MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 8. "tx512t1023octgbfis,MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 7. "tx256t511octgbfis,MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 6. "tx128t255octgbfis,MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 5. "tx65t127octgbfis,MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 4. "tx64octgbfis,MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status." "0,1"
newline
bitfld.long 0x4 3. "txmcgfis,MMC Transmit Multicast Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 2. "txbcgfis,MMC Transmit Broadcast Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 1. "txgbfrmis,MMC Transmit Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 0. "txgboctis,MMC Transmit Good Bad Octet Counter Interrupt Status" "0,1"
group.long 0x10C++0x7
line.long 0x0 "gmacgrp_mmc_receive_interrupt_mask,Regsiter 67 (MMC Receive Interrupt Mask Register)"
hexmask.long.byte 0x0 26.--31. 1. "reserved_31_26,Reserved"
newline
bitfld.long 0x0 25. "rxctrlfim,MMC Receive Control Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 24. "rxrcverrfim,MMC Receive Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 23. "rxwdogfim,MMC Receive Watchdog Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 22. "rxvlangbfim,MMC Receive VLAN Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 21. "rxfovfim,MMC Receive FIFO Overflow Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 20. "rxpausfim,MMC Receive Pause Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 19. "rxorangefim,MMC Receive Out Of Range Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 18. "rxlenerfim,MMC Receive Length Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 17. "rxucgfim,MMC Receive Unicast Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 16. "rx1024tmaxoctgbfim,MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 15. "rx512t1023octgbfim,MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 14. "rx256t511octgbfim,MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 13. "rx128t255octgbfim,MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 12. "rx65t127octgbfim,MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 11. "rx64octgbfim,MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 10. "rxosizegfim,MMC Receive Oversize Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 9. "rxusizegfim,MMC Receive Undersize Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 8. "rxjaberfim,MMC Receive Jabber Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 7. "rxruntfim,MMC Receive Runt Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 6. "rxalgnerfim,MMC Receive Alignment Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 5. "rxcrcerfim,MMC Receive CRC Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 4. "rxmcgfim,MMC Receive Multicast Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 3. "rxbcgfim,MMC Receive Broadcast Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "rxgoctim,MMC Receive Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "rxgboctim,MMC Receive Good Bad Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "rxgbfrmim,MMC Receive Good Bad Frame Counter Interrupt Mask" "0,1"
line.long 0x4 "gmacgrp_mmc_transmit_interrupt_mask,Register 68 (MMC Transmit Interrupt Mask Register)"
hexmask.long.byte 0x4 26.--31. 1. "reserved_31_26,Reserved"
newline
bitfld.long 0x4 25. "txosizegfim,MMC Transmit Oversize Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 24. "txvlangfim,MMC Transmit VLAN Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 23. "txpausfim,MMC Transmit Pause Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 22. "txexdeffim,MMC Transmit Excessive Deferral Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 21. "txgfrmim,MMC Transmit Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 20. "txgoctim,MMC Transmit Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 19. "txcarerfim,MMC Transmit Carrier Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 18. "txexcolfim,MMC Transmit Excessive Collision Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 17. "txlatcolfim,MMC Transmit Late Collision Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 16. "txdeffim,MMC Transmit Deferred Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 15. "txmcolgfim,MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 14. "txscolgfim,MMC Transmit Single Collision Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 13. "txuflowerfim,MMC Transmit Underflow Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 12. "txbcgbfim,MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 11. "txmcgbfim,MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 10. "txucgbfim,MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 9. "tx1024tmaxoctgbfim,MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 8. "tx512t1023octgbfim,MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 7. "tx256t511octgbfim,MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 6. "tx128t255octgbfim,MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 5. "tx65t127octgbfim,MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 4. "tx64octgbfim,MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 3. "txmcgfim,MMC Transmit Multicast Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 2. "txbcgfim,MMC Transmit Broadcast Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 1. "txgbfrmim,MMC Transmit Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 0. "txgboctim,MMC Transmit Good Bad Octet Counter Interrupt Mask" "0,1"
rgroup.long 0x114++0x67
line.long 0x0 "gmacgrp_txoctetcount_gb,Register 69 (Transmit Octet Count for Good and Bad Frames)"
hexmask.long 0x0 0.--31. 1. "cnt,This field indicates the number of bytes transmitted in good and bad frames exclusive of preamble and retried bytes."
line.long 0x4 "gmacgrp_txframecount_gb,Register 70 (Transmit Frame Count for Good and Bad Frames)"
hexmask.long 0x4 0.--31. 1. "cnt,This field indicates the number of good and bad frames transmitted  exclusive of retried frames"
line.long 0x8 "gmacgrp_txbroadcastframes_g,Register 71 (Transmit Frame Count for Good Broadcast Frames)"
hexmask.long 0x8 0.--31. 1. "cnt,This field indicates the number of transmitted good broadcast frames."
line.long 0xC "gmacgrp_txmulticastframes_g,Register 72 (Transmit Frame Count for Good Multicast Frames)"
hexmask.long 0xC 0.--31. 1. "cnt,This field indicates the number of transmitted good multicast frames."
line.long 0x10 "gmacgrp_tx64octets_gb,Register 73 (Transmit Octet Count for Good and Bad 64 Byte Frames)"
hexmask.long 0x10 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad frames with length of 64 bytes  exclusive of preamble and retried frames."
line.long 0x14 "gmacgrp_tx65to127octets_gb,Register 74 (Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames)"
hexmask.long 0x14 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad frames with length between 65 and 127 (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x18 "gmacgrp_tx128to255octets_gb,Register 75 (Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames)"
hexmask.long 0x18 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad frames with length between 128 and 255 (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x1C "gmacgrp_tx256to511octets_gb,Register 76 (Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames)"
hexmask.long 0x1C 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad frames with length between 256 and 511 (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x20 "gmacgrp_tx512to1023octets_gb,Register 77 (Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames)"
hexmask.long 0x20 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad frames with length between 512 and 1 023 (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x24 "gmacgrp_tx1024tomaxoctets_gb,Register 78 (Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames)"
hexmask.long 0x24 0.--31. 1. "cnt,This field indicates the number of good and bad frames transmitted with length between 1 024 and maxsize (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x28 "gmacgrp_txunicastframes_gb,Register 79 (Transmit Frame Count for Good and Bad Unicast Frames)"
hexmask.long 0x28 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad unicast frames."
line.long 0x2C "gmacgrp_txmulticastframes_gb,Register 80 (Transmit Frame Count for Good and Bad Multicast Frames)"
hexmask.long 0x2C 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad multicast frames."
line.long 0x30 "gmacgrp_txbroadcastframes_gb,Register 81 (Transmit Frame Count for Good and Bad Broadcast Frames)"
hexmask.long 0x30 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad broadcast frames."
line.long 0x34 "gmacgrp_txunderflowerror,Register 82 (Transmit Frame Count for Underflow Error Frames)"
hexmask.long 0x34 0.--31. 1. "cnt,This field indicates the number of frames aborted because of frame underflow error."
line.long 0x38 "gmacgrp_txsinglecol_g,Register 83 (Transmit Frame Count for Frames Transmitted after Single Collision)"
hexmask.long 0x38 0.--31. 1. "cnt,This field indicates the number of successfully transmitted frames after a single collision in the half-duplex mode."
line.long 0x3C "gmacgrp_txmulticol_g,Register 84 (Transmit Frame Count for Frames Transmitted after Multiple Collision)"
hexmask.long 0x3C 0.--31. 1. "cnt,This field indicates the number of successfully transmitted frames after multiple collisions in the half-duplex mode."
line.long 0x40 "gmacgrp_txdeferred,Register 85 (Transmit Frame Count for Deferred Frames)"
hexmask.long 0x40 0.--31. 1. "cnt,This field indicates the number of successfully transmitted frames after a deferral in the half-duplex mode."
line.long 0x44 "gmacgrp_txlatecol,Register 86 (Transmit Frame Count for Late Collision Error Frames)"
hexmask.long 0x44 0.--31. 1. "cnt,This field indicates the number of frames aborted because of late collision error."
line.long 0x48 "gmacgrp_txexesscol,Register 87 (Transmit Frame Count for Excessive Collision Error Frames)"
hexmask.long 0x48 0.--31. 1. "cnt,This field indicates the number of frames aborted because of excessive (16) collision error."
line.long 0x4C "gmacgrp_txcarriererr,Register 88 (Transmit Frame Count for Carrier Sense Error Frames)"
hexmask.long 0x4C 0.--31. 1. "cnt,This field indicates the number of frames aborted because of carrier sense error (no carrier or loss of carrier)."
line.long 0x50 "gmacgrp_txoctetcnt,Register 89 (Transmit Octet Count for Good Frames)"
hexmask.long 0x50 0.--31. 1. "txoctetcount_g,This field indicates the number of bytes transmitted  exclusive of preamble  in good frames."
line.long 0x54 "gmacgrp_txframecount_g,Register 90 (Transmit Frame Count for Good Frames)"
hexmask.long 0x54 0.--31. 1. "cnt,This field indicates the number of transmitted good frames  exclusive of preamble."
line.long 0x58 "gmacgrp_txexcessdef,Register 91 (Transmit Frame Count for Excessive Deferral Error Frames)"
hexmask.long 0x58 0.--31. 1. "cnt,This field indicates the number of frames aborted because of excessive deferral error  that is  frames deferred for more than two max-sized frame times."
line.long 0x5C "gmacgrp_txpauseframes,Register 92 (Transmit Frame Count for Good PAUSE Frames)"
hexmask.long 0x5C 0.--31. 1. "cnt,This field indicates the number of transmitted good PAUSE frames."
line.long 0x60 "gmacgrp_txvlanframes_g,Register 93 (Transmit Frame Count for Good VLAN Frames)"
hexmask.long 0x60 0.--31. 1. "cnt,This register maintains the number of transmitted good VLAN frames  exclusive of retried frames."
line.long 0x64 "gmacgrp_txoversize_g,Register 94 (Transmit Frame Count for Good Oversize Frames)"
hexmask.long 0x64 0.--31. 1. "cnt,This field indicates the number of frames transmitted without errors and with length greater than the maxsize (1 518 or 1 522 bytes for VLAN tagged frames; 2000 bytes if enabled in bit 27 of Register 0 (MAC Configuration Register))."
rgroup.long 0x180++0x67
line.long 0x0 "gmacgrp_rxframecount_gb,Register 96 (Receive Frame Count for Good and Bad Frames)"
hexmask.long 0x0 0.--31. 1. "cnt,This field indicates the number of received good and bad frames."
line.long 0x4 "gmacgrp_rxoctetcount_gb,Register 97 (Receive Octet Count for Good and Bad Frames)"
hexmask.long 0x4 0.--31. 1. "cnt,This field indicates the number of bytes received  exclusive of preamble  in good and bad frames."
line.long 0x8 "gmacgrp_rxoctetcount_g,Register 98 (Receive Octet Count for Good Frames)"
hexmask.long 0x8 0.--31. 1. "cnt,This field indicates the number of bytes received  exclusive of preamble  only in good frames."
line.long 0xC "gmacgrp_rxbroadcastframes_g,Register 99 (Receive Frame Count for Good Broadcast Frames)"
hexmask.long 0xC 0.--31. 1. "cnt,This field indicates the number of received good broadcast frames."
line.long 0x10 "gmacgrp_rxmulticastframes_g,Register 100 (Receive Frame Count for Good Multicast Frames)"
hexmask.long 0x10 0.--31. 1. "cnt,This field indicates the number of received good multicast frames."
line.long 0x14 "gmacgrp_rxcrcerror,Register 101 (Receive Frame Count for CRC Error Frames)"
hexmask.long 0x14 0.--31. 1. "cnt,This field indicates the number of frames received with CRC error."
line.long 0x18 "gmacgrp_rxalignmenterror,Register 102 (Receive Frame Count for Alignment Error Frames)"
hexmask.long 0x18 0.--31. 1. "cnt,This field indicates the number of frames received with alignment (dribble) error. This field is valid only in the 10 or 100 Mbps mode."
line.long 0x1C "gmacgrp_rxrunterror,Register 103 (Receive Frame Count for Runt Error Frames)"
hexmask.long 0x1C 0.--31. 1. "cnt,This field indicates the number of frames received with runt error(< bytes and CRC error)."
line.long 0x20 "gmacgrp_rxjabbererror,Register 104 (Receive Frame Count for Jabber Error Frames)"
hexmask.long 0x20 0.--31. 1. "cnt,This field indicates the number of giant frames received with length (including CRC) greater than 1 518 bytes (1 522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled  then frames of length greater than 9 018 bytes (9 022 for.."
line.long 0x24 "gmacgrp_rxundersize_g,Register 105 (Receive Frame Count for Undersize Frames)"
hexmask.long 0x24 0.--31. 1. "cnt,This field indicates the number of frames received with length less than 64 bytes and without errors."
line.long 0x28 "gmacgrp_rxoversize_g,Register 106 (Receive Frame Count for Oversize Frames)"
hexmask.long 0x28 0.--31. 1. "cnt,This field indicates the number of frames received without errors  with length greater than the maxsize (1 518 or 1 522 for VLAN tagged frames; 2 000 bytes if enabled in bit 27 of Register 0 (MAC Configuration Register))."
line.long 0x2C "gmacgrp_rx64octets_gb,Register 107 (Receive Frame Count for Good and Bad 64 Byte Frames)"
hexmask.long 0x2C 0.--31. 1. "cnt,This field indicates the number of received good and bad frames with length 64 bytes  exclusive of preamble."
line.long 0x30 "gmacgrp_rx65to127octets_gb,Register 108 (Receive Frame Count for Good and Bad 65 to 127 Bytes Frames)"
hexmask.long 0x30 0.--31. 1. "cnt,This field indicates the number of received good and bad frames received with length between 65 and 127 (inclusive) bytes  exclusive of preamble."
line.long 0x34 "gmacgrp_rx128to255octets_gb,Register 109 (Receive Frame Count for Good and Bad 128 to 255 Bytes Frames)"
hexmask.long 0x34 0.--31. 1. "cnt,This field indicates the number of received good and bad frames with length between 128 and 255 (inclusive) bytes  exclusive of preamble."
line.long 0x38 "gmacgrp_rx256to511octets_gb,Register 110 (Receive Frame Count for Good and Bad 256 to 511 Bytes Frames)"
hexmask.long 0x38 0.--31. 1. "cnt,This field indicates the number of received good and bad frames with length between 256 and 511 (inclusive) bytes  exclusive of preamble."
line.long 0x3C "gmacgrp_rx512to1023octets_gb,Register 111 (Receive Frame Count for Good and Bad 512 to 1.023 Bytes Frames)"
hexmask.long 0x3C 0.--31. 1. "cnt,This field indicates the number of received good and bad frames with length between 512 and 1 023 (inclusive) bytes  exclusive of preamble."
line.long 0x40 "gmacgrp_rx1024tomaxoctets_gb,Register 112 (Receive Frame Count for Good and Bad 1.024 to Maxsize Bytes Frames)"
hexmask.long 0x40 0.--31. 1. "cnt,This field indicates the number of received good and bad frames with length between 1 024 and maxsize (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x44 "gmacgrp_rxunicastframes_g,Register 113 (Receive Frame Count for Good Unicast Frames)"
hexmask.long 0x44 0.--31. 1. "cnt,This field indicates the number of received good unicast frames."
line.long 0x48 "gmacgrp_rxlengtherror,Register 114 (Receive Frame Count for Length Error Frames)"
hexmask.long 0x48 0.--31. 1. "cnt,This field indicates the number of frames received with length error (Length type field not equal to frame size) for all frames with valid length field."
line.long 0x4C "gmacgrp_rxoutofrangetype,Register 115 (Receive Frame Count for Out of Range Frames)"
hexmask.long 0x4C 0.--31. 1. "cnt,This field indicates the number of received frames with length field not equal to the valid frame size (greater than 1 500 but less than 1 536)."
line.long 0x50 "gmacgrp_rxpauseframes,Register 116 (Receive Frame Count for PAUSE Frames)"
hexmask.long 0x50 0.--31. 1. "cnt,This field indicates the number of received good and valid PAUSE frames."
line.long 0x54 "gmacgrp_rxfifooverflow,Register 117 (Receive Frame Count for FIFO Overflow Frames)"
hexmask.long 0x54 0.--31. 1. "cnt,This field indicates the number of received frames missed because of FIFO overflow."
line.long 0x58 "gmacgrp_rxvlanframes_gb,Register 118 (Receive Frame Count for Good and Bad VLAN Frames)"
hexmask.long 0x58 0.--31. 1. "cnt,This field indicates the number of received good and bad VLAN frames."
line.long 0x5C "gmacgrp_rxwatchdogerror,Register 119 (Receive Frame Count for Watchdog Error Frames)"
hexmask.long 0x5C 0.--31. 1. "cnt,This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2 048 bytes or value programmed in Register 55 (Watchdog Timeout Register))."
line.long 0x60 "gmacgrp_rxrcverror,Register 120 (Receive Frame Count for Receive Error Frames)"
hexmask.long 0x60 0.--31. 1. "cnt,This field indicates the number of frames received with error because of the GMII/MII RXER error or Frame Extension error on GMII."
line.long 0x64 "gmacgrp_rxctrlframes_g,Register 121 (Receive Frame Count for Good Control Frames Frames)"
hexmask.long 0x64 0.--31. 1. "cnt,This field indicates the number of good control frames received."
group.long 0x200++0x3
line.long 0x0 "gmacgrp_mmc_ipc_receive_interrupt_mask,This register maintains the mask for the interrupt generated from the receive IPC statistic"
bitfld.long 0x0 29. "rxicmperoim,Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 28. "rxicmpgoim,Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 27. "rxtcperoim,Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 26. "rxtcpgoim,Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 25. "rxudperoim,Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 24. "rxudpgoim,Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 23. "rxipv6nopayoim,Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 22. "rxipv6heroim,Setting this bit masks interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 21. "rxipv6goim,Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 20. "rxipv4udsbloim,Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 19. "rxipv4fragoim,Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 18. "rxipv4nopayoim,Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 17. "rxipv4heroim,Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 16. "rxipv4goim,Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 13. "rxicmperfim,Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 12. "rxicmpgfim,Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 11. "rxtcperfim,Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 10. "rxtcpgfim,Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 9. "rxudperfim,Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 8. "rxudpgfim,Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 7. "rxipv6nopayfim,Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 6. "rxipv6herfim,Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 5. "rxipv6gfim,Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 4. "rxipv4udsblfim,Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 3. "rxipv4fragfim,Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 2. "rxipv4nopayfim,Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 1. "rxipv4herfim,Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 0. "rxipv4gfim,Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
rgroup.long 0x208++0x3
line.long 0x0 "gmacgrp_mmc_ipc_receive_interrupt,This register maintains the interrupts generated when receive IPC statistic counters reach half their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter). and when they cross their maximum.."
bitfld.long 0x0 29. "rxicmperois,This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 28. "rxicmpgois,This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 27. "rxtcperois,This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 26. "rxtcpgois,This bit is set when the rxtcp_gd_octets counter reaches half the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 25. "rxudperois,This bit is set when the rxudp_err_octets counter reaches half the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 24. "rxudpgois,This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 23. "rxipv6nopayois,This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 22. "rxipv6herois,This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 21. "rxipv6gois,This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 20. "rxipv4udsblois,This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 19. "rxipv4fragois,This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 18. "rxipv4nopayois,This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 17. "rxipv4herois,This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 16. "rxipv4gois,This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 13. "rxicmperfis,This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 12. "rxicmpgfis,This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 11. "rxtcperfis,This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 10. "rxtcpgfis,This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 9. "rxudperfis,This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 8. "rxudpgfis,This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 7. "rxipv6nopayfis,This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 6. "rxipv6herfis,This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 5. "rxipv6gfis,This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 4. "rxipv4udsblfis,This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 3. "rxipv4fragfis,This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 2. "rxipv4nopayfis,This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 1. "rxipv4herfis,This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 0. "rxipv4gfis,This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
rgroup.long 0x210++0x37
line.long 0x0 "gmacgrp_rxipv4_gd_frms,Number of good IPv4 datagrams received with the TCP. UDP. or ICMP payload"
hexmask.long 0x0 0.--31. 1. "cnt,Number of good IPv4 datagrams received with the TCP  UDP  or ICMP payload"
line.long 0x4 "gmacgrp_rxipv4_hdrerr_frms,Number of IPv4 datagrams received with header (checksum. length. or version mismatch) errors"
hexmask.long 0x4 0.--31. 1. "cnt,Number of IPv4 datagrams received with header (checksum  length  or version mismatch) errors"
line.long 0x8 "gmacgrp_rxipv4_nopay_frms,Number of IPv4 datagram frames received that did not have a TCP. UDP. or ICMP payload processed by the Checksum engine"
hexmask.long 0x8 0.--31. 1. "cnt,Number of IPv4 datagram frames received that did not have a TCP  UDP  or ICMP payload processed by the Checksum engine"
line.long 0xC "gmacgrp_rxipv4_frag_frms,Number of good IPv4 datagrams with fragmentation"
hexmask.long 0xC 0.--31. 1. "cnt,Number of good IPv4 datagrams with fragmentation"
line.long 0x10 "gmacgrp_rxipv4_udsbl_frms,Number of good IPv4 datagrams received that had a UDP payload with checksum disabled"
hexmask.long 0x10 0.--31. 1. "cnt,Number of good IPv4 datagrams received that had a UDP payload with checksum disabled"
line.long 0x14 "gmacgrp_rxipv6_gd_frms,Number of good IPv6 datagrams received with TCP. UDP. or ICMP payloads"
hexmask.long 0x14 0.--31. 1. "cnt,Number of good IPv6 datagrams received with TCP  UDP  or ICMP payloads"
line.long 0x18 "gmacgrp_rxipv6_hdrerr_frms,Number of IPv6 datagrams received with header errors (length or version mismatch)"
hexmask.long 0x18 0.--31. 1. "cnt,Number of IPv6 datagrams received with header errors (length or version mismatch)"
line.long 0x1C "gmacgrp_rxipv6_nopay_frms,Number of IPv6 datagram frames received that did not have a TCP. UDP. or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers"
hexmask.long 0x1C 0.--31. 1. "cnt,Number of IPv6 datagram frames received that did not have a TCP  UDP  or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers"
line.long 0x20 "gmacgrp_rxudp_gd_frms,Number of good IP datagrams with a good UDP payload. This counter is not updated when the counter is incremented"
hexmask.long 0x20 0.--31. 1. "cnt,Number of good IP datagrams with a good UDP payload. This counter is not updated when the counter is incremented"
line.long 0x24 "gmacgrp_rxudp_err_frms,Number of good IP datagrams whose UDP payload has a checksum error"
hexmask.long 0x24 0.--31. 1. "cnt,Number of good IP datagrams whose UDP payload has a checksum error"
line.long 0x28 "gmacgrp_rxtcp_gd_frms,Number of good IP datagrams with a good TCP payload"
hexmask.long 0x28 0.--31. 1. "cnt,Number of good IP datagrams with a good TCP payload"
line.long 0x2C "gmacgrp_rxtcp_err_frms,Number of good IP datagrams whose TCP payload has a checksum error"
hexmask.long 0x2C 0.--31. 1. "cnt,Number of good IP datagrams whose TCP payload has a checksum error"
line.long 0x30 "gmacgrp_rxicmp_gd_frms,Number of good IP datagrams with a good ICMP payload"
hexmask.long 0x30 0.--31. 1. "cnt,Number of good IP datagrams with a good ICMP payload"
line.long 0x34 "gmacgrp_rxicmp_err_frms,Number of good IP datagrams whose ICMP payload has a checksum error"
hexmask.long 0x34 0.--31. 1. "cnt,Number of good IP datagrams whose ICMP payload has a checksum error"
rgroup.long 0x250++0x37
line.long 0x0 "gmacgrp_rxipv4_gd_octets,Number of bytes received in good IPv4 datagrams encapsulating TCP. UDP. or ICMP data"
hexmask.long 0x0 0.--31. 1. "cnt,Number of bytes received in good IPv4 datagrams encapsulating TCP  UDP  or ICMP data"
line.long 0x4 "gmacgrp_rxipv4_hdrerr_octets,Number of bytes received in IPv4 datagrams with header errors (checksum. length. version mismatch). The value in the Length field of IPv4 header is used to update this counter"
hexmask.long 0x4 0.--31. 1. "cnt,Number of bytes received in IPv4 datagrams with header errors (checksum  length  version mismatch). The value in the Length field of IPv4 header is used to update this counter"
line.long 0x8 "gmacgrp_rxipv4_nopay_octets,Number of bytes received in IPv4 datagrams that did not have a TCP. UDP. or ICMP payload. The value in the IPv4 headers Length field is used to update this counter"
hexmask.long 0x8 0.--31. 1. "cnt,Number of bytes received in IPv4 datagrams that did not have a TCP  UDP  or ICMP payload. The value in the IPv4 headers Length field is used to update this counter"
line.long 0xC "gmacgrp_rxipv4_frag_octets,Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 headers Length field is used to update this counter"
hexmask.long 0xC 0.--31. 1. "cnt,Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 headers Length field is used to update this counter"
line.long 0x10 "gmacgrp_rxipv4_udsbl_octets,Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes"
hexmask.long 0x10 0.--31. 1. "cnt,Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes"
line.long 0x14 "gmacgrp_rxipv6_gd_octets,Number of bytes received in good IPv6 datagrams encapsulating TCP. UDP or ICMPv6 data"
hexmask.long 0x14 0.--31. 1. "cnt,Number of bytes received in good IPv6 datagrams encapsulating TCP  UDP or ICMPv6 data"
line.long 0x18 "gmacgrp_rxipv6_hdrerr_octets,Number of bytes received in IPv6 datagrams with header errors (length. version mismatch). The value in the IPv6 headers Length field is used to update this counter"
hexmask.long 0x18 0.--31. 1. "cnt,Number of bytes received in IPv6 datagrams with header errors (length  version mismatch). The value in the IPv6 headers Length field is used to update this counter"
line.long 0x1C "gmacgrp_rxipv6_nopay_octets,Number of bytes received in IPv6 datagrams that did not have a TCP. UDP. or ICMP payload. The value in the IPv6 headers Length field is used to update this counter"
hexmask.long 0x1C 0.--31. 1. "cnt,Number of bytes received in IPv6 datagrams that did not have a TCP  UDP  or ICMP payload. The value in the IPv6 headers Length field is used to update this counter"
line.long 0x20 "gmacgrp_rxudp_gd_octets,Number of bytes received in a good UDP segment. This counter does not count IP header bytes"
hexmask.long 0x20 0.--31. 1. "cnt,Number of bytes received in a good UDP segment. This counter does not count IP header bytes"
line.long 0x24 "gmacgrp_rxudp_err_octets,Number of bytes received in a UDP segment that had checksum errors"
hexmask.long 0x24 0.--31. 1. "cnt,Number of bytes received in a UDP segment that had checksum errors"
line.long 0x28 "gmacgrp_rxtcp_gd_octets,Number of bytes received in a good TCP segment"
hexmask.long 0x28 0.--31. 1. "cnt,Number of bytes received in a good TCP segment"
line.long 0x2C "gmacgrp_rxtcperroctets,Number of bytes received in a TCP segment with checksum errors"
hexmask.long 0x2C 0.--31. 1. "rxtcp_err_octets,Number of bytes received in a TCP segment with checksum errors"
line.long 0x30 "gmacgrp_rxicmp_gd_octets,Number of bytes received in a good ICMP segment"
hexmask.long 0x30 0.--31. 1. "cnt,Number of bytes received in a good ICMP segment"
line.long 0x34 "gmacgrp_rxicmp_err_octets,Number of bytes received in an ICMP segment with checksum errors"
hexmask.long 0x34 0.--31. 1. "cnt,Number of bytes received in an ICMP segment with checksum errors"
group.long 0x400++0x7
line.long 0x0 "gmacgrp_l3_l4_control0,Register 256 (Layer 3 and Layer 4 Control Register 0)"
hexmask.long.word 0x0 22.--31. 1. "reserved_31_22,Reserved"
newline
bitfld.long 0x0 21. "l4dpim0,Layer 4 Destination Port Inverse Match Enable" "0,1"
newline
bitfld.long 0x0 20. "l4dpm0,Layer 4 Destination Port Match Enable" "0,1"
newline
bitfld.long 0x0 19. "l4spim0,Layer 4 Source Port Inverse Match Enable" "0,1"
newline
bitfld.long 0x0 18. "l4spm0,Layer 4 Source Port Match Enable" "0,1"
newline
rbitfld.long 0x0 17. "reserved_17,Reserved" "0,1"
newline
bitfld.long 0x0 16. "l4pen0,Layer 4 Protocol Enable" "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "l3hdbm0,Layer 3 IP DA Higher Bits Match"
newline
hexmask.long.byte 0x0 6.--10. 1. "l3hsbm0,Layer 3 IP SA Higher Bits Match"
newline
bitfld.long 0x0 5. "l3daim0,Layer 3 IP DA Inverse Match Enable" "0,1"
newline
bitfld.long 0x0 4. "l3dam0,Layer 3 IP DA Match Enable" "0,1"
newline
bitfld.long 0x0 3. "l3saim0,Layer 3 IP SA Inverse Match Enable" "0,1"
newline
bitfld.long 0x0 2. "l3sam0,Layer 3 IP SA Match Enable" "0,1"
newline
rbitfld.long 0x0 1. "reserved_1,Reserved" "0,1"
newline
bitfld.long 0x0 0. "l3pen0,Layer 3 Protocol Enable" "0,1"
line.long 0x4 "gmacgrp_layer4_address0,Register 257 (Layer 4 Address Register 0)"
hexmask.long.word 0x4 16.--31. 1. "l4dp0,Layer 4 Destination Port Number Field"
newline
hexmask.long.word 0x4 0.--15. 1. "l4sp0,Layer 4 Source Port Number Field"
group.long 0x410++0xF
line.long 0x0 "gmacgrp_layer3_addr0_reg0,Register 260 (Layer 3 Address 0 Register 0)"
hexmask.long 0x0 0.--31. 1. "l3a00,Layer 3 Address 0 Field"
line.long 0x4 "gmacgrp_layer3_addr1_reg0,Register 261 (Layer 3 Address 1 Register 0)"
hexmask.long 0x4 0.--31. 1. "l3a10,Layer 3 Address 1 Field"
line.long 0x8 "gmacgrp_layer3_addr2_reg0,Register 262 (Layer 3 Address 2 Register 0)"
hexmask.long 0x8 0.--31. 1. "l3a20,Layer 3 Address 2 Field"
line.long 0xC "gmacgrp_layer3_addr3_reg0,Register 263 (Layer 3 Address 3 Register 0)"
hexmask.long 0xC 0.--31. 1. "l3a30,Layer 3 Address 3 Field"
group.long 0x430++0x7
line.long 0x0 "gmacgrp_l3_l4_control1,This register controls the operations of the filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 21. "l4dpim1,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching." "0,1"
newline
bitfld.long 0x0 20. "l4dpm1,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for matching." "0,1"
newline
bitfld.long 0x0 19. "l4spim1,When set  this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching." "0,1"
newline
bitfld.long 0x0 18. "l4spm1,When set  this bit indicates that the Layer 4 Source Port number field is enabled for matching." "0,1"
newline
bitfld.long 0x0 16. "l4pen1,When set  this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset  this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "l3hdbm1,IPv4 Frames:"
newline
hexmask.long.byte 0x0 6.--10. 1. "l3hsbm1,IPv4 Frames:"
newline
bitfld.long 0x0 5. "l3daim1,When set  this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching." "0,1"
newline
bitfld.long 0x0 4. "l3dam1,When set  this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Destination Address field for matching." "0,1"
newline
bitfld.long 0x0 3. "l3saim1,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching." "0,1"
newline
bitfld.long 0x0 2. "l3sam1,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Source Address field for matching." "0,1"
newline
bitfld.long 0x0 0. "l3pen1,When set  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames." "0,1"
line.long 0x4 "gmacgrp_layer4_address1,Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains. then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer.."
hexmask.long.word 0x4 16.--31. 1. "l4dp1,When Bit 16 (L4PEN1) is reset and Bit 20 (L4DPM1) is set in Register 268 (Layer 3 and Layer 4 Control Register 0)  this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames."
newline
hexmask.long.word 0x4 0.--15. 1. "l4sp1,When Bit 16 (L4PEN1) is reset and Bit 20 (L4DPM1) is set in Register 268 (Layer 3 and Layer 4 Control Register 1)  this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames."
group.long 0x440++0xF
line.long 0x0 "gmacgrp_layer3_addr0_reg1,For IPv4 frames. the Layer 3 Address 0 Register 1 contains the 32-bit IP Source Address field. For IPv6 frames. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "l3a01,When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and Layer 4 Control Register 1)  this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 frames."
line.long 0x4 "gmacgrp_layer3_addr1_reg1,For IPv4 frames. the Layer 3 Address 1 Register 1 contains the 32-bit IP Destination Address field. For IPv6 frames. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field"
hexmask.long 0x4 0.--31. 1. "l3a11,When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and Layer 4 Control Register 1)  this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames."
line.long 0x8 "gmacgrp_layer3_addr2_reg1,For IPv4 frames. the Layer 3 Address 2 Register 1 is reserved. For IPv6 frames. it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x8 0.--31. 1. "l3a21,When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and Layer 4 Control Register 1)  this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames."
line.long 0xC "gmacgrp_layer3_addr3_reg1,For IPv4 frames. the Layer 3 Address 3 Register 1 is reserved. For IPv6 frames. it contains Bits [127:96] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0xC 0.--31. 1. "l3a31,When Bit 1 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and Layer 4 Control Register 1)  this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames."
group.long 0x460++0x7
line.long 0x0 "gmacgrp_l3_l4_control2,This register controls the operations of the filter 2 of Layer 3 and Layer 4."
bitfld.long 0x0 21. "l4dpim2,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset  this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching." "0,1"
newline
bitfld.long 0x0 20. "l4dpm2,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset  the MAC ignores the Layer 4 Destination Port number field for matching." "0,1"
newline
bitfld.long 0x0 19. "l4spim2,When set  this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset  this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching." "0,1"
newline
bitfld.long 0x0 18. "l4spm2,When set  this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset  the MAC ignores the Layer 4 Source Port number field for matching." "0,1"
newline
bitfld.long 0x0 16. "l4pen2,When set  this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset  this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "l3hdbm2,IPv4 Frames:"
newline
hexmask.long.byte 0x0 6.--10. 1. "l3hsbm2,Layer 3 IP SA Higher Bits Match"
newline
bitfld.long 0x0 5. "l3daim2,When set  this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 4. "l3dam2,When set  this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Destination Address field for matching." "0,1"
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bitfld.long 0x0 3. "l3saim2,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 2. "l3sam2,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Source Address field for matching." "0,1"
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bitfld.long 0x0 0. "l3pen2,When set  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames." "0,1"
line.long 0x4 "gmacgrp_layer4_address2,Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains. then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer.."
hexmask.long.word 0x4 16.--31. 1. "l4dp2,When Bit 16 (L4PEN2) is reset and Bit 20 (L4DPM2) is set in Register 280 (Layer 3 and Layer 4 Control Register 2)  this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames."
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hexmask.long.word 0x4 0.--15. 1. "l4sp2,When Bit 16 (L4PEN2) is reset and Bit 20 (L4DPM2) is set in Register 280 (Layer 3 and Layer 4 Control Register 2)  this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames."
group.long 0x470++0xF
line.long 0x0 "gmacgrp_layer3_addr0_reg2,For IPv4 frames. the Layer 3 Address 0 Register 2 contains the 32-bit IP Source Address field. For IPv6 frames. it contains Bits [31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "l3a02,When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and Layer 4 Control Register 2)  this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames."
line.long 0x4 "gmacgrp_layer3_addr1_reg2,For IPv4 frames. the Layer 3 Address 1 Register 2 contains the 32-bit IP Destination Address field. For IPv6 frames. it contains Bits [63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x4 0.--31. 1. "l3a12,Layer 3 Address 1 Field"
line.long 0x8 "gmacgrp_layer3_addr2_reg2,For IPv4 frames. the Layer 3 Address 2 Register 2 is reserved. For IPv6 frames. it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x8 0.--31. 1. "l3a22,When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and Layer 4 Control Register 2)  this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames."
line.long 0xC "gmacgrp_layer3_addr3_reg2,For IPv4 frames. the Layer 3 Address 3 Register 2 is reserved. For IPv6 frames. it contains Bits [127:96] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0xC 0.--31. 1. "l3a32,When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and Layer 4 Control Register 2)  this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames."
group.long 0x490++0x7
line.long 0x0 "gmacgrp_l3_l4_control3,This register controls the operations of the filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 21. "l4dpim3,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset  this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 20. "l4dpm3,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset  the MAC ignores the Layer 4 Destination Port number field for matching." "0,1"
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bitfld.long 0x0 19. "l4spim3,When set  this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset  this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 18. "l4spm3,When set  this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset  the MAC ignores the Layer 4 Source Port number field for matching." "0,1"
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bitfld.long 0x0 16. "l4pen3,When set  this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset  this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching." "0,1"
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hexmask.long.byte 0x0 11.--15. 1. "l3hdbm3,Layer 3 IP DA Higher Bits Match"
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hexmask.long.byte 0x0 6.--10. 1. "l3hsbm3,IPv4 Frames:"
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bitfld.long 0x0 5. "l3daim3,When set  this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 4. "l3dam3,When set  this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Destination Address field for matching." "0,1"
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bitfld.long 0x0 3. "l3saim3,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 2. "l3sam3,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Source Address field for matching." "0,1"
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bitfld.long 0x0 0. "l3pen3,When set  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames." "0,1"
line.long 0x4 "gmacgrp_layer4_address3,Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains. then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer.."
hexmask.long.word 0x4 16.--31. 1. "l4dp3,When Bit 16 (L4PEN3) is reset and Bit 20 (L4DPM3) is set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames."
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hexmask.long.word 0x4 0.--15. 1. "l4sp3,When Bit 16 (L4PEN3) is reset and Bit 20 (L4DPM3) is set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames."
group.long 0x4A0++0xF
line.long 0x0 "gmacgrp_layer3_addr0_reg3,For IPv4 frames. the Layer 3 Address 0 Register 3 contains the 32-bit IP Source Address field. For IPv6 frames. it contains Bits [31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "l3a03,When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames."
line.long 0x4 "gmacgrp_layer3_addr1_reg3,For IPv4 frames. the Layer 3 Address 1 Register 3 contains the 32-bit IP Destination Address field. For IPv6 frames. it contains Bits [63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x4 0.--31. 1. "l3a13,When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames."
line.long 0x8 "gmacgrp_layer3_addr2_reg3,For IPv4 frames. the Layer 3 Address 2 Register 3 is reserved. For IPv6 frames. it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x8 0.--31. 1. "l3a23,When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames."
line.long 0xC "gmacgrp_layer3_addr3_reg3,For IPv4 frames. the Layer 3 Address 3 Register 3 is reserved. For IPv6 frames. it contains Bits [127:96] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0xC 0.--31. 1. "l3a33,When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames."
group.long 0x500++0x1F
line.long 0x0 "gmacgrp_hash_table_reg0,This register contains the first 32 bits of the hash table."
hexmask.long 0x0 0.--31. 1. "ht31t0,This field contains the first 32 Bits (31:0) of the Hash table."
line.long 0x4 "gmacgrp_hash_table_reg1,This register contains the second 32 bits of the hash table."
hexmask.long 0x4 0.--31. 1. "ht63t32,This field contains the second 32 Bits (63:32) of the Hash table."
line.long 0x8 "gmacgrp_hash_table_reg2,This register contains the third 32 bits of the hash table."
hexmask.long 0x8 0.--31. 1. "ht95t64,This field contains the third 32 Bits (95:64) of the Hash table."
line.long 0xC "gmacgrp_hash_table_reg3,This register contains the fourth 32 bits of the hash table."
hexmask.long 0xC 0.--31. 1. "ht127t96,This field contains the fourth 32 Bits (127:96) of the Hash table."
line.long 0x10 "gmacgrp_hash_table_reg4,This register contains the fifth 32 bits of the hash table."
hexmask.long 0x10 0.--31. 1. "ht159t128,This field contains the fifth 32 Bits (159:128) of the Hash table."
line.long 0x14 "gmacgrp_hash_table_reg5,This register contains the sixth 32 bits of the hash table."
hexmask.long 0x14 0.--31. 1. "ht191t160,This field contains the sixth 32 Bits (191:160) of the Hash table."
line.long 0x18 "gmacgrp_hash_table_reg6,This register contains the seventh 32 bits of the hash table."
hexmask.long 0x18 0.--31. 1. "ht223t196,This field contains the seventh 32 Bits (223:196) of the Hash table."
line.long 0x1C "gmacgrp_hash_table_reg7,This register contains the eighth 32 bits of the hash table."
hexmask.long 0x1C 0.--31. 1. "ht255t224,This field contains the eighth 32 Bits (255:224) of the Hash table."
group.long 0x584++0x7
line.long 0x0 "gmacgrp_vlan_incl_reg,Register 353 (VLAN Tag Inclusion or Replacement Register)"
hexmask.long.word 0x0 20.--31. 1. "reserved_31_20,Reserved"
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bitfld.long 0x0 19. "csvl,C-VLAN or S-VLAN" "0,1"
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bitfld.long 0x0 18. "vlp,VLAN Priority Control" "0,1"
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bitfld.long 0x0 16.--17. "vlc,VLAN Tag Control in Transmit Frames" "0: No VLAN tag deletion,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
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hexmask.long.word 0x0 0.--15. 1. "vlt,VLAN Tag for Transmit Frames"
line.long 0x4 "gmacgrp_vlan_hash_table_reg,The 16-bit Hash table is used for group address filtering based on VLAN tag when Bit 18 (VTHM) of Register 7 (VLAN Tag Register) is set. For hash filtering. the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on Bit 16.."
hexmask.long.word 0x4 0.--15. 1. "vlht,This field contains the 16-bit VLAN Hash Table."
group.long 0x700++0x7
line.long 0x0 "gmacgrp_timestamp_control,Register 448 (Timestamp Control Register)"
rbitfld.long 0x0 29.--31. "reserved_31_29,Reserved" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 28. "atsen3,Auxiliary Snapshot 3 Enable" "0,1"
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rbitfld.long 0x0 27. "atsen2,Auxiliary Snapshot 2 Enable" "0,1"
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rbitfld.long 0x0 26. "atsen1,Auxiliary Snapshot 1 Enable" "0,1"
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rbitfld.long 0x0 25. "atsen0,Auxiliary Snapshot 0 Enable" "0,1"
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rbitfld.long 0x0 24. "atsfc,Auxiliary Snapshot FIFO Clear" "0,1"
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hexmask.long.byte 0x0 19.--23. 1. "reserved_23_19,Reserved"
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bitfld.long 0x0 18. "tsenmacaddr,Enable MAC address for PTP Frame Filtering" "0,1"
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bitfld.long 0x0 16.--17. "snaptypsel,Select PTP packets for Taking Snapshots" "0,1,2,3"
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bitfld.long 0x0 15. "tsmstrena,Enable Snapshot for Messages Relevant to Master" "0,1"
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bitfld.long 0x0 14. "tsevntena,Enable Timestamp Snapshot for Event Messages" "0,1"
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bitfld.long 0x0 13. "tsipv4ena,Enable Processing of PTP Frames Sent over IPv4-UDP" "0,1"
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bitfld.long 0x0 12. "tsipv6ena,Enable Processing of PTP Frames Sent Over IPv6-UDP" "0,1"
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bitfld.long 0x0 11. "tsipena,Enable Processing of PTP over Ethernet Frames" "0,1"
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bitfld.long 0x0 10. "tsver2ena,Enable PTP packet Processing for Version 2 Format" "0,1"
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bitfld.long 0x0 9. "tsctrlssr,Timestamp Digital or Binary Rollover Control" "0,1"
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bitfld.long 0x0 8. "tsenall,Enable Timestamp for All Frames" "0,1"
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rbitfld.long 0x0 6.--7. "reserved_7_6,Reserved" "0,1,2,3"
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rbitfld.long 0x0 5. "tsaddreg,Addend Reg Update" "0,1"
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rbitfld.long 0x0 4. "tstrig,Timestamp Interrupt Trigger Enable" "0,1"
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rbitfld.long 0x0 3. "tsupdt,Timestamp Update" "0,1"
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rbitfld.long 0x0 2. "tsinit,Timestamp Initialize" "0,1"
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rbitfld.long 0x0 1. "tscfupdt,Timestamp Fine or Coarse Update" "0,1"
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bitfld.long 0x0 0. "tsena,Timestamp Enable" "0,1"
line.long 0x4 "gmacgrp_sub_second_increment,In the Coarse Update mode (TSCFUPDT bit in Register 448). the value in this register is added to the system time every clock cycle of clk_ptp_ref_i. In the Fine Update mode. the value in this register is added to the system.."
hexmask.long.byte 0x4 0.--7. 1. "ssinc,The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example  when PTP clock is 50 MHz (period is 20 ns)  you should program 20 (0x14) when the System Time-Nanoseconds.."
rgroup.long 0x708++0x7
line.long 0x0 "gmacgrp_system_time_seconds,The System Time -Seconds register. along with System-TimeNanoseconds register. indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis. there is some delay from the.."
hexmask.long 0x0 0.--31. 1. "tss,The value in this field indicates the current value in seconds of the System Time maintained by the MAC."
line.long 0x4 "gmacgrp_system_time_nanoseconds,The value in this field has the sub second representation of time. with an accuracy of 0.46 ns. When TSCTRLSSR is set. each bit represents 1 ns and the maximum value is 0x3B9A_C9FF. after which it rolls-over to zero."
hexmask.long 0x4 0.--30. 1. "tsss,The value in this field has the sub second representation of time  with an accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)  each bit represents 1 ns and the maximum value is 0x3B9A_C9FF  after which it.."
group.long 0x710++0x17
line.long 0x0 "gmacgrp_system_time_seconds_update,The System Time - Seconds Update register. along with the System Time - Nanoseconds Update register. initializes or updates the system time maintained by the MAC. You must write both of these registers before setting.."
hexmask.long 0x0 0.--31. 1. "tss,The value in this field indicates the time in seconds to be initialized or added to the system time."
line.long 0x4 "gmacgrp_system_time_nanoseconds_update,Update system time"
bitfld.long 0x4 31. "addsub,When this bit is set  the time value is subtracted with the contents of the update register. When this bit is reset  the time value is added with the contents of the update register." "0,1"
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hexmask.long 0x4 0.--30. 1. "tsss,The value in this field has the sub second representation of time  with an accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)  each bit represents 1 ns and the programmed value should not exceed.."
line.long 0x8 "gmacgrp_timestamp_addend,This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in Register 448). This register content is added to a 32-bit accumulator in every clock cycle (of clk_ptp_ref_i) and the.."
hexmask.long 0x8 0.--31. 1. "tsar,This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization."
line.long 0xC "gmacgrp_target_time_seconds,The Target Time Seconds register. along with Target Time Nanoseconds register. is used to schedule an interrupt event (Register 458[1] when Advanced Timestamping is enabled; otherwise. TS interrupt bit in Register14[9]) when.."
hexmask.long 0xC 0.--31. 1. "tstr,This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers  then based on Bits [6:5] of Register 459 (PPS Control Register)  the MAC starts or stops the PPS signal output and generates an.."
line.long 0x10 "gmacgrp_target_time_nanoseconds,Target time"
rbitfld.long 0x10 31. "trgtbusy,The MAC sets this bit when the PPSCMD field (Bits[3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD field to 010 or 011  instructs the MAC to synchronize the Target Time Registers to the PTP clock.." "0,1"
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hexmask.long 0x10 0.--30. 1. "ttslo,This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers  then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register)  the MAC starts or stops the.."
line.long 0x14 "gmacgrp_system_time_higher_word_seconds,System time higher word"
hexmask.long.word 0x14 0.--15. 1. "tshwr,This field contains the most significant 16-bits of the timestamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register."
rgroup.long 0x728++0x3
line.long 0x0 "gmacgrp_timestamp_status,Timestamp status. All bits except Bits[27:25] get cleared when the host reads this register."
hexmask.long.byte 0x0 25.--29. 1. "atsns,This field indicates the number of Snapshots available in the FIFO. A value of 16 (equal to the depth of the FIFO) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is.."
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bitfld.long 0x0 24. "atsstm,This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO." "0,1"
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hexmask.long.byte 0x0 16.--19. 1. "atsstn,These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time  it means that corresponding auxiliary triggers were sampled at the.."
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bitfld.long 0x0 3. "tstrgterr,This bit is set when the target time  being programmed in Target Time Registers  is already elapsed. This bit is cleared when read by the application." "0,1"
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bitfld.long 0x0 2. "auxtstrig,This bit is set high when the auxiliary snapshot is written to the FIFO." "0,1"
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bitfld.long 0x0 1. "tstargt,When set  this bit indicates that the value of system time is greater or equal to the value specified in the Register 455 (Target Time Seconds Register) and Register 456 (Target Time Nanoseconds Register)." "0,1"
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bitfld.long 0x0 0. "tssovf,When set  this bit indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF." "0,1"
group.long 0x72C++0x3
line.long 0x0 "gmacgrp_pps_control,Controls timestamp Pulse-Per-Second output"
bitfld.long 0x0 5.--6. "trgtmodsel0,This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal" "0,1,2,3"
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bitfld.long 0x0 4. "ppsen0,When set low  Bits[3:0] function as PPSCTRL (backward compatible). When set high  Bits[3:0] function as PPSCMD." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "ppsctrl_ppscmd,PPSCTRL0: PPS0 Output Frequency Control"
rgroup.long 0x730++0x7
line.long 0x0 "gmacgrp_auxiliary_timestamp_nanoseconds,This register. along with Register 461 (Auxiliary Timestamp Seconds Register). gives the 64-bit timestamp stored as auxiliary snapshot. The two registers together form the read port of a 64-bit wide FIFO with a.."
hexmask.long 0x0 0.--30. 1. "auxtslo,Contains the lower 32 bits (nano-seconds field) of the auxiliary timestamp."
line.long 0x4 "gmacgrp_auxiliary_timestamp_seconds,Contains the higher 32 bits (Seconds field) of the auxiliary timestamp."
hexmask.long 0x4 0.--31. 1. "auxtshi,Contains the higher 32 bits (Seconds field) of the auxiliary timestamp."
group.long 0x760++0x7
line.long 0x0 "gmacgrp_pps0_interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])."
hexmask.long 0x0 0.--31. 1. "ppsint,These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value."
line.long 0x4 "gmacgrp_pps0_width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of the PPS0 signal output (ptp_pps_o[0])."
hexmask.long 0x4 0.--31. 1. "ppswidth,These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value."
group.long 0x800++0x37F
line.long 0x0 "gmacgrp_mac_address16_high,Register 512 (MAC Address16 High Register)"
bitfld.long 0x0 31. "ae,Address Enable" "0,1"
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bitfld.long 0x0 30. "sa,Source Address" "0,1"
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bitfld.long 0x0 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x0 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x0 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x0 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x0 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x0 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "reserved_23_16,Reserved"
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hexmask.long.word 0x0 0.--15. 1. "addrhi,MAC Address16 [47:32]"
line.long 0x4 "gmacgrp_mac_address16_low,Register 513 (MAC Address16 Low Register)"
hexmask.long 0x4 0.--31. 1. "addrlo,MAC Address16 [31:0]"
line.long 0x8 "gmacgrp_mac_address17_high,Register 514 (MAC Address17 High Register)"
bitfld.long 0x8 31. "ae,Address Enable" "0,1"
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bitfld.long 0x8 30. "sa,Source Address" "0,1"
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bitfld.long 0x8 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x8 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x8 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x8 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x8 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x8 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x8 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x8 0.--15. 1. "addrhi,MAC Address18 [47:32]"
line.long 0xC "gmacgrp_mac_address17_low,Register 515 (MAC Address17 Low Register)"
hexmask.long 0xC 0.--31. 1. "addrlo,MAC Address17 [31:0]"
line.long 0x10 "gmacgrp_mac_address18_high,Register 516 (MAC Address18 High Register)"
bitfld.long 0x10 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x10 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x10 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x10 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x10 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x10 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x10 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x10 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x10 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x10 0.--15. 1. "addrhi,MAC Address18 [47:32]"
line.long 0x14 "gmacgrp_mac_address18_low,Register 517 (MAC Address18 Low Register)"
hexmask.long 0x14 0.--31. 1. "addrlo,MAC Address18 [31:0]"
line.long 0x18 "gmacgrp_mac_address19_high,Register 518 (MAC Address19 High Register)"
bitfld.long 0x18 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x18 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x18 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x18 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x18 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x18 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x18 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x18 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x18 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x18 0.--15. 1. "addrhi,MAC Address19 [47:32]"
line.long 0x1C "gmacgrp_mac_address19_low,Register 519 (MAC Address19 Low Register)"
hexmask.long 0x1C 0.--31. 1. "addrlo,MAC Address19 [31:0]"
line.long 0x20 "gmacgrp_mac_address20_high,Register 520 (MAC Address20 High Register)"
bitfld.long 0x20 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x20 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x20 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x20 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x20 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x20 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x20 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x20 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x20 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x20 0.--15. 1. "addrhi,MAC Address20 [47:32]"
line.long 0x24 "gmacgrp_mac_address20_low,Register 521 (MAC Address20 Low Register)"
hexmask.long 0x24 0.--31. 1. "addrlo,MAC Address20 [31:0]"
line.long 0x28 "gmacgrp_mac_address21_high,Register 522 (MAC Address21 High Register)"
bitfld.long 0x28 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x28 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x28 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x28 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x28 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x28 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x28 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x28 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x28 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x28 0.--15. 1. "addrhi,MAC Address21 [47:32]"
line.long 0x2C "gmacgrp_mac_address21_low,Register 523 (MAC Address21 Low Register)"
hexmask.long 0x2C 0.--31. 1. "addrlo,MAC Address21 [31:0]"
line.long 0x30 "gmacgrp_mac_address22_high,Register 524 (MAC Address22 High Register)"
bitfld.long 0x30 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x30 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x30 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x30 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x30 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x30 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x30 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x30 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x30 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x30 0.--15. 1. "addrhi,MAC Address22 [47:32]"
line.long 0x34 "gmacgrp_mac_address22_low,Register 525 (MAC Address22 Low Register)"
hexmask.long 0x34 0.--31. 1. "addrlo,MAC Address22 [31:0]"
line.long 0x38 "gmacgrp_mac_address23_high,Register 526 (MAC Address23 High Register"
bitfld.long 0x38 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x38 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x38 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x38 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x38 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x38 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x38 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x38 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x38 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x38 0.--15. 1. "addrhi,MAC Address23 [47:32]"
line.long 0x3C "gmacgrp_mac_address23_low,Register 527 (MAC Address23 Low Register)"
hexmask.long 0x3C 0.--31. 1. "addrlo,MAC Address23 [31:0]"
line.long 0x40 "gmacgrp_mac_address24_high,Register 528 (MAC Address24 High Register)"
bitfld.long 0x40 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x40 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x40 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x40 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x40 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x40 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x40 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x40 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x40 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x40 0.--15. 1. "addrhi,MAC Address1 [47:32]"
line.long 0x44 "gmacgrp_mac_address24_low,Register 529 (MAC Address24 Low Register)"
hexmask.long 0x44 0.--31. 1. "addrlo,MAC Address24 [31:0]"
line.long 0x48 "gmacgrp_mac_address25_high,Register 530 (MAC Address25 High Register)"
bitfld.long 0x48 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x48 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x48 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x48 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x48 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x48 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x48 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x48 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x48 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x48 0.--15. 1. "addrhi,MAC Address25 [47:32]"
line.long 0x4C "gmacgrp_mac_address25_low,Register 531 (MAC Address25 Low Register)"
hexmask.long 0x4C 0.--31. 1. "addrlo,MAC Address25 [31:0]"
line.long 0x50 "gmacgrp_mac_address26_high,Register 532 (MAC Address26 High Register)"
bitfld.long 0x50 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x50 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x50 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x50 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x50 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x50 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x50 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x50 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x50 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x50 0.--15. 1. "addrhi,MAC Address26 [47:32]"
line.long 0x54 "gmacgrp_mac_address26_low,Register 533 (MAC Address26 Low Register)"
hexmask.long 0x54 0.--31. 1. "addrlo,MAC Address26 [31:0]"
line.long 0x58 "gmacgrp_mac_address27_high,Register 534 (MAC Address27 High Register)"
bitfld.long 0x58 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x58 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x58 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x58 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x58 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x58 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x58 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x58 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x58 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x58 0.--15. 1. "addrhi,MAC Address27 [47:32]"
line.long 0x5C "gmacgrp_mac_address27_low,Register 535 (MAC Address27 Low Register)"
hexmask.long 0x5C 0.--31. 1. "addrlo,MAC Address27 [31:0]"
line.long 0x60 "gmacgrp_mac_address28_high,Register 536 (MAC Address28 High Register)"
bitfld.long 0x60 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x60 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x60 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x60 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x60 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x60 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x60 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x60 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x60 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x60 0.--15. 1. "addrhi,MAC Address28 [47:32]"
line.long 0x64 "gmacgrp_mac_address28_low,Register 537 (MAC Address28 Low Register)"
hexmask.long 0x64 0.--31. 1. "addrlo,MAC Address28 [31:0]"
line.long 0x68 "gmacgrp_mac_address29_high,Register 538 (MAC Address29 High Register)"
bitfld.long 0x68 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x68 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x68 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x68 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x68 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x68 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x68 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x68 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x68 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x68 0.--15. 1. "addrhi,MAC Address29 [47:32]"
line.long 0x6C "gmacgrp_mac_address29_low,Register 539 (MAC Address29 Low Register)"
hexmask.long 0x6C 0.--31. 1. "addrlo,MAC Address29 [31:0]"
line.long 0x70 "gmacgrp_mac_address30_high,Register 540 (MAC Address30 High Register)"
bitfld.long 0x70 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x70 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x70 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x70 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x70 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x70 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x70 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x70 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x70 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x70 0.--15. 1. "addrhi,MAC Address30 [47:32]"
line.long 0x74 "gmacgrp_mac_address30_low,Register 541 (MAC Address30 Low Register)"
hexmask.long 0x74 0.--31. 1. "addrlo,MAC Address30 [31:0]"
line.long 0x78 "gmacgrp_mac_address31_high,Register 542 (MAC Address31 High Register)"
bitfld.long 0x78 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x78 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x78 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x78 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x78 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x78 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x78 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x78 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x78 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x78 0.--15. 1. "addrhi,MAC Address31 [47:32]"
line.long 0x7C "gmacgrp_mac_address31_low,Register 543 (MAC Address31 Low Register)"
hexmask.long 0x7C 0.--31. 1. "addrlo,MAC Address31 [31:0]"
line.long 0x80 "gmacgrp_mac_address32_high,Register 544 (MAC Address32 High Register)"
bitfld.long 0x80 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x80 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x80 0.--15. 1. "addrhi,MAC Address32 [47:32]"
line.long 0x84 "gmacgrp_mac_address32_low,Register 545 (MAC Address32 Low Register)"
hexmask.long 0x84 0.--31. 1. "addrlo,MAC Address32 [31:0]"
line.long 0x88 "gmacgrp_mac_address33_high,Register 546 (MAC Address33 High Register)"
bitfld.long 0x88 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x88 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x88 0.--15. 1. "addrhi,MAC Address33 [47:32]"
line.long 0x8C "gmacgrp_mac_address33_low,Register 547 (MAC Address33 Low Register)"
hexmask.long 0x8C 0.--31. 1. "addrlo,MAC Address33 [31:0]"
line.long 0x90 "gmacgrp_mac_address34_high,Register 548 (MAC Address34 High Register)"
bitfld.long 0x90 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x90 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x90 0.--15. 1. "addrhi,MAC Address34 [47:32]"
line.long 0x94 "gmacgrp_mac_address34_low,Register 549 (MAC Address34 Low Register)"
hexmask.long 0x94 0.--31. 1. "addrlo,MAC Address34 [31:0]"
line.long 0x98 "gmacgrp_mac_address35_high,Register 550 (MAC Address35 High Register)"
bitfld.long 0x98 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x98 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x98 0.--15. 1. "addrhi,MAC Address35 [47:32]"
line.long 0x9C "gmacgrp_mac_address35_low,Register 551 (MAC Address35 Low Register)"
hexmask.long 0x9C 0.--31. 1. "addrlo,MAC Address35 [31:0]"
line.long 0xA0 "gmacgrp_mac_address36_high,Register 552 (MAC Address36 High Register)"
bitfld.long 0xA0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xA0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xA0 0.--15. 1. "addrhi,MAC Address36 [47:32]"
line.long 0xA4 "gmacgrp_mac_address36_low,Register 553 (MAC Address36 Low Register)"
hexmask.long 0xA4 0.--31. 1. "addrlo,MAC Address36 [31:0]"
line.long 0xA8 "gmacgrp_mac_address37_high,Register 554 (MAC Address37 High Register)"
bitfld.long 0xA8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xA8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xA8 0.--15. 1. "addrhi,MAC Address37 [47:32]"
line.long 0xAC "gmacgrp_mac_address37_low,Register 555 (MAC Address37 Low Register)"
hexmask.long 0xAC 0.--31. 1. "addrlo,MAC Address37 [31:0]"
line.long 0xB0 "gmacgrp_mac_address38_high,Register 556 (MAC Address38 High Register)"
bitfld.long 0xB0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xB0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xB0 0.--15. 1. "addrhi,MAC Address38 [47:32]"
line.long 0xB4 "gmacgrp_mac_address38_low,Register 557 (MAC Address38 Low Register)"
hexmask.long 0xB4 0.--31. 1. "addrlo,MAC Address38 [31:0]"
line.long 0xB8 "gmacgrp_mac_address39_high,Register 558 (MAC Address39 High Register)"
bitfld.long 0xB8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xB8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xB8 0.--15. 1. "addrhi,MAC Address39 [47:32]"
line.long 0xBC "gmacgrp_mac_address39_low,Register 559 (MAC Address39 Low Register)"
hexmask.long 0xBC 0.--31. 1. "addrlo,MAC Address39 [31:0]"
line.long 0xC0 "gmacgrp_mac_address40_high,Register 560 (MAC Address40 High Register)"
bitfld.long 0xC0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xC0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xC0 0.--15. 1. "addrhi,MAC Address40 [47:32]"
line.long 0xC4 "gmacgrp_mac_address40_low,Register 561 (MAC Address40 Low Register)"
hexmask.long 0xC4 0.--31. 1. "addrlo,MAC Address40 [31:0]"
line.long 0xC8 "gmacgrp_mac_address41_high,Register 562 (MAC Address41 High Register)"
bitfld.long 0xC8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xC8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xC8 0.--15. 1. "addrhi,MAC Address41 [47:32]"
line.long 0xCC "gmacgrp_mac_address41_low,Register 563 (MAC Address41 Low Register)"
hexmask.long 0xCC 0.--31. 1. "addrlo,MAC Address41 [31:0]"
line.long 0xD0 "gmacgrp_mac_address42_high,Register 564 (MAC Address42 High Register)"
bitfld.long 0xD0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xD0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xD0 0.--15. 1. "addrhi,MAC Address42 [47:32]"
line.long 0xD4 "gmacgrp_mac_address42_low,Register 565 (MAC Address42 Low Register)"
hexmask.long 0xD4 0.--31. 1. "addrlo,MAC Address42 [31:0]"
line.long 0xD8 "gmacgrp_mac_address43_high,Register 566 (MAC Address43 High Register)"
bitfld.long 0xD8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xD8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xD8 0.--15. 1. "addrhi,MAC Address43 [47:32]"
line.long 0xDC "gmacgrp_mac_address43_low,Register 567 (MAC Address43 Low Register)"
hexmask.long 0xDC 0.--31. 1. "addrlo,MAC Address43 [31:0]"
line.long 0xE0 "gmacgrp_mac_address44_high,Register 568 (MAC Address44 High Register)"
bitfld.long 0xE0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xE0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xE0 0.--15. 1. "addrhi,MAC Address44 [47:32]"
line.long 0xE4 "gmacgrp_mac_address44_low,Register 569 (MAC Address44 Low Register)"
hexmask.long 0xE4 0.--31. 1. "addrlo,MAC Address44 [31:0]"
line.long 0xE8 "gmacgrp_mac_address45_high,Register 570 (MAC Address45 High Register)"
bitfld.long 0xE8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xE8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xE8 0.--15. 1. "addrhi,MAC Address45 [47:32]"
line.long 0xEC "gmacgrp_mac_address45_low,Register 571 (MAC Address45 Low Register)"
hexmask.long 0xEC 0.--31. 1. "addrlo,MAC Address45 [31:0]"
line.long 0xF0 "gmacgrp_mac_address46_high,Register 572 (MAC Address46 High Register)"
bitfld.long 0xF0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xF0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xF0 0.--15. 1. "addrhi,MAC Address46 [47:32]"
line.long 0xF4 "gmacgrp_mac_address46_low,Register 573 (MAC Address46 Low Register)"
hexmask.long 0xF4 0.--31. 1. "addrlo,MAC Address46 [31:0]"
line.long 0xF8 "gmacgrp_mac_address47_high,Register 574 (MAC Address47 High Register)"
bitfld.long 0xF8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xF8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xF8 0.--15. 1. "addrhi,MAC Address47 [47:32]"
line.long 0xFC "gmacgrp_mac_address47_low,Register 575 (MAC Address47 Low Register)"
hexmask.long 0xFC 0.--31. 1. "addrlo,MAC Address47 [31:0]"
line.long 0x100 "gmacgrp_mac_address48_high,Register 576 (MAC Address48 High Register)"
bitfld.long 0x100 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x100 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x100 0.--15. 1. "addrhi,MAC Address48 [47:32]"
line.long 0x104 "gmacgrp_mac_address48_low,Register 577 (MAC Address48 Low Register)"
hexmask.long 0x104 0.--31. 1. "addrlo,MAC Address48 [31:0]"
line.long 0x108 "gmacgrp_mac_address49_high,Register 578 (MAC Address49 High Register)"
bitfld.long 0x108 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x108 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x108 0.--15. 1. "addrhi,MAC Address49 [47:32]"
line.long 0x10C "gmacgrp_mac_address49_low,Register 579 (MAC Address49 Low Register)"
hexmask.long 0x10C 0.--31. 1. "addrlo,MAC Address49 [31:0]"
line.long 0x110 "gmacgrp_mac_address50_high,Register 580 (MAC Address50 High Register)"
bitfld.long 0x110 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x110 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x110 0.--15. 1. "addrhi,MAC Address50 [47:32]"
line.long 0x114 "gmacgrp_mac_address50_low,Register 581 (MAC Address50 Low Register)"
hexmask.long 0x114 0.--31. 1. "addrlo,MAC Address50 [31:0]"
line.long 0x118 "gmacgrp_mac_address51_high,Register 582 (MAC Address51 High Register)"
bitfld.long 0x118 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x118 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x118 0.--15. 1. "addrhi,MAC Address51 [47:32]"
line.long 0x11C "gmacgrp_mac_address51_low,Register 583 (MAC Address51 Low Register)"
hexmask.long 0x11C 0.--31. 1. "addrlo,MAC Address51 [31:0]"
line.long 0x120 "gmacgrp_mac_address52_high,Register 584 (MAC Address52 High Register)"
bitfld.long 0x120 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x120 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x120 0.--15. 1. "addrhi,MAC Address52 [47:32]"
line.long 0x124 "gmacgrp_mac_address52_low,Register 585 (MAC Address52 Low Register)"
hexmask.long 0x124 0.--31. 1. "addrlo,MAC Address52 [31:0]"
line.long 0x128 "gmacgrp_mac_address53_high,Register 586 (MAC Address53 High Register)"
bitfld.long 0x128 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x128 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x128 0.--15. 1. "addrhi,MAC Address53 [47:32]"
line.long 0x12C "gmacgrp_mac_address53_low,Register 587 (MAC Address53 Low Register)"
hexmask.long 0x12C 0.--31. 1. "addrlo,MAC Address53 [31:0]"
line.long 0x130 "gmacgrp_mac_address54_high,Register 588 (MAC Address54 High Register)"
bitfld.long 0x130 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x130 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x130 0.--15. 1. "addrhi,MAC Address54 [47:32]"
line.long 0x134 "gmacgrp_mac_address54_low,Register 589 (MAC Address54 Low Register)"
hexmask.long 0x134 0.--31. 1. "addrlo,MAC Address54 [31:0]"
line.long 0x138 "gmacgrp_mac_address55_high,Register 590 (MAC Address55 High Register)"
bitfld.long 0x138 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x138 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x138 0.--15. 1. "addrhi,MAC Address55 [47:32]"
line.long 0x13C "gmacgrp_mac_address55_low,Register 591 (MAC Address55 Low Register)"
hexmask.long 0x13C 0.--31. 1. "addrlo,MAC Address55 [31:0]"
line.long 0x140 "gmacgrp_mac_address56_high,Register 592 (MAC Address56 High Register)"
bitfld.long 0x140 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x140 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x140 0.--15. 1. "addrhi,MAC Address56 [47:32]"
line.long 0x144 "gmacgrp_mac_address56_low,Register 593 (MAC Address56 Low Register)"
hexmask.long 0x144 0.--31. 1. "addrlo,MAC Address56 [31:0]"
line.long 0x148 "gmacgrp_mac_address57_high,Register 594 (MAC Address57 High Register)"
bitfld.long 0x148 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x148 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x148 0.--15. 1. "addrhi,MAC Address57 [47:32]"
line.long 0x14C "gmacgrp_mac_address57_low,Register 595 (MAC Address57 Low Register)"
hexmask.long 0x14C 0.--31. 1. "addrlo,MAC Address57 [31:0]"
line.long 0x150 "gmacgrp_mac_address58_high,Register 596 (MAC Address58 High Register)"
bitfld.long 0x150 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x150 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x150 0.--15. 1. "addrhi,MAC Address58 [47:32]"
line.long 0x154 "gmacgrp_mac_address58_low,Register 597 (MAC Address58 Low Register)"
hexmask.long 0x154 0.--31. 1. "addrlo,MAC Address58 [31:0]"
line.long 0x158 "gmacgrp_mac_address59_high,Register 598 (MAC Address59 High Register)"
bitfld.long 0x158 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x158 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x158 0.--15. 1. "addrhi,MAC Address59 [47:32]"
line.long 0x15C "gmacgrp_mac_address59_low,Register 599 (MAC Address59 Low Register)"
hexmask.long 0x15C 0.--31. 1. "addrlo,MAC Address59 [31:0]"
line.long 0x160 "gmacgrp_mac_address60_high,Register 600 (MAC Address60 High Register)"
bitfld.long 0x160 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x160 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x160 0.--15. 1. "addrhi,MAC Address60 [47:32]"
line.long 0x164 "gmacgrp_mac_address60_low,Register 601 (MAC Address60 Low Register)"
hexmask.long 0x164 0.--31. 1. "addrlo,MAC Address60 [31:0]"
line.long 0x168 "gmacgrp_mac_address61_high,Register 602 (MAC Address61 High Register)"
bitfld.long 0x168 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x168 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x168 0.--15. 1. "addrhi,MAC Address61 [47:32]"
line.long 0x16C "gmacgrp_mac_address61_low,Register 603 (MAC Address61 Low Register)"
hexmask.long 0x16C 0.--31. 1. "addrlo,MAC Address61 [31:0]"
line.long 0x170 "gmacgrp_mac_address62_high,Register 604 (MAC Address62 High Register)"
bitfld.long 0x170 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x170 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x170 0.--15. 1. "addrhi,MAC Address62 [47:32]"
line.long 0x174 "gmacgrp_mac_address62_low,Register 605 (MAC Address62 Low Register)"
hexmask.long 0x174 0.--31. 1. "addrlo,MAC Address62 [31:0]"
line.long 0x178 "gmacgrp_mac_address63_high,Register 606 (MAC Address63 High Register)"
bitfld.long 0x178 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x178 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x178 0.--15. 1. "addrhi,MAC Address63 [47:32]"
line.long 0x17C "gmacgrp_mac_address63_low,Register 607 (MAC Address63 Low Register)"
hexmask.long 0x17C 0.--31. 1. "addrlo,MAC Address63 [31:0]"
line.long 0x180 "gmacgrp_mac_address64_high,Register 608 (MAC Address64 High Register)"
bitfld.long 0x180 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x180 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x180 0.--15. 1. "addrhi,MAC Address64 [47:32]"
line.long 0x184 "gmacgrp_mac_address64_low,Register 609 (MAC Address64 Low Register)"
hexmask.long 0x184 0.--31. 1. "addrlo,MAC Address64 [31:0]"
line.long 0x188 "gmacgrp_mac_address65_high,Register 610 (MAC Address65 High Register)"
bitfld.long 0x188 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x188 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x188 0.--15. 1. "addrhi,MAC Address65 [47:32]"
line.long 0x18C "gmacgrp_mac_address65_low,Register 611 (MAC Address65 Low Register)"
hexmask.long 0x18C 0.--31. 1. "addrlo,MAC Address65 [31:0]"
line.long 0x190 "gmacgrp_mac_address66_high,Register 612 (MAC Address66 High Register)"
bitfld.long 0x190 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x190 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x190 0.--15. 1. "addrhi,MAC Address66 [47:32]"
line.long 0x194 "gmacgrp_mac_address66_low,Register 613 (MAC Address66 Low Register)"
hexmask.long 0x194 0.--31. 1. "addrlo,MAC Address66 [31:0]"
line.long 0x198 "gmacgrp_mac_address67_high,Register 614 (MAC Address67 High Register)"
bitfld.long 0x198 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x198 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x198 0.--15. 1. "addrhi,MAC Address67 [47:32]"
line.long 0x19C "gmacgrp_mac_address67_low,Register 615 (MAC Address67 Low Register)"
hexmask.long 0x19C 0.--31. 1. "addrlo,MAC Address67 [31:0]"
line.long 0x1A0 "gmacgrp_mac_address68_high,Register 616 (MAC Address68 High Register)"
bitfld.long 0x1A0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1A0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1A0 0.--15. 1. "addrhi,MAC Address68 [47:32]"
line.long 0x1A4 "gmacgrp_mac_address68_low,Register 617 (MAC Address68 Low Register)"
hexmask.long 0x1A4 0.--31. 1. "addrlo,MAC Address68 [31:0]"
line.long 0x1A8 "gmacgrp_mac_address69_high,Register 618 (MAC Address69 High Register)"
bitfld.long 0x1A8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1A8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1A8 0.--15. 1. "addrhi,MAC Address69 [47:32]"
line.long 0x1AC "gmacgrp_mac_address69_low,Register 619 (MAC Address69 Low Register)"
hexmask.long 0x1AC 0.--31. 1. "addrlo,MAC Address69 [31:0]"
line.long 0x1B0 "gmacgrp_mac_address70_high,Register 620 (MAC Address70 High Register)"
bitfld.long 0x1B0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1B0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1B0 0.--15. 1. "addrhi,MAC Address70 [47:32]"
line.long 0x1B4 "gmacgrp_mac_address70_low,Register 621 (MAC Address70 Low Register)"
hexmask.long 0x1B4 0.--31. 1. "addrlo,MAC Address70 [31:0]"
line.long 0x1B8 "gmacgrp_mac_address71_high,Register 622 (MAC Address71 High Register)"
bitfld.long 0x1B8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1B8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1B8 0.--15. 1. "addrhi,MAC Address71 [47:32]"
line.long 0x1BC "gmacgrp_mac_address71_low,Register 623 (MAC Address71 Low Register)"
hexmask.long 0x1BC 0.--31. 1. "addrlo,MAC Address71 [31:0]"
line.long 0x1C0 "gmacgrp_mac_address72_high,Register 624 (MAC Address72 High Register)"
bitfld.long 0x1C0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1C0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1C0 0.--15. 1. "addrhi,MAC Address72 [47:32]"
line.long 0x1C4 "gmacgrp_mac_address72_low,Register 625 (MAC Address72 Low Register)"
hexmask.long 0x1C4 0.--31. 1. "addrlo,MAC Address72 [31:0]"
line.long 0x1C8 "gmacgrp_mac_address73_high,Register 626 (MAC Address73 High Register)"
bitfld.long 0x1C8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1C8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1C8 0.--15. 1. "addrhi,MAC Address73 [47:32]"
line.long 0x1CC "gmacgrp_mac_address73_low,Register 627 (MAC Address73 Low Register)"
hexmask.long 0x1CC 0.--31. 1. "addrlo,MAC Address73 [31:0]"
line.long 0x1D0 "gmacgrp_mac_address74_high,Register 628 (MAC Address74 High Register)"
bitfld.long 0x1D0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1D0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1D0 0.--15. 1. "addrhi,MAC Address74 [47:32]"
line.long 0x1D4 "gmacgrp_mac_address74_low,Register 629 (MAC Address74 Low Register)"
hexmask.long 0x1D4 0.--31. 1. "addrlo,MAC Address74 [31:0]"
line.long 0x1D8 "gmacgrp_mac_address75_high,Register 630 (MAC Address75 High Register)"
bitfld.long 0x1D8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1D8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1D8 0.--15. 1. "addrhi,MAC Address75 [47:32]"
line.long 0x1DC "gmacgrp_mac_address75_low,Register 631 (MAC Address75 Low Register)"
hexmask.long 0x1DC 0.--31. 1. "addrlo,MAC Address75 [31:0]"
line.long 0x1E0 "gmacgrp_mac_address76_high,Register 632 (MAC Address76 High Register)"
bitfld.long 0x1E0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1E0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1E0 0.--15. 1. "addrhi,MAC Address76 [47:32]"
line.long 0x1E4 "gmacgrp_mac_address76_low,Register 633 (MAC Address76 Low Register)"
hexmask.long 0x1E4 0.--31. 1. "addrlo,MAC Address76 [31:0]"
line.long 0x1E8 "gmacgrp_mac_address77_high,Register 634 (MAC Address77 High Register)"
bitfld.long 0x1E8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1E8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1E8 0.--15. 1. "addrhi,MAC Address77 [47:32]"
line.long 0x1EC "gmacgrp_mac_address77_low,Register 635 (MAC Address77 Low Register)"
hexmask.long 0x1EC 0.--31. 1. "addrlo,MAC Address77 [31:0]"
line.long 0x1F0 "gmacgrp_mac_address78_high,Register 636 (MAC Address78 High Register)"
bitfld.long 0x1F0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1F0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1F0 0.--15. 1. "addrhi,MAC Address78 [47:32]"
line.long 0x1F4 "gmacgrp_mac_address78_low,Register 637 (MAC Address78 Low Register)"
hexmask.long 0x1F4 0.--31. 1. "addrlo,MAC Address78 [31:0]"
line.long 0x1F8 "gmacgrp_mac_address79_high,Register 638 (MAC Address79 High Register)"
bitfld.long 0x1F8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1F8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1F8 0.--15. 1. "addrhi,MAC Address79 [47:32]"
line.long 0x1FC "gmacgrp_mac_address79_low,Register 639 (MAC Address79 Low Register)"
hexmask.long 0x1FC 0.--31. 1. "addrlo,MAC Address79 [31:0]"
line.long 0x200 "gmacgrp_mac_address80_high,Register 640 (MAC Address80 High Register)"
bitfld.long 0x200 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x200 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x200 0.--15. 1. "addrhi,MAC Address80 [47:32]"
line.long 0x204 "gmacgrp_mac_address80_low,Register 641 (MAC Address80 Low Register)"
hexmask.long 0x204 0.--31. 1. "addrlo,MAC Address80 [31:0]"
line.long 0x208 "gmacgrp_mac_address81_high,Register 642 (MAC Address81 High Register)"
bitfld.long 0x208 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x208 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x208 0.--15. 1. "addrhi,MAC Address81 [47:32]"
line.long 0x20C "gmacgrp_mac_address81_low,Register 643 (MAC Address81 Low Register)"
hexmask.long 0x20C 0.--31. 1. "addrlo,MAC Address81 [31:0]"
line.long 0x210 "gmacgrp_mac_address82_high,Register 644 (MAC Address82 High Register)"
bitfld.long 0x210 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x210 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x210 0.--15. 1. "addrhi,MAC Address82 [47:32]"
line.long 0x214 "gmacgrp_mac_address82_low,Register 645 (MAC Address82 Low Register)"
hexmask.long 0x214 0.--31. 1. "addrlo,MAC Address82 [31:0]"
line.long 0x218 "gmacgrp_mac_address83_high,Register 646 (MAC Address83 High Register)"
bitfld.long 0x218 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x218 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x218 0.--15. 1. "addrhi,MAC Address83 [47:32]"
line.long 0x21C "gmacgrp_mac_address83_low,Register 647 (MAC Address83 Low Register)"
hexmask.long 0x21C 0.--31. 1. "addrlo,MAC Address83 [31:0]"
line.long 0x220 "gmacgrp_mac_address84_high,Register 648 (MAC Address84 High Register)"
bitfld.long 0x220 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x220 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x220 0.--15. 1. "addrhi,MAC Address84 [47:32]"
line.long 0x224 "gmacgrp_mac_address84_low,Register 649 (MAC Address84 Low Register)"
hexmask.long 0x224 0.--31. 1. "addrlo,MAC Address84 [31:0]"
line.long 0x228 "gmacgrp_mac_address85_high,Register 650 (MAC Address85 High Register)"
bitfld.long 0x228 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x228 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x228 0.--15. 1. "addrhi,MAC Address85 [47:32]"
line.long 0x22C "gmacgrp_mac_address85_low,Register 651 (MAC Address85 Low Register)"
hexmask.long 0x22C 0.--31. 1. "addrlo,MAC Address85 [31:0]"
line.long 0x230 "gmacgrp_mac_address86_high,Register 652 (MAC Address86 High Register)"
bitfld.long 0x230 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x230 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x230 0.--15. 1. "addrhi,MAC Address86 [47:32]"
line.long 0x234 "gmacgrp_mac_address86_low,Register 653 (MAC Address86 Low Register)"
hexmask.long 0x234 0.--31. 1. "addrlo,MAC Address86 [31:0]"
line.long 0x238 "gmacgrp_mac_address87_high,Register 654 (MAC Address87 High Register)"
bitfld.long 0x238 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x238 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x238 0.--15. 1. "addrhi,MAC Address87 [47:32]"
line.long 0x23C "gmacgrp_mac_address87_low,Register 655 (MAC Address87 Low Register)"
hexmask.long 0x23C 0.--31. 1. "addrlo,MAC Address87 [31:0]"
line.long 0x240 "gmacgrp_mac_address88_high,Register 656 (MAC Address88 High Register)"
bitfld.long 0x240 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x240 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x240 0.--15. 1. "addrhi,MAC Address88 [47:32]"
line.long 0x244 "gmacgrp_mac_address88_low,Register 657 (MAC Address88 Low Register)"
hexmask.long 0x244 0.--31. 1. "addrlo,MAC Address88 [31:0]"
line.long 0x248 "gmacgrp_mac_address89_high,Register 658 (MAC Address89 High Register)"
bitfld.long 0x248 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x248 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x248 0.--15. 1. "addrhi,MAC Address89 [47:32]"
line.long 0x24C "gmacgrp_mac_address89_low,Register 659 (MAC Address89 Low Register)"
hexmask.long 0x24C 0.--31. 1. "addrlo,MAC Address89 [31:0]"
line.long 0x250 "gmacgrp_mac_address90_high,Register 660 (MAC Address90 High Register)"
bitfld.long 0x250 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x250 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x250 0.--15. 1. "addrhi,MAC Address90 [47:32]"
line.long 0x254 "gmacgrp_mac_address90_low,Register 661 (MAC Address90 Low Register)"
hexmask.long 0x254 0.--31. 1. "addrlo,MAC Address90 [31:0]"
line.long 0x258 "gmacgrp_mac_address91_high,Register 662 (MAC Address91 High Register)"
bitfld.long 0x258 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x258 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x258 0.--15. 1. "addrhi,MAC Address91 [47:32]"
line.long 0x25C "gmacgrp_mac_address91_low,Register 663 (MAC Address91 Low Register)"
hexmask.long 0x25C 0.--31. 1. "addrlo,MAC Address91 [31:0]"
line.long 0x260 "gmacgrp_mac_address92_high,Register 664 (MAC Address92 High Register)"
bitfld.long 0x260 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x260 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x260 0.--15. 1. "addrhi,MAC Address92 [47:32]"
line.long 0x264 "gmacgrp_mac_address92_low,Register 665 (MAC Address92 Low Register)"
hexmask.long 0x264 0.--31. 1. "addrlo,MAC Address92 [31:0]"
line.long 0x268 "gmacgrp_mac_address93_high,Register 666 (MAC Address93 High Register)"
bitfld.long 0x268 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x268 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x268 0.--15. 1. "addrhi,MAC Address93 [47:32]"
line.long 0x26C "gmacgrp_mac_address93_low,Register 667 (MAC Address93 Low Register)"
hexmask.long 0x26C 0.--31. 1. "addrlo,MAC Address93 [31:0]"
line.long 0x270 "gmacgrp_mac_address94_high,Register 668 (MAC Address94 High Register)"
bitfld.long 0x270 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x270 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x270 0.--15. 1. "addrhi,MAC Address94 [47:32]"
line.long 0x274 "gmacgrp_mac_address94_low,Register 669 (MAC Address94 Low Register)"
hexmask.long 0x274 0.--31. 1. "addrlo,MAC Address94 [31:0]"
line.long 0x278 "gmacgrp_mac_address95_high,Register 670 (MAC Address95 High Register)"
bitfld.long 0x278 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x278 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x278 0.--15. 1. "addrhi,MAC Address95 [47:32]"
line.long 0x27C "gmacgrp_mac_address95_low,Register 671 (MAC Address95 Low Register)"
hexmask.long 0x27C 0.--31. 1. "addrlo,MAC Address95 [31:0]"
line.long 0x280 "gmacgrp_mac_address96_high,Register 672 (MAC Address96 High Register)"
bitfld.long 0x280 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x280 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x280 0.--15. 1. "addrhi,MAC Address96 [47:32]"
line.long 0x284 "gmacgrp_mac_address96_low,Register 673 (MAC Address96 Low Register)"
hexmask.long 0x284 0.--31. 1. "addrlo,MAC Address96 [31:0]"
line.long 0x288 "gmacgrp_mac_address97_high,Register 674 (MAC Address97 High Register)"
bitfld.long 0x288 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x288 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x288 0.--15. 1. "addrhi,MAC Address97 [47:32]"
line.long 0x28C "gmacgrp_mac_address97_low,Register 675 (MAC Address97 Low Register)"
hexmask.long 0x28C 0.--31. 1. "addrlo,MAC Address97 [31:0]"
line.long 0x290 "gmacgrp_mac_address98_high,Register 676 (MAC Address98 High Register)"
bitfld.long 0x290 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x290 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x290 0.--15. 1. "addrhi,MAC Address98 [47:32]"
line.long 0x294 "gmacgrp_mac_address98_low,Register 677 (MAC Address98 Low Register)"
hexmask.long 0x294 0.--31. 1. "addrlo,MAC Address98 [31:0]"
line.long 0x298 "gmacgrp_mac_address99_high,Register 678 (MAC Address99 High Register)"
bitfld.long 0x298 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x298 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x298 0.--15. 1. "addrhi,MAC Address99 [47:32]"
line.long 0x29C "gmacgrp_mac_address99_low,Register 679 (MAC Address99 Low Register)"
hexmask.long 0x29C 0.--31. 1. "addrlo,MAC Address99 [31:0]"
line.long 0x2A0 "gmacgrp_mac_address100_high,Register 680 (MAC Address100 High Register)"
bitfld.long 0x2A0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2A0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2A0 0.--15. 1. "addrhi,MAC Address100 [47:32]"
line.long 0x2A4 "gmacgrp_mac_address100_low,Register 681 (MAC Address100 Low Register)"
hexmask.long 0x2A4 0.--31. 1. "addrlo,MAC Address100 [31:0]"
line.long 0x2A8 "gmacgrp_mac_address101_high,Register 682 (MAC Address101 High Register)"
bitfld.long 0x2A8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2A8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2A8 0.--15. 1. "addrhi,MAC Address101 [47:32]"
line.long 0x2AC "gmacgrp_mac_address101_low,Register 683 (MAC Address101 Low Register)"
hexmask.long 0x2AC 0.--31. 1. "addrlo,MAC Address101 [31:0]"
line.long 0x2B0 "gmacgrp_mac_address102_high,Register 684 (MAC Address102 High Register)"
bitfld.long 0x2B0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2B0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2B0 0.--15. 1. "addrhi,MAC Address102 [47:32]"
line.long 0x2B4 "gmacgrp_mac_address102_low,Register 685 (MAC Address102 Low Register)"
hexmask.long 0x2B4 0.--31. 1. "addrlo,MAC Address102 [31:0]"
line.long 0x2B8 "gmacgrp_mac_address103_high,Register 686 (MAC Address103 High Register)"
bitfld.long 0x2B8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2B8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2B8 0.--15. 1. "addrhi,MAC Address103 [47:32]"
line.long 0x2BC "gmacgrp_mac_address103_low,Register 687 (MAC Address103 Low Register)"
hexmask.long 0x2BC 0.--31. 1. "addrlo,MAC Address103 [31:0]"
line.long 0x2C0 "gmacgrp_mac_address104_high,Register 688 (MAC Address104 High Register)"
bitfld.long 0x2C0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2C0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2C0 0.--15. 1. "addrhi,MAC Address104 [47:32]"
line.long 0x2C4 "gmacgrp_mac_address104_low,Register 689 (MAC Address104 Low Register)"
hexmask.long 0x2C4 0.--31. 1. "addrlo,MAC Address104 [31:0]"
line.long 0x2C8 "gmacgrp_mac_address105_high,Register 690 (MAC Address105 High Register)"
bitfld.long 0x2C8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2C8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2C8 0.--15. 1. "addrhi,MAC Address105 [47:32]"
line.long 0x2CC "gmacgrp_mac_address105_low,Register 691 (MAC Address105 Low Register)"
hexmask.long 0x2CC 0.--31. 1. "addrlo,MAC Address105 [31:0]"
line.long 0x2D0 "gmacgrp_mac_address106_high,Register 692 (MAC Address106 High Register)"
bitfld.long 0x2D0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2D0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2D0 0.--15. 1. "addrhi,MAC Address106 [47:32]"
line.long 0x2D4 "gmacgrp_mac_address106_low,Register 693 (MAC Address106 Low Register)"
hexmask.long 0x2D4 0.--31. 1. "addrlo,MAC Address106 [31:0]"
line.long 0x2D8 "gmacgrp_mac_address107_high,Register 694 (MAC Address107 High Register)"
bitfld.long 0x2D8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2D8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2D8 0.--15. 1. "addrhi,MAC Address107 [47:32]"
line.long 0x2DC "gmacgrp_mac_address107_low,Register 695 (MAC Address107 Low Register)"
hexmask.long 0x2DC 0.--31. 1. "addrlo,MAC Address107 [31:0]"
line.long 0x2E0 "gmacgrp_mac_address108_high,Register 696 (MAC Address108 High Register)"
bitfld.long 0x2E0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2E0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2E0 0.--15. 1. "addrhi,MAC Address108 [47:32]"
line.long 0x2E4 "gmacgrp_mac_address108_low,Register 697 (MAC Address108 Low Register)"
hexmask.long 0x2E4 0.--31. 1. "addrlo,MAC Address108 [31:0]"
line.long 0x2E8 "gmacgrp_mac_address109_high,Register 698 (MAC Address109 High Register)"
bitfld.long 0x2E8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2E8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2E8 0.--15. 1. "addrhi,MAC Address109 [47:32]"
line.long 0x2EC "gmacgrp_mac_address109_low,Register 699 (MAC Address109 Low Register)"
hexmask.long 0x2EC 0.--31. 1. "addrlo,MAC Address109 [31:0]"
line.long 0x2F0 "gmacgrp_mac_address110_high,Register XXX (MAC AddressXX High Register)"
bitfld.long 0x2F0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2F0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2F0 0.--15. 1. "addrhi,MAC Address110 [47:32]"
line.long 0x2F4 "gmacgrp_mac_address110_low,Register 700 (MAC Address110 Low Register)"
hexmask.long 0x2F4 0.--31. 1. "addrlo,MAC Address110 [31:0]"
line.long 0x2F8 "gmacgrp_mac_address111_high,Register 701 (MAC Address111 High Register)"
bitfld.long 0x2F8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2F8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2F8 0.--15. 1. "addrhi,MAC Address111 [47:32]"
line.long 0x2FC "gmacgrp_mac_address111_low,Register 702 (MAC Address111 Low Register)"
hexmask.long 0x2FC 0.--31. 1. "addrlo,MAC Address111 [31:0]"
line.long 0x300 "gmacgrp_mac_address112_high,Register 703 (MAC Address112 High Register)"
bitfld.long 0x300 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x300 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x300 0.--15. 1. "addrhi,MAC Address112 [47:32]"
line.long 0x304 "gmacgrp_mac_address112_low,Register 704 (MAC Address112 Low Register)"
hexmask.long 0x304 0.--31. 1. "addrlo,MAC Address112 [31:0]"
line.long 0x308 "gmacgrp_mac_address113_high,Register 705 (MAC Address113 High Register)"
bitfld.long 0x308 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x308 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x308 0.--15. 1. "addrhi,MAC Address113 [47:32]"
line.long 0x30C "gmacgrp_mac_address113_low,Register 706 (MAC Address113 Low Register)"
hexmask.long 0x30C 0.--31. 1. "addrlo,MAC Address113 [31:0]"
line.long 0x310 "gmacgrp_mac_address114_high,Register 707 (MAC Address114 High Register)"
bitfld.long 0x310 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x310 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x310 0.--15. 1. "addrhi,MAC Address114 [47:32]"
line.long 0x314 "gmacgrp_mac_address114_low,Register 708 (MAC Address114 Low Register)"
hexmask.long 0x314 0.--31. 1. "addrlo,MAC Address114 [31:0]"
line.long 0x318 "gmacgrp_mac_address115_high,Register 709 (MAC Address115 High Register)"
bitfld.long 0x318 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x318 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x318 0.--15. 1. "addrhi,MAC Address115 [47:32]"
line.long 0x31C "gmacgrp_mac_address115_low,Register 710 (MAC Address115 Low Register)"
hexmask.long 0x31C 0.--31. 1. "addrlo,MAC Address115 [31:0]"
line.long 0x320 "gmacgrp_mac_address116_high,Register 711 (MAC Address116 High Register)"
bitfld.long 0x320 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x320 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x320 0.--15. 1. "addrhi,MAC Address116 [47:32]"
line.long 0x324 "gmacgrp_mac_address116_low,Register 712 (MAC Address116 Low Register)"
hexmask.long 0x324 0.--31. 1. "addrlo,MAC Address116 [31:0]"
line.long 0x328 "gmacgrp_mac_address117_high,Register 713 (MAC Address117 High Register)"
bitfld.long 0x328 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x328 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x328 0.--15. 1. "addrhi,MAC Address117 [47:32]"
line.long 0x32C "gmacgrp_mac_address117_low,Register 714 (MAC Address117 Low Register)"
hexmask.long 0x32C 0.--31. 1. "addrlo,MAC Address117 [31:0]"
line.long 0x330 "gmacgrp_mac_address118_high,Register 715 (MAC Address118 High Register)"
bitfld.long 0x330 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x330 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x330 0.--15. 1. "addrhi,MAC Address118 [47:32]"
line.long 0x334 "gmacgrp_mac_address118_low,Register 716 (MAC Address118 Low Register)"
hexmask.long 0x334 0.--31. 1. "addrlo,MAC Address118 [31:0]"
line.long 0x338 "gmacgrp_mac_address119_high,Register 717 (MAC Address119 High Register)"
bitfld.long 0x338 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x338 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x338 0.--15. 1. "addrhi,MAC Address119 [47:32]"
line.long 0x33C "gmacgrp_mac_address119_low,Register 718 (MAC Address119 Low Register)"
hexmask.long 0x33C 0.--31. 1. "addrlo,MAC Address119 [31:0]"
line.long 0x340 "gmacgrp_mac_address120_high,Register 719 (MAC Address120 High Register)"
bitfld.long 0x340 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x340 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x340 0.--15. 1. "addrhi,MAC Address120 [47:32]"
line.long 0x344 "gmacgrp_mac_address120_low,Register 720 (MAC Address120 Low Register)"
hexmask.long 0x344 0.--31. 1. "addrlo,MAC Address120 [31:0]"
line.long 0x348 "gmacgrp_mac_address121_high,Register 721 (MAC Address121 High Register)"
bitfld.long 0x348 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x348 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x348 0.--15. 1. "addrhi,MAC Address121 [47:32]"
line.long 0x34C "gmacgrp_mac_address121_low,Register 722 (MAC Address121 Low Register)"
hexmask.long 0x34C 0.--31. 1. "addrlo,MAC Address121 [31:0]"
line.long 0x350 "gmacgrp_mac_address122_high,Register 723 (MAC Address122 High Register)"
bitfld.long 0x350 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x350 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x350 0.--15. 1. "addrhi,MAC Address122 [47:32]"
line.long 0x354 "gmacgrp_mac_address122_low,Register 724 (MAC Address122 Low Register)"
hexmask.long 0x354 0.--31. 1. "addrlo,MAC Address122 [31:0]"
line.long 0x358 "gmacgrp_mac_address123_high,Register 725 (MAC Address123 High Register)"
bitfld.long 0x358 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x358 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x358 0.--15. 1. "addrhi,MAC Address123 [47:32]"
line.long 0x35C "gmacgrp_mac_address123_low,Register 726 (MAC AddressXX 123 Register)"
hexmask.long 0x35C 0.--31. 1. "addrlo,MAC Address123 [31:0]"
line.long 0x360 "gmacgrp_mac_address124_high,Register 727 (MAC Address124 High Register)"
bitfld.long 0x360 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x360 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x360 0.--15. 1. "addrhi,MAC Address124 [47:32]"
line.long 0x364 "gmacgrp_mac_address124_low,Register 728 (MAC Address124 Low Register)"
hexmask.long 0x364 0.--31. 1. "addrlo,MAC Address124 [31:0]"
line.long 0x368 "gmacgrp_mac_address125_high,Register 729 (MAC Address125 High Register)"
bitfld.long 0x368 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x368 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x368 0.--15. 1. "addrhi,MAC Address125 [47:32]"
line.long 0x36C "gmacgrp_mac_address125_low,Register 730 (MAC Address125 Low Register)"
hexmask.long 0x36C 0.--31. 1. "addrlo,MAC Address125 [31:0]"
line.long 0x370 "gmacgrp_mac_address126_high,Register 731 (MAC Address126 High Register)"
bitfld.long 0x370 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x370 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x370 0.--15. 1. "addrhi,MAC Address126 [47:32]"
line.long 0x374 "gmacgrp_mac_address126_low,Register 732 (MAC Address126 Low Register)"
hexmask.long 0x374 0.--31. 1. "addrlo,MAC Address126 [31:0]"
line.long 0x378 "gmacgrp_mac_address127_high,Register 733 (MAC Address127 High Register)"
bitfld.long 0x378 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x378 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x378 0.--15. 1. "addrhi,MAC Address127 [47:32]"
line.long 0x37C "gmacgrp_mac_address127_low,Register 734 (MAC Address127 Low Register)"
hexmask.long 0x37C 0.--31. 1. "addrlo,MAC Address127 [31:0]"
group.long 0x1000++0x1F
line.long 0x0 "dmagrp_bus_mode,Register 0 (Bus Mode Register)"
bitfld.long 0x0 31. "rib,Rebuild INCRx Burst" "0,1"
newline
rbitfld.long 0x0 30. "reserved_30,Reserved" "0,1"
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bitfld.long 0x0 28.--29. "prwg,Channel Priority Weights" "0: The priority weight is 1,1: The priority weight is 2,?,?"
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bitfld.long 0x0 27. "txpr,Transmit Priority" "0,1"
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bitfld.long 0x0 26. "mb,Mixed Burst" "0,1"
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bitfld.long 0x0 25. "aal,Address Aligned Beats" "0,1"
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bitfld.long 0x0 24. "eightxpbl,PBLx8 Mode" "0,1"
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bitfld.long 0x0 23. "usp,Use Seperate PBL" "0,1"
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hexmask.long.byte 0x0 17.--22. 1. "rpbl,Rx DMA PBL"
newline
bitfld.long 0x0 16. "fb,Fixed Burst" "0,1"
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bitfld.long 0x0 14.--15. "pr,Priority Ratio" "0: The Priority Ratio is,1: The Priority Ratio is,2: 1,3: 1"
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hexmask.long.byte 0x0 8.--13. 1. "pbl,Programmable Burst Length"
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bitfld.long 0x0 7. "atds,Alternate Descriptor Size" "0,1"
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hexmask.long.byte 0x0 2.--6. 1. "dsl,Descriptor Skip Length"
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bitfld.long 0x0 1. "da,DMA Arbitration Scheme" "0: Weighted round-robin with Rx:Tx or Tx:Rx,1: Fixed priority"
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bitfld.long 0x0 0. "swr,Software Reset" "0,1"
line.long 0x4 "dmagrp_transmit_poll_demand,Register 1 (Transmit Poll Demand Register)"
hexmask.long 0x4 0.--31. 1. "tpd,Transmit Poll Demand"
line.long 0x8 "dmagrp_receive_poll_demand,Register 2 (Receive Poll Demand Register)"
hexmask.long 0x8 0.--31. 1. "rpd,Receive Poll Demand"
line.long 0xC "dmagrp_receive_descriptor_list_address,Register 3 (Receive Descriptor List Address Register)"
hexmask.long 0xC 2.--31. 1. "rdesla_32bit,This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB bits (1:0) are ignored (32-bit wide bus) and internally taken as all-zero by the DMA. Therefore  these LSB bits are read-only (RO)."
line.long 0x10 "dmagrp_transmit_descriptor_list_address,Register 4 (Transmit Descriptor List Address Register)"
hexmask.long 0x10 2.--31. 1. "tdesla_32bit,This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (1:0) are ignored (32-bit wide bus) and are internally taken as all-zero by the DMA. Therefore  these LSB bits are read-only (RO)."
line.long 0x14 "dmagrp_status,Register 5 (Status Register)"
rbitfld.long 0x14 31. "reserved_31,Reserved" "0,1"
newline
rbitfld.long 0x14 30. "glpii,GMAC LPI Interrupt (for Channel 0)" "0,1"
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rbitfld.long 0x14 29. "tti,Timestamp Trigger Interrupt" "0,1"
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rbitfld.long 0x14 28. "gpi,GMAC PMT Interrupt" "0,1"
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rbitfld.long 0x14 27. "gmi,GMAC MMC Interrupt" "0,1"
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rbitfld.long 0x14 26. "gli,GMAC Line interface Interrupt" "0,1"
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rbitfld.long 0x14 23.--25. "eb,Error Bits" "0: Error during Rx DMA Descriptor Read Access,1: Error during Tx DMA Descriptor Read Access,?,?,?,?,?,?"
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rbitfld.long 0x14 20.--22. "ts,Transmit Process State" "0: Stopped,1: Running,2: Running,3: Running,4: TIME_STAMP write state,5: Reserved for future use,6: Suspended,7: Running"
newline
rbitfld.long 0x14 17.--19. "rs,Received Process State" "0: Stopped: Reset or Stop Receive Command issued,1: Running: Fetching Receive Transfer Descriptor,2: Reserved for future use,3: Running: Waiting for receive packet,4: Suspended: Receive Descriptor Unavailable,5: Running: Closing Receive Descriptor,6: TIME_STAMP write state,7: Running: Transferring the receive packet data.."
newline
bitfld.long 0x14 16. "nis,Normal Interrupt Summary" "0,1"
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bitfld.long 0x14 15. "ais,Abnormal Interrupt Summary" "0,1"
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bitfld.long 0x14 14. "eri,Early Receive Interrupt" "0,1"
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bitfld.long 0x14 13. "fbi,Fatal Bus Error Interrupt" "0,1"
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rbitfld.long 0x14 11.--12. "reserved_12_11,Reserved" "0,1,2,3"
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bitfld.long 0x14 10. "eti,Early Transmit Interrupt" "0,1"
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bitfld.long 0x14 9. "rwt,Receive Watchdog Timeout" "0,1"
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bitfld.long 0x14 8. "rps,Receive Process Stopped" "0,1"
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bitfld.long 0x14 7. "ru,Receive Buffer Unavailable" "0,1"
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bitfld.long 0x14 6. "ri,Receive Interrupt" "0,1"
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bitfld.long 0x14 5. "unf,Transmit Underflow" "0,1"
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bitfld.long 0x14 4. "ovf,Receive Overflow" "0,1"
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bitfld.long 0x14 3. "tjt,Transmit Jabber Timeout" "0,1"
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bitfld.long 0x14 2. "tu,Transmit Buffer Unavailable" "0,1"
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bitfld.long 0x14 1. "tps,Transmit Process Stopped" "0,1"
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bitfld.long 0x14 0. "ti,Transmit Interrupt" "0,1"
line.long 0x18 "dmagrp_operation_mode,Register 6 (Operation Mode Register)"
hexmask.long.byte 0x18 27.--31. 1. "reserved_31_27,Reserved"
newline
bitfld.long 0x18 26. "dt,Disable Dropping of TCP/IP Checksum Error Frames" "0,1"
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bitfld.long 0x18 25. "rsf,Receive Store and Forward" "0,1"
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bitfld.long 0x18 24. "dff,Disable Flushing of Received Frames" "0,1"
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rbitfld.long 0x18 23. "rfa_2,MSB of Threshold for Activating Flow Control" "0,1"
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rbitfld.long 0x18 22. "rfd_2,MSB of Threshold for Deactivating Flow Control" "0,1"
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bitfld.long 0x18 21. "tsf,Transmit Store and Forward" "0,1"
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bitfld.long 0x18 20. "ftf,Flush Transmit FIFO" "0,1"
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rbitfld.long 0x18 17.--19. "reserved_19_17,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 14.--16. "ttc,Transmit Threshold Control" "0: 64,1: 128,?,?,?,?,?,?"
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bitfld.long 0x18 13. "st,Start or Stop Transmission Command" "0,1"
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rbitfld.long 0x18 11.--12. "rfd,Threshold for Deactivating Flow Control (in half-duplex and full-duplex)" "0: Full minus 1 KB,1: Full minus 2 KB,?,?"
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rbitfld.long 0x18 9.--10. "rfa,Threshold for Activating Flow Control (in half-duplex and full-duplex)" "0: Full minus 1 KB,1: Full minus 2 KB,?,?"
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rbitfld.long 0x18 8. "efc,Reserved" "0,1"
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bitfld.long 0x18 7. "fef,Forward Error Frames" "0,1"
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bitfld.long 0x18 6. "fuf,Forward Undersized Good Frames" "0,1"
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bitfld.long 0x18 5. "dgf,Drop Giant Frames" "0,1"
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bitfld.long 0x18 3.--4. "rtc,Receive Threshold Control" "0: 64,1: 32,?,?"
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bitfld.long 0x18 2. "osf,Operate on Second Frame" "0,1"
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bitfld.long 0x18 1. "sr,Start or Stop Receive" "0,1"
newline
rbitfld.long 0x18 0. "reserved_0,Reserved" "0,1"
line.long 0x1C "dmagrp_interrupt_enable,Register 7 (Interrupt Enable Register)"
hexmask.long.word 0x1C 17.--31. 1. "reserved_31_17,Reserved"
newline
bitfld.long 0x1C 16. "nie,Normal Interrupt Summary Enable" "0,1"
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bitfld.long 0x1C 15. "aie,Abnormal Interrupt Summary Enable" "0,1"
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bitfld.long 0x1C 14. "ere,Early Receive Interrupt Enable" "0,1"
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bitfld.long 0x1C 13. "fbe,Fatal Bus Error Enable" "0,1"
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rbitfld.long 0x1C 11.--12. "reserved_12_11,Reserved" "0,1,2,3"
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bitfld.long 0x1C 10. "ete,Early Transmit Interrupt Enable" "0,1"
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bitfld.long 0x1C 9. "rwe,Receive Watchdog Timeout Enable" "0,1"
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bitfld.long 0x1C 8. "rse,Receive Stopped Enable" "0,1"
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bitfld.long 0x1C 7. "rue,Receive Buffer Unavailable Enable" "0,1"
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bitfld.long 0x1C 6. "rie,Receive Interrupt Enable" "0,1"
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bitfld.long 0x1C 5. "une,Underflow Interrupt Enable" "0,1"
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bitfld.long 0x1C 4. "ove,Overflow Interrupt Enable" "0,1"
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bitfld.long 0x1C 3. "tje,Transmit Jabber Timeout Enable" "0,1"
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bitfld.long 0x1C 2. "tue,Transmit Buffer Unavailable Enable" "0,1"
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bitfld.long 0x1C 1. "tse,Transmit Stopped Enable" "0,1"
newline
bitfld.long 0x1C 0. "tie,Transmit Interrupt Enable" "0,1"
rgroup.long 0x1020++0x3
line.long 0x0 "dmagrp_missed_frame_and_buffer_overflow_counter,Register 8 (Missed Frame and Buffer Overflow Counter Register)"
bitfld.long 0x0 29.--31. "reserved_31_29,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 28. "ovfcntovf,Overflow Bit for FIFO Overflow Counter" "0,1"
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hexmask.long.word 0x0 17.--27. 1. "ovffrmcnt,Overflow Frame Counter"
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bitfld.long 0x0 16. "miscntovf,Overflow Bit for Missed Frame Counter" "0,1"
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hexmask.long.word 0x0 0.--15. 1. "misfrmcnt,Missed Frame Counter"
group.long 0x1024++0x7
line.long 0x0 "dmagrp_receive_interrupt_watchdog_timer,Register 9 (Receive Interrupt Watchdog Timer Register)"
hexmask.long.tbyte 0x0 8.--31. 1. "reserved_31_8,Reserved"
newline
hexmask.long.byte 0x0 0.--7. 1. "riwt,RI Watchdog Timer Count"
line.long 0x4 "dmagrp_axi_bus_mode,The AXI Bus Mode Register controls the behavior of the AXI master. It is mainly used to control the burst splitting and the number of outstanding requests."
bitfld.long 0x4 31. "en_lpi,When set to 1  this bit enables the LPI mode supported by the AXI master and accepts the LPI request from the AXI System Clock controller." "0,1"
newline
bitfld.long 0x4 30. "lpi_xit_frm,When set to 1  this bit enables the GMAC-AXI to come out of the LPI mode only when the Magic Packet or Remote Wake Up Packet is received." "0,1"
newline
hexmask.long.byte 0x4 20.--23. 1. "wr_osr_lmt,AXI Maximum Write OutStanding Request Limit"
newline
hexmask.long.byte 0x4 16.--19. 1. "rd_osr_lmt,This value limits the maximum outstanding request on the AXI read interface."
newline
bitfld.long 0x4 13. "onekbbe,1 KB Boundary Crossing Enable for the GMAC-AXI Master" "0,1"
newline
rbitfld.long 0x4 12. "axi_aal,This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register)." "0,1"
newline
bitfld.long 0x4 3. "blen16,When this bit is set to 1 or UNDEFINED is set to 1  the GMAC-AXI is allowed to select a burst length of 16 on the AXI Master interface." "0,1"
newline
bitfld.long 0x4 2. "blen8,When this bit is set to 1  the GMAC-AXI is allowed to select a burst length of 8 on the AXI Master interface." "0,1"
newline
bitfld.long 0x4 1. "blen4,When this bit is set to 1  the GMAC-AXI is allowed to select a burst length of 4 on the AXI Master interface." "0,1"
newline
rbitfld.long 0x4 0. "undefined,This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register[16])." "0,1"
rgroup.long 0x102C++0x3
line.long 0x0 "dmagrp_ahb_or_axi_status,Register 11 (AHB or AXI Status Register)"
hexmask.long 0x0 2.--31. 1. "reserved_31_2,Reserved"
newline
bitfld.long 0x0 1. "axirdsts,AXI Master Read Channel Status" "0,1"
newline
bitfld.long 0x0 0. "axwhsts,AXI Master Write Channel or AHB Master Status" "0,1"
rgroup.long 0x1048++0x13
line.long 0x0 "dmagrp_current_host_transmit_descriptor,Register 18 (Current Host Transmit Descriptor Register)"
hexmask.long 0x0 0.--31. 1. "curtdesaptr,Host Transmit Descriptor Address Pointer"
line.long 0x4 "dmagrp_current_host_receive_descriptor,Register 19 (Current Host Receive Descriptor Register)"
hexmask.long 0x4 0.--31. 1. "currdesaptr,Host Receive Descriptor Address Pointer"
line.long 0x8 "dmagrp_current_host_transmit_buffer_address,Register 20 (Current Host Transmit Buffer Address Register)"
hexmask.long 0x8 0.--31. 1. "curtbufaptr,Host Transmit Buffer Address Pointer"
line.long 0xC "dmagrp_current_host_receive_buffer_address,Register 21 (Current Host Receive Buffer Address Register)"
hexmask.long 0xC 0.--31. 1. "currbufaptr,Host Receive Buffer Address Pointer"
line.long 0x10 "dmagrp_hw_feature,Register 22 (HW Feature Register)"
bitfld.long 0x10 31. "reserved_31,Reserved" "0,1"
newline
bitfld.long 0x10 28.--30. "actphyif,Active or Selected PHY interface" "0: GMII or MII,1: RGMII,?,?,?,?,?,?"
newline
bitfld.long 0x10 27. "SAVLANINS,Source Address or VLAN Insertion" "0,1"
newline
bitfld.long 0x10 26. "FLEXIPPSEN,Flexible Pulse-Per-Second Output" "0,1"
newline
bitfld.long 0x10 25. "INTTSEN,Timestamping with Internal System Time" "0,1"
newline
bitfld.long 0x10 24. "enhdessel,Alternate (Enhanced Descriptor)" "0,1"
newline
bitfld.long 0x10 22.--23. "txchcnt,Number of additional Tx channels" "0,1,2,3"
newline
bitfld.long 0x10 20.--21. "rxchcnt,Number of additional Rx channels" "0,1,2,3"
newline
bitfld.long 0x10 19. "rxfifosize,Rx FIFO > 2 048 Bytes" "0,1"
newline
bitfld.long 0x10 18. "rxtyp2coe,IP Checksum Offload (Type 2) in Rx" "0,1"
newline
bitfld.long 0x10 17. "rxtyp1coe,IP Checksum Offload (Type 1) in Rx" "0,1"
newline
bitfld.long 0x10 16. "txoesel,Checksum Offload in Tx" "0,1"
newline
bitfld.long 0x10 15. "avsel,AV Feature" "0,1"
newline
bitfld.long 0x10 14. "eeesel,Energy Efficient Ethernet" "0,1"
newline
bitfld.long 0x10 13. "tsver2sel,IEEE 1588-2008 Advanced Timestamp" "0,1"
newline
bitfld.long 0x10 12. "tsver1sel,Only IEEE 1588-2002 Timestamp" "0,1"
newline
bitfld.long 0x10 11. "mmcsel,RMON Module" "0,1"
newline
bitfld.long 0x10 10. "mgksel,PMT Magic Packet" "0,1"
newline
bitfld.long 0x10 9. "rwksel,PMT Remote Wakeup" "0,1"
newline
bitfld.long 0x10 8. "smasel,SMA (MDIO) Interface" "0,1"
newline
bitfld.long 0x10 7. "l3l4fltren,Layer 3 and Layer 4 Filter Feature" "0,1"
newline
bitfld.long 0x10 6. "pcssel,PCS registers (TBI  SGMII  or RTBI PHY interface)" "0,1"
newline
bitfld.long 0x10 5. "addmacadrsel,Multiple MAC Address Registers" "0,1"
newline
bitfld.long 0x10 4. "hashsel,HASH Filter" "0,1"
newline
bitfld.long 0x10 3. "exthashen,Expanded DA Hash Filter" "0,1"
newline
bitfld.long 0x10 2. "hdsel,Half-Duplex support" "0,1"
newline
bitfld.long 0x10 1. "gmiisel,1000 Mbps support" "0,1"
newline
bitfld.long 0x10 0. "miisel,10 or 100 Mbps support" "0,1"
tree.end
tree "EMAC2 (EMAC2 Module)"
base ad:0xFF804000
group.long 0x0++0x7
line.long 0x0 "gmacgrp_mac_configuration,Register 0 (MAC Configuration Register)"
rbitfld.long 0x0 31. "reserved_31,Reserved" "0,1"
newline
bitfld.long 0x0 28.--30. "sarc,Source Address Insertion or Replacement Control" "?,?,2: ,3: ,?,?,?,?"
newline
bitfld.long 0x0 27. "twokpe,IEEE 802.3as Support for 2K Packets" "0,1"
newline
rbitfld.long 0x0 26. "sfterr,SMII Force Transmit Error" "0,1"
newline
bitfld.long 0x0 25. "cst,CRC Stripping for Type Frames" "0,1"
newline
rbitfld.long 0x0 24. "tc,Transmit Configuration in RGMII  SGMII  or SMII" "0,1"
newline
bitfld.long 0x0 23. "wd,Watchdog Disable" "0,1"
newline
bitfld.long 0x0 22. "jd,Jabber Disable" "0,1"
newline
bitfld.long 0x0 21. "be,Frame Burst Enable" "0,1"
newline
bitfld.long 0x0 20. "je,Jumbo Frame Enable" "0,1"
newline
bitfld.long 0x0 17.--19. "ifg,Inter-Frame Gap" "0: 96 bit times,1: 88 bit times,?,?,?,?,?,?"
newline
bitfld.long 0x0 16. "dcrs,Disable Carrier Sense During Transmission" "0,1"
newline
bitfld.long 0x0 15. "ps,Port Select" "0: For 1000 Mbps operations,1: For 10 or 100 Mbps operations"
newline
bitfld.long 0x0 14. "fes,Speed" "0: 10 Mbps,1: 100 Mbps"
newline
bitfld.long 0x0 13. "do,Disable Receive Own" "0,1"
newline
bitfld.long 0x0 12. "lm,Loopback Mode" "0,1"
newline
bitfld.long 0x0 11. "dm,Duplex Mode" "0,1"
newline
bitfld.long 0x0 10. "ipc,Checksum Offload" "0,1"
newline
bitfld.long 0x0 9. "dr,Disable Retry" "0,1"
newline
rbitfld.long 0x0 8. "lud,Link Up or Down" "0: Link Down,1: Link Up"
newline
bitfld.long 0x0 7. "acs,Automatic Pad or CRC Stripping" "0,1"
newline
bitfld.long 0x0 5.--6. "bl,Back-Off Limit" "0: k = min,1: k = min,?,?"
newline
bitfld.long 0x0 4. "dc,Deferral Check" "0,1"
newline
bitfld.long 0x0 3. "te,Transmitter Enable" "0,1"
newline
bitfld.long 0x0 2. "re,Receiver Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "prelen,Preamble Length for Transmit Frames" "0: 7 bytes of preamble,1: 5 byte of preamble,2: 3 bytes of preamble,3: 1 byte of preamble"
line.long 0x4 "gmacgrp_mac_frame_filter,Register 1 (MAC Frame Filter)"
bitfld.long 0x4 31. "ra,Receive All" "0,1"
newline
hexmask.long.word 0x4 22.--30. 1. "reserved_30_22,Reserved"
newline
bitfld.long 0x4 21. "dntu,Drop non-TCP/UDP over IP Frames" "0,1"
newline
bitfld.long 0x4 20. "ipfe,Layer 3 and Layer 4 Filter Enable" "0,1"
newline
rbitfld.long 0x4 17.--19. "reserved_19_17,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 16. "vtfe,VLAN Tag Filter Enable" "0,1"
newline
hexmask.long.byte 0x4 11.--15. 1. "reserved_15_11,Reserved"
newline
rbitfld.long 0x4 10. "hpf,Hash or Perfect Filter" "0,1"
newline
bitfld.long 0x4 9. "saf,Source Address Filter Enable" "0,1"
newline
bitfld.long 0x4 8. "saif,SA Inverse Filtering" "0,1"
newline
bitfld.long 0x4 6.--7. "pcf,Pass Control Frames" "0: MAC filters all control frames from reaching the..,1: The MAC is in the full-duplex mode and flow..,2: The destination address,3: The Type field of the received frame is 0x8808.."
newline
bitfld.long 0x4 5. "dbf,Disable Broadcast Frames" "0,1"
newline
bitfld.long 0x4 4. "pm,Pass All Multicast" "0,1"
newline
bitfld.long 0x4 3. "daif,DA Inverse Filtering" "0,1"
newline
rbitfld.long 0x4 2. "hmc,Hash Multicast" "0,1"
newline
rbitfld.long 0x4 1. "huc,Hash Unicast" "0,1"
newline
bitfld.long 0x4 0. "pr,Promiscuous Mode" "0,1"
group.long 0x10++0xF
line.long 0x0 "gmacgrp_gmii_address,Register 4 (GMII Address Register)"
hexmask.long.word 0x0 16.--31. 1. "reserved_31_16,Reserved"
newline
hexmask.long.byte 0x0 11.--15. 1. "pa,Physical Layer Address"
newline
hexmask.long.byte 0x0 6.--10. 1. "gr,GMII Register"
newline
hexmask.long.byte 0x0 2.--5. 1. "cr,CSR Clock Range"
newline
bitfld.long 0x0 1. "gw,GMII Write" "0,1"
newline
bitfld.long 0x0 0. "gb,GMII Busy" "0,1"
line.long 0x4 "gmacgrp_gmii_data,Register 5 (GMII Data Register)"
hexmask.long.word 0x4 16.--31. 1. "reserved_31_16,Reserved"
newline
hexmask.long.word 0x4 0.--15. 1. "gd,GMII Data"
line.long 0x8 "gmacgrp_flow_control,Register 6 (Flow Control Register)"
hexmask.long.word 0x8 16.--31. 1. "pt,Pause Time"
newline
hexmask.long.byte 0x8 8.--15. 1. "reserved_15_8,Reserved"
newline
bitfld.long 0x8 7. "dzpq,Disable Zero-Quanta Pause" "0,1"
newline
rbitfld.long 0x8 6. "reserved_6,Reserved" "0,1"
newline
bitfld.long 0x8 4.--5. "plt,Pause Low Threshold" "0: The threshold is Pause time minus 4 slot times,1: The threshold is Pause time minus 28 slot times,?,?"
newline
bitfld.long 0x8 3. "up,Unicast Pause Frame Detect" "0,1"
newline
bitfld.long 0x8 2. "rfe,Receive Flow Control Enable" "0,1"
newline
bitfld.long 0x8 1. "tfe,Transmit Flow Control Enable" "0,1"
newline
bitfld.long 0x8 0. "fca_bpa,Flow Control Busy or Backpressure Activate" "0,1"
line.long 0xC "gmacgrp_vlan_tag,Register 7 (VLAN Tag Register)"
hexmask.long.word 0xC 20.--31. 1. "reserved_31_20,Reserved"
newline
rbitfld.long 0xC 19. "vthm,VLAN Tag Hash Table Match Enable" "0,1"
newline
bitfld.long 0xC 18. "esvl,Enable S-VLAN" "0,1"
newline
bitfld.long 0xC 17. "vtim,VLAN Tag Inverse Match Enable" "0,1"
newline
bitfld.long 0xC 16. "etv,Enable 12-Bit VLAN Tag Comparison" "0,1"
newline
hexmask.long.word 0xC 0.--15. 1. "vl,VLAN Tag Identifier for Receive Frames"
rgroup.long 0x20++0x7
line.long 0x0 "gmacgrp_version,Register 8 (Version Register)"
hexmask.long.word 0x0 16.--31. 1. "reserved_31_16,Reserved"
newline
hexmask.long.byte 0x0 8.--15. 1. "userver,User-defined Version (Configured with the coreConsultant)"
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hexmask.long.byte 0x0 0.--7. 1. "snpsver,Synopsys-defined Version (3.7)"
line.long 0x4 "gmacgrp_debug,Register 9 (Debug Register)"
hexmask.long.byte 0x4 26.--31. 1. "reserved_31_26,Reserved"
newline
bitfld.long 0x4 25. "txstsfsts,MTL TxStatus FIFO Full Status" "0,1"
newline
bitfld.long 0x4 24. "txfsts,MTL Tx FIFO Not Empty Status" "0,1"
newline
bitfld.long 0x4 23. "reserved_23,Reserved" "0,1"
newline
bitfld.long 0x4 22. "twcsts,MTL Tx FIFO Write Controller Active Status" "0,1"
newline
bitfld.long 0x4 20.--21. "trcsts,MTL Tx FIFO Read Controller Status" "0: IDLE state,1: READ state,?,?"
newline
bitfld.long 0x4 19. "txpaused,MAC transmitter in PAUSE" "0,1"
newline
bitfld.long 0x4 17.--18. "tfcsts,MAC Transmit Frame Controller Status" "0: IDLE state,1: Waiting for Status of previous frame or IFG or..,?,?"
newline
bitfld.long 0x4 16. "tpests,MAC GMII or MII Transmit Protocol Engine Status" "0,1"
newline
hexmask.long.byte 0x4 10.--15. 1. "reserved_15_10,Reserved"
newline
bitfld.long 0x4 8.--9. "rxfsts,MTL Rx FIFO Fill-level Status" "0: Rx FIFO Empty,1: Rx FIFO fill level is below the flow-control..,?,?"
newline
bitfld.long 0x4 7. "reserved_7,Reserved" "0,1"
newline
bitfld.long 0x4 5.--6. "rrcsts,MTL Rx FIFO Read Controller State" "0: IDLE state,1: Reading frame data,?,?"
newline
bitfld.long 0x4 4. "rwcsts,MTL Rx FIFO Write Controller Active Status" "0,1"
newline
bitfld.long 0x4 3. "reserved_3,Reserved" "0,1"
newline
bitfld.long 0x4 1.--2. "rfcfcsts,MAC Receive Frame Controller FIFO Status" "0,1,2,3"
newline
bitfld.long 0x4 0. "rpests,MAC GMII or MII Receive Protocol Engine Status" "0,1"
group.long 0x30++0x7
line.long 0x0 "gmacgrp_lpi_control_status,Register 12 (LPI Control and Status Register)"
hexmask.long.word 0x0 20.--31. 1. "reserved_31_20,Reserved"
newline
bitfld.long 0x0 19. "lpitxa,LPI TX Automate" "0,1"
newline
rbitfld.long 0x0 18. "plsen,PHY Link Status Enable" "0,1"
newline
bitfld.long 0x0 17. "pls,PHY Link Status" "0,1"
newline
bitfld.long 0x0 16. "lpien,LPI Enable" "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "reserved_15_10,Reserved"
newline
rbitfld.long 0x0 9. "rlpist,Receive LPI State" "0,1"
newline
rbitfld.long 0x0 8. "tlpist,Transmit LPI State" "0,1"
newline
hexmask.long.byte 0x0 4.--7. 1. "reserved_7_4,Reserved"
newline
rbitfld.long 0x0 3. "rlpiex,Receive LPI Exit" "0,1"
newline
rbitfld.long 0x0 2. "rlpien,Receive LPI Entry" "0,1"
newline
rbitfld.long 0x0 1. "tlpiex,Transmit LPI Exit" "0,1"
newline
rbitfld.long 0x0 0. "tlpien,Transmit LPI Entry" "0,1"
line.long 0x4 "gmacgrp_lpi_timers_control,Register 13 (LPI Timers Control Register)"
hexmask.long.byte 0x4 26.--31. 1. "reserved_31_26,Reserved"
newline
hexmask.long.word 0x4 16.--25. 1. "lst,LPI LS Timer"
newline
hexmask.long.word 0x4 0.--15. 1. "twt,LPI TW Timer"
rgroup.long 0x38++0x3
line.long 0x0 "gmacgrp_interrupt_status,Register 14 (Interrupt Register)"
hexmask.long.tbyte 0x0 12.--31. 1. "reserved_31_12,Reserved"
newline
bitfld.long 0x0 11. "gpiis,GPI Interrupt Status" "0,1"
newline
bitfld.long 0x0 10. "lpiis,LPI Interrupt Status" "0,1"
newline
bitfld.long 0x0 9. "tsis,Timestamp Interrupt Status" "0,1"
newline
bitfld.long 0x0 8. "reserved_8,Reserved" "0,1"
newline
bitfld.long 0x0 7. "mmcrxipis,MMC Receive Checksum Offload Interrupt Status" "0,1"
newline
bitfld.long 0x0 6. "mmctxis,MMC Transmit Interrupt Status" "0,1"
newline
bitfld.long 0x0 5. "mmcrxis,MMC Receive Interrupt Status" "0,1"
newline
bitfld.long 0x0 4. "mmcis,MMC Interrupt Status" "0,1"
newline
bitfld.long 0x0 3. "pmtis,PMT Interrupt Status" "0,1"
newline
bitfld.long 0x0 2. "pcsancis,PCS Auto-Negotiation Complete" "0,1"
newline
bitfld.long 0x0 1. "pcslchgis,PCS Link Status Changed" "0,1"
newline
bitfld.long 0x0 0. "rgsmiiis,RGMII or SMII Interrupt Status" "0,1"
group.long 0x3C++0x83
line.long 0x0 "gmacgrp_interrupt_mask,Register 15 (Interrupt Mask Register)"
hexmask.long.tbyte 0x0 11.--31. 1. "reserved_31_11,Reserved"
newline
bitfld.long 0x0 10. "lpiim,LPI Interrupt Mask" "0,1"
newline
rbitfld.long 0x0 9. "tsim,Timestamp Interrupt Mask" "0,1"
newline
hexmask.long.byte 0x0 4.--8. 1. "reserved_8_4,Reserved"
newline
bitfld.long 0x0 3. "pmtim,PMT Interrupt Mask" "0,1"
newline
rbitfld.long 0x0 2. "pcsancim,PCS AN Completion Interrupt Mask" "0,1"
newline
rbitfld.long 0x0 1. "pcslchgim,PCS Link Status Interrupt Mask" "0,1"
newline
rbitfld.long 0x0 0. "rgsmiiim,RGMII or SMII Interrupt Mask" "0,1"
line.long 0x4 "gmacgrp_mac_address0_high,Register 16 (MAC Address0 High Register)"
rbitfld.long 0x4 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x4 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x4 0.--15. 1. "addrhi,MAC Address0 [47:32]"
line.long 0x8 "gmacgrp_mac_address0_low,Register 17 (MAC Address0 Low Register)"
hexmask.long 0x8 0.--31. 1. "addrlo,MAC Address0 [31:0]"
line.long 0xC "gmacgrp_mac_address1_high,Register 18 (MAC Address1 High Register)"
bitfld.long 0xC 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0xC 30. "sa,Source Address" "0,1"
newline
bitfld.long 0xC 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0xC 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0xC 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0xC 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0xC 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0xC 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0xC 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0xC 0.--15. 1. "addrhi,MAC Address1 [47:32]"
line.long 0x10 "gmacgrp_mac_address1_low,Register 19 (MAC Address1 Low Register)"
hexmask.long 0x10 0.--31. 1. "addrlo,MAC Address1 [31:0]"
line.long 0x14 "gmacgrp_mac_address2_high,Register 20 (MAC Address2 High Register)"
bitfld.long 0x14 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x14 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x14 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x14 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x14 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x14 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x14 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x14 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x14 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x14 0.--15. 1. "addrhi,MAC Address2 [47:32]"
line.long 0x18 "gmacgrp_mac_address2_low,Register 21 (MAC Address2 Low Register)"
hexmask.long 0x18 0.--31. 1. "addrlo,MAC Address2 [31:0]"
line.long 0x1C "gmacgrp_mac_address3_high,Register 22 (MAC Address3 High Register)"
bitfld.long 0x1C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x1C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x1C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x1C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x1C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x1C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x1C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x1C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x1C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x1C 0.--15. 1. "addrhi,MAC Address3 [47:32]"
line.long 0x20 "gmacgrp_mac_address3_low,Register 23 (MAC Address3 Low Register)"
hexmask.long 0x20 0.--31. 1. "addrlo,MAC Address3 [31:0]"
line.long 0x24 "gmacgrp_mac_address4_high,Register 24 (MAC Address4 High Register)"
bitfld.long 0x24 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x24 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x24 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x24 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x24 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x24 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x24 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x24 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x24 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x24 0.--15. 1. "addrhi,MAC Address4 [47:32]"
line.long 0x28 "gmacgrp_mac_address4_low,Register 25 (MAC Address4 Low Register)"
hexmask.long 0x28 0.--31. 1. "addrlo,MAC Address4 [31:0]"
line.long 0x2C "gmacgrp_mac_address5_high,Register 26 (MAC Address5 High Register)"
bitfld.long 0x2C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x2C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x2C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x2C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x2C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x2C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x2C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x2C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x2C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x2C 0.--15. 1. "addrhi,MAC Address5 [47:32]"
line.long 0x30 "gmacgrp_mac_address5_low,Register 27 (MAC Address5 Low Register)"
hexmask.long 0x30 0.--31. 1. "addrlo,MAC Address5 [31:0]"
line.long 0x34 "gmacgrp_mac_address6_high,Register 28 (MAC Address6 High Register)"
bitfld.long 0x34 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x34 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x34 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x34 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x34 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x34 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x34 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x34 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x34 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x34 0.--15. 1. "addrhi,MAC Address6 [47:32]"
line.long 0x38 "gmacgrp_mac_address6_low,Register 29 (MAC Address6 Low Register)"
hexmask.long 0x38 0.--31. 1. "addrlo,MAC Address6 [31:0]"
line.long 0x3C "gmacgrp_mac_address7_high,Register 30 (MAC Address7 High Register)"
bitfld.long 0x3C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x3C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x3C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x3C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x3C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x3C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x3C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x3C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address7 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x3C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x3C 0.--15. 1. "addrhi,MAC Address7 [47:32]"
line.long 0x40 "gmacgrp_mac_address7_low,Register 31 (MAC Address7 Low Register)"
hexmask.long 0x40 0.--31. 1. "addrlo,MAC Address7 [31:0]"
line.long 0x44 "gmacgrp_mac_address8_high,Register 32 (MAC Address8 High Register)"
bitfld.long 0x44 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x44 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x44 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x44 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x44 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x44 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x44 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x44 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x44 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x44 0.--15. 1. "addrhi,MAC Address8 [47:32]"
line.long 0x48 "gmacgrp_mac_address8_low,Register 33 (MAC Address8 Low Register)"
hexmask.long 0x48 0.--31. 1. "addrlo,MAC Address8 [31:0]"
line.long 0x4C "gmacgrp_mac_address9_high,Register 34 (MAC Address9 High Register)"
bitfld.long 0x4C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x4C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x4C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x4C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x4C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x4C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x4C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x4C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address9 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x4C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x4C 0.--15. 1. "addrhi,MAC Address9 [47:32]"
line.long 0x50 "gmacgrp_mac_address9_low,Register 35 (MAC Address9 Low Register)"
hexmask.long 0x50 0.--31. 1. "addrlo,MAC Address9 [31:0]"
line.long 0x54 "gmacgrp_mac_address10_high,Register 36 (MAC Address10 High Register)"
bitfld.long 0x54 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x54 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x54 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x54 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x54 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x54 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x54 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x54 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address10 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x54 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x54 0.--15. 1. "addrhi,MAC Address10 [47:32]"
line.long 0x58 "gmacgrp_mac_address10_low,Register 37 (MAC Address10 Low Register)"
hexmask.long 0x58 0.--31. 1. "addrlo,MAC Address10 [31:0]"
line.long 0x5C "gmacgrp_mac_address11_high,Register 38 (MAC Address11 High Register)"
bitfld.long 0x5C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x5C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x5C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x5C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x5C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x5C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x5C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x5C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address11 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x5C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x5C 0.--15. 1. "addrhi,MAC Address11 [47:32]"
line.long 0x60 "gmacgrp_mac_address11_low,Register 39 (MAC Address1 Low Register)"
hexmask.long 0x60 0.--31. 1. "addrlo,MAC Address11 [31:0]"
line.long 0x64 "gmacgrp_mac_address12_high,Register 40 (MAC Address12 High Register )"
bitfld.long 0x64 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x64 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x64 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x64 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x64 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x64 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x64 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x64 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address12 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x64 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x64 0.--15. 1. "addrhi,MAC Address12 [47:32]"
line.long 0x68 "gmacgrp_mac_address12_low,Register 41 (MAC Address12 Low Register)"
hexmask.long 0x68 0.--31. 1. "addrlo,MAC Address12 [31:0]"
line.long 0x6C "gmacgrp_mac_address13_high,Register 42 (MAC Address13 High Register)"
bitfld.long 0x6C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x6C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x6C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x6C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x6C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x6C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x6C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x6C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address13 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x6C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x6C 0.--15. 1. "addrhi,MAC Address13 [47:32]"
line.long 0x70 "gmacgrp_mac_address13_low,Register 43 (MAC Address13 Low Register)"
hexmask.long 0x70 0.--31. 1. "addrlo,MAC Address13 [31:0]"
line.long 0x74 "gmacgrp_mac_address14_high,Register 44 (MAC Address14 High Register)"
bitfld.long 0x74 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x74 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x74 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x74 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x74 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x74 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x74 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x74 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address14 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x74 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x74 0.--15. 1. "addrhi,MAC Address14 [47:32]"
line.long 0x78 "gmacgrp_mac_address14_low,Register 45 (MAC Address14 Low Register)"
hexmask.long 0x78 0.--31. 1. "addrlo,MAC Address14 [31:0]"
line.long 0x7C "gmacgrp_mac_address15_high,Register 46 (MAC Address15 High Register)"
bitfld.long 0x7C 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x7C 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x7C 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x7C 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x7C 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x7C 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x7C 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x7C 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address15 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x7C 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x7C 0.--15. 1. "addrhi,MAC Address15 [47:32] This field contains the upper 16 bits (47:32) of the 16th 6-byte MAC address."
line.long 0x80 "gmacgrp_mac_address15_low,Register 47 (MAC Address15 Low Register)"
hexmask.long 0x80 0.--31. 1. "addrlo,MAC Address15 [31:0]"
rgroup.long 0xD8++0x3
line.long 0x0 "gmacgrp_sgmii_rgmii_smii_control_status,The SGMII/RGMII/SMII Status register indicates the status signals received by the RGMII interface (selected at reset) from the PHY."
bitfld.long 0x0 3. "lnksts,This bit indicates whether the link is up (1'b1) or down (1'b0)." "0,1"
newline
bitfld.long 0x0 1.--2. "lnkspeed,This bit indicates the current speed of the link. Bit 2 is reserved when the MAC is configured for the SMII PHY interface." "0,1,2,3"
newline
bitfld.long 0x0 0. "lnkmod,This bit indicates the current mode of operation of the link" "0,1"
group.long 0xDC++0x7
line.long 0x0 "gmacgrp_wdog_timeout,Register 55 (Watchdog Timeout Register)"
hexmask.long.word 0x0 17.--31. 1. "reserved_31_17,Reserved"
newline
bitfld.long 0x0 16. "pwe,Programmable Watchdog Enable" "0,1"
newline
rbitfld.long 0x0 14.--15. "reserved_15_14,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "wto,Watchdog Timeout"
line.long 0x4 "gmacgrp_genpio,Register 56 (General Purpose IO Register)"
hexmask.long.byte 0x4 25.--31. 1. "reserved_31_x,Reserved"
newline
bitfld.long 0x4 24. "gpit,GPI Type" "0,1"
newline
hexmask.long.byte 0x4 17.--23. 1. "reserved_23_x,Reserved"
newline
bitfld.long 0x4 16. "gpie,GPI Interrupt Enable" "0,1"
newline
hexmask.long.byte 0x4 9.--15. 1. "reserved_15_x,Reserved"
newline
bitfld.long 0x4 8. "gpo,General Purpose Output" "0,1"
newline
hexmask.long.byte 0x4 1.--7. 1. "reserved_7_x,Reserved"
newline
rbitfld.long 0x4 0. "gpis,General Purpose Input Status" "0,1"
group.long 0x100++0x3
line.long 0x0 "gmacgrp_mmc_control,Register 64 (MMC Control Register)"
hexmask.long.tbyte 0x0 9.--31. 1. "reserved_31_9,Reserved"
newline
bitfld.long 0x0 8. "ucdbc,Update MMC Counters for Dropped Broadcast Frames" "0,1"
newline
rbitfld.long 0x0 6.--7. "reserved_7_6,Reserved" "0,1,2,3"
newline
bitfld.long 0x0 5. "cntprstlvl,Full-Half Preset" "0,1"
newline
bitfld.long 0x0 4. "cntprst,Counters Preset" "0,1"
newline
bitfld.long 0x0 3. "cntfreez,MMC Counter Freeze" "0,1"
newline
bitfld.long 0x0 2. "rstonrd,Reset on Read" "0,1"
newline
bitfld.long 0x0 1. "cntstopro,Counters Stop Rollover" "0,1"
newline
bitfld.long 0x0 0. "cntrst,Counters Reset" "0,1"
rgroup.long 0x104++0x7
line.long 0x0 "gmacgrp_mmc_receive_interrupt,Register 65 (MMC Receive Interrupt Register)"
hexmask.long.byte 0x0 26.--31. 1. "reserved_31_26,Reserved"
newline
bitfld.long 0x0 25. "rxctrlfis,MMC Receive Control Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 24. "rxrcverrfis,MMC Receive Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 23. "rxwdogfis,MMC Receive Watchdog Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 22. "rxvlangbfis,MMC Receive VLAN Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 21. "rxfovfis,MMC Receive FIFO Overflow Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 20. "rxpausfis,MMC Receive Pause Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 19. "rxorangefis,MMC Receive Out Of Range Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 18. "rxlenerfis,MMC Receive Length Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 17. "rxucgfis,MMC Receive Unicast Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 16. "rx1024tmaxoctgbfis,MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 15. "rx512t1023octgbfis,MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 14. "rx256t511octgbfis,MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 13. "rx128t255octgbfis,MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 12. "rx65t127octgbfis,MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 11. "rx64octgbfis,MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 10. "rxosizegfis,MMC Receive Oversize Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 9. "rxusizegfis,MMC Receive Undersize Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 8. "rxjaberfis,MMC Receive Jabber Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 7. "rxruntfis,MMC Receive Runt Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 6. "rxalgnerfis,MMC Receive Alignment Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 5. "rxcrcerfis,MMC Receive CRC Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 4. "rxmcgfis,MMC Receive Multicast Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 3. "rxbcgfis,MMC Receive Broadcast Good Frame Counter Interrupt Status." "0,1"
newline
bitfld.long 0x0 2. "rxgoctis,MMC Receive Good Octet Counter Interrupt Status." "0,1"
newline
bitfld.long 0x0 1. "rxgboctis,MMC Receive Good Bad Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "rxgbfrmis,MMC Receive Good Bad Frame Counter Interrupt Status" "0,1"
line.long 0x4 "gmacgrp_mmc_transmit_interrupt,Register 66 (MMC Transmit Interrupt Register)"
hexmask.long.byte 0x4 26.--31. 1. "reserved_31_26,Reserved"
newline
bitfld.long 0x4 25. "txosizegfis,MMC Transmit Oversize Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 24. "txvlangfis,MMC Transmit VLAN Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 23. "txpausfis,MMC Transmit Pause Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 22. "txexdeffis,MMC Transmit Excessive Deferral Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 21. "txgfrmis,MMC Transmit Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 20. "txgoctis,MMC Transmit Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 19. "txcarerfis,MMC Transmit Carrier Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 18. "txexcolfis,MMC Transmit Excessive Collision Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 17. "txlatcolfis,MMC Transmit Late Collision Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 16. "txdeffis,MMC Transmit Deferred Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 15. "txmcolgfis,MMC Transmit Multiple Collision Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 14. "txscolgfis,MMC Transmit Single Collision Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 13. "txuflowerfis,MMC Transmit Underflow Error Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 12. "txbcgbfis,MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 11. "txmcgbfis,MMC Transmit Multicast Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 10. "txucgbfis,MMC Transmit Unicast Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 9. "tx1024tmaxoctgbfis,MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 8. "tx512t1023octgbfis,MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 7. "tx256t511octgbfis,MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 6. "tx128t255octgbfis,MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 5. "tx65t127octgbfis,MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 4. "tx64octgbfis,MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status." "0,1"
newline
bitfld.long 0x4 3. "txmcgfis,MMC Transmit Multicast Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 2. "txbcgfis,MMC Transmit Broadcast Good Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 1. "txgbfrmis,MMC Transmit Good Bad Frame Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 0. "txgboctis,MMC Transmit Good Bad Octet Counter Interrupt Status" "0,1"
group.long 0x10C++0x7
line.long 0x0 "gmacgrp_mmc_receive_interrupt_mask,Regsiter 67 (MMC Receive Interrupt Mask Register)"
hexmask.long.byte 0x0 26.--31. 1. "reserved_31_26,Reserved"
newline
bitfld.long 0x0 25. "rxctrlfim,MMC Receive Control Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 24. "rxrcverrfim,MMC Receive Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 23. "rxwdogfim,MMC Receive Watchdog Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 22. "rxvlangbfim,MMC Receive VLAN Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 21. "rxfovfim,MMC Receive FIFO Overflow Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 20. "rxpausfim,MMC Receive Pause Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 19. "rxorangefim,MMC Receive Out Of Range Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 18. "rxlenerfim,MMC Receive Length Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 17. "rxucgfim,MMC Receive Unicast Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 16. "rx1024tmaxoctgbfim,MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 15. "rx512t1023octgbfim,MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 14. "rx256t511octgbfim,MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 13. "rx128t255octgbfim,MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 12. "rx65t127octgbfim,MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 11. "rx64octgbfim,MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 10. "rxosizegfim,MMC Receive Oversize Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 9. "rxusizegfim,MMC Receive Undersize Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 8. "rxjaberfim,MMC Receive Jabber Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 7. "rxruntfim,MMC Receive Runt Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 6. "rxalgnerfim,MMC Receive Alignment Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 5. "rxcrcerfim,MMC Receive CRC Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 4. "rxmcgfim,MMC Receive Multicast Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 3. "rxbcgfim,MMC Receive Broadcast Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "rxgoctim,MMC Receive Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "rxgboctim,MMC Receive Good Bad Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "rxgbfrmim,MMC Receive Good Bad Frame Counter Interrupt Mask" "0,1"
line.long 0x4 "gmacgrp_mmc_transmit_interrupt_mask,Register 68 (MMC Transmit Interrupt Mask Register)"
hexmask.long.byte 0x4 26.--31. 1. "reserved_31_26,Reserved"
newline
bitfld.long 0x4 25. "txosizegfim,MMC Transmit Oversize Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 24. "txvlangfim,MMC Transmit VLAN Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 23. "txpausfim,MMC Transmit Pause Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 22. "txexdeffim,MMC Transmit Excessive Deferral Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 21. "txgfrmim,MMC Transmit Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 20. "txgoctim,MMC Transmit Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 19. "txcarerfim,MMC Transmit Carrier Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 18. "txexcolfim,MMC Transmit Excessive Collision Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 17. "txlatcolfim,MMC Transmit Late Collision Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 16. "txdeffim,MMC Transmit Deferred Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 15. "txmcolgfim,MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 14. "txscolgfim,MMC Transmit Single Collision Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 13. "txuflowerfim,MMC Transmit Underflow Error Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 12. "txbcgbfim,MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 11. "txmcgbfim,MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 10. "txucgbfim,MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 9. "tx1024tmaxoctgbfim,MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 8. "tx512t1023octgbfim,MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 7. "tx256t511octgbfim,MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 6. "tx128t255octgbfim,MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 5. "tx65t127octgbfim,MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 4. "tx64octgbfim,MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 3. "txmcgfim,MMC Transmit Multicast Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 2. "txbcgfim,MMC Transmit Broadcast Good Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 1. "txgbfrmim,MMC Transmit Good Bad Frame Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x4 0. "txgboctim,MMC Transmit Good Bad Octet Counter Interrupt Mask" "0,1"
rgroup.long 0x114++0x67
line.long 0x0 "gmacgrp_txoctetcount_gb,Register 69 (Transmit Octet Count for Good and Bad Frames)"
hexmask.long 0x0 0.--31. 1. "cnt,This field indicates the number of bytes transmitted in good and bad frames exclusive of preamble and retried bytes."
line.long 0x4 "gmacgrp_txframecount_gb,Register 70 (Transmit Frame Count for Good and Bad Frames)"
hexmask.long 0x4 0.--31. 1. "cnt,This field indicates the number of good and bad frames transmitted  exclusive of retried frames"
line.long 0x8 "gmacgrp_txbroadcastframes_g,Register 71 (Transmit Frame Count for Good Broadcast Frames)"
hexmask.long 0x8 0.--31. 1. "cnt,This field indicates the number of transmitted good broadcast frames."
line.long 0xC "gmacgrp_txmulticastframes_g,Register 72 (Transmit Frame Count for Good Multicast Frames)"
hexmask.long 0xC 0.--31. 1. "cnt,This field indicates the number of transmitted good multicast frames."
line.long 0x10 "gmacgrp_tx64octets_gb,Register 73 (Transmit Octet Count for Good and Bad 64 Byte Frames)"
hexmask.long 0x10 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad frames with length of 64 bytes  exclusive of preamble and retried frames."
line.long 0x14 "gmacgrp_tx65to127octets_gb,Register 74 (Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames)"
hexmask.long 0x14 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad frames with length between 65 and 127 (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x18 "gmacgrp_tx128to255octets_gb,Register 75 (Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames)"
hexmask.long 0x18 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad frames with length between 128 and 255 (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x1C "gmacgrp_tx256to511octets_gb,Register 76 (Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames)"
hexmask.long 0x1C 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad frames with length between 256 and 511 (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x20 "gmacgrp_tx512to1023octets_gb,Register 77 (Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames)"
hexmask.long 0x20 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad frames with length between 512 and 1 023 (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x24 "gmacgrp_tx1024tomaxoctets_gb,Register 78 (Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames)"
hexmask.long 0x24 0.--31. 1. "cnt,This field indicates the number of good and bad frames transmitted with length between 1 024 and maxsize (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x28 "gmacgrp_txunicastframes_gb,Register 79 (Transmit Frame Count for Good and Bad Unicast Frames)"
hexmask.long 0x28 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad unicast frames."
line.long 0x2C "gmacgrp_txmulticastframes_gb,Register 80 (Transmit Frame Count for Good and Bad Multicast Frames)"
hexmask.long 0x2C 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad multicast frames."
line.long 0x30 "gmacgrp_txbroadcastframes_gb,Register 81 (Transmit Frame Count for Good and Bad Broadcast Frames)"
hexmask.long 0x30 0.--31. 1. "cnt,This field indicates the number of transmitted good and bad broadcast frames."
line.long 0x34 "gmacgrp_txunderflowerror,Register 82 (Transmit Frame Count for Underflow Error Frames)"
hexmask.long 0x34 0.--31. 1. "cnt,This field indicates the number of frames aborted because of frame underflow error."
line.long 0x38 "gmacgrp_txsinglecol_g,Register 83 (Transmit Frame Count for Frames Transmitted after Single Collision)"
hexmask.long 0x38 0.--31. 1. "cnt,This field indicates the number of successfully transmitted frames after a single collision in the half-duplex mode."
line.long 0x3C "gmacgrp_txmulticol_g,Register 84 (Transmit Frame Count for Frames Transmitted after Multiple Collision)"
hexmask.long 0x3C 0.--31. 1. "cnt,This field indicates the number of successfully transmitted frames after multiple collisions in the half-duplex mode."
line.long 0x40 "gmacgrp_txdeferred,Register 85 (Transmit Frame Count for Deferred Frames)"
hexmask.long 0x40 0.--31. 1. "cnt,This field indicates the number of successfully transmitted frames after a deferral in the half-duplex mode."
line.long 0x44 "gmacgrp_txlatecol,Register 86 (Transmit Frame Count for Late Collision Error Frames)"
hexmask.long 0x44 0.--31. 1. "cnt,This field indicates the number of frames aborted because of late collision error."
line.long 0x48 "gmacgrp_txexesscol,Register 87 (Transmit Frame Count for Excessive Collision Error Frames)"
hexmask.long 0x48 0.--31. 1. "cnt,This field indicates the number of frames aborted because of excessive (16) collision error."
line.long 0x4C "gmacgrp_txcarriererr,Register 88 (Transmit Frame Count for Carrier Sense Error Frames)"
hexmask.long 0x4C 0.--31. 1. "cnt,This field indicates the number of frames aborted because of carrier sense error (no carrier or loss of carrier)."
line.long 0x50 "gmacgrp_txoctetcnt,Register 89 (Transmit Octet Count for Good Frames)"
hexmask.long 0x50 0.--31. 1. "txoctetcount_g,This field indicates the number of bytes transmitted  exclusive of preamble  in good frames."
line.long 0x54 "gmacgrp_txframecount_g,Register 90 (Transmit Frame Count for Good Frames)"
hexmask.long 0x54 0.--31. 1. "cnt,This field indicates the number of transmitted good frames  exclusive of preamble."
line.long 0x58 "gmacgrp_txexcessdef,Register 91 (Transmit Frame Count for Excessive Deferral Error Frames)"
hexmask.long 0x58 0.--31. 1. "cnt,This field indicates the number of frames aborted because of excessive deferral error  that is  frames deferred for more than two max-sized frame times."
line.long 0x5C "gmacgrp_txpauseframes,Register 92 (Transmit Frame Count for Good PAUSE Frames)"
hexmask.long 0x5C 0.--31. 1. "cnt,This field indicates the number of transmitted good PAUSE frames."
line.long 0x60 "gmacgrp_txvlanframes_g,Register 93 (Transmit Frame Count for Good VLAN Frames)"
hexmask.long 0x60 0.--31. 1. "cnt,This register maintains the number of transmitted good VLAN frames  exclusive of retried frames."
line.long 0x64 "gmacgrp_txoversize_g,Register 94 (Transmit Frame Count for Good Oversize Frames)"
hexmask.long 0x64 0.--31. 1. "cnt,This field indicates the number of frames transmitted without errors and with length greater than the maxsize (1 518 or 1 522 bytes for VLAN tagged frames; 2000 bytes if enabled in bit 27 of Register 0 (MAC Configuration Register))."
rgroup.long 0x180++0x67
line.long 0x0 "gmacgrp_rxframecount_gb,Register 96 (Receive Frame Count for Good and Bad Frames)"
hexmask.long 0x0 0.--31. 1. "cnt,This field indicates the number of received good and bad frames."
line.long 0x4 "gmacgrp_rxoctetcount_gb,Register 97 (Receive Octet Count for Good and Bad Frames)"
hexmask.long 0x4 0.--31. 1. "cnt,This field indicates the number of bytes received  exclusive of preamble  in good and bad frames."
line.long 0x8 "gmacgrp_rxoctetcount_g,Register 98 (Receive Octet Count for Good Frames)"
hexmask.long 0x8 0.--31. 1. "cnt,This field indicates the number of bytes received  exclusive of preamble  only in good frames."
line.long 0xC "gmacgrp_rxbroadcastframes_g,Register 99 (Receive Frame Count for Good Broadcast Frames)"
hexmask.long 0xC 0.--31. 1. "cnt,This field indicates the number of received good broadcast frames."
line.long 0x10 "gmacgrp_rxmulticastframes_g,Register 100 (Receive Frame Count for Good Multicast Frames)"
hexmask.long 0x10 0.--31. 1. "cnt,This field indicates the number of received good multicast frames."
line.long 0x14 "gmacgrp_rxcrcerror,Register 101 (Receive Frame Count for CRC Error Frames)"
hexmask.long 0x14 0.--31. 1. "cnt,This field indicates the number of frames received with CRC error."
line.long 0x18 "gmacgrp_rxalignmenterror,Register 102 (Receive Frame Count for Alignment Error Frames)"
hexmask.long 0x18 0.--31. 1. "cnt,This field indicates the number of frames received with alignment (dribble) error. This field is valid only in the 10 or 100 Mbps mode."
line.long 0x1C "gmacgrp_rxrunterror,Register 103 (Receive Frame Count for Runt Error Frames)"
hexmask.long 0x1C 0.--31. 1. "cnt,This field indicates the number of frames received with runt error(< bytes and CRC error)."
line.long 0x20 "gmacgrp_rxjabbererror,Register 104 (Receive Frame Count for Jabber Error Frames)"
hexmask.long 0x20 0.--31. 1. "cnt,This field indicates the number of giant frames received with length (including CRC) greater than 1 518 bytes (1 522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled  then frames of length greater than 9 018 bytes (9 022 for.."
line.long 0x24 "gmacgrp_rxundersize_g,Register 105 (Receive Frame Count for Undersize Frames)"
hexmask.long 0x24 0.--31. 1. "cnt,This field indicates the number of frames received with length less than 64 bytes and without errors."
line.long 0x28 "gmacgrp_rxoversize_g,Register 106 (Receive Frame Count for Oversize Frames)"
hexmask.long 0x28 0.--31. 1. "cnt,This field indicates the number of frames received without errors  with length greater than the maxsize (1 518 or 1 522 for VLAN tagged frames; 2 000 bytes if enabled in bit 27 of Register 0 (MAC Configuration Register))."
line.long 0x2C "gmacgrp_rx64octets_gb,Register 107 (Receive Frame Count for Good and Bad 64 Byte Frames)"
hexmask.long 0x2C 0.--31. 1. "cnt,This field indicates the number of received good and bad frames with length 64 bytes  exclusive of preamble."
line.long 0x30 "gmacgrp_rx65to127octets_gb,Register 108 (Receive Frame Count for Good and Bad 65 to 127 Bytes Frames)"
hexmask.long 0x30 0.--31. 1. "cnt,This field indicates the number of received good and bad frames received with length between 65 and 127 (inclusive) bytes  exclusive of preamble."
line.long 0x34 "gmacgrp_rx128to255octets_gb,Register 109 (Receive Frame Count for Good and Bad 128 to 255 Bytes Frames)"
hexmask.long 0x34 0.--31. 1. "cnt,This field indicates the number of received good and bad frames with length between 128 and 255 (inclusive) bytes  exclusive of preamble."
line.long 0x38 "gmacgrp_rx256to511octets_gb,Register 110 (Receive Frame Count for Good and Bad 256 to 511 Bytes Frames)"
hexmask.long 0x38 0.--31. 1. "cnt,This field indicates the number of received good and bad frames with length between 256 and 511 (inclusive) bytes  exclusive of preamble."
line.long 0x3C "gmacgrp_rx512to1023octets_gb,Register 111 (Receive Frame Count for Good and Bad 512 to 1.023 Bytes Frames)"
hexmask.long 0x3C 0.--31. 1. "cnt,This field indicates the number of received good and bad frames with length between 512 and 1 023 (inclusive) bytes  exclusive of preamble."
line.long 0x40 "gmacgrp_rx1024tomaxoctets_gb,Register 112 (Receive Frame Count for Good and Bad 1.024 to Maxsize Bytes Frames)"
hexmask.long 0x40 0.--31. 1. "cnt,This field indicates the number of received good and bad frames with length between 1 024 and maxsize (inclusive) bytes  exclusive of preamble and retried frames."
line.long 0x44 "gmacgrp_rxunicastframes_g,Register 113 (Receive Frame Count for Good Unicast Frames)"
hexmask.long 0x44 0.--31. 1. "cnt,This field indicates the number of received good unicast frames."
line.long 0x48 "gmacgrp_rxlengtherror,Register 114 (Receive Frame Count for Length Error Frames)"
hexmask.long 0x48 0.--31. 1. "cnt,This field indicates the number of frames received with length error (Length type field not equal to frame size) for all frames with valid length field."
line.long 0x4C "gmacgrp_rxoutofrangetype,Register 115 (Receive Frame Count for Out of Range Frames)"
hexmask.long 0x4C 0.--31. 1. "cnt,This field indicates the number of received frames with length field not equal to the valid frame size (greater than 1 500 but less than 1 536)."
line.long 0x50 "gmacgrp_rxpauseframes,Register 116 (Receive Frame Count for PAUSE Frames)"
hexmask.long 0x50 0.--31. 1. "cnt,This field indicates the number of received good and valid PAUSE frames."
line.long 0x54 "gmacgrp_rxfifooverflow,Register 117 (Receive Frame Count for FIFO Overflow Frames)"
hexmask.long 0x54 0.--31. 1. "cnt,This field indicates the number of received frames missed because of FIFO overflow."
line.long 0x58 "gmacgrp_rxvlanframes_gb,Register 118 (Receive Frame Count for Good and Bad VLAN Frames)"
hexmask.long 0x58 0.--31. 1. "cnt,This field indicates the number of received good and bad VLAN frames."
line.long 0x5C "gmacgrp_rxwatchdogerror,Register 119 (Receive Frame Count for Watchdog Error Frames)"
hexmask.long 0x5C 0.--31. 1. "cnt,This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2 048 bytes or value programmed in Register 55 (Watchdog Timeout Register))."
line.long 0x60 "gmacgrp_rxrcverror,Register 120 (Receive Frame Count for Receive Error Frames)"
hexmask.long 0x60 0.--31. 1. "cnt,This field indicates the number of frames received with error because of the GMII/MII RXER error or Frame Extension error on GMII."
line.long 0x64 "gmacgrp_rxctrlframes_g,Register 121 (Receive Frame Count for Good Control Frames Frames)"
hexmask.long 0x64 0.--31. 1. "cnt,This field indicates the number of good control frames received."
group.long 0x200++0x3
line.long 0x0 "gmacgrp_mmc_ipc_receive_interrupt_mask,This register maintains the mask for the interrupt generated from the receive IPC statistic"
bitfld.long 0x0 29. "rxicmperoim,Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 28. "rxicmpgoim,Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 27. "rxtcperoim,Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 26. "rxtcpgoim,Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 25. "rxudperoim,Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 24. "rxudpgoim,Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 23. "rxipv6nopayoim,Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 22. "rxipv6heroim,Setting this bit masks interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 21. "rxipv6goim,Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 20. "rxipv4udsbloim,Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 19. "rxipv4fragoim,Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 18. "rxipv4nopayoim,Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 17. "rxipv4heroim,Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 16. "rxipv4goim,Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 13. "rxicmperfim,Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 12. "rxicmpgfim,Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 11. "rxtcperfim,Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 10. "rxtcpgfim,Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 9. "rxudperfim,Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 8. "rxudpgfim,Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 7. "rxipv6nopayfim,Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 6. "rxipv6herfim,Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 5. "rxipv6gfim,Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 4. "rxipv4udsblfim,Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 3. "rxipv4fragfim,Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 2. "rxipv4nopayfim,Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 1. "rxipv4herfim,Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 0. "rxipv4gfim,Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
rgroup.long 0x208++0x3
line.long 0x0 "gmacgrp_mmc_ipc_receive_interrupt,This register maintains the interrupts generated when receive IPC statistic counters reach half their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter). and when they cross their maximum.."
bitfld.long 0x0 29. "rxicmperois,This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 28. "rxicmpgois,This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 27. "rxtcperois,This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 26. "rxtcpgois,This bit is set when the rxtcp_gd_octets counter reaches half the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 25. "rxudperois,This bit is set when the rxudp_err_octets counter reaches half the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 24. "rxudpgois,This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 23. "rxipv6nopayois,This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 22. "rxipv6herois,This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 21. "rxipv6gois,This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 20. "rxipv4udsblois,This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 19. "rxipv4fragois,This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 18. "rxipv4nopayois,This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 17. "rxipv4herois,This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 16. "rxipv4gois,This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 13. "rxicmperfis,This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 12. "rxicmpgfis,This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 11. "rxtcperfis,This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 10. "rxtcpgfis,This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 9. "rxudperfis,This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 8. "rxudpgfis,This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 7. "rxipv6nopayfis,This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 6. "rxipv6herfis,This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 5. "rxipv6gfis,This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 4. "rxipv4udsblfis,This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 3. "rxipv4fragfis,This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 2. "rxipv4nopayfis,This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 1. "rxipv4herfis,This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value." "0,1"
newline
bitfld.long 0x0 0. "rxipv4gfis,This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value." "0,1"
rgroup.long 0x210++0x37
line.long 0x0 "gmacgrp_rxipv4_gd_frms,Number of good IPv4 datagrams received with the TCP. UDP. or ICMP payload"
hexmask.long 0x0 0.--31. 1. "cnt,Number of good IPv4 datagrams received with the TCP  UDP  or ICMP payload"
line.long 0x4 "gmacgrp_rxipv4_hdrerr_frms,Number of IPv4 datagrams received with header (checksum. length. or version mismatch) errors"
hexmask.long 0x4 0.--31. 1. "cnt,Number of IPv4 datagrams received with header (checksum  length  or version mismatch) errors"
line.long 0x8 "gmacgrp_rxipv4_nopay_frms,Number of IPv4 datagram frames received that did not have a TCP. UDP. or ICMP payload processed by the Checksum engine"
hexmask.long 0x8 0.--31. 1. "cnt,Number of IPv4 datagram frames received that did not have a TCP  UDP  or ICMP payload processed by the Checksum engine"
line.long 0xC "gmacgrp_rxipv4_frag_frms,Number of good IPv4 datagrams with fragmentation"
hexmask.long 0xC 0.--31. 1. "cnt,Number of good IPv4 datagrams with fragmentation"
line.long 0x10 "gmacgrp_rxipv4_udsbl_frms,Number of good IPv4 datagrams received that had a UDP payload with checksum disabled"
hexmask.long 0x10 0.--31. 1. "cnt,Number of good IPv4 datagrams received that had a UDP payload with checksum disabled"
line.long 0x14 "gmacgrp_rxipv6_gd_frms,Number of good IPv6 datagrams received with TCP. UDP. or ICMP payloads"
hexmask.long 0x14 0.--31. 1. "cnt,Number of good IPv6 datagrams received with TCP  UDP  or ICMP payloads"
line.long 0x18 "gmacgrp_rxipv6_hdrerr_frms,Number of IPv6 datagrams received with header errors (length or version mismatch)"
hexmask.long 0x18 0.--31. 1. "cnt,Number of IPv6 datagrams received with header errors (length or version mismatch)"
line.long 0x1C "gmacgrp_rxipv6_nopay_frms,Number of IPv6 datagram frames received that did not have a TCP. UDP. or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers"
hexmask.long 0x1C 0.--31. 1. "cnt,Number of IPv6 datagram frames received that did not have a TCP  UDP  or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers"
line.long 0x20 "gmacgrp_rxudp_gd_frms,Number of good IP datagrams with a good UDP payload. This counter is not updated when the counter is incremented"
hexmask.long 0x20 0.--31. 1. "cnt,Number of good IP datagrams with a good UDP payload. This counter is not updated when the counter is incremented"
line.long 0x24 "gmacgrp_rxudp_err_frms,Number of good IP datagrams whose UDP payload has a checksum error"
hexmask.long 0x24 0.--31. 1. "cnt,Number of good IP datagrams whose UDP payload has a checksum error"
line.long 0x28 "gmacgrp_rxtcp_gd_frms,Number of good IP datagrams with a good TCP payload"
hexmask.long 0x28 0.--31. 1. "cnt,Number of good IP datagrams with a good TCP payload"
line.long 0x2C "gmacgrp_rxtcp_err_frms,Number of good IP datagrams whose TCP payload has a checksum error"
hexmask.long 0x2C 0.--31. 1. "cnt,Number of good IP datagrams whose TCP payload has a checksum error"
line.long 0x30 "gmacgrp_rxicmp_gd_frms,Number of good IP datagrams with a good ICMP payload"
hexmask.long 0x30 0.--31. 1. "cnt,Number of good IP datagrams with a good ICMP payload"
line.long 0x34 "gmacgrp_rxicmp_err_frms,Number of good IP datagrams whose ICMP payload has a checksum error"
hexmask.long 0x34 0.--31. 1. "cnt,Number of good IP datagrams whose ICMP payload has a checksum error"
rgroup.long 0x250++0x37
line.long 0x0 "gmacgrp_rxipv4_gd_octets,Number of bytes received in good IPv4 datagrams encapsulating TCP. UDP. or ICMP data"
hexmask.long 0x0 0.--31. 1. "cnt,Number of bytes received in good IPv4 datagrams encapsulating TCP  UDP  or ICMP data"
line.long 0x4 "gmacgrp_rxipv4_hdrerr_octets,Number of bytes received in IPv4 datagrams with header errors (checksum. length. version mismatch). The value in the Length field of IPv4 header is used to update this counter"
hexmask.long 0x4 0.--31. 1. "cnt,Number of bytes received in IPv4 datagrams with header errors (checksum  length  version mismatch). The value in the Length field of IPv4 header is used to update this counter"
line.long 0x8 "gmacgrp_rxipv4_nopay_octets,Number of bytes received in IPv4 datagrams that did not have a TCP. UDP. or ICMP payload. The value in the IPv4 headers Length field is used to update this counter"
hexmask.long 0x8 0.--31. 1. "cnt,Number of bytes received in IPv4 datagrams that did not have a TCP  UDP  or ICMP payload. The value in the IPv4 headers Length field is used to update this counter"
line.long 0xC "gmacgrp_rxipv4_frag_octets,Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 headers Length field is used to update this counter"
hexmask.long 0xC 0.--31. 1. "cnt,Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 headers Length field is used to update this counter"
line.long 0x10 "gmacgrp_rxipv4_udsbl_octets,Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes"
hexmask.long 0x10 0.--31. 1. "cnt,Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes"
line.long 0x14 "gmacgrp_rxipv6_gd_octets,Number of bytes received in good IPv6 datagrams encapsulating TCP. UDP or ICMPv6 data"
hexmask.long 0x14 0.--31. 1. "cnt,Number of bytes received in good IPv6 datagrams encapsulating TCP  UDP or ICMPv6 data"
line.long 0x18 "gmacgrp_rxipv6_hdrerr_octets,Number of bytes received in IPv6 datagrams with header errors (length. version mismatch). The value in the IPv6 headers Length field is used to update this counter"
hexmask.long 0x18 0.--31. 1. "cnt,Number of bytes received in IPv6 datagrams with header errors (length  version mismatch). The value in the IPv6 headers Length field is used to update this counter"
line.long 0x1C "gmacgrp_rxipv6_nopay_octets,Number of bytes received in IPv6 datagrams that did not have a TCP. UDP. or ICMP payload. The value in the IPv6 headers Length field is used to update this counter"
hexmask.long 0x1C 0.--31. 1. "cnt,Number of bytes received in IPv6 datagrams that did not have a TCP  UDP  or ICMP payload. The value in the IPv6 headers Length field is used to update this counter"
line.long 0x20 "gmacgrp_rxudp_gd_octets,Number of bytes received in a good UDP segment. This counter does not count IP header bytes"
hexmask.long 0x20 0.--31. 1. "cnt,Number of bytes received in a good UDP segment. This counter does not count IP header bytes"
line.long 0x24 "gmacgrp_rxudp_err_octets,Number of bytes received in a UDP segment that had checksum errors"
hexmask.long 0x24 0.--31. 1. "cnt,Number of bytes received in a UDP segment that had checksum errors"
line.long 0x28 "gmacgrp_rxtcp_gd_octets,Number of bytes received in a good TCP segment"
hexmask.long 0x28 0.--31. 1. "cnt,Number of bytes received in a good TCP segment"
line.long 0x2C "gmacgrp_rxtcperroctets,Number of bytes received in a TCP segment with checksum errors"
hexmask.long 0x2C 0.--31. 1. "rxtcp_err_octets,Number of bytes received in a TCP segment with checksum errors"
line.long 0x30 "gmacgrp_rxicmp_gd_octets,Number of bytes received in a good ICMP segment"
hexmask.long 0x30 0.--31. 1. "cnt,Number of bytes received in a good ICMP segment"
line.long 0x34 "gmacgrp_rxicmp_err_octets,Number of bytes received in an ICMP segment with checksum errors"
hexmask.long 0x34 0.--31. 1. "cnt,Number of bytes received in an ICMP segment with checksum errors"
group.long 0x400++0x7
line.long 0x0 "gmacgrp_l3_l4_control0,Register 256 (Layer 3 and Layer 4 Control Register 0)"
hexmask.long.word 0x0 22.--31. 1. "reserved_31_22,Reserved"
newline
bitfld.long 0x0 21. "l4dpim0,Layer 4 Destination Port Inverse Match Enable" "0,1"
newline
bitfld.long 0x0 20. "l4dpm0,Layer 4 Destination Port Match Enable" "0,1"
newline
bitfld.long 0x0 19. "l4spim0,Layer 4 Source Port Inverse Match Enable" "0,1"
newline
bitfld.long 0x0 18. "l4spm0,Layer 4 Source Port Match Enable" "0,1"
newline
rbitfld.long 0x0 17. "reserved_17,Reserved" "0,1"
newline
bitfld.long 0x0 16. "l4pen0,Layer 4 Protocol Enable" "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "l3hdbm0,Layer 3 IP DA Higher Bits Match"
newline
hexmask.long.byte 0x0 6.--10. 1. "l3hsbm0,Layer 3 IP SA Higher Bits Match"
newline
bitfld.long 0x0 5. "l3daim0,Layer 3 IP DA Inverse Match Enable" "0,1"
newline
bitfld.long 0x0 4. "l3dam0,Layer 3 IP DA Match Enable" "0,1"
newline
bitfld.long 0x0 3. "l3saim0,Layer 3 IP SA Inverse Match Enable" "0,1"
newline
bitfld.long 0x0 2. "l3sam0,Layer 3 IP SA Match Enable" "0,1"
newline
rbitfld.long 0x0 1. "reserved_1,Reserved" "0,1"
newline
bitfld.long 0x0 0. "l3pen0,Layer 3 Protocol Enable" "0,1"
line.long 0x4 "gmacgrp_layer4_address0,Register 257 (Layer 4 Address Register 0)"
hexmask.long.word 0x4 16.--31. 1. "l4dp0,Layer 4 Destination Port Number Field"
newline
hexmask.long.word 0x4 0.--15. 1. "l4sp0,Layer 4 Source Port Number Field"
group.long 0x410++0xF
line.long 0x0 "gmacgrp_layer3_addr0_reg0,Register 260 (Layer 3 Address 0 Register 0)"
hexmask.long 0x0 0.--31. 1. "l3a00,Layer 3 Address 0 Field"
line.long 0x4 "gmacgrp_layer3_addr1_reg0,Register 261 (Layer 3 Address 1 Register 0)"
hexmask.long 0x4 0.--31. 1. "l3a10,Layer 3 Address 1 Field"
line.long 0x8 "gmacgrp_layer3_addr2_reg0,Register 262 (Layer 3 Address 2 Register 0)"
hexmask.long 0x8 0.--31. 1. "l3a20,Layer 3 Address 2 Field"
line.long 0xC "gmacgrp_layer3_addr3_reg0,Register 263 (Layer 3 Address 3 Register 0)"
hexmask.long 0xC 0.--31. 1. "l3a30,Layer 3 Address 3 Field"
group.long 0x430++0x7
line.long 0x0 "gmacgrp_l3_l4_control1,This register controls the operations of the filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 21. "l4dpim1,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching." "0,1"
newline
bitfld.long 0x0 20. "l4dpm1,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for matching." "0,1"
newline
bitfld.long 0x0 19. "l4spim1,When set  this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching." "0,1"
newline
bitfld.long 0x0 18. "l4spm1,When set  this bit indicates that the Layer 4 Source Port number field is enabled for matching." "0,1"
newline
bitfld.long 0x0 16. "l4pen1,When set  this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset  this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "l3hdbm1,IPv4 Frames:"
newline
hexmask.long.byte 0x0 6.--10. 1. "l3hsbm1,IPv4 Frames:"
newline
bitfld.long 0x0 5. "l3daim1,When set  this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching." "0,1"
newline
bitfld.long 0x0 4. "l3dam1,When set  this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Destination Address field for matching." "0,1"
newline
bitfld.long 0x0 3. "l3saim1,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching." "0,1"
newline
bitfld.long 0x0 2. "l3sam1,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Source Address field for matching." "0,1"
newline
bitfld.long 0x0 0. "l3pen1,When set  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames." "0,1"
line.long 0x4 "gmacgrp_layer4_address1,Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains. then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer.."
hexmask.long.word 0x4 16.--31. 1. "l4dp1,When Bit 16 (L4PEN1) is reset and Bit 20 (L4DPM1) is set in Register 268 (Layer 3 and Layer 4 Control Register 0)  this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames."
newline
hexmask.long.word 0x4 0.--15. 1. "l4sp1,When Bit 16 (L4PEN1) is reset and Bit 20 (L4DPM1) is set in Register 268 (Layer 3 and Layer 4 Control Register 1)  this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames."
group.long 0x440++0xF
line.long 0x0 "gmacgrp_layer3_addr0_reg1,For IPv4 frames. the Layer 3 Address 0 Register 1 contains the 32-bit IP Source Address field. For IPv6 frames. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "l3a01,When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and Layer 4 Control Register 1)  this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 frames."
line.long 0x4 "gmacgrp_layer3_addr1_reg1,For IPv4 frames. the Layer 3 Address 1 Register 1 contains the 32-bit IP Destination Address field. For IPv6 frames. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field"
hexmask.long 0x4 0.--31. 1. "l3a11,When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and Layer 4 Control Register 1)  this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames."
line.long 0x8 "gmacgrp_layer3_addr2_reg1,For IPv4 frames. the Layer 3 Address 2 Register 1 is reserved. For IPv6 frames. it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x8 0.--31. 1. "l3a21,When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and Layer 4 Control Register 1)  this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames."
line.long 0xC "gmacgrp_layer3_addr3_reg1,For IPv4 frames. the Layer 3 Address 3 Register 1 is reserved. For IPv6 frames. it contains Bits [127:96] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0xC 0.--31. 1. "l3a31,When Bit 1 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and Layer 4 Control Register 1)  this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames."
group.long 0x460++0x7
line.long 0x0 "gmacgrp_l3_l4_control2,This register controls the operations of the filter 2 of Layer 3 and Layer 4."
bitfld.long 0x0 21. "l4dpim2,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset  this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 20. "l4dpm2,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset  the MAC ignores the Layer 4 Destination Port number field for matching." "0,1"
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bitfld.long 0x0 19. "l4spim2,When set  this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset  this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 18. "l4spm2,When set  this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset  the MAC ignores the Layer 4 Source Port number field for matching." "0,1"
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bitfld.long 0x0 16. "l4pen2,When set  this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset  this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching." "0,1"
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hexmask.long.byte 0x0 11.--15. 1. "l3hdbm2,IPv4 Frames:"
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hexmask.long.byte 0x0 6.--10. 1. "l3hsbm2,Layer 3 IP SA Higher Bits Match"
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bitfld.long 0x0 5. "l3daim2,When set  this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 4. "l3dam2,When set  this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Destination Address field for matching." "0,1"
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bitfld.long 0x0 3. "l3saim2,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 2. "l3sam2,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Source Address field for matching." "0,1"
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bitfld.long 0x0 0. "l3pen2,When set  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames." "0,1"
line.long 0x4 "gmacgrp_layer4_address2,Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains. then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer.."
hexmask.long.word 0x4 16.--31. 1. "l4dp2,When Bit 16 (L4PEN2) is reset and Bit 20 (L4DPM2) is set in Register 280 (Layer 3 and Layer 4 Control Register 2)  this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames."
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hexmask.long.word 0x4 0.--15. 1. "l4sp2,When Bit 16 (L4PEN2) is reset and Bit 20 (L4DPM2) is set in Register 280 (Layer 3 and Layer 4 Control Register 2)  this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames."
group.long 0x470++0xF
line.long 0x0 "gmacgrp_layer3_addr0_reg2,For IPv4 frames. the Layer 3 Address 0 Register 2 contains the 32-bit IP Source Address field. For IPv6 frames. it contains Bits [31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "l3a02,When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and Layer 4 Control Register 2)  this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames."
line.long 0x4 "gmacgrp_layer3_addr1_reg2,For IPv4 frames. the Layer 3 Address 1 Register 2 contains the 32-bit IP Destination Address field. For IPv6 frames. it contains Bits [63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x4 0.--31. 1. "l3a12,Layer 3 Address 1 Field"
line.long 0x8 "gmacgrp_layer3_addr2_reg2,For IPv4 frames. the Layer 3 Address 2 Register 2 is reserved. For IPv6 frames. it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x8 0.--31. 1. "l3a22,When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and Layer 4 Control Register 2)  this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames."
line.long 0xC "gmacgrp_layer3_addr3_reg2,For IPv4 frames. the Layer 3 Address 3 Register 2 is reserved. For IPv6 frames. it contains Bits [127:96] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0xC 0.--31. 1. "l3a32,When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and Layer 4 Control Register 2)  this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames."
group.long 0x490++0x7
line.long 0x0 "gmacgrp_l3_l4_control3,This register controls the operations of the filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 21. "l4dpim3,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset  this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 20. "l4dpm3,When set  this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset  the MAC ignores the Layer 4 Destination Port number field for matching." "0,1"
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bitfld.long 0x0 19. "l4spim3,When set  this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset  this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 18. "l4spm3,When set  this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset  the MAC ignores the Layer 4 Source Port number field for matching." "0,1"
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bitfld.long 0x0 16. "l4pen3,When set  this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset  this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching." "0,1"
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hexmask.long.byte 0x0 11.--15. 1. "l3hdbm3,Layer 3 IP DA Higher Bits Match"
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hexmask.long.byte 0x0 6.--10. 1. "l3hsbm3,IPv4 Frames:"
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bitfld.long 0x0 5. "l3daim3,When set  this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 4. "l3dam3,When set  this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Destination Address field for matching." "0,1"
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bitfld.long 0x0 3. "l3saim3,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset  this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching." "0,1"
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bitfld.long 0x0 2. "l3sam3,When set  this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset  the MAC ignores the Layer 3 IP Source Address field for matching." "0,1"
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bitfld.long 0x0 0. "l3pen3,When set  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset  this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames." "0,1"
line.long 0x4 "gmacgrp_layer4_address3,Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains. then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer.."
hexmask.long.word 0x4 16.--31. 1. "l4dp3,When Bit 16 (L4PEN3) is reset and Bit 20 (L4DPM3) is set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames."
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hexmask.long.word 0x4 0.--15. 1. "l4sp3,When Bit 16 (L4PEN3) is reset and Bit 20 (L4DPM3) is set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames."
group.long 0x4A0++0xF
line.long 0x0 "gmacgrp_layer3_addr0_reg3,For IPv4 frames. the Layer 3 Address 0 Register 3 contains the 32-bit IP Source Address field. For IPv6 frames. it contains Bits [31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "l3a03,When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames."
line.long 0x4 "gmacgrp_layer3_addr1_reg3,For IPv4 frames. the Layer 3 Address 1 Register 3 contains the 32-bit IP Destination Address field. For IPv6 frames. it contains Bits [63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x4 0.--31. 1. "l3a13,When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames."
line.long 0x8 "gmacgrp_layer3_addr2_reg3,For IPv4 frames. the Layer 3 Address 2 Register 3 is reserved. For IPv6 frames. it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x8 0.--31. 1. "l3a23,When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames."
line.long 0xC "gmacgrp_layer3_addr3_reg3,For IPv4 frames. the Layer 3 Address 3 Register 3 is reserved. For IPv6 frames. it contains Bits [127:96] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0xC 0.--31. 1. "l3a33,When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and Layer 4 Control Register 3)  this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames."
group.long 0x500++0x1F
line.long 0x0 "gmacgrp_hash_table_reg0,This register contains the first 32 bits of the hash table."
hexmask.long 0x0 0.--31. 1. "ht31t0,This field contains the first 32 Bits (31:0) of the Hash table."
line.long 0x4 "gmacgrp_hash_table_reg1,This register contains the second 32 bits of the hash table."
hexmask.long 0x4 0.--31. 1. "ht63t32,This field contains the second 32 Bits (63:32) of the Hash table."
line.long 0x8 "gmacgrp_hash_table_reg2,This register contains the third 32 bits of the hash table."
hexmask.long 0x8 0.--31. 1. "ht95t64,This field contains the third 32 Bits (95:64) of the Hash table."
line.long 0xC "gmacgrp_hash_table_reg3,This register contains the fourth 32 bits of the hash table."
hexmask.long 0xC 0.--31. 1. "ht127t96,This field contains the fourth 32 Bits (127:96) of the Hash table."
line.long 0x10 "gmacgrp_hash_table_reg4,This register contains the fifth 32 bits of the hash table."
hexmask.long 0x10 0.--31. 1. "ht159t128,This field contains the fifth 32 Bits (159:128) of the Hash table."
line.long 0x14 "gmacgrp_hash_table_reg5,This register contains the sixth 32 bits of the hash table."
hexmask.long 0x14 0.--31. 1. "ht191t160,This field contains the sixth 32 Bits (191:160) of the Hash table."
line.long 0x18 "gmacgrp_hash_table_reg6,This register contains the seventh 32 bits of the hash table."
hexmask.long 0x18 0.--31. 1. "ht223t196,This field contains the seventh 32 Bits (223:196) of the Hash table."
line.long 0x1C "gmacgrp_hash_table_reg7,This register contains the eighth 32 bits of the hash table."
hexmask.long 0x1C 0.--31. 1. "ht255t224,This field contains the eighth 32 Bits (255:224) of the Hash table."
group.long 0x584++0x7
line.long 0x0 "gmacgrp_vlan_incl_reg,Register 353 (VLAN Tag Inclusion or Replacement Register)"
hexmask.long.word 0x0 20.--31. 1. "reserved_31_20,Reserved"
newline
bitfld.long 0x0 19. "csvl,C-VLAN or S-VLAN" "0,1"
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bitfld.long 0x0 18. "vlp,VLAN Priority Control" "0,1"
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bitfld.long 0x0 16.--17. "vlc,VLAN Tag Control in Transmit Frames" "0: No VLAN tag deletion,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
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hexmask.long.word 0x0 0.--15. 1. "vlt,VLAN Tag for Transmit Frames"
line.long 0x4 "gmacgrp_vlan_hash_table_reg,The 16-bit Hash table is used for group address filtering based on VLAN tag when Bit 18 (VTHM) of Register 7 (VLAN Tag Register) is set. For hash filtering. the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on Bit 16.."
hexmask.long.word 0x4 0.--15. 1. "vlht,This field contains the 16-bit VLAN Hash Table."
group.long 0x700++0x7
line.long 0x0 "gmacgrp_timestamp_control,Register 448 (Timestamp Control Register)"
rbitfld.long 0x0 29.--31. "reserved_31_29,Reserved" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 28. "atsen3,Auxiliary Snapshot 3 Enable" "0,1"
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rbitfld.long 0x0 27. "atsen2,Auxiliary Snapshot 2 Enable" "0,1"
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rbitfld.long 0x0 26. "atsen1,Auxiliary Snapshot 1 Enable" "0,1"
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rbitfld.long 0x0 25. "atsen0,Auxiliary Snapshot 0 Enable" "0,1"
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rbitfld.long 0x0 24. "atsfc,Auxiliary Snapshot FIFO Clear" "0,1"
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hexmask.long.byte 0x0 19.--23. 1. "reserved_23_19,Reserved"
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bitfld.long 0x0 18. "tsenmacaddr,Enable MAC address for PTP Frame Filtering" "0,1"
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bitfld.long 0x0 16.--17. "snaptypsel,Select PTP packets for Taking Snapshots" "0,1,2,3"
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bitfld.long 0x0 15. "tsmstrena,Enable Snapshot for Messages Relevant to Master" "0,1"
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bitfld.long 0x0 14. "tsevntena,Enable Timestamp Snapshot for Event Messages" "0,1"
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bitfld.long 0x0 13. "tsipv4ena,Enable Processing of PTP Frames Sent over IPv4-UDP" "0,1"
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bitfld.long 0x0 12. "tsipv6ena,Enable Processing of PTP Frames Sent Over IPv6-UDP" "0,1"
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bitfld.long 0x0 11. "tsipena,Enable Processing of PTP over Ethernet Frames" "0,1"
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bitfld.long 0x0 10. "tsver2ena,Enable PTP packet Processing for Version 2 Format" "0,1"
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bitfld.long 0x0 9. "tsctrlssr,Timestamp Digital or Binary Rollover Control" "0,1"
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bitfld.long 0x0 8. "tsenall,Enable Timestamp for All Frames" "0,1"
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rbitfld.long 0x0 6.--7. "reserved_7_6,Reserved" "0,1,2,3"
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rbitfld.long 0x0 5. "tsaddreg,Addend Reg Update" "0,1"
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rbitfld.long 0x0 4. "tstrig,Timestamp Interrupt Trigger Enable" "0,1"
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rbitfld.long 0x0 3. "tsupdt,Timestamp Update" "0,1"
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rbitfld.long 0x0 2. "tsinit,Timestamp Initialize" "0,1"
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rbitfld.long 0x0 1. "tscfupdt,Timestamp Fine or Coarse Update" "0,1"
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bitfld.long 0x0 0. "tsena,Timestamp Enable" "0,1"
line.long 0x4 "gmacgrp_sub_second_increment,In the Coarse Update mode (TSCFUPDT bit in Register 448). the value in this register is added to the system time every clock cycle of clk_ptp_ref_i. In the Fine Update mode. the value in this register is added to the system.."
hexmask.long.byte 0x4 0.--7. 1. "ssinc,The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example  when PTP clock is 50 MHz (period is 20 ns)  you should program 20 (0x14) when the System Time-Nanoseconds.."
rgroup.long 0x708++0x7
line.long 0x0 "gmacgrp_system_time_seconds,The System Time -Seconds register. along with System-TimeNanoseconds register. indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis. there is some delay from the.."
hexmask.long 0x0 0.--31. 1. "tss,The value in this field indicates the current value in seconds of the System Time maintained by the MAC."
line.long 0x4 "gmacgrp_system_time_nanoseconds,The value in this field has the sub second representation of time. with an accuracy of 0.46 ns. When TSCTRLSSR is set. each bit represents 1 ns and the maximum value is 0x3B9A_C9FF. after which it rolls-over to zero."
hexmask.long 0x4 0.--30. 1. "tsss,The value in this field has the sub second representation of time  with an accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)  each bit represents 1 ns and the maximum value is 0x3B9A_C9FF  after which it.."
group.long 0x710++0x17
line.long 0x0 "gmacgrp_system_time_seconds_update,The System Time - Seconds Update register. along with the System Time - Nanoseconds Update register. initializes or updates the system time maintained by the MAC. You must write both of these registers before setting.."
hexmask.long 0x0 0.--31. 1. "tss,The value in this field indicates the time in seconds to be initialized or added to the system time."
line.long 0x4 "gmacgrp_system_time_nanoseconds_update,Update system time"
bitfld.long 0x4 31. "addsub,When this bit is set  the time value is subtracted with the contents of the update register. When this bit is reset  the time value is added with the contents of the update register." "0,1"
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hexmask.long 0x4 0.--30. 1. "tsss,The value in this field has the sub second representation of time  with an accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)  each bit represents 1 ns and the programmed value should not exceed.."
line.long 0x8 "gmacgrp_timestamp_addend,This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in Register 448). This register content is added to a 32-bit accumulator in every clock cycle (of clk_ptp_ref_i) and the.."
hexmask.long 0x8 0.--31. 1. "tsar,This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization."
line.long 0xC "gmacgrp_target_time_seconds,The Target Time Seconds register. along with Target Time Nanoseconds register. is used to schedule an interrupt event (Register 458[1] when Advanced Timestamping is enabled; otherwise. TS interrupt bit in Register14[9]) when.."
hexmask.long 0xC 0.--31. 1. "tstr,This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers  then based on Bits [6:5] of Register 459 (PPS Control Register)  the MAC starts or stops the PPS signal output and generates an.."
line.long 0x10 "gmacgrp_target_time_nanoseconds,Target time"
rbitfld.long 0x10 31. "trgtbusy,The MAC sets this bit when the PPSCMD field (Bits[3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD field to 010 or 011  instructs the MAC to synchronize the Target Time Registers to the PTP clock.." "0,1"
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hexmask.long 0x10 0.--30. 1. "ttslo,This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers  then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register)  the MAC starts or stops the.."
line.long 0x14 "gmacgrp_system_time_higher_word_seconds,System time higher word"
hexmask.long.word 0x14 0.--15. 1. "tshwr,This field contains the most significant 16-bits of the timestamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register."
rgroup.long 0x728++0x3
line.long 0x0 "gmacgrp_timestamp_status,Timestamp status. All bits except Bits[27:25] get cleared when the host reads this register."
hexmask.long.byte 0x0 25.--29. 1. "atsns,This field indicates the number of Snapshots available in the FIFO. A value of 16 (equal to the depth of the FIFO) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is.."
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bitfld.long 0x0 24. "atsstm,This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO." "0,1"
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hexmask.long.byte 0x0 16.--19. 1. "atsstn,These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time  it means that corresponding auxiliary triggers were sampled at the.."
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bitfld.long 0x0 3. "tstrgterr,This bit is set when the target time  being programmed in Target Time Registers  is already elapsed. This bit is cleared when read by the application." "0,1"
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bitfld.long 0x0 2. "auxtstrig,This bit is set high when the auxiliary snapshot is written to the FIFO." "0,1"
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bitfld.long 0x0 1. "tstargt,When set  this bit indicates that the value of system time is greater or equal to the value specified in the Register 455 (Target Time Seconds Register) and Register 456 (Target Time Nanoseconds Register)." "0,1"
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bitfld.long 0x0 0. "tssovf,When set  this bit indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF." "0,1"
group.long 0x72C++0x3
line.long 0x0 "gmacgrp_pps_control,Controls timestamp Pulse-Per-Second output"
bitfld.long 0x0 5.--6. "trgtmodsel0,This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal" "0,1,2,3"
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bitfld.long 0x0 4. "ppsen0,When set low  Bits[3:0] function as PPSCTRL (backward compatible). When set high  Bits[3:0] function as PPSCMD." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "ppsctrl_ppscmd,PPSCTRL0: PPS0 Output Frequency Control"
rgroup.long 0x730++0x7
line.long 0x0 "gmacgrp_auxiliary_timestamp_nanoseconds,This register. along with Register 461 (Auxiliary Timestamp Seconds Register). gives the 64-bit timestamp stored as auxiliary snapshot. The two registers together form the read port of a 64-bit wide FIFO with a.."
hexmask.long 0x0 0.--30. 1. "auxtslo,Contains the lower 32 bits (nano-seconds field) of the auxiliary timestamp."
line.long 0x4 "gmacgrp_auxiliary_timestamp_seconds,Contains the higher 32 bits (Seconds field) of the auxiliary timestamp."
hexmask.long 0x4 0.--31. 1. "auxtshi,Contains the higher 32 bits (Seconds field) of the auxiliary timestamp."
group.long 0x760++0x7
line.long 0x0 "gmacgrp_pps0_interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])."
hexmask.long 0x0 0.--31. 1. "ppsint,These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value."
line.long 0x4 "gmacgrp_pps0_width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of the PPS0 signal output (ptp_pps_o[0])."
hexmask.long 0x4 0.--31. 1. "ppswidth,These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value."
group.long 0x800++0x37F
line.long 0x0 "gmacgrp_mac_address16_high,Register 512 (MAC Address16 High Register)"
bitfld.long 0x0 31. "ae,Address Enable" "0,1"
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bitfld.long 0x0 30. "sa,Source Address" "0,1"
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bitfld.long 0x0 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x0 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x0 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x0 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
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bitfld.long 0x0 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x0 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address16 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x0 0.--15. 1. "addrhi,MAC Address16 [47:32]"
line.long 0x4 "gmacgrp_mac_address16_low,Register 513 (MAC Address16 Low Register)"
hexmask.long 0x4 0.--31. 1. "addrlo,MAC Address16 [31:0]"
line.long 0x8 "gmacgrp_mac_address17_high,Register 514 (MAC Address17 High Register)"
bitfld.long 0x8 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x8 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x8 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x8 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x8 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x8 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x8 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x8 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address17 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x8 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x8 0.--15. 1. "addrhi,MAC Address18 [47:32]"
line.long 0xC "gmacgrp_mac_address17_low,Register 515 (MAC Address17 Low Register)"
hexmask.long 0xC 0.--31. 1. "addrlo,MAC Address17 [31:0]"
line.long 0x10 "gmacgrp_mac_address18_high,Register 516 (MAC Address18 High Register)"
bitfld.long 0x10 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x10 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x10 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x10 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x10 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x10 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x10 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x10 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address18 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x10 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x10 0.--15. 1. "addrhi,MAC Address18 [47:32]"
line.long 0x14 "gmacgrp_mac_address18_low,Register 517 (MAC Address18 Low Register)"
hexmask.long 0x14 0.--31. 1. "addrlo,MAC Address18 [31:0]"
line.long 0x18 "gmacgrp_mac_address19_high,Register 518 (MAC Address19 High Register)"
bitfld.long 0x18 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x18 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x18 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x18 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x18 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x18 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x18 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x18 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address19 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x18 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x18 0.--15. 1. "addrhi,MAC Address19 [47:32]"
line.long 0x1C "gmacgrp_mac_address19_low,Register 519 (MAC Address19 Low Register)"
hexmask.long 0x1C 0.--31. 1. "addrlo,MAC Address19 [31:0]"
line.long 0x20 "gmacgrp_mac_address20_high,Register 520 (MAC Address20 High Register)"
bitfld.long 0x20 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x20 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x20 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x20 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x20 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x20 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x20 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x20 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address20 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x20 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x20 0.--15. 1. "addrhi,MAC Address20 [47:32]"
line.long 0x24 "gmacgrp_mac_address20_low,Register 521 (MAC Address20 Low Register)"
hexmask.long 0x24 0.--31. 1. "addrlo,MAC Address20 [31:0]"
line.long 0x28 "gmacgrp_mac_address21_high,Register 522 (MAC Address21 High Register)"
bitfld.long 0x28 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x28 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x28 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x28 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x28 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x28 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x28 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x28 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address21 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x28 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x28 0.--15. 1. "addrhi,MAC Address21 [47:32]"
line.long 0x2C "gmacgrp_mac_address21_low,Register 523 (MAC Address21 Low Register)"
hexmask.long 0x2C 0.--31. 1. "addrlo,MAC Address21 [31:0]"
line.long 0x30 "gmacgrp_mac_address22_high,Register 524 (MAC Address22 High Register)"
bitfld.long 0x30 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x30 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x30 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x30 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x30 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x30 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x30 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x30 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address22 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x30 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x30 0.--15. 1. "addrhi,MAC Address22 [47:32]"
line.long 0x34 "gmacgrp_mac_address22_low,Register 525 (MAC Address22 Low Register)"
hexmask.long 0x34 0.--31. 1. "addrlo,MAC Address22 [31:0]"
line.long 0x38 "gmacgrp_mac_address23_high,Register 526 (MAC Address23 High Register"
bitfld.long 0x38 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x38 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x38 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x38 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x38 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x38 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x38 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x38 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address23 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x38 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x38 0.--15. 1. "addrhi,MAC Address23 [47:32]"
line.long 0x3C "gmacgrp_mac_address23_low,Register 527 (MAC Address23 Low Register)"
hexmask.long 0x3C 0.--31. 1. "addrlo,MAC Address23 [31:0]"
line.long 0x40 "gmacgrp_mac_address24_high,Register 528 (MAC Address24 High Register)"
bitfld.long 0x40 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x40 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x40 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x40 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x40 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x40 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x40 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x40 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address24 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x40 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x40 0.--15. 1. "addrhi,MAC Address1 [47:32]"
line.long 0x44 "gmacgrp_mac_address24_low,Register 529 (MAC Address24 Low Register)"
hexmask.long 0x44 0.--31. 1. "addrlo,MAC Address24 [31:0]"
line.long 0x48 "gmacgrp_mac_address25_high,Register 530 (MAC Address25 High Register)"
bitfld.long 0x48 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x48 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x48 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x48 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x48 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x48 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x48 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x48 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address25 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x48 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x48 0.--15. 1. "addrhi,MAC Address25 [47:32]"
line.long 0x4C "gmacgrp_mac_address25_low,Register 531 (MAC Address25 Low Register)"
hexmask.long 0x4C 0.--31. 1. "addrlo,MAC Address25 [31:0]"
line.long 0x50 "gmacgrp_mac_address26_high,Register 532 (MAC Address26 High Register)"
bitfld.long 0x50 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x50 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x50 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x50 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x50 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x50 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x50 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x50 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address26 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x50 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x50 0.--15. 1. "addrhi,MAC Address26 [47:32]"
line.long 0x54 "gmacgrp_mac_address26_low,Register 533 (MAC Address26 Low Register)"
hexmask.long 0x54 0.--31. 1. "addrlo,MAC Address26 [31:0]"
line.long 0x58 "gmacgrp_mac_address27_high,Register 534 (MAC Address27 High Register)"
bitfld.long 0x58 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x58 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x58 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x58 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x58 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x58 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x58 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x58 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address27 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x58 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x58 0.--15. 1. "addrhi,MAC Address27 [47:32]"
line.long 0x5C "gmacgrp_mac_address27_low,Register 535 (MAC Address27 Low Register)"
hexmask.long 0x5C 0.--31. 1. "addrlo,MAC Address27 [31:0]"
line.long 0x60 "gmacgrp_mac_address28_high,Register 536 (MAC Address28 High Register)"
bitfld.long 0x60 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x60 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x60 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x60 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x60 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x60 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x60 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x60 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address28 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x60 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x60 0.--15. 1. "addrhi,MAC Address28 [47:32]"
line.long 0x64 "gmacgrp_mac_address28_low,Register 537 (MAC Address28 Low Register)"
hexmask.long 0x64 0.--31. 1. "addrlo,MAC Address28 [31:0]"
line.long 0x68 "gmacgrp_mac_address29_high,Register 538 (MAC Address29 High Register)"
bitfld.long 0x68 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x68 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x68 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x68 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x68 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x68 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x68 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x68 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address29 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x68 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x68 0.--15. 1. "addrhi,MAC Address29 [47:32]"
line.long 0x6C "gmacgrp_mac_address29_low,Register 539 (MAC Address29 Low Register)"
hexmask.long 0x6C 0.--31. 1. "addrlo,MAC Address29 [31:0]"
line.long 0x70 "gmacgrp_mac_address30_high,Register 540 (MAC Address30 High Register)"
bitfld.long 0x70 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x70 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x70 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x70 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x70 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x70 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x70 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x70 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address30 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x70 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x70 0.--15. 1. "addrhi,MAC Address30 [47:32]"
line.long 0x74 "gmacgrp_mac_address30_low,Register 541 (MAC Address30 Low Register)"
hexmask.long 0x74 0.--31. 1. "addrlo,MAC Address30 [31:0]"
line.long 0x78 "gmacgrp_mac_address31_high,Register 542 (MAC Address31 High Register)"
bitfld.long 0x78 31. "ae,Address Enable" "0,1"
newline
bitfld.long 0x78 30. "sa,Source Address" "0,1"
newline
bitfld.long 0x78 29. "mbc_5,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x78 28. "mbc_4,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x78 27. "mbc_3,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x78 26. "mbc_2,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x78 25. "mbc_1,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
bitfld.long 0x78 24. "mbc_0,This array of bits are mask control bits for comparison of each of the MAC Address bytes. When masked  the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address31 high and low registers. Each bit controls.." "0,1"
newline
hexmask.long.byte 0x78 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.word 0x78 0.--15. 1. "addrhi,MAC Address31 [47:32]"
line.long 0x7C "gmacgrp_mac_address31_low,Register 543 (MAC Address31 Low Register)"
hexmask.long 0x7C 0.--31. 1. "addrlo,MAC Address31 [31:0]"
line.long 0x80 "gmacgrp_mac_address32_high,Register 544 (MAC Address32 High Register)"
bitfld.long 0x80 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x80 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x80 0.--15. 1. "addrhi,MAC Address32 [47:32]"
line.long 0x84 "gmacgrp_mac_address32_low,Register 545 (MAC Address32 Low Register)"
hexmask.long 0x84 0.--31. 1. "addrlo,MAC Address32 [31:0]"
line.long 0x88 "gmacgrp_mac_address33_high,Register 546 (MAC Address33 High Register)"
bitfld.long 0x88 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x88 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x88 0.--15. 1. "addrhi,MAC Address33 [47:32]"
line.long 0x8C "gmacgrp_mac_address33_low,Register 547 (MAC Address33 Low Register)"
hexmask.long 0x8C 0.--31. 1. "addrlo,MAC Address33 [31:0]"
line.long 0x90 "gmacgrp_mac_address34_high,Register 548 (MAC Address34 High Register)"
bitfld.long 0x90 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x90 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x90 0.--15. 1. "addrhi,MAC Address34 [47:32]"
line.long 0x94 "gmacgrp_mac_address34_low,Register 549 (MAC Address34 Low Register)"
hexmask.long 0x94 0.--31. 1. "addrlo,MAC Address34 [31:0]"
line.long 0x98 "gmacgrp_mac_address35_high,Register 550 (MAC Address35 High Register)"
bitfld.long 0x98 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x98 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x98 0.--15. 1. "addrhi,MAC Address35 [47:32]"
line.long 0x9C "gmacgrp_mac_address35_low,Register 551 (MAC Address35 Low Register)"
hexmask.long 0x9C 0.--31. 1. "addrlo,MAC Address35 [31:0]"
line.long 0xA0 "gmacgrp_mac_address36_high,Register 552 (MAC Address36 High Register)"
bitfld.long 0xA0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xA0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xA0 0.--15. 1. "addrhi,MAC Address36 [47:32]"
line.long 0xA4 "gmacgrp_mac_address36_low,Register 553 (MAC Address36 Low Register)"
hexmask.long 0xA4 0.--31. 1. "addrlo,MAC Address36 [31:0]"
line.long 0xA8 "gmacgrp_mac_address37_high,Register 554 (MAC Address37 High Register)"
bitfld.long 0xA8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xA8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xA8 0.--15. 1. "addrhi,MAC Address37 [47:32]"
line.long 0xAC "gmacgrp_mac_address37_low,Register 555 (MAC Address37 Low Register)"
hexmask.long 0xAC 0.--31. 1. "addrlo,MAC Address37 [31:0]"
line.long 0xB0 "gmacgrp_mac_address38_high,Register 556 (MAC Address38 High Register)"
bitfld.long 0xB0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xB0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xB0 0.--15. 1. "addrhi,MAC Address38 [47:32]"
line.long 0xB4 "gmacgrp_mac_address38_low,Register 557 (MAC Address38 Low Register)"
hexmask.long 0xB4 0.--31. 1. "addrlo,MAC Address38 [31:0]"
line.long 0xB8 "gmacgrp_mac_address39_high,Register 558 (MAC Address39 High Register)"
bitfld.long 0xB8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xB8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xB8 0.--15. 1. "addrhi,MAC Address39 [47:32]"
line.long 0xBC "gmacgrp_mac_address39_low,Register 559 (MAC Address39 Low Register)"
hexmask.long 0xBC 0.--31. 1. "addrlo,MAC Address39 [31:0]"
line.long 0xC0 "gmacgrp_mac_address40_high,Register 560 (MAC Address40 High Register)"
bitfld.long 0xC0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xC0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xC0 0.--15. 1. "addrhi,MAC Address40 [47:32]"
line.long 0xC4 "gmacgrp_mac_address40_low,Register 561 (MAC Address40 Low Register)"
hexmask.long 0xC4 0.--31. 1. "addrlo,MAC Address40 [31:0]"
line.long 0xC8 "gmacgrp_mac_address41_high,Register 562 (MAC Address41 High Register)"
bitfld.long 0xC8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xC8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xC8 0.--15. 1. "addrhi,MAC Address41 [47:32]"
line.long 0xCC "gmacgrp_mac_address41_low,Register 563 (MAC Address41 Low Register)"
hexmask.long 0xCC 0.--31. 1. "addrlo,MAC Address41 [31:0]"
line.long 0xD0 "gmacgrp_mac_address42_high,Register 564 (MAC Address42 High Register)"
bitfld.long 0xD0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xD0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xD0 0.--15. 1. "addrhi,MAC Address42 [47:32]"
line.long 0xD4 "gmacgrp_mac_address42_low,Register 565 (MAC Address42 Low Register)"
hexmask.long 0xD4 0.--31. 1. "addrlo,MAC Address42 [31:0]"
line.long 0xD8 "gmacgrp_mac_address43_high,Register 566 (MAC Address43 High Register)"
bitfld.long 0xD8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xD8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xD8 0.--15. 1. "addrhi,MAC Address43 [47:32]"
line.long 0xDC "gmacgrp_mac_address43_low,Register 567 (MAC Address43 Low Register)"
hexmask.long 0xDC 0.--31. 1. "addrlo,MAC Address43 [31:0]"
line.long 0xE0 "gmacgrp_mac_address44_high,Register 568 (MAC Address44 High Register)"
bitfld.long 0xE0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xE0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xE0 0.--15. 1. "addrhi,MAC Address44 [47:32]"
line.long 0xE4 "gmacgrp_mac_address44_low,Register 569 (MAC Address44 Low Register)"
hexmask.long 0xE4 0.--31. 1. "addrlo,MAC Address44 [31:0]"
line.long 0xE8 "gmacgrp_mac_address45_high,Register 570 (MAC Address45 High Register)"
bitfld.long 0xE8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xE8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xE8 0.--15. 1. "addrhi,MAC Address45 [47:32]"
line.long 0xEC "gmacgrp_mac_address45_low,Register 571 (MAC Address45 Low Register)"
hexmask.long 0xEC 0.--31. 1. "addrlo,MAC Address45 [31:0]"
line.long 0xF0 "gmacgrp_mac_address46_high,Register 572 (MAC Address46 High Register)"
bitfld.long 0xF0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xF0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xF0 0.--15. 1. "addrhi,MAC Address46 [47:32]"
line.long 0xF4 "gmacgrp_mac_address46_low,Register 573 (MAC Address46 Low Register)"
hexmask.long 0xF4 0.--31. 1. "addrlo,MAC Address46 [31:0]"
line.long 0xF8 "gmacgrp_mac_address47_high,Register 574 (MAC Address47 High Register)"
bitfld.long 0xF8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0xF8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0xF8 0.--15. 1. "addrhi,MAC Address47 [47:32]"
line.long 0xFC "gmacgrp_mac_address47_low,Register 575 (MAC Address47 Low Register)"
hexmask.long 0xFC 0.--31. 1. "addrlo,MAC Address47 [31:0]"
line.long 0x100 "gmacgrp_mac_address48_high,Register 576 (MAC Address48 High Register)"
bitfld.long 0x100 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x100 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x100 0.--15. 1. "addrhi,MAC Address48 [47:32]"
line.long 0x104 "gmacgrp_mac_address48_low,Register 577 (MAC Address48 Low Register)"
hexmask.long 0x104 0.--31. 1. "addrlo,MAC Address48 [31:0]"
line.long 0x108 "gmacgrp_mac_address49_high,Register 578 (MAC Address49 High Register)"
bitfld.long 0x108 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x108 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x108 0.--15. 1. "addrhi,MAC Address49 [47:32]"
line.long 0x10C "gmacgrp_mac_address49_low,Register 579 (MAC Address49 Low Register)"
hexmask.long 0x10C 0.--31. 1. "addrlo,MAC Address49 [31:0]"
line.long 0x110 "gmacgrp_mac_address50_high,Register 580 (MAC Address50 High Register)"
bitfld.long 0x110 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x110 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x110 0.--15. 1. "addrhi,MAC Address50 [47:32]"
line.long 0x114 "gmacgrp_mac_address50_low,Register 581 (MAC Address50 Low Register)"
hexmask.long 0x114 0.--31. 1. "addrlo,MAC Address50 [31:0]"
line.long 0x118 "gmacgrp_mac_address51_high,Register 582 (MAC Address51 High Register)"
bitfld.long 0x118 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x118 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x118 0.--15. 1. "addrhi,MAC Address51 [47:32]"
line.long 0x11C "gmacgrp_mac_address51_low,Register 583 (MAC Address51 Low Register)"
hexmask.long 0x11C 0.--31. 1. "addrlo,MAC Address51 [31:0]"
line.long 0x120 "gmacgrp_mac_address52_high,Register 584 (MAC Address52 High Register)"
bitfld.long 0x120 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x120 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x120 0.--15. 1. "addrhi,MAC Address52 [47:32]"
line.long 0x124 "gmacgrp_mac_address52_low,Register 585 (MAC Address52 Low Register)"
hexmask.long 0x124 0.--31. 1. "addrlo,MAC Address52 [31:0]"
line.long 0x128 "gmacgrp_mac_address53_high,Register 586 (MAC Address53 High Register)"
bitfld.long 0x128 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x128 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x128 0.--15. 1. "addrhi,MAC Address53 [47:32]"
line.long 0x12C "gmacgrp_mac_address53_low,Register 587 (MAC Address53 Low Register)"
hexmask.long 0x12C 0.--31. 1. "addrlo,MAC Address53 [31:0]"
line.long 0x130 "gmacgrp_mac_address54_high,Register 588 (MAC Address54 High Register)"
bitfld.long 0x130 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x130 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x130 0.--15. 1. "addrhi,MAC Address54 [47:32]"
line.long 0x134 "gmacgrp_mac_address54_low,Register 589 (MAC Address54 Low Register)"
hexmask.long 0x134 0.--31. 1. "addrlo,MAC Address54 [31:0]"
line.long 0x138 "gmacgrp_mac_address55_high,Register 590 (MAC Address55 High Register)"
bitfld.long 0x138 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x138 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x138 0.--15. 1. "addrhi,MAC Address55 [47:32]"
line.long 0x13C "gmacgrp_mac_address55_low,Register 591 (MAC Address55 Low Register)"
hexmask.long 0x13C 0.--31. 1. "addrlo,MAC Address55 [31:0]"
line.long 0x140 "gmacgrp_mac_address56_high,Register 592 (MAC Address56 High Register)"
bitfld.long 0x140 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x140 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x140 0.--15. 1. "addrhi,MAC Address56 [47:32]"
line.long 0x144 "gmacgrp_mac_address56_low,Register 593 (MAC Address56 Low Register)"
hexmask.long 0x144 0.--31. 1. "addrlo,MAC Address56 [31:0]"
line.long 0x148 "gmacgrp_mac_address57_high,Register 594 (MAC Address57 High Register)"
bitfld.long 0x148 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x148 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x148 0.--15. 1. "addrhi,MAC Address57 [47:32]"
line.long 0x14C "gmacgrp_mac_address57_low,Register 595 (MAC Address57 Low Register)"
hexmask.long 0x14C 0.--31. 1. "addrlo,MAC Address57 [31:0]"
line.long 0x150 "gmacgrp_mac_address58_high,Register 596 (MAC Address58 High Register)"
bitfld.long 0x150 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x150 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x150 0.--15. 1. "addrhi,MAC Address58 [47:32]"
line.long 0x154 "gmacgrp_mac_address58_low,Register 597 (MAC Address58 Low Register)"
hexmask.long 0x154 0.--31. 1. "addrlo,MAC Address58 [31:0]"
line.long 0x158 "gmacgrp_mac_address59_high,Register 598 (MAC Address59 High Register)"
bitfld.long 0x158 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x158 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x158 0.--15. 1. "addrhi,MAC Address59 [47:32]"
line.long 0x15C "gmacgrp_mac_address59_low,Register 599 (MAC Address59 Low Register)"
hexmask.long 0x15C 0.--31. 1. "addrlo,MAC Address59 [31:0]"
line.long 0x160 "gmacgrp_mac_address60_high,Register 600 (MAC Address60 High Register)"
bitfld.long 0x160 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x160 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x160 0.--15. 1. "addrhi,MAC Address60 [47:32]"
line.long 0x164 "gmacgrp_mac_address60_low,Register 601 (MAC Address60 Low Register)"
hexmask.long 0x164 0.--31. 1. "addrlo,MAC Address60 [31:0]"
line.long 0x168 "gmacgrp_mac_address61_high,Register 602 (MAC Address61 High Register)"
bitfld.long 0x168 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x168 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x168 0.--15. 1. "addrhi,MAC Address61 [47:32]"
line.long 0x16C "gmacgrp_mac_address61_low,Register 603 (MAC Address61 Low Register)"
hexmask.long 0x16C 0.--31. 1. "addrlo,MAC Address61 [31:0]"
line.long 0x170 "gmacgrp_mac_address62_high,Register 604 (MAC Address62 High Register)"
bitfld.long 0x170 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x170 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x170 0.--15. 1. "addrhi,MAC Address62 [47:32]"
line.long 0x174 "gmacgrp_mac_address62_low,Register 605 (MAC Address62 Low Register)"
hexmask.long 0x174 0.--31. 1. "addrlo,MAC Address62 [31:0]"
line.long 0x178 "gmacgrp_mac_address63_high,Register 606 (MAC Address63 High Register)"
bitfld.long 0x178 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x178 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x178 0.--15. 1. "addrhi,MAC Address63 [47:32]"
line.long 0x17C "gmacgrp_mac_address63_low,Register 607 (MAC Address63 Low Register)"
hexmask.long 0x17C 0.--31. 1. "addrlo,MAC Address63 [31:0]"
line.long 0x180 "gmacgrp_mac_address64_high,Register 608 (MAC Address64 High Register)"
bitfld.long 0x180 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x180 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x180 0.--15. 1. "addrhi,MAC Address64 [47:32]"
line.long 0x184 "gmacgrp_mac_address64_low,Register 609 (MAC Address64 Low Register)"
hexmask.long 0x184 0.--31. 1. "addrlo,MAC Address64 [31:0]"
line.long 0x188 "gmacgrp_mac_address65_high,Register 610 (MAC Address65 High Register)"
bitfld.long 0x188 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x188 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x188 0.--15. 1. "addrhi,MAC Address65 [47:32]"
line.long 0x18C "gmacgrp_mac_address65_low,Register 611 (MAC Address65 Low Register)"
hexmask.long 0x18C 0.--31. 1. "addrlo,MAC Address65 [31:0]"
line.long 0x190 "gmacgrp_mac_address66_high,Register 612 (MAC Address66 High Register)"
bitfld.long 0x190 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x190 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x190 0.--15. 1. "addrhi,MAC Address66 [47:32]"
line.long 0x194 "gmacgrp_mac_address66_low,Register 613 (MAC Address66 Low Register)"
hexmask.long 0x194 0.--31. 1. "addrlo,MAC Address66 [31:0]"
line.long 0x198 "gmacgrp_mac_address67_high,Register 614 (MAC Address67 High Register)"
bitfld.long 0x198 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x198 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x198 0.--15. 1. "addrhi,MAC Address67 [47:32]"
line.long 0x19C "gmacgrp_mac_address67_low,Register 615 (MAC Address67 Low Register)"
hexmask.long 0x19C 0.--31. 1. "addrlo,MAC Address67 [31:0]"
line.long 0x1A0 "gmacgrp_mac_address68_high,Register 616 (MAC Address68 High Register)"
bitfld.long 0x1A0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1A0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1A0 0.--15. 1. "addrhi,MAC Address68 [47:32]"
line.long 0x1A4 "gmacgrp_mac_address68_low,Register 617 (MAC Address68 Low Register)"
hexmask.long 0x1A4 0.--31. 1. "addrlo,MAC Address68 [31:0]"
line.long 0x1A8 "gmacgrp_mac_address69_high,Register 618 (MAC Address69 High Register)"
bitfld.long 0x1A8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1A8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1A8 0.--15. 1. "addrhi,MAC Address69 [47:32]"
line.long 0x1AC "gmacgrp_mac_address69_low,Register 619 (MAC Address69 Low Register)"
hexmask.long 0x1AC 0.--31. 1. "addrlo,MAC Address69 [31:0]"
line.long 0x1B0 "gmacgrp_mac_address70_high,Register 620 (MAC Address70 High Register)"
bitfld.long 0x1B0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1B0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1B0 0.--15. 1. "addrhi,MAC Address70 [47:32]"
line.long 0x1B4 "gmacgrp_mac_address70_low,Register 621 (MAC Address70 Low Register)"
hexmask.long 0x1B4 0.--31. 1. "addrlo,MAC Address70 [31:0]"
line.long 0x1B8 "gmacgrp_mac_address71_high,Register 622 (MAC Address71 High Register)"
bitfld.long 0x1B8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1B8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1B8 0.--15. 1. "addrhi,MAC Address71 [47:32]"
line.long 0x1BC "gmacgrp_mac_address71_low,Register 623 (MAC Address71 Low Register)"
hexmask.long 0x1BC 0.--31. 1. "addrlo,MAC Address71 [31:0]"
line.long 0x1C0 "gmacgrp_mac_address72_high,Register 624 (MAC Address72 High Register)"
bitfld.long 0x1C0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1C0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1C0 0.--15. 1. "addrhi,MAC Address72 [47:32]"
line.long 0x1C4 "gmacgrp_mac_address72_low,Register 625 (MAC Address72 Low Register)"
hexmask.long 0x1C4 0.--31. 1. "addrlo,MAC Address72 [31:0]"
line.long 0x1C8 "gmacgrp_mac_address73_high,Register 626 (MAC Address73 High Register)"
bitfld.long 0x1C8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1C8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1C8 0.--15. 1. "addrhi,MAC Address73 [47:32]"
line.long 0x1CC "gmacgrp_mac_address73_low,Register 627 (MAC Address73 Low Register)"
hexmask.long 0x1CC 0.--31. 1. "addrlo,MAC Address73 [31:0]"
line.long 0x1D0 "gmacgrp_mac_address74_high,Register 628 (MAC Address74 High Register)"
bitfld.long 0x1D0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1D0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1D0 0.--15. 1. "addrhi,MAC Address74 [47:32]"
line.long 0x1D4 "gmacgrp_mac_address74_low,Register 629 (MAC Address74 Low Register)"
hexmask.long 0x1D4 0.--31. 1. "addrlo,MAC Address74 [31:0]"
line.long 0x1D8 "gmacgrp_mac_address75_high,Register 630 (MAC Address75 High Register)"
bitfld.long 0x1D8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1D8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1D8 0.--15. 1. "addrhi,MAC Address75 [47:32]"
line.long 0x1DC "gmacgrp_mac_address75_low,Register 631 (MAC Address75 Low Register)"
hexmask.long 0x1DC 0.--31. 1. "addrlo,MAC Address75 [31:0]"
line.long 0x1E0 "gmacgrp_mac_address76_high,Register 632 (MAC Address76 High Register)"
bitfld.long 0x1E0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1E0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1E0 0.--15. 1. "addrhi,MAC Address76 [47:32]"
line.long 0x1E4 "gmacgrp_mac_address76_low,Register 633 (MAC Address76 Low Register)"
hexmask.long 0x1E4 0.--31. 1. "addrlo,MAC Address76 [31:0]"
line.long 0x1E8 "gmacgrp_mac_address77_high,Register 634 (MAC Address77 High Register)"
bitfld.long 0x1E8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1E8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1E8 0.--15. 1. "addrhi,MAC Address77 [47:32]"
line.long 0x1EC "gmacgrp_mac_address77_low,Register 635 (MAC Address77 Low Register)"
hexmask.long 0x1EC 0.--31. 1. "addrlo,MAC Address77 [31:0]"
line.long 0x1F0 "gmacgrp_mac_address78_high,Register 636 (MAC Address78 High Register)"
bitfld.long 0x1F0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1F0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1F0 0.--15. 1. "addrhi,MAC Address78 [47:32]"
line.long 0x1F4 "gmacgrp_mac_address78_low,Register 637 (MAC Address78 Low Register)"
hexmask.long 0x1F4 0.--31. 1. "addrlo,MAC Address78 [31:0]"
line.long 0x1F8 "gmacgrp_mac_address79_high,Register 638 (MAC Address79 High Register)"
bitfld.long 0x1F8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x1F8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x1F8 0.--15. 1. "addrhi,MAC Address79 [47:32]"
line.long 0x1FC "gmacgrp_mac_address79_low,Register 639 (MAC Address79 Low Register)"
hexmask.long 0x1FC 0.--31. 1. "addrlo,MAC Address79 [31:0]"
line.long 0x200 "gmacgrp_mac_address80_high,Register 640 (MAC Address80 High Register)"
bitfld.long 0x200 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x200 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x200 0.--15. 1. "addrhi,MAC Address80 [47:32]"
line.long 0x204 "gmacgrp_mac_address80_low,Register 641 (MAC Address80 Low Register)"
hexmask.long 0x204 0.--31. 1. "addrlo,MAC Address80 [31:0]"
line.long 0x208 "gmacgrp_mac_address81_high,Register 642 (MAC Address81 High Register)"
bitfld.long 0x208 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x208 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x208 0.--15. 1. "addrhi,MAC Address81 [47:32]"
line.long 0x20C "gmacgrp_mac_address81_low,Register 643 (MAC Address81 Low Register)"
hexmask.long 0x20C 0.--31. 1. "addrlo,MAC Address81 [31:0]"
line.long 0x210 "gmacgrp_mac_address82_high,Register 644 (MAC Address82 High Register)"
bitfld.long 0x210 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x210 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x210 0.--15. 1. "addrhi,MAC Address82 [47:32]"
line.long 0x214 "gmacgrp_mac_address82_low,Register 645 (MAC Address82 Low Register)"
hexmask.long 0x214 0.--31. 1. "addrlo,MAC Address82 [31:0]"
line.long 0x218 "gmacgrp_mac_address83_high,Register 646 (MAC Address83 High Register)"
bitfld.long 0x218 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x218 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x218 0.--15. 1. "addrhi,MAC Address83 [47:32]"
line.long 0x21C "gmacgrp_mac_address83_low,Register 647 (MAC Address83 Low Register)"
hexmask.long 0x21C 0.--31. 1. "addrlo,MAC Address83 [31:0]"
line.long 0x220 "gmacgrp_mac_address84_high,Register 648 (MAC Address84 High Register)"
bitfld.long 0x220 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x220 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x220 0.--15. 1. "addrhi,MAC Address84 [47:32]"
line.long 0x224 "gmacgrp_mac_address84_low,Register 649 (MAC Address84 Low Register)"
hexmask.long 0x224 0.--31. 1. "addrlo,MAC Address84 [31:0]"
line.long 0x228 "gmacgrp_mac_address85_high,Register 650 (MAC Address85 High Register)"
bitfld.long 0x228 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x228 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x228 0.--15. 1. "addrhi,MAC Address85 [47:32]"
line.long 0x22C "gmacgrp_mac_address85_low,Register 651 (MAC Address85 Low Register)"
hexmask.long 0x22C 0.--31. 1. "addrlo,MAC Address85 [31:0]"
line.long 0x230 "gmacgrp_mac_address86_high,Register 652 (MAC Address86 High Register)"
bitfld.long 0x230 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x230 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x230 0.--15. 1. "addrhi,MAC Address86 [47:32]"
line.long 0x234 "gmacgrp_mac_address86_low,Register 653 (MAC Address86 Low Register)"
hexmask.long 0x234 0.--31. 1. "addrlo,MAC Address86 [31:0]"
line.long 0x238 "gmacgrp_mac_address87_high,Register 654 (MAC Address87 High Register)"
bitfld.long 0x238 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x238 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x238 0.--15. 1. "addrhi,MAC Address87 [47:32]"
line.long 0x23C "gmacgrp_mac_address87_low,Register 655 (MAC Address87 Low Register)"
hexmask.long 0x23C 0.--31. 1. "addrlo,MAC Address87 [31:0]"
line.long 0x240 "gmacgrp_mac_address88_high,Register 656 (MAC Address88 High Register)"
bitfld.long 0x240 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x240 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x240 0.--15. 1. "addrhi,MAC Address88 [47:32]"
line.long 0x244 "gmacgrp_mac_address88_low,Register 657 (MAC Address88 Low Register)"
hexmask.long 0x244 0.--31. 1. "addrlo,MAC Address88 [31:0]"
line.long 0x248 "gmacgrp_mac_address89_high,Register 658 (MAC Address89 High Register)"
bitfld.long 0x248 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x248 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x248 0.--15. 1. "addrhi,MAC Address89 [47:32]"
line.long 0x24C "gmacgrp_mac_address89_low,Register 659 (MAC Address89 Low Register)"
hexmask.long 0x24C 0.--31. 1. "addrlo,MAC Address89 [31:0]"
line.long 0x250 "gmacgrp_mac_address90_high,Register 660 (MAC Address90 High Register)"
bitfld.long 0x250 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x250 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x250 0.--15. 1. "addrhi,MAC Address90 [47:32]"
line.long 0x254 "gmacgrp_mac_address90_low,Register 661 (MAC Address90 Low Register)"
hexmask.long 0x254 0.--31. 1. "addrlo,MAC Address90 [31:0]"
line.long 0x258 "gmacgrp_mac_address91_high,Register 662 (MAC Address91 High Register)"
bitfld.long 0x258 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x258 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x258 0.--15. 1. "addrhi,MAC Address91 [47:32]"
line.long 0x25C "gmacgrp_mac_address91_low,Register 663 (MAC Address91 Low Register)"
hexmask.long 0x25C 0.--31. 1. "addrlo,MAC Address91 [31:0]"
line.long 0x260 "gmacgrp_mac_address92_high,Register 664 (MAC Address92 High Register)"
bitfld.long 0x260 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x260 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x260 0.--15. 1. "addrhi,MAC Address92 [47:32]"
line.long 0x264 "gmacgrp_mac_address92_low,Register 665 (MAC Address92 Low Register)"
hexmask.long 0x264 0.--31. 1. "addrlo,MAC Address92 [31:0]"
line.long 0x268 "gmacgrp_mac_address93_high,Register 666 (MAC Address93 High Register)"
bitfld.long 0x268 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x268 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x268 0.--15. 1. "addrhi,MAC Address93 [47:32]"
line.long 0x26C "gmacgrp_mac_address93_low,Register 667 (MAC Address93 Low Register)"
hexmask.long 0x26C 0.--31. 1. "addrlo,MAC Address93 [31:0]"
line.long 0x270 "gmacgrp_mac_address94_high,Register 668 (MAC Address94 High Register)"
bitfld.long 0x270 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x270 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x270 0.--15. 1. "addrhi,MAC Address94 [47:32]"
line.long 0x274 "gmacgrp_mac_address94_low,Register 669 (MAC Address94 Low Register)"
hexmask.long 0x274 0.--31. 1. "addrlo,MAC Address94 [31:0]"
line.long 0x278 "gmacgrp_mac_address95_high,Register 670 (MAC Address95 High Register)"
bitfld.long 0x278 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x278 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x278 0.--15. 1. "addrhi,MAC Address95 [47:32]"
line.long 0x27C "gmacgrp_mac_address95_low,Register 671 (MAC Address95 Low Register)"
hexmask.long 0x27C 0.--31. 1. "addrlo,MAC Address95 [31:0]"
line.long 0x280 "gmacgrp_mac_address96_high,Register 672 (MAC Address96 High Register)"
bitfld.long 0x280 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x280 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x280 0.--15. 1. "addrhi,MAC Address96 [47:32]"
line.long 0x284 "gmacgrp_mac_address96_low,Register 673 (MAC Address96 Low Register)"
hexmask.long 0x284 0.--31. 1. "addrlo,MAC Address96 [31:0]"
line.long 0x288 "gmacgrp_mac_address97_high,Register 674 (MAC Address97 High Register)"
bitfld.long 0x288 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x288 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x288 0.--15. 1. "addrhi,MAC Address97 [47:32]"
line.long 0x28C "gmacgrp_mac_address97_low,Register 675 (MAC Address97 Low Register)"
hexmask.long 0x28C 0.--31. 1. "addrlo,MAC Address97 [31:0]"
line.long 0x290 "gmacgrp_mac_address98_high,Register 676 (MAC Address98 High Register)"
bitfld.long 0x290 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x290 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x290 0.--15. 1. "addrhi,MAC Address98 [47:32]"
line.long 0x294 "gmacgrp_mac_address98_low,Register 677 (MAC Address98 Low Register)"
hexmask.long 0x294 0.--31. 1. "addrlo,MAC Address98 [31:0]"
line.long 0x298 "gmacgrp_mac_address99_high,Register 678 (MAC Address99 High Register)"
bitfld.long 0x298 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x298 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x298 0.--15. 1. "addrhi,MAC Address99 [47:32]"
line.long 0x29C "gmacgrp_mac_address99_low,Register 679 (MAC Address99 Low Register)"
hexmask.long 0x29C 0.--31. 1. "addrlo,MAC Address99 [31:0]"
line.long 0x2A0 "gmacgrp_mac_address100_high,Register 680 (MAC Address100 High Register)"
bitfld.long 0x2A0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2A0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2A0 0.--15. 1. "addrhi,MAC Address100 [47:32]"
line.long 0x2A4 "gmacgrp_mac_address100_low,Register 681 (MAC Address100 Low Register)"
hexmask.long 0x2A4 0.--31. 1. "addrlo,MAC Address100 [31:0]"
line.long 0x2A8 "gmacgrp_mac_address101_high,Register 682 (MAC Address101 High Register)"
bitfld.long 0x2A8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2A8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2A8 0.--15. 1. "addrhi,MAC Address101 [47:32]"
line.long 0x2AC "gmacgrp_mac_address101_low,Register 683 (MAC Address101 Low Register)"
hexmask.long 0x2AC 0.--31. 1. "addrlo,MAC Address101 [31:0]"
line.long 0x2B0 "gmacgrp_mac_address102_high,Register 684 (MAC Address102 High Register)"
bitfld.long 0x2B0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2B0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2B0 0.--15. 1. "addrhi,MAC Address102 [47:32]"
line.long 0x2B4 "gmacgrp_mac_address102_low,Register 685 (MAC Address102 Low Register)"
hexmask.long 0x2B4 0.--31. 1. "addrlo,MAC Address102 [31:0]"
line.long 0x2B8 "gmacgrp_mac_address103_high,Register 686 (MAC Address103 High Register)"
bitfld.long 0x2B8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2B8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2B8 0.--15. 1. "addrhi,MAC Address103 [47:32]"
line.long 0x2BC "gmacgrp_mac_address103_low,Register 687 (MAC Address103 Low Register)"
hexmask.long 0x2BC 0.--31. 1. "addrlo,MAC Address103 [31:0]"
line.long 0x2C0 "gmacgrp_mac_address104_high,Register 688 (MAC Address104 High Register)"
bitfld.long 0x2C0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2C0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2C0 0.--15. 1. "addrhi,MAC Address104 [47:32]"
line.long 0x2C4 "gmacgrp_mac_address104_low,Register 689 (MAC Address104 Low Register)"
hexmask.long 0x2C4 0.--31. 1. "addrlo,MAC Address104 [31:0]"
line.long 0x2C8 "gmacgrp_mac_address105_high,Register 690 (MAC Address105 High Register)"
bitfld.long 0x2C8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2C8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2C8 0.--15. 1. "addrhi,MAC Address105 [47:32]"
line.long 0x2CC "gmacgrp_mac_address105_low,Register 691 (MAC Address105 Low Register)"
hexmask.long 0x2CC 0.--31. 1. "addrlo,MAC Address105 [31:0]"
line.long 0x2D0 "gmacgrp_mac_address106_high,Register 692 (MAC Address106 High Register)"
bitfld.long 0x2D0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2D0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2D0 0.--15. 1. "addrhi,MAC Address106 [47:32]"
line.long 0x2D4 "gmacgrp_mac_address106_low,Register 693 (MAC Address106 Low Register)"
hexmask.long 0x2D4 0.--31. 1. "addrlo,MAC Address106 [31:0]"
line.long 0x2D8 "gmacgrp_mac_address107_high,Register 694 (MAC Address107 High Register)"
bitfld.long 0x2D8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2D8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2D8 0.--15. 1. "addrhi,MAC Address107 [47:32]"
line.long 0x2DC "gmacgrp_mac_address107_low,Register 695 (MAC Address107 Low Register)"
hexmask.long 0x2DC 0.--31. 1. "addrlo,MAC Address107 [31:0]"
line.long 0x2E0 "gmacgrp_mac_address108_high,Register 696 (MAC Address108 High Register)"
bitfld.long 0x2E0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2E0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2E0 0.--15. 1. "addrhi,MAC Address108 [47:32]"
line.long 0x2E4 "gmacgrp_mac_address108_low,Register 697 (MAC Address108 Low Register)"
hexmask.long 0x2E4 0.--31. 1. "addrlo,MAC Address108 [31:0]"
line.long 0x2E8 "gmacgrp_mac_address109_high,Register 698 (MAC Address109 High Register)"
bitfld.long 0x2E8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2E8 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2E8 0.--15. 1. "addrhi,MAC Address109 [47:32]"
line.long 0x2EC "gmacgrp_mac_address109_low,Register 699 (MAC Address109 Low Register)"
hexmask.long 0x2EC 0.--31. 1. "addrlo,MAC Address109 [31:0]"
line.long 0x2F0 "gmacgrp_mac_address110_high,Register XXX (MAC AddressXX High Register)"
bitfld.long 0x2F0 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2F0 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x2F0 0.--15. 1. "addrhi,MAC Address110 [47:32]"
line.long 0x2F4 "gmacgrp_mac_address110_low,Register 700 (MAC Address110 Low Register)"
hexmask.long 0x2F4 0.--31. 1. "addrlo,MAC Address110 [31:0]"
line.long 0x2F8 "gmacgrp_mac_address111_high,Register 701 (MAC Address111 High Register)"
bitfld.long 0x2F8 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x2F8 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x2F8 0.--15. 1. "addrhi,MAC Address111 [47:32]"
line.long 0x2FC "gmacgrp_mac_address111_low,Register 702 (MAC Address111 Low Register)"
hexmask.long 0x2FC 0.--31. 1. "addrlo,MAC Address111 [31:0]"
line.long 0x300 "gmacgrp_mac_address112_high,Register 703 (MAC Address112 High Register)"
bitfld.long 0x300 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x300 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x300 0.--15. 1. "addrhi,MAC Address112 [47:32]"
line.long 0x304 "gmacgrp_mac_address112_low,Register 704 (MAC Address112 Low Register)"
hexmask.long 0x304 0.--31. 1. "addrlo,MAC Address112 [31:0]"
line.long 0x308 "gmacgrp_mac_address113_high,Register 705 (MAC Address113 High Register)"
bitfld.long 0x308 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x308 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x308 0.--15. 1. "addrhi,MAC Address113 [47:32]"
line.long 0x30C "gmacgrp_mac_address113_low,Register 706 (MAC Address113 Low Register)"
hexmask.long 0x30C 0.--31. 1. "addrlo,MAC Address113 [31:0]"
line.long 0x310 "gmacgrp_mac_address114_high,Register 707 (MAC Address114 High Register)"
bitfld.long 0x310 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x310 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x310 0.--15. 1. "addrhi,MAC Address114 [47:32]"
line.long 0x314 "gmacgrp_mac_address114_low,Register 708 (MAC Address114 Low Register)"
hexmask.long 0x314 0.--31. 1. "addrlo,MAC Address114 [31:0]"
line.long 0x318 "gmacgrp_mac_address115_high,Register 709 (MAC Address115 High Register)"
bitfld.long 0x318 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x318 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x318 0.--15. 1. "addrhi,MAC Address115 [47:32]"
line.long 0x31C "gmacgrp_mac_address115_low,Register 710 (MAC Address115 Low Register)"
hexmask.long 0x31C 0.--31. 1. "addrlo,MAC Address115 [31:0]"
line.long 0x320 "gmacgrp_mac_address116_high,Register 711 (MAC Address116 High Register)"
bitfld.long 0x320 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x320 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x320 0.--15. 1. "addrhi,MAC Address116 [47:32]"
line.long 0x324 "gmacgrp_mac_address116_low,Register 712 (MAC Address116 Low Register)"
hexmask.long 0x324 0.--31. 1. "addrlo,MAC Address116 [31:0]"
line.long 0x328 "gmacgrp_mac_address117_high,Register 713 (MAC Address117 High Register)"
bitfld.long 0x328 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x328 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x328 0.--15. 1. "addrhi,MAC Address117 [47:32]"
line.long 0x32C "gmacgrp_mac_address117_low,Register 714 (MAC Address117 Low Register)"
hexmask.long 0x32C 0.--31. 1. "addrlo,MAC Address117 [31:0]"
line.long 0x330 "gmacgrp_mac_address118_high,Register 715 (MAC Address118 High Register)"
bitfld.long 0x330 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x330 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x330 0.--15. 1. "addrhi,MAC Address118 [47:32]"
line.long 0x334 "gmacgrp_mac_address118_low,Register 716 (MAC Address118 Low Register)"
hexmask.long 0x334 0.--31. 1. "addrlo,MAC Address118 [31:0]"
line.long 0x338 "gmacgrp_mac_address119_high,Register 717 (MAC Address119 High Register)"
bitfld.long 0x338 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x338 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x338 0.--15. 1. "addrhi,MAC Address119 [47:32]"
line.long 0x33C "gmacgrp_mac_address119_low,Register 718 (MAC Address119 Low Register)"
hexmask.long 0x33C 0.--31. 1. "addrlo,MAC Address119 [31:0]"
line.long 0x340 "gmacgrp_mac_address120_high,Register 719 (MAC Address120 High Register)"
bitfld.long 0x340 31. "ae,Address Enable" "0,1"
newline
hexmask.long.word 0x340 16.--30. 1. "reserved_30_16,Reserved"
newline
hexmask.long.word 0x340 0.--15. 1. "addrhi,MAC Address120 [47:32]"
line.long 0x344 "gmacgrp_mac_address120_low,Register 720 (MAC Address120 Low Register)"
hexmask.long 0x344 0.--31. 1. "addrlo,MAC Address120 [31:0]"
line.long 0x348 "gmacgrp_mac_address121_high,Register 721 (MAC Address121 High Register)"
bitfld.long 0x348 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x348 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x348 0.--15. 1. "addrhi,MAC Address121 [47:32]"
line.long 0x34C "gmacgrp_mac_address121_low,Register 722 (MAC Address121 Low Register)"
hexmask.long 0x34C 0.--31. 1. "addrlo,MAC Address121 [31:0]"
line.long 0x350 "gmacgrp_mac_address122_high,Register 723 (MAC Address122 High Register)"
bitfld.long 0x350 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x350 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x350 0.--15. 1. "addrhi,MAC Address122 [47:32]"
line.long 0x354 "gmacgrp_mac_address122_low,Register 724 (MAC Address122 Low Register)"
hexmask.long 0x354 0.--31. 1. "addrlo,MAC Address122 [31:0]"
line.long 0x358 "gmacgrp_mac_address123_high,Register 725 (MAC Address123 High Register)"
bitfld.long 0x358 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x358 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x358 0.--15. 1. "addrhi,MAC Address123 [47:32]"
line.long 0x35C "gmacgrp_mac_address123_low,Register 726 (MAC AddressXX 123 Register)"
hexmask.long 0x35C 0.--31. 1. "addrlo,MAC Address123 [31:0]"
line.long 0x360 "gmacgrp_mac_address124_high,Register 727 (MAC Address124 High Register)"
bitfld.long 0x360 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x360 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x360 0.--15. 1. "addrhi,MAC Address124 [47:32]"
line.long 0x364 "gmacgrp_mac_address124_low,Register 728 (MAC Address124 Low Register)"
hexmask.long 0x364 0.--31. 1. "addrlo,MAC Address124 [31:0]"
line.long 0x368 "gmacgrp_mac_address125_high,Register 729 (MAC Address125 High Register)"
bitfld.long 0x368 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x368 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x368 0.--15. 1. "addrhi,MAC Address125 [47:32]"
line.long 0x36C "gmacgrp_mac_address125_low,Register 730 (MAC Address125 Low Register)"
hexmask.long 0x36C 0.--31. 1. "addrlo,MAC Address125 [31:0]"
line.long 0x370 "gmacgrp_mac_address126_high,Register 731 (MAC Address126 High Register)"
bitfld.long 0x370 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x370 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x370 0.--15. 1. "addrhi,MAC Address126 [47:32]"
line.long 0x374 "gmacgrp_mac_address126_low,Register 732 (MAC Address126 Low Register)"
hexmask.long 0x374 0.--31. 1. "addrlo,MAC Address126 [31:0]"
line.long 0x378 "gmacgrp_mac_address127_high,Register 733 (MAC Address127 High Register)"
bitfld.long 0x378 31. "ae,Address Enable" "0,1"
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hexmask.long.word 0x378 16.--30. 1. "reserved_30_16,Reserved"
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hexmask.long.word 0x378 0.--15. 1. "addrhi,MAC Address127 [47:32]"
line.long 0x37C "gmacgrp_mac_address127_low,Register 734 (MAC Address127 Low Register)"
hexmask.long 0x37C 0.--31. 1. "addrlo,MAC Address127 [31:0]"
group.long 0x1000++0x1F
line.long 0x0 "dmagrp_bus_mode,Register 0 (Bus Mode Register)"
bitfld.long 0x0 31. "rib,Rebuild INCRx Burst" "0,1"
newline
rbitfld.long 0x0 30. "reserved_30,Reserved" "0,1"
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bitfld.long 0x0 28.--29. "prwg,Channel Priority Weights" "0: The priority weight is 1,1: The priority weight is 2,?,?"
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bitfld.long 0x0 27. "txpr,Transmit Priority" "0,1"
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bitfld.long 0x0 26. "mb,Mixed Burst" "0,1"
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bitfld.long 0x0 25. "aal,Address Aligned Beats" "0,1"
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bitfld.long 0x0 24. "eightxpbl,PBLx8 Mode" "0,1"
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bitfld.long 0x0 23. "usp,Use Seperate PBL" "0,1"
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hexmask.long.byte 0x0 17.--22. 1. "rpbl,Rx DMA PBL"
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bitfld.long 0x0 16. "fb,Fixed Burst" "0,1"
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bitfld.long 0x0 14.--15. "pr,Priority Ratio" "0: The Priority Ratio is,1: The Priority Ratio is,2: 1,3: 1"
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hexmask.long.byte 0x0 8.--13. 1. "pbl,Programmable Burst Length"
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bitfld.long 0x0 7. "atds,Alternate Descriptor Size" "0,1"
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hexmask.long.byte 0x0 2.--6. 1. "dsl,Descriptor Skip Length"
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bitfld.long 0x0 1. "da,DMA Arbitration Scheme" "0: Weighted round-robin with Rx:Tx or Tx:Rx,1: Fixed priority"
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bitfld.long 0x0 0. "swr,Software Reset" "0,1"
line.long 0x4 "dmagrp_transmit_poll_demand,Register 1 (Transmit Poll Demand Register)"
hexmask.long 0x4 0.--31. 1. "tpd,Transmit Poll Demand"
line.long 0x8 "dmagrp_receive_poll_demand,Register 2 (Receive Poll Demand Register)"
hexmask.long 0x8 0.--31. 1. "rpd,Receive Poll Demand"
line.long 0xC "dmagrp_receive_descriptor_list_address,Register 3 (Receive Descriptor List Address Register)"
hexmask.long 0xC 2.--31. 1. "rdesla_32bit,This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB bits (1:0) are ignored (32-bit wide bus) and internally taken as all-zero by the DMA. Therefore  these LSB bits are read-only (RO)."
line.long 0x10 "dmagrp_transmit_descriptor_list_address,Register 4 (Transmit Descriptor List Address Register)"
hexmask.long 0x10 2.--31. 1. "tdesla_32bit,This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (1:0) are ignored (32-bit wide bus) and are internally taken as all-zero by the DMA. Therefore  these LSB bits are read-only (RO)."
line.long 0x14 "dmagrp_status,Register 5 (Status Register)"
rbitfld.long 0x14 31. "reserved_31,Reserved" "0,1"
newline
rbitfld.long 0x14 30. "glpii,GMAC LPI Interrupt (for Channel 0)" "0,1"
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rbitfld.long 0x14 29. "tti,Timestamp Trigger Interrupt" "0,1"
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rbitfld.long 0x14 28. "gpi,GMAC PMT Interrupt" "0,1"
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rbitfld.long 0x14 27. "gmi,GMAC MMC Interrupt" "0,1"
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rbitfld.long 0x14 26. "gli,GMAC Line interface Interrupt" "0,1"
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rbitfld.long 0x14 23.--25. "eb,Error Bits" "0: Error during Rx DMA Descriptor Read Access,1: Error during Tx DMA Descriptor Read Access,?,?,?,?,?,?"
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rbitfld.long 0x14 20.--22. "ts,Transmit Process State" "0: Stopped,1: Running,2: Running,3: Running,4: TIME_STAMP write state,5: Reserved for future use,6: Suspended,7: Running"
newline
rbitfld.long 0x14 17.--19. "rs,Received Process State" "0: Stopped: Reset or Stop Receive Command issued,1: Running: Fetching Receive Transfer Descriptor,2: Reserved for future use,3: Running: Waiting for receive packet,4: Suspended: Receive Descriptor Unavailable,5: Running: Closing Receive Descriptor,6: TIME_STAMP write state,7: Running: Transferring the receive packet data.."
newline
bitfld.long 0x14 16. "nis,Normal Interrupt Summary" "0,1"
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bitfld.long 0x14 15. "ais,Abnormal Interrupt Summary" "0,1"
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bitfld.long 0x14 14. "eri,Early Receive Interrupt" "0,1"
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bitfld.long 0x14 13. "fbi,Fatal Bus Error Interrupt" "0,1"
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rbitfld.long 0x14 11.--12. "reserved_12_11,Reserved" "0,1,2,3"
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bitfld.long 0x14 10. "eti,Early Transmit Interrupt" "0,1"
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bitfld.long 0x14 9. "rwt,Receive Watchdog Timeout" "0,1"
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bitfld.long 0x14 8. "rps,Receive Process Stopped" "0,1"
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bitfld.long 0x14 7. "ru,Receive Buffer Unavailable" "0,1"
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bitfld.long 0x14 6. "ri,Receive Interrupt" "0,1"
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bitfld.long 0x14 5. "unf,Transmit Underflow" "0,1"
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bitfld.long 0x14 4. "ovf,Receive Overflow" "0,1"
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bitfld.long 0x14 3. "tjt,Transmit Jabber Timeout" "0,1"
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bitfld.long 0x14 2. "tu,Transmit Buffer Unavailable" "0,1"
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bitfld.long 0x14 1. "tps,Transmit Process Stopped" "0,1"
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bitfld.long 0x14 0. "ti,Transmit Interrupt" "0,1"
line.long 0x18 "dmagrp_operation_mode,Register 6 (Operation Mode Register)"
hexmask.long.byte 0x18 27.--31. 1. "reserved_31_27,Reserved"
newline
bitfld.long 0x18 26. "dt,Disable Dropping of TCP/IP Checksum Error Frames" "0,1"
newline
bitfld.long 0x18 25. "rsf,Receive Store and Forward" "0,1"
newline
bitfld.long 0x18 24. "dff,Disable Flushing of Received Frames" "0,1"
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rbitfld.long 0x18 23. "rfa_2,MSB of Threshold for Activating Flow Control" "0,1"
newline
rbitfld.long 0x18 22. "rfd_2,MSB of Threshold for Deactivating Flow Control" "0,1"
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bitfld.long 0x18 21. "tsf,Transmit Store and Forward" "0,1"
newline
bitfld.long 0x18 20. "ftf,Flush Transmit FIFO" "0,1"
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rbitfld.long 0x18 17.--19. "reserved_19_17,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 14.--16. "ttc,Transmit Threshold Control" "0: 64,1: 128,?,?,?,?,?,?"
newline
bitfld.long 0x18 13. "st,Start or Stop Transmission Command" "0,1"
newline
rbitfld.long 0x18 11.--12. "rfd,Threshold for Deactivating Flow Control (in half-duplex and full-duplex)" "0: Full minus 1 KB,1: Full minus 2 KB,?,?"
newline
rbitfld.long 0x18 9.--10. "rfa,Threshold for Activating Flow Control (in half-duplex and full-duplex)" "0: Full minus 1 KB,1: Full minus 2 KB,?,?"
newline
rbitfld.long 0x18 8. "efc,Reserved" "0,1"
newline
bitfld.long 0x18 7. "fef,Forward Error Frames" "0,1"
newline
bitfld.long 0x18 6. "fuf,Forward Undersized Good Frames" "0,1"
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bitfld.long 0x18 5. "dgf,Drop Giant Frames" "0,1"
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bitfld.long 0x18 3.--4. "rtc,Receive Threshold Control" "0: 64,1: 32,?,?"
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bitfld.long 0x18 2. "osf,Operate on Second Frame" "0,1"
newline
bitfld.long 0x18 1. "sr,Start or Stop Receive" "0,1"
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rbitfld.long 0x18 0. "reserved_0,Reserved" "0,1"
line.long 0x1C "dmagrp_interrupt_enable,Register 7 (Interrupt Enable Register)"
hexmask.long.word 0x1C 17.--31. 1. "reserved_31_17,Reserved"
newline
bitfld.long 0x1C 16. "nie,Normal Interrupt Summary Enable" "0,1"
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bitfld.long 0x1C 15. "aie,Abnormal Interrupt Summary Enable" "0,1"
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bitfld.long 0x1C 14. "ere,Early Receive Interrupt Enable" "0,1"
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bitfld.long 0x1C 13. "fbe,Fatal Bus Error Enable" "0,1"
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rbitfld.long 0x1C 11.--12. "reserved_12_11,Reserved" "0,1,2,3"
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bitfld.long 0x1C 10. "ete,Early Transmit Interrupt Enable" "0,1"
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bitfld.long 0x1C 9. "rwe,Receive Watchdog Timeout Enable" "0,1"
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bitfld.long 0x1C 8. "rse,Receive Stopped Enable" "0,1"
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bitfld.long 0x1C 7. "rue,Receive Buffer Unavailable Enable" "0,1"
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bitfld.long 0x1C 6. "rie,Receive Interrupt Enable" "0,1"
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bitfld.long 0x1C 5. "une,Underflow Interrupt Enable" "0,1"
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bitfld.long 0x1C 4. "ove,Overflow Interrupt Enable" "0,1"
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bitfld.long 0x1C 3. "tje,Transmit Jabber Timeout Enable" "0,1"
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bitfld.long 0x1C 2. "tue,Transmit Buffer Unavailable Enable" "0,1"
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bitfld.long 0x1C 1. "tse,Transmit Stopped Enable" "0,1"
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bitfld.long 0x1C 0. "tie,Transmit Interrupt Enable" "0,1"
rgroup.long 0x1020++0x3
line.long 0x0 "dmagrp_missed_frame_and_buffer_overflow_counter,Register 8 (Missed Frame and Buffer Overflow Counter Register)"
bitfld.long 0x0 29.--31. "reserved_31_29,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 28. "ovfcntovf,Overflow Bit for FIFO Overflow Counter" "0,1"
newline
hexmask.long.word 0x0 17.--27. 1. "ovffrmcnt,Overflow Frame Counter"
newline
bitfld.long 0x0 16. "miscntovf,Overflow Bit for Missed Frame Counter" "0,1"
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hexmask.long.word 0x0 0.--15. 1. "misfrmcnt,Missed Frame Counter"
group.long 0x1024++0x7
line.long 0x0 "dmagrp_receive_interrupt_watchdog_timer,Register 9 (Receive Interrupt Watchdog Timer Register)"
hexmask.long.tbyte 0x0 8.--31. 1. "reserved_31_8,Reserved"
newline
hexmask.long.byte 0x0 0.--7. 1. "riwt,RI Watchdog Timer Count"
line.long 0x4 "dmagrp_axi_bus_mode,The AXI Bus Mode Register controls the behavior of the AXI master. It is mainly used to control the burst splitting and the number of outstanding requests."
bitfld.long 0x4 31. "en_lpi,When set to 1  this bit enables the LPI mode supported by the AXI master and accepts the LPI request from the AXI System Clock controller." "0,1"
newline
bitfld.long 0x4 30. "lpi_xit_frm,When set to 1  this bit enables the GMAC-AXI to come out of the LPI mode only when the Magic Packet or Remote Wake Up Packet is received." "0,1"
newline
hexmask.long.byte 0x4 20.--23. 1. "wr_osr_lmt,AXI Maximum Write OutStanding Request Limit"
newline
hexmask.long.byte 0x4 16.--19. 1. "rd_osr_lmt,This value limits the maximum outstanding request on the AXI read interface."
newline
bitfld.long 0x4 13. "onekbbe,1 KB Boundary Crossing Enable for the GMAC-AXI Master" "0,1"
newline
rbitfld.long 0x4 12. "axi_aal,This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register)." "0,1"
newline
bitfld.long 0x4 3. "blen16,When this bit is set to 1 or UNDEFINED is set to 1  the GMAC-AXI is allowed to select a burst length of 16 on the AXI Master interface." "0,1"
newline
bitfld.long 0x4 2. "blen8,When this bit is set to 1  the GMAC-AXI is allowed to select a burst length of 8 on the AXI Master interface." "0,1"
newline
bitfld.long 0x4 1. "blen4,When this bit is set to 1  the GMAC-AXI is allowed to select a burst length of 4 on the AXI Master interface." "0,1"
newline
rbitfld.long 0x4 0. "undefined,This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register[16])." "0,1"
rgroup.long 0x102C++0x3
line.long 0x0 "dmagrp_ahb_or_axi_status,Register 11 (AHB or AXI Status Register)"
hexmask.long 0x0 2.--31. 1. "reserved_31_2,Reserved"
newline
bitfld.long 0x0 1. "axirdsts,AXI Master Read Channel Status" "0,1"
newline
bitfld.long 0x0 0. "axwhsts,AXI Master Write Channel or AHB Master Status" "0,1"
rgroup.long 0x1048++0x13
line.long 0x0 "dmagrp_current_host_transmit_descriptor,Register 18 (Current Host Transmit Descriptor Register)"
hexmask.long 0x0 0.--31. 1. "curtdesaptr,Host Transmit Descriptor Address Pointer"
line.long 0x4 "dmagrp_current_host_receive_descriptor,Register 19 (Current Host Receive Descriptor Register)"
hexmask.long 0x4 0.--31. 1. "currdesaptr,Host Receive Descriptor Address Pointer"
line.long 0x8 "dmagrp_current_host_transmit_buffer_address,Register 20 (Current Host Transmit Buffer Address Register)"
hexmask.long 0x8 0.--31. 1. "curtbufaptr,Host Transmit Buffer Address Pointer"
line.long 0xC "dmagrp_current_host_receive_buffer_address,Register 21 (Current Host Receive Buffer Address Register)"
hexmask.long 0xC 0.--31. 1. "currbufaptr,Host Receive Buffer Address Pointer"
line.long 0x10 "dmagrp_hw_feature,Register 22 (HW Feature Register)"
bitfld.long 0x10 31. "reserved_31,Reserved" "0,1"
newline
bitfld.long 0x10 28.--30. "actphyif,Active or Selected PHY interface" "0: GMII or MII,1: RGMII,?,?,?,?,?,?"
newline
bitfld.long 0x10 27. "SAVLANINS,Source Address or VLAN Insertion" "0,1"
newline
bitfld.long 0x10 26. "FLEXIPPSEN,Flexible Pulse-Per-Second Output" "0,1"
newline
bitfld.long 0x10 25. "INTTSEN,Timestamping with Internal System Time" "0,1"
newline
bitfld.long 0x10 24. "enhdessel,Alternate (Enhanced Descriptor)" "0,1"
newline
bitfld.long 0x10 22.--23. "txchcnt,Number of additional Tx channels" "0,1,2,3"
newline
bitfld.long 0x10 20.--21. "rxchcnt,Number of additional Rx channels" "0,1,2,3"
newline
bitfld.long 0x10 19. "rxfifosize,Rx FIFO > 2 048 Bytes" "0,1"
newline
bitfld.long 0x10 18. "rxtyp2coe,IP Checksum Offload (Type 2) in Rx" "0,1"
newline
bitfld.long 0x10 17. "rxtyp1coe,IP Checksum Offload (Type 1) in Rx" "0,1"
newline
bitfld.long 0x10 16. "txoesel,Checksum Offload in Tx" "0,1"
newline
bitfld.long 0x10 15. "avsel,AV Feature" "0,1"
newline
bitfld.long 0x10 14. "eeesel,Energy Efficient Ethernet" "0,1"
newline
bitfld.long 0x10 13. "tsver2sel,IEEE 1588-2008 Advanced Timestamp" "0,1"
newline
bitfld.long 0x10 12. "tsver1sel,Only IEEE 1588-2002 Timestamp" "0,1"
newline
bitfld.long 0x10 11. "mmcsel,RMON Module" "0,1"
newline
bitfld.long 0x10 10. "mgksel,PMT Magic Packet" "0,1"
newline
bitfld.long 0x10 9. "rwksel,PMT Remote Wakeup" "0,1"
newline
bitfld.long 0x10 8. "smasel,SMA (MDIO) Interface" "0,1"
newline
bitfld.long 0x10 7. "l3l4fltren,Layer 3 and Layer 4 Filter Feature" "0,1"
newline
bitfld.long 0x10 6. "pcssel,PCS registers (TBI  SGMII  or RTBI PHY interface)" "0,1"
newline
bitfld.long 0x10 5. "addmacadrsel,Multiple MAC Address Registers" "0,1"
newline
bitfld.long 0x10 4. "hashsel,HASH Filter" "0,1"
newline
bitfld.long 0x10 3. "exthashen,Expanded DA Hash Filter" "0,1"
newline
bitfld.long 0x10 2. "hdsel,Half-Duplex support" "0,1"
newline
bitfld.long 0x10 1. "gmiisel,1000 Mbps support" "0,1"
newline
bitfld.long 0x10 0. "miisel,10 or 100 Mbps support" "0,1"
tree.end
tree.end
tree "GIC (General Interrupt Controller)"
base ad:0xFFFC1000
group.long 0x0++0x3
line.long 0x0 "GICD_CTLR,Distributor Control Register"
hexmask.long 0x0 0.--31. 1. "GICD_CTLR,Distributor Control Register"
rgroup.long 0x4++0x7
line.long 0x0 "GICD_TYPER,Interrupt Controller Type Register"
hexmask.long 0x0 0.--31. 1. "GICD_TYPER,Interrupt Controller Type Register"
line.long 0x4 "GICD_IIDR,Distributor Implementer Identification Register"
hexmask.long 0x4 0.--31. 1. "GICD_IIDR,Distributor Implementer Identification Register"
group.long 0x80++0x3F
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Registers"
hexmask.long 0x0 0.--31. 1. "GICD_IGROUPR0,Interrupt Group Registers"
line.long 0x4 "GICD_IGROUPR1,Interrupt Group Registers"
hexmask.long 0x4 0.--31. 1. "GICD_IGROUPR1,Interrupt Group Registers"
line.long 0x8 "GICD_IGROUPR2,Interrupt Group Registers"
hexmask.long 0x8 0.--31. 1. "GICD_IGROUPR2,Interrupt Group Registers"
line.long 0xC "GICD_IGROUPR3,Interrupt Group Registers"
hexmask.long 0xC 0.--31. 1. "GICD_IGROUPR3,Interrupt Group Registers"
line.long 0x10 "GICD_IGROUPR4,Interrupt Group Registers"
hexmask.long 0x10 0.--31. 1. "GICD_IGROUPR4,Interrupt Group Registers"
line.long 0x14 "GICD_IGROUPR5,Interrupt Group Registers"
hexmask.long 0x14 0.--31. 1. "GICD_IGROUPR5,Interrupt Group Registers"
line.long 0x18 "GICD_IGROUPR6,Interrupt Group Registers"
hexmask.long 0x18 0.--31. 1. "GICD_IGROUPR6,Interrupt Group Registers"
line.long 0x1C "GICD_IGROUPR7,Interrupt Group Registers"
hexmask.long 0x1C 0.--31. 1. "GICD_IGROUPR7,Interrupt Group Registers"
line.long 0x20 "GICD_IGROUPR8,Interrupt Group Registers"
hexmask.long 0x20 0.--31. 1. "GICD_IGROUPR8,Interrupt Group Registers"
line.long 0x24 "GICD_IGROUPR9,Interrupt Group Registers"
hexmask.long 0x24 0.--31. 1. "GICD_IGROUPR9,Interrupt Group Registers"
line.long 0x28 "GICD_IGROUPR10,Interrupt Group Registers"
hexmask.long 0x28 0.--31. 1. "GICD_IGROUPR10,Interrupt Group Registers"
line.long 0x2C "GICD_IGROUPR11,Interrupt Group Registers"
hexmask.long 0x2C 0.--31. 1. "GICD_IGROUPR11,Interrupt Group Registers"
line.long 0x30 "GICD_IGROUPR12,Interrupt Group Registers"
hexmask.long 0x30 0.--31. 1. "GICD_IGROUPR12,Interrupt Group Registers"
line.long 0x34 "GICD_IGROUPR13,Interrupt Group Registers"
hexmask.long 0x34 0.--31. 1. "GICD_IGROUPR13,Interrupt Group Registers"
line.long 0x38 "GICD_IGROUPR14,Interrupt Group Registers"
hexmask.long 0x38 0.--31. 1. "GICD_IGROUPR14,Interrupt Group Registers"
line.long 0x3C "GICD_IGROUPR15,Interrupt Group Registers"
hexmask.long 0x3C 0.--31. 1. "GICD_IGROUPR15,Interrupt Group Registers"
group.long 0x100++0x3F
line.long 0x0 "GICD_ISENABLER0,Interrupt Set-Enable Registers"
hexmask.long 0x0 0.--31. 1. "GICD_ISENABLER0,Interrupt Set-Enable Registers"
line.long 0x4 "GICD_ISENABLER1,Interrupt Set-Enable Registers"
hexmask.long 0x4 0.--31. 1. "GICD_ISENABLER1,Interrupt Set-Enable Registers"
line.long 0x8 "GICD_ISENABLER2,Interrupt Set-Enable Registers"
hexmask.long 0x8 0.--31. 1. "GICD_ISENABLER2,Interrupt Set-Enable Registers"
line.long 0xC "GICD_ISENABLER3,Interrupt Set-Enable Registers"
hexmask.long 0xC 0.--31. 1. "GICD_ISENABLER3,Interrupt Set-Enable Registers"
line.long 0x10 "GICD_ISENABLER4,Interrupt Set-Enable Registers"
hexmask.long 0x10 0.--31. 1. "GICD_ISENABLER4,Interrupt Set-Enable Registers"
line.long 0x14 "GICD_ISENABLER5,Interrupt Set-Enable Registers"
hexmask.long 0x14 0.--31. 1. "GICD_ISENABLER5,Interrupt Set-Enable Registers"
line.long 0x18 "GICD_ISENABLER6,Interrupt Set-Enable Registers"
hexmask.long 0x18 0.--31. 1. "GICD_ISENABLER6,Interrupt Set-Enable Registers"
line.long 0x1C "GICD_ISENABLER7,Interrupt Set-Enable Registers"
hexmask.long 0x1C 0.--31. 1. "GICD_ISENABLER7,Interrupt Set-Enable Registers"
line.long 0x20 "GICD_ISENABLER8,Interrupt Set-Enable Registers"
hexmask.long 0x20 0.--31. 1. "GICD_ISENABLER8,Interrupt Set-Enable Registers"
line.long 0x24 "GICD_ISENABLER9,Interrupt Set-Enable Registers"
hexmask.long 0x24 0.--31. 1. "GICD_ISENABLER9,Interrupt Set-Enable Registers"
line.long 0x28 "GICD_ISENABLER10,Interrupt Set-Enable Registers"
hexmask.long 0x28 0.--31. 1. "GICD_ISENABLER10,Interrupt Set-Enable Registers"
line.long 0x2C "GICD_ISENABLER11,Interrupt Set-Enable Registers"
hexmask.long 0x2C 0.--31. 1. "GICD_ISENABLER11,Interrupt Set-Enable Registers"
line.long 0x30 "GICD_ISENABLER12,Interrupt Set-Enable Registers"
hexmask.long 0x30 0.--31. 1. "GICD_ISENABLER12,Interrupt Set-Enable Registers"
line.long 0x34 "GICD_ISENABLER13,Interrupt Set-Enable Registers"
hexmask.long 0x34 0.--31. 1. "GICD_ISENABLER13,Interrupt Set-Enable Registers"
line.long 0x38 "GICD_ISENABLER14,Interrupt Set-Enable Registers"
hexmask.long 0x38 0.--31. 1. "GICD_ISENABLER14,Interrupt Set-Enable Registers"
line.long 0x3C "GICD_ISENABLER15,Interrupt Set-Enable Registers"
hexmask.long 0x3C 0.--31. 1. "GICD_ISENABLER15,Interrupt Set-Enable Registers"
group.long 0x180++0x3F
line.long 0x0 "GICD_ICENABLER0,Interrupt Clear-Enable Registers"
hexmask.long 0x0 0.--31. 1. "GICD_ICENABLER0,Interrupt Clear-Enable Registers"
line.long 0x4 "GICD_ICENABLER1,Interrupt Clear-Enable Registers"
hexmask.long 0x4 0.--31. 1. "GICD_ICENABLER1,Interrupt Clear-Enable Registers"
line.long 0x8 "GICD_ICENABLER2,Interrupt Clear-Enable Registers"
hexmask.long 0x8 0.--31. 1. "GICD_ICENABLER2,Interrupt Clear-Enable Registers"
line.long 0xC "GICD_ICENABLER3,Interrupt Clear-Enable Registers"
hexmask.long 0xC 0.--31. 1. "GICD_ICENABLER3,Interrupt Clear-Enable Registers"
line.long 0x10 "GICD_ICENABLER4,Interrupt Clear-Enable Registers"
hexmask.long 0x10 0.--31. 1. "GICD_ICENABLER4,Interrupt Clear-Enable Registers"
line.long 0x14 "GICD_ICENABLER5,Interrupt Clear-Enable Registers"
hexmask.long 0x14 0.--31. 1. "GICD_ICENABLER5,Interrupt Clear-Enable Registers"
line.long 0x18 "GICD_ICENABLER6,Interrupt Clear-Enable Registers"
hexmask.long 0x18 0.--31. 1. "GICD_ICENABLER6,Interrupt Clear-Enable Registers"
line.long 0x1C "GICD_ICENABLER7,Interrupt Clear-Enable Registers"
hexmask.long 0x1C 0.--31. 1. "GICD_ICENABLER7,Interrupt Clear-Enable Registers"
line.long 0x20 "GICD_ICENABLER8,Interrupt Clear-Enable Registers"
hexmask.long 0x20 0.--31. 1. "GICD_ICENABLER8,Interrupt Clear-Enable Registers"
line.long 0x24 "GICD_ICENABLER9,Interrupt Clear-Enable Registers"
hexmask.long 0x24 0.--31. 1. "GICD_ICENABLER9,Interrupt Clear-Enable Registers"
line.long 0x28 "GICD_ICENABLER10,Interrupt Clear-Enable Registers"
hexmask.long 0x28 0.--31. 1. "GICD_ICENABLER10,Interrupt Clear-Enable Registers"
line.long 0x2C "GICD_ICENABLER11,Interrupt Clear-Enable Registers"
hexmask.long 0x2C 0.--31. 1. "GICD_ICENABLER11,Interrupt Clear-Enable Registers"
line.long 0x30 "GICD_ICENABLER12,Interrupt Clear-Enable Registers"
hexmask.long 0x30 0.--31. 1. "GICD_ICENABLER12,Interrupt Clear-Enable Registers"
line.long 0x34 "GICD_ICENABLER13,Interrupt Clear-Enable Registers"
hexmask.long 0x34 0.--31. 1. "GICD_ICENABLER13,Interrupt Clear-Enable Registers"
line.long 0x38 "GICD_ICENABLER14,Interrupt Clear-Enable Registers"
hexmask.long 0x38 0.--31. 1. "GICD_ICENABLER14,Interrupt Clear-Enable Registers"
line.long 0x3C "GICD_ICENABLER15,Interrupt Clear-Enable Registers"
hexmask.long 0x3C 0.--31. 1. "GICD_ICENABLER15,Interrupt Clear-Enable Registers"
group.long 0x200++0x3F
line.long 0x0 "GICD_ISPENDR0,Interrupt Set-Pending Registers"
hexmask.long 0x0 0.--31. 1. "GICD_ISPENDR0,Interrupt Set-Pending Registers"
line.long 0x4 "GICD_ISPENDR1,Interrupt Set-Pending Registers"
hexmask.long 0x4 0.--31. 1. "GICD_ISPENDR1,Interrupt Set-Pending Registers"
line.long 0x8 "GICD_ISPENDR2,Interrupt Set-Pending Registers"
hexmask.long 0x8 0.--31. 1. "GICD_ISPENDR2,Interrupt Set-Pending Registers"
line.long 0xC "GICD_ISPENDR3,Interrupt Set-Pending Registers"
hexmask.long 0xC 0.--31. 1. "GICD_ISPENDR3,Interrupt Set-Pending Registers"
line.long 0x10 "GICD_ISPENDR4,Interrupt Set-Pending Registers"
hexmask.long 0x10 0.--31. 1. "GICD_ISPENDR4,Interrupt Set-Pending Registers"
line.long 0x14 "GICD_ISPENDR5,Interrupt Set-Pending Registers"
hexmask.long 0x14 0.--31. 1. "GICD_ISPENDR5,Interrupt Set-Pending Registers"
line.long 0x18 "GICD_ISPENDR6,Interrupt Set-Pending Registers"
hexmask.long 0x18 0.--31. 1. "GICD_ISPENDR6,Interrupt Set-Pending Registers"
line.long 0x1C "GICD_ISPENDR7,Interrupt Set-Pending Registers"
hexmask.long 0x1C 0.--31. 1. "GICD_ISPENDR7,Interrupt Set-Pending Registers"
line.long 0x20 "GICD_ISPENDR8,Interrupt Set-Pending Registers"
hexmask.long 0x20 0.--31. 1. "GICD_ISPENDR8,Interrupt Set-Pending Registers"
line.long 0x24 "GICD_ISPENDR9,Interrupt Set-Pending Registers"
hexmask.long 0x24 0.--31. 1. "GICD_ISPENDR9,Interrupt Set-Pending Registers"
line.long 0x28 "GICD_ISPENDR10,Interrupt Set-Pending Registers"
hexmask.long 0x28 0.--31. 1. "GICD_ISPENDR10,Interrupt Set-Pending Registers"
line.long 0x2C "GICD_ISPENDR11,Interrupt Set-Pending Registers"
hexmask.long 0x2C 0.--31. 1. "GICD_ISPENDR11,Interrupt Set-Pending Registers"
line.long 0x30 "GICD_ISPENDR12,Interrupt Set-Pending Registers"
hexmask.long 0x30 0.--31. 1. "GICD_ISPENDR12,Interrupt Set-Pending Registers"
line.long 0x34 "GICD_ISPENDR13,Interrupt Set-Pending Registers"
hexmask.long 0x34 0.--31. 1. "GICD_ISPENDR13,Interrupt Set-Pending Registers"
line.long 0x38 "GICD_ISPENDR14,Interrupt Set-Pending Registers"
hexmask.long 0x38 0.--31. 1. "GICD_ISPENDR14,Interrupt Set-Pending Registers"
line.long 0x3C "GICD_ISPENDR15,Interrupt Set-Pending Registers"
hexmask.long 0x3C 0.--31. 1. "GICD_ISPENDR15,Interrupt Set-Pending Registers"
group.long 0x280++0x3F
line.long 0x0 "GICD_ICPENDR0,Interrupt Clear-Pending Registers"
hexmask.long 0x0 0.--31. 1. "GICD_ICPENDR0,Interrupt Clear-Pending Registers"
line.long 0x4 "GICD_ICPENDR1,Interrupt Clear-Pending Registers"
hexmask.long 0x4 0.--31. 1. "GICD_ICPENDR1,Interrupt Clear-Pending Registers"
line.long 0x8 "GICD_ICPENDR2,Interrupt Clear-Pending Registers"
hexmask.long 0x8 0.--31. 1. "GICD_ICPENDR2,Interrupt Clear-Pending Registers"
line.long 0xC "GICD_ICPENDR3,Interrupt Clear-Pending Registers"
hexmask.long 0xC 0.--31. 1. "GICD_ICPENDR3,Interrupt Clear-Pending Registers"
line.long 0x10 "GICD_ICPENDR4,Interrupt Clear-Pending Registers"
hexmask.long 0x10 0.--31. 1. "GICD_ICPENDR4,Interrupt Clear-Pending Registers"
line.long 0x14 "GICD_ICPENDR5,Interrupt Clear-Pending Registers"
hexmask.long 0x14 0.--31. 1. "GICD_ICPENDR5,Interrupt Clear-Pending Registers"
line.long 0x18 "GICD_ICPENDR6,Interrupt Clear-Pending Registers"
hexmask.long 0x18 0.--31. 1. "GICD_ICPENDR6,Interrupt Clear-Pending Registers"
line.long 0x1C "GICD_ICPENDR7,Interrupt Clear-Pending Registers"
hexmask.long 0x1C 0.--31. 1. "GICD_ICPENDR7,Interrupt Clear-Pending Registers"
line.long 0x20 "GICD_ICPENDR8,Interrupt Clear-Pending Registers"
hexmask.long 0x20 0.--31. 1. "GICD_ICPENDR8,Interrupt Clear-Pending Registers"
line.long 0x24 "GICD_ICPENDR9,Interrupt Clear-Pending Registers"
hexmask.long 0x24 0.--31. 1. "GICD_ICPENDR9,Interrupt Clear-Pending Registers"
line.long 0x28 "GICD_ICPENDR10,Interrupt Clear-Pending Registers"
hexmask.long 0x28 0.--31. 1. "GICD_ICPENDR10,Interrupt Clear-Pending Registers"
line.long 0x2C "GICD_ICPENDR11,Interrupt Clear-Pending Registers"
hexmask.long 0x2C 0.--31. 1. "GICD_ICPENDR11,Interrupt Clear-Pending Registers"
line.long 0x30 "GICD_ICPENDR12,Interrupt Clear-Pending Registers"
hexmask.long 0x30 0.--31. 1. "GICD_ICPENDR12,Interrupt Clear-Pending Registers"
line.long 0x34 "GICD_ICPENDR13,Interrupt Clear-Pending Registers"
hexmask.long 0x34 0.--31. 1. "GICD_ICPENDR13,Interrupt Clear-Pending Registers"
line.long 0x38 "GICD_ICPENDR14,Interrupt Clear-Pending Registers"
hexmask.long 0x38 0.--31. 1. "GICD_ICPENDR14,Interrupt Clear-Pending Registers"
line.long 0x3C "GICD_ICPENDR15,Interrupt Clear-Pending Registers"
hexmask.long 0x3C 0.--31. 1. "GICD_ICPENDR15,Interrupt Clear-Pending Registers"
group.long 0x300++0x3F
line.long 0x0 "GICD_ISACTIVER0,Interrupt Set-Active Registers"
hexmask.long 0x0 0.--31. 1. "GICD_ISACTIVER0,Interrupt Set-Active Registers"
line.long 0x4 "GICD_ISACTIVER1,Interrupt Set-Active Registers"
hexmask.long 0x4 0.--31. 1. "GICD_ISACTIVER1,Interrupt Set-Active Registers"
line.long 0x8 "GICD_ISACTIVER2,Interrupt Set-Active Registers"
hexmask.long 0x8 0.--31. 1. "GICD_ISACTIVER2,Interrupt Set-Active Registers"
line.long 0xC "GICD_ISACTIVER3,Interrupt Set-Active Registers"
hexmask.long 0xC 0.--31. 1. "GICD_ISACTIVER3,Interrupt Set-Active Registers"
line.long 0x10 "GICD_ISACTIVER4,Interrupt Set-Active Registers"
hexmask.long 0x10 0.--31. 1. "GICD_ISACTIVER4,Interrupt Set-Active Registers"
line.long 0x14 "GICD_ISACTIVER5,Interrupt Set-Active Registers"
hexmask.long 0x14 0.--31. 1. "GICD_ISACTIVER5,Interrupt Set-Active Registers"
line.long 0x18 "GICD_ISACTIVER6,Interrupt Set-Active Registers"
hexmask.long 0x18 0.--31. 1. "GICD_ISACTIVER6,Interrupt Set-Active Registers"
line.long 0x1C "GICD_ISACTIVER7,Interrupt Set-Active Registers"
hexmask.long 0x1C 0.--31. 1. "GICD_ISACTIVER7,Interrupt Set-Active Registers"
line.long 0x20 "GICD_ISACTIVER8,Interrupt Set-Active Registers"
hexmask.long 0x20 0.--31. 1. "GICD_ISACTIVER8,Interrupt Set-Active Registers"
line.long 0x24 "GICD_ISACTIVER9,Interrupt Set-Active Registers"
hexmask.long 0x24 0.--31. 1. "GICD_ISACTIVER9,Interrupt Set-Active Registers"
line.long 0x28 "GICD_ISACTIVER10,Interrupt Set-Active Registers"
hexmask.long 0x28 0.--31. 1. "GICD_ISACTIVER10,Interrupt Set-Active Registers"
line.long 0x2C "GICD_ISACTIVER11,Interrupt Set-Active Registers"
hexmask.long 0x2C 0.--31. 1. "GICD_ISACTIVER11,Interrupt Set-Active Registers"
line.long 0x30 "GICD_ISACTIVER12,Interrupt Set-Active Registers"
hexmask.long 0x30 0.--31. 1. "GICD_ISACTIVER12,Interrupt Set-Active Registers"
line.long 0x34 "GICD_ISACTIVER13,Interrupt Set-Active Registers"
hexmask.long 0x34 0.--31. 1. "GICD_ISACTIVER13,Interrupt Set-Active Registers"
line.long 0x38 "GICD_ISACTIVER14,Interrupt Set-Active Registers"
hexmask.long 0x38 0.--31. 1. "GICD_ISACTIVER14,Interrupt Set-Active Registers"
line.long 0x3C "GICD_ISACTIVER15,Interrupt Set-Active Registers"
hexmask.long 0x3C 0.--31. 1. "GICD_ISACTIVER15,Interrupt Set-Active Registers"
group.long 0x380++0x3F
line.long 0x0 "GICD_ICACTIVER0,Interrupt Clear-Active Registers"
hexmask.long 0x0 0.--31. 1. "GICD_ICACTIVER0,Interrupt Clear-Active Registers"
line.long 0x4 "GICD_ICACTIVER1,Interrupt Clear-Active Registers"
hexmask.long 0x4 0.--31. 1. "GICD_ICACTIVER1,Interrupt Clear-Active Registers"
line.long 0x8 "GICD_ICACTIVER2,Interrupt Clear-Active Registers"
hexmask.long 0x8 0.--31. 1. "GICD_ICACTIVER2,Interrupt Clear-Active Registers"
line.long 0xC "GICD_ICACTIVER3,Interrupt Clear-Active Registers"
hexmask.long 0xC 0.--31. 1. "GICD_ICACTIVER3,Interrupt Clear-Active Registers"
line.long 0x10 "GICD_ICACTIVER4,Interrupt Clear-Active Registers"
hexmask.long 0x10 0.--31. 1. "GICD_ICACTIVER4,Interrupt Clear-Active Registers"
line.long 0x14 "GICD_ICACTIVER5,Interrupt Clear-Active Registers"
hexmask.long 0x14 0.--31. 1. "GICD_ICACTIVER5,Interrupt Clear-Active Registers"
line.long 0x18 "GICD_ICACTIVER6,Interrupt Clear-Active Registers"
hexmask.long 0x18 0.--31. 1. "GICD_ICACTIVER6,Interrupt Clear-Active Registers"
line.long 0x1C "GICD_ICACTIVER7,Interrupt Clear-Active Registers"
hexmask.long 0x1C 0.--31. 1. "GICD_ICACTIVER7,Interrupt Clear-Active Registers"
line.long 0x20 "GICD_ICACTIVER8,Interrupt Clear-Active Registers"
hexmask.long 0x20 0.--31. 1. "GICD_ICACTIVER8,Interrupt Clear-Active Registers"
line.long 0x24 "GICD_ICACTIVER9,Interrupt Clear-Active Registers"
hexmask.long 0x24 0.--31. 1. "GICD_ICACTIVER9,Interrupt Clear-Active Registers"
line.long 0x28 "GICD_ICACTIVER10,Interrupt Clear-Active Registers"
hexmask.long 0x28 0.--31. 1. "GICD_ICACTIVER10,Interrupt Clear-Active Registers"
line.long 0x2C "GICD_ICACTIVER11,Interrupt Clear-Active Registers"
hexmask.long 0x2C 0.--31. 1. "GICD_ICACTIVER11,Interrupt Clear-Active Registers"
line.long 0x30 "GICD_ICACTIVER12,Interrupt Clear-Active Registers"
hexmask.long 0x30 0.--31. 1. "GICD_ICACTIVER12,Interrupt Clear-Active Registers"
line.long 0x34 "GICD_ICACTIVER13,Interrupt Clear-Active Registers"
hexmask.long 0x34 0.--31. 1. "GICD_ICACTIVER13,Interrupt Clear-Active Registers"
line.long 0x38 "GICD_ICACTIVER14,Interrupt Clear-Active Registers"
hexmask.long 0x38 0.--31. 1. "GICD_ICACTIVER14,Interrupt Clear-Active Registers"
line.long 0x3C "GICD_ICACTIVER15,Interrupt Clear-Active Registers"
hexmask.long 0x3C 0.--31. 1. "GICD_ICACTIVER15,Interrupt Clear-Active Registers"
group.long 0x400++0x1FF
line.long 0x0 "GICD_IPRIORITYR0,Interrupt Priority Registers"
hexmask.long 0x0 0.--31. 1. "GICD_IPRIORITYR0,Interrupt Priority Registers"
line.long 0x4 "GICD_IPRIORITYR1,Interrupt Priority Registers"
hexmask.long 0x4 0.--31. 1. "GICD_IPRIORITYR1,Interrupt Priority Registers"
line.long 0x8 "GICD_IPRIORITYR2,Interrupt Priority Registers"
hexmask.long 0x8 0.--31. 1. "GICD_IPRIORITYR2,Interrupt Priority Registers"
line.long 0xC "GICD_IPRIORITYR3,Interrupt Priority Registers"
hexmask.long 0xC 0.--31. 1. "GICD_IPRIORITYR3,Interrupt Priority Registers"
line.long 0x10 "GICD_IPRIORITYR4,Interrupt Priority Registers"
hexmask.long 0x10 0.--31. 1. "GICD_IPRIORITYR4,Interrupt Priority Registers"
line.long 0x14 "GICD_IPRIORITYR5,Interrupt Priority Registers"
hexmask.long 0x14 0.--31. 1. "GICD_IPRIORITYR5,Interrupt Priority Registers"
line.long 0x18 "GICD_IPRIORITYR6,Interrupt Priority Registers"
hexmask.long 0x18 0.--31. 1. "GICD_IPRIORITYR6,Interrupt Priority Registers"
line.long 0x1C "GICD_IPRIORITYR7,Interrupt Priority Registers"
hexmask.long 0x1C 0.--31. 1. "GICD_IPRIORITYR7,Interrupt Priority Registers"
line.long 0x20 "GICD_IPRIORITYR8,Interrupt Priority Registers"
hexmask.long 0x20 0.--31. 1. "GICD_IPRIORITYR8,Interrupt Priority Registers"
line.long 0x24 "GICD_IPRIORITYR9,Interrupt Priority Registers"
hexmask.long 0x24 0.--31. 1. "GICD_IPRIORITYR9,Interrupt Priority Registers"
line.long 0x28 "GICD_IPRIORITYR10,Interrupt Priority Registers"
hexmask.long 0x28 0.--31. 1. "GICD_IPRIORITYR10,Interrupt Priority Registers"
line.long 0x2C "GICD_IPRIORITYR11,Interrupt Priority Registers"
hexmask.long 0x2C 0.--31. 1. "GICD_IPRIORITYR11,Interrupt Priority Registers"
line.long 0x30 "GICD_IPRIORITYR12,Interrupt Priority Registers"
hexmask.long 0x30 0.--31. 1. "GICD_IPRIORITYR12,Interrupt Priority Registers"
line.long 0x34 "GICD_IPRIORITYR13,Interrupt Priority Registers"
hexmask.long 0x34 0.--31. 1. "GICD_IPRIORITYR13,Interrupt Priority Registers"
line.long 0x38 "GICD_IPRIORITYR14,Interrupt Priority Registers"
hexmask.long 0x38 0.--31. 1. "GICD_IPRIORITYR14,Interrupt Priority Registers"
line.long 0x3C "GICD_IPRIORITYR15,Interrupt Priority Registers"
hexmask.long 0x3C 0.--31. 1. "GICD_IPRIORITYR15,Interrupt Priority Registers"
line.long 0x40 "GICD_IPRIORITYR16,Interrupt Priority Registers"
hexmask.long 0x40 0.--31. 1. "GICD_IPRIORITYR16,Interrupt Priority Registers"
line.long 0x44 "GICD_IPRIORITYR17,Interrupt Priority Registers"
hexmask.long 0x44 0.--31. 1. "GICD_IPRIORITYR17,Interrupt Priority Registers"
line.long 0x48 "GICD_IPRIORITYR18,Interrupt Priority Registers"
hexmask.long 0x48 0.--31. 1. "GICD_IPRIORITYR18,Interrupt Priority Registers"
line.long 0x4C "GICD_IPRIORITYR19,Interrupt Priority Registers"
hexmask.long 0x4C 0.--31. 1. "GICD_IPRIORITYR19,Interrupt Priority Registers"
line.long 0x50 "GICD_IPRIORITYR20,Interrupt Priority Registers"
hexmask.long 0x50 0.--31. 1. "GICD_IPRIORITYR20,Interrupt Priority Registers"
line.long 0x54 "GICD_IPRIORITYR21,Interrupt Priority Registers"
hexmask.long 0x54 0.--31. 1. "GICD_IPRIORITYR21,Interrupt Priority Registers"
line.long 0x58 "GICD_IPRIORITYR22,Interrupt Priority Registers"
hexmask.long 0x58 0.--31. 1. "GICD_IPRIORITYR22,Interrupt Priority Registers"
line.long 0x5C "GICD_IPRIORITYR23,Interrupt Priority Registers"
hexmask.long 0x5C 0.--31. 1. "GICD_IPRIORITYR23,Interrupt Priority Registers"
line.long 0x60 "GICD_IPRIORITYR24,Interrupt Priority Registers"
hexmask.long 0x60 0.--31. 1. "GICD_IPRIORITYR24,Interrupt Priority Registers"
line.long 0x64 "GICD_IPRIORITYR25,Interrupt Priority Registers"
hexmask.long 0x64 0.--31. 1. "GICD_IPRIORITYR25,Interrupt Priority Registers"
line.long 0x68 "GICD_IPRIORITYR26,Interrupt Priority Registers"
hexmask.long 0x68 0.--31. 1. "GICD_IPRIORITYR26,Interrupt Priority Registers"
line.long 0x6C "GICD_IPRIORITYR27,Interrupt Priority Registers"
hexmask.long 0x6C 0.--31. 1. "GICD_IPRIORITYR27,Interrupt Priority Registers"
line.long 0x70 "GICD_IPRIORITYR28,Interrupt Priority Registers"
hexmask.long 0x70 0.--31. 1. "GICD_IPRIORITYR28,Interrupt Priority Registers"
line.long 0x74 "GICD_IPRIORITYR29,Interrupt Priority Registers"
hexmask.long 0x74 0.--31. 1. "GICD_IPRIORITYR29,Interrupt Priority Registers"
line.long 0x78 "GICD_IPRIORITYR30,Interrupt Priority Registers"
hexmask.long 0x78 0.--31. 1. "GICD_IPRIORITYR30,Interrupt Priority Registers"
line.long 0x7C "GICD_IPRIORITYR31,Interrupt Priority Registers"
hexmask.long 0x7C 0.--31. 1. "GICD_IPRIORITYR31,Interrupt Priority Registers"
line.long 0x80 "GICD_IPRIORITYR32,Interrupt Priority Registers"
hexmask.long 0x80 0.--31. 1. "GICD_IPRIORITYR32,Interrupt Priority Registers"
line.long 0x84 "GICD_IPRIORITYR33,Interrupt Priority Registers"
hexmask.long 0x84 0.--31. 1. "GICD_IPRIORITYR33,Interrupt Priority Registers"
line.long 0x88 "GICD_IPRIORITYR34,Interrupt Priority Registers"
hexmask.long 0x88 0.--31. 1. "GICD_IPRIORITYR34,Interrupt Priority Registers"
line.long 0x8C "GICD_IPRIORITYR35,Interrupt Priority Registers"
hexmask.long 0x8C 0.--31. 1. "GICD_IPRIORITYR35,Interrupt Priority Registers"
line.long 0x90 "GICD_IPRIORITYR36,Interrupt Priority Registers"
hexmask.long 0x90 0.--31. 1. "GICD_IPRIORITYR36,Interrupt Priority Registers"
line.long 0x94 "GICD_IPRIORITYR37,Interrupt Priority Registers"
hexmask.long 0x94 0.--31. 1. "GICD_IPRIORITYR37,Interrupt Priority Registers"
line.long 0x98 "GICD_IPRIORITYR38,Interrupt Priority Registers"
hexmask.long 0x98 0.--31. 1. "GICD_IPRIORITYR38,Interrupt Priority Registers"
line.long 0x9C "GICD_IPRIORITYR39,Interrupt Priority Registers"
hexmask.long 0x9C 0.--31. 1. "GICD_IPRIORITYR39,Interrupt Priority Registers"
line.long 0xA0 "GICD_IPRIORITYR40,Interrupt Priority Registers"
hexmask.long 0xA0 0.--31. 1. "GICD_IPRIORITYR40,Interrupt Priority Registers"
line.long 0xA4 "GICD_IPRIORITYR41,Interrupt Priority Registers"
hexmask.long 0xA4 0.--31. 1. "GICD_IPRIORITYR41,Interrupt Priority Registers"
line.long 0xA8 "GICD_IPRIORITYR42,Interrupt Priority Registers"
hexmask.long 0xA8 0.--31. 1. "GICD_IPRIORITYR42,Interrupt Priority Registers"
line.long 0xAC "GICD_IPRIORITYR43,Interrupt Priority Registers"
hexmask.long 0xAC 0.--31. 1. "GICD_IPRIORITYR43,Interrupt Priority Registers"
line.long 0xB0 "GICD_IPRIORITYR44,Interrupt Priority Registers"
hexmask.long 0xB0 0.--31. 1. "GICD_IPRIORITYR44,Interrupt Priority Registers"
line.long 0xB4 "GICD_IPRIORITYR45,Interrupt Priority Registers"
hexmask.long 0xB4 0.--31. 1. "GICD_IPRIORITYR45,Interrupt Priority Registers"
line.long 0xB8 "GICD_IPRIORITYR46,Interrupt Priority Registers"
hexmask.long 0xB8 0.--31. 1. "GICD_IPRIORITYR46,Interrupt Priority Registers"
line.long 0xBC "GICD_IPRIORITYR47,Interrupt Priority Registers"
hexmask.long 0xBC 0.--31. 1. "GICD_IPRIORITYR47,Interrupt Priority Registers"
line.long 0xC0 "GICD_IPRIORITYR48,Interrupt Priority Registers"
hexmask.long 0xC0 0.--31. 1. "GICD_IPRIORITYR48,Interrupt Priority Registers"
line.long 0xC4 "GICD_IPRIORITYR49,Interrupt Priority Registers"
hexmask.long 0xC4 0.--31. 1. "GICD_IPRIORITYR49,Interrupt Priority Registers"
line.long 0xC8 "GICD_IPRIORITYR50,Interrupt Priority Registers"
hexmask.long 0xC8 0.--31. 1. "GICD_IPRIORITYR50,Interrupt Priority Registers"
line.long 0xCC "GICD_IPRIORITYR51,Interrupt Priority Registers"
hexmask.long 0xCC 0.--31. 1. "GICD_IPRIORITYR51,Interrupt Priority Registers"
line.long 0xD0 "GICD_IPRIORITYR52,Interrupt Priority Registers"
hexmask.long 0xD0 0.--31. 1. "GICD_IPRIORITYR52,Interrupt Priority Registers"
line.long 0xD4 "GICD_IPRIORITYR53,Interrupt Priority Registers"
hexmask.long 0xD4 0.--31. 1. "GICD_IPRIORITYR53,Interrupt Priority Registers"
line.long 0xD8 "GICD_IPRIORITYR54,Interrupt Priority Registers"
hexmask.long 0xD8 0.--31. 1. "GICD_IPRIORITYR54,Interrupt Priority Registers"
line.long 0xDC "GICD_IPRIORITYR55,Interrupt Priority Registers"
hexmask.long 0xDC 0.--31. 1. "GICD_IPRIORITYR55,Interrupt Priority Registers"
line.long 0xE0 "GICD_IPRIORITYR56,Interrupt Priority Registers"
hexmask.long 0xE0 0.--31. 1. "GICD_IPRIORITYR56,Interrupt Priority Registers"
line.long 0xE4 "GICD_IPRIORITYR57,Interrupt Priority Registers"
hexmask.long 0xE4 0.--31. 1. "GICD_IPRIORITYR57,Interrupt Priority Registers"
line.long 0xE8 "GICD_IPRIORITYR58,Interrupt Priority Registers"
hexmask.long 0xE8 0.--31. 1. "GICD_IPRIORITYR58,Interrupt Priority Registers"
line.long 0xEC "GICD_IPRIORITYR59,Interrupt Priority Registers"
hexmask.long 0xEC 0.--31. 1. "GICD_IPRIORITYR59,Interrupt Priority Registers"
line.long 0xF0 "GICD_IPRIORITYR60,Interrupt Priority Registers"
hexmask.long 0xF0 0.--31. 1. "GICD_IPRIORITYR60,Interrupt Priority Registers"
line.long 0xF4 "GICD_IPRIORITYR61,Interrupt Priority Registers"
hexmask.long 0xF4 0.--31. 1. "GICD_IPRIORITYR61,Interrupt Priority Registers"
line.long 0xF8 "GICD_IPRIORITYR62,Interrupt Priority Registers"
hexmask.long 0xF8 0.--31. 1. "GICD_IPRIORITYR62,Interrupt Priority Registers"
line.long 0xFC "GICD_IPRIORITYR63,Interrupt Priority Registers"
hexmask.long 0xFC 0.--31. 1. "GICD_IPRIORITYR63,Interrupt Priority Registers"
line.long 0x100 "GICD_IPRIORITYR64,Interrupt Priority Registers"
hexmask.long 0x100 0.--31. 1. "GICD_IPRIORITYR64,Interrupt Priority Registers"
line.long 0x104 "GICD_IPRIORITYR65,Interrupt Priority Registers"
hexmask.long 0x104 0.--31. 1. "GICD_IPRIORITYR65,Interrupt Priority Registers"
line.long 0x108 "GICD_IPRIORITYR66,Interrupt Priority Registers"
hexmask.long 0x108 0.--31. 1. "GICD_IPRIORITYR66,Interrupt Priority Registers"
line.long 0x10C "GICD_IPRIORITYR67,Interrupt Priority Registers"
hexmask.long 0x10C 0.--31. 1. "GICD_IPRIORITYR67,Interrupt Priority Registers"
line.long 0x110 "GICD_IPRIORITYR68,Interrupt Priority Registers"
hexmask.long 0x110 0.--31. 1. "GICD_IPRIORITYR68,Interrupt Priority Registers"
line.long 0x114 "GICD_IPRIORITYR69,Interrupt Priority Registers"
hexmask.long 0x114 0.--31. 1. "GICD_IPRIORITYR69,Interrupt Priority Registers"
line.long 0x118 "GICD_IPRIORITYR70,Interrupt Priority Registers"
hexmask.long 0x118 0.--31. 1. "GICD_IPRIORITYR70,Interrupt Priority Registers"
line.long 0x11C "GICD_IPRIORITYR71,Interrupt Priority Registers"
hexmask.long 0x11C 0.--31. 1. "GICD_IPRIORITYR71,Interrupt Priority Registers"
line.long 0x120 "GICD_IPRIORITYR72,Interrupt Priority Registers"
hexmask.long 0x120 0.--31. 1. "GICD_IPRIORITYR72,Interrupt Priority Registers"
line.long 0x124 "GICD_IPRIORITYR73,Interrupt Priority Registers"
hexmask.long 0x124 0.--31. 1. "GICD_IPRIORITYR73,Interrupt Priority Registers"
line.long 0x128 "GICD_IPRIORITYR74,Interrupt Priority Registers"
hexmask.long 0x128 0.--31. 1. "GICD_IPRIORITYR74,Interrupt Priority Registers"
line.long 0x12C "GICD_IPRIORITYR75,Interrupt Priority Registers"
hexmask.long 0x12C 0.--31. 1. "GICD_IPRIORITYR75,Interrupt Priority Registers"
line.long 0x130 "GICD_IPRIORITYR76,Interrupt Priority Registers"
hexmask.long 0x130 0.--31. 1. "GICD_IPRIORITYR76,Interrupt Priority Registers"
line.long 0x134 "GICD_IPRIORITYR77,Interrupt Priority Registers"
hexmask.long 0x134 0.--31. 1. "GICD_IPRIORITYR77,Interrupt Priority Registers"
line.long 0x138 "GICD_IPRIORITYR78,Interrupt Priority Registers"
hexmask.long 0x138 0.--31. 1. "GICD_IPRIORITYR78,Interrupt Priority Registers"
line.long 0x13C "GICD_IPRIORITYR79,Interrupt Priority Registers"
hexmask.long 0x13C 0.--31. 1. "GICD_IPRIORITYR79,Interrupt Priority Registers"
line.long 0x140 "GICD_IPRIORITYR80,Interrupt Priority Registers"
hexmask.long 0x140 0.--31. 1. "GICD_IPRIORITYR80,Interrupt Priority Registers"
line.long 0x144 "GICD_IPRIORITYR81,Interrupt Priority Registers"
hexmask.long 0x144 0.--31. 1. "GICD_IPRIORITYR81,Interrupt Priority Registers"
line.long 0x148 "GICD_IPRIORITYR82,Interrupt Priority Registers"
hexmask.long 0x148 0.--31. 1. "GICD_IPRIORITYR82,Interrupt Priority Registers"
line.long 0x14C "GICD_IPRIORITYR83,Interrupt Priority Registers"
hexmask.long 0x14C 0.--31. 1. "GICD_IPRIORITYR83,Interrupt Priority Registers"
line.long 0x150 "GICD_IPRIORITYR84,Interrupt Priority Registers"
hexmask.long 0x150 0.--31. 1. "GICD_IPRIORITYR84,Interrupt Priority Registers"
line.long 0x154 "GICD_IPRIORITYR85,Interrupt Priority Registers"
hexmask.long 0x154 0.--31. 1. "GICD_IPRIORITYR85,Interrupt Priority Registers"
line.long 0x158 "GICD_IPRIORITYR86,Interrupt Priority Registers"
hexmask.long 0x158 0.--31. 1. "GICD_IPRIORITYR86,Interrupt Priority Registers"
line.long 0x15C "GICD_IPRIORITYR87,Interrupt Priority Registers"
hexmask.long 0x15C 0.--31. 1. "GICD_IPRIORITYR87,Interrupt Priority Registers"
line.long 0x160 "GICD_IPRIORITYR88,Interrupt Priority Registers"
hexmask.long 0x160 0.--31. 1. "GICD_IPRIORITYR88,Interrupt Priority Registers"
line.long 0x164 "GICD_IPRIORITYR89,Interrupt Priority Registers"
hexmask.long 0x164 0.--31. 1. "GICD_IPRIORITYR89,Interrupt Priority Registers"
line.long 0x168 "GICD_IPRIORITYR90,Interrupt Priority Registers"
hexmask.long 0x168 0.--31. 1. "GICD_IPRIORITYR90,Interrupt Priority Registers"
line.long 0x16C "GICD_IPRIORITYR91,Interrupt Priority Registers"
hexmask.long 0x16C 0.--31. 1. "GICD_IPRIORITYR91,Interrupt Priority Registers"
line.long 0x170 "GICD_IPRIORITYR92,Interrupt Priority Registers"
hexmask.long 0x170 0.--31. 1. "GICD_IPRIORITYR92,Interrupt Priority Registers"
line.long 0x174 "GICD_IPRIORITYR93,Interrupt Priority Registers"
hexmask.long 0x174 0.--31. 1. "GICD_IPRIORITYR93,Interrupt Priority Registers"
line.long 0x178 "GICD_IPRIORITYR94,Interrupt Priority Registers"
hexmask.long 0x178 0.--31. 1. "GICD_IPRIORITYR94,Interrupt Priority Registers"
line.long 0x17C "GICD_IPRIORITYR95,Interrupt Priority Registers"
hexmask.long 0x17C 0.--31. 1. "GICD_IPRIORITYR95,Interrupt Priority Registers"
line.long 0x180 "GICD_IPRIORITYR96,Interrupt Priority Registers"
hexmask.long 0x180 0.--31. 1. "GICD_IPRIORITYR96,Interrupt Priority Registers"
line.long 0x184 "GICD_IPRIORITYR97,Interrupt Priority Registers"
hexmask.long 0x184 0.--31. 1. "GICD_IPRIORITYR97,Interrupt Priority Registers"
line.long 0x188 "GICD_IPRIORITYR98,Interrupt Priority Registers"
hexmask.long 0x188 0.--31. 1. "GICD_IPRIORITYR98,Interrupt Priority Registers"
line.long 0x18C "GICD_IPRIORITYR99,Interrupt Priority Registers"
hexmask.long 0x18C 0.--31. 1. "GICD_IPRIORITYR99,Interrupt Priority Registers"
line.long 0x190 "GICD_IPRIORITYR100,Interrupt Priority Registers"
hexmask.long 0x190 0.--31. 1. "GICD_IPRIORITYR100,Interrupt Priority Registers"
line.long 0x194 "GICD_IPRIORITYR101,Interrupt Priority Registers"
hexmask.long 0x194 0.--31. 1. "GICD_IPRIORITYR101,Interrupt Priority Registers"
line.long 0x198 "GICD_IPRIORITYR102,Interrupt Priority Registers"
hexmask.long 0x198 0.--31. 1. "GICD_IPRIORITYR102,Interrupt Priority Registers"
line.long 0x19C "GICD_IPRIORITYR103,Interrupt Priority Registers"
hexmask.long 0x19C 0.--31. 1. "GICD_IPRIORITYR103,Interrupt Priority Registers"
line.long 0x1A0 "GICD_IPRIORITYR104,Interrupt Priority Registers"
hexmask.long 0x1A0 0.--31. 1. "GICD_IPRIORITYR104,Interrupt Priority Registers"
line.long 0x1A4 "GICD_IPRIORITYR105,Interrupt Priority Registers"
hexmask.long 0x1A4 0.--31. 1. "GICD_IPRIORITYR105,Interrupt Priority Registers"
line.long 0x1A8 "GICD_IPRIORITYR106,Interrupt Priority Registers"
hexmask.long 0x1A8 0.--31. 1. "GICD_IPRIORITYR106,Interrupt Priority Registers"
line.long 0x1AC "GICD_IPRIORITYR107,Interrupt Priority Registers"
hexmask.long 0x1AC 0.--31. 1. "GICD_IPRIORITYR107,Interrupt Priority Registers"
line.long 0x1B0 "GICD_IPRIORITYR108,Interrupt Priority Registers"
hexmask.long 0x1B0 0.--31. 1. "GICD_IPRIORITYR108,Interrupt Priority Registers"
line.long 0x1B4 "GICD_IPRIORITYR109,Interrupt Priority Registers"
hexmask.long 0x1B4 0.--31. 1. "GICD_IPRIORITYR109,Interrupt Priority Registers"
line.long 0x1B8 "GICD_IPRIORITYR110,Interrupt Priority Registers"
hexmask.long 0x1B8 0.--31. 1. "GICD_IPRIORITYR110,Interrupt Priority Registers"
line.long 0x1BC "GICD_IPRIORITYR111,Interrupt Priority Registers"
hexmask.long 0x1BC 0.--31. 1. "GICD_IPRIORITYR111,Interrupt Priority Registers"
line.long 0x1C0 "GICD_IPRIORITYR112,Interrupt Priority Registers"
hexmask.long 0x1C0 0.--31. 1. "GICD_IPRIORITYR112,Interrupt Priority Registers"
line.long 0x1C4 "GICD_IPRIORITYR113,Interrupt Priority Registers"
hexmask.long 0x1C4 0.--31. 1. "GICD_IPRIORITYR113,Interrupt Priority Registers"
line.long 0x1C8 "GICD_IPRIORITYR114,Interrupt Priority Registers"
hexmask.long 0x1C8 0.--31. 1. "GICD_IPRIORITYR114,Interrupt Priority Registers"
line.long 0x1CC "GICD_IPRIORITYR115,Interrupt Priority Registers"
hexmask.long 0x1CC 0.--31. 1. "GICD_IPRIORITYR115,Interrupt Priority Registers"
line.long 0x1D0 "GICD_IPRIORITYR116,Interrupt Priority Registers"
hexmask.long 0x1D0 0.--31. 1. "GICD_IPRIORITYR116,Interrupt Priority Registers"
line.long 0x1D4 "GICD_IPRIORITYR117,Interrupt Priority Registers"
hexmask.long 0x1D4 0.--31. 1. "GICD_IPRIORITYR117,Interrupt Priority Registers"
line.long 0x1D8 "GICD_IPRIORITYR118,Interrupt Priority Registers"
hexmask.long 0x1D8 0.--31. 1. "GICD_IPRIORITYR118,Interrupt Priority Registers"
line.long 0x1DC "GICD_IPRIORITYR119,Interrupt Priority Registers"
hexmask.long 0x1DC 0.--31. 1. "GICD_IPRIORITYR119,Interrupt Priority Registers"
line.long 0x1E0 "GICD_IPRIORITYR120,Interrupt Priority Registers"
hexmask.long 0x1E0 0.--31. 1. "GICD_IPRIORITYR120,Interrupt Priority Registers"
line.long 0x1E4 "GICD_IPRIORITYR121,Interrupt Priority Registers"
hexmask.long 0x1E4 0.--31. 1. "GICD_IPRIORITYR121,Interrupt Priority Registers"
line.long 0x1E8 "GICD_IPRIORITYR122,Interrupt Priority Registers"
hexmask.long 0x1E8 0.--31. 1. "GICD_IPRIORITYR122,Interrupt Priority Registers"
line.long 0x1EC "GICD_IPRIORITYR123,Interrupt Priority Registers"
hexmask.long 0x1EC 0.--31. 1. "GICD_IPRIORITYR123,Interrupt Priority Registers"
line.long 0x1F0 "GICD_IPRIORITYR124,Interrupt Priority Registers"
hexmask.long 0x1F0 0.--31. 1. "GICD_IPRIORITYR124,Interrupt Priority Registers"
line.long 0x1F4 "GICD_IPRIORITYR125,Interrupt Priority Registers"
hexmask.long 0x1F4 0.--31. 1. "GICD_IPRIORITYR125,Interrupt Priority Registers"
line.long 0x1F8 "GICD_IPRIORITYR126,Interrupt Priority Registers"
hexmask.long 0x1F8 0.--31. 1. "GICD_IPRIORITYR126,Interrupt Priority Registers"
line.long 0x1FC "GICD_IPRIORITYR127,Interrupt Priority Registers"
hexmask.long 0x1FC 0.--31. 1. "GICD_IPRIORITYR127,Interrupt Priority Registers"
rgroup.long 0x800++0x1F
line.long 0x0 "GICD_ITARGETSR0,Interrupt Processor Targets Registers"
hexmask.long 0x0 0.--31. 1. "GICD_ITARGETSR0,Interrupt Processor Targets Registers"
line.long 0x4 "GICD_ITARGETSR1,Interrupt Processor Targets Registers"
hexmask.long 0x4 0.--31. 1. "GICD_ITARGETSR1,Interrupt Processor Targets Registers"
line.long 0x8 "GICD_ITARGETSR2,Interrupt Processor Targets Registers"
hexmask.long 0x8 0.--31. 1. "GICD_ITARGETSR2,Interrupt Processor Targets Registers"
line.long 0xC "GICD_ITARGETSR3,Interrupt Processor Targets Registers"
hexmask.long 0xC 0.--31. 1. "GICD_ITARGETSR3,Interrupt Processor Targets Registers"
line.long 0x10 "GICD_ITARGETSR4,Interrupt Processor Targets Registers"
hexmask.long 0x10 0.--31. 1. "GICD_ITARGETSR4,Interrupt Processor Targets Registers"
line.long 0x14 "GICD_ITARGETSR5,Interrupt Processor Targets Registers"
hexmask.long 0x14 0.--31. 1. "GICD_ITARGETSR5,Interrupt Processor Targets Registers"
line.long 0x18 "GICD_ITARGETSR6,Interrupt Processor Targets Registers"
hexmask.long 0x18 0.--31. 1. "GICD_ITARGETSR6,Interrupt Processor Targets Registers"
line.long 0x1C "GICD_ITARGETSR7,Interrupt Processor Targets Registers"
hexmask.long 0x1C 0.--31. 1. "GICD_ITARGETSR7,Interrupt Processor Targets Registers"
group.long 0x820++0x1DF
line.long 0x0 "GICD_ITARGETSR8,Interrupt Processor Targets Registers"
hexmask.long 0x0 0.--31. 1. "GICD_ITARGETSR8,Interrupt Processor Targets Registers"
line.long 0x4 "GICD_ITARGETSR9,Interrupt Processor Targets Registers"
hexmask.long 0x4 0.--31. 1. "GICD_ITARGETSR9,Interrupt Processor Targets Registers"
line.long 0x8 "GICD_ITARGETSR10,Interrupt Processor Targets Registers"
hexmask.long 0x8 0.--31. 1. "GICD_ITARGETSR10,Interrupt Processor Targets Registers"
line.long 0xC "GICD_ITARGETSR11,Interrupt Processor Targets Registers"
hexmask.long 0xC 0.--31. 1. "GICD_ITARGETSR11,Interrupt Processor Targets Registers"
line.long 0x10 "GICD_ITARGETSR12,Interrupt Processor Targets Registers"
hexmask.long 0x10 0.--31. 1. "GICD_ITARGETSR12,Interrupt Processor Targets Registers"
line.long 0x14 "GICD_ITARGETSR13,Interrupt Processor Targets Registers"
hexmask.long 0x14 0.--31. 1. "GICD_ITARGETSR13,Interrupt Processor Targets Registers"
line.long 0x18 "GICD_ITARGETSR14,Interrupt Processor Targets Registers"
hexmask.long 0x18 0.--31. 1. "GICD_ITARGETSR14,Interrupt Processor Targets Registers"
line.long 0x1C "GICD_ITARGETSR15,Interrupt Processor Targets Registers"
hexmask.long 0x1C 0.--31. 1. "GICD_ITARGETSR15,Interrupt Processor Targets Registers"
line.long 0x20 "GICD_ITARGETSR16,Interrupt Processor Targets Registers"
hexmask.long 0x20 0.--31. 1. "GICD_ITARGETSR16,Interrupt Processor Targets Registers"
line.long 0x24 "GICD_ITARGETSR17,Interrupt Processor Targets Registers"
hexmask.long 0x24 0.--31. 1. "GICD_ITARGETSR17,Interrupt Processor Targets Registers"
line.long 0x28 "GICD_ITARGETSR18,Interrupt Processor Targets Registers"
hexmask.long 0x28 0.--31. 1. "GICD_ITARGETSR18,Interrupt Processor Targets Registers"
line.long 0x2C "GICD_ITARGETSR19,Interrupt Processor Targets Registers"
hexmask.long 0x2C 0.--31. 1. "GICD_ITARGETSR19,Interrupt Processor Targets Registers"
line.long 0x30 "GICD_ITARGETSR20,Interrupt Processor Targets Registers"
hexmask.long 0x30 0.--31. 1. "GICD_ITARGETSR20,Interrupt Processor Targets Registers"
line.long 0x34 "GICD_ITARGETSR21,Interrupt Processor Targets Registers"
hexmask.long 0x34 0.--31. 1. "GICD_ITARGETSR21,Interrupt Processor Targets Registers"
line.long 0x38 "GICD_ITARGETSR22,Interrupt Processor Targets Registers"
hexmask.long 0x38 0.--31. 1. "GICD_ITARGETSR22,Interrupt Processor Targets Registers"
line.long 0x3C "GICD_ITARGETSR23,Interrupt Processor Targets Registers"
hexmask.long 0x3C 0.--31. 1. "GICD_ITARGETSR23,Interrupt Processor Targets Registers"
line.long 0x40 "GICD_ITARGETSR24,Interrupt Processor Targets Registers"
hexmask.long 0x40 0.--31. 1. "GICD_ITARGETSR24,Interrupt Processor Targets Registers"
line.long 0x44 "GICD_ITARGETSR25,Interrupt Processor Targets Registers"
hexmask.long 0x44 0.--31. 1. "GICD_ITARGETSR25,Interrupt Processor Targets Registers"
line.long 0x48 "GICD_ITARGETSR26,Interrupt Processor Targets Registers"
hexmask.long 0x48 0.--31. 1. "GICD_ITARGETSR26,Interrupt Processor Targets Registers"
line.long 0x4C "GICD_ITARGETSR27,Interrupt Processor Targets Registers"
hexmask.long 0x4C 0.--31. 1. "GICD_ITARGETSR27,Interrupt Processor Targets Registers"
line.long 0x50 "GICD_ITARGETSR28,Interrupt Processor Targets Registers"
hexmask.long 0x50 0.--31. 1. "GICD_ITARGETSR28,Interrupt Processor Targets Registers"
line.long 0x54 "GICD_ITARGETSR29,Interrupt Processor Targets Registers"
hexmask.long 0x54 0.--31. 1. "GICD_ITARGETSR29,Interrupt Processor Targets Registers"
line.long 0x58 "GICD_ITARGETSR30,Interrupt Processor Targets Registers"
hexmask.long 0x58 0.--31. 1. "GICD_ITARGETSR30,Interrupt Processor Targets Registers"
line.long 0x5C "GICD_ITARGETSR31,Interrupt Processor Targets Registers"
hexmask.long 0x5C 0.--31. 1. "GICD_ITARGETSR31,Interrupt Processor Targets Registers"
line.long 0x60 "GICD_ITARGETSR32,Interrupt Processor Targets Registers"
hexmask.long 0x60 0.--31. 1. "GICD_ITARGETSR32,Interrupt Processor Targets Registers"
line.long 0x64 "GICD_ITARGETSR33,Interrupt Processor Targets Registers"
hexmask.long 0x64 0.--31. 1. "GICD_ITARGETSR33,Interrupt Processor Targets Registers"
line.long 0x68 "GICD_ITARGETSR34,Interrupt Processor Targets Registers"
hexmask.long 0x68 0.--31. 1. "GICD_ITARGETSR34,Interrupt Processor Targets Registers"
line.long 0x6C "GICD_ITARGETSR35,Interrupt Processor Targets Registers"
hexmask.long 0x6C 0.--31. 1. "GICD_ITARGETSR35,Interrupt Processor Targets Registers"
line.long 0x70 "GICD_ITARGETSR36,Interrupt Processor Targets Registers"
hexmask.long 0x70 0.--31. 1. "GICD_ITARGETSR36,Interrupt Processor Targets Registers"
line.long 0x74 "GICD_ITARGETSR37,Interrupt Processor Targets Registers"
hexmask.long 0x74 0.--31. 1. "GICD_ITARGETSR37,Interrupt Processor Targets Registers"
line.long 0x78 "GICD_ITARGETSR38,Interrupt Processor Targets Registers"
hexmask.long 0x78 0.--31. 1. "GICD_ITARGETSR38,Interrupt Processor Targets Registers"
line.long 0x7C "GICD_ITARGETSR39,Interrupt Processor Targets Registers"
hexmask.long 0x7C 0.--31. 1. "GICD_ITARGETSR39,Interrupt Processor Targets Registers"
line.long 0x80 "GICD_ITARGETSR40,Interrupt Processor Targets Registers"
hexmask.long 0x80 0.--31. 1. "GICD_ITARGETSR40,Interrupt Processor Targets Registers"
line.long 0x84 "GICD_ITARGETSR41,Interrupt Processor Targets Registers"
hexmask.long 0x84 0.--31. 1. "GICD_ITARGETSR41,Interrupt Processor Targets Registers"
line.long 0x88 "GICD_ITARGETSR42,Interrupt Processor Targets Registers"
hexmask.long 0x88 0.--31. 1. "GICD_ITARGETSR42,Interrupt Processor Targets Registers"
line.long 0x8C "GICD_ITARGETSR43,Interrupt Processor Targets Registers"
hexmask.long 0x8C 0.--31. 1. "GICD_ITARGETSR43,Interrupt Processor Targets Registers"
line.long 0x90 "GICD_ITARGETSR44,Interrupt Processor Targets Registers"
hexmask.long 0x90 0.--31. 1. "GICD_ITARGETSR44,Interrupt Processor Targets Registers"
line.long 0x94 "GICD_ITARGETSR45,Interrupt Processor Targets Registers"
hexmask.long 0x94 0.--31. 1. "GICD_ITARGETSR45,Interrupt Processor Targets Registers"
line.long 0x98 "GICD_ITARGETSR46,Interrupt Processor Targets Registers"
hexmask.long 0x98 0.--31. 1. "GICD_ITARGETSR46,Interrupt Processor Targets Registers"
line.long 0x9C "GICD_ITARGETSR47,Interrupt Processor Targets Registers"
hexmask.long 0x9C 0.--31. 1. "GICD_ITARGETSR47,Interrupt Processor Targets Registers"
line.long 0xA0 "GICD_ITARGETSR48,Interrupt Processor Targets Registers"
hexmask.long 0xA0 0.--31. 1. "GICD_ITARGETSR48,Interrupt Processor Targets Registers"
line.long 0xA4 "GICD_ITARGETSR49,Interrupt Processor Targets Registers"
hexmask.long 0xA4 0.--31. 1. "GICD_ITARGETSR49,Interrupt Processor Targets Registers"
line.long 0xA8 "GICD_ITARGETSR50,Interrupt Processor Targets Registers"
hexmask.long 0xA8 0.--31. 1. "GICD_ITARGETSR50,Interrupt Processor Targets Registers"
line.long 0xAC "GICD_ITARGETSR51,Interrupt Processor Targets Registers"
hexmask.long 0xAC 0.--31. 1. "GICD_ITARGETSR51,Interrupt Processor Targets Registers"
line.long 0xB0 "GICD_ITARGETSR52,Interrupt Processor Targets Registers"
hexmask.long 0xB0 0.--31. 1. "GICD_ITARGETSR52,Interrupt Processor Targets Registers"
line.long 0xB4 "GICD_ITARGETSR53,Interrupt Processor Targets Registers"
hexmask.long 0xB4 0.--31. 1. "GICD_ITARGETSR53,Interrupt Processor Targets Registers"
line.long 0xB8 "GICD_ITARGETSR54,Interrupt Processor Targets Registers"
hexmask.long 0xB8 0.--31. 1. "GICD_ITARGETSR54,Interrupt Processor Targets Registers"
line.long 0xBC "GICD_ITARGETSR55,Interrupt Processor Targets Registers"
hexmask.long 0xBC 0.--31. 1. "GICD_ITARGETSR55,Interrupt Processor Targets Registers"
line.long 0xC0 "GICD_ITARGETSR56,Interrupt Processor Targets Registers"
hexmask.long 0xC0 0.--31. 1. "GICD_ITARGETSR56,Interrupt Processor Targets Registers"
line.long 0xC4 "GICD_ITARGETSR57,Interrupt Processor Targets Registers"
hexmask.long 0xC4 0.--31. 1. "GICD_ITARGETSR57,Interrupt Processor Targets Registers"
line.long 0xC8 "GICD_ITARGETSR58,Interrupt Processor Targets Registers"
hexmask.long 0xC8 0.--31. 1. "GICD_ITARGETSR58,Interrupt Processor Targets Registers"
line.long 0xCC "GICD_ITARGETSR59,Interrupt Processor Targets Registers"
hexmask.long 0xCC 0.--31. 1. "GICD_ITARGETSR59,Interrupt Processor Targets Registers"
line.long 0xD0 "GICD_ITARGETSR60,Interrupt Processor Targets Registers"
hexmask.long 0xD0 0.--31. 1. "GICD_ITARGETSR60,Interrupt Processor Targets Registers"
line.long 0xD4 "GICD_ITARGETSR61,Interrupt Processor Targets Registers"
hexmask.long 0xD4 0.--31. 1. "GICD_ITARGETSR61,Interrupt Processor Targets Registers"
line.long 0xD8 "GICD_ITARGETSR62,Interrupt Processor Targets Registers"
hexmask.long 0xD8 0.--31. 1. "GICD_ITARGETSR62,Interrupt Processor Targets Registers"
line.long 0xDC "GICD_ITARGETSR63,Interrupt Processor Targets Registers"
hexmask.long 0xDC 0.--31. 1. "GICD_ITARGETSR63,Interrupt Processor Targets Registers"
line.long 0xE0 "GICD_ITARGETSR64,Interrupt Processor Targets Registers"
hexmask.long 0xE0 0.--31. 1. "GICD_ITARGETSR64,Interrupt Processor Targets Registers"
line.long 0xE4 "GICD_ITARGETSR65,Interrupt Processor Targets Registers"
hexmask.long 0xE4 0.--31. 1. "GICD_ITARGETSR65,Interrupt Processor Targets Registers"
line.long 0xE8 "GICD_ITARGETSR66,Interrupt Processor Targets Registers"
hexmask.long 0xE8 0.--31. 1. "GICD_ITARGETSR66,Interrupt Processor Targets Registers"
line.long 0xEC "GICD_ITARGETSR67,Interrupt Processor Targets Registers"
hexmask.long 0xEC 0.--31. 1. "GICD_ITARGETSR67,Interrupt Processor Targets Registers"
line.long 0xF0 "GICD_ITARGETSR68,Interrupt Processor Targets Registers"
hexmask.long 0xF0 0.--31. 1. "GICD_ITARGETSR68,Interrupt Processor Targets Registers"
line.long 0xF4 "GICD_ITARGETSR69,Interrupt Processor Targets Registers"
hexmask.long 0xF4 0.--31. 1. "GICD_ITARGETSR69,Interrupt Processor Targets Registers"
line.long 0xF8 "GICD_ITARGETSR70,Interrupt Processor Targets Registers"
hexmask.long 0xF8 0.--31. 1. "GICD_ITARGETSR70,Interrupt Processor Targets Registers"
line.long 0xFC "GICD_ITARGETSR71,Interrupt Processor Targets Registers"
hexmask.long 0xFC 0.--31. 1. "GICD_ITARGETSR71,Interrupt Processor Targets Registers"
line.long 0x100 "GICD_ITARGETSR72,Interrupt Processor Targets Registers"
hexmask.long 0x100 0.--31. 1. "GICD_ITARGETSR72,Interrupt Processor Targets Registers"
line.long 0x104 "GICD_ITARGETSR73,Interrupt Processor Targets Registers"
hexmask.long 0x104 0.--31. 1. "GICD_ITARGETSR73,Interrupt Processor Targets Registers"
line.long 0x108 "GICD_ITARGETSR74,Interrupt Processor Targets Registers"
hexmask.long 0x108 0.--31. 1. "GICD_ITARGETSR74,Interrupt Processor Targets Registers"
line.long 0x10C "GICD_ITARGETSR75,Interrupt Processor Targets Registers"
hexmask.long 0x10C 0.--31. 1. "GICD_ITARGETSR75,Interrupt Processor Targets Registers"
line.long 0x110 "GICD_ITARGETSR76,Interrupt Processor Targets Registers"
hexmask.long 0x110 0.--31. 1. "GICD_ITARGETSR76,Interrupt Processor Targets Registers"
line.long 0x114 "GICD_ITARGETSR77,Interrupt Processor Targets Registers"
hexmask.long 0x114 0.--31. 1. "GICD_ITARGETSR77,Interrupt Processor Targets Registers"
line.long 0x118 "GICD_ITARGETSR78,Interrupt Processor Targets Registers"
hexmask.long 0x118 0.--31. 1. "GICD_ITARGETSR78,Interrupt Processor Targets Registers"
line.long 0x11C "GICD_ITARGETSR79,Interrupt Processor Targets Registers"
hexmask.long 0x11C 0.--31. 1. "GICD_ITARGETSR79,Interrupt Processor Targets Registers"
line.long 0x120 "GICD_ITARGETSR80,Interrupt Processor Targets Registers"
hexmask.long 0x120 0.--31. 1. "GICD_ITARGETSR80,Interrupt Processor Targets Registers"
line.long 0x124 "GICD_ITARGETSR81,Interrupt Processor Targets Registers"
hexmask.long 0x124 0.--31. 1. "GICD_ITARGETSR81,Interrupt Processor Targets Registers"
line.long 0x128 "GICD_ITARGETSR82,Interrupt Processor Targets Registers"
hexmask.long 0x128 0.--31. 1. "GICD_ITARGETSR82,Interrupt Processor Targets Registers"
line.long 0x12C "GICD_ITARGETSR83,Interrupt Processor Targets Registers"
hexmask.long 0x12C 0.--31. 1. "GICD_ITARGETSR83,Interrupt Processor Targets Registers"
line.long 0x130 "GICD_ITARGETSR84,Interrupt Processor Targets Registers"
hexmask.long 0x130 0.--31. 1. "GICD_ITARGETSR84,Interrupt Processor Targets Registers"
line.long 0x134 "GICD_ITARGETSR85,Interrupt Processor Targets Registers"
hexmask.long 0x134 0.--31. 1. "GICD_ITARGETSR85,Interrupt Processor Targets Registers"
line.long 0x138 "GICD_ITARGETSR86,Interrupt Processor Targets Registers"
hexmask.long 0x138 0.--31. 1. "GICD_ITARGETSR86,Interrupt Processor Targets Registers"
line.long 0x13C "GICD_ITARGETSR87,Interrupt Processor Targets Registers"
hexmask.long 0x13C 0.--31. 1. "GICD_ITARGETSR87,Interrupt Processor Targets Registers"
line.long 0x140 "GICD_ITARGETSR88,Interrupt Processor Targets Registers"
hexmask.long 0x140 0.--31. 1. "GICD_ITARGETSR88,Interrupt Processor Targets Registers"
line.long 0x144 "GICD_ITARGETSR89,Interrupt Processor Targets Registers"
hexmask.long 0x144 0.--31. 1. "GICD_ITARGETSR89,Interrupt Processor Targets Registers"
line.long 0x148 "GICD_ITARGETSR90,Interrupt Processor Targets Registers"
hexmask.long 0x148 0.--31. 1. "GICD_ITARGETSR90,Interrupt Processor Targets Registers"
line.long 0x14C "GICD_ITARGETSR91,Interrupt Processor Targets Registers"
hexmask.long 0x14C 0.--31. 1. "GICD_ITARGETSR91,Interrupt Processor Targets Registers"
line.long 0x150 "GICD_ITARGETSR92,Interrupt Processor Targets Registers"
hexmask.long 0x150 0.--31. 1. "GICD_ITARGETSR92,Interrupt Processor Targets Registers"
line.long 0x154 "GICD_ITARGETSR93,Interrupt Processor Targets Registers"
hexmask.long 0x154 0.--31. 1. "GICD_ITARGETSR93,Interrupt Processor Targets Registers"
line.long 0x158 "GICD_ITARGETSR94,Interrupt Processor Targets Registers"
hexmask.long 0x158 0.--31. 1. "GICD_ITARGETSR94,Interrupt Processor Targets Registers"
line.long 0x15C "GICD_ITARGETSR95,Interrupt Processor Targets Registers"
hexmask.long 0x15C 0.--31. 1. "GICD_ITARGETSR95,Interrupt Processor Targets Registers"
line.long 0x160 "GICD_ITARGETSR96,Interrupt Processor Targets Registers"
hexmask.long 0x160 0.--31. 1. "GICD_ITARGETSR96,Interrupt Processor Targets Registers"
line.long 0x164 "GICD_ITARGETSR97,Interrupt Processor Targets Registers"
hexmask.long 0x164 0.--31. 1. "GICD_ITARGETSR97,Interrupt Processor Targets Registers"
line.long 0x168 "GICD_ITARGETSR98,Interrupt Processor Targets Registers"
hexmask.long 0x168 0.--31. 1. "GICD_ITARGETSR98,Interrupt Processor Targets Registers"
line.long 0x16C "GICD_ITARGETSR99,Interrupt Processor Targets Registers"
hexmask.long 0x16C 0.--31. 1. "GICD_ITARGETSR99,Interrupt Processor Targets Registers"
line.long 0x170 "GICD_ITARGETSR100,Interrupt Processor Targets Registers"
hexmask.long 0x170 0.--31. 1. "GICD_ITARGETSR100,Interrupt Processor Targets Registers"
line.long 0x174 "GICD_ITARGETSR101,Interrupt Processor Targets Registers"
hexmask.long 0x174 0.--31. 1. "GICD_ITARGETSR101,Interrupt Processor Targets Registers"
line.long 0x178 "GICD_ITARGETSR102,Interrupt Processor Targets Registers"
hexmask.long 0x178 0.--31. 1. "GICD_ITARGETSR102,Interrupt Processor Targets Registers"
line.long 0x17C "GICD_ITARGETSR103,Interrupt Processor Targets Registers"
hexmask.long 0x17C 0.--31. 1. "GICD_ITARGETSR103,Interrupt Processor Targets Registers"
line.long 0x180 "GICD_ITARGETSR104,Interrupt Processor Targets Registers"
hexmask.long 0x180 0.--31. 1. "GICD_ITARGETSR104,Interrupt Processor Targets Registers"
line.long 0x184 "GICD_ITARGETSR105,Interrupt Processor Targets Registers"
hexmask.long 0x184 0.--31. 1. "GICD_ITARGETSR105,Interrupt Processor Targets Registers"
line.long 0x188 "GICD_ITARGETSR106,Interrupt Processor Targets Registers"
hexmask.long 0x188 0.--31. 1. "GICD_ITARGETSR106,Interrupt Processor Targets Registers"
line.long 0x18C "GICD_ITARGETSR107,Interrupt Processor Targets Registers"
hexmask.long 0x18C 0.--31. 1. "GICD_ITARGETSR107,Interrupt Processor Targets Registers"
line.long 0x190 "GICD_ITARGETSR108,Interrupt Processor Targets Registers"
hexmask.long 0x190 0.--31. 1. "GICD_ITARGETSR108,Interrupt Processor Targets Registers"
line.long 0x194 "GICD_ITARGETSR109,Interrupt Processor Targets Registers"
hexmask.long 0x194 0.--31. 1. "GICD_ITARGETSR109,Interrupt Processor Targets Registers"
line.long 0x198 "GICD_ITARGETSR110,Interrupt Processor Targets Registers"
hexmask.long 0x198 0.--31. 1. "GICD_ITARGETSR110,Interrupt Processor Targets Registers"
line.long 0x19C "GICD_ITARGETSR111,Interrupt Processor Targets Registers"
hexmask.long 0x19C 0.--31. 1. "GICD_ITARGETSR111,Interrupt Processor Targets Registers"
line.long 0x1A0 "GICD_ITARGETSR112,Interrupt Processor Targets Registers"
hexmask.long 0x1A0 0.--31. 1. "GICD_ITARGETSR112,Interrupt Processor Targets Registers"
line.long 0x1A4 "GICD_ITARGETSR113,Interrupt Processor Targets Registers"
hexmask.long 0x1A4 0.--31. 1. "GICD_ITARGETSR113,Interrupt Processor Targets Registers"
line.long 0x1A8 "GICD_ITARGETSR114,Interrupt Processor Targets Registers"
hexmask.long 0x1A8 0.--31. 1. "GICD_ITARGETSR114,Interrupt Processor Targets Registers"
line.long 0x1AC "GICD_ITARGETSR115,Interrupt Processor Targets Registers"
hexmask.long 0x1AC 0.--31. 1. "GICD_ITARGETSR115,Interrupt Processor Targets Registers"
line.long 0x1B0 "GICD_ITARGETSR116,Interrupt Processor Targets Registers"
hexmask.long 0x1B0 0.--31. 1. "GICD_ITARGETSR116,Interrupt Processor Targets Registers"
line.long 0x1B4 "GICD_ITARGETSR117,Interrupt Processor Targets Registers"
hexmask.long 0x1B4 0.--31. 1. "GICD_ITARGETSR117,Interrupt Processor Targets Registers"
line.long 0x1B8 "GICD_ITARGETSR118,Interrupt Processor Targets Registers"
hexmask.long 0x1B8 0.--31. 1. "GICD_ITARGETSR118,Interrupt Processor Targets Registers"
line.long 0x1BC "GICD_ITARGETSR119,Interrupt Processor Targets Registers"
hexmask.long 0x1BC 0.--31. 1. "GICD_ITARGETSR119,Interrupt Processor Targets Registers"
line.long 0x1C0 "GICD_ITARGETSR120,Interrupt Processor Targets Registers"
hexmask.long 0x1C0 0.--31. 1. "GICD_ITARGETSR120,Interrupt Processor Targets Registers"
line.long 0x1C4 "GICD_ITARGETSR121,Interrupt Processor Targets Registers"
hexmask.long 0x1C4 0.--31. 1. "GICD_ITARGETSR121,Interrupt Processor Targets Registers"
line.long 0x1C8 "GICD_ITARGETSR122,Interrupt Processor Targets Registers"
hexmask.long 0x1C8 0.--31. 1. "GICD_ITARGETSR122,Interrupt Processor Targets Registers"
line.long 0x1CC "GICD_ITARGETSR123,Interrupt Processor Targets Registers"
hexmask.long 0x1CC 0.--31. 1. "GICD_ITARGETSR123,Interrupt Processor Targets Registers"
line.long 0x1D0 "GICD_ITARGETSR124,Interrupt Processor Targets Registers"
hexmask.long 0x1D0 0.--31. 1. "GICD_ITARGETSR124,Interrupt Processor Targets Registers"
line.long 0x1D4 "GICD_ITARGETSR125,Interrupt Processor Targets Registers"
hexmask.long 0x1D4 0.--31. 1. "GICD_ITARGETSR125,Interrupt Processor Targets Registers"
line.long 0x1D8 "GICD_ITARGETSR126,Interrupt Processor Targets Registers"
hexmask.long 0x1D8 0.--31. 1. "GICD_ITARGETSR126,Interrupt Processor Targets Registers"
line.long 0x1DC "GICD_ITARGETSR127,Interrupt Processor Targets Registers"
hexmask.long 0x1DC 0.--31. 1. "GICD_ITARGETSR127,Interrupt Processor Targets Registers"
rgroup.long 0xC00++0x7
line.long 0x0 "GICD_ICFGR0,Interrupt Configuration Registers"
hexmask.long 0x0 0.--31. 1. "GICD_ICFGR0,Interrupt Configuration Registers"
line.long 0x4 "GICD_ICFGR1,Interrupt Configuration Registers"
hexmask.long 0x4 0.--31. 1. "GICD_ICFGR1,Interrupt Configuration Registers"
group.long 0xC08++0x77
line.long 0x0 "GICD_ICFGR2,Interrupt Configuration Registers"
hexmask.long 0x0 0.--31. 1. "GICD_ICFGR2,Interrupt Configuration Registers"
line.long 0x4 "GICD_ICFGR3,Interrupt Configuration Registers"
hexmask.long 0x4 0.--31. 1. "GICD_ICFGR3,Interrupt Configuration Registers"
line.long 0x8 "GICD_ICFGR4,Interrupt Configuration Registers"
hexmask.long 0x8 0.--31. 1. "GICD_ICFGR4,Interrupt Configuration Registers"
line.long 0xC "GICD_ICFGR5,Interrupt Configuration Registers"
hexmask.long 0xC 0.--31. 1. "GICD_ICFGR5,Interrupt Configuration Registers"
line.long 0x10 "GICD_ICFGR6,Interrupt Configuration Registers"
hexmask.long 0x10 0.--31. 1. "GICD_ICFGR6,Interrupt Configuration Registers"
line.long 0x14 "GICD_ICFGR7,Interrupt Configuration Registers"
hexmask.long 0x14 0.--31. 1. "GICD_ICFGR7,Interrupt Configuration Registers"
line.long 0x18 "GICD_ICFGR8,Interrupt Configuration Registers"
hexmask.long 0x18 0.--31. 1. "GICD_ICFGR8,Interrupt Configuration Registers"
line.long 0x1C "GICD_ICFGR9,Interrupt Configuration Registers"
hexmask.long 0x1C 0.--31. 1. "GICD_ICFGR9,Interrupt Configuration Registers"
line.long 0x20 "GICD_ICFGR10,Interrupt Configuration Registers"
hexmask.long 0x20 0.--31. 1. "GICD_ICFGR10,Interrupt Configuration Registers"
line.long 0x24 "GICD_ICFGR11,Interrupt Configuration Registers"
hexmask.long 0x24 0.--31. 1. "GICD_ICFGR11,Interrupt Configuration Registers"
line.long 0x28 "GICD_ICFGR12,Interrupt Configuration Registers"
hexmask.long 0x28 0.--31. 1. "GICD_ICFGR12,Interrupt Configuration Registers"
line.long 0x2C "GICD_ICFGR13,Interrupt Configuration Registers"
hexmask.long 0x2C 0.--31. 1. "GICD_ICFGR13,Interrupt Configuration Registers"
line.long 0x30 "GICD_ICFGR14,Interrupt Configuration Registers"
hexmask.long 0x30 0.--31. 1. "GICD_ICFGR14,Interrupt Configuration Registers"
line.long 0x34 "GICD_ICFGR15,Interrupt Configuration Registers"
hexmask.long 0x34 0.--31. 1. "GICD_ICFGR15,Interrupt Configuration Registers"
line.long 0x38 "GICD_ICFGR16,Interrupt Configuration Registers"
hexmask.long 0x38 0.--31. 1. "GICD_ICFGR16,Interrupt Configuration Registers"
line.long 0x3C "GICD_ICFGR17,Interrupt Configuration Registers"
hexmask.long 0x3C 0.--31. 1. "GICD_ICFGR17,Interrupt Configuration Registers"
line.long 0x40 "GICD_ICFGR18,Interrupt Configuration Registers"
hexmask.long 0x40 0.--31. 1. "GICD_ICFGR18,Interrupt Configuration Registers"
line.long 0x44 "GICD_ICFGR19,Interrupt Configuration Registers"
hexmask.long 0x44 0.--31. 1. "GICD_ICFGR19,Interrupt Configuration Registers"
line.long 0x48 "GICD_ICFGR20,Interrupt Configuration Registers"
hexmask.long 0x48 0.--31. 1. "GICD_ICFGR20,Interrupt Configuration Registers"
line.long 0x4C "GICD_ICFGR21,Interrupt Configuration Registers"
hexmask.long 0x4C 0.--31. 1. "GICD_ICFGR21,Interrupt Configuration Registers"
line.long 0x50 "GICD_ICFGR22,Interrupt Configuration Registers"
hexmask.long 0x50 0.--31. 1. "GICD_ICFGR22,Interrupt Configuration Registers"
line.long 0x54 "GICD_ICFGR23,Interrupt Configuration Registers"
hexmask.long 0x54 0.--31. 1. "GICD_ICFGR23,Interrupt Configuration Registers"
line.long 0x58 "GICD_ICFGR24,Interrupt Configuration Registers"
hexmask.long 0x58 0.--31. 1. "GICD_ICFGR24,Interrupt Configuration Registers"
line.long 0x5C "GICD_ICFGR25,Interrupt Configuration Registers"
hexmask.long 0x5C 0.--31. 1. "GICD_ICFGR25,Interrupt Configuration Registers"
line.long 0x60 "GICD_ICFGR26,Interrupt Configuration Registers"
hexmask.long 0x60 0.--31. 1. "GICD_ICFGR26,Interrupt Configuration Registers"
line.long 0x64 "GICD_ICFGR27,Interrupt Configuration Registers"
hexmask.long 0x64 0.--31. 1. "GICD_ICFGR27,Interrupt Configuration Registers"
line.long 0x68 "GICD_ICFGR28,Interrupt Configuration Registers"
hexmask.long 0x68 0.--31. 1. "GICD_ICFGR28,Interrupt Configuration Registers"
line.long 0x6C "GICD_ICFGR29,Interrupt Configuration Registers"
hexmask.long 0x6C 0.--31. 1. "GICD_ICFGR29,Interrupt Configuration Registers"
line.long 0x70 "GICD_ICFGR30,Interrupt Configuration Registers"
hexmask.long 0x70 0.--31. 1. "GICD_ICFGR30,Interrupt Configuration Registers"
line.long 0x74 "GICD_ICFGR31,Interrupt Configuration Registers"
hexmask.long 0x74 0.--31. 1. "GICD_ICFGR31,Interrupt Configuration Registers"
rgroup.long 0xD00++0x3F
line.long 0x0 "GICD_PPISR,Private Peripheral Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICD_PPISR,Private Peripheral Interrupt Status Register"
line.long 0x4 "GICD_SPISR0,Shared Peripheral Interrupt Status Registers"
hexmask.long 0x4 0.--31. 1. "GICD_SPISR0,Shared Peripheral Interrupt Status Registers"
line.long 0x8 "GICD_SPISR1,Shared Peripheral Interrupt Status Registers"
hexmask.long 0x8 0.--31. 1. "GICD_SPISR1,Shared Peripheral Interrupt Status Registers"
line.long 0xC "GICD_SPISR2,Shared Peripheral Interrupt Status Registers"
hexmask.long 0xC 0.--31. 1. "GICD_SPISR2,Shared Peripheral Interrupt Status Registers"
line.long 0x10 "GICD_SPISR3,Shared Peripheral Interrupt Status Registers"
hexmask.long 0x10 0.--31. 1. "GICD_SPISR3,Shared Peripheral Interrupt Status Registers"
line.long 0x14 "GICD_SPISR4,Shared Peripheral Interrupt Status Registers"
hexmask.long 0x14 0.--31. 1. "GICD_SPISR4,Shared Peripheral Interrupt Status Registers"
line.long 0x18 "GICD_SPISR5,Shared Peripheral Interrupt Status Registers"
hexmask.long 0x18 0.--31. 1. "GICD_SPISR5,Shared Peripheral Interrupt Status Registers"
line.long 0x1C "GICD_SPISR6,Shared Peripheral Interrupt Status Registers"
hexmask.long 0x1C 0.--31. 1. "GICD_SPISR6,Shared Peripheral Interrupt Status Registers"
line.long 0x20 "GICD_SPISR7,Shared Peripheral Interrupt Status Registers"
hexmask.long 0x20 0.--31. 1. "GICD_SPISR7,Shared Peripheral Interrupt Status Registers"
line.long 0x24 "GICD_SPISR8,Shared Peripheral Interrupt Status Registers"
hexmask.long 0x24 0.--31. 1. "GICD_SPISR8,Shared Peripheral Interrupt Status Registers"
line.long 0x28 "GICD_SPISR9,Shared Peripheral Interrupt Status Registers"
hexmask.long 0x28 0.--31. 1. "GICD_SPISR9,Shared Peripheral Interrupt Status Registers"
line.long 0x2C "GICD_SPISR10,Shared Peripheral Interrupt Status Registers"
hexmask.long 0x2C 0.--31. 1. "GICD_SPISR10,Shared Peripheral Interrupt Status Registers"
line.long 0x30 "GICD_SPISR11,Shared Peripheral Interrupt Status Registers"
hexmask.long 0x30 0.--31. 1. "GICD_SPISR11,Shared Peripheral Interrupt Status Registers"
line.long 0x34 "GICD_SPISR12,Shared Peripheral Interrupt Status Registers"
hexmask.long 0x34 0.--31. 1. "GICD_SPISR12,Shared Peripheral Interrupt Status Registers"
line.long 0x38 "GICD_SPISR13,Shared Peripheral Interrupt Status Registers"
hexmask.long 0x38 0.--31. 1. "GICD_SPISR13,Shared Peripheral Interrupt Status Registers"
line.long 0x3C "GICD_SPISR14,Shared Peripheral Interrupt Status Registers"
hexmask.long 0x3C 0.--31. 1. "GICD_SPISR14,Shared Peripheral Interrupt Status Registers"
wgroup.long 0xF00++0x3
line.long 0x0 "GICD_SGIR,Software Generated Interrupt Register"
hexmask.long 0x0 0.--31. 1. "GICD_SGIR,Software Generated Interrupt Register"
group.long 0xF10++0x1F
line.long 0x0 "GICD_CPENDSGIR0,SGI Clear-Pending Registers"
hexmask.long 0x0 0.--31. 1. "GICD_CPENDSGIR0,SGI Clear-Pending Registers"
line.long 0x4 "GICD_CPENDSGIR1,SGI Clear-Pending Registers"
hexmask.long 0x4 0.--31. 1. "GICD_CPENDSGIR1,SGI Clear-Pending Registers"
line.long 0x8 "GICD_CPENDSGIR2,SGI Clear-Pending Registers"
hexmask.long 0x8 0.--31. 1. "GICD_CPENDSGIR2,SGI Clear-Pending Registers"
line.long 0xC "GICD_CPENDSGIR3,SGI Clear-Pending Registers"
hexmask.long 0xC 0.--31. 1. "GICD_CPENDSGIR3,SGI Clear-Pending Registers"
line.long 0x10 "GICD_SPENDSGIR0,SGI Set-Pending Registers"
hexmask.long 0x10 0.--31. 1. "GICD_SPENDSGIR0,SGI Set-Pending Registers"
line.long 0x14 "GICD_SPENDSGIR1,SGI Set-Pending Registers"
hexmask.long 0x14 0.--31. 1. "GICD_SPENDSGIR1,SGI Set-Pending Registers"
line.long 0x18 "GICD_SPENDSGIR2,SGI Set-Pending Registers"
hexmask.long 0x18 0.--31. 1. "GICD_SPENDSGIR2,SGI Set-Pending Registers"
line.long 0x1C "GICD_SPENDSGIR3,SGI Set-Pending Registers"
hexmask.long 0x1C 0.--31. 1. "GICD_SPENDSGIR3,SGI Set-Pending Registers"
rgroup.long 0xFD0++0x2F
line.long 0x0 "GICD_PIDR4,Peripheral ID4 Register"
hexmask.long 0x0 0.--31. 1. "GICD_PIDR4,Peripheral ID4 Register"
line.long 0x4 "GICD_PIDR5,Peripheral ID5 Register"
hexmask.long 0x4 0.--31. 1. "GICD_PIDR5,Peripheral ID5 Register"
line.long 0x8 "GICD_PIDR6,Peripheral ID6 Register"
hexmask.long 0x8 0.--31. 1. "GICD_PIDR6,Peripheral ID6 Register"
line.long 0xC "GICD_PIDR7,Peripheral ID7 Register"
hexmask.long 0xC 0.--31. 1. "GICD_PIDR7,Peripheral ID7 Register"
line.long 0x10 "GICD_PIDR0,Peripheral ID0 Register"
hexmask.long 0x10 0.--31. 1. "GICD_PIDR0,Peripheral ID0 Register"
line.long 0x14 "GICD_PIDR1,Peripheral ID1 Register"
hexmask.long 0x14 0.--31. 1. "GICD_PIDR1,Peripheral ID1 Register"
line.long 0x18 "GICD_PIDR2,Peripheral ID2 Register"
hexmask.long 0x18 0.--31. 1. "GICD_PIDR2,Peripheral ID2 Register"
line.long 0x1C "GICD_PIDR3,Peripheral ID3 Register"
hexmask.long 0x1C 0.--31. 1. "GICD_PIDR3,Peripheral ID3 Register"
line.long 0x20 "GICD_CIDR0,Component ID0 Register"
hexmask.long 0x20 0.--31. 1. "GICD_CIDR0,Component ID0 Register"
line.long 0x24 "GICD_CIDR1,Component ID1 Register"
hexmask.long 0x24 0.--31. 1. "GICD_CIDR1,Component ID1 Register"
line.long 0x28 "GICD_CIDR2,Component ID2 Register"
hexmask.long 0x28 0.--31. 1. "GICD_CIDR2,Component ID2 Register"
line.long 0x2C "GICD_CIDR3,Component ID3 Register"
hexmask.long 0x2C 0.--31. 1. "GICD_CIDR3,Component ID3 Register"
group.long 0x1000++0xB
line.long 0x0 "GICC_CTLR,CPU Interface Control Register"
hexmask.long 0x0 0.--31. 1. "GICC_CTLR,CPU Interface Control Register"
line.long 0x4 "GICC_PMR,Interrupt Priority Mask Register"
hexmask.long 0x4 0.--31. 1. "GICC_PMR,Interrupt Priority Mask Register"
line.long 0x8 "GICC_BPR,Binary Point Register"
hexmask.long 0x8 0.--31. 1. "GICC_BPR,Binary Point Register"
rgroup.long 0x100C++0x3
line.long 0x0 "GICC_IAR,Interrupt Acknowledge Register"
hexmask.long 0x0 0.--31. 1. "GICC_IAR,Interrupt Acknowledge Register"
wgroup.long 0x1010++0x3
line.long 0x0 "GICC_EOIR,End of Interrupt Register"
hexmask.long 0x0 0.--31. 1. "GICC_EOIR,End of Interrupt Register"
rgroup.long 0x1014++0x7
line.long 0x0 "GICC_RPR,Running Priority Register"
hexmask.long 0x0 0.--31. 1. "GICC_RPR,Running Priority Register"
line.long 0x4 "GICC_HPPIR,Highest Priority Pending Interrupt Register"
hexmask.long 0x4 0.--31. 1. "GICC_HPPIR,Highest Priority Pending Interrupt Register"
group.long 0x101C++0x3
line.long 0x0 "GICC_ABPR,Aliased Binary Point Register"
hexmask.long 0x0 0.--31. 1. "GICC_ABPR,Aliased Binary Point Register"
rgroup.long 0x1020++0x3
line.long 0x0 "GICC_AIAR,Aliased Interrupt Acknowledge Register"
hexmask.long 0x0 0.--31. 1. "GICC_AIAR,Aliased Interrupt Acknowledge Register"
wgroup.long 0x1024++0x3
line.long 0x0 "GICC_AEOIR,Aliased End of Interrupt Register"
hexmask.long 0x0 0.--31. 1. "GICC_AEOIR,Aliased End of Interrupt Register"
rgroup.long 0x1028++0x3
line.long 0x0 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register"
hexmask.long 0x0 0.--31. 1. "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register"
group.long 0x10D0++0x3
line.long 0x0 "GICC_APR0,Active Priority Register"
hexmask.long 0x0 0.--31. 1. "GICC_APR0,Active Priority Register"
group.long 0x10E0++0x3
line.long 0x0 "GICC_NSAPR0,Non-Secure Active Priority Register"
hexmask.long 0x0 0.--31. 1. "GICC_NSAPR0,Non-Secure Active Priority Register"
rgroup.long 0x10FC++0x3
line.long 0x0 "GICC_IIDR,CPU Interface Identification Register"
hexmask.long 0x0 0.--31. 1. "GICC_IIDR,CPU Interface Identification Register"
wgroup.long 0x2000++0x3
line.long 0x0 "GICC_DIR,Deactivate Interrupt Register"
hexmask.long 0x0 0.--31. 1. "GICC_DIR,Deactivate Interrupt Register"
group.long 0x3000++0x3
line.long 0x0 "GICH_HCR,Hypervisor Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_HCR,Hypervisor Control Register"
rgroup.long 0x3004++0x3
line.long 0x0 "GICH_VTR,VGIC Type Register"
hexmask.long 0x0 0.--31. 1. "GICH_VTR,VGIC Type Register"
group.long 0x3008++0x3
line.long 0x0 "GICH_VMCR,Virtual Machine Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_VMCR,Virtual Machine Control Register"
rgroup.long 0x3010++0x3
line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_MISR,Maintenance Interrupt Status Register"
rgroup.long 0x3020++0x3
line.long 0x0 "GICH_EISR0,End of Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_EISR0,End of Interrupt Status Register"
rgroup.long 0x3030++0x3
line.long 0x0 "GICH_ELSR0,Empty List register Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_ELSR0,Empty List register Status Register"
group.long 0x30F0++0x3
line.long 0x0 "GICH_APR0,Active Priority Register"
hexmask.long 0x0 0.--31. 1. "GICH_APR0,Active Priority Register"
group.long 0x3100++0xF
line.long 0x0 "GICH_LR0,List Register 0"
hexmask.long 0x0 0.--31. 1. "GICH_LR0,List Register 0"
line.long 0x4 "GICH_LR1,List Register 1"
hexmask.long 0x4 0.--31. 1. "GICH_LR1,List Register 1"
line.long 0x8 "GICH_LR2,List Register 2"
hexmask.long 0x8 0.--31. 1. "GICH_LR2,List Register 2"
line.long 0xC "GICH_LR3,List Register 3"
hexmask.long 0xC 0.--31. 1. "GICH_LR3,List Register 3"
group.long 0x4000++0x3
line.long 0x0 "GICH_HCR,Hypervisor Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_HCR,Hypervisor Control Register"
rgroup.long 0x4004++0x3
line.long 0x0 "GICH_VTR,VGIC Type Register"
hexmask.long 0x0 0.--31. 1. "GICH_VTR,VGIC Type Register"
group.long 0x4008++0x3
line.long 0x0 "GICH_VMCR,Virtual Machine Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_VMCR,Virtual Machine Control Register"
rgroup.long 0x4010++0x3
line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_MISR,Maintenance Interrupt Status Register"
rgroup.long 0x4020++0x3
line.long 0x0 "GICH_EISR0,End of Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_EISR0,End of Interrupt Status Register"
rgroup.long 0x4030++0x3
line.long 0x0 "GICH_ELSR0,Empty List register Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_ELSR0,Empty List register Status Register"
group.long 0x40F0++0x3
line.long 0x0 "GICH_APR0,Active Priority Register"
hexmask.long 0x0 0.--31. 1. "GICH_APR0,Active Priority Register"
group.long 0x4100++0xF
line.long 0x0 "GICH_LR0,List Register 0"
hexmask.long 0x0 0.--31. 1. "GICH_LR0,List Register 0"
line.long 0x4 "GICH_LR1,List Register 1"
hexmask.long 0x4 0.--31. 1. "GICH_LR1,List Register 1"
line.long 0x8 "GICH_LR2,List Register 2"
hexmask.long 0x8 0.--31. 1. "GICH_LR2,List Register 2"
line.long 0xC "GICH_LR3,List Register 3"
hexmask.long 0xC 0.--31. 1. "GICH_LR3,List Register 3"
group.long 0x4200++0x3
line.long 0x0 "GICH_HCR,Hypervisor Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_HCR,Hypervisor Control Register"
rgroup.long 0x4204++0x3
line.long 0x0 "GICH_VTR,VGIC Type Register"
hexmask.long 0x0 0.--31. 1. "GICH_VTR,VGIC Type Register"
group.long 0x4208++0x3
line.long 0x0 "GICH_VMCR,Virtual Machine Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_VMCR,Virtual Machine Control Register"
rgroup.long 0x4210++0x3
line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_MISR,Maintenance Interrupt Status Register"
rgroup.long 0x4220++0x3
line.long 0x0 "GICH_EISR0,End of Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_EISR0,End of Interrupt Status Register"
rgroup.long 0x4230++0x3
line.long 0x0 "GICH_ELSR0,Empty List register Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_ELSR0,Empty List register Status Register"
group.long 0x42F0++0x3
line.long 0x0 "GICH_APR0,Active Priority Register"
hexmask.long 0x0 0.--31. 1. "GICH_APR0,Active Priority Register"
group.long 0x4300++0xF
line.long 0x0 "GICH_LR0,List Register 0"
hexmask.long 0x0 0.--31. 1. "GICH_LR0,List Register 0"
line.long 0x4 "GICH_LR1,List Register 1"
hexmask.long 0x4 0.--31. 1. "GICH_LR1,List Register 1"
line.long 0x8 "GICH_LR2,List Register 2"
hexmask.long 0x8 0.--31. 1. "GICH_LR2,List Register 2"
line.long 0xC "GICH_LR3,List Register 3"
hexmask.long 0xC 0.--31. 1. "GICH_LR3,List Register 3"
group.long 0x4400++0x3
line.long 0x0 "GICH_HCR,Hypervisor Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_HCR,Hypervisor Control Register"
rgroup.long 0x4404++0x3
line.long 0x0 "GICH_VTR,VGIC Type Register"
hexmask.long 0x0 0.--31. 1. "GICH_VTR,VGIC Type Register"
group.long 0x4408++0x3
line.long 0x0 "GICH_VMCR,Virtual Machine Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_VMCR,Virtual Machine Control Register"
rgroup.long 0x4410++0x3
line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_MISR,Maintenance Interrupt Status Register"
rgroup.long 0x4420++0x3
line.long 0x0 "GICH_EISR0,End of Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_EISR0,End of Interrupt Status Register"
rgroup.long 0x4430++0x3
line.long 0x0 "GICH_ELSR0,Empty List register Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_ELSR0,Empty List register Status Register"
group.long 0x44F0++0x3
line.long 0x0 "GICH_APR0,Active Priority Register"
hexmask.long 0x0 0.--31. 1. "GICH_APR0,Active Priority Register"
group.long 0x4500++0xF
line.long 0x0 "GICH_LR0,List Register 0"
hexmask.long 0x0 0.--31. 1. "GICH_LR0,List Register 0"
line.long 0x4 "GICH_LR1,List Register 1"
hexmask.long 0x4 0.--31. 1. "GICH_LR1,List Register 1"
line.long 0x8 "GICH_LR2,List Register 2"
hexmask.long 0x8 0.--31. 1. "GICH_LR2,List Register 2"
line.long 0xC "GICH_LR3,List Register 3"
hexmask.long 0xC 0.--31. 1. "GICH_LR3,List Register 3"
group.long 0x4600++0x3
line.long 0x0 "GICH_HCR,Hypervisor Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_HCR,Hypervisor Control Register"
rgroup.long 0x4604++0x3
line.long 0x0 "GICH_VTR,VGIC Type Register"
hexmask.long 0x0 0.--31. 1. "GICH_VTR,VGIC Type Register"
group.long 0x4608++0x3
line.long 0x0 "GICH_VMCR,Virtual Machine Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_VMCR,Virtual Machine Control Register"
rgroup.long 0x4610++0x3
line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_MISR,Maintenance Interrupt Status Register"
rgroup.long 0x4620++0x3
line.long 0x0 "GICH_EISR0,End of Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_EISR0,End of Interrupt Status Register"
rgroup.long 0x4630++0x3
line.long 0x0 "GICH_ELSR0,Empty List register Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_ELSR0,Empty List register Status Register"
group.long 0x46F0++0x3
line.long 0x0 "GICH_APR0,Active Priority Register"
hexmask.long 0x0 0.--31. 1. "GICH_APR0,Active Priority Register"
group.long 0x4700++0xF
line.long 0x0 "GICH_LR0,List Register 0"
hexmask.long 0x0 0.--31. 1. "GICH_LR0,List Register 0"
line.long 0x4 "GICH_LR1,List Register 1"
hexmask.long 0x4 0.--31. 1. "GICH_LR1,List Register 1"
line.long 0x8 "GICH_LR2,List Register 2"
hexmask.long 0x8 0.--31. 1. "GICH_LR2,List Register 2"
line.long 0xC "GICH_LR3,List Register 3"
hexmask.long 0xC 0.--31. 1. "GICH_LR3,List Register 3"
group.long 0x4800++0x3
line.long 0x0 "GICH_HCR,Hypervisor Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_HCR,Hypervisor Control Register"
rgroup.long 0x4804++0x3
line.long 0x0 "GICH_VTR,VGIC Type Register"
hexmask.long 0x0 0.--31. 1. "GICH_VTR,VGIC Type Register"
group.long 0x4808++0x3
line.long 0x0 "GICH_VMCR,Virtual Machine Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_VMCR,Virtual Machine Control Register"
rgroup.long 0x4810++0x3
line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_MISR,Maintenance Interrupt Status Register"
rgroup.long 0x4820++0x3
line.long 0x0 "GICH_EISR0,End of Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_EISR0,End of Interrupt Status Register"
rgroup.long 0x4830++0x3
line.long 0x0 "GICH_ELSR0,Empty List register Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_ELSR0,Empty List register Status Register"
group.long 0x48F0++0x3
line.long 0x0 "GICH_APR0,Active Priority Register"
hexmask.long 0x0 0.--31. 1. "GICH_APR0,Active Priority Register"
group.long 0x4900++0xF
line.long 0x0 "GICH_LR0,List Register 0"
hexmask.long 0x0 0.--31. 1. "GICH_LR0,List Register 0"
line.long 0x4 "GICH_LR1,List Register 1"
hexmask.long 0x4 0.--31. 1. "GICH_LR1,List Register 1"
line.long 0x8 "GICH_LR2,List Register 2"
hexmask.long 0x8 0.--31. 1. "GICH_LR2,List Register 2"
line.long 0xC "GICH_LR3,List Register 3"
hexmask.long 0xC 0.--31. 1. "GICH_LR3,List Register 3"
group.long 0x4A00++0x3
line.long 0x0 "GICH_HCR,Hypervisor Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_HCR,Hypervisor Control Register"
rgroup.long 0x4A04++0x3
line.long 0x0 "GICH_VTR,VGIC Type Register"
hexmask.long 0x0 0.--31. 1. "GICH_VTR,VGIC Type Register"
group.long 0x4A08++0x3
line.long 0x0 "GICH_VMCR,Virtual Machine Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_VMCR,Virtual Machine Control Register"
rgroup.long 0x4A10++0x3
line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_MISR,Maintenance Interrupt Status Register"
rgroup.long 0x4A20++0x3
line.long 0x0 "GICH_EISR0,End of Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_EISR0,End of Interrupt Status Register"
rgroup.long 0x4A30++0x3
line.long 0x0 "GICH_ELSR0,Empty List register Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_ELSR0,Empty List register Status Register"
group.long 0x4AF0++0x3
line.long 0x0 "GICH_APR0,Active Priority Register"
hexmask.long 0x0 0.--31. 1. "GICH_APR0,Active Priority Register"
group.long 0x4B00++0xF
line.long 0x0 "GICH_LR0,List Register 0"
hexmask.long 0x0 0.--31. 1. "GICH_LR0,List Register 0"
line.long 0x4 "GICH_LR1,List Register 1"
hexmask.long 0x4 0.--31. 1. "GICH_LR1,List Register 1"
line.long 0x8 "GICH_LR2,List Register 2"
hexmask.long 0x8 0.--31. 1. "GICH_LR2,List Register 2"
line.long 0xC "GICH_LR3,List Register 3"
hexmask.long 0xC 0.--31. 1. "GICH_LR3,List Register 3"
group.long 0x4C00++0x3
line.long 0x0 "GICH_HCR,Hypervisor Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_HCR,Hypervisor Control Register"
rgroup.long 0x4C04++0x3
line.long 0x0 "GICH_VTR,VGIC Type Register"
hexmask.long 0x0 0.--31. 1. "GICH_VTR,VGIC Type Register"
group.long 0x4C08++0x3
line.long 0x0 "GICH_VMCR,Virtual Machine Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_VMCR,Virtual Machine Control Register"
rgroup.long 0x4C10++0x3
line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_MISR,Maintenance Interrupt Status Register"
rgroup.long 0x4C20++0x3
line.long 0x0 "GICH_EISR0,End of Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_EISR0,End of Interrupt Status Register"
rgroup.long 0x4C30++0x3
line.long 0x0 "GICH_ELSR0,Empty List register Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_ELSR0,Empty List register Status Register"
group.long 0x4CF0++0x3
line.long 0x0 "GICH_APR0,Active Priority Register"
hexmask.long 0x0 0.--31. 1. "GICH_APR0,Active Priority Register"
group.long 0x4D00++0xF
line.long 0x0 "GICH_LR0,List Register 0"
hexmask.long 0x0 0.--31. 1. "GICH_LR0,List Register 0"
line.long 0x4 "GICH_LR1,List Register 1"
hexmask.long 0x4 0.--31. 1. "GICH_LR1,List Register 1"
line.long 0x8 "GICH_LR2,List Register 2"
hexmask.long 0x8 0.--31. 1. "GICH_LR2,List Register 2"
line.long 0xC "GICH_LR3,List Register 3"
hexmask.long 0xC 0.--31. 1. "GICH_LR3,List Register 3"
group.long 0x4E00++0x3
line.long 0x0 "GICH_HCR,Hypervisor Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_HCR,Hypervisor Control Register"
rgroup.long 0x4E04++0x3
line.long 0x0 "GICH_VTR,VGIC Type Register"
hexmask.long 0x0 0.--31. 1. "GICH_VTR,VGIC Type Register"
group.long 0x4E08++0x3
line.long 0x0 "GICH_VMCR,Virtual Machine Control Register"
hexmask.long 0x0 0.--31. 1. "GICH_VMCR,Virtual Machine Control Register"
rgroup.long 0x4E10++0x3
line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_MISR,Maintenance Interrupt Status Register"
rgroup.long 0x4E20++0x3
line.long 0x0 "GICH_EISR0,End of Interrupt Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_EISR0,End of Interrupt Status Register"
rgroup.long 0x4E30++0x3
line.long 0x0 "GICH_ELSR0,Empty List register Status Register"
hexmask.long 0x0 0.--31. 1. "GICH_ELSR0,Empty List register Status Register"
group.long 0x4EF0++0x3
line.long 0x0 "GICH_APR0,Active Priority Register"
hexmask.long 0x0 0.--31. 1. "GICH_APR0,Active Priority Register"
group.long 0x4F00++0xF
line.long 0x0 "GICH_LR0,List Register 0"
hexmask.long 0x0 0.--31. 1. "GICH_LR0,List Register 0"
line.long 0x4 "GICH_LR1,List Register 1"
hexmask.long 0x4 0.--31. 1. "GICH_LR1,List Register 1"
line.long 0x8 "GICH_LR2,List Register 2"
hexmask.long 0x8 0.--31. 1. "GICH_LR2,List Register 2"
line.long 0xC "GICH_LR3,List Register 3"
hexmask.long 0xC 0.--31. 1. "GICH_LR3,List Register 3"
group.long 0x5000++0xB
line.long 0x0 "GICV_CTLR,Virtual Machine Control Register"
hexmask.long 0x0 0.--31. 1. "GICV_CTLR,Virtual Machine Control Register"
line.long 0x4 "GICV_PMR,VM Priority Mask Register"
hexmask.long 0x4 0.--31. 1. "GICV_PMR,VM Priority Mask Register"
line.long 0x8 "GICV_BPR,VM Binary Point Register"
hexmask.long 0x8 0.--31. 1. "GICV_BPR,VM Binary Point Register"
rgroup.long 0x500C++0x3
line.long 0x0 "GICV_IAR,VM Interrupt Acknowledge Register"
hexmask.long 0x0 0.--31. 1. "GICV_IAR,VM Interrupt Acknowledge Register"
wgroup.long 0x5010++0x3
line.long 0x0 "GICV_EOIR,VM End of Interrupt Register"
hexmask.long 0x0 0.--31. 1. "GICV_EOIR,VM End of Interrupt Register"
rgroup.long 0x5014++0x7
line.long 0x0 "GICV_RPR,VM Running Priority Register"
hexmask.long 0x0 0.--31. 1. "GICV_RPR,VM Running Priority Register"
line.long 0x4 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register"
hexmask.long 0x4 0.--31. 1. "GICV_HPPIR,VM Highest Priority Pending Interrupt Register"
group.long 0x501C++0x3
line.long 0x0 "GICV_ABPR,VM Aliased Binary Point Register"
hexmask.long 0x0 0.--31. 1. "GICV_ABPR,VM Aliased Binary Point Register"
rgroup.long 0x5020++0x3
line.long 0x0 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register"
hexmask.long 0x0 0.--31. 1. "GICV_AIAR,VM Aliased Interrupt Acknowledge Register"
wgroup.long 0x5024++0x3
line.long 0x0 "GICV_AEOIR,VM Aliased End of Interrupt Register"
hexmask.long 0x0 0.--31. 1. "GICV_AEOIR,VM Aliased End of Interrupt Register"
rgroup.long 0x5028++0x3
line.long 0x0 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register"
hexmask.long 0x0 0.--31. 1. "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register"
group.long 0x50D0++0x3
line.long 0x0 "GICV_APR0,VM Active Priority Register"
hexmask.long 0x0 0.--31. 1. "GICV_APR0,VM Active Priority Register"
rgroup.long 0x50FC++0x3
line.long 0x0 "GICV_IIDR,VM CPU Interface Identification Register"
hexmask.long 0x0 0.--31. 1. "GICV_IIDR,VM CPU Interface Identification Register"
wgroup.long 0x6000++0x3
line.long 0x0 "GICV_DIR,VM Deactivate Interrupt Register"
hexmask.long 0x0 0.--31. 1. "GICV_DIR,VM Deactivate Interrupt Register"
tree.end
tree "GPIO (General Purpose I/O)"
base ad:0x0
tree "GPIO0 (GPIO0 Module)"
base ad:0xFFC03200
group.long 0x0++0x7
line.long 0x0 "GPIO_SWPORTA_DR,Name: Port A data register"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_SWPORTA_DR,Values written to this register are output on the I/O signals"
line.long 0x4 "GPIO_SWPORTA_DDR,Name: Port A Data Direction Register"
hexmask.long.tbyte 0x4 0.--23. 1. "GPIO_SWPORTA_DDR,Values written to this register independently control the"
group.long 0x30++0xF
line.long 0x0 "GPIO_INTEN,Name: Interrupt enable register"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_INTEN,Allows each bit of Port A to be configured for interrupts. By"
line.long 0x4 "GPIO_INTMASK,Name: Interrupt mask register"
hexmask.long.tbyte 0x4 0.--23. 1. "GPIO_INTMASK,Controls whether an interrupt on Port A can create an"
line.long 0x8 "GPIO_INTTYPE_LEVEL,Name: Interrupt level"
hexmask.long.tbyte 0x8 0.--23. 1. "GPIO_INTTYPE_LEVEL,Controls the type of interrupt that can occur on Port A."
line.long 0xC "GPIO_INT_POLARITY,Name: Interrupt polarity"
hexmask.long.tbyte 0xC 0.--23. 1. "GPIO_INT_POLARITY,Controls the polarity of edge or level sensitivity that can"
rgroup.long 0x40++0x7
line.long 0x0 "GPIO_INTSTATUS,Name: Interrupt status"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_INTSTATUS,Interrupt status of Port A."
line.long 0x4 "GPIO_RAW_INTSTATUS,Name: Raw interrupt status"
hexmask.long.tbyte 0x4 0.--23. 1. "GPIO_RAW_INTSTATUS,Raw interrupt of status of Port A (premasking bits)"
group.long 0x48++0x3
line.long 0x0 "GPIO_DEBOUNCE,Name: Debounce enable"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_DEBOUNCE,Controls whether an external signal that is the source"
wgroup.long 0x4C++0x3
line.long 0x0 "GPIO_PORTA_EOI,Name: Port A clear interrupt register"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_PORTA_EOI,Controls the clearing of edge type interrupts from Port A."
rgroup.long 0x50++0x3
line.long 0x0 "GPIO_EXT_PORTA,Name: Port A external port register"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_EXT_PORTA,This register always reflects the signals value on the External Port A."
group.long 0x60++0x3
line.long 0x0 "GPIO_LS_SYNC,Name: Synchronization level"
bitfld.long 0x0 0. "GPIO_LS_SYNC,Writing a 1 to this register results in all level-sensitive interrupts being" "0,1"
rgroup.long 0x64++0x3
line.long 0x0 "GPIO_ID_CODE,Name: GPIO ID code"
hexmask.long 0x0 0.--31. 1. "GPIO_ID_CODE,This is a user-specified code that a system can read. It can"
rgroup.long 0x6C++0xB
line.long 0x0 "GPIO_VER_ID_CODE,Name: GPIO Component Version"
hexmask.long 0x0 0.--31. 1. "GPIO_VER_ID_CODE,ASCII value for each number in the version."
line.long 0x4 "GPIO_CONFIG_REG2,Name: GPIO Configuration Register 2"
hexmask.long.byte 0x4 15.--19. 1. "ENCODED_ID_PWIDTH_D,The value of this register is derived from the"
hexmask.long.byte 0x4 10.--14. 1. "ENCODED_ID_PWIDTH_C,The value of this register is derived from the"
hexmask.long.byte 0x4 5.--9. 1. "ENCODED_ID_PWIDTH_B,The value of this register is derived from the"
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hexmask.long.byte 0x4 0.--4. 1. "ENCODED_ID_PWIDTH_A,The value of this register is derived from the"
line.long 0x8 "GPIO_CONFIG_REG1,Name: GPIO Configuration Register 1"
bitfld.long 0x8 21. "INTERRUPT_BOTH_EDGE_TYPE,The value of this register is derived from the" "0,1"
hexmask.long.byte 0x8 16.--20. 1. "ENCODED_ID_WIDTH,The value of this register is derived from the"
bitfld.long 0x8 15. "GPIO_ID,The value of this register is derived from the" "0: Exclude,1: Include"
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bitfld.long 0x8 14. "ADD_ENCODED_PARAMS,The value of this register is derived from the" "0: False,1: True"
bitfld.long 0x8 13. "DEBOUNCE,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 12. "PORTA_INTR,The value of this register is derived from the" "0: Exclude,1: Include"
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bitfld.long 0x8 11. "HW_PORTD,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 10. "HW_PORTC,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 9. "HW_PORTB,The value of this register is derived from the" "0: Exclude,1: Include"
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bitfld.long 0x8 8. "HW_PORTA,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 7. "PORTD_SINGLE_CTL,The value of this register is derived from the" "0: False,1: True"
bitfld.long 0x8 6. "PORTC_SINGLE_CTL,The value of this register is derived from the" "0: False,1: True"
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bitfld.long 0x8 5. "PORTB_SINGLE_CTL,The value of this register is derived from the" "0: False,1: True"
bitfld.long 0x8 4. "PORTA_SINGLE_CTL,The value of this register is derived from the" "0: False,1: True"
bitfld.long 0x8 2.--3. "NUM_PORTS,The value of this register is derived from the" "0: 1,1: 2,2: 3,3: 4"
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bitfld.long 0x8 0.--1. "APB_DATA_WIDTH,The value of this register is derived from the" "0: 8 bits,1: 16 bits,2: 32 bits,3: Reserved"
tree.end
tree "GPIO1 (GPIO1 Module)"
base ad:0xFFC03300
group.long 0x0++0x7
line.long 0x0 "GPIO_SWPORTA_DR,Name: Port A data register"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_SWPORTA_DR,Values written to this register are output on the I/O signals"
line.long 0x4 "GPIO_SWPORTA_DDR,Name: Port A Data Direction Register"
hexmask.long.tbyte 0x4 0.--23. 1. "GPIO_SWPORTA_DDR,Values written to this register independently control the"
group.long 0x30++0xF
line.long 0x0 "GPIO_INTEN,Name: Interrupt enable register"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_INTEN,Allows each bit of Port A to be configured for interrupts. By"
line.long 0x4 "GPIO_INTMASK,Name: Interrupt mask register"
hexmask.long.tbyte 0x4 0.--23. 1. "GPIO_INTMASK,Controls whether an interrupt on Port A can create an"
line.long 0x8 "GPIO_INTTYPE_LEVEL,Name: Interrupt level"
hexmask.long.tbyte 0x8 0.--23. 1. "GPIO_INTTYPE_LEVEL,Controls the type of interrupt that can occur on Port A."
line.long 0xC "GPIO_INT_POLARITY,Name: Interrupt polarity"
hexmask.long.tbyte 0xC 0.--23. 1. "GPIO_INT_POLARITY,Controls the polarity of edge or level sensitivity that can"
rgroup.long 0x40++0x7
line.long 0x0 "GPIO_INTSTATUS,Name: Interrupt status"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_INTSTATUS,Interrupt status of Port A."
line.long 0x4 "GPIO_RAW_INTSTATUS,Name: Raw interrupt status"
hexmask.long.tbyte 0x4 0.--23. 1. "GPIO_RAW_INTSTATUS,Raw interrupt of status of Port A (premasking bits)"
group.long 0x48++0x3
line.long 0x0 "GPIO_DEBOUNCE,Name: Debounce enable"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_DEBOUNCE,Controls whether an external signal that is the source"
wgroup.long 0x4C++0x3
line.long 0x0 "GPIO_PORTA_EOI,Name: Port A clear interrupt register"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_PORTA_EOI,Controls the clearing of edge type interrupts from Port A."
rgroup.long 0x50++0x3
line.long 0x0 "GPIO_EXT_PORTA,Name: Port A external port register"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_EXT_PORTA,This register always reflects the signals value on the External Port A."
group.long 0x60++0x3
line.long 0x0 "GPIO_LS_SYNC,Name: Synchronization level"
bitfld.long 0x0 0. "GPIO_LS_SYNC,Writing a 1 to this register results in all level-sensitive interrupts being" "0,1"
rgroup.long 0x64++0x3
line.long 0x0 "GPIO_ID_CODE,Name: GPIO ID code"
hexmask.long 0x0 0.--31. 1. "GPIO_ID_CODE,This is a user-specified code that a system can read. It can"
rgroup.long 0x6C++0xB
line.long 0x0 "GPIO_VER_ID_CODE,Name: GPIO Component Version"
hexmask.long 0x0 0.--31. 1. "GPIO_VER_ID_CODE,ASCII value for each number in the version."
line.long 0x4 "GPIO_CONFIG_REG2,Name: GPIO Configuration Register 2"
hexmask.long.byte 0x4 15.--19. 1. "ENCODED_ID_PWIDTH_D,The value of this register is derived from the"
hexmask.long.byte 0x4 10.--14. 1. "ENCODED_ID_PWIDTH_C,The value of this register is derived from the"
hexmask.long.byte 0x4 5.--9. 1. "ENCODED_ID_PWIDTH_B,The value of this register is derived from the"
newline
hexmask.long.byte 0x4 0.--4. 1. "ENCODED_ID_PWIDTH_A,The value of this register is derived from the"
line.long 0x8 "GPIO_CONFIG_REG1,Name: GPIO Configuration Register 1"
bitfld.long 0x8 21. "INTERRUPT_BOTH_EDGE_TYPE,The value of this register is derived from the" "0,1"
hexmask.long.byte 0x8 16.--20. 1. "ENCODED_ID_WIDTH,The value of this register is derived from the"
bitfld.long 0x8 15. "GPIO_ID,The value of this register is derived from the" "0: Exclude,1: Include"
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bitfld.long 0x8 14. "ADD_ENCODED_PARAMS,The value of this register is derived from the" "0: False,1: True"
bitfld.long 0x8 13. "DEBOUNCE,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 12. "PORTA_INTR,The value of this register is derived from the" "0: Exclude,1: Include"
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bitfld.long 0x8 11. "HW_PORTD,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 10. "HW_PORTC,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 9. "HW_PORTB,The value of this register is derived from the" "0: Exclude,1: Include"
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bitfld.long 0x8 8. "HW_PORTA,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 7. "PORTD_SINGLE_CTL,The value of this register is derived from the" "0: False,1: True"
bitfld.long 0x8 6. "PORTC_SINGLE_CTL,The value of this register is derived from the" "0: False,1: True"
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bitfld.long 0x8 5. "PORTB_SINGLE_CTL,The value of this register is derived from the" "0: False,1: True"
bitfld.long 0x8 4. "PORTA_SINGLE_CTL,The value of this register is derived from the" "0: False,1: True"
bitfld.long 0x8 2.--3. "NUM_PORTS,The value of this register is derived from the" "0: 1,1: 2,2: 3,3: 4"
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bitfld.long 0x8 0.--1. "APB_DATA_WIDTH,The value of this register is derived from the" "0: 8 bits,1: 16 bits,2: 32 bits,3: Reserved"
tree.end
tree.end
tree "I2C (Inter Integrated Circuit)"
base ad:0x0
tree "I2C0 (I2C0 Module)"
base ad:0xFFC02800
group.long 0x0++0xB
line.long 0x0 "IC_CON,Name: I2C Control Register"
hexmask.long.word 0x0 20.--31. 1. "RSVD_IC_CON_2,Reserved bits - Read Only"
newline
rbitfld.long 0x0 19. "RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 18. "RSVD_SMBUS_ARP_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_QUICK_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 16. "RSVD_OPTIONAL_SAR_CTRL,Reserved bits - Read Only" "0,1"
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hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_CON_1,Reserved bits - Read Only"
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rbitfld.long 0x0 11. "RSVD_BUS_CLEAR_FEATURE_CTRL,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 10. "STOP_DET_IF_MASTER_ACTIVE,In Master mode:" "0: issues the STOP_DET irrespective of whether..,1: issues the STOP_DET interrupt only when master.."
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rbitfld.long 0x0 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether" "0,1"
newline
bitfld.long 0x0 8. "TX_EMPTY_CTRL,This bit controls the generation" "0,1"
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bitfld.long 0x0 7. "STOP_DET_IFADDRESSED,In slave mode:" "0: issues the STOP_DET irrespective of whether it's..,1: issues the STOP_DET interrrupt only when it is.."
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bitfld.long 0x0 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled " "0: slave is enabled,1: slave is disabled"
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bitfld.long 0x0 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when" "0: disable,1: enable"
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rbitfld.long 0x0 4. "IC_10BITADDR_MASTER_rd_only,If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 3. "IC_10BITADDR_SLAVE,When acting as a slave  this bit controls whether the DW_apb_i2c" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates; its" "?,1: standard mode,2: fast mode,3: high speed mode"
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bitfld.long 0x0 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled." "0: master disabled,1: master enabled"
line.long 0x4 "IC_TAR,Name: I2C Target Address Register"
hexmask.long.word 0x4 17.--31. 1. "RSVD_IC_TAR_2,Reserved bits - Read Only"
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rbitfld.long 0x4 16. "RSVD_SMBUS_QUICK_CMD,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x4 14.--15. "RSVD_IC_TAR_1,Reserved bits - Read Only" "0,1,2,3"
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rbitfld.long 0x4 13. "RSVD_DEVICE_ID,Reserved bits - Read Only" "0,1"
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bitfld.long 0x4 12. "IC_10BITADDR_MASTER,This bit controls whether the DW_apb_i2c starts its transfers in 7-" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x4 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or" "0: ignore bit 10 GC_OR_START and use IC_TAR normally,1: perform special I2C command as specified in.."
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bitfld.long 0x4 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0  then this bit indicates whether a" "0: General Call Address after issuing a General Call,1: START BYTE"
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hexmask.long.word 0x4 0.--9. 1. "IC_TAR,This is the target address for any master transaction. When"
line.long 0x8 "IC_SAR,Name: I2C Slave Address Register"
hexmask.long.tbyte 0x8 10.--31. 1. "RSVD_IC_SAR,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit"
group.long 0x10++0x13
line.long 0x0 "IC_DATA_CMD,Name: I2C Rx/Tx Data Buffer and Command Register;"
hexmask.long.tbyte 0x0 12.--31. 1. "RSVD_IC_DATA_CMD,Reserved bits - Read Only"
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rbitfld.long 0x0 11. "FIRST_DATA_BYTE,Indicates the first data byte" "0,1"
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bitfld.long 0x0 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received." "0,1"
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bitfld.long 0x0 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received." "0,1"
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bitfld.long 0x0 8. "CMD,This bit controls whether a read or a write is performed." "0: Write,1: Read"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus."
line.long 0x4 "IC_SS_SCL_HCNT,Name: Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x4 16.--31. 1. "RSVD_IC_SS_SCL_HIGH_COUNT,Reserved bits - Read Only"
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hexmask.long.word 0x4 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x8 "IC_SS_SCL_LCNT,Name: Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x8 16.--31. 1. "RSVD_IC_SS_SCL_LOW_COUNT,Reserved bits - Read Only"
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hexmask.long.word 0x8 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0xC "IC_FS_SCL_HCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"
hexmask.long.word 0xC 16.--31. 1. "RSVD_IC_FS_SCL_HCNT,Reserved bits - Read Only"
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hexmask.long.word 0xC 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x10 "IC_FS_SCL_LCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"
hexmask.long.word 0x10 16.--31. 1. "RSVD_IC_FS_SCL_LCNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x10 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0x2C++0x3
line.long 0x0 "IC_INTR_STAT,Name: I2C Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "RSVD_R_SCL_STUCK_AT_LOW,Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT number of ic_clk periods." "0,1"
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bitfld.long 0x0 13. "R_MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
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bitfld.long 0x0 12. "R_RESTART_DET,Indicates a RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
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bitfld.long 0x0 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 9. "R_STOP_DET,The behavior of the STOP_DET interrupt status differs based on the" "0: Indicates whether a STOP condition has occurred..,1: In Master Mode"
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bitfld.long 0x0 8. "R_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
newline
bitfld.long 0x0 7. "R_RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "R_TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
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bitfld.long 0x0 5. "R_RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
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bitfld.long 0x0 4. "R_TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the" "0: This bit is set to 1 when the transmit buffer is..,1: This bit is set to 1 when the transmit buffer is.."
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bitfld.long 0x0 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
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bitfld.long 0x0 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
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bitfld.long 0x0 1. "R_RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
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bitfld.long 0x0 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x30++0x3
line.long 0x0 "IC_INTR_MASK,Name: I2C Interrupt Mask Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
newline
rbitfld.long 0x0 14. "RSVD_M_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 13. "M_MASTER_ON_HOLD,This bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register." "0,1"
rgroup.long 0x34++0x3
line.long 0x0 "IC_RAW_INTR_STAT,Name: I2C Raw Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_RAW_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "RSVD_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 13. "MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
newline
bitfld.long 0x0 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface" "0,1"
newline
bitfld.long 0x0 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
newline
bitfld.long 0x0 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 9. "STOP_DET,Indicates whether a STOP condition" "0,1"
newline
bitfld.long 0x0 8. "RAW_INTR_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
newline
bitfld.long 0x0 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
newline
bitfld.long 0x0 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
newline
bitfld.long 0x0 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status" "0: This bit is set to 1 when the transmit buffer..,1: This bit is set to 1 when the transmit buffer.."
newline
bitfld.long 0x0 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
newline
bitfld.long 0x0 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
newline
bitfld.long 0x0 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
newline
bitfld.long 0x0 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x38++0x7
line.long 0x0 "IC_RX_TL,Name: I2C Receive FIFO Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_RX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "RX_TL,Receive FIFO Threshold Level"
line.long 0x4 "IC_TX_TL,Name: I2C Transmit FIFO Threshold Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IC_TX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level"
rgroup.long 0x40++0x2B
line.long 0x0 "IC_CLR_INTR,Name: Clear Combined and Individual Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_INTR,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_INTR,Read this register to clear the combined interrupt " "0,1"
line.long 0x4 "IC_CLR_RX_UNDER,Name: Clear RX_UNDER Interrupt Register"
hexmask.long 0x4 1.--31. 1. "RSVD_IC_CLR_RX_UNDER,Reserved bits - Read Only"
newline
bitfld.long 0x4 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER" "0,1"
line.long 0x8 "IC_CLR_RX_OVER,Name: Clear RX_OVER Interrupt Register"
hexmask.long 0x8 1.--31. 1. "RSVD_IC_CLR_RX_OVER,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "CLR_RX_OVER,Read this register to clear the RX_OVER" "0,1"
line.long 0xC "IC_CLR_TX_OVER,Name: Clear TX_OVER Interrupt Register"
hexmask.long 0xC 1.--31. 1. "RSVD_IC_CLR_TX_OVER,Reserved bits - Read Only"
newline
bitfld.long 0xC 0. "CLR_TX_OVER,Read this register to clear the TX_OVER" "0,1"
line.long 0x10 "IC_CLR_RD_REQ,Name: Clear RD_REQ Interrupt Register"
hexmask.long 0x10 1.--31. 1. "RSVD_IC_CLR_RD_REQ,Reserved bits - Read Only"
newline
bitfld.long 0x10 0. "CLR_RD_REQ,Read this register to clear the RD_REQ" "0,1"
line.long 0x14 "IC_CLR_TX_ABRT,Name: Clear TX_ABRT Interrupt Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_CLR_TX_ABRT,Reserved bits - Read Only"
newline
bitfld.long 0x14 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT" "0,1"
line.long 0x18 "IC_CLR_RX_DONE,Name: Clear RX_DONE Interrupt Register"
hexmask.long 0x18 1.--31. 1. "RSVD_IC_CLR_RX_DONE,Reserved bits - Read Only"
newline
bitfld.long 0x18 0. "CLR_RX_DONE,Read this register to clear the RX_DONE" "0,1"
line.long 0x1C "IC_CLR_ACTIVITY,Name: Clear ACTIVITY Interrupt Register"
hexmask.long 0x1C 1.--31. 1. "RSVD_IC_CLR_ACTIVITY,Reserved bits - Read Only"
newline
bitfld.long 0x1C 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY" "0,1"
line.long 0x20 "IC_CLR_STOP_DET,Name: Clear STOP_DET Interrupt Register"
hexmask.long 0x20 1.--31. 1. "RSVD_IC_CLR_STOP_DET,Reserved bits - Read Only"
newline
bitfld.long 0x20 0. "CLR_STOP_DET,Read this register to clear the STOP_DET" "0,1"
line.long 0x24 "IC_CLR_START_DET,Name: Clear START_DET Interrupt Register"
hexmask.long 0x24 1.--31. 1. "RSVD_IC_CLR_START_DET,Reserved bits - Read Only"
newline
bitfld.long 0x24 0. "CLR_START_DET,Read this register to clear the START_DET" "0,1"
line.long 0x28 "IC_CLR_GEN_CALL,Name: Clear GEN_CALL Interrupt Register"
hexmask.long 0x28 1.--31. 1. "RSVD_IC_CLR_GEN_CALL,Reserved bits - Read Only"
newline
bitfld.long 0x28 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL" "0,1"
group.long 0x6C++0x3
line.long 0x0 "IC_ENABLE,Name: I2C Enable Register"
hexmask.long.word 0x0 19.--31. 1. "RSVD_IC_ENABLE_2,Reserved bits - Read Only"
newline
rbitfld.long 0x0 18. "RSVD_SMBUS_ALERT_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 17. "RSVD_SMBUS_SUSPEND_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 16. "RSVD_SMBUS_CLK_RESET,Reserved bits - Read Only" "0,1"
newline
hexmask.long.word 0x0 4.--15. 1. "RSVD_IC_ENABLE_1,Reserved bits - Read Only"
newline
rbitfld.long 0x0 3. "RSVD_SDA_STUCK_RECOVERY_ENABLE,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 2. "TX_CMD_BLOCK,In Master mode" "0,1"
newline
bitfld.long 0x0 1. "ABORT,When set  the controller initiates the transfer abort." "0: ABORT not initiated or ABORT done,1: ABORT operation in progress"
newline
bitfld.long 0x0 0. "ENABLE,Controls whether the DW_apb_i2c is enabled." "0: Disables DW_apb_i2c,1: Enables DW_apb_i2c"
rgroup.long 0x70++0xB
line.long 0x0 "IC_STATUS,Name: I2C Status Register"
hexmask.long.word 0x0 21.--31. 1. "RSVD_IC_STATUS_2,Reserved bits - Read Only"
newline
bitfld.long 0x0 20. "RSVD_SMBUS_ALERT_STATUS,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 19. "RSVD_SMBUS_SUSPEND_STATUS,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 18. "RSVD_SMBUS_SLAVE_ADDR_RESOLVED,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_ADDR_VALID,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 16. "RSVD_SMBUS_QUICK_CMD_BIT,Reserved bits - Read Only" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_STATUS_1,Reserved bits - Read Only"
newline
bitfld.long 0x0 11. "RSVD_SDA_STUCK_NOT_RECOVERED,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 10. "RSVD_SLV_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 9. "RSVD_SLV_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 8. "RSVD_MST_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 7. "RSVD_MST_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 6. "SLV_ACTIVITY,Slave FSM Activity Status." "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave part"
newline
bitfld.long 0x0 5. "MST_ACTIVITY,Master FSM Activity Status." "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
newline
bitfld.long 0x0 4. "RFF,Receive FIFO Completely Full." "0: Receive FIFO is not full,1: Receive FIFO is full"
newline
bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
newline
bitfld.long 0x0 2. "TFE,Transmit FIFO Completely Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
newline
bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
newline
bitfld.long 0x0 0. "IC_STATUS_ACTIVITY,I2C Activity Status." "0,1"
line.long 0x4 "IC_TXFLR,Name: I2C Transmit FIFO Level Register"
hexmask.long 0x4 7.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--6. 1. "TXFLR,Transmit FIFO Level."
line.long 0x8 "IC_RXFLR,Name: I2C Receive FIFO Level Register"
hexmask.long 0x8 7.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x8 0.--6. 1. "RXFLR,Receive FIFO Level."
group.long 0x7C++0x3
line.long 0x0 "IC_SDA_HOLD,Name: I2C SDA Hold Time Length Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_SDA_HOLD,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time"
newline
hexmask.long.word 0x0 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time"
rgroup.long 0x80++0x3
line.long 0x0 "IC_TX_ABRT_SOURCE,Name: I2C Transmit Abort Source Register"
hexmask.long.word 0x0 23.--31. 1. "TX_FLUSH_CNT,This field indicates the"
newline
bitfld.long 0x0 21.--22. "RSVD_IC_TX_ABRT_SOURCE,Reserved bits - Read Only" "0,1,2,3"
newline
bitfld.long 0x0 18.--20. "RSVD_ABRT_DEVICE_WRITE,Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 17. "RSVD_ABRT_SDA_STUCK_AT_LOW," "0,1"
newline
bitfld.long 0x0 16. "ABRT_USER_ABRT,This is a master-mode-only bit. Master has" "0,1"
newline
bitfld.long 0x0 15. "ABRT_SLVRD_INTX,1: When the processor side responds to" "?,1: When the processor side responds to"
newline
bitfld.long 0x0 14. "ABRT_SLV_ARBLOST,1: Slave lost the bus while transmitting" "?,1: Slave lost the bus while transmitting"
newline
bitfld.long 0x0 13. "ABRT_SLVFLUSH_TXFIFO,1: Slave has received a read command" "?,1: Slave has received a read command"
newline
bitfld.long 0x0 12. "ARB_LOST,1: Master has lost arbitration  or if" "?,1: Master has lost arbitration"
newline
bitfld.long 0x0 11. "ABRT_MASTER_DIS,1: User tries to initiate a Master" "?,1: User tries to initiate a Master"
newline
bitfld.long 0x0 10. "ABRT_10B_RD_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
newline
bitfld.long 0x0 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9  the source of the" "?,1: The restart is disabled"
newline
bitfld.long 0x0 8. "ABRT_HS_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
newline
bitfld.long 0x0 7. "ABRT_SBYTE_ACKDET,1: Master has sent a START Byte and" "?,1: Master has sent a START Byte and"
newline
bitfld.long 0x0 6. "ABRT_HS_ACKDET,1: Master is in High Speed mode and" "?,1: Master is in High Speed mode and"
newline
bitfld.long 0x0 5. "ABRT_GCALL_READ,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
newline
bitfld.long 0x0 4. "ABRT_GCALL_NOACK,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
newline
bitfld.long 0x0 3. "ABRT_TXDATA_NOACK,1: This is a master-mode only bit." "?,1: This is a master-mode only bit"
newline
bitfld.long 0x0 2. "ABRT_10ADDR2_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
newline
bitfld.long 0x0 1. "ABRT_10ADDR1_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
newline
bitfld.long 0x0 0. "ABRT_7B_ADDR_NOACK,1: Master is in 7-bit addressing mode" "?,1: Master is in 7-bit addressing mode"
group.long 0x84++0x17
line.long 0x0 "IC_SLV_DATA_NACK_ONLY,Name: Generate Slave Data NACK Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_SLV_DATA_NACK_ONLY,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "NACK,Generate NACK." "0: generate NACK/ACK normally,1: generate NACK after data byte received"
line.long 0x4 "IC_DMA_CR,Name: DMA Control Register"
hexmask.long 0x4 2.--31. 1. "RSVD_IC_DMA_CR_2_31,Reserved bits [31:1] - Read Only"
newline
bitfld.long 0x4 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
newline
bitfld.long 0x4 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x8 "IC_DMA_TDLR,Name: DMA Transmit Data Level Register"
hexmask.long 0x8 6.--31. 1. "RSVD_DMA_TDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x8 0.--5. 1. "DMATDL,Transmit Data Level."
line.long 0xC "IC_DMA_RDLR,Name: I2C Receive Data Level Register"
hexmask.long 0xC 6.--31. 1. "RSVD_DMA_RDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0xC 0.--5. 1. "DMARDL,Receive Data Level."
line.long 0x10 "IC_SDA_SETUP,Name: I2C SDA Setup Register"
hexmask.long.tbyte 0x10 8.--31. 1. "RSVD_IC_SDA_SETUP,Reserved bits - Read Only"
newline
hexmask.long.byte 0x10 0.--7. 1. "SDA_SETUP,SDA Setup."
line.long 0x14 "IC_ACK_GENERAL_CALL,Name: I2C ACK General Call Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_ACK_GEN_1_31,Reserved bits [31:1] - Read Only"
newline
bitfld.long 0x14 0. "ACK_GEN_CALL,ACK General Call." "0,1"
rgroup.long 0x9C++0x3
line.long 0x0 "IC_ENABLE_STATUS,Name: I2C Enable Status Register"
hexmask.long 0x0 3.--31. 1. "RSVD_IC_ENABLE_STATUS,Reserved bits - Read Only"
newline
bitfld.long 0x0 2. "SLV_RX_DATA_LOST,Slave Received Data Lost." "0,1"
newline
bitfld.long 0x0 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit  Receive)." "0,1"
newline
bitfld.long 0x0 0. "IC_EN,ic_en Status." "0,1"
group.long 0xA0++0x3
line.long 0x0 "IC_FS_SPKLEN,Name: I2C SS. FS or FM+ spike suppression limit"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_FS_SPKLEN,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0xA8++0x3
line.long 0x0 "IC_CLR_RESTART_DET,Name: Clear RESTART_DET Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_RESTART_DET,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "IC_COMP_PARAM_1,Name: Component Parameter Register 1"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_COMP_PARAM_1,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 16.--23. 1. "TX_BUFFER_DEPTH,The value of this register is derived"
newline
hexmask.long.byte 0x0 8.--15. 1. "RX_BUFFER_DEPTH,The value of this register is"
newline
bitfld.long 0x0 7. "ADD_ENCODED_PARAMS,The value of this register is derived" "0: False,1: True"
newline
bitfld.long 0x0 6. "HAS_DMA,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 5. "INTR_IO,The value of this register is" "0: Individual,1: Combined"
newline
bitfld.long 0x0 4. "HC_COUNT_VALUES,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 2.--3. "MAX_SPEED_MODE,The value of this register is" "0: Reserved,1: Standard,2: Fast,3: High"
newline
bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,The value of this register is" "0: 8 bits,1: 16 bits,2: 32 bits,3: Reserved"
line.long 0x4 "IC_COMP_VERSION,Name: I2C Component Version Register"
hexmask.long 0x4 0.--31. 1. "IC_COMP_VERSION,Specific values for this register are"
line.long 0x8 "IC_COMP_TYPE,Name: I2C Component Type Register"
hexmask.long 0x8 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number"
tree.end
tree "I2C1 (I2C1 Module)"
base ad:0xFFC02900
group.long 0x0++0xB
line.long 0x0 "IC_CON,Name: I2C Control Register"
hexmask.long.word 0x0 20.--31. 1. "RSVD_IC_CON_2,Reserved bits - Read Only"
newline
rbitfld.long 0x0 19. "RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 18. "RSVD_SMBUS_ARP_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_QUICK_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 16. "RSVD_OPTIONAL_SAR_CTRL,Reserved bits - Read Only" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_CON_1,Reserved bits - Read Only"
newline
rbitfld.long 0x0 11. "RSVD_BUS_CLEAR_FEATURE_CTRL,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 10. "STOP_DET_IF_MASTER_ACTIVE,In Master mode:" "0: issues the STOP_DET irrespective of whether..,1: issues the STOP_DET interrupt only when master.."
newline
rbitfld.long 0x0 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether" "0,1"
newline
bitfld.long 0x0 8. "TX_EMPTY_CTRL,This bit controls the generation" "0,1"
newline
bitfld.long 0x0 7. "STOP_DET_IFADDRESSED,In slave mode:" "0: issues the STOP_DET irrespective of whether it's..,1: issues the STOP_DET interrrupt only when it is.."
newline
bitfld.long 0x0 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled " "0: slave is enabled,1: slave is disabled"
newline
bitfld.long 0x0 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when" "0: disable,1: enable"
newline
rbitfld.long 0x0 4. "IC_10BITADDR_MASTER_rd_only,If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.long 0x0 3. "IC_10BITADDR_SLAVE,When acting as a slave  this bit controls whether the DW_apb_i2c" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.long 0x0 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates; its" "?,1: standard mode,2: fast mode,3: high speed mode"
newline
bitfld.long 0x0 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled." "0: master disabled,1: master enabled"
line.long 0x4 "IC_TAR,Name: I2C Target Address Register"
hexmask.long.word 0x4 17.--31. 1. "RSVD_IC_TAR_2,Reserved bits - Read Only"
newline
rbitfld.long 0x4 16. "RSVD_SMBUS_QUICK_CMD,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x4 14.--15. "RSVD_IC_TAR_1,Reserved bits - Read Only" "0,1,2,3"
newline
rbitfld.long 0x4 13. "RSVD_DEVICE_ID,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x4 12. "IC_10BITADDR_MASTER,This bit controls whether the DW_apb_i2c starts its transfers in 7-" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x4 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or" "0: ignore bit 10 GC_OR_START and use IC_TAR normally,1: perform special I2C command as specified in.."
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bitfld.long 0x4 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0  then this bit indicates whether a" "0: General Call Address after issuing a General Call,1: START BYTE"
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hexmask.long.word 0x4 0.--9. 1. "IC_TAR,This is the target address for any master transaction. When"
line.long 0x8 "IC_SAR,Name: I2C Slave Address Register"
hexmask.long.tbyte 0x8 10.--31. 1. "RSVD_IC_SAR,Reserved bits - Read Only"
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hexmask.long.word 0x8 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit"
group.long 0x10++0x13
line.long 0x0 "IC_DATA_CMD,Name: I2C Rx/Tx Data Buffer and Command Register;"
hexmask.long.tbyte 0x0 12.--31. 1. "RSVD_IC_DATA_CMD,Reserved bits - Read Only"
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rbitfld.long 0x0 11. "FIRST_DATA_BYTE,Indicates the first data byte" "0,1"
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bitfld.long 0x0 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received." "0,1"
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bitfld.long 0x0 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received." "0,1"
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bitfld.long 0x0 8. "CMD,This bit controls whether a read or a write is performed." "0: Write,1: Read"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus."
line.long 0x4 "IC_SS_SCL_HCNT,Name: Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x4 16.--31. 1. "RSVD_IC_SS_SCL_HIGH_COUNT,Reserved bits - Read Only"
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hexmask.long.word 0x4 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x8 "IC_SS_SCL_LCNT,Name: Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x8 16.--31. 1. "RSVD_IC_SS_SCL_LOW_COUNT,Reserved bits - Read Only"
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hexmask.long.word 0x8 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0xC "IC_FS_SCL_HCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"
hexmask.long.word 0xC 16.--31. 1. "RSVD_IC_FS_SCL_HCNT,Reserved bits - Read Only"
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hexmask.long.word 0xC 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x10 "IC_FS_SCL_LCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"
hexmask.long.word 0x10 16.--31. 1. "RSVD_IC_FS_SCL_LCNT,Reserved bits - Read Only"
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hexmask.long.word 0x10 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0x2C++0x3
line.long 0x0 "IC_INTR_STAT,Name: I2C Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
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bitfld.long 0x0 14. "RSVD_R_SCL_STUCK_AT_LOW,Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT number of ic_clk periods." "0,1"
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bitfld.long 0x0 13. "R_MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
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bitfld.long 0x0 12. "R_RESTART_DET,Indicates a RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
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bitfld.long 0x0 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 9. "R_STOP_DET,The behavior of the STOP_DET interrupt status differs based on the" "0: Indicates whether a STOP condition has occurred..,1: In Master Mode"
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bitfld.long 0x0 8. "R_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
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bitfld.long 0x0 7. "R_RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
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bitfld.long 0x0 6. "R_TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
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bitfld.long 0x0 5. "R_RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
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bitfld.long 0x0 4. "R_TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the" "0: This bit is set to 1 when the transmit buffer is..,1: This bit is set to 1 when the transmit buffer is.."
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bitfld.long 0x0 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
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bitfld.long 0x0 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
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bitfld.long 0x0 1. "R_RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
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bitfld.long 0x0 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x30++0x3
line.long 0x0 "IC_INTR_MASK,Name: I2C Interrupt Mask Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
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rbitfld.long 0x0 14. "RSVD_M_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 13. "M_MASTER_ON_HOLD,This bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register." "0,1"
rgroup.long 0x34++0x3
line.long 0x0 "IC_RAW_INTR_STAT,Name: I2C Raw Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_RAW_INTR_STAT,Reserved bits - Read Only"
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bitfld.long 0x0 14. "RSVD_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 13. "MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
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bitfld.long 0x0 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface" "0,1"
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bitfld.long 0x0 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
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bitfld.long 0x0 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 9. "STOP_DET,Indicates whether a STOP condition" "0,1"
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bitfld.long 0x0 8. "RAW_INTR_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
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bitfld.long 0x0 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
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bitfld.long 0x0 6. "TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
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bitfld.long 0x0 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
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bitfld.long 0x0 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status" "0: This bit is set to 1 when the transmit buffer..,1: This bit is set to 1 when the transmit buffer.."
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bitfld.long 0x0 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
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bitfld.long 0x0 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
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bitfld.long 0x0 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
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bitfld.long 0x0 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x38++0x7
line.long 0x0 "IC_RX_TL,Name: I2C Receive FIFO Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_RX_TL,Reserved bits - Read Only"
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hexmask.long.byte 0x0 0.--7. 1. "RX_TL,Receive FIFO Threshold Level"
line.long 0x4 "IC_TX_TL,Name: I2C Transmit FIFO Threshold Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IC_TX_TL,Reserved bits - Read Only"
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hexmask.long.byte 0x4 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level"
rgroup.long 0x40++0x2B
line.long 0x0 "IC_CLR_INTR,Name: Clear Combined and Individual Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_INTR,Reserved bits - Read Only"
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bitfld.long 0x0 0. "CLR_INTR,Read this register to clear the combined interrupt " "0,1"
line.long 0x4 "IC_CLR_RX_UNDER,Name: Clear RX_UNDER Interrupt Register"
hexmask.long 0x4 1.--31. 1. "RSVD_IC_CLR_RX_UNDER,Reserved bits - Read Only"
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bitfld.long 0x4 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER" "0,1"
line.long 0x8 "IC_CLR_RX_OVER,Name: Clear RX_OVER Interrupt Register"
hexmask.long 0x8 1.--31. 1. "RSVD_IC_CLR_RX_OVER,Reserved bits - Read Only"
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bitfld.long 0x8 0. "CLR_RX_OVER,Read this register to clear the RX_OVER" "0,1"
line.long 0xC "IC_CLR_TX_OVER,Name: Clear TX_OVER Interrupt Register"
hexmask.long 0xC 1.--31. 1. "RSVD_IC_CLR_TX_OVER,Reserved bits - Read Only"
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bitfld.long 0xC 0. "CLR_TX_OVER,Read this register to clear the TX_OVER" "0,1"
line.long 0x10 "IC_CLR_RD_REQ,Name: Clear RD_REQ Interrupt Register"
hexmask.long 0x10 1.--31. 1. "RSVD_IC_CLR_RD_REQ,Reserved bits - Read Only"
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bitfld.long 0x10 0. "CLR_RD_REQ,Read this register to clear the RD_REQ" "0,1"
line.long 0x14 "IC_CLR_TX_ABRT,Name: Clear TX_ABRT Interrupt Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_CLR_TX_ABRT,Reserved bits - Read Only"
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bitfld.long 0x14 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT" "0,1"
line.long 0x18 "IC_CLR_RX_DONE,Name: Clear RX_DONE Interrupt Register"
hexmask.long 0x18 1.--31. 1. "RSVD_IC_CLR_RX_DONE,Reserved bits - Read Only"
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bitfld.long 0x18 0. "CLR_RX_DONE,Read this register to clear the RX_DONE" "0,1"
line.long 0x1C "IC_CLR_ACTIVITY,Name: Clear ACTIVITY Interrupt Register"
hexmask.long 0x1C 1.--31. 1. "RSVD_IC_CLR_ACTIVITY,Reserved bits - Read Only"
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bitfld.long 0x1C 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY" "0,1"
line.long 0x20 "IC_CLR_STOP_DET,Name: Clear STOP_DET Interrupt Register"
hexmask.long 0x20 1.--31. 1. "RSVD_IC_CLR_STOP_DET,Reserved bits - Read Only"
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bitfld.long 0x20 0. "CLR_STOP_DET,Read this register to clear the STOP_DET" "0,1"
line.long 0x24 "IC_CLR_START_DET,Name: Clear START_DET Interrupt Register"
hexmask.long 0x24 1.--31. 1. "RSVD_IC_CLR_START_DET,Reserved bits - Read Only"
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bitfld.long 0x24 0. "CLR_START_DET,Read this register to clear the START_DET" "0,1"
line.long 0x28 "IC_CLR_GEN_CALL,Name: Clear GEN_CALL Interrupt Register"
hexmask.long 0x28 1.--31. 1. "RSVD_IC_CLR_GEN_CALL,Reserved bits - Read Only"
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bitfld.long 0x28 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL" "0,1"
group.long 0x6C++0x3
line.long 0x0 "IC_ENABLE,Name: I2C Enable Register"
hexmask.long.word 0x0 19.--31. 1. "RSVD_IC_ENABLE_2,Reserved bits - Read Only"
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rbitfld.long 0x0 18. "RSVD_SMBUS_ALERT_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 17. "RSVD_SMBUS_SUSPEND_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 16. "RSVD_SMBUS_CLK_RESET,Reserved bits - Read Only" "0,1"
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hexmask.long.word 0x0 4.--15. 1. "RSVD_IC_ENABLE_1,Reserved bits - Read Only"
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rbitfld.long 0x0 3. "RSVD_SDA_STUCK_RECOVERY_ENABLE,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 2. "TX_CMD_BLOCK,In Master mode" "0,1"
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bitfld.long 0x0 1. "ABORT,When set  the controller initiates the transfer abort." "0: ABORT not initiated or ABORT done,1: ABORT operation in progress"
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bitfld.long 0x0 0. "ENABLE,Controls whether the DW_apb_i2c is enabled." "0: Disables DW_apb_i2c,1: Enables DW_apb_i2c"
rgroup.long 0x70++0xB
line.long 0x0 "IC_STATUS,Name: I2C Status Register"
hexmask.long.word 0x0 21.--31. 1. "RSVD_IC_STATUS_2,Reserved bits - Read Only"
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bitfld.long 0x0 20. "RSVD_SMBUS_ALERT_STATUS,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 19. "RSVD_SMBUS_SUSPEND_STATUS,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 18. "RSVD_SMBUS_SLAVE_ADDR_RESOLVED,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_ADDR_VALID,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 16. "RSVD_SMBUS_QUICK_CMD_BIT,Reserved bits - Read Only" "0,1"
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hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_STATUS_1,Reserved bits - Read Only"
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bitfld.long 0x0 11. "RSVD_SDA_STUCK_NOT_RECOVERED,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 10. "RSVD_SLV_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 9. "RSVD_SLV_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 8. "RSVD_MST_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 7. "RSVD_MST_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 6. "SLV_ACTIVITY,Slave FSM Activity Status." "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave part"
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bitfld.long 0x0 5. "MST_ACTIVITY,Master FSM Activity Status." "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
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bitfld.long 0x0 4. "RFF,Receive FIFO Completely Full." "0: Receive FIFO is not full,1: Receive FIFO is full"
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bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
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bitfld.long 0x0 2. "TFE,Transmit FIFO Completely Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
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bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 0. "IC_STATUS_ACTIVITY,I2C Activity Status." "0,1"
line.long 0x4 "IC_TXFLR,Name: I2C Transmit FIFO Level Register"
hexmask.long 0x4 7.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
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hexmask.long.byte 0x4 0.--6. 1. "TXFLR,Transmit FIFO Level."
line.long 0x8 "IC_RXFLR,Name: I2C Receive FIFO Level Register"
hexmask.long 0x8 7.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
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hexmask.long.byte 0x8 0.--6. 1. "RXFLR,Receive FIFO Level."
group.long 0x7C++0x3
line.long 0x0 "IC_SDA_HOLD,Name: I2C SDA Hold Time Length Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_SDA_HOLD,Reserved bits - Read Only"
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hexmask.long.byte 0x0 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time"
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hexmask.long.word 0x0 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time"
rgroup.long 0x80++0x3
line.long 0x0 "IC_TX_ABRT_SOURCE,Name: I2C Transmit Abort Source Register"
hexmask.long.word 0x0 23.--31. 1. "TX_FLUSH_CNT,This field indicates the"
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bitfld.long 0x0 21.--22. "RSVD_IC_TX_ABRT_SOURCE,Reserved bits - Read Only" "0,1,2,3"
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bitfld.long 0x0 18.--20. "RSVD_ABRT_DEVICE_WRITE,Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 17. "RSVD_ABRT_SDA_STUCK_AT_LOW," "0,1"
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bitfld.long 0x0 16. "ABRT_USER_ABRT,This is a master-mode-only bit. Master has" "0,1"
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bitfld.long 0x0 15. "ABRT_SLVRD_INTX,1: When the processor side responds to" "?,1: When the processor side responds to"
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bitfld.long 0x0 14. "ABRT_SLV_ARBLOST,1: Slave lost the bus while transmitting" "?,1: Slave lost the bus while transmitting"
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bitfld.long 0x0 13. "ABRT_SLVFLUSH_TXFIFO,1: Slave has received a read command" "?,1: Slave has received a read command"
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bitfld.long 0x0 12. "ARB_LOST,1: Master has lost arbitration  or if" "?,1: Master has lost arbitration"
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bitfld.long 0x0 11. "ABRT_MASTER_DIS,1: User tries to initiate a Master" "?,1: User tries to initiate a Master"
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bitfld.long 0x0 10. "ABRT_10B_RD_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
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bitfld.long 0x0 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9  the source of the" "?,1: The restart is disabled"
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bitfld.long 0x0 8. "ABRT_HS_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
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bitfld.long 0x0 7. "ABRT_SBYTE_ACKDET,1: Master has sent a START Byte and" "?,1: Master has sent a START Byte and"
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bitfld.long 0x0 6. "ABRT_HS_ACKDET,1: Master is in High Speed mode and" "?,1: Master is in High Speed mode and"
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bitfld.long 0x0 5. "ABRT_GCALL_READ,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
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bitfld.long 0x0 4. "ABRT_GCALL_NOACK,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
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bitfld.long 0x0 3. "ABRT_TXDATA_NOACK,1: This is a master-mode only bit." "?,1: This is a master-mode only bit"
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bitfld.long 0x0 2. "ABRT_10ADDR2_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
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bitfld.long 0x0 1. "ABRT_10ADDR1_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
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bitfld.long 0x0 0. "ABRT_7B_ADDR_NOACK,1: Master is in 7-bit addressing mode" "?,1: Master is in 7-bit addressing mode"
group.long 0x84++0x17
line.long 0x0 "IC_SLV_DATA_NACK_ONLY,Name: Generate Slave Data NACK Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_SLV_DATA_NACK_ONLY,Reserved bits - Read Only"
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bitfld.long 0x0 0. "NACK,Generate NACK." "0: generate NACK/ACK normally,1: generate NACK after data byte received"
line.long 0x4 "IC_DMA_CR,Name: DMA Control Register"
hexmask.long 0x4 2.--31. 1. "RSVD_IC_DMA_CR_2_31,Reserved bits [31:1] - Read Only"
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bitfld.long 0x4 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
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bitfld.long 0x4 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x8 "IC_DMA_TDLR,Name: DMA Transmit Data Level Register"
hexmask.long 0x8 6.--31. 1. "RSVD_DMA_TDLR,Reserved bits - Read Only"
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hexmask.long.byte 0x8 0.--5. 1. "DMATDL,Transmit Data Level."
line.long 0xC "IC_DMA_RDLR,Name: I2C Receive Data Level Register"
hexmask.long 0xC 6.--31. 1. "RSVD_DMA_RDLR,Reserved bits - Read Only"
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hexmask.long.byte 0xC 0.--5. 1. "DMARDL,Receive Data Level."
line.long 0x10 "IC_SDA_SETUP,Name: I2C SDA Setup Register"
hexmask.long.tbyte 0x10 8.--31. 1. "RSVD_IC_SDA_SETUP,Reserved bits - Read Only"
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hexmask.long.byte 0x10 0.--7. 1. "SDA_SETUP,SDA Setup."
line.long 0x14 "IC_ACK_GENERAL_CALL,Name: I2C ACK General Call Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_ACK_GEN_1_31,Reserved bits [31:1] - Read Only"
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bitfld.long 0x14 0. "ACK_GEN_CALL,ACK General Call." "0,1"
rgroup.long 0x9C++0x3
line.long 0x0 "IC_ENABLE_STATUS,Name: I2C Enable Status Register"
hexmask.long 0x0 3.--31. 1. "RSVD_IC_ENABLE_STATUS,Reserved bits - Read Only"
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bitfld.long 0x0 2. "SLV_RX_DATA_LOST,Slave Received Data Lost." "0,1"
newline
bitfld.long 0x0 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit  Receive)." "0,1"
newline
bitfld.long 0x0 0. "IC_EN,ic_en Status." "0,1"
group.long 0xA0++0x3
line.long 0x0 "IC_FS_SPKLEN,Name: I2C SS. FS or FM+ spike suppression limit"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_FS_SPKLEN,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0xA8++0x3
line.long 0x0 "IC_CLR_RESTART_DET,Name: Clear RESTART_DET Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_RESTART_DET,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "IC_COMP_PARAM_1,Name: Component Parameter Register 1"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_COMP_PARAM_1,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 16.--23. 1. "TX_BUFFER_DEPTH,The value of this register is derived"
newline
hexmask.long.byte 0x0 8.--15. 1. "RX_BUFFER_DEPTH,The value of this register is"
newline
bitfld.long 0x0 7. "ADD_ENCODED_PARAMS,The value of this register is derived" "0: False,1: True"
newline
bitfld.long 0x0 6. "HAS_DMA,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 5. "INTR_IO,The value of this register is" "0: Individual,1: Combined"
newline
bitfld.long 0x0 4. "HC_COUNT_VALUES,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 2.--3. "MAX_SPEED_MODE,The value of this register is" "0: Reserved,1: Standard,2: Fast,3: High"
newline
bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,The value of this register is" "0: 8 bits,1: 16 bits,2: 32 bits,3: Reserved"
line.long 0x4 "IC_COMP_VERSION,Name: I2C Component Version Register"
hexmask.long 0x4 0.--31. 1. "IC_COMP_VERSION,Specific values for this register are"
line.long 0x8 "IC_COMP_TYPE,Name: I2C Component Type Register"
hexmask.long 0x8 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number"
tree.end
tree "I2C2 (I2C2 Module)"
base ad:0xFFC02A00
group.long 0x0++0xB
line.long 0x0 "IC_CON,Name: I2C Control Register"
hexmask.long.word 0x0 20.--31. 1. "RSVD_IC_CON_2,Reserved bits - Read Only"
newline
rbitfld.long 0x0 19. "RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 18. "RSVD_SMBUS_ARP_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_QUICK_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 16. "RSVD_OPTIONAL_SAR_CTRL,Reserved bits - Read Only" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_CON_1,Reserved bits - Read Only"
newline
rbitfld.long 0x0 11. "RSVD_BUS_CLEAR_FEATURE_CTRL,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 10. "STOP_DET_IF_MASTER_ACTIVE,In Master mode:" "0: issues the STOP_DET irrespective of whether..,1: issues the STOP_DET interrupt only when master.."
newline
rbitfld.long 0x0 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether" "0,1"
newline
bitfld.long 0x0 8. "TX_EMPTY_CTRL,This bit controls the generation" "0,1"
newline
bitfld.long 0x0 7. "STOP_DET_IFADDRESSED,In slave mode:" "0: issues the STOP_DET irrespective of whether it's..,1: issues the STOP_DET interrrupt only when it is.."
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bitfld.long 0x0 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled " "0: slave is enabled,1: slave is disabled"
newline
bitfld.long 0x0 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when" "0: disable,1: enable"
newline
rbitfld.long 0x0 4. "IC_10BITADDR_MASTER_rd_only,If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.long 0x0 3. "IC_10BITADDR_SLAVE,When acting as a slave  this bit controls whether the DW_apb_i2c" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates; its" "?,1: standard mode,2: fast mode,3: high speed mode"
newline
bitfld.long 0x0 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled." "0: master disabled,1: master enabled"
line.long 0x4 "IC_TAR,Name: I2C Target Address Register"
hexmask.long.word 0x4 17.--31. 1. "RSVD_IC_TAR_2,Reserved bits - Read Only"
newline
rbitfld.long 0x4 16. "RSVD_SMBUS_QUICK_CMD,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x4 14.--15. "RSVD_IC_TAR_1,Reserved bits - Read Only" "0,1,2,3"
newline
rbitfld.long 0x4 13. "RSVD_DEVICE_ID,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x4 12. "IC_10BITADDR_MASTER,This bit controls whether the DW_apb_i2c starts its transfers in 7-" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x4 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or" "0: ignore bit 10 GC_OR_START and use IC_TAR normally,1: perform special I2C command as specified in.."
newline
bitfld.long 0x4 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0  then this bit indicates whether a" "0: General Call Address after issuing a General Call,1: START BYTE"
newline
hexmask.long.word 0x4 0.--9. 1. "IC_TAR,This is the target address for any master transaction. When"
line.long 0x8 "IC_SAR,Name: I2C Slave Address Register"
hexmask.long.tbyte 0x8 10.--31. 1. "RSVD_IC_SAR,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit"
group.long 0x10++0x13
line.long 0x0 "IC_DATA_CMD,Name: I2C Rx/Tx Data Buffer and Command Register;"
hexmask.long.tbyte 0x0 12.--31. 1. "RSVD_IC_DATA_CMD,Reserved bits - Read Only"
newline
rbitfld.long 0x0 11. "FIRST_DATA_BYTE,Indicates the first data byte" "0,1"
newline
bitfld.long 0x0 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received." "0,1"
newline
bitfld.long 0x0 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received." "0,1"
newline
bitfld.long 0x0 8. "CMD,This bit controls whether a read or a write is performed." "0: Write,1: Read"
newline
hexmask.long.byte 0x0 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus."
line.long 0x4 "IC_SS_SCL_HCNT,Name: Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x4 16.--31. 1. "RSVD_IC_SS_SCL_HIGH_COUNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x8 "IC_SS_SCL_LCNT,Name: Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x8 16.--31. 1. "RSVD_IC_SS_SCL_LOW_COUNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0xC "IC_FS_SCL_HCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"
hexmask.long.word 0xC 16.--31. 1. "RSVD_IC_FS_SCL_HCNT,Reserved bits - Read Only"
newline
hexmask.long.word 0xC 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x10 "IC_FS_SCL_LCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"
hexmask.long.word 0x10 16.--31. 1. "RSVD_IC_FS_SCL_LCNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x10 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0x2C++0x3
line.long 0x0 "IC_INTR_STAT,Name: I2C Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "RSVD_R_SCL_STUCK_AT_LOW,Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT number of ic_clk periods." "0,1"
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bitfld.long 0x0 13. "R_MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
newline
bitfld.long 0x0 12. "R_RESTART_DET,Indicates a RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
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bitfld.long 0x0 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
newline
bitfld.long 0x0 9. "R_STOP_DET,The behavior of the STOP_DET interrupt status differs based on the" "0: Indicates whether a STOP condition has occurred..,1: In Master Mode"
newline
bitfld.long 0x0 8. "R_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
newline
bitfld.long 0x0 7. "R_RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "R_TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
newline
bitfld.long 0x0 5. "R_RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
newline
bitfld.long 0x0 4. "R_TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the" "0: This bit is set to 1 when the transmit buffer is..,1: This bit is set to 1 when the transmit buffer is.."
newline
bitfld.long 0x0 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
newline
bitfld.long 0x0 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
newline
bitfld.long 0x0 1. "R_RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
newline
bitfld.long 0x0 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x30++0x3
line.long 0x0 "IC_INTR_MASK,Name: I2C Interrupt Mask Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
newline
rbitfld.long 0x0 14. "RSVD_M_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 13. "M_MASTER_ON_HOLD,This bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register." "0,1"
rgroup.long 0x34++0x3
line.long 0x0 "IC_RAW_INTR_STAT,Name: I2C Raw Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_RAW_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "RSVD_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 13. "MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
newline
bitfld.long 0x0 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface" "0,1"
newline
bitfld.long 0x0 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
newline
bitfld.long 0x0 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
newline
bitfld.long 0x0 9. "STOP_DET,Indicates whether a STOP condition" "0,1"
newline
bitfld.long 0x0 8. "RAW_INTR_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
newline
bitfld.long 0x0 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
newline
bitfld.long 0x0 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
newline
bitfld.long 0x0 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status" "0: This bit is set to 1 when the transmit buffer..,1: This bit is set to 1 when the transmit buffer.."
newline
bitfld.long 0x0 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
newline
bitfld.long 0x0 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
newline
bitfld.long 0x0 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
newline
bitfld.long 0x0 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x38++0x7
line.long 0x0 "IC_RX_TL,Name: I2C Receive FIFO Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_RX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "RX_TL,Receive FIFO Threshold Level"
line.long 0x4 "IC_TX_TL,Name: I2C Transmit FIFO Threshold Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IC_TX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level"
rgroup.long 0x40++0x2B
line.long 0x0 "IC_CLR_INTR,Name: Clear Combined and Individual Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_INTR,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_INTR,Read this register to clear the combined interrupt " "0,1"
line.long 0x4 "IC_CLR_RX_UNDER,Name: Clear RX_UNDER Interrupt Register"
hexmask.long 0x4 1.--31. 1. "RSVD_IC_CLR_RX_UNDER,Reserved bits - Read Only"
newline
bitfld.long 0x4 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER" "0,1"
line.long 0x8 "IC_CLR_RX_OVER,Name: Clear RX_OVER Interrupt Register"
hexmask.long 0x8 1.--31. 1. "RSVD_IC_CLR_RX_OVER,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "CLR_RX_OVER,Read this register to clear the RX_OVER" "0,1"
line.long 0xC "IC_CLR_TX_OVER,Name: Clear TX_OVER Interrupt Register"
hexmask.long 0xC 1.--31. 1. "RSVD_IC_CLR_TX_OVER,Reserved bits - Read Only"
newline
bitfld.long 0xC 0. "CLR_TX_OVER,Read this register to clear the TX_OVER" "0,1"
line.long 0x10 "IC_CLR_RD_REQ,Name: Clear RD_REQ Interrupt Register"
hexmask.long 0x10 1.--31. 1. "RSVD_IC_CLR_RD_REQ,Reserved bits - Read Only"
newline
bitfld.long 0x10 0. "CLR_RD_REQ,Read this register to clear the RD_REQ" "0,1"
line.long 0x14 "IC_CLR_TX_ABRT,Name: Clear TX_ABRT Interrupt Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_CLR_TX_ABRT,Reserved bits - Read Only"
newline
bitfld.long 0x14 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT" "0,1"
line.long 0x18 "IC_CLR_RX_DONE,Name: Clear RX_DONE Interrupt Register"
hexmask.long 0x18 1.--31. 1. "RSVD_IC_CLR_RX_DONE,Reserved bits - Read Only"
newline
bitfld.long 0x18 0. "CLR_RX_DONE,Read this register to clear the RX_DONE" "0,1"
line.long 0x1C "IC_CLR_ACTIVITY,Name: Clear ACTIVITY Interrupt Register"
hexmask.long 0x1C 1.--31. 1. "RSVD_IC_CLR_ACTIVITY,Reserved bits - Read Only"
newline
bitfld.long 0x1C 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY" "0,1"
line.long 0x20 "IC_CLR_STOP_DET,Name: Clear STOP_DET Interrupt Register"
hexmask.long 0x20 1.--31. 1. "RSVD_IC_CLR_STOP_DET,Reserved bits - Read Only"
newline
bitfld.long 0x20 0. "CLR_STOP_DET,Read this register to clear the STOP_DET" "0,1"
line.long 0x24 "IC_CLR_START_DET,Name: Clear START_DET Interrupt Register"
hexmask.long 0x24 1.--31. 1. "RSVD_IC_CLR_START_DET,Reserved bits - Read Only"
newline
bitfld.long 0x24 0. "CLR_START_DET,Read this register to clear the START_DET" "0,1"
line.long 0x28 "IC_CLR_GEN_CALL,Name: Clear GEN_CALL Interrupt Register"
hexmask.long 0x28 1.--31. 1. "RSVD_IC_CLR_GEN_CALL,Reserved bits - Read Only"
newline
bitfld.long 0x28 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL" "0,1"
group.long 0x6C++0x3
line.long 0x0 "IC_ENABLE,Name: I2C Enable Register"
hexmask.long.word 0x0 19.--31. 1. "RSVD_IC_ENABLE_2,Reserved bits - Read Only"
newline
rbitfld.long 0x0 18. "RSVD_SMBUS_ALERT_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 17. "RSVD_SMBUS_SUSPEND_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 16. "RSVD_SMBUS_CLK_RESET,Reserved bits - Read Only" "0,1"
newline
hexmask.long.word 0x0 4.--15. 1. "RSVD_IC_ENABLE_1,Reserved bits - Read Only"
newline
rbitfld.long 0x0 3. "RSVD_SDA_STUCK_RECOVERY_ENABLE,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 2. "TX_CMD_BLOCK,In Master mode" "0,1"
newline
bitfld.long 0x0 1. "ABORT,When set  the controller initiates the transfer abort." "0: ABORT not initiated or ABORT done,1: ABORT operation in progress"
newline
bitfld.long 0x0 0. "ENABLE,Controls whether the DW_apb_i2c is enabled." "0: Disables DW_apb_i2c,1: Enables DW_apb_i2c"
rgroup.long 0x70++0xB
line.long 0x0 "IC_STATUS,Name: I2C Status Register"
hexmask.long.word 0x0 21.--31. 1. "RSVD_IC_STATUS_2,Reserved bits - Read Only"
newline
bitfld.long 0x0 20. "RSVD_SMBUS_ALERT_STATUS,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 19. "RSVD_SMBUS_SUSPEND_STATUS,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 18. "RSVD_SMBUS_SLAVE_ADDR_RESOLVED,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_ADDR_VALID,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 16. "RSVD_SMBUS_QUICK_CMD_BIT,Reserved bits - Read Only" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_STATUS_1,Reserved bits - Read Only"
newline
bitfld.long 0x0 11. "RSVD_SDA_STUCK_NOT_RECOVERED,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 10. "RSVD_SLV_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 9. "RSVD_SLV_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 8. "RSVD_MST_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 7. "RSVD_MST_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 6. "SLV_ACTIVITY,Slave FSM Activity Status." "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave part"
newline
bitfld.long 0x0 5. "MST_ACTIVITY,Master FSM Activity Status." "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
newline
bitfld.long 0x0 4. "RFF,Receive FIFO Completely Full." "0: Receive FIFO is not full,1: Receive FIFO is full"
newline
bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
newline
bitfld.long 0x0 2. "TFE,Transmit FIFO Completely Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
newline
bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 0. "IC_STATUS_ACTIVITY,I2C Activity Status." "0,1"
line.long 0x4 "IC_TXFLR,Name: I2C Transmit FIFO Level Register"
hexmask.long 0x4 7.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
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hexmask.long.byte 0x4 0.--6. 1. "TXFLR,Transmit FIFO Level."
line.long 0x8 "IC_RXFLR,Name: I2C Receive FIFO Level Register"
hexmask.long 0x8 7.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
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hexmask.long.byte 0x8 0.--6. 1. "RXFLR,Receive FIFO Level."
group.long 0x7C++0x3
line.long 0x0 "IC_SDA_HOLD,Name: I2C SDA Hold Time Length Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_SDA_HOLD,Reserved bits - Read Only"
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hexmask.long.byte 0x0 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time"
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hexmask.long.word 0x0 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time"
rgroup.long 0x80++0x3
line.long 0x0 "IC_TX_ABRT_SOURCE,Name: I2C Transmit Abort Source Register"
hexmask.long.word 0x0 23.--31. 1. "TX_FLUSH_CNT,This field indicates the"
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bitfld.long 0x0 21.--22. "RSVD_IC_TX_ABRT_SOURCE,Reserved bits - Read Only" "0,1,2,3"
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bitfld.long 0x0 18.--20. "RSVD_ABRT_DEVICE_WRITE,Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 17. "RSVD_ABRT_SDA_STUCK_AT_LOW," "0,1"
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bitfld.long 0x0 16. "ABRT_USER_ABRT,This is a master-mode-only bit. Master has" "0,1"
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bitfld.long 0x0 15. "ABRT_SLVRD_INTX,1: When the processor side responds to" "?,1: When the processor side responds to"
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bitfld.long 0x0 14. "ABRT_SLV_ARBLOST,1: Slave lost the bus while transmitting" "?,1: Slave lost the bus while transmitting"
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bitfld.long 0x0 13. "ABRT_SLVFLUSH_TXFIFO,1: Slave has received a read command" "?,1: Slave has received a read command"
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bitfld.long 0x0 12. "ARB_LOST,1: Master has lost arbitration  or if" "?,1: Master has lost arbitration"
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bitfld.long 0x0 11. "ABRT_MASTER_DIS,1: User tries to initiate a Master" "?,1: User tries to initiate a Master"
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bitfld.long 0x0 10. "ABRT_10B_RD_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
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bitfld.long 0x0 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9  the source of the" "?,1: The restart is disabled"
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bitfld.long 0x0 8. "ABRT_HS_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
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bitfld.long 0x0 7. "ABRT_SBYTE_ACKDET,1: Master has sent a START Byte and" "?,1: Master has sent a START Byte and"
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bitfld.long 0x0 6. "ABRT_HS_ACKDET,1: Master is in High Speed mode and" "?,1: Master is in High Speed mode and"
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bitfld.long 0x0 5. "ABRT_GCALL_READ,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
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bitfld.long 0x0 4. "ABRT_GCALL_NOACK,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
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bitfld.long 0x0 3. "ABRT_TXDATA_NOACK,1: This is a master-mode only bit." "?,1: This is a master-mode only bit"
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bitfld.long 0x0 2. "ABRT_10ADDR2_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
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bitfld.long 0x0 1. "ABRT_10ADDR1_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
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bitfld.long 0x0 0. "ABRT_7B_ADDR_NOACK,1: Master is in 7-bit addressing mode" "?,1: Master is in 7-bit addressing mode"
group.long 0x84++0x17
line.long 0x0 "IC_SLV_DATA_NACK_ONLY,Name: Generate Slave Data NACK Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_SLV_DATA_NACK_ONLY,Reserved bits - Read Only"
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bitfld.long 0x0 0. "NACK,Generate NACK." "0: generate NACK/ACK normally,1: generate NACK after data byte received"
line.long 0x4 "IC_DMA_CR,Name: DMA Control Register"
hexmask.long 0x4 2.--31. 1. "RSVD_IC_DMA_CR_2_31,Reserved bits [31:1] - Read Only"
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bitfld.long 0x4 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
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bitfld.long 0x4 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x8 "IC_DMA_TDLR,Name: DMA Transmit Data Level Register"
hexmask.long 0x8 6.--31. 1. "RSVD_DMA_TDLR,Reserved bits - Read Only"
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hexmask.long.byte 0x8 0.--5. 1. "DMATDL,Transmit Data Level."
line.long 0xC "IC_DMA_RDLR,Name: I2C Receive Data Level Register"
hexmask.long 0xC 6.--31. 1. "RSVD_DMA_RDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0xC 0.--5. 1. "DMARDL,Receive Data Level."
line.long 0x10 "IC_SDA_SETUP,Name: I2C SDA Setup Register"
hexmask.long.tbyte 0x10 8.--31. 1. "RSVD_IC_SDA_SETUP,Reserved bits - Read Only"
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hexmask.long.byte 0x10 0.--7. 1. "SDA_SETUP,SDA Setup."
line.long 0x14 "IC_ACK_GENERAL_CALL,Name: I2C ACK General Call Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_ACK_GEN_1_31,Reserved bits [31:1] - Read Only"
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bitfld.long 0x14 0. "ACK_GEN_CALL,ACK General Call." "0,1"
rgroup.long 0x9C++0x3
line.long 0x0 "IC_ENABLE_STATUS,Name: I2C Enable Status Register"
hexmask.long 0x0 3.--31. 1. "RSVD_IC_ENABLE_STATUS,Reserved bits - Read Only"
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bitfld.long 0x0 2. "SLV_RX_DATA_LOST,Slave Received Data Lost." "0,1"
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bitfld.long 0x0 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit  Receive)." "0,1"
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bitfld.long 0x0 0. "IC_EN,ic_en Status." "0,1"
group.long 0xA0++0x3
line.long 0x0 "IC_FS_SPKLEN,Name: I2C SS. FS or FM+ spike suppression limit"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_FS_SPKLEN,Reserved bits - Read Only"
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hexmask.long.byte 0x0 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0xA8++0x3
line.long 0x0 "IC_CLR_RESTART_DET,Name: Clear RESTART_DET Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_RESTART_DET,Reserved bits - Read Only"
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bitfld.long 0x0 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "IC_COMP_PARAM_1,Name: Component Parameter Register 1"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_COMP_PARAM_1,Reserved bits - Read Only"
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hexmask.long.byte 0x0 16.--23. 1. "TX_BUFFER_DEPTH,The value of this register is derived"
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hexmask.long.byte 0x0 8.--15. 1. "RX_BUFFER_DEPTH,The value of this register is"
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bitfld.long 0x0 7. "ADD_ENCODED_PARAMS,The value of this register is derived" "0: False,1: True"
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bitfld.long 0x0 6. "HAS_DMA,The value of this register is" "0: False,1: True"
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bitfld.long 0x0 5. "INTR_IO,The value of this register is" "0: Individual,1: Combined"
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bitfld.long 0x0 4. "HC_COUNT_VALUES,The value of this register is" "0: False,1: True"
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bitfld.long 0x0 2.--3. "MAX_SPEED_MODE,The value of this register is" "0: Reserved,1: Standard,2: Fast,3: High"
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bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,The value of this register is" "0: 8 bits,1: 16 bits,2: 32 bits,3: Reserved"
line.long 0x4 "IC_COMP_VERSION,Name: I2C Component Version Register"
hexmask.long 0x4 0.--31. 1. "IC_COMP_VERSION,Specific values for this register are"
line.long 0x8 "IC_COMP_TYPE,Name: I2C Component Type Register"
hexmask.long 0x8 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number"
tree.end
tree "I2C3 (I2C3 Module)"
base ad:0xFFC02B00
group.long 0x0++0xB
line.long 0x0 "IC_CON,Name: I2C Control Register"
hexmask.long.word 0x0 20.--31. 1. "RSVD_IC_CON_2,Reserved bits - Read Only"
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rbitfld.long 0x0 19. "RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 18. "RSVD_SMBUS_ARP_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_QUICK_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 16. "RSVD_OPTIONAL_SAR_CTRL,Reserved bits - Read Only" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_CON_1,Reserved bits - Read Only"
newline
rbitfld.long 0x0 11. "RSVD_BUS_CLEAR_FEATURE_CTRL,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 10. "STOP_DET_IF_MASTER_ACTIVE,In Master mode:" "0: issues the STOP_DET irrespective of whether..,1: issues the STOP_DET interrupt only when master.."
newline
rbitfld.long 0x0 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether" "0,1"
newline
bitfld.long 0x0 8. "TX_EMPTY_CTRL,This bit controls the generation" "0,1"
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bitfld.long 0x0 7. "STOP_DET_IFADDRESSED,In slave mode:" "0: issues the STOP_DET irrespective of whether it's..,1: issues the STOP_DET interrrupt only when it is.."
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bitfld.long 0x0 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled " "0: slave is enabled,1: slave is disabled"
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bitfld.long 0x0 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when" "0: disable,1: enable"
newline
rbitfld.long 0x0 4. "IC_10BITADDR_MASTER_rd_only,If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 3. "IC_10BITADDR_SLAVE,When acting as a slave  this bit controls whether the DW_apb_i2c" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates; its" "?,1: standard mode,2: fast mode,3: high speed mode"
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bitfld.long 0x0 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled." "0: master disabled,1: master enabled"
line.long 0x4 "IC_TAR,Name: I2C Target Address Register"
hexmask.long.word 0x4 17.--31. 1. "RSVD_IC_TAR_2,Reserved bits - Read Only"
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rbitfld.long 0x4 16. "RSVD_SMBUS_QUICK_CMD,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x4 14.--15. "RSVD_IC_TAR_1,Reserved bits - Read Only" "0,1,2,3"
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rbitfld.long 0x4 13. "RSVD_DEVICE_ID,Reserved bits - Read Only" "0,1"
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bitfld.long 0x4 12. "IC_10BITADDR_MASTER,This bit controls whether the DW_apb_i2c starts its transfers in 7-" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x4 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or" "0: ignore bit 10 GC_OR_START and use IC_TAR normally,1: perform special I2C command as specified in.."
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bitfld.long 0x4 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0  then this bit indicates whether a" "0: General Call Address after issuing a General Call,1: START BYTE"
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hexmask.long.word 0x4 0.--9. 1. "IC_TAR,This is the target address for any master transaction. When"
line.long 0x8 "IC_SAR,Name: I2C Slave Address Register"
hexmask.long.tbyte 0x8 10.--31. 1. "RSVD_IC_SAR,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit"
group.long 0x10++0x13
line.long 0x0 "IC_DATA_CMD,Name: I2C Rx/Tx Data Buffer and Command Register;"
hexmask.long.tbyte 0x0 12.--31. 1. "RSVD_IC_DATA_CMD,Reserved bits - Read Only"
newline
rbitfld.long 0x0 11. "FIRST_DATA_BYTE,Indicates the first data byte" "0,1"
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bitfld.long 0x0 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received." "0,1"
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bitfld.long 0x0 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received." "0,1"
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bitfld.long 0x0 8. "CMD,This bit controls whether a read or a write is performed." "0: Write,1: Read"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus."
line.long 0x4 "IC_SS_SCL_HCNT,Name: Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x4 16.--31. 1. "RSVD_IC_SS_SCL_HIGH_COUNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x8 "IC_SS_SCL_LCNT,Name: Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x8 16.--31. 1. "RSVD_IC_SS_SCL_LOW_COUNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0xC "IC_FS_SCL_HCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"
hexmask.long.word 0xC 16.--31. 1. "RSVD_IC_FS_SCL_HCNT,Reserved bits - Read Only"
newline
hexmask.long.word 0xC 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x10 "IC_FS_SCL_LCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"
hexmask.long.word 0x10 16.--31. 1. "RSVD_IC_FS_SCL_LCNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x10 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0x2C++0x3
line.long 0x0 "IC_INTR_STAT,Name: I2C Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "RSVD_R_SCL_STUCK_AT_LOW,Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT number of ic_clk periods." "0,1"
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bitfld.long 0x0 13. "R_MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
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bitfld.long 0x0 12. "R_RESTART_DET,Indicates a RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
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bitfld.long 0x0 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 9. "R_STOP_DET,The behavior of the STOP_DET interrupt status differs based on the" "0: Indicates whether a STOP condition has occurred..,1: In Master Mode"
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bitfld.long 0x0 8. "R_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
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bitfld.long 0x0 7. "R_RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
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bitfld.long 0x0 6. "R_TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
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bitfld.long 0x0 5. "R_RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
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bitfld.long 0x0 4. "R_TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the" "0: This bit is set to 1 when the transmit buffer is..,1: This bit is set to 1 when the transmit buffer is.."
newline
bitfld.long 0x0 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
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bitfld.long 0x0 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
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bitfld.long 0x0 1. "R_RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
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bitfld.long 0x0 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x30++0x3
line.long 0x0 "IC_INTR_MASK,Name: I2C Interrupt Mask Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
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rbitfld.long 0x0 14. "RSVD_M_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 13. "M_MASTER_ON_HOLD,This bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register." "0,1"
rgroup.long 0x34++0x3
line.long 0x0 "IC_RAW_INTR_STAT,Name: I2C Raw Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_RAW_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "RSVD_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 13. "MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
newline
bitfld.long 0x0 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface" "0,1"
newline
bitfld.long 0x0 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
newline
bitfld.long 0x0 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
newline
bitfld.long 0x0 9. "STOP_DET,Indicates whether a STOP condition" "0,1"
newline
bitfld.long 0x0 8. "RAW_INTR_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
newline
bitfld.long 0x0 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
newline
bitfld.long 0x0 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
newline
bitfld.long 0x0 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status" "0: This bit is set to 1 when the transmit buffer..,1: This bit is set to 1 when the transmit buffer.."
newline
bitfld.long 0x0 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
newline
bitfld.long 0x0 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
newline
bitfld.long 0x0 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
newline
bitfld.long 0x0 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x38++0x7
line.long 0x0 "IC_RX_TL,Name: I2C Receive FIFO Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_RX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "RX_TL,Receive FIFO Threshold Level"
line.long 0x4 "IC_TX_TL,Name: I2C Transmit FIFO Threshold Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IC_TX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level"
rgroup.long 0x40++0x2B
line.long 0x0 "IC_CLR_INTR,Name: Clear Combined and Individual Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_INTR,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_INTR,Read this register to clear the combined interrupt " "0,1"
line.long 0x4 "IC_CLR_RX_UNDER,Name: Clear RX_UNDER Interrupt Register"
hexmask.long 0x4 1.--31. 1. "RSVD_IC_CLR_RX_UNDER,Reserved bits - Read Only"
newline
bitfld.long 0x4 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER" "0,1"
line.long 0x8 "IC_CLR_RX_OVER,Name: Clear RX_OVER Interrupt Register"
hexmask.long 0x8 1.--31. 1. "RSVD_IC_CLR_RX_OVER,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "CLR_RX_OVER,Read this register to clear the RX_OVER" "0,1"
line.long 0xC "IC_CLR_TX_OVER,Name: Clear TX_OVER Interrupt Register"
hexmask.long 0xC 1.--31. 1. "RSVD_IC_CLR_TX_OVER,Reserved bits - Read Only"
newline
bitfld.long 0xC 0. "CLR_TX_OVER,Read this register to clear the TX_OVER" "0,1"
line.long 0x10 "IC_CLR_RD_REQ,Name: Clear RD_REQ Interrupt Register"
hexmask.long 0x10 1.--31. 1. "RSVD_IC_CLR_RD_REQ,Reserved bits - Read Only"
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bitfld.long 0x10 0. "CLR_RD_REQ,Read this register to clear the RD_REQ" "0,1"
line.long 0x14 "IC_CLR_TX_ABRT,Name: Clear TX_ABRT Interrupt Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_CLR_TX_ABRT,Reserved bits - Read Only"
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bitfld.long 0x14 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT" "0,1"
line.long 0x18 "IC_CLR_RX_DONE,Name: Clear RX_DONE Interrupt Register"
hexmask.long 0x18 1.--31. 1. "RSVD_IC_CLR_RX_DONE,Reserved bits - Read Only"
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bitfld.long 0x18 0. "CLR_RX_DONE,Read this register to clear the RX_DONE" "0,1"
line.long 0x1C "IC_CLR_ACTIVITY,Name: Clear ACTIVITY Interrupt Register"
hexmask.long 0x1C 1.--31. 1. "RSVD_IC_CLR_ACTIVITY,Reserved bits - Read Only"
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bitfld.long 0x1C 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY" "0,1"
line.long 0x20 "IC_CLR_STOP_DET,Name: Clear STOP_DET Interrupt Register"
hexmask.long 0x20 1.--31. 1. "RSVD_IC_CLR_STOP_DET,Reserved bits - Read Only"
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bitfld.long 0x20 0. "CLR_STOP_DET,Read this register to clear the STOP_DET" "0,1"
line.long 0x24 "IC_CLR_START_DET,Name: Clear START_DET Interrupt Register"
hexmask.long 0x24 1.--31. 1. "RSVD_IC_CLR_START_DET,Reserved bits - Read Only"
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bitfld.long 0x24 0. "CLR_START_DET,Read this register to clear the START_DET" "0,1"
line.long 0x28 "IC_CLR_GEN_CALL,Name: Clear GEN_CALL Interrupt Register"
hexmask.long 0x28 1.--31. 1. "RSVD_IC_CLR_GEN_CALL,Reserved bits - Read Only"
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bitfld.long 0x28 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL" "0,1"
group.long 0x6C++0x3
line.long 0x0 "IC_ENABLE,Name: I2C Enable Register"
hexmask.long.word 0x0 19.--31. 1. "RSVD_IC_ENABLE_2,Reserved bits - Read Only"
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rbitfld.long 0x0 18. "RSVD_SMBUS_ALERT_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 17. "RSVD_SMBUS_SUSPEND_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 16. "RSVD_SMBUS_CLK_RESET,Reserved bits - Read Only" "0,1"
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hexmask.long.word 0x0 4.--15. 1. "RSVD_IC_ENABLE_1,Reserved bits - Read Only"
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rbitfld.long 0x0 3. "RSVD_SDA_STUCK_RECOVERY_ENABLE,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 2. "TX_CMD_BLOCK,In Master mode" "0,1"
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bitfld.long 0x0 1. "ABORT,When set  the controller initiates the transfer abort." "0: ABORT not initiated or ABORT done,1: ABORT operation in progress"
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bitfld.long 0x0 0. "ENABLE,Controls whether the DW_apb_i2c is enabled." "0: Disables DW_apb_i2c,1: Enables DW_apb_i2c"
rgroup.long 0x70++0xB
line.long 0x0 "IC_STATUS,Name: I2C Status Register"
hexmask.long.word 0x0 21.--31. 1. "RSVD_IC_STATUS_2,Reserved bits - Read Only"
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bitfld.long 0x0 20. "RSVD_SMBUS_ALERT_STATUS,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 19. "RSVD_SMBUS_SUSPEND_STATUS,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 18. "RSVD_SMBUS_SLAVE_ADDR_RESOLVED,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_ADDR_VALID,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 16. "RSVD_SMBUS_QUICK_CMD_BIT,Reserved bits - Read Only" "0,1"
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hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_STATUS_1,Reserved bits - Read Only"
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bitfld.long 0x0 11. "RSVD_SDA_STUCK_NOT_RECOVERED,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 10. "RSVD_SLV_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 9. "RSVD_SLV_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 8. "RSVD_MST_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 7. "RSVD_MST_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 6. "SLV_ACTIVITY,Slave FSM Activity Status." "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave part"
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bitfld.long 0x0 5. "MST_ACTIVITY,Master FSM Activity Status." "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
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bitfld.long 0x0 4. "RFF,Receive FIFO Completely Full." "0: Receive FIFO is not full,1: Receive FIFO is full"
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bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
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bitfld.long 0x0 2. "TFE,Transmit FIFO Completely Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
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bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 0. "IC_STATUS_ACTIVITY,I2C Activity Status." "0,1"
line.long 0x4 "IC_TXFLR,Name: I2C Transmit FIFO Level Register"
hexmask.long 0x4 7.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
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hexmask.long.byte 0x4 0.--6. 1. "TXFLR,Transmit FIFO Level."
line.long 0x8 "IC_RXFLR,Name: I2C Receive FIFO Level Register"
hexmask.long 0x8 7.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
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hexmask.long.byte 0x8 0.--6. 1. "RXFLR,Receive FIFO Level."
group.long 0x7C++0x3
line.long 0x0 "IC_SDA_HOLD,Name: I2C SDA Hold Time Length Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_SDA_HOLD,Reserved bits - Read Only"
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hexmask.long.byte 0x0 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time"
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hexmask.long.word 0x0 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time"
rgroup.long 0x80++0x3
line.long 0x0 "IC_TX_ABRT_SOURCE,Name: I2C Transmit Abort Source Register"
hexmask.long.word 0x0 23.--31. 1. "TX_FLUSH_CNT,This field indicates the"
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bitfld.long 0x0 21.--22. "RSVD_IC_TX_ABRT_SOURCE,Reserved bits - Read Only" "0,1,2,3"
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bitfld.long 0x0 18.--20. "RSVD_ABRT_DEVICE_WRITE,Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 17. "RSVD_ABRT_SDA_STUCK_AT_LOW," "0,1"
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bitfld.long 0x0 16. "ABRT_USER_ABRT,This is a master-mode-only bit. Master has" "0,1"
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bitfld.long 0x0 15. "ABRT_SLVRD_INTX,1: When the processor side responds to" "?,1: When the processor side responds to"
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bitfld.long 0x0 14. "ABRT_SLV_ARBLOST,1: Slave lost the bus while transmitting" "?,1: Slave lost the bus while transmitting"
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bitfld.long 0x0 13. "ABRT_SLVFLUSH_TXFIFO,1: Slave has received a read command" "?,1: Slave has received a read command"
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bitfld.long 0x0 12. "ARB_LOST,1: Master has lost arbitration  or if" "?,1: Master has lost arbitration"
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bitfld.long 0x0 11. "ABRT_MASTER_DIS,1: User tries to initiate a Master" "?,1: User tries to initiate a Master"
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bitfld.long 0x0 10. "ABRT_10B_RD_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
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bitfld.long 0x0 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9  the source of the" "?,1: The restart is disabled"
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bitfld.long 0x0 8. "ABRT_HS_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
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bitfld.long 0x0 7. "ABRT_SBYTE_ACKDET,1: Master has sent a START Byte and" "?,1: Master has sent a START Byte and"
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bitfld.long 0x0 6. "ABRT_HS_ACKDET,1: Master is in High Speed mode and" "?,1: Master is in High Speed mode and"
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bitfld.long 0x0 5. "ABRT_GCALL_READ,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
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bitfld.long 0x0 4. "ABRT_GCALL_NOACK,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
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bitfld.long 0x0 3. "ABRT_TXDATA_NOACK,1: This is a master-mode only bit." "?,1: This is a master-mode only bit"
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bitfld.long 0x0 2. "ABRT_10ADDR2_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
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bitfld.long 0x0 1. "ABRT_10ADDR1_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
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bitfld.long 0x0 0. "ABRT_7B_ADDR_NOACK,1: Master is in 7-bit addressing mode" "?,1: Master is in 7-bit addressing mode"
group.long 0x84++0x17
line.long 0x0 "IC_SLV_DATA_NACK_ONLY,Name: Generate Slave Data NACK Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_SLV_DATA_NACK_ONLY,Reserved bits - Read Only"
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bitfld.long 0x0 0. "NACK,Generate NACK." "0: generate NACK/ACK normally,1: generate NACK after data byte received"
line.long 0x4 "IC_DMA_CR,Name: DMA Control Register"
hexmask.long 0x4 2.--31. 1. "RSVD_IC_DMA_CR_2_31,Reserved bits [31:1] - Read Only"
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bitfld.long 0x4 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
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bitfld.long 0x4 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x8 "IC_DMA_TDLR,Name: DMA Transmit Data Level Register"
hexmask.long 0x8 6.--31. 1. "RSVD_DMA_TDLR,Reserved bits - Read Only"
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hexmask.long.byte 0x8 0.--5. 1. "DMATDL,Transmit Data Level."
line.long 0xC "IC_DMA_RDLR,Name: I2C Receive Data Level Register"
hexmask.long 0xC 6.--31. 1. "RSVD_DMA_RDLR,Reserved bits - Read Only"
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hexmask.long.byte 0xC 0.--5. 1. "DMARDL,Receive Data Level."
line.long 0x10 "IC_SDA_SETUP,Name: I2C SDA Setup Register"
hexmask.long.tbyte 0x10 8.--31. 1. "RSVD_IC_SDA_SETUP,Reserved bits - Read Only"
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hexmask.long.byte 0x10 0.--7. 1. "SDA_SETUP,SDA Setup."
line.long 0x14 "IC_ACK_GENERAL_CALL,Name: I2C ACK General Call Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_ACK_GEN_1_31,Reserved bits [31:1] - Read Only"
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bitfld.long 0x14 0. "ACK_GEN_CALL,ACK General Call." "0,1"
rgroup.long 0x9C++0x3
line.long 0x0 "IC_ENABLE_STATUS,Name: I2C Enable Status Register"
hexmask.long 0x0 3.--31. 1. "RSVD_IC_ENABLE_STATUS,Reserved bits - Read Only"
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bitfld.long 0x0 2. "SLV_RX_DATA_LOST,Slave Received Data Lost." "0,1"
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bitfld.long 0x0 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit  Receive)." "0,1"
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bitfld.long 0x0 0. "IC_EN,ic_en Status." "0,1"
group.long 0xA0++0x3
line.long 0x0 "IC_FS_SPKLEN,Name: I2C SS. FS or FM+ spike suppression limit"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_FS_SPKLEN,Reserved bits - Read Only"
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hexmask.long.byte 0x0 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0xA8++0x3
line.long 0x0 "IC_CLR_RESTART_DET,Name: Clear RESTART_DET Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_RESTART_DET,Reserved bits - Read Only"
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bitfld.long 0x0 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "IC_COMP_PARAM_1,Name: Component Parameter Register 1"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_COMP_PARAM_1,Reserved bits - Read Only"
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hexmask.long.byte 0x0 16.--23. 1. "TX_BUFFER_DEPTH,The value of this register is derived"
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hexmask.long.byte 0x0 8.--15. 1. "RX_BUFFER_DEPTH,The value of this register is"
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bitfld.long 0x0 7. "ADD_ENCODED_PARAMS,The value of this register is derived" "0: False,1: True"
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bitfld.long 0x0 6. "HAS_DMA,The value of this register is" "0: False,1: True"
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bitfld.long 0x0 5. "INTR_IO,The value of this register is" "0: Individual,1: Combined"
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bitfld.long 0x0 4. "HC_COUNT_VALUES,The value of this register is" "0: False,1: True"
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bitfld.long 0x0 2.--3. "MAX_SPEED_MODE,The value of this register is" "0: Reserved,1: Standard,2: Fast,3: High"
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bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,The value of this register is" "0: 8 bits,1: 16 bits,2: 32 bits,3: Reserved"
line.long 0x4 "IC_COMP_VERSION,Name: I2C Component Version Register"
hexmask.long 0x4 0.--31. 1. "IC_COMP_VERSION,Specific values for this register are"
line.long 0x8 "IC_COMP_TYPE,Name: I2C Component Type Register"
hexmask.long 0x8 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number"
tree.end
tree "I2C4 (I2C4 Module)"
base ad:0xFFC02C00
group.long 0x0++0xB
line.long 0x0 "IC_CON,Name: I2C Control Register"
hexmask.long.word 0x0 20.--31. 1. "RSVD_IC_CON_2,Reserved bits - Read Only"
newline
rbitfld.long 0x0 19. "RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 18. "RSVD_SMBUS_ARP_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_QUICK_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 16. "RSVD_OPTIONAL_SAR_CTRL,Reserved bits - Read Only" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_CON_1,Reserved bits - Read Only"
newline
rbitfld.long 0x0 11. "RSVD_BUS_CLEAR_FEATURE_CTRL,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 10. "STOP_DET_IF_MASTER_ACTIVE,In Master mode:" "0: issues the STOP_DET irrespective of whether..,1: issues the STOP_DET interrupt only when master.."
newline
rbitfld.long 0x0 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether" "0,1"
newline
bitfld.long 0x0 8. "TX_EMPTY_CTRL,This bit controls the generation" "0,1"
newline
bitfld.long 0x0 7. "STOP_DET_IFADDRESSED,In slave mode:" "0: issues the STOP_DET irrespective of whether it's..,1: issues the STOP_DET interrrupt only when it is.."
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bitfld.long 0x0 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled " "0: slave is enabled,1: slave is disabled"
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bitfld.long 0x0 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when" "0: disable,1: enable"
newline
rbitfld.long 0x0 4. "IC_10BITADDR_MASTER_rd_only,If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 3. "IC_10BITADDR_SLAVE,When acting as a slave  this bit controls whether the DW_apb_i2c" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates; its" "?,1: standard mode,2: fast mode,3: high speed mode"
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bitfld.long 0x0 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled." "0: master disabled,1: master enabled"
line.long 0x4 "IC_TAR,Name: I2C Target Address Register"
hexmask.long.word 0x4 17.--31. 1. "RSVD_IC_TAR_2,Reserved bits - Read Only"
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rbitfld.long 0x4 16. "RSVD_SMBUS_QUICK_CMD,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x4 14.--15. "RSVD_IC_TAR_1,Reserved bits - Read Only" "0,1,2,3"
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rbitfld.long 0x4 13. "RSVD_DEVICE_ID,Reserved bits - Read Only" "0,1"
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bitfld.long 0x4 12. "IC_10BITADDR_MASTER,This bit controls whether the DW_apb_i2c starts its transfers in 7-" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x4 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or" "0: ignore bit 10 GC_OR_START and use IC_TAR normally,1: perform special I2C command as specified in.."
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bitfld.long 0x4 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0  then this bit indicates whether a" "0: General Call Address after issuing a General Call,1: START BYTE"
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hexmask.long.word 0x4 0.--9. 1. "IC_TAR,This is the target address for any master transaction. When"
line.long 0x8 "IC_SAR,Name: I2C Slave Address Register"
hexmask.long.tbyte 0x8 10.--31. 1. "RSVD_IC_SAR,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit"
group.long 0x10++0x13
line.long 0x0 "IC_DATA_CMD,Name: I2C Rx/Tx Data Buffer and Command Register;"
hexmask.long.tbyte 0x0 12.--31. 1. "RSVD_IC_DATA_CMD,Reserved bits - Read Only"
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rbitfld.long 0x0 11. "FIRST_DATA_BYTE,Indicates the first data byte" "0,1"
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bitfld.long 0x0 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received." "0,1"
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bitfld.long 0x0 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received." "0,1"
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bitfld.long 0x0 8. "CMD,This bit controls whether a read or a write is performed." "0: Write,1: Read"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus."
line.long 0x4 "IC_SS_SCL_HCNT,Name: Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x4 16.--31. 1. "RSVD_IC_SS_SCL_HIGH_COUNT,Reserved bits - Read Only"
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hexmask.long.word 0x4 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x8 "IC_SS_SCL_LCNT,Name: Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x8 16.--31. 1. "RSVD_IC_SS_SCL_LOW_COUNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0xC "IC_FS_SCL_HCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"
hexmask.long.word 0xC 16.--31. 1. "RSVD_IC_FS_SCL_HCNT,Reserved bits - Read Only"
newline
hexmask.long.word 0xC 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x10 "IC_FS_SCL_LCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"
hexmask.long.word 0x10 16.--31. 1. "RSVD_IC_FS_SCL_LCNT,Reserved bits - Read Only"
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hexmask.long.word 0x10 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0x2C++0x3
line.long 0x0 "IC_INTR_STAT,Name: I2C Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "RSVD_R_SCL_STUCK_AT_LOW,Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT number of ic_clk periods." "0,1"
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bitfld.long 0x0 13. "R_MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
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bitfld.long 0x0 12. "R_RESTART_DET,Indicates a RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
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bitfld.long 0x0 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 9. "R_STOP_DET,The behavior of the STOP_DET interrupt status differs based on the" "0: Indicates whether a STOP condition has occurred..,1: In Master Mode"
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bitfld.long 0x0 8. "R_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
newline
bitfld.long 0x0 7. "R_RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "R_TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
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bitfld.long 0x0 5. "R_RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
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bitfld.long 0x0 4. "R_TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the" "0: This bit is set to 1 when the transmit buffer is..,1: This bit is set to 1 when the transmit buffer is.."
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bitfld.long 0x0 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
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bitfld.long 0x0 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
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bitfld.long 0x0 1. "R_RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
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bitfld.long 0x0 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x30++0x3
line.long 0x0 "IC_INTR_MASK,Name: I2C Interrupt Mask Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
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rbitfld.long 0x0 14. "RSVD_M_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 13. "M_MASTER_ON_HOLD,This bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register." "0,1"
rgroup.long 0x34++0x3
line.long 0x0 "IC_RAW_INTR_STAT,Name: I2C Raw Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_RAW_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "RSVD_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 13. "MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
newline
bitfld.long 0x0 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface" "0,1"
newline
bitfld.long 0x0 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
newline
bitfld.long 0x0 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
newline
bitfld.long 0x0 9. "STOP_DET,Indicates whether a STOP condition" "0,1"
newline
bitfld.long 0x0 8. "RAW_INTR_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
newline
bitfld.long 0x0 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
newline
bitfld.long 0x0 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
newline
bitfld.long 0x0 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status" "0: This bit is set to 1 when the transmit buffer..,1: This bit is set to 1 when the transmit buffer.."
newline
bitfld.long 0x0 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
newline
bitfld.long 0x0 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
newline
bitfld.long 0x0 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
newline
bitfld.long 0x0 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x38++0x7
line.long 0x0 "IC_RX_TL,Name: I2C Receive FIFO Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_RX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "RX_TL,Receive FIFO Threshold Level"
line.long 0x4 "IC_TX_TL,Name: I2C Transmit FIFO Threshold Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IC_TX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level"
rgroup.long 0x40++0x2B
line.long 0x0 "IC_CLR_INTR,Name: Clear Combined and Individual Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_INTR,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_INTR,Read this register to clear the combined interrupt " "0,1"
line.long 0x4 "IC_CLR_RX_UNDER,Name: Clear RX_UNDER Interrupt Register"
hexmask.long 0x4 1.--31. 1. "RSVD_IC_CLR_RX_UNDER,Reserved bits - Read Only"
newline
bitfld.long 0x4 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER" "0,1"
line.long 0x8 "IC_CLR_RX_OVER,Name: Clear RX_OVER Interrupt Register"
hexmask.long 0x8 1.--31. 1. "RSVD_IC_CLR_RX_OVER,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "CLR_RX_OVER,Read this register to clear the RX_OVER" "0,1"
line.long 0xC "IC_CLR_TX_OVER,Name: Clear TX_OVER Interrupt Register"
hexmask.long 0xC 1.--31. 1. "RSVD_IC_CLR_TX_OVER,Reserved bits - Read Only"
newline
bitfld.long 0xC 0. "CLR_TX_OVER,Read this register to clear the TX_OVER" "0,1"
line.long 0x10 "IC_CLR_RD_REQ,Name: Clear RD_REQ Interrupt Register"
hexmask.long 0x10 1.--31. 1. "RSVD_IC_CLR_RD_REQ,Reserved bits - Read Only"
newline
bitfld.long 0x10 0. "CLR_RD_REQ,Read this register to clear the RD_REQ" "0,1"
line.long 0x14 "IC_CLR_TX_ABRT,Name: Clear TX_ABRT Interrupt Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_CLR_TX_ABRT,Reserved bits - Read Only"
newline
bitfld.long 0x14 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT" "0,1"
line.long 0x18 "IC_CLR_RX_DONE,Name: Clear RX_DONE Interrupt Register"
hexmask.long 0x18 1.--31. 1. "RSVD_IC_CLR_RX_DONE,Reserved bits - Read Only"
newline
bitfld.long 0x18 0. "CLR_RX_DONE,Read this register to clear the RX_DONE" "0,1"
line.long 0x1C "IC_CLR_ACTIVITY,Name: Clear ACTIVITY Interrupt Register"
hexmask.long 0x1C 1.--31. 1. "RSVD_IC_CLR_ACTIVITY,Reserved bits - Read Only"
newline
bitfld.long 0x1C 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY" "0,1"
line.long 0x20 "IC_CLR_STOP_DET,Name: Clear STOP_DET Interrupt Register"
hexmask.long 0x20 1.--31. 1. "RSVD_IC_CLR_STOP_DET,Reserved bits - Read Only"
newline
bitfld.long 0x20 0. "CLR_STOP_DET,Read this register to clear the STOP_DET" "0,1"
line.long 0x24 "IC_CLR_START_DET,Name: Clear START_DET Interrupt Register"
hexmask.long 0x24 1.--31. 1. "RSVD_IC_CLR_START_DET,Reserved bits - Read Only"
newline
bitfld.long 0x24 0. "CLR_START_DET,Read this register to clear the START_DET" "0,1"
line.long 0x28 "IC_CLR_GEN_CALL,Name: Clear GEN_CALL Interrupt Register"
hexmask.long 0x28 1.--31. 1. "RSVD_IC_CLR_GEN_CALL,Reserved bits - Read Only"
newline
bitfld.long 0x28 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL" "0,1"
group.long 0x6C++0x3
line.long 0x0 "IC_ENABLE,Name: I2C Enable Register"
hexmask.long.word 0x0 19.--31. 1. "RSVD_IC_ENABLE_2,Reserved bits - Read Only"
newline
rbitfld.long 0x0 18. "RSVD_SMBUS_ALERT_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 17. "RSVD_SMBUS_SUSPEND_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 16. "RSVD_SMBUS_CLK_RESET,Reserved bits - Read Only" "0,1"
newline
hexmask.long.word 0x0 4.--15. 1. "RSVD_IC_ENABLE_1,Reserved bits - Read Only"
newline
rbitfld.long 0x0 3. "RSVD_SDA_STUCK_RECOVERY_ENABLE,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 2. "TX_CMD_BLOCK,In Master mode" "0,1"
newline
bitfld.long 0x0 1. "ABORT,When set  the controller initiates the transfer abort." "0: ABORT not initiated or ABORT done,1: ABORT operation in progress"
newline
bitfld.long 0x0 0. "ENABLE,Controls whether the DW_apb_i2c is enabled." "0: Disables DW_apb_i2c,1: Enables DW_apb_i2c"
rgroup.long 0x70++0xB
line.long 0x0 "IC_STATUS,Name: I2C Status Register"
hexmask.long.word 0x0 21.--31. 1. "RSVD_IC_STATUS_2,Reserved bits - Read Only"
newline
bitfld.long 0x0 20. "RSVD_SMBUS_ALERT_STATUS,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 19. "RSVD_SMBUS_SUSPEND_STATUS,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 18. "RSVD_SMBUS_SLAVE_ADDR_RESOLVED,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_ADDR_VALID,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 16. "RSVD_SMBUS_QUICK_CMD_BIT,Reserved bits - Read Only" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_STATUS_1,Reserved bits - Read Only"
newline
bitfld.long 0x0 11. "RSVD_SDA_STUCK_NOT_RECOVERED,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 10. "RSVD_SLV_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 9. "RSVD_SLV_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 8. "RSVD_MST_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 7. "RSVD_MST_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 6. "SLV_ACTIVITY,Slave FSM Activity Status." "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave part"
newline
bitfld.long 0x0 5. "MST_ACTIVITY,Master FSM Activity Status." "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
newline
bitfld.long 0x0 4. "RFF,Receive FIFO Completely Full." "0: Receive FIFO is not full,1: Receive FIFO is full"
newline
bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
newline
bitfld.long 0x0 2. "TFE,Transmit FIFO Completely Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
newline
bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
newline
bitfld.long 0x0 0. "IC_STATUS_ACTIVITY,I2C Activity Status." "0,1"
line.long 0x4 "IC_TXFLR,Name: I2C Transmit FIFO Level Register"
hexmask.long 0x4 7.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--6. 1. "TXFLR,Transmit FIFO Level."
line.long 0x8 "IC_RXFLR,Name: I2C Receive FIFO Level Register"
hexmask.long 0x8 7.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x8 0.--6. 1. "RXFLR,Receive FIFO Level."
group.long 0x7C++0x3
line.long 0x0 "IC_SDA_HOLD,Name: I2C SDA Hold Time Length Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_SDA_HOLD,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time"
newline
hexmask.long.word 0x0 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time"
rgroup.long 0x80++0x3
line.long 0x0 "IC_TX_ABRT_SOURCE,Name: I2C Transmit Abort Source Register"
hexmask.long.word 0x0 23.--31. 1. "TX_FLUSH_CNT,This field indicates the"
newline
bitfld.long 0x0 21.--22. "RSVD_IC_TX_ABRT_SOURCE,Reserved bits - Read Only" "0,1,2,3"
newline
bitfld.long 0x0 18.--20. "RSVD_ABRT_DEVICE_WRITE,Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 17. "RSVD_ABRT_SDA_STUCK_AT_LOW," "0,1"
newline
bitfld.long 0x0 16. "ABRT_USER_ABRT,This is a master-mode-only bit. Master has" "0,1"
newline
bitfld.long 0x0 15. "ABRT_SLVRD_INTX,1: When the processor side responds to" "?,1: When the processor side responds to"
newline
bitfld.long 0x0 14. "ABRT_SLV_ARBLOST,1: Slave lost the bus while transmitting" "?,1: Slave lost the bus while transmitting"
newline
bitfld.long 0x0 13. "ABRT_SLVFLUSH_TXFIFO,1: Slave has received a read command" "?,1: Slave has received a read command"
newline
bitfld.long 0x0 12. "ARB_LOST,1: Master has lost arbitration  or if" "?,1: Master has lost arbitration"
newline
bitfld.long 0x0 11. "ABRT_MASTER_DIS,1: User tries to initiate a Master" "?,1: User tries to initiate a Master"
newline
bitfld.long 0x0 10. "ABRT_10B_RD_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
newline
bitfld.long 0x0 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9  the source of the" "?,1: The restart is disabled"
newline
bitfld.long 0x0 8. "ABRT_HS_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
newline
bitfld.long 0x0 7. "ABRT_SBYTE_ACKDET,1: Master has sent a START Byte and" "?,1: Master has sent a START Byte and"
newline
bitfld.long 0x0 6. "ABRT_HS_ACKDET,1: Master is in High Speed mode and" "?,1: Master is in High Speed mode and"
newline
bitfld.long 0x0 5. "ABRT_GCALL_READ,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
newline
bitfld.long 0x0 4. "ABRT_GCALL_NOACK,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
newline
bitfld.long 0x0 3. "ABRT_TXDATA_NOACK,1: This is a master-mode only bit." "?,1: This is a master-mode only bit"
newline
bitfld.long 0x0 2. "ABRT_10ADDR2_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
newline
bitfld.long 0x0 1. "ABRT_10ADDR1_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
newline
bitfld.long 0x0 0. "ABRT_7B_ADDR_NOACK,1: Master is in 7-bit addressing mode" "?,1: Master is in 7-bit addressing mode"
group.long 0x84++0x17
line.long 0x0 "IC_SLV_DATA_NACK_ONLY,Name: Generate Slave Data NACK Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_SLV_DATA_NACK_ONLY,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "NACK,Generate NACK." "0: generate NACK/ACK normally,1: generate NACK after data byte received"
line.long 0x4 "IC_DMA_CR,Name: DMA Control Register"
hexmask.long 0x4 2.--31. 1. "RSVD_IC_DMA_CR_2_31,Reserved bits [31:1] - Read Only"
newline
bitfld.long 0x4 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
newline
bitfld.long 0x4 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x8 "IC_DMA_TDLR,Name: DMA Transmit Data Level Register"
hexmask.long 0x8 6.--31. 1. "RSVD_DMA_TDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x8 0.--5. 1. "DMATDL,Transmit Data Level."
line.long 0xC "IC_DMA_RDLR,Name: I2C Receive Data Level Register"
hexmask.long 0xC 6.--31. 1. "RSVD_DMA_RDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0xC 0.--5. 1. "DMARDL,Receive Data Level."
line.long 0x10 "IC_SDA_SETUP,Name: I2C SDA Setup Register"
hexmask.long.tbyte 0x10 8.--31. 1. "RSVD_IC_SDA_SETUP,Reserved bits - Read Only"
newline
hexmask.long.byte 0x10 0.--7. 1. "SDA_SETUP,SDA Setup."
line.long 0x14 "IC_ACK_GENERAL_CALL,Name: I2C ACK General Call Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_ACK_GEN_1_31,Reserved bits [31:1] - Read Only"
newline
bitfld.long 0x14 0. "ACK_GEN_CALL,ACK General Call." "0,1"
rgroup.long 0x9C++0x3
line.long 0x0 "IC_ENABLE_STATUS,Name: I2C Enable Status Register"
hexmask.long 0x0 3.--31. 1. "RSVD_IC_ENABLE_STATUS,Reserved bits - Read Only"
newline
bitfld.long 0x0 2. "SLV_RX_DATA_LOST,Slave Received Data Lost." "0,1"
newline
bitfld.long 0x0 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit  Receive)." "0,1"
newline
bitfld.long 0x0 0. "IC_EN,ic_en Status." "0,1"
group.long 0xA0++0x3
line.long 0x0 "IC_FS_SPKLEN,Name: I2C SS. FS or FM+ spike suppression limit"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_FS_SPKLEN,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0xA8++0x3
line.long 0x0 "IC_CLR_RESTART_DET,Name: Clear RESTART_DET Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_RESTART_DET,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "IC_COMP_PARAM_1,Name: Component Parameter Register 1"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_COMP_PARAM_1,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 16.--23. 1. "TX_BUFFER_DEPTH,The value of this register is derived"
newline
hexmask.long.byte 0x0 8.--15. 1. "RX_BUFFER_DEPTH,The value of this register is"
newline
bitfld.long 0x0 7. "ADD_ENCODED_PARAMS,The value of this register is derived" "0: False,1: True"
newline
bitfld.long 0x0 6. "HAS_DMA,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 5. "INTR_IO,The value of this register is" "0: Individual,1: Combined"
newline
bitfld.long 0x0 4. "HC_COUNT_VALUES,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 2.--3. "MAX_SPEED_MODE,The value of this register is" "0: Reserved,1: Standard,2: Fast,3: High"
newline
bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,The value of this register is" "0: 8 bits,1: 16 bits,2: 32 bits,3: Reserved"
line.long 0x4 "IC_COMP_VERSION,Name: I2C Component Version Register"
hexmask.long 0x4 0.--31. 1. "IC_COMP_VERSION,Specific values for this register are"
line.long 0x8 "IC_COMP_TYPE,Name: I2C Component Type Register"
hexmask.long 0x8 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number"
tree.end
tree.end
tree "IOMGR (I/O Manager Module)"
base ad:0xFFD13000
group.long 0x0++0x9F
line.long 0x0 "pin0sel,HPS Pinmux Select for IO0"
hexmask.long.byte 0x0 0.--3. 1. "val,Select value determines which interface has been selected for IO0. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x4 "pin1sel,HPS Pinmux Select for IO1"
hexmask.long.byte 0x4 0.--3. 1. "val,Select value determines which interface has been selected for IO1. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x8 "pin2sel,HPS Pinmux Select for IO2"
hexmask.long.byte 0x8 0.--3. 1. "val,Select value determines which interface has been selected for IO2. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0xC "pin3sel,HPS Pinmux Select for IO3"
hexmask.long.byte 0xC 0.--3. 1. "val,Select value determines which interface has been selected for IO3. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x10 "pin4sel,HPS Pinmux Select for IO4"
hexmask.long.byte 0x10 0.--3. 1. "val,Select value determines which interface has been selected for IO4. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x14 "pin5sel,HPS Pinmux Select for IO5"
hexmask.long.byte 0x14 0.--3. 1. "val,Select value determines which interface has been selected for IO5. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x18 "pin6sel,HPS Pinmux Select for IO6"
hexmask.long.byte 0x18 0.--3. 1. "val,Select value determines which interface has been selected for IO6. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x1C "pin7sel,HPS Pinmux Select for IO7"
hexmask.long.byte 0x1C 0.--3. 1. "val,Select value determines which interface has been selected for IO7. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x20 "pin8sel,HPS Pinmux Select for IO8"
hexmask.long.byte 0x20 0.--3. 1. "val,Select value determines which interface has been selected for IO8. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x24 "pin9sel,HPS Pinmux Select for IO9"
hexmask.long.byte 0x24 0.--3. 1. "val,Select value determines which interface has been selected for IO9. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x28 "pin10sel,HPS Pinmux Select for IO10"
hexmask.long.byte 0x28 0.--3. 1. "val,Select value determines which interface has been selected for IO10. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x2C "pin11sel,HPS Pinmux Select for IO11"
hexmask.long.byte 0x2C 0.--3. 1. "val,Select value determines which interface has been selected for IO11. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x30 "pin12sel,HPS Pinmux Select for IO12"
hexmask.long.byte 0x30 0.--3. 1. "val,Select value determines which interface has been selected for IO12. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x34 "pin13sel,HPS Pinmux Select for IO13"
hexmask.long.byte 0x34 0.--3. 1. "val,Select value determines which interface has been selected for IO13. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x38 "pin14sel,HPS Pinmux Select for IO14"
hexmask.long.byte 0x38 0.--3. 1. "val,Select value determines which interface has been selected for IO14. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x3C "pin15sel,HPS Pinmux Select for IO15"
hexmask.long.byte 0x3C 0.--3. 1. "val,Select value determines which interface has been selected for IO15. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x40 "pin16sel,HPS Pinmux Select for IO16"
hexmask.long.byte 0x40 0.--3. 1. "val,Select value determines which interface has been selected for IO16. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x44 "pin17sel,HPS Pinmux Select for IO17"
hexmask.long.byte 0x44 0.--3. 1. "val,Select value determines which interface has been selected for IO17. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x48 "pin18sel,HPS Pinmux Select for IO18"
hexmask.long.byte 0x48 0.--3. 1. "val,Select value determines which interface has been selected for IO18. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x4C "pin19sel,HPS Pinmux Select for IO19"
hexmask.long.byte 0x4C 0.--3. 1. "val,Select value determines which interface has been selected for IO19. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x50 "pin20sel,HPS Pinmux Select for IO20"
hexmask.long.byte 0x50 0.--3. 1. "val,Select value determines which interface has been selected for IO20. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x54 "pin21sel,HPS Pinmux Select for IO21"
hexmask.long.byte 0x54 0.--3. 1. "val,Select value determines which interface has been selected for IO21. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x58 "pin22sel,HPS Pinmux Select for IO22"
hexmask.long.byte 0x58 0.--3. 1. "val,Select value determines which interface has been selected for IO22. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x5C "pin23sel,HPS Pinmux Select for IO23"
hexmask.long.byte 0x5C 0.--3. 1. "val,Select value determines which interface has been selected for IO23. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x60 "pin24sel,HPS Pinmux Select for IO0"
hexmask.long.byte 0x60 0.--3. 1. "val,Select value determines which interface has been selected for IO0. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x64 "pin25sel,HPS Pinmux Select for IO1"
hexmask.long.byte 0x64 0.--3. 1. "val,Select value determines which interface has been selected for IO1. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x68 "pin26sel,HPS Pinmux Select for IO2"
hexmask.long.byte 0x68 0.--3. 1. "val,Select value determines which interface has been selected for IO2. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x6C "pin27sel,HPS Pinmux Select for IO3"
hexmask.long.byte 0x6C 0.--3. 1. "val,Select value determines which interface has been selected for IO3. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x70 "pin28sel,HPS Pinmux Select for IO4"
hexmask.long.byte 0x70 0.--3. 1. "val,Select value determines which interface has been selected for IO4. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x74 "pin29sel,HPS Pinmux Select for IO5"
hexmask.long.byte 0x74 0.--3. 1. "val,Select value determines which interface has been selected for IO5. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x78 "pin30sel,HPS Pinmux Select for IO6"
hexmask.long.byte 0x78 0.--3. 1. "val,Select value determines which interface has been selected for IO6. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x7C "pin31sel,HPS Pinmux Select for IO7"
hexmask.long.byte 0x7C 0.--3. 1. "val,Select value determines which interface has been selected for IO7. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x80 "pin32sel,HPS Pinmux Select for IO8"
hexmask.long.byte 0x80 0.--3. 1. "val,Select value determines which interface has been selected for IO8. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x84 "pin33sel,HPS Pinmux Select for IO9"
hexmask.long.byte 0x84 0.--3. 1. "val,Select value determines which interface has been selected for IO9. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x88 "pin34sel,HPS Pinmux Select for IO10"
hexmask.long.byte 0x88 0.--3. 1. "val,Select value determines which interface has been selected for IO10. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x8C "pin35sel,HPS Pinmux Select for IO11"
hexmask.long.byte 0x8C 0.--3. 1. "val,Select value determines which interface has been selected for IO11. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x90 "pin36sel,HPS Pinmux Select for IO12"
hexmask.long.byte 0x90 0.--3. 1. "val,Select value determines which interface has been selected for IO12. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x94 "pin37sel,HPS Pinmux Select for IO13"
hexmask.long.byte 0x94 0.--3. 1. "val,Select value determines which interface has been selected for IO13. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x98 "pin38sel,HPS Pinmux Select for IO14"
hexmask.long.byte 0x98 0.--3. 1. "val,Select value determines which interface has been selected for IO14. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x9C "pin39sel,HPS Pinmux Select for IO15"
hexmask.long.byte 0x9C 0.--3. 1. "val,Select value determines which interface has been selected for IO15. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
group.long 0x100++0x1F
line.long 0x0 "pin40sel,HPS Pinmux Select for IO16"
hexmask.long.byte 0x0 0.--3. 1. "val,Select value determines which interface has been selected for IO16. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x4 "pin41sel,HPS Pinmux Select for IO17"
hexmask.long.byte 0x4 0.--3. 1. "val,Select value determines which interface has been selected for IO17. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x8 "pin42sel,HPS Pinmux Select for IO18"
hexmask.long.byte 0x8 0.--3. 1. "val,Select value determines which interface has been selected for IO18. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0xC "pin43sel,HPS Pinmux Select for IO19"
hexmask.long.byte 0xC 0.--3. 1. "val,Select value determines which interface has been selected for IO19. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x10 "pin44sel,HPS Pinmux Select for IO20"
hexmask.long.byte 0x10 0.--3. 1. "val,Select value determines which interface has been selected for IO20. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x14 "pin45sel,HPS Pinmux Select for IO21"
hexmask.long.byte 0x14 0.--3. 1. "val,Select value determines which interface has been selected for IO21. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x18 "pin46sel,HPS Pinmux Select for IO22"
hexmask.long.byte 0x18 0.--3. 1. "val,Select value determines which interface has been selected for IO22. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x1C "pin47sel,HPS Pinmux Select for IO23"
hexmask.long.byte 0x1C 0.--3. 1. "val,Select value determines which interface has been selected for IO23. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
group.long 0x130++0x6F
line.long 0x0 "io0ctrl,HPS Pinmux Control Value"
bitfld.long 0x0 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0x0 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
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bitfld.long 0x0 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
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bitfld.long 0x0 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x0 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
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bitfld.long 0x0 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x4 "io1ctrl,HPS Pinmux Control Value"
bitfld.long 0x4 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0x4 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
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bitfld.long 0x4 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
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bitfld.long 0x4 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x4 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
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bitfld.long 0x4 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x8 "io2ctrl,HPS Pinmux Control Value"
bitfld.long 0x8 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0x8 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
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bitfld.long 0x8 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
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bitfld.long 0x8 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x8 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
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bitfld.long 0x8 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0xC "io3ctrl,HPS Pinmux Control Value"
bitfld.long 0xC 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0xC 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0xC 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0xC 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0xC 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
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bitfld.long 0xC 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x10 "io4ctrl,HPS Pinmux Control Value"
bitfld.long 0x10 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x10 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x10 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x10 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x10 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x10 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x14 "io5ctrl,HPS Pinmux Control Value"
bitfld.long 0x14 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x14 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x14 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x14 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x14 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x14 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x18 "io6ctrl,HPS Pinmux Control Value"
bitfld.long 0x18 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x18 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x18 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x18 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x18 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x18 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x1C "io7ctrl,HPS Pinmux Control Value"
bitfld.long 0x1C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x1C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x1C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x1C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x1C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x1C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x20 "io8ctrl,HPS Pinmux Control Value"
bitfld.long 0x20 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x20 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x20 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x20 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x20 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x20 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x24 "io9ctrl,HPS Pinmux Control Value"
bitfld.long 0x24 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x24 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x24 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x24 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x24 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x24 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x24 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x28 "io10ctrl,HPS Pinmux Control Value"
bitfld.long 0x28 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x28 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x28 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x28 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x28 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x28 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x2C "io11ctrl,HPS Pinmux Control Value"
bitfld.long 0x2C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x2C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x2C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x2C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x2C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x2C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x30 "io12ctrl,HPS Pinmux Control Value"
bitfld.long 0x30 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x30 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x30 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x30 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x30 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x30 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x34 "io13ctrl,HPS Pinmux Control Value"
bitfld.long 0x34 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x34 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x34 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x34 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x34 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x34 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x38 "io14ctrl,HPS Pinmux Control Value"
bitfld.long 0x38 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0x38 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x38 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x38 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x38 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x38 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x3C "io15ctrl,HPS Pinmux Control Value"
bitfld.long 0x3C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x3C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x3C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x3C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x3C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x3C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x3C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x40 "io16ctrl,HPS Pinmux Control Value"
bitfld.long 0x40 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x40 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x40 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x40 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x40 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x40 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x40 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x44 "io17ctrl,HPS Pinmux Control Value"
bitfld.long 0x44 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x44 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x44 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x44 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x44 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x44 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x44 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x48 "io18ctrl,HPS Pinmux Control Value"
bitfld.long 0x48 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x48 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x48 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x48 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x48 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x48 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x48 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x4C "io19ctrl,HPS Pinmux Control Value"
bitfld.long 0x4C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x4C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x4C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x4C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x4C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x4C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x50 "io20ctrl,HPS Pinmux Control Value"
bitfld.long 0x50 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x50 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x50 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x50 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x50 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x50 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x50 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x54 "io21ctrl,HPS Pinmux Control Value"
bitfld.long 0x54 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x54 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x54 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x54 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x54 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x54 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x54 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x58 "io22ctrl,HPS Pinmux Control Value"
bitfld.long 0x58 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x58 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x58 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x58 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x58 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x58 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x58 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x5C "io23ctrl,HPS Pinmux Control Value"
bitfld.long 0x5C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x5C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x5C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x5C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x5C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x5C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x5C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x60 "io24ctrl,HPS Pinmux Control Value"
bitfld.long 0x60 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x60 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x60 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x60 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x60 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x60 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x60 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x64 "io25ctrl,HPS Pinmux Control Value"
bitfld.long 0x64 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x64 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x64 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x64 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x64 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x64 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x64 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x68 "io26ctrl,HPS Pinmux Control Value"
bitfld.long 0x68 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x68 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x68 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x68 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x68 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x68 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x68 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x6C "io27ctrl,HPS Pinmux Control Value"
bitfld.long 0x6C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0x6C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x6C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x6C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
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bitfld.long 0x6C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x6C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x6C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
group.long 0x200++0x4F
line.long 0x0 "io28ctrl,HPS Pinmux Control Value"
bitfld.long 0x0 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0x0 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x0 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x0 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x0 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x0 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x4 "io29ctrl,HPS Pinmux Control Value"
bitfld.long 0x4 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0x4 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x4 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
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bitfld.long 0x4 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x4 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x4 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x8 "io30ctrl,HPS Pinmux Control Value"
bitfld.long 0x8 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0x8 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x8 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x8 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x8 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x8 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0xC "io31ctrl,HPS Pinmux Control Value"
bitfld.long 0xC 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0xC 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0xC 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0xC 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0xC 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0xC 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x10 "io32ctrl,HPS Pinmux Control Value"
bitfld.long 0x10 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x10 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x10 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x10 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x10 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x10 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x14 "io33ctrl,HPS Pinmux Control Value"
bitfld.long 0x14 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x14 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x14 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x14 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x14 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x14 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x18 "io34ctrl,HPS Pinmux Control Value"
bitfld.long 0x18 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x18 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x18 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x18 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x18 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x18 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x1C "io35ctrl,HPS Pinmux Control Value"
bitfld.long 0x1C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x1C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x1C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x1C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x1C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x1C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x20 "io36ctrl,HPS Pinmux Control Value"
bitfld.long 0x20 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x20 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x20 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x20 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x20 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x20 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x24 "io37ctrl,HPS Pinmux Control Value"
bitfld.long 0x24 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x24 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x24 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x24 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x24 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x24 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x24 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x28 "io38ctrl,HPS Pinmux Control Value"
bitfld.long 0x28 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x28 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x28 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x28 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x28 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x28 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x2C "io39ctrl,HPS Pinmux Control Value"
bitfld.long 0x2C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x2C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x2C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x2C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x2C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x2C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x30 "io40ctrl,HPS Pinmux Control Value"
bitfld.long 0x30 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x30 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x30 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x30 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x30 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x30 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x34 "io41ctrl,HPS Pinmux Control Value"
bitfld.long 0x34 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x34 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x34 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x34 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x34 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x34 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x38 "io42ctrl,HPS Pinmux Control Value"
bitfld.long 0x38 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x38 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x38 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x38 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x38 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x38 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x3C "io43ctrl,HPS Pinmux Control Value"
bitfld.long 0x3C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x3C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x3C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x3C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x3C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x3C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x3C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x40 "io44ctrl,HPS Pinmux Control Value"
bitfld.long 0x40 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x40 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x40 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x40 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x40 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x40 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x40 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x44 "io45ctrl,HPS Pinmux Control Value"
bitfld.long 0x44 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x44 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x44 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x44 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x44 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x44 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x44 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x48 "io46ctrl,HPS Pinmux Control Value"
bitfld.long 0x48 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x48 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x48 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x48 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x48 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x48 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x48 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x4C "io47ctrl,HPS Pinmux Control Value"
bitfld.long 0x4C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x4C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x4C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x4C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x4C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x4C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
group.long 0x300++0x23
line.long 0x0 "pinmux_emac0_usefpga,Selection between HPS Pin and FPGA Interface for EMAC0 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0x0 0. "sel,Select connection for EMAC0." "0: EMAC0 uses HPS IO Pins.,1: EMAC0 uses the FPGA Inteface."
line.long 0x4 "pinmux_emac1_usefpga,Selection between HPS Pin and FPGA Interface for EMAC1 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0x4 0. "sel,Select connection for EMAC1." "0: EMAC1 uses HPS IO Pins.,1: EMAC1 uses the FPGA Inteface."
line.long 0x8 "pinmux_emac2_usefpga,Selection between HPS Pin and FPGA Interface for EMAC2 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0x8 0. "sel,Select connection for EMAC2." "0: EMAC2 uses HPS IO Pins.,1: EMAC2 uses the FPGA Inteface."
line.long 0xC "pinmux_i2c0_usefpga,Selection between HPS Pin and FPGA Interface for I2C0 signals."
bitfld.long 0xC 0. "sel,Select connection for I2C0." "0: I2C0 uses HPS IO Pins.,1: I2C0 uses the FPGA Inteface."
line.long 0x10 "pinmux_i2c1_usefpga,Selection between HPS Pin and FPGA Interface for I2C1 signals."
bitfld.long 0x10 0. "sel,Select connection for I2C1." "0: I2C1 uses HPS IO Pins.,1: I2C1uses the FPGA Inteface."
line.long 0x14 "pinmux_i2c_emac0_usefpga,Selection between HPS Pin and FPGA Interface for I2C_EMAC0 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0x14 0. "sel,Select connection for I2C_EMAC0." "0: I2C_EMAC0 uses HPS IO Pins.,1: I2C_EMAC0 uses the FPGA Inteface."
line.long 0x18 "pinmux_i2c_emac1_usefpga,Selection between HPS Pin and FPGA Interface for I2C_EMAC1 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0x18 0. "sel,Select connection for I2C_EMAC1." "0: I2C_EMAC1 uses HPS IO Pins.,1: I2C_EMAC1uses the FPGA Inteface."
line.long 0x1C "pinmux_i2c_emac2_usefpga,Selection between HPS Pin and FPGA Interface for I2C_EMAC2 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0x1C 0. "sel,Select connection for I2C_EMAC2." "0: I2C_EMAC2 uses HPS IO Pins.,1: I2C_EMAC2uses the FPGA Inteface."
line.long 0x20 "pinmux_nand_usefpga,Selection between HPS Pin and FPGA Interface for NAND signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0x20 0. "sel,Select connection for NAND." "0: NAND uses HPS IO Pins.,1: NAND uses the FPGA Inteface."
group.long 0x328++0x23
line.long 0x0 "pinmux_spim0_usefpga,Selection between HPS Pin and FPGA Interface for SPIM0 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0x0 0. "sel,Select connection for SPIM0." "0: SPIM0 uses HPS IO Pins.,1: SPIM0 uses the FPGA Inteface."
line.long 0x4 "pinmux_spim1_usefpga,Selection between HPS Pin and FPGA Interface for SPIM1 signals."
bitfld.long 0x4 0. "sel,Select connection for SPIM1." "0: SPIM1 uses HPS IO Pins.,1: SPIM1uses the FPGA Inteface."
line.long 0x8 "pinmux_spis0_usefpga,Selection between HPS Pin and FPGA Interface for SPIS0 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0x8 0. "sel,Select connection for SPIS0." "0: SPIS0 uses HPS IO Pins.,1: SPIS0 uses the FPGA Inteface."
line.long 0xC "pinmux_spis1_usefpga,Selection between HPS Pin and FPGA Interface for SPIS1 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0xC 0. "sel,Select connection for SPIS1." "0: SPIS1 uses HPS IO Pins.,1: SPIS1uses the FPGA Inteface."
line.long 0x10 "pinmux_uart0_usefpga,Selection between HPS Pin and FPGA Interface for UART0 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0x10 0. "sel,Select connection for UART0." "0: UART0 uses HPS IO Pins.,1: UART0 uses the FPGA Inteface."
line.long 0x14 "pinmux_uart1_usefpga,Selection between HPS Pin and FPGA Interface for UART1 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0x14 0. "sel,Select connection for UART1." "0: UART1 uses HPS IO Pins.,1: UART1uses the FPGA Inteface."
line.long 0x18 "pinmux_mdio0_usefpga,Selection between HPS Pin and FPGA Interface for MDIO0 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0x18 0. "sel,Select connection for MDIO0." "0: MDIO0 uses HPS IO Pins.,1: MDIO0 uses the FPGA Inteface."
line.long 0x1C "pinmux_mdio1_usefpga,Selection between HPS Pin and FPGA Interface for MDIO1 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0x1C 0. "sel,Select connection for MDIO1." "0: MDIO1 uses HPS IO Pins.,1: MDIO1uses the FPGA Inteface."
line.long 0x20 "pinmux_mdio2_usefpga,Selection between HPS Pin and FPGA Interface for MDIO2 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0x20 0. "sel,Select connection for MDIO2." "0: MDIO2 uses HPS IO Pins.,1: MDIO2 uses the FPGA Inteface."
group.long 0x350++0x7
line.long 0x0 "pinmux_jtag_usefpga,Selection between HPS Pin and FPGA Interface for JTAG signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0x0 0. "sel,Select connection for JTAG." "0: JTAG uses HPS IO Pins.,1: JTAG uses the FPGA Inteface."
line.long 0x4 "pinmux_sdmmc_usefpga,Selection between HPS Pin and FPGA Interface for SDMMC signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
bitfld.long 0x4 0. "sel,Select connection for SDMMC." "0: SDMMC uses HPS IO Pins.,1: SDMMC uses the FPGA Inteface."
group.long 0x400++0xBF
line.long 0x0 "io0_delay,Adds the delay chains in IO0."
bitfld.long 0x0 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x0 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0x0 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x0 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x4 "io1_delay,Adds the delay chains in IO1."
bitfld.long 0x4 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x4 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0x4 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x4 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x8 "io2_delay,Adds the delay chains in IO2."
bitfld.long 0x8 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x8 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0x8 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x8 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xC "io3_delay,Adds the delay chains in IO3."
bitfld.long 0xC 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xC 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0xC 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xC 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x10 "io4_delay,Adds the delay chains in IO4."
bitfld.long 0x10 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x10 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0x10 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x10 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x14 "io5_delay,Adds the delay chains in IO5."
bitfld.long 0x14 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x14 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0x14 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x14 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x18 "io6_delay,Adds the delay chains in IO6."
bitfld.long 0x18 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x18 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0x18 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x18 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x1C "io7_delay,Adds the delay chains in IO7."
bitfld.long 0x1C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x1C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0x1C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x1C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x20 "io8_delay,Adds the delay chains in IO8."
bitfld.long 0x20 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x20 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0x20 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x20 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x24 "io9_delay,Adds the delay chains in IO9."
bitfld.long 0x24 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x24 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0x24 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x24 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x28 "io10_delay,Adds the delay chains in IO10."
bitfld.long 0x28 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x28 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0x28 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x28 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x2C "io11_delay,Adds the delay chains in IO11."
bitfld.long 0x2C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x2C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x2C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x2C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x30 "io12_delay,Adds the delay chains in IO12."
bitfld.long 0x30 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x30 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x30 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x30 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x34 "io13_delay,Adds the delay chains in IO13."
bitfld.long 0x34 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x34 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x34 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x34 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x38 "io14_delay,Adds the delay chains in IO14."
bitfld.long 0x38 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x38 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x38 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x38 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x3C "io15_delay,Adds the delay chains in IO15."
bitfld.long 0x3C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x3C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x3C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x3C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x40 "io16_delay,Adds the delay chains in IO16."
bitfld.long 0x40 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x40 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x40 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x40 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x44 "io17_delay,Adds the delay chains in IO17."
bitfld.long 0x44 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x44 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x44 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x44 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x48 "io18_delay,Adds the delay chains in IO18."
bitfld.long 0x48 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x48 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x48 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x48 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x4C "io19_delay,Adds the delay chains in IO19."
bitfld.long 0x4C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x4C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x4C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x4C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x50 "io20_delay,Adds the delay chains in IO20."
bitfld.long 0x50 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x50 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x50 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x50 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x54 "io21_delay,Adds the delay chains in IO21."
bitfld.long 0x54 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x54 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x54 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x54 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x58 "io22_delay,Adds the delay chains in IO22."
bitfld.long 0x58 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x58 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x58 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x58 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x5C "io23_delay,Adds the delay chains in IO23."
bitfld.long 0x5C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x5C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x5C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x5C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x60 "io24_delay,Adds the delay chains in IO24."
bitfld.long 0x60 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x60 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x60 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x60 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x64 "io25_delay,Adds the delay chains in IO25."
bitfld.long 0x64 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x64 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x64 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x64 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x68 "io26_delay,Adds the delay chains in IO26."
bitfld.long 0x68 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x68 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x68 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x68 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x6C "io27_delay,Adds the delay chains in IO27."
bitfld.long 0x6C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x6C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x6C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x6C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x70 "io28_delay,Adds the delay chains in IO28."
bitfld.long 0x70 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x70 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x70 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x70 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x74 "io29_delay,Adds the delay chains in IO29."
bitfld.long 0x74 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x74 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x74 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x74 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x78 "io30_delay,Adds the delay chains in IO30."
bitfld.long 0x78 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x78 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x78 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x78 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x7C "io31_delay,Adds the delay chains in IO31."
bitfld.long 0x7C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x7C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x7C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x7C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x80 "io32_delay,Adds the delay chains in IO32."
bitfld.long 0x80 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x80 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x80 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x80 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x84 "io33_delay,Adds the delay chains in IO33."
bitfld.long 0x84 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x84 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x84 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x84 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x88 "io34_delay,Adds the delay chains in IO34."
bitfld.long 0x88 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x88 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x88 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x88 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x8C "io35_delay,Adds the delay chains in IO35."
bitfld.long 0x8C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x8C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x8C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x8C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x90 "io36_delay,Adds the delay chains in IO36."
bitfld.long 0x90 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x90 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x90 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x90 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x94 "io37_delay,Adds the delay chains in IO37."
bitfld.long 0x94 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x94 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x94 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x94 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x98 "io38_delay,Adds the delay chains in IO38."
bitfld.long 0x98 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x98 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x98 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x98 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x9C "io39_delay,Adds the delay chains in IO39."
bitfld.long 0x9C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x9C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0x9C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x9C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xA0 "io40_delay,Adds the delay chains in IO40."
bitfld.long 0xA0 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0xA0 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
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bitfld.long 0xA0 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0xA0 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xA4 "io41_delay,Adds the delay chains in IO41."
bitfld.long 0xA4 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0xA4 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0xA4 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xA4 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xA8 "io42_delay,Adds the delay chains in IO42."
bitfld.long 0xA8 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xA8 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0xA8 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xA8 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xAC "io43_delay,Adds the delay chains in IO43."
bitfld.long 0xAC 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xAC 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0xAC 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xAC 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xB0 "io44_delay,Adds the delay chains in IO44."
bitfld.long 0xB0 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xB0 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0xB0 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xB0 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xB4 "io45_delay,Adds the delay chains in IO45."
bitfld.long 0xB4 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xB4 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0xB4 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xB4 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xB8 "io46_delay,Adds the delay chains in IO46."
bitfld.long 0xB8 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xB8 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0xB8 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xB8 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xBC "io47_delay,Adds the delay chains in IO47."
bitfld.long 0xBC 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xBC 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
bitfld.long 0xBC 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xBC 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
tree.end
tree "L4FRW (L4 Interconnect Firewall CSR)"
base ad:0x0
tree "L4_PER (L4_PER Security Control Registers)"
base ad:0xFFD21000
group.long 0x0++0x7
line.long 0x0 "nand_register,Per-Master Security bit for nand register"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to nand_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to nand_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to nand_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "nand_data,Per-Master Security bit for nand_data"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to nand_data. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to nand_data. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to nand_data. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0xC++0x7
line.long 0x0 "usb0_register,Per-Master Security bit for usb0_register"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to usb0_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to usb0_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to usb0_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "usb1_register,Per-Master Security bit for usb1_register"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to usb1_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to usb1_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to usb1_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0x1C++0x1B
line.long 0x0 "spi_master0,Per-Master Security bit for spi_master0"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to spi_master0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to spi_master0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 8. "dma,Security bit configuration for transactions from dma to spi_master0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to spi_master0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "spi_master1,Per-Master Security bit for spi_master1"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to spi_master1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to spi_master1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 8. "dma,Security bit configuration for transactions from dma to spi_master1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to spi_master1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x8 "spi_slave0,Per-Master Security bit for spi_slave0"
bitfld.long 0x8 24. "axi_ap,Security bit configuration for transactions from axi_ap to spi_slave0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to spi_slave0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 8. "dma,Security bit configuration for transactions from dma to spi_slave0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 0. "mpu,Security bit configuration for transactions from mpu to spi_slave0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0xC "spi_slave1,Per-Master Security bit for spi_slave1"
bitfld.long 0xC 24. "axi_ap,Security bit configuration for transactions from axi_ap to spi_slave1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to spi_slave1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 8. "dma,Security bit configuration for transactions from dma to spi_slave1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 0. "mpu,Security bit configuration for transactions from mpu to spi_slave1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x10 "emac0,Per-Master Security bit for emac0"
bitfld.long 0x10 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x10 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x10 0. "mpu,Security bit configuration for transactions from mpu to emac0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x14 "emac1,Per-Master Security bit for emac1"
bitfld.long 0x14 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x14 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x14 0. "mpu,Security bit configuration for transactions from mpu to emac1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x18 "emac2,Per-Master Security bit for emac2"
bitfld.long 0x18 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x18 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x18 0. "mpu,Security bit configuration for transactions from mpu to emac2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0x40++0xB
line.long 0x0 "sdmmc,Per-Master Security bit for sdmmc"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to sdmmc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to sdmmc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to sdmmc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "gpio0,Per-Master Security bit for gpio0"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to gpio0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to gpio0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 8. "dma,Security bit configuration for transactions from dma to gpio0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to gpio0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x8 "gpio1,Per-Master Security bit for gpio1"
bitfld.long 0x8 24. "axi_ap,Security bit configuration for transactions from axi_ap to gpio1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to gpio1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 8. "dma,Security bit configuration for transactions from dma to gpio1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 0. "mpu,Security bit configuration for transactions from mpu to gpio1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0x50++0x23
line.long 0x0 "i2c0,Per-Master Security bit for i2c0"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to i2c0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to i2c0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 8. "dma,Security bit configuration for transactions from dma to i2c0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to i2c0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "i2c1,Per-Master Security bit for i2c1"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to i2c1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to i2c1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 8. "dma,Security bit configuration for transactions from dma to i2c1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to i2c1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x8 "i2c2,Per-Master Security bit for i2c2"
bitfld.long 0x8 24. "axi_ap,Security bit configuration for transactions from axi_ap to i2c2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to i2c2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 8. "dma,Security bit configuration for transactions from dma to i2c2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 0. "mpu,Security bit configuration for transactions from mpu to i2c2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0xC "i2c3,Per-Master Security bit for i2c3"
bitfld.long 0xC 24. "axi_ap,Security bit configuration for transactions from axi_ap to i2c3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to i2c3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 8. "dma,Security bit configuration for transactions from dma to i2c3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 0. "mpu,Security bit configuration for transactions from mpu to i2c3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x10 "i2c4,Per-Master Security bit for i2c4"
bitfld.long 0x10 24. "axi_ap,Security bit configuration for transactions from axi_ap to. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x10 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to i2c4. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x10 8. "dma,Security bit configuration for transactions from dma to i2c4. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x10 0. "mpu,Security bit configuration for transactions from mpu to i2c4. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x14 "sp_timer0,Per-Master Security bit for sp_timer0"
bitfld.long 0x14 24. "axi_ap,Security bit configuration for transactions from axi_ap to sp_timer0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x14 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to sp_timer0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x14 8. "dma,Security bit configuration for transactions from dma to sp_timer0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x14 0. "mpu,Security bit configuration for transactions from mpu to sp_timer0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x18 "sp_timer1,Per-Master Security bit for sp_timer1"
bitfld.long 0x18 24. "axi_ap,Security bit configuration for transactions from axi_ap to sp_timer1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x18 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to sp_timer1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x18 8. "dma,Security bit configuration for transactions from dma to sp_timer1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x18 0. "mpu,Security bit configuration for transactions from mpu to sp_timer1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x1C "uart0,Per-Master Security bit for uart0"
bitfld.long 0x1C 24. "axi_ap,Security bit configuration for transactions from axi_ap to uart0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x1C 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to uart0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x1C 8. "dma,Security bit configuration for transactions from dma to uart0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x1C 0. "mpu,Security bit configuration for transactions from mpu to uart0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x20 "uart1,Per-Master Security bit for uart1"
bitfld.long 0x20 24. "axi_ap,Security bit configuration for transactions from axi_ap to uart1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x20 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to uart1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x20 8. "dma,Security bit configuration for transactions from dma to uart1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x20 0. "mpu,Security bit configuration for transactions from mpu to uart1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
tree.end
tree "L4_PRIV (L4 Privilege Filter)"
base ad:0xFFD24800
group.long 0x0++0x3
line.long 0x0 "priv,This register controls access to various Peripherals depending on the privilege setting. By default. all slaves will be assumed as Privileged. To allow non-Privileged access to a slave. the corresponding bit for the slave must be set. Once set. both.."
bitfld.long 0x0 31. "tcu,Privilege bit for TCU slave. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 30. "soc2fpga,Privilege bit for SOC2FPGA. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 29. "lwsoc2fpga,Privilege bit for Lightweight SOC2FPGA. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 28. "uart1,Privilege bit for uart1. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 27. "uart0,Privilege bit for uart0. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 26. "sp_timer1,Privilege bit for sp_timer1. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 25. "sp_timer0,Privilege bit for sp_timer0. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 24. "i2c4,Privilege bit for i2c4. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
newline
bitfld.long 0x0 23. "i2c3,Privilege bit for i2c3. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 22. "i2c2,Privilege bit for i2c2. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 21. "i2c1,Privilege bit for i2c1. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 20. "i2c0,Privilege bit for i2c0. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 18. "gpio1,Privilege bit for gpio1. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 17. "gpio0,Privilege bit for gpio0. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 16. "sdmmc,Privilege bit for sdmmc. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 13. "emac2,Privilege bit for emac2. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
newline
bitfld.long 0x0 12. "emac1,Privilege bit for emac1. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 11. "emac0,Privilege bit for emac0. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 10. "spi_slave1,Privilege bit for spi_slave1. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 9. "spi_slave0,Privilege bit for spi_slave0. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 8. "spi_master1,Privilege bit for spi_master1. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 7. "spi_master0,Privilege bit for spi_master0. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 6. "dma_secure,Privilege bit for dma_secure. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 5. "dma_nonsecure,Privilege bit for dma_nonsecure. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
newline
bitfld.long 0x0 4. "usb1_register,Privilege bit for usb1_register. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 3. "usb0_register,Privilege bit for usb0_register. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 1. "nand_data,Privilege bit for nand_data. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
bitfld.long 0x0 0. "nand_register,Privilege bit for nand register. When 0  only privileged transactions are allowed to slave. When 1  both privileged and non-privileged transactions are allowed to slave" "0,1"
wgroup.long 0x4++0x7
line.long 0x0 "priv_set,Sets Region Enable field when written with 1"
bitfld.long 0x0 31. "tcu,Privilege bit for TCU slave. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 30. "soc2fpga,Privilege bit for SOC2FPGA. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 29. "lwsoc2fpga,Privilege bit for Lightweight SOC2FPGA. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 28. "uart1,Privilege bit for uart1. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 27. "uart0,Privilege bit for uart0. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 26. "sp_timer1,Privilege bit for sp_timer1. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 25. "sp_timer0,Privilege bit for sp_timer0. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 24. "i2c4,Privilege bit for i2c4. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
newline
bitfld.long 0x0 23. "i2c3,Privilege bit for i2c3. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 22. "i2c2,Privilege bit for i2c2. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 21. "i2c1,Privilege bit for i2c1. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 20. "i2c0,Privilege bit for i2c0. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 18. "gpio1,Privilege bit for gpio1. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 17. "gpio0,Privilege bit for gpio0. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 16. "sdmmc,Privilege bit for sdmmc. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 13. "emac2,Privilege bit for emac2. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
newline
bitfld.long 0x0 12. "emac1,Privilege bit for emac1. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 11. "emac0,Privilege bit for emac0. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 10. "spi_slave1,Privilege bit for spi_slave1. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 9. "spi_slave0,Privilege bit for spi_slave0. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 8. "spi_master1,Privilege bit for spi_master1. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 7. "spi_master0,Privilege bit for spi_master0. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 6. "dma_secure,Privilege bit for dma_secure. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 5. "dma_nonsecure,Privilege bit for dma_nonsecure. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
newline
bitfld.long 0x0 4. "usb1_register,Privilege bit for usb1_register. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 3. "usb0_register,Privilege bit for usb0_register. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 1. "nand_data,Privilege bit for nand_data. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
bitfld.long 0x0 0. "nand_register,Privilege bit for nand register. Writing zero has no effect. Writing one will set the privilege bit" "0,1"
line.long 0x4 "priv_clear,Clears Region Enable field when written with 1"
eventfld.long 0x4 31. "tcu,Privilege bit for TCU slave. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 30. "soc2fpga,Privilege bit for SOC2FPGA. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 29. "lwsoc2fpga,Privilege bit for Lightweight SOC2FPGA. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 28. "uart1,Privilege bit for uart1. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 27. "uart0,Privilege bit for uart0. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 26. "sp_timer1,Privilege bit for sp_timer1. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 25. "sp_timer0,Privilege bit for sp_timer0. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 24. "i2c4,Privilege bit for i2c4. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
newline
eventfld.long 0x4 23. "i2c3,Privilege bit for i2c3. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 22. "i2c2,Privilege bit for i2c2. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 21. "i2c1,Privilege bit for i2c1. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 20. "i2c0,Privilege bit for i2c0. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 18. "gpio1,Privilege bit for gpio1. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 17. "gpio0,Privilege bit for gpio0. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 16. "sdmmc,Privilege bit for sdmmc. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 13. "emac2,Privilege bit for emac2. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
newline
eventfld.long 0x4 12. "emac1,Privilege bit for emac1. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 11. "emac0,Privilege bit for emac0. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 10. "spi_slave1,Privilege bit for spi_slave1. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 9. "spi_slave0,Privilege bit for spi_slave0. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 8. "spi_master1,Privilege bit for spi_master1. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 7. "spi_master0,Privilege bit for spi_master0. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 6. "dma_secure,Privilege bit for dma_secure. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 5. "dma_nonsecure,Privilege bit for dma_nonsecure. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
newline
eventfld.long 0x4 4. "usb1_register,Privilege bit for usb1_register. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 3. "usb0_register,Privilege bit for usb0_register. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 1. "nand_data,Privilege bit for nand_data. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
eventfld.long 0x4 0. "nand_register,Privilege bit for nand register. Writing zero has no effect. Writing one will clear the privilege bit" "0,1"
tree.end
tree "L4_SYS (L4_SYS Security Control Registers)"
base ad:0xFFD21100
group.long 0x8++0x1B
line.long 0x0 "dma_ecc,Per-Master Security bit for dma_ecc"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to dma_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to dma_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to dma_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "emac0rx_ecc,Per-Master Security bit for emac0rx_ecc"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac0rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac0rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to emac0rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x8 "emac0tx_ecc,Per-Master Security bit for emac0tx_ecc"
bitfld.long 0x8 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac0tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac0tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 0. "mpu,Security bit configuration for transactions from mpu to emac0tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0xC "emac1rx_ecc,Per-Master Security bit for emac1rx_ecc"
bitfld.long 0xC 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac1rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac1rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 0. "mpu,Security bit configuration for transactions from mpu to emac1rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x10 "emac1tx_ecc,Per-Master Security bit for emac1tx_ecc"
bitfld.long 0x10 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac1tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x10 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac1tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x10 0. "mpu,Security bit configuration for transactions from mpu to emac1tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x14 "emac2rx_ecc,Per-Master Security bit for emac2rx_ecc"
bitfld.long 0x14 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac2rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x14 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac2rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x14 0. "mpu,Security bit configuration for transactions from mpu to emac2rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x18 "emac2tx_ecc,Per-Master Security bit for emac2tx_ecc"
bitfld.long 0x18 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac2tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x18 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac2tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x18 0. "mpu,Security bit configuration for transactions from mpu to emac2tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0x2C++0xF
line.long 0x0 "nand_ecc,Per-Master Security bit for nand_ecc"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to nand_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to nand_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to nand_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "nand_read_ecc,Per-Master Security bit for nand_read_ecc"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to nand_read_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to nand_read_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to nand_read_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x8 "nand_write_ecc,Per-Master Security bit for nand_write_ecc"
bitfld.long 0x8 24. "axi_ap,Security bit configuration for transactions from axi_ap to nand_write_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to nand_write_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 0. "mpu,Security bit configuration for transactions from mpu to nand_write_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0xC "ocram_ecc,Per-Master Security bit for onchipram_ecc"
bitfld.long 0xC 24. "axi_ap,Security bit configuration for transactions from axi_ap to onchipram_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to onchipram_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 0. "mpu,Security bit configuration for transactions from mpu to onchipram_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0x40++0xF
line.long 0x0 "sdmmc_ecc,Per-Master Security bit for sdmmc_ecc"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to sdmmc_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to sdmmc_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to sdmmc_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "usb0_ecc,Per-Master Security bit for usb0_ecc"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to usb0_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to usb0_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to usb0_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x8 "usb1_ecc,Per-Master Security bit for usb1_ecc"
bitfld.long 0x8 24. "axi_ap,Security bit configuration for transactions from axi_ap to usb1_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to usb1_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 0. "mpu,Security bit configuration for transactions from mpu to usb1_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0xC "clock_manager,Per-Master Security bit for clock_manager"
bitfld.long 0xC 24. "axi_ap,Security bit configuration for transactions from axi_ap to clock_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to clock_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 0. "mpu,Security bit configuration for transactions from mpu to clock_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0x54++0x27
line.long 0x0 "io_manager,Per-Master Security bit for pin_mux_register"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to pin_mux_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to pin_mux_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to pin_mux_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "reset_manager,Per-Master Security bit for reset_manager"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to reset_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to reset_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to reset_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x8 "system_manager,Per-Master Security bit for system_manager"
bitfld.long 0x8 24. "axi_ap,Security bit configuration for transactions from axi_ap to system_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to system_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 0. "mpu,Security bit configuration for transactions from mpu to system_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0xC "osc0_timer,Per-Master Security bit for osc0_timer"
bitfld.long 0xC 24. "axi_ap,Security bit configuration for transactions from axi_ap to osc0_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to osc0_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 8. "dma,Security bit configuration for transactions from dma to osc0_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 0. "mpu,Security bit configuration for transactions from mpu to osc0_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x10 "osc1_timer,Per-Master Security bit for osc1_timer"
bitfld.long 0x10 24. "axi_ap,Security bit configuration for transactions from axi_ap to osc1_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x10 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to osc1_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x10 8. "dma,Security bit configuration for transactions from dma to osc1_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x10 0. "mpu,Security bit configuration for transactions from mpu to osc1_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x14 "watchdog0,Per-Master Security bit for watchdog0"
bitfld.long 0x14 24. "axi_ap,Security bit configuration for transactions from axi_ap to watchdog0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x14 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to watchdog0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x14 8. "dma,Security bit configuration for transactions from dma to watchdog0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x14 0. "mpu,Security bit configuration for transactions from mpu to watchdog0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x18 "watchdog1,Per-Master Security bit for watchdog1"
bitfld.long 0x18 24. "axi_ap,Security bit configuration for transactions from axi_ap to watchdog1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x18 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to watchdog1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x18 8. "dma,Security bit configuration for transactions from dma to watchdog1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x18 0. "mpu,Security bit configuration for transactions from mpu to watchdog1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x1C "watchdog2,Per-Master Security bit for watchdog0"
bitfld.long 0x1C 24. "axi_ap,Security bit configuration for transactions from axi_ap to watchdog2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x1C 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to watchdog2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x1C 8. "dma,Security bit configuration for transactions from dma to watchdog2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x1C 0. "mpu,Security bit configuration for transactions from mpu to watchdog2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x20 "watchdog3,Per-Master Security bit for watchdog1"
bitfld.long 0x20 24. "axi_ap,Security bit configuration for transactions from axi_ap to watchdog3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x20 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to watchdog3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x20 8. "dma,Security bit configuration for transactions from dma to watchdog3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x20 0. "mpu,Security bit configuration for transactions from mpu to watchdog3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x24 "dap,Per-Master Security bit for dap"
bitfld.long 0x24 25. "etr,Security bit configuration for transactions from etr to dap. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x24 24. "axi_ap,Security bit configuration for transactions from axi_ap to dap. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x24 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to dap. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x24 0. "mpu,Security bit configuration for transactions from mpu to dap. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0x90++0x7
line.long 0x0 "l4_noc_probes,Per-Master Security bit for noc_probes_register"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to noc_probes_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to noc_probes_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to noc_probes_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "l4_noc_qos,Per-Master Security bit for noc_probes_register"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to noc_probes_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to noc_probes_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to noc_probes_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
tree.end
tree "L4_TCU (TCU Security Control Registers)"
base ad:0xFFD21400
group.long 0x0++0x3
line.long 0x0 "tcu,Per-Master Security bit for dma_ecc"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to dma_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to dma_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to dma_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
tree.end
tree "LWSOC2FPGA (Lightweight SOC2FPGA Security Control Registers)"
base ad:0xFFD21300
group.long 0x0++0x3
line.long 0x0 "lwsoc2fpga,Per-Master Security bit for Lightweight SOC2FPGA"
bitfld.long 0x0 27. "sdm_nand,Security bit configuration for transactions from SDM NAND to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 26. "sdm_sdmmc,Security bit configuration for transactions from SDM SDMMC to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 25. "etr,Security bit configuration for transactions from etr to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 23. "nand,Security bit configuration for transactions from nand to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 22. "sdmmc,Security bit configuration for transactions from sdmmc to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 21. "usb1,Security bit configuration for transactions from usb1 to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 20. "usb0,Security bit configuration for transactions from usb0 to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 19. "emac2,Security bit configuration for transactions from emac2 to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 18. "emac1,Security bit configuration for transactions from emac1 to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
newline
bitfld.long 0x0 17. "emac0,Security bit configuration for transactions from emac0 to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 8. "dma,Security bit configuration for transactions from dma to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
tree.end
tree "SOC2FPGA (SOC2FPGA Security Control Registers)"
base ad:0xFFD21200
group.long 0x0++0x3
line.long 0x0 "soc2fpga,Per-Master Security bit for SOC2FPGA"
bitfld.long 0x0 27. "sdm_nand,Security bit configuration for transactions from SDM NAND to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 26. "sdm_sdmmc,Security bit configuration for transactions from SDM SDMMC to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 25. "etr,Security bit configuration for transactions from etr to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 23. "nand,Security bit configuration for transactions from nand to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 22. "sdmmc,Security bit configuration for transactions from sdmmc to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 21. "usb1,Security bit configuration for transactions from usb1 to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 20. "usb0,Security bit configuration for transactions from usb0 to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 19. "emac2,Security bit configuration for transactions from emac2 to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 18. "emac1,Security bit configuration for transactions from emac1 to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
newline
bitfld.long 0x0 17. "emac0,Security bit configuration for transactions from emac0 to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 8. "dma,Security bit configuration for transactions from dma to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
tree.end
tree.end
tree "L4WD (Watchdog Module)"
base ad:0x0
tree "L4WD0 (Watchdog0 Module)"
base ad:0xFFD00200
group.long 0x0++0x7
line.long 0x0 "WDT_CR,Control Register"
bitfld.long 0x0 2.--4. "RPL,Reset pulse length. Writes have no effect when the configuration parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 1. "RMOD,Response mode. Writes have no effect when the parameter" "0: Generate a system reset,1: First generate an interrupt and if it is not.."
newline
bitfld.long 0x0 0. "WDT_EN,When the configuration parameter WDT_ALWAYS_EN = 0  this bit can be set" "0: WDT disabled,1: WDT enabled"
line.long 0x4 "WDT_TORR,Timeout Range Register"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved,Reserved and read as 0."
hexmask.long.byte 0x4 4.--7. 1. "TOP_INIT,Timeout period for initialization."
newline
hexmask.long.byte 0x4 0.--3. 1. "TOP,Timeout period. Writes have no effect when the configuration parameter"
rgroup.long 0x8++0x3
line.long 0x0 "WDT_CCVR,Current Counter Value Register."
hexmask.long 0x0 0.--31. 1. "wdt_ccvr,This register  when read  is the current value of the internal"
wgroup.long 0xC++0x3
line.long 0x0 "WDT_CRR,Counter Restart Register."
hexmask.long.byte 0x0 0.--7. 1. "wdt_crr,This register is used to restart the WDT counter. As a safety feature to"
rgroup.long 0x10++0x7
line.long 0x0 "WDT_STAT,Interrupt Status Register."
bitfld.long 0x0 0. "wdt_stat,This register shows the interrupt status of the WDT." "0: Interrupt is inactive,1: Interrupt is active regardless of polarity"
line.long 0x4 "WDT_EOI,Interrupt Clear Register."
bitfld.long 0x4 0. "wdt_eoi,Clears the watchdog interrupt. This can be used to clear the interrupt" "0,1"
rgroup.long 0xE4++0x1B
line.long 0x0 "WDT_COMP_PARAM_5,Component Parameters Register 5"
hexmask.long 0x0 0.--31. 1. "WDT_COMP_PARAM_5,Component Parameters Register 5"
line.long 0x4 "WDT_COMP_PARAM_4,Component Parameters Register 4"
hexmask.long 0x4 0.--31. 1. "WDT_COMP_PARAM_4,Component Parameters Register 4"
line.long 0x8 "WDT_COMP_PARAM_3,Component Parameters Register 3"
hexmask.long 0x8 0.--31. 1. "WDT_COMP_PARAM_3,Component Parameters Register 3"
line.long 0xC "WDT_COMP_PARAM_2,Component Parameters Register 2"
hexmask.long 0xC 0.--31. 1. "WDT_COMP_PARAM_2,Component Parameters Register 2"
line.long 0x10 "WDT_COMP_PARAM_1,Component Parameters Register 1"
bitfld.long 0x10 29.--31. "RSVD_31_29," "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 24.--28. 1. "WDT_CNT_WIDTH,"
newline
hexmask.long.byte 0x10 20.--23. 1. "WDT_DFLT_TOP_INIT,"
hexmask.long.byte 0x10 16.--19. 1. "WDT_DFLT_TOP,"
newline
bitfld.long 0x10 13.--15. "RSVD_15_13," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 10.--12. "WDT_DFLT_RPL," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 8.--9. "APB_DATA_WIDTH," "0,1,2,3"
bitfld.long 0x10 7. "WDT_PAUSE," "0,1"
newline
bitfld.long 0x10 6. "WDT_USE_FIX_TOP," "0,1"
bitfld.long 0x10 5. "WDT_HC_TOP," "0,1"
newline
bitfld.long 0x10 4. "WDT_HC_RPL," "0,1"
bitfld.long 0x10 3. "WDT_HC_RMOD," "0,1"
newline
bitfld.long 0x10 2. "WDT_DUAL_TOP," "0,1"
bitfld.long 0x10 1. "WDT_DFLT_RMOD," "0,1"
newline
bitfld.long 0x10 0. "WDT_ALWAYS_EN," "0,1"
line.long 0x14 "WDT_COMP_VERSION,Component Version Register"
hexmask.long 0x14 0.--31. 1. "wdt_comp_version,ASCII value for each number in the version  followed by *. For example "
line.long 0x18 "WDT_COMP_TYPE,Component Type Register"
hexmask.long 0x18 0.--31. 1. "wdt_comp_type,Component Type Register"
tree.end
tree "L4WD1 (Watchdog1 Module)"
base ad:0xFFD00300
group.long 0x0++0x7
line.long 0x0 "WDT_CR,Control Register"
bitfld.long 0x0 2.--4. "RPL,Reset pulse length. Writes have no effect when the configuration parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 1. "RMOD,Response mode. Writes have no effect when the parameter" "0: Generate a system reset,1: First generate an interrupt and if it is not.."
newline
bitfld.long 0x0 0. "WDT_EN,When the configuration parameter WDT_ALWAYS_EN = 0  this bit can be set" "0: WDT disabled,1: WDT enabled"
line.long 0x4 "WDT_TORR,Timeout Range Register"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved,Reserved and read as 0."
hexmask.long.byte 0x4 4.--7. 1. "TOP_INIT,Timeout period for initialization."
newline
hexmask.long.byte 0x4 0.--3. 1. "TOP,Timeout period. Writes have no effect when the configuration parameter"
rgroup.long 0x8++0x3
line.long 0x0 "WDT_CCVR,Current Counter Value Register."
hexmask.long 0x0 0.--31. 1. "wdt_ccvr,This register  when read  is the current value of the internal"
wgroup.long 0xC++0x3
line.long 0x0 "WDT_CRR,Counter Restart Register."
hexmask.long.byte 0x0 0.--7. 1. "wdt_crr,This register is used to restart the WDT counter. As a safety feature to"
rgroup.long 0x10++0x7
line.long 0x0 "WDT_STAT,Interrupt Status Register."
bitfld.long 0x0 0. "wdt_stat,This register shows the interrupt status of the WDT." "0: Interrupt is inactive,1: Interrupt is active regardless of polarity"
line.long 0x4 "WDT_EOI,Interrupt Clear Register."
bitfld.long 0x4 0. "wdt_eoi,Clears the watchdog interrupt. This can be used to clear the interrupt" "0,1"
rgroup.long 0xE4++0x1B
line.long 0x0 "WDT_COMP_PARAM_5,Component Parameters Register 5"
hexmask.long 0x0 0.--31. 1. "WDT_COMP_PARAM_5,Component Parameters Register 5"
line.long 0x4 "WDT_COMP_PARAM_4,Component Parameters Register 4"
hexmask.long 0x4 0.--31. 1. "WDT_COMP_PARAM_4,Component Parameters Register 4"
line.long 0x8 "WDT_COMP_PARAM_3,Component Parameters Register 3"
hexmask.long 0x8 0.--31. 1. "WDT_COMP_PARAM_3,Component Parameters Register 3"
line.long 0xC "WDT_COMP_PARAM_2,Component Parameters Register 2"
hexmask.long 0xC 0.--31. 1. "WDT_COMP_PARAM_2,Component Parameters Register 2"
line.long 0x10 "WDT_COMP_PARAM_1,Component Parameters Register 1"
bitfld.long 0x10 29.--31. "RSVD_31_29," "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 24.--28. 1. "WDT_CNT_WIDTH,"
newline
hexmask.long.byte 0x10 20.--23. 1. "WDT_DFLT_TOP_INIT,"
hexmask.long.byte 0x10 16.--19. 1. "WDT_DFLT_TOP,"
newline
bitfld.long 0x10 13.--15. "RSVD_15_13," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 10.--12. "WDT_DFLT_RPL," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 8.--9. "APB_DATA_WIDTH," "0,1,2,3"
bitfld.long 0x10 7. "WDT_PAUSE," "0,1"
newline
bitfld.long 0x10 6. "WDT_USE_FIX_TOP," "0,1"
bitfld.long 0x10 5. "WDT_HC_TOP," "0,1"
newline
bitfld.long 0x10 4. "WDT_HC_RPL," "0,1"
bitfld.long 0x10 3. "WDT_HC_RMOD," "0,1"
newline
bitfld.long 0x10 2. "WDT_DUAL_TOP," "0,1"
bitfld.long 0x10 1. "WDT_DFLT_RMOD," "0,1"
newline
bitfld.long 0x10 0. "WDT_ALWAYS_EN," "0,1"
line.long 0x14 "WDT_COMP_VERSION,Component Version Register"
hexmask.long 0x14 0.--31. 1. "wdt_comp_version,ASCII value for each number in the version  followed by *. For example "
line.long 0x18 "WDT_COMP_TYPE,Component Type Register"
hexmask.long 0x18 0.--31. 1. "wdt_comp_type,Component Type Register"
tree.end
tree "L4WD2 (Watchdog2 Module)"
base ad:0xFFD00400
group.long 0x0++0x7
line.long 0x0 "WDT_CR,Control Register"
bitfld.long 0x0 2.--4. "RPL,Reset pulse length. Writes have no effect when the configuration parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 1. "RMOD,Response mode. Writes have no effect when the parameter" "0: Generate a system reset,1: First generate an interrupt and if it is not.."
newline
bitfld.long 0x0 0. "WDT_EN,When the configuration parameter WDT_ALWAYS_EN = 0  this bit can be set" "0: WDT disabled,1: WDT enabled"
line.long 0x4 "WDT_TORR,Timeout Range Register"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved,Reserved and read as 0."
hexmask.long.byte 0x4 4.--7. 1. "TOP_INIT,Timeout period for initialization."
newline
hexmask.long.byte 0x4 0.--3. 1. "TOP,Timeout period. Writes have no effect when the configuration parameter"
rgroup.long 0x8++0x3
line.long 0x0 "WDT_CCVR,Current Counter Value Register."
hexmask.long 0x0 0.--31. 1. "wdt_ccvr,This register  when read  is the current value of the internal"
wgroup.long 0xC++0x3
line.long 0x0 "WDT_CRR,Counter Restart Register."
hexmask.long.byte 0x0 0.--7. 1. "wdt_crr,This register is used to restart the WDT counter. As a safety feature to"
rgroup.long 0x10++0x7
line.long 0x0 "WDT_STAT,Interrupt Status Register."
bitfld.long 0x0 0. "wdt_stat,This register shows the interrupt status of the WDT." "0: Interrupt is inactive,1: Interrupt is active regardless of polarity"
line.long 0x4 "WDT_EOI,Interrupt Clear Register."
bitfld.long 0x4 0. "wdt_eoi,Clears the watchdog interrupt. This can be used to clear the interrupt" "0,1"
rgroup.long 0xE4++0x1B
line.long 0x0 "WDT_COMP_PARAM_5,Component Parameters Register 5"
hexmask.long 0x0 0.--31. 1. "WDT_COMP_PARAM_5,Component Parameters Register 5"
line.long 0x4 "WDT_COMP_PARAM_4,Component Parameters Register 4"
hexmask.long 0x4 0.--31. 1. "WDT_COMP_PARAM_4,Component Parameters Register 4"
line.long 0x8 "WDT_COMP_PARAM_3,Component Parameters Register 3"
hexmask.long 0x8 0.--31. 1. "WDT_COMP_PARAM_3,Component Parameters Register 3"
line.long 0xC "WDT_COMP_PARAM_2,Component Parameters Register 2"
hexmask.long 0xC 0.--31. 1. "WDT_COMP_PARAM_2,Component Parameters Register 2"
line.long 0x10 "WDT_COMP_PARAM_1,Component Parameters Register 1"
bitfld.long 0x10 29.--31. "RSVD_31_29," "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 24.--28. 1. "WDT_CNT_WIDTH,"
newline
hexmask.long.byte 0x10 20.--23. 1. "WDT_DFLT_TOP_INIT,"
hexmask.long.byte 0x10 16.--19. 1. "WDT_DFLT_TOP,"
newline
bitfld.long 0x10 13.--15. "RSVD_15_13," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 10.--12. "WDT_DFLT_RPL," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 8.--9. "APB_DATA_WIDTH," "0,1,2,3"
bitfld.long 0x10 7. "WDT_PAUSE," "0,1"
newline
bitfld.long 0x10 6. "WDT_USE_FIX_TOP," "0,1"
bitfld.long 0x10 5. "WDT_HC_TOP," "0,1"
newline
bitfld.long 0x10 4. "WDT_HC_RPL," "0,1"
bitfld.long 0x10 3. "WDT_HC_RMOD," "0,1"
newline
bitfld.long 0x10 2. "WDT_DUAL_TOP," "0,1"
bitfld.long 0x10 1. "WDT_DFLT_RMOD," "0,1"
newline
bitfld.long 0x10 0. "WDT_ALWAYS_EN," "0,1"
line.long 0x14 "WDT_COMP_VERSION,Component Version Register"
hexmask.long 0x14 0.--31. 1. "wdt_comp_version,ASCII value for each number in the version  followed by *. For example "
line.long 0x18 "WDT_COMP_TYPE,Component Type Register"
hexmask.long 0x18 0.--31. 1. "wdt_comp_type,Component Type Register"
tree.end
tree "L4WD3 (Watchdog3 Module)"
base ad:0xFFD00500
group.long 0x0++0x7
line.long 0x0 "WDT_CR,Control Register"
bitfld.long 0x0 2.--4. "RPL,Reset pulse length. Writes have no effect when the configuration parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 1. "RMOD,Response mode. Writes have no effect when the parameter" "0: Generate a system reset,1: First generate an interrupt and if it is not.."
newline
bitfld.long 0x0 0. "WDT_EN,When the configuration parameter WDT_ALWAYS_EN = 0  this bit can be set" "0: WDT disabled,1: WDT enabled"
line.long 0x4 "WDT_TORR,Timeout Range Register"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved,Reserved and read as 0."
hexmask.long.byte 0x4 4.--7. 1. "TOP_INIT,Timeout period for initialization."
newline
hexmask.long.byte 0x4 0.--3. 1. "TOP,Timeout period. Writes have no effect when the configuration parameter"
rgroup.long 0x8++0x3
line.long 0x0 "WDT_CCVR,Current Counter Value Register."
hexmask.long 0x0 0.--31. 1. "wdt_ccvr,This register  when read  is the current value of the internal"
wgroup.long 0xC++0x3
line.long 0x0 "WDT_CRR,Counter Restart Register."
hexmask.long.byte 0x0 0.--7. 1. "wdt_crr,This register is used to restart the WDT counter. As a safety feature to"
rgroup.long 0x10++0x7
line.long 0x0 "WDT_STAT,Interrupt Status Register."
bitfld.long 0x0 0. "wdt_stat,This register shows the interrupt status of the WDT." "0: Interrupt is inactive,1: Interrupt is active regardless of polarity"
line.long 0x4 "WDT_EOI,Interrupt Clear Register."
bitfld.long 0x4 0. "wdt_eoi,Clears the watchdog interrupt. This can be used to clear the interrupt" "0,1"
rgroup.long 0xE4++0x1B
line.long 0x0 "WDT_COMP_PARAM_5,Component Parameters Register 5"
hexmask.long 0x0 0.--31. 1. "WDT_COMP_PARAM_5,Component Parameters Register 5"
line.long 0x4 "WDT_COMP_PARAM_4,Component Parameters Register 4"
hexmask.long 0x4 0.--31. 1. "WDT_COMP_PARAM_4,Component Parameters Register 4"
line.long 0x8 "WDT_COMP_PARAM_3,Component Parameters Register 3"
hexmask.long 0x8 0.--31. 1. "WDT_COMP_PARAM_3,Component Parameters Register 3"
line.long 0xC "WDT_COMP_PARAM_2,Component Parameters Register 2"
hexmask.long 0xC 0.--31. 1. "WDT_COMP_PARAM_2,Component Parameters Register 2"
line.long 0x10 "WDT_COMP_PARAM_1,Component Parameters Register 1"
bitfld.long 0x10 29.--31. "RSVD_31_29," "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 24.--28. 1. "WDT_CNT_WIDTH,"
newline
hexmask.long.byte 0x10 20.--23. 1. "WDT_DFLT_TOP_INIT,"
hexmask.long.byte 0x10 16.--19. 1. "WDT_DFLT_TOP,"
newline
bitfld.long 0x10 13.--15. "RSVD_15_13," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 10.--12. "WDT_DFLT_RPL," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 8.--9. "APB_DATA_WIDTH," "0,1,2,3"
bitfld.long 0x10 7. "WDT_PAUSE," "0,1"
newline
bitfld.long 0x10 6. "WDT_USE_FIX_TOP," "0,1"
bitfld.long 0x10 5. "WDT_HC_TOP," "0,1"
newline
bitfld.long 0x10 4. "WDT_HC_RPL," "0,1"
bitfld.long 0x10 3. "WDT_HC_RMOD," "0,1"
newline
bitfld.long 0x10 2. "WDT_DUAL_TOP," "0,1"
bitfld.long 0x10 1. "WDT_DFLT_RMOD," "0,1"
newline
bitfld.long 0x10 0. "WDT_ALWAYS_EN," "0,1"
line.long 0x14 "WDT_COMP_VERSION,Component Version Register"
hexmask.long 0x14 0.--31. 1. "wdt_comp_version,ASCII value for each number in the version  followed by *. For example "
line.long 0x18 "WDT_COMP_TYPE,Component Type Register"
hexmask.long 0x18 0.--31. 1. "wdt_comp_type,Component Type Register"
tree.end
tree.end
tree "LWFPGASLAVES (Cache Cleaning Slaves)"
base ad:0xF9C00000
rgroup.long 0x6122000++0x7
line.long 0x0 "cs_obs_at_main_AtbEndPoint_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "cs_obs_at_main_AtbEndPoint_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x6122008++0xB
line.long 0x0 "cs_obs_at_main_AtbEndPoint_AtbId,"
hexmask.long.byte 0x0 0.--6. 1. "ATBID,ATB AtId"
line.long 0x4 "cs_obs_at_main_AtbEndPoint_AtbEn,"
bitfld.long 0x4 0. "ATBEN,ATB Unit Enable" "0,1"
line.long 0x8 "cs_obs_at_main_AtbEndPoint_SyncPeriod,"
hexmask.long.byte 0x8 0.--4. 1. "SYNCPERIOD,ATB Synchro Period"
rgroup.long 0x6122080++0x7
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "cs_obs_at_main_ErrorLogger_0_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x6122088++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_FaultEn,"
bitfld.long 0x0 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1"
rgroup.long 0x612208C++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_ErrVld,"
bitfld.long 0x0 0. "ERRVLD,1 indicates an error has been logged" "0,1"
group.long 0x6122090++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_ErrClr,"
eventfld.long 0x0 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1"
rgroup.long 0x6122094++0x7
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_ErrLog0,Stores NTTP packet header fields Lock. Opc. ErrCode. Len1 and indicates version of NTTP transport protocol"
bitfld.long 0x0 31. "FORMAT,NTTP transport protocol version" "0,1"
newline
hexmask.long.word 0x0 16.--27. 1. "LEN1,Len1"
newline
bitfld.long 0x0 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 1.--4. 1. "OPC,Opc"
newline
bitfld.long 0x0 0. "LOCK,Lock" "0,1"
line.long 0x4 "cs_obs_at_main_ErrorLogger_0_ErrLog1,"
hexmask.long.tbyte 0x4 0.--22. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error"
rgroup.long 0x61220A0++0xB
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_ErrLog3,"
hexmask.long 0x0 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error"
line.long 0x4 "cs_obs_at_main_ErrorLogger_0_ErrLog4,"
hexmask.long.byte 0x4 0.--7. 1. "ERRLOG4,Stores NTTP packet header field Addr (MSBs) of the logged error"
line.long 0x8 "cs_obs_at_main_ErrorLogger_0_ErrLog5,"
hexmask.long 0x8 0.--28. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error"
rgroup.long 0x61220B0++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_ErrLog7,"
bitfld.long 0x0 0.--1. "ERRLOG7,Stores NTTP packet header field Security of the logged error" "0,1,2,3"
group.long 0x61220B8++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_StallEn,"
bitfld.long 0x0 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1"
rgroup.long 0x6122400++0x7
line.long 0x0 "probe_ccu_main_Probe_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "probe_ccu_main_Probe_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x6122408++0x7
line.long 0x0 "probe_ccu_main_Probe_MainCtl,Register MainCtl contains probe global control bits. The register has seven bit fields:"
bitfld.long 0x0 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0  filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore  only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1  filters are.." "0,1"
newline
rbitfld.long 0x0 6. "INTRUSIVEMODE,When set to 1  register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0  the register enables trace operation in Overflow flow-control mode" "0,1"
newline
bitfld.long 0x0 5. "STATCONDDUMP,When set  register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin  StatAlarmMax  and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1"
newline
bitfld.long 0x0 4. "ALARMEN,When set  register field AlarmEn enables the probe to collect alarm-related information. When the register field bit is null  both TraceAlarm and StatAlarm outputs are driven to 0." "0,1"
newline
bitfld.long 0x0 3. "STATEN,When set to 1  register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0  counters are disabled." "0,1"
newline
bitfld.long 0x0 2. "PAYLOADEN,Register field PayloadEn  when set to 1  enables traces to contain headers and payload. When set ot 0  only headers are reported." "0,1"
newline
bitfld.long 0x0 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1"
newline
bitfld.long 0x0 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status  independently of filtering mechanisms  thus constituting a simple supplementary global filter." "0,1"
line.long 0x4 "probe_ccu_main_Probe_CfgCtl,"
rbitfld.long 0x4 1. "ACTIVE," "0,1"
newline
bitfld.long 0x4 0. "GLOBALEN," "0,1"
group.long 0x6122414++0x7
line.long 0x0 "probe_ccu_main_Probe_FilterLut,"
hexmask.long.byte 0x0 0.--3. 1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.."
line.long 0x4 "probe_ccu_main_Probe_TraceAlarmEn,"
bitfld.long 0x4 0.--2. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3,4,5,6,7"
rgroup.long 0x612241C++0x3
line.long 0x0 "probe_ccu_main_Probe_TraceAlarmStatus,"
bitfld.long 0x0 0.--2. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet  independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3,4,5,6,7"
group.long 0x6122420++0x13
line.long 0x0 "probe_ccu_main_Probe_TraceAlarmClr,"
eventfld.long 0x0 0.--2. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0  TraceAlarmClr is reserved.NOTE The.." "0,1,2,3,4,5,6,7"
line.long 0x4 "probe_ccu_main_Probe_StatPeriod,"
hexmask.long.byte 0x4 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period  within a range of 2 cycles to 2 gigacycles  during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.."
line.long 0x8 "probe_ccu_main_Probe_StatGo,"
eventfld.long 0x8 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode  that is  when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1"
line.long 0xC "probe_ccu_main_Probe_StatAlarmMin,"
hexmask.long 0xC 0.--31. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .."
line.long 0x10 "probe_ccu_main_Probe_StatAlarmMax,"
hexmask.long 0x10 0.--31. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .."
rgroup.long 0x6122434++0x3
line.long 0x0 "probe_ccu_main_Probe_StatAlarmStatus,"
bitfld.long 0x0 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1"
group.long 0x6122438++0x7
line.long 0x0 "probe_ccu_main_Probe_StatAlarmClr,"
eventfld.long 0x0 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False  StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1"
line.long 0x4 "probe_ccu_main_Probe_StatAlarmEn,"
bitfld.long 0x4 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1"
group.long 0x6122444++0x2B
line.long 0x0 "probe_ccu_main_Probe_Filters_0_RouteIdBase,"
hexmask.long.tbyte 0x0 0.--22. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x4 "probe_ccu_main_Probe_Filters_0_RouteIdMask,"
hexmask.long.tbyte 0x4 0.--22. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &RouteIdMask = RouteIdBase &RouteIdMask."
line.long 0x8 "probe_ccu_main_Probe_Filters_0_AddrBase_Low,"
hexmask.long 0x8 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register."
line.long 0xC "probe_ccu_main_Probe_Filters_0_AddrBase_High,"
hexmask.long.byte 0xC 0.--7. 1. "FILTERS_0_ADDRBASE_HIGH,Address MSB register."
line.long 0x10 "probe_ccu_main_Probe_Filters_0_WindowSize,"
hexmask.long.byte 0x10 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr &Mask = AddrBase &Mask. This allows.."
line.long 0x14 "probe_ccu_main_Probe_Filters_0_SecurityBase,"
bitfld.long 0x14 0.--1. "FILTERS_0_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x18 "probe_ccu_main_Probe_Filters_0_SecurityMask,"
bitfld.long 0x18 0.--1. "FILTERS_0_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security &SecurityMask = SecurityBase &SecurityMasks." "0,1,2,3"
line.long 0x1C "probe_ccu_main_Probe_Filters_0_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
bitfld.long 0x1C 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x1C 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x1C 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x1C 0. "RDEN,Selects RD packets." "0,1"
line.long 0x20 "probe_ccu_main_Probe_Filters_0_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
bitfld.long 0x20 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x20 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x24 "probe_ccu_main_Probe_Filters_0_Length,"
hexmask.long.byte 0x24 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0x28 "probe_ccu_main_Probe_Filters_0_Urgency,"
bitfld.long 0x28 0.--1. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
group.long 0x6122480++0x2B
line.long 0x0 "probe_ccu_main_Probe_Filters_1_RouteIdBase,"
hexmask.long.tbyte 0x0 0.--22. 1. "FILTERS_1_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x4 "probe_ccu_main_Probe_Filters_1_RouteIdMask,"
hexmask.long.tbyte 0x4 0.--22. 1. "FILTERS_1_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &RouteIdMask = RouteIdBase &RouteIdMask."
line.long 0x8 "probe_ccu_main_Probe_Filters_1_AddrBase_Low,"
hexmask.long 0x8 0.--31. 1. "FILTERS_1_ADDRBASE_LOW,Address LSB register."
line.long 0xC "probe_ccu_main_Probe_Filters_1_AddrBase_High,"
hexmask.long.byte 0xC 0.--7. 1. "FILTERS_1_ADDRBASE_HIGH,Address MSB register."
line.long 0x10 "probe_ccu_main_Probe_Filters_1_WindowSize,"
hexmask.long.byte 0x10 0.--5. 1. "FILTERS_1_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr &Mask = AddrBase &Mask. This allows.."
line.long 0x14 "probe_ccu_main_Probe_Filters_1_SecurityBase,"
bitfld.long 0x14 0.--1. "FILTERS_1_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x18 "probe_ccu_main_Probe_Filters_1_SecurityMask,"
bitfld.long 0x18 0.--1. "FILTERS_1_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security &SecurityMask = SecurityBase &SecurityMasks." "0,1,2,3"
line.long 0x1C "probe_ccu_main_Probe_Filters_1_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
bitfld.long 0x1C 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x1C 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x1C 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x1C 0. "RDEN,Selects RD packets." "0,1"
line.long 0x20 "probe_ccu_main_Probe_Filters_1_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
bitfld.long 0x20 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x20 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x24 "probe_ccu_main_Probe_Filters_1_Length,"
hexmask.long.byte 0x24 0.--3. 1. "FILTERS_1_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0x28 "probe_ccu_main_Probe_Filters_1_Urgency,"
bitfld.long 0x28 0.--1. "FILTERS_1_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
group.long 0x6122538++0x7
line.long 0x0 "probe_ccu_main_Probe_Counters_0_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_ccu_main_Probe_Counters_0_AlarmMode,"
bitfld.long 0x4 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0,1,2,3"
rgroup.long 0x6122540++0x3
line.long 0x0 "probe_ccu_main_Probe_Counters_0_Val,"
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0x612254C++0x7
line.long 0x0 "probe_ccu_main_Probe_Counters_1_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_ccu_main_Probe_Counters_1_AlarmMode,"
bitfld.long 0x4 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0,1,2,3"
rgroup.long 0x6122554++0x3
line.long 0x0 "probe_ccu_main_Probe_Counters_1_Val,"
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0x6122560++0x7
line.long 0x0 "probe_ccu_main_Probe_Counters_2_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_ccu_main_Probe_Counters_2_AlarmMode,"
bitfld.long 0x4 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0,1,2,3"
rgroup.long 0x6122568++0x3
line.long 0x0 "probe_ccu_main_Probe_Counters_2_Val,"
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0x6122574++0x7
line.long 0x0 "probe_ccu_main_Probe_Counters_3_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_ccu_main_Probe_Counters_3_AlarmMode,"
bitfld.long 0x4 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0,1,2,3"
rgroup.long 0x612257C++0x3
line.long 0x0 "probe_ccu_main_Probe_Counters_3_Val,"
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
rgroup.long 0x6122800++0x7
line.long 0x0 "probe_emac_main_Probe_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "probe_emac_main_Probe_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x6122808++0x7
line.long 0x0 "probe_emac_main_Probe_MainCtl,Register MainCtl contains probe global control bits. The register has seven bit fields:"
bitfld.long 0x0 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0  filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore  only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1  filters are.." "0,1"
newline
rbitfld.long 0x0 6. "INTRUSIVEMODE,When set to 1  register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0  the register enables trace operation in Overflow flow-control mode" "0,1"
newline
bitfld.long 0x0 5. "STATCONDDUMP,When set  register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin  StatAlarmMax  and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1"
newline
bitfld.long 0x0 4. "ALARMEN,When set  register field AlarmEn enables the probe to collect alarm-related information. When the register field bit is null  both TraceAlarm and StatAlarm outputs are driven to 0." "0,1"
newline
bitfld.long 0x0 3. "STATEN,When set to 1  register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0  counters are disabled." "0,1"
newline
bitfld.long 0x0 2. "PAYLOADEN,Register field PayloadEn  when set to 1  enables traces to contain headers and payload. When set ot 0  only headers are reported." "0,1"
newline
bitfld.long 0x0 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1"
newline
bitfld.long 0x0 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status  independently of filtering mechanisms  thus constituting a simple supplementary global filter." "0,1"
line.long 0x4 "probe_emac_main_Probe_CfgCtl,"
rbitfld.long 0x4 1. "ACTIVE," "0,1"
newline
bitfld.long 0x4 0. "GLOBALEN," "0,1"
group.long 0x6122814++0x7
line.long 0x0 "probe_emac_main_Probe_FilterLut,"
hexmask.long.byte 0x0 0.--3. 1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.."
line.long 0x4 "probe_emac_main_Probe_TraceAlarmEn,"
bitfld.long 0x4 0.--2. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3,4,5,6,7"
rgroup.long 0x612281C++0x3
line.long 0x0 "probe_emac_main_Probe_TraceAlarmStatus,"
bitfld.long 0x0 0.--2. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet  independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3,4,5,6,7"
group.long 0x6122820++0x13
line.long 0x0 "probe_emac_main_Probe_TraceAlarmClr,"
eventfld.long 0x0 0.--2. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0  TraceAlarmClr is reserved.NOTE The.." "0,1,2,3,4,5,6,7"
line.long 0x4 "probe_emac_main_Probe_StatPeriod,"
hexmask.long.byte 0x4 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period  within a range of 2 cycles to 2 gigacycles  during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.."
line.long 0x8 "probe_emac_main_Probe_StatGo,"
eventfld.long 0x8 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode  that is  when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1"
line.long 0xC "probe_emac_main_Probe_StatAlarmMin,"
hexmask.long 0xC 0.--31. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .."
line.long 0x10 "probe_emac_main_Probe_StatAlarmMax,"
hexmask.long 0x10 0.--31. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .."
rgroup.long 0x6122834++0x3
line.long 0x0 "probe_emac_main_Probe_StatAlarmStatus,"
bitfld.long 0x0 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1"
group.long 0x6122838++0x7
line.long 0x0 "probe_emac_main_Probe_StatAlarmClr,"
eventfld.long 0x0 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False  StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1"
line.long 0x4 "probe_emac_main_Probe_StatAlarmEn,"
bitfld.long 0x4 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1"
group.long 0x6122844++0x2B
line.long 0x0 "probe_emac_main_Probe_Filters_0_RouteIdBase,"
hexmask.long.tbyte 0x0 0.--22. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x4 "probe_emac_main_Probe_Filters_0_RouteIdMask,"
hexmask.long.tbyte 0x4 0.--22. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &RouteIdMask = RouteIdBase &RouteIdMask."
line.long 0x8 "probe_emac_main_Probe_Filters_0_AddrBase_Low,"
hexmask.long 0x8 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register."
line.long 0xC "probe_emac_main_Probe_Filters_0_AddrBase_High,"
hexmask.long.byte 0xC 0.--7. 1. "FILTERS_0_ADDRBASE_HIGH,Address MSB register."
line.long 0x10 "probe_emac_main_Probe_Filters_0_WindowSize,"
hexmask.long.byte 0x10 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr &Mask = AddrBase &Mask. This allows.."
line.long 0x14 "probe_emac_main_Probe_Filters_0_SecurityBase,"
bitfld.long 0x14 0.--1. "FILTERS_0_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x18 "probe_emac_main_Probe_Filters_0_SecurityMask,"
bitfld.long 0x18 0.--1. "FILTERS_0_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security &SecurityMask = SecurityBase &SecurityMasks." "0,1,2,3"
line.long 0x1C "probe_emac_main_Probe_Filters_0_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
bitfld.long 0x1C 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x1C 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x1C 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x1C 0. "RDEN,Selects RD packets." "0,1"
line.long 0x20 "probe_emac_main_Probe_Filters_0_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
bitfld.long 0x20 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x20 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x24 "probe_emac_main_Probe_Filters_0_Length,"
hexmask.long.byte 0x24 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0x28 "probe_emac_main_Probe_Filters_0_Urgency,"
bitfld.long 0x28 0.--1. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
group.long 0x6122880++0x2B
line.long 0x0 "probe_emac_main_Probe_Filters_1_RouteIdBase,"
hexmask.long.tbyte 0x0 0.--22. 1. "FILTERS_1_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x4 "probe_emac_main_Probe_Filters_1_RouteIdMask,"
hexmask.long.tbyte 0x4 0.--22. 1. "FILTERS_1_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &RouteIdMask = RouteIdBase &RouteIdMask."
line.long 0x8 "probe_emac_main_Probe_Filters_1_AddrBase_Low,"
hexmask.long 0x8 0.--31. 1. "FILTERS_1_ADDRBASE_LOW,Address LSB register."
line.long 0xC "probe_emac_main_Probe_Filters_1_AddrBase_High,"
hexmask.long.byte 0xC 0.--7. 1. "FILTERS_1_ADDRBASE_HIGH,Address MSB register."
line.long 0x10 "probe_emac_main_Probe_Filters_1_WindowSize,"
hexmask.long.byte 0x10 0.--5. 1. "FILTERS_1_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr &Mask = AddrBase &Mask. This allows.."
line.long 0x14 "probe_emac_main_Probe_Filters_1_SecurityBase,"
bitfld.long 0x14 0.--1. "FILTERS_1_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x18 "probe_emac_main_Probe_Filters_1_SecurityMask,"
bitfld.long 0x18 0.--1. "FILTERS_1_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security &SecurityMask = SecurityBase &SecurityMasks." "0,1,2,3"
line.long 0x1C "probe_emac_main_Probe_Filters_1_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
bitfld.long 0x1C 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x1C 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x1C 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x1C 0. "RDEN,Selects RD packets." "0,1"
line.long 0x20 "probe_emac_main_Probe_Filters_1_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
bitfld.long 0x20 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x20 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x24 "probe_emac_main_Probe_Filters_1_Length,"
hexmask.long.byte 0x24 0.--3. 1. "FILTERS_1_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0x28 "probe_emac_main_Probe_Filters_1_Urgency,"
bitfld.long 0x28 0.--1. "FILTERS_1_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
group.long 0x6122938++0x7
line.long 0x0 "probe_emac_main_Probe_Counters_0_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
bitfld.long 0x0 5. "EXTEVENT,When different than 0  counts the cycles where CntSrc[log2(nExtEvent):] = 1. It exists when nExtEvent > 0." "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_emac_main_Probe_Counters_0_AlarmMode,"
bitfld.long 0x4 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0,1,2,3"
rgroup.long 0x6122940++0x3
line.long 0x0 "probe_emac_main_Probe_Counters_0_Val,"
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0x612294C++0x7
line.long 0x0 "probe_emac_main_Probe_Counters_1_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
bitfld.long 0x0 5. "EXTEVENT,When different than 0  counts the cycles where CntSrc[log2(nExtEvent):] = 1. It exists when nExtEvent > 0." "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_emac_main_Probe_Counters_1_AlarmMode,"
bitfld.long 0x4 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0,1,2,3"
rgroup.long 0x6122954++0x3
line.long 0x0 "probe_emac_main_Probe_Counters_1_Val,"
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0x6122960++0x7
line.long 0x0 "probe_emac_main_Probe_Counters_2_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
bitfld.long 0x0 5. "EXTEVENT,When different than 0  counts the cycles where CntSrc[log2(nExtEvent):] = 1. It exists when nExtEvent > 0." "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_emac_main_Probe_Counters_2_AlarmMode,"
bitfld.long 0x4 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0,1,2,3"
rgroup.long 0x6122968++0x3
line.long 0x0 "probe_emac_main_Probe_Counters_2_Val,"
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0x6122974++0x7
line.long 0x0 "probe_emac_main_Probe_Counters_3_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
bitfld.long 0x0 5. "EXTEVENT,When different than 0  counts the cycles where CntSrc[log2(nExtEvent):] = 1. It exists when nExtEvent > 0." "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_emac_main_Probe_Counters_3_AlarmMode,"
bitfld.long 0x4 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0,1,2,3"
rgroup.long 0x612297C++0x3
line.long 0x0 "probe_emac_main_Probe_Counters_3_Val,"
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
rgroup.long 0x6122C00++0x7
line.long 0x0 "probe_soc2fpga_main_Probe_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "probe_soc2fpga_main_Probe_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x6122C08++0x13
line.long 0x0 "probe_soc2fpga_main_Probe_MainCtl,Register MainCtl contains probe global control bits. The register has seven bit fields:"
bitfld.long 0x0 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0  filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore  only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1  filters are.." "0,1"
newline
rbitfld.long 0x0 6. "INTRUSIVEMODE,When set to 1  register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0  the register enables trace operation in Overflow flow-control mode" "0,1"
newline
bitfld.long 0x0 5. "STATCONDDUMP,When set  register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin  StatAlarmMax  and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1"
newline
bitfld.long 0x0 4. "ALARMEN,When set  register field AlarmEn enables the probe to collect alarm-related information. When the register field bit is null  both TraceAlarm and StatAlarm outputs are driven to 0." "0,1"
newline
bitfld.long 0x0 3. "STATEN,When set to 1  register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0  counters are disabled." "0,1"
newline
bitfld.long 0x0 2. "PAYLOADEN,Register field PayloadEn  when set to 1  enables traces to contain headers and payload. When set ot 0  only headers are reported." "0,1"
newline
bitfld.long 0x0 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1"
newline
bitfld.long 0x0 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status  independently of filtering mechanisms  thus constituting a simple supplementary global filter." "0,1"
line.long 0x4 "probe_soc2fpga_main_Probe_CfgCtl,"
rbitfld.long 0x4 1. "ACTIVE," "0,1"
newline
bitfld.long 0x4 0. "GLOBALEN," "0,1"
line.long 0x8 "probe_soc2fpga_main_Probe_TracePortSel,"
bitfld.long 0x8 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1"
line.long 0xC "probe_soc2fpga_main_Probe_FilterLut,"
hexmask.long.byte 0xC 0.--3. 1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.."
line.long 0x10 "probe_soc2fpga_main_Probe_TraceAlarmEn,"
bitfld.long 0x10 0.--2. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3,4,5,6,7"
rgroup.long 0x6122C1C++0x3
line.long 0x0 "probe_soc2fpga_main_Probe_TraceAlarmStatus,"
bitfld.long 0x0 0.--2. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet  independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3,4,5,6,7"
group.long 0x6122C20++0x13
line.long 0x0 "probe_soc2fpga_main_Probe_TraceAlarmClr,"
eventfld.long 0x0 0.--2. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0  TraceAlarmClr is reserved.NOTE The.." "0,1,2,3,4,5,6,7"
line.long 0x4 "probe_soc2fpga_main_Probe_StatPeriod,"
hexmask.long.byte 0x4 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period  within a range of 2 cycles to 2 gigacycles  during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.."
line.long 0x8 "probe_soc2fpga_main_Probe_StatGo,"
eventfld.long 0x8 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode  that is  when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1"
line.long 0xC "probe_soc2fpga_main_Probe_StatAlarmMin,"
hexmask.long 0xC 0.--31. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .."
line.long 0x10 "probe_soc2fpga_main_Probe_StatAlarmMax,"
hexmask.long 0x10 0.--31. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .."
rgroup.long 0x6122C34++0x3
line.long 0x0 "probe_soc2fpga_main_Probe_StatAlarmStatus,"
bitfld.long 0x0 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1"
group.long 0x6122C38++0x7
line.long 0x0 "probe_soc2fpga_main_Probe_StatAlarmClr,"
eventfld.long 0x0 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False  StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1"
line.long 0x4 "probe_soc2fpga_main_Probe_StatAlarmEn,"
bitfld.long 0x4 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1"
group.long 0x6122C44++0x2B
line.long 0x0 "probe_soc2fpga_main_Probe_Filters_0_RouteIdBase,"
hexmask.long.tbyte 0x0 0.--22. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x4 "probe_soc2fpga_main_Probe_Filters_0_RouteIdMask,"
hexmask.long.tbyte 0x4 0.--22. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &RouteIdMask = RouteIdBase &RouteIdMask."
line.long 0x8 "probe_soc2fpga_main_Probe_Filters_0_AddrBase_Low,"
hexmask.long 0x8 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register."
line.long 0xC "probe_soc2fpga_main_Probe_Filters_0_AddrBase_High,"
hexmask.long.byte 0xC 0.--7. 1. "FILTERS_0_ADDRBASE_HIGH,Address MSB register."
line.long 0x10 "probe_soc2fpga_main_Probe_Filters_0_WindowSize,"
hexmask.long.byte 0x10 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr &Mask = AddrBase &Mask. This allows.."
line.long 0x14 "probe_soc2fpga_main_Probe_Filters_0_SecurityBase,"
bitfld.long 0x14 0.--1. "FILTERS_0_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x18 "probe_soc2fpga_main_Probe_Filters_0_SecurityMask,"
bitfld.long 0x18 0.--1. "FILTERS_0_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security &SecurityMask = SecurityBase &SecurityMasks." "0,1,2,3"
line.long 0x1C "probe_soc2fpga_main_Probe_Filters_0_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
bitfld.long 0x1C 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x1C 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x1C 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x1C 0. "RDEN,Selects RD packets." "0,1"
line.long 0x20 "probe_soc2fpga_main_Probe_Filters_0_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
bitfld.long 0x20 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x20 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x24 "probe_soc2fpga_main_Probe_Filters_0_Length,"
hexmask.long.byte 0x24 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0x28 "probe_soc2fpga_main_Probe_Filters_0_Urgency,"
bitfld.long 0x28 0.--1. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
group.long 0x6122C80++0x2B
line.long 0x0 "probe_soc2fpga_main_Probe_Filters_1_RouteIdBase,"
hexmask.long.tbyte 0x0 0.--22. 1. "FILTERS_1_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x4 "probe_soc2fpga_main_Probe_Filters_1_RouteIdMask,"
hexmask.long.tbyte 0x4 0.--22. 1. "FILTERS_1_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &RouteIdMask = RouteIdBase &RouteIdMask."
line.long 0x8 "probe_soc2fpga_main_Probe_Filters_1_AddrBase_Low,"
hexmask.long 0x8 0.--31. 1. "FILTERS_1_ADDRBASE_LOW,Address LSB register."
line.long 0xC "probe_soc2fpga_main_Probe_Filters_1_AddrBase_High,"
hexmask.long.byte 0xC 0.--7. 1. "FILTERS_1_ADDRBASE_HIGH,Address MSB register."
line.long 0x10 "probe_soc2fpga_main_Probe_Filters_1_WindowSize,"
hexmask.long.byte 0x10 0.--5. 1. "FILTERS_1_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr &Mask = AddrBase &Mask. This allows.."
line.long 0x14 "probe_soc2fpga_main_Probe_Filters_1_SecurityBase,"
bitfld.long 0x14 0.--1. "FILTERS_1_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x18 "probe_soc2fpga_main_Probe_Filters_1_SecurityMask,"
bitfld.long 0x18 0.--1. "FILTERS_1_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security &SecurityMask = SecurityBase &SecurityMasks." "0,1,2,3"
line.long 0x1C "probe_soc2fpga_main_Probe_Filters_1_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
bitfld.long 0x1C 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x1C 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x1C 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x1C 0. "RDEN,Selects RD packets." "0,1"
line.long 0x20 "probe_soc2fpga_main_Probe_Filters_1_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
bitfld.long 0x20 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x20 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x24 "probe_soc2fpga_main_Probe_Filters_1_Length,"
hexmask.long.byte 0x24 0.--3. 1. "FILTERS_1_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0x28 "probe_soc2fpga_main_Probe_Filters_1_Urgency,"
bitfld.long 0x28 0.--1. "FILTERS_1_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
group.long 0x6122D34++0xB
line.long 0x0 "probe_soc2fpga_main_Probe_Counters_0_PortSel,"
bitfld.long 0x0 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time  with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1"
line.long 0x4 "probe_soc2fpga_main_Probe_Counters_0_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long.byte 0x4 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x8 "probe_soc2fpga_main_Probe_Counters_0_AlarmMode,"
bitfld.long 0x8 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0,1,2,3"
rgroup.long 0x6122D40++0x3
line.long 0x0 "probe_soc2fpga_main_Probe_Counters_0_Val,"
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0x6122D48++0xB
line.long 0x0 "probe_soc2fpga_main_Probe_Counters_1_PortSel,"
bitfld.long 0x0 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time  with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1"
line.long 0x4 "probe_soc2fpga_main_Probe_Counters_1_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long.byte 0x4 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x8 "probe_soc2fpga_main_Probe_Counters_1_AlarmMode,"
bitfld.long 0x8 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0,1,2,3"
rgroup.long 0x6122D54++0x3
line.long 0x0 "probe_soc2fpga_main_Probe_Counters_1_Val,"
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0x6122D5C++0xB
line.long 0x0 "probe_soc2fpga_main_Probe_Counters_2_PortSel,"
bitfld.long 0x0 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time  with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1"
line.long 0x4 "probe_soc2fpga_main_Probe_Counters_2_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long.byte 0x4 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x8 "probe_soc2fpga_main_Probe_Counters_2_AlarmMode,"
bitfld.long 0x8 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0,1,2,3"
rgroup.long 0x6122D68++0x3
line.long 0x0 "probe_soc2fpga_main_Probe_Counters_2_Val,"
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0x6122D70++0xB
line.long 0x0 "probe_soc2fpga_main_Probe_Counters_3_PortSel,"
bitfld.long 0x0 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time  with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1"
line.long 0x4 "probe_soc2fpga_main_Probe_Counters_3_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long.byte 0x4 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x8 "probe_soc2fpga_main_Probe_Counters_3_AlarmMode,"
bitfld.long 0x8 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0,1,2,3"
rgroup.long 0x6122D7C++0x3
line.long 0x0 "probe_soc2fpga_main_Probe_Counters_3_Val,"
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
rgroup.long 0x6123000++0x7
line.long 0x0 "probe_emac_main_TransactionStatProfiler_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "probe_emac_main_TransactionStatProfiler_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x6123008++0x7
line.long 0x0 "probe_emac_main_TransactionStatProfiler_En,"
bitfld.long 0x0 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1"
line.long 0x4 "probe_emac_main_TransactionStatProfiler_Mode,"
bitfld.long 0x4 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay  Mode = 1 for Pending)" "0,1"
group.long 0x612302C++0xB
line.long 0x0 "probe_emac_main_TransactionStatProfiler_Thresholds_0_0,"
bitfld.long 0x0 0.--1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." "0,1,2,3"
line.long 0x4 "probe_emac_main_TransactionStatProfiler_Thresholds_0_1,"
bitfld.long 0x4 0.--1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." "0,1,2,3"
line.long 0x8 "probe_emac_main_TransactionStatProfiler_Thresholds_0_2,"
bitfld.long 0x8 0.--1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." "0,1,2,3"
rgroup.long 0x612306C++0x3
line.long 0x0 "probe_emac_main_TransactionStatProfiler_OverflowStatus,"
bitfld.long 0x0 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1"
group.long 0x6123070++0xB
line.long 0x0 "probe_emac_main_TransactionStatProfiler_OverflowReset,"
eventfld.long 0x0 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1"
line.long 0x4 "probe_emac_main_TransactionStatProfiler_PendingEventMode,"
bitfld.long 0x4 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE)  and when register mode is set to PENDING  the pending event is generated on each cycle when the counter is greater than.." "0,1"
line.long 0x8 "probe_emac_main_TransactionStatProfiler_PreScaler,"
hexmask.long.byte 0x8 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0  pre-scaling is disabled. If set to any other supported value 'n'  the threshold counter value is divided by (n + 1)."
rgroup.long 0x6124000++0x7
line.long 0x0 "ccu_ios_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "ccu_ios_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x6124008++0x13
line.long 0x0 "ccu_ios_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--9. "P1,In Programmable or Bandwidth Limiter mode  the priority level for read transactions. In Bandwidth regulator mode  the priority level when the used throughput is below the threshold. In Bandwidth Regulator mode  P1 should have a value equal or greater.." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "P0,In Programmable or Bandwidth Limiter mode  the priority level for write transactions. In Bandwidth Regulator mode  the priority level when the used throughput is above the threshold. In Bandwidth Regulator mode  P0 should have a value equal or lower.." "0,1,2,3"
line.long 0x4 "ccu_ios_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,0 = Programmable mode: a programmed priority is assigned to each read or write  1 = Bandwidth Limiter Mode: a hard limit restricts throughput  2 = Bypass mode: See SoC-specific QOS generator documentation  3 = Bandwidth Regulator mode: priority.." "0: Programmable mode: a programmed priority is..,1: Bandwidth Limiter Mode: a hard limit restricts..,2: Bypass mode: See SoC-specific QOS generator..,3: Bandwidth Regulator mode: priority decreases.."
line.long 0x8 "ccu_ios_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--11. 1. "BANDWIDTH,In Bandwidth Limiter or Bandwidth Regulator mode  the bandwidth threshold in units of 1/256th bytes per cycle. For example  80 MBps on a 250 MHz interface is value 0x0052."
line.long 0xC "ccu_ios_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,In Bandwidth Limiter or Bandwidth Regulator mode  the maximum data count value  in units of 16 bytes. This determines the window of time over which bandwidth is measured. For example  to measure bandwidth within a 1000 cycle window on a 64-bit.."
line.long 0x10 "ccu_ios_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 2. "INTCLKEN,n/a" "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,n/a" "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,n/a" "0,1"
rgroup.long 0x6124080++0x7
line.long 0x0 "dma_tbu_m_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "dma_tbu_m_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x6124088++0x13
line.long 0x0 "dma_tbu_m_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--9. "P1,In Programmable or Bandwidth Limiter mode  the priority level for read transactions. In Bandwidth regulator mode  the priority level when the used throughput is below the threshold. In Bandwidth Regulator mode  P1 should have a value equal or greater.." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "P0,In Programmable or Bandwidth Limiter mode  the priority level for write transactions. In Bandwidth Regulator mode  the priority level when the used throughput is above the threshold. In Bandwidth Regulator mode  P0 should have a value equal or lower.." "0,1,2,3"
line.long 0x4 "dma_tbu_m_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,0 = Programmable mode: a programmed priority is assigned to each read or write  1 = Bandwidth Limiter Mode: a hard limit restricts throughput  2 = Bypass mode: See SoC-specific QoS generator documentation  3 = Bandwidth Regulator mode: priority.." "0: Programmable mode: a programmed priority is..,1: Bandwidth Limiter Mode: a hard limit restricts..,2: Bypass mode: See SoC-specific QoS generator..,3: Bandwidth Regulator mode: priority decreases.."
line.long 0x8 "dma_tbu_m_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--11. 1. "BANDWIDTH,In Bandwidth Limiter or Bandwidth Regulator mode  the bandwidth threshold in units of 1/256th bytes per cycle. For example  80 MBps on a 250 MHz interface is value 0x0052."
line.long 0xC "dma_tbu_m_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,In Bandwidth Limiter or Bandwidth Regulator mode  the maximum data count value  in units of 16 bytes. This determines the window of time over which bandwidth is measured. For example  to measure bandwidth within a 1000 cycle window on a 64-bit.."
line.long 0x10 "dma_tbu_m_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 2. "INTCLKEN,n/a" "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,n/a" "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,n/a" "0,1"
rgroup.long 0x6124100++0x7
line.long 0x0 "emac_tbu_m_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "emac_tbu_m_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x6124108++0x13
line.long 0x0 "emac_tbu_m_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--9. "P1,In Programmable or Bandwidth Limiter mode  the priority level for read transactions. In Bandwidth regulator mode  the priority level when the used throughput is below the threshold. In Bandwidth Regulator mode  P1 should have a value equal or greater.." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "P0,In Programmable or Bandwidth Limiter mode  the priority level for write transactions. In Bandwidth Regulator mode  the priority level when the used throughput is above the threshold. In Bandwidth Regulator mode  P0 should have a value equal or lower.." "0,1,2,3"
line.long 0x4 "emac_tbu_m_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,0 = Programmable mode: a programmed priority is assigned to each read or write  1 = Bandwidth Limiter Mode: a hard limit restricts throughput  2 = Bypass mode: See SoC-specific QoS generator documentation  3 = Bandwidth Regulator mode: priority.." "0: Programmable mode: a programmed priority is..,1: Bandwidth Limiter Mode: a hard limit restricts..,2: Bypass mode: See SoC-specific QoS generator..,3: Bandwidth Regulator mode: priority decreases.."
line.long 0x8 "emac_tbu_m_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--11. 1. "BANDWIDTH,In Bandwidth Limiter or Bandwidth Regulator mode  the bandwidth threshold in units of 1/256th bytes per cycle. For example  80 MBps on a 250 MHz interface is value 0x0052."
line.long 0xC "emac_tbu_m_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,In Bandwidth Limiter or Bandwidth Regulator mode  the maximum data count value  in units of 16 bytes. This determines the window of time over which bandwidth is measured. For example  to measure bandwidth within a 1000 cycle window on a 64-bit.."
line.long 0x10 "emac_tbu_m_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 2. "INTCLKEN,n/a" "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,n/a" "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,n/a" "0,1"
rgroup.long 0x6124180++0x7
line.long 0x0 "io_tbu_m_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "io_tbu_m_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x6124188++0x13
line.long 0x0 "io_tbu_m_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--9. "P1,In Programmable or Bandwidth Limiter mode  the priority level for read transactions. In Bandwidth regulator mode  the priority level when the used throughput is below the threshold. In Bandwidth Regulator mode  P1 should have a value equal or greater.." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "P0,In Programmable or Bandwidth Limiter mode  the priority level for write transactions. In Bandwidth Regulator mode  the priority level when the used throughput is above the threshold. In Bandwidth Regulator mode  P0 should have a value equal or lower.." "0,1,2,3"
line.long 0x4 "io_tbu_m_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,0 = Programmable mode: a programmed priority is assigned to each read or write  1 = Bandwidth Limiter Mode: a hard limit restricts throughput  2 = Bypass mode: See SoC-specific QoS generator documentation  3 = Bandwidth Regulator mode: priority.." "0: Programmable mode: a programmed priority is..,1: Bandwidth Limiter Mode: a hard limit restricts..,2: Bypass mode: See SoC-specific QoS generator..,3: Bandwidth Regulator mode: priority decreases.."
line.long 0x8 "io_tbu_m_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--11. 1. "BANDWIDTH,In Bandwidth Limiter or Bandwidth Regulator mode  the bandwidth threshold in units of 1/256th bytes per cycle. For example  80 MBps on a 250 MHz interface is value 0x0052."
line.long 0xC "io_tbu_m_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,In Bandwidth Limiter or Bandwidth Regulator mode  the maximum data count value  in units of 16 bytes. This determines the window of time over which bandwidth is measured. For example  to measure bandwidth within a 1000 cycle window on a 64-bit.."
line.long 0x10 "io_tbu_m_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 2. "INTCLKEN,n/a" "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,n/a" "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,n/a" "0,1"
rgroup.long 0x6124200++0x7
line.long 0x0 "sdm_tbu_m_I_main_QosGenerator_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "sdm_tbu_m_I_main_QosGenerator_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x6124208++0x13
line.long 0x0 "sdm_tbu_m_I_main_QosGenerator_Priority,Priority register."
rbitfld.long 0x0 31. "MARK,Backward compatibility marker when 0." "0,1"
newline
bitfld.long 0x0 8.--9. "P1,In Programmable or Bandwidth Limiter mode  the priority level for read transactions. In Bandwidth regulator mode  the priority level when the used throughput is below the threshold. In Bandwidth Regulator mode  P1 should have a value equal or greater.." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "P0,In Programmable or Bandwidth Limiter mode  the priority level for write transactions. In Bandwidth Regulator mode  the priority level when the used throughput is above the threshold. In Bandwidth Regulator mode  P0 should have a value equal or lower.." "0,1,2,3"
line.long 0x4 "sdm_tbu_m_I_main_QosGenerator_Mode,"
bitfld.long 0x4 0.--1. "MODE,0 = Programmable mode: a programmed priority is assigned to each read or write  1 = Bandwidth Limiter Mode: a hard limit restricts throughput  2 = Bypass mode: See SoC-specific QoS generator documentation  3 = Bandwidth Regulator mode: priority.." "0: Programmable mode: a programmed priority is..,1: Bandwidth Limiter Mode: a hard limit restricts..,2: Bypass mode: See SoC-specific QoS generator..,3: Bandwidth Regulator mode: priority decreases.."
line.long 0x8 "sdm_tbu_m_I_main_QosGenerator_Bandwidth,"
hexmask.long.word 0x8 0.--11. 1. "BANDWIDTH,In Bandwidth Limiter or Bandwidth Regulator mode  the bandwidth threshold in units of 1/256th bytes per cycle. For example  80 MBps on a 250 MHz interface is value 0x0052."
line.long 0xC "sdm_tbu_m_I_main_QosGenerator_Saturation,"
hexmask.long.word 0xC 0.--9. 1. "SATURATION,In Bandwidth Limiter or Bandwidth Regulator mode  the maximum data count value  in units of 16 bytes. This determines the window of time over which bandwidth is measured. For example  to measure bandwidth within a 1000 cycle window on a 64-bit.."
line.long 0x10 "sdm_tbu_m_I_main_QosGenerator_ExtControl,External inputs control."
bitfld.long 0x10 2. "INTCLKEN,n/a" "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,n/a" "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,n/a" "0,1"
rgroup.long 0x6124400++0x7
line.long 0x0 "emac_tbu_m_I_main_TransactionStatFilter_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "emac_tbu_m_I_main_TransactionStatFilter_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x6124408++0xF
line.long 0x0 "emac_tbu_m_I_main_TransactionStatFilter_Mode,"
bitfld.long 0x0 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1"
line.long 0x4 "emac_tbu_m_I_main_TransactionStatFilter_AddrBase_Low,"
hexmask.long 0x4 0.--31. 1. "ADDRBASE_LOW,Address base LSB register."
line.long 0x8 "emac_tbu_m_I_main_TransactionStatFilter_AddrBase_High,"
hexmask.long.word 0x8 0.--9. 1. "ADDRBASE_HIGH,Address base MSB register."
line.long 0xC "emac_tbu_m_I_main_TransactionStatFilter_AddrWindowSize,"
hexmask.long.byte 0xC 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr &AddrMask = AddrBase &AddrMask."
group.long 0x6124420++0x13
line.long 0x0 "emac_tbu_m_I_main_TransactionStatFilter_Opcode,This register selects candidate packets based on packet opcodes. (0 disables the filter):"
bitfld.long 0x0 1. "WREN,When set to 1  selects WR requests." "0,1"
newline
bitfld.long 0x0 0. "RDEN,When set to 1  selects RD requests." "0,1"
line.long 0x4 "emac_tbu_m_I_main_TransactionStatFilter_UserBase,"
hexmask.long 0x4 0.--28. 1. "USERBASE,This register contains the User base used to filter requests."
line.long 0x8 "emac_tbu_m_I_main_TransactionStatFilter_UserMask,"
hexmask.long 0x8 0.--28. 1. "USERMASK,This register contains the User mask used to filter requests."
line.long 0xC "emac_tbu_m_I_main_TransactionStatFilter_SecurityBase,"
bitfld.long 0xC 0.--1. "SECURITYBASE,This register contains the Security base used to filter requests." "0,1,2,3"
line.long 0x10 "emac_tbu_m_I_main_TransactionStatFilter_SecurityMask,"
bitfld.long 0x10 0.--1. "SECURITYMASK,This register contains the Security mask used to filter requests." "0,1,2,3"
rgroup.long 0x6124C00++0x7
line.long 0x0 "l4_linkResp_main_RateAdapter_Id_CoreId,"
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "l4_linkResp_main_RateAdapter_Id_RevisionId,"
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x6124C08++0x7
line.long 0x0 "l4_linkResp_main_RateAdapter_Rate,"
hexmask.long.word 0x0 0.--9. 1. "RATE,The ratio of outgoing to incoming throughput. This value determines what portion of a received packet will be stored before its head is transmitted. An optimal setting avoids transmitting bubbles  while adding no delay to packets. The ratio is.."
line.long 0x4 "l4_linkResp_main_RateAdapter_Bypass,"
bitfld.long 0x4 0. "BYPASS,Disable the rate adaptation capability. This causes the rate adapter to act as a FIFO by transmitting received words  without delay  as soon as they can be transmitted. This setting is useful when the incoming throughput is equal to or greater.." "0,1"
tree.end
tree "MAILBOX (Mailbox to/from SDM)"
base ad:0xFFA30000
group.long 0x400++0x3
line.long 0x0 "em2sdm,External master to SDM doorbell register"
bitfld.long 0x0 0. "doorbell,external master to sdm door bell register." "0,1"
group.long 0x480++0x3
line.long 0x0 "sdm2em,SDM to External Master doorbell register"
bitfld.long 0x0 0. "doorbell,sdm to external master door bell register." "0,1"
tree.end
tree "NANDREGS (NAND Controller Module Registers)"
base ad:0xFFB80000
group.long 0x0++0x3
line.long 0x0 "device_reset,Device reset. Controller sends a RESET command to device."
bitfld.long 0x0 3. "bank3,Issues reset to bank 3. Controller resets the bit after" "0,1"
bitfld.long 0x0 2. "bank2,Issues reset to bank 2. Controller resets the bit after" "0,1"
newline
bitfld.long 0x0 1. "bank1,Issues reset to bank 1. Controller resets the bit after" "0,1"
bitfld.long 0x0 0. "bank0,Issues reset to bank 0. Controller resets the bit after" "0,1"
group.long 0x10++0x3
line.long 0x0 "transfer_spare_reg,Default data transfer mode. (Ignored during Spare only mode)"
bitfld.long 0x0 0. "flag,On all read or write commands through Map 01  if this bit is set " "0,1"
group.long 0x20++0x3
line.long 0x0 "load_wait_cnt,Wait count value for Load operation"
hexmask.long.word 0x0 0.--15. 1. "value,Number of clock cycles after issue of load operation before"
group.long 0x30++0x3
line.long 0x0 "program_wait_cnt,Wait count value for Program operation"
hexmask.long.word 0x0 0.--15. 1. "value,Number of clock cycles after issue of program operation before"
group.long 0x40++0x3
line.long 0x0 "erase_wait_cnt,Wait count value for Erase operation"
hexmask.long.word 0x0 0.--15. 1. "value,Number of clock cycles after issue of erase operation before"
group.long 0x50++0x3
line.long 0x0 "int_mon_cyccnt,Interrupt monitor cycle count value"
hexmask.long.word 0x0 0.--15. 1. "value,In polling mode  sets the number of cycles Cadence Flash Controller"
group.long 0x60++0x3
line.long 0x0 "rb_pin_enabled,Interrupt or polling mode. Ready/Busy pin is enabled from device."
bitfld.long 0x0 3. "bank3,Sets Cadence Flash Controller in interrupt pin or polling mode" "0,1"
bitfld.long 0x0 2. "bank2,Sets Cadence Flash Controller in interrupt pin or polling mode" "0,1"
newline
bitfld.long 0x0 1. "bank1,Sets Cadence Flash Controller in interrupt pin or polling mode" "0,1"
bitfld.long 0x0 0. "bank0,Sets Cadence Flash Controller in interrupt pin or polling mode" "0,1"
group.long 0x70++0x3
line.long 0x0 "multiplane_operation,Multiplane transfer mode. Pipelined read. copyback. erase"
bitfld.long 0x0 0. "flag,[list][*]1 - Multiplane operation enabled" "0,1"
group.long 0x80++0x3
line.long 0x0 "multiplane_read_enable,Device supports multiplane read command sequence"
bitfld.long 0x0 0. "flag,Certain devices support dedicated multiplane read command sequences" "0,1"
group.long 0x90++0x3
line.long 0x0 "copyback_disable,Device does not support copyback command sequence"
bitfld.long 0x0 0. "flag,[list][*]1 - Copyback disabled [*]0 - Copyback enabled[/list]" "0,1"
group.long 0xA0++0x3
line.long 0x0 "cache_write_enable,Device supports cache write command sequence"
bitfld.long 0x0 0. "flag,[list][*]1 - Cache write supported [*]0 - Cache write not supported[/list]" "0,1"
group.long 0xB0++0x3
line.long 0x0 "cache_read_enable,Device supports cache read command sequence"
bitfld.long 0x0 0. "flag,[list][*]1 - Cache read supported [*]0 - Cache read not supported[/list]" "0,1"
group.long 0xC0++0x3
line.long 0x0 "prefetch_mode,Enables read data prefetching to faster performance"
hexmask.long.word 0x0 4.--15. 1. "prefetch_burst_length,If prefetch_en is set and prefetch_burst_length is set to ZERO  the controller will"
bitfld.long 0x0 0. "prefetch_en,Enable prefetch of Data" "0,1"
group.long 0xD0++0x3
line.long 0x0 "chip_enable_dont_care,Device can work in the chip enable dont care mode"
bitfld.long 0x0 0. "flag,Controller can interleave commands between banks when this feature is enabled." "0,1"
group.long 0xE0++0x3
line.long 0x0 "ecc_enable,Enable controller ECC check bit generation and correction"
bitfld.long 0x0 0. "flag,Enables or disables controller ECC capabilities. When enabled  controller calculates" "0,1"
group.long 0xF0++0x3
line.long 0x0 "global_int_enable,Global Interrupt enable and Error/Timeout disable."
bitfld.long 0x0 8. "error_rpt_disable,Command and ECC uncorrectable failures will not be" "0,1"
bitfld.long 0x0 4. "timeout_disable,Watchdog timer logic will be de-activated when" "0,1"
newline
bitfld.long 0x0 0. "flag,Host will receive an interrupt only when this bit is set." "0,1"
group.long 0x100++0x3
line.long 0x0 "twhr2_and_we_2_re,"
hexmask.long.byte 0x0 8.--13. 1. "twhr2,Signifies the number of controller clocks that should be introduced between"
hexmask.long.byte 0x0 0.--5. 1. "we_2_re,Signifies the number of bus interface clk_x clocks that should be introduced between"
group.long 0x110++0x3
line.long 0x0 "tcwaw_and_addr_2_data,"
hexmask.long.byte 0x0 8.--13. 1. "tcwaw,Signifies the number of controller clocks that should be introduced between"
hexmask.long.byte 0x0 0.--6. 1. "addr_2_data,Signifies the number of bus interface clk_x clocks that should be introduced"
group.long 0x120++0x3
line.long 0x0 "re_2_we,Timing parameter between re high to we low (Trhw)"
hexmask.long.byte 0x0 0.--5. 1. "value,Signifies the number of bus interface clk_x clocks that should be introduced between"
group.long 0x130++0x3
line.long 0x0 "acc_clks,Timing parameter from read enable going low to capture read data"
hexmask.long.byte 0x0 0.--3. 1. "value,Signifies the number of bus interface clk_x clock cycles  controller"
group.long 0x140++0x3
line.long 0x0 "number_of_planes,Number of planes in the device"
bitfld.long 0x0 0.--2. "value,Controller will read Electronic Signature of devices and populate" "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x0 "pages_per_block,Number of pages in a block"
hexmask.long.word 0x0 0.--15. 1. "value,Controller will read Electronic Signature of devices and populate"
group.long 0x160++0x3
line.long 0x0 "device_width,I/O width of attached devices"
bitfld.long 0x0 0.--1. "value,Controller will read Electronic Signature of devices and populate" "0,1,2,3"
group.long 0x170++0x3
line.long 0x0 "device_main_area_size,Page main area size of device in bytes"
hexmask.long.word 0x0 0.--15. 1. "value,Controller will read Electronic Signature of devices and populate"
group.long 0x180++0x3
line.long 0x0 "device_spare_area_size,Page spare area size of device in bytes"
hexmask.long.word 0x0 0.--15. 1. "value,Controller will read Electronic Signature of devices and populate"
group.long 0x190++0x3
line.long 0x0 "two_row_addr_cycles,Attached device has only 2 ROW address cycles"
bitfld.long 0x0 4. "four,This flag must be set for devices which allow for 4 ROW address cycles instead" "0,1"
bitfld.long 0x0 0. "flag,This flag must be set for devices which allow for 2 ROW address cycles instead" "0,1"
group.long 0x1A0++0x3
line.long 0x0 "multiplane_addr_restrict,Address restriction for multiplane commands"
bitfld.long 0x0 0. "flag,This flag must be set for devices which require that during multiplane" "0,1"
group.long 0x1B0++0x3
line.long 0x0 "ecc_correction,Correction capability required and the Erase threshold value."
hexmask.long.word 0x0 16.--31. 1. "erase_threshold,This value informs the ECC logic of the number of 0's to count"
hexmask.long.byte 0x0 0.--7. 1. "value,The required correction capability. A smaller correction capability will"
group.long 0x1C0++0x3
line.long 0x0 "read_mode,The type of read sequence that the controller will follow for pipe read commands."
hexmask.long.byte 0x0 0.--3. 1. "value,The values in the field should be as follows[list]"
group.long 0x1D0++0x3
line.long 0x0 "write_mode,The type of write sequence that the controller will follow for pipe write commands."
hexmask.long.byte 0x0 0.--3. 1. "value,The values in the field should be as follows[list]"
group.long 0x1E0++0x3
line.long 0x0 "copyback_mode,The type of copyback sequence that the controller will follow."
hexmask.long.byte 0x0 0.--3. 1. "value,The values in the field should be as follows[list]"
group.long 0x1F0++0x3
line.long 0x0 "rdwr_en_lo_cnt,Read/Write Enable low pulse width"
hexmask.long.byte 0x0 0.--4. 1. "value,Number of clk_x cycles that read or write enable will kept low to meet the min"
group.long 0x200++0x3
line.long 0x0 "rdwr_en_hi_cnt,Read/Write Enable high pulse width"
hexmask.long.byte 0x0 0.--4. 1. "value,Number of clk_x cycles that read or write enable will kept high to meet the min"
group.long 0x210++0x3
line.long 0x0 "max_rd_delay,Max round trip read data delay for data capture"
hexmask.long.byte 0x0 0.--3. 1. "value,Number of clk_x cycles after generation of feedback clk_x_out pulse when it is safe"
group.long 0x220++0x3
line.long 0x0 "cs_setup_cnt,Chip select setup/tWB time"
hexmask.long.byte 0x0 12.--17. 1. "twb,Number of clk_x cycles required for meeting the tWB time. This register"
hexmask.long.byte 0x0 0.--4. 1. "value,Number of clk_x cycles required for meeting chip select setup time. This register"
group.long 0x230++0x3
line.long 0x0 "spare_area_skip_bytes,Spare area skip bytes"
hexmask.long.byte 0x0 0.--5. 1. "value,Number of bytes to skip from start of spare area before last ECC sector"
group.long 0x240++0x3
line.long 0x0 "spare_area_marker,Spare area marker value"
hexmask.long.word 0x0 0.--15. 1. "value,A 16bit value that will be written in the spare area skip bytes. This value"
group.long 0x250++0x3
line.long 0x0 "devices_connected,Number of Devices connected on one bank"
bitfld.long 0x0 0.--2. "value,Indicates the number of devices connected to a bank. At POR  the value loaded" "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x0 "die_mask,Indicates the die differentiator in case of NAND devices with stacked dies."
hexmask.long.word 0x0 0.--15. 1. "value,The die_mask register information will be used for devices having address restrictions."
group.long 0x270++0x3
line.long 0x0 "first_block_of_next_plane,The starting block address of the next plane in a multi plane device."
hexmask.long.word 0x0 0.--15. 1. "value,This values informs the controller of the plane structure of the device."
group.long 0x280++0x3
line.long 0x0 "write_protect,This register is used to control the assertion/de-assertion of the WP# pin to the device."
bitfld.long 0x0 0. "flag,When the controller is in reset  the WP# pin is always asserted to the device. Once the" "0,1"
group.long 0x290++0x3
line.long 0x0 "re_2_re,Timing parameter between re high to re low (Trhz) for the next bank"
hexmask.long.byte 0x0 0.--5. 1. "value,Signifies the number of bus interface clk_x clocks that should be introduced between"
group.long 0x2A0++0x3
line.long 0x0 "por_reset_count,The number of cycles the controller waits after POR to issue the first RESET command"
hexmask.long.word 0x0 0.--15. 1. "value,The controller waits for this number of cycles before issuing the first"
group.long 0x2B0++0x3
line.long 0x0 "watchdog_reset_count,The number of cycles the controller waits before flagging a"
hexmask.long.word 0x0 0.--15. 1. "value,The controller waits for this number of cycles before issuing"
group.long 0x300++0x3
line.long 0x0 "manufacturer_id,"
hexmask.long.byte 0x0 0.--7. 1. "value,Manufacturer ID"
rgroup.long 0x310++0x3
line.long 0x0 "device_id,"
hexmask.long.byte 0x0 0.--7. 1. "value,Device ID"
rgroup.long 0x320++0x3
line.long 0x0 "device_param_0,"
hexmask.long.byte 0x0 0.--7. 1. "value,3rd byte relating to Device Signature. This register is"
rgroup.long 0x330++0x3
line.long 0x0 "device_param_1,"
hexmask.long.byte 0x0 0.--7. 1. "value,4th byte relating to Device Signature. This register is"
rgroup.long 0x340++0x3
line.long 0x0 "device_param_2,"
hexmask.long.byte 0x0 0.--7. 1. "value,Reserved."
rgroup.long 0x350++0x3
line.long 0x0 "logical_page_data_size,Logical page data area size in bytes"
hexmask.long.word 0x0 0.--15. 1. "value,Logical page spare area size in bytes. If multiple devices are"
rgroup.long 0x360++0x3
line.long 0x0 "logical_page_spare_size,Logical page data area size in bytes"
hexmask.long.word 0x0 0.--15. 1. "value,Logical page spare area size in bytes. If multiple devices are"
rgroup.long 0x370++0x3
line.long 0x0 "revision,Controller Revision"
hexmask.long.byte 0x0 8.--15. 1. "minor,The Minor revision number of the controller"
hexmask.long.byte 0x0 0.--7. 1. "value,The Major revision number of the controller"
rgroup.long 0x380++0x3
line.long 0x0 "onfi_device_features,Features supported by the connected ONFI device"
hexmask.long.word 0x0 0.--15. 1. "value,The values in the field should be interpreted as follows[list]"
rgroup.long 0x390++0x3
line.long 0x0 "onfi_optional_commands,Optional commands supported by the connected ONFI device"
hexmask.long.word 0x0 0.--15. 1. "value,The values in the field should be interpreted as follows[list]"
rgroup.long 0x3A0++0x3
line.long 0x0 "onfi_timing_mode,Asynchronous Timing modes supported by the connected ONFI device"
hexmask.long.byte 0x0 0.--5. 1. "value,The values in the field should be interpreted as follows[list]"
rgroup.long 0x3B0++0x3
line.long 0x0 "onfi_pgm_cache_timing_mode,Asynchronous Program Cache Timing modes supported by the connected ONFI device"
hexmask.long.byte 0x0 0.--5. 1. "value,The values in the field should be interpreted as follows[list]"
group.long 0x3C0++0x3
line.long 0x0 "onfi_device_no_of_luns,Indicates if the device is an ONFI compliant device and the number"
bitfld.long 0x0 20. "ce_reduction_volume_addr_and_change,Device supports CE pin reduction with volume assignments volume addressing" "0,1"
bitfld.long 0x0 16. "onfi_jedec_multiplane_erase_seq,Device supports ONFI JEDEC Multiplane erase sequence.(Only valid for Onfi devices)" "0,1"
newline
bitfld.long 0x0 12. "prog_page_reg_clear_enhancement,Device supports program page register clear enhancement.In such a device " "0,1"
bitfld.long 0x0 8. "onfi_device,Indicates if the device is an ONFI compliant device.[list]" "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "no_of_luns,Indicates the number of LUNS present in the device"
rgroup.long 0x3D0++0x3
line.long 0x0 "onfi_device_no_of_blocks_per_lun_l,Lower bits of number of blocks per LUN present in"
hexmask.long.word 0x0 0.--15. 1. "value,Indicates the lower bits of number of blocks per"
rgroup.long 0x3E0++0x3
line.long 0x0 "onfi_device_no_of_blocks_per_lun_u,Upper bits of number of blocks per LUN present in"
hexmask.long.word 0x0 0.--15. 1. "value,Indicates the upper bits of number of blocks per"
rgroup.long 0x3F0++0x3
line.long 0x0 "features,Shows Available hardware features or attributes"
bitfld.long 0x0 13. "lba,if set  hardware supports Toshiba LBA devices." "0,1"
bitfld.long 0x0 12. "dfi_intf,if set  hardware supports ONFI2.x synchronous interface." "0,1"
newline
bitfld.long 0x0 11. "index_addr,if set  hardware support only Indexed addressing." "0,1"
bitfld.long 0x0 10. "gpreg,if set  General purpose registers are is present in hardware." "0,1"
newline
bitfld.long 0x0 9. "xdma_sideband,if set  Side band DMA signals are present in hardware." "0,1"
bitfld.long 0x0 8. "partition,if set  Partition logic is present in hardware." "0,1"
newline
bitfld.long 0x0 7. "cmd_dma,if set  CMD-DMA is present in hardware." "0,1"
bitfld.long 0x0 6. "dma,if set  DATA-DMA is present in hardware." "0,1"
newline
bitfld.long 0x0 0.--1. "n_banks,Maximum number of banks supported by hardware. This is an" "0,1,2,3"
rgroup.long 0x400++0x3
line.long 0x0 "transfer_mode,Current data transfer mode is Main only. Spare only or Main+Spare."
bitfld.long 0x0 6.--7. "value3,[list][*]00 - Bank 3 is in Main mode [*]01 - Bank 3 is in Spare mode [*]10 - Bank 3 is in Main+Spare mode[/list]" "0,1,2,3"
bitfld.long 0x0 4.--5. "value2,[list][*]00 - Bank 2 is in Main mode [*]01 - Bank 2 is in Spare mode [*]10 - Bank 2 is in Main+Spare mode[/list]" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "value1,[list][*]00 - Bank 1 is in Main mode [*]01 - Bank 1 is in Spare mode [*]10 - Bank 1 is in Main+Spare mode[/list]" "0,1,2,3"
bitfld.long 0x0 0.--1. "value0,[list][*]00 - Bank 0 is in Main mode [*]01 - Bank 0 is in Spare mode [*]10 - Bank 0 is in Main+Spare mode[/list]" "0,1,2,3"
group.long 0x410++0x3
line.long 0x0 "intr_status0,Interrupt status register for bank 0"
eventfld.long 0x0 16. "erased_page,If an erased page is detected on reads  this bit will be set. The detection of erased" "0,1"
eventfld.long 0x0 15. "page_xfer_inc,For every page of data transfer to or from the device  this bit will be set." "0,1"
newline
eventfld.long 0x0 14. "pipe_cmd_err,A pipeline command sequence has been violated. This occurs when Map 01 page read/write" "0,1"
eventfld.long 0x0 13. "rst_comp,Controller has finished reset and initialization process" "0,1"
newline
eventfld.long 0x0 12. "int_act,R/B pin of device transitioned from low to high" "0,1"
eventfld.long 0x0 11. "unsup_cmd,An unsupported command was received. This interrupt is set when an invalid command is" "0,1"
newline
eventfld.long 0x0 10. "locked_blk,The address to program or erase operation is to a locked block and the operation failed" "0,1"
eventfld.long 0x0 9. "pipe_cpybck_cmd_comp,A pipeline command or a copyback bank command has completed on this particular bank" "0,1"
newline
eventfld.long 0x0 8. "erase_comp,Device erase operation complete" "0,1"
eventfld.long 0x0 7. "program_comp,Device finished the last issued program command." "0,1"
newline
eventfld.long 0x0 6. "load_comp,Device finished the last issued load command." "0,1"
eventfld.long 0x0 5. "erase_fail,Erase failure occurred in the device on issuance of a erase command. err_block_addr" "0,1"
newline
eventfld.long 0x0 4. "program_fail,Program failure occurred in the device on issuance of a program command. err_block_addr" "0,1"
eventfld.long 0x0 3. "time_out,Watchdog timer has triggered in the controller due to one of the reasons like device" "0,1"
newline
eventfld.long 0x0 2. "dma_cmd_comp,A data DMA command has completed on this bank" "0,1"
eventfld.long 0x0 0. "ecc_uncor_err,Ecc logic detected uncorrectable error while reading data from flash device." "0,1"
group.long 0x420++0x3
line.long 0x0 "intr_en0,Enables corresponding interrupt bit in interrupt register"
eventfld.long 0x0 16. "erased_page,If an erased page is detected on reads  this bit will be set. The detection of erased" "0,1"
eventfld.long 0x0 15. "page_xfer_inc,For every page of data transfer to or from the device  this bit will be set." "0,1"
newline
eventfld.long 0x0 14. "pipe_cmd_err,A pipeline command sequence has been violated. This occurs when Map 01 page read/write" "0,1"
eventfld.long 0x0 13. "rst_comp,A reset command has completed on this bank" "0,1"
newline
eventfld.long 0x0 12. "int_act,R/B pin of device transitioned from low to high" "0,1"
eventfld.long 0x0 11. "unsup_cmd,An unsupported command was received. This interrupt is set when an invalid command is" "0,1"
newline
eventfld.long 0x0 10. "locked_blk,The address to program or erase operation is to a locked block and the operation failed" "0,1"
eventfld.long 0x0 9. "pipe_cpybck_cmd_comp,A pipeline command or a copyback bank command has completed on this particular bank" "0,1"
newline
eventfld.long 0x0 8. "erase_comp,Device erase operation complete" "0,1"
eventfld.long 0x0 7. "program_comp,Device finished the last issued program command." "0,1"
newline
eventfld.long 0x0 6. "load_comp,Device finished the last issued load command." "0,1"
eventfld.long 0x0 5. "erase_fail,Erase failure occurred in the device on issuance of a erase command. err_block_addr" "0,1"
newline
eventfld.long 0x0 4. "program_fail,Program failure occurred in the device on issuance of a program command. err_block_addr" "0,1"
eventfld.long 0x0 3. "time_out,Watchdog timer has triggered in the controller due to one of the reasons like device" "0,1"
newline
eventfld.long 0x0 2. "dma_cmd_comp,A data DMA command has completed on this bank" "0,1"
eventfld.long 0x0 0. "ecc_uncor_err,If set  Controller will interrupt processor when Ecc logic detects uncorrectable error." "0,1"
rgroup.long 0x430++0x3
line.long 0x0 "page_cnt0,Decrementing page count bank 0"
hexmask.long.byte 0x0 0.--7. 1. "value,Maintains a decrementing count of the number of pages in"
rgroup.long 0x440++0x3
line.long 0x0 "err_page_addr0,Erred page address bank 0"
hexmask.long.word 0x0 0.--15. 1. "value,Holds the page address that resulted in a failure on program"
rgroup.long 0x450++0x3
line.long 0x0 "err_block_addr0,Erred block address bank 0"
hexmask.long.word 0x0 0.--15. 1. "value,Holds the block address that resulted in a failure on program"
group.long 0x460++0x3
line.long 0x0 "intr_status1,Interrupt status register for bank 1"
eventfld.long 0x0 16. "erased_page,If an erased page is detected on reads  this bit will be set. The detection of erased" "0,1"
eventfld.long 0x0 15. "page_xfer_inc,For every page of data transfer to or from the device  this bit will be set." "0,1"
newline
eventfld.long 0x0 14. "pipe_cmd_err,A pipeline command sequence has been violated. This occurs when Map 01 page read/write" "0,1"
eventfld.long 0x0 13. "rst_comp,The Cadence NAND Flash Memory Controller has completed its reset and initialization process" "0,1"
newline
eventfld.long 0x0 12. "int_act,R/B pin of device transitioned from low to high" "0,1"
eventfld.long 0x0 11. "unsup_cmd,An unsupported command was received. This interrupt is set when an invalid command is" "0,1"
newline
eventfld.long 0x0 10. "locked_blk,The address to program or erase operation is to a locked block and the operation failed" "0,1"
eventfld.long 0x0 9. "pipe_cpybck_cmd_comp,A pipeline command or a copyback bank command has completed on this particular bank" "0,1"
newline
eventfld.long 0x0 8. "erase_comp,Device erase operation complete" "0,1"
eventfld.long 0x0 7. "program_comp,Device finished the last issued program command." "0,1"
newline
eventfld.long 0x0 6. "load_comp,Device finished the last issued load command." "0,1"
eventfld.long 0x0 5. "erase_fail,Erase failure occurred in the device on issuance of a erase command. err_block_addr" "0,1"
newline
eventfld.long 0x0 4. "program_fail,Program failure occurred in the device on issuance of a program command. err_block_addr" "0,1"
eventfld.long 0x0 3. "time_out,Watchdog timer has triggered in the controller due to one of the reasons like device" "0,1"
newline
eventfld.long 0x0 2. "dma_cmd_comp,A data DMA command has completed on this bank" "0,1"
eventfld.long 0x0 0. "ecc_uncor_err,Ecc logic detected uncorrectable error while reading data from flash device." "0,1"
group.long 0x470++0x3
line.long 0x0 "intr_en1,Enables corresponding interrupt bit in interrupt register"
eventfld.long 0x0 16. "erased_page,If an erased page is detected on reads  this bit will be set. The detection of erased" "0,1"
eventfld.long 0x0 15. "page_xfer_inc,For every page of data transfer to or from the device  this bit will be set." "0,1"
newline
eventfld.long 0x0 14. "pipe_cmd_err,A pipeline command sequence has been violated. This occurs when Map 01 page read/write" "0,1"
eventfld.long 0x0 13. "rst_comp,A reset command has completed on this bank" "0,1"
newline
eventfld.long 0x0 12. "int_act,R/B pin of device transitioned from low to high" "0,1"
eventfld.long 0x0 11. "unsup_cmd,An unsupported command was received. This interrupt is set when an invalid command is" "0,1"
newline
eventfld.long 0x0 10. "locked_blk,The address to program or erase operation is to a locked block and the operation failed" "0,1"
eventfld.long 0x0 9. "pipe_cpybck_cmd_comp,A pipeline command or a copyback bank command has completed on this particular bank" "0,1"
newline
eventfld.long 0x0 8. "erase_comp,Device erase operation complete" "0,1"
eventfld.long 0x0 7. "program_comp,Device finished the last issued program command." "0,1"
newline
eventfld.long 0x0 6. "load_comp,Device finished the last issued load command." "0,1"
eventfld.long 0x0 5. "erase_fail,Erase failure occurred in the device on issuance of a erase command. err_block_addr" "0,1"
newline
eventfld.long 0x0 4. "program_fail,Program failure occurred in the device on issuance of a program command. err_block_addr" "0,1"
eventfld.long 0x0 3. "time_out,Watchdog timer has triggered in the controller due to one of the reasons like device" "0,1"
newline
eventfld.long 0x0 2. "dma_cmd_comp,A data DMA command has completed on this bank" "0,1"
eventfld.long 0x0 0. "ecc_uncor_err,If set  Controller will interrupt processor when Ecc logic detects uncorrectable error." "0,1"
rgroup.long 0x480++0x3
line.long 0x0 "page_cnt1,Decrementing page count bank 1"
hexmask.long.byte 0x0 0.--7. 1. "value,Maintains a decrementing count of the number of pages in"
rgroup.long 0x490++0x3
line.long 0x0 "err_page_addr1,Erred page address bank 1"
hexmask.long.word 0x0 0.--15. 1. "value,Holds the page address that resulted in a failure on program"
rgroup.long 0x4A0++0x3
line.long 0x0 "err_block_addr1,Erred block address bank 1"
hexmask.long.word 0x0 0.--15. 1. "value,Holds the block address that resulted in a failure on program"
group.long 0x4B0++0x3
line.long 0x0 "intr_status2,Interrupt status register for bank 2"
eventfld.long 0x0 16. "erased_page,If an erased page is detected on reads  this bit will be set. The detection of erased" "0,1"
eventfld.long 0x0 15. "page_xfer_inc,For every page of data transfer to or from the device  this bit will be set." "0,1"
newline
eventfld.long 0x0 14. "pipe_cmd_err,A pipeline command sequence has been violated. This occurs when Map 01 page read/write" "0,1"
eventfld.long 0x0 13. "rst_comp,The Cadence NAND Flash Memory Controller has completed its reset and initialization process" "0,1"
newline
eventfld.long 0x0 12. "int_act,R/B pin of device transitioned from low to high" "0,1"
eventfld.long 0x0 11. "unsup_cmd,An unsupported command was received. This interrupt is set when an invalid command is" "0,1"
newline
eventfld.long 0x0 10. "locked_blk,The address to program or erase operation is to a locked block and the operation failed" "0,1"
eventfld.long 0x0 9. "pipe_cpybck_cmd_comp,A pipeline command or a copyback bank command has completed on this particular bank" "0,1"
newline
eventfld.long 0x0 8. "erase_comp,Device erase operation complete" "0,1"
eventfld.long 0x0 7. "program_comp,Device finished the last issued program command." "0,1"
newline
eventfld.long 0x0 6. "load_comp,Device finished the last issued load command." "0,1"
eventfld.long 0x0 5. "erase_fail,Erase failure occurred in the device on issuance of a erase command. err_block_addr" "0,1"
newline
eventfld.long 0x0 4. "program_fail,Program failure occurred in the device on issuance of a program command. err_block_addr" "0,1"
eventfld.long 0x0 3. "time_out,Watchdog timer has triggered in the controller due to one of the reasons like device" "0,1"
newline
eventfld.long 0x0 2. "dma_cmd_comp,A data DMA command has completed on this bank" "0,1"
eventfld.long 0x0 0. "ecc_uncor_err,Ecc logic detected uncorrectable error while reading data from flash device." "0,1"
group.long 0x4C0++0x3
line.long 0x0 "intr_en2,Enables corresponding interrupt bit in interrupt register"
eventfld.long 0x0 16. "erased_page,If an erased page is detected on reads  this bit will be set. The detection of erased" "0,1"
eventfld.long 0x0 15. "page_xfer_inc,For every page of data transfer to or from the device  this bit will be set." "0,1"
newline
eventfld.long 0x0 14. "pipe_cmd_err,A pipeline command sequence has been violated. This occurs when Map 01 page read/write" "0,1"
eventfld.long 0x0 13. "rst_comp,A reset command has completed on this bank" "0,1"
newline
eventfld.long 0x0 12. "int_act,R/B pin of device transitioned from low to high" "0,1"
eventfld.long 0x0 11. "unsup_cmd,An unsupported command was received. This interrupt is set when an invalid command is" "0,1"
newline
eventfld.long 0x0 10. "locked_blk,The address to program or erase operation is to a locked block and the operation failed" "0,1"
eventfld.long 0x0 9. "pipe_cpybck_cmd_comp,A pipeline command or a copyback bank command has completed on this particular bank" "0,1"
newline
eventfld.long 0x0 8. "erase_comp,Device erase operation complete" "0,1"
eventfld.long 0x0 7. "program_comp,Device finished the last issued program command." "0,1"
newline
eventfld.long 0x0 6. "load_comp,Device finished the last issued load command." "0,1"
eventfld.long 0x0 5. "erase_fail,Erase failure occurred in the device on issuance of a erase command. err_block_addr" "0,1"
newline
eventfld.long 0x0 4. "program_fail,Program failure occurred in the device on issuance of a program command. err_block_addr" "0,1"
eventfld.long 0x0 3. "time_out,Watchdog timer has triggered in the controller due to one of the reasons like device" "0,1"
newline
eventfld.long 0x0 2. "dma_cmd_comp,A data DMA command has completed on this bank" "0,1"
eventfld.long 0x0 0. "ecc_uncor_err,If set  Controller will interrupt processor when Ecc logic detects uncorrectable error." "0,1"
rgroup.long 0x4D0++0x3
line.long 0x0 "page_cnt2,Decrementing page count bank 2"
hexmask.long.byte 0x0 0.--7. 1. "value,Maintains a decrementing count of the number of pages in"
rgroup.long 0x4E0++0x3
line.long 0x0 "err_page_addr2,Erred page address bank 2"
hexmask.long.word 0x0 0.--15. 1. "value,Holds the page address that resulted in a failure on program"
rgroup.long 0x4F0++0x3
line.long 0x0 "err_block_addr2,Erred block address bank 2"
hexmask.long.word 0x0 0.--15. 1. "value,Holds the block address that resulted in a failure on program"
group.long 0x500++0x3
line.long 0x0 "intr_status3,Interrupt status register for bank 3"
eventfld.long 0x0 16. "erased_page,If an erased page is detected on reads  this bit will be set. The detection of erased" "0,1"
eventfld.long 0x0 15. "page_xfer_inc,For every page of data transfer to or from the device  this bit will be set." "0,1"
newline
eventfld.long 0x0 14. "pipe_cmd_err,A pipeline command sequence has been violated. This occurs when Map 01 page read/write" "0,1"
eventfld.long 0x0 13. "rst_comp,The Cadence NAND Flash Memory Controller has completed its reset and initialization process" "0,1"
newline
eventfld.long 0x0 12. "int_act,R/B pin of device transitioned from low to high" "0,1"
eventfld.long 0x0 11. "unsup_cmd,An unsupported command was received. This interrupt is set when an invalid command is" "0,1"
newline
eventfld.long 0x0 10. "locked_blk,The address to program or erase operation is to a locked block and the operation failed" "0,1"
eventfld.long 0x0 9. "pipe_cpybck_cmd_comp,A pipeline command or a copyback bank command has completed on this particular bank" "0,1"
newline
eventfld.long 0x0 8. "erase_comp,Device erase operation complete" "0,1"
eventfld.long 0x0 7. "program_comp,Device finished the last issued program command." "0,1"
newline
eventfld.long 0x0 6. "load_comp,Device finished the last issued load command." "0,1"
eventfld.long 0x0 5. "erase_fail,Erase failure occurred in the device on issuance of a erase command. err_block_addr" "0,1"
newline
eventfld.long 0x0 4. "program_fail,Program failure occurred in the device on issuance of a program command. err_block_addr" "0,1"
eventfld.long 0x0 3. "time_out,Watchdog timer has triggered in the controller due to one of the reasons like device" "0,1"
newline
eventfld.long 0x0 2. "dma_cmd_comp,A data DMA command has completed on this bank" "0,1"
eventfld.long 0x0 0. "ecc_uncor_err,Ecc logic detected uncorrectable error while reading data from flash device." "0,1"
group.long 0x510++0x3
line.long 0x0 "intr_en3,Enables corresponding interrupt bit in interrupt register"
eventfld.long 0x0 16. "erased_page,If an erased page is detected on reads  this bit will be set. The detection of erased" "0,1"
eventfld.long 0x0 15. "page_xfer_inc,For every page of data transfer to or from the device  this bit will be set." "0,1"
newline
eventfld.long 0x0 14. "pipe_cmd_err,A pipeline command sequence has been violated. This occurs when Map 01 page read/write" "0,1"
eventfld.long 0x0 13. "rst_comp,A reset command has completed on this bank" "0,1"
newline
eventfld.long 0x0 12. "int_act,R/B pin of device transitioned from low to high" "0,1"
eventfld.long 0x0 11. "unsup_cmd,An unsupported command was received. This interrupt is set when an invalid command is" "0,1"
newline
eventfld.long 0x0 10. "locked_blk,The address to program or erase operation is to a locked block and the operation failed" "0,1"
eventfld.long 0x0 9. "pipe_cpybck_cmd_comp,A pipeline command or a copyback bank command has completed on this particular bank" "0,1"
newline
eventfld.long 0x0 8. "erase_comp,Device erase operation complete" "0,1"
eventfld.long 0x0 7. "program_comp,Device finished the last issued program command." "0,1"
newline
eventfld.long 0x0 6. "load_comp,Device finished the last issued load command." "0,1"
eventfld.long 0x0 5. "erase_fail,Erase failure occurred in the device on issuance of a erase command. err_block_addr" "0,1"
newline
eventfld.long 0x0 4. "program_fail,Program failure occurred in the device on issuance of a program command. err_block_addr" "0,1"
eventfld.long 0x0 3. "time_out,Watchdog timer has triggered in the controller due to one of the reasons like device" "0,1"
newline
eventfld.long 0x0 2. "dma_cmd_comp,A data DMA command has completed on this bank" "0,1"
eventfld.long 0x0 0. "ecc_uncor_err,If set  Controller will interrupt processor when Ecc logic detects uncorrectable error." "0,1"
rgroup.long 0x520++0x3
line.long 0x0 "page_cnt3,Decrementing page count bank 3"
hexmask.long.byte 0x0 0.--7. 1. "value,Maintains a decrementing count of the number of pages in"
rgroup.long 0x530++0x3
line.long 0x0 "err_page_addr3,Erred page address bank 3"
hexmask.long.word 0x0 0.--15. 1. "value,Holds the page address that resulted in a failure on program"
rgroup.long 0x540++0x3
line.long 0x0 "err_block_addr3,Erred block address bank 3"
hexmask.long.word 0x0 0.--15. 1. "value,Holds the block address that resulted in a failure on program"
rgroup.long 0x650++0x3
line.long 0x0 "ecccorinfo_b01,ECC Error correction Information register. Controller updates this register when it completes"
bitfld.long 0x0 15. "uncor_err_b1,Uncorrectable error occurred while reading pages for last transaction in Bank1. Uncorrectable" "0,1"
hexmask.long.byte 0x0 8.--14. 1. "max_errors_b1,Maximum of number of errors corrected per sector in Bank1. This field is not valid for"
newline
bitfld.long 0x0 7. "uncor_err_b0,Uncorrectable error occurred while reading pages for last transaction in Bank0. Uncorrectable" "0,1"
hexmask.long.byte 0x0 0.--6. 1. "max_errors_b0,Maximum of number of errors corrected per sector in Bank0. This field is not valid for"
rgroup.long 0x660++0x3
line.long 0x0 "ecccorinfo_b23,ECC Error correction Information register. Controller updates this register when it completes"
bitfld.long 0x0 15. "uncor_err_b3,Uncorrectable error occurred while reading pages for last transaction in Bank3. Uncorrectable" "0,1"
hexmask.long.byte 0x0 8.--14. 1. "max_errors_b3,Maximum of number of errors corrected per sector in Bank3. This field is not valid for"
newline
bitfld.long 0x0 7. "uncor_err_b2,Uncorrectable error occurred while reading pages for last transaction in Bank2. Uncorrectable" "0,1"
hexmask.long.byte 0x0 0.--6. 1. "max_errors_b2,Maximum of number of errors corrected per sector in Bank2. This field is not valid for"
group.long 0x700++0x3
line.long 0x0 "dma_enable,"
bitfld.long 0x0 0. "flag,Enables data DMA operation in the controller" "0,1"
group.long 0x720++0x3
line.long 0x0 "dma_intr,DMA interrupt register"
eventfld.long 0x0 6. "cmddma_idle,Command DMA became IDLE after completing all descriptors" "0,1"
eventfld.long 0x0 4. "desc_comp_channel3,Indicates CMD-DMA channel 3 descriptor execution done (updated when interrupt bit in cmd flags set)." "0,1"
newline
eventfld.long 0x0 3. "desc_comp_channel2,Indicates CMD-DMA channel 2 descriptor execution done (updated when interrupt bit in cmd flags set)." "0,1"
eventfld.long 0x0 2. "desc_comp_channel1,Indicates CMD-DMA channel 1 descriptor execution done (updated when interrupt bit in cmd flags set)." "0,1"
newline
eventfld.long 0x0 1. "desc_comp_channel0,Indicates CMD-DMA channel 0 descriptor execution done (updated when interrupt bit in cmd flags set)." "0,1"
eventfld.long 0x0 0. "target_error,Controller initiator interface received an ERROR target response for a transaction." "0,1"
group.long 0x730++0x3
line.long 0x0 "dma_intr_en,Enables corresponding interrupt bit in dma interrupt register"
eventfld.long 0x0 6. "cmddma_idle,Interrupt processor when command DMA becomes IDLE after completing all" "0,1"
eventfld.long 0x0 4. "desc_comp_channel3,Enable bit to indicates CMD-DMA channel 3 descriptor execution done (updated when interrupt bit in cmd flags set)." "0,1"
newline
eventfld.long 0x0 3. "desc_comp_channel2,Enable bit to indicates CMD-DMA channel 2 descriptor execution done (updated when interrupt bit in cmd flags set)." "0,1"
eventfld.long 0x0 2. "desc_comp_channel1,Enable bit to indicates CMD-DMA channel 1 descriptor execution done (updated when interrupt bit in cmd flags set)." "0,1"
newline
eventfld.long 0x0 1. "desc_comp_channel0,Enable bit to indicates CMD-DMA channel 0 descriptor execution done (updated when interrupt bit in cmd flags set)." "0,1"
eventfld.long 0x0 0. "target_error,Controller initiator interface received an ERROR target response for a transaction." "0,1"
rgroup.long 0x740++0x3
line.long 0x0 "target_err_addr_lo,Transaction address for which controller initiator interface received an ERROR target response."
hexmask.long.word 0x0 0.--15. 1. "value,Least significant 16 bits"
rgroup.long 0x750++0x3
line.long 0x0 "target_err_addr_hi,Transaction address for which controller initiator interface received an ERROR target response."
hexmask.long.word 0x0 0.--15. 1. "value,Most significant 16 bits"
rgroup.long 0x760++0x3
line.long 0x0 "chnl_active,Indicates CMD-DMA channel activity status"
eventfld.long 0x0 3. "channel3,CMD-DMA channel 3 is active" "0,1"
eventfld.long 0x0 2. "channel2,CMD-DMA channel 2 is active" "0,1"
newline
eventfld.long 0x0 1. "channel1,CMD-DMA channel 1 is active" "0,1"
eventfld.long 0x0 0. "channel0,CMD-DMA channel 0 is active" "0,1"
group.long 0x770++0x3
line.long 0x0 "flash_burst_length,"
hexmask.long.tbyte 0x0 8.--31. 1. "polling_sync_counter_value,Number of cycles CMDDMA channel has to wait before polling the SYNC Pointer again."
eventfld.long 0x0 4. "continous_burst,When this bit is set  the Data DMA will burst the entire page from/to the" "0,1"
newline
eventfld.long 0x0 0.--1. "value,Sets the burst used by data dma for transferring data to/from flash device." "0,1,2,3"
group.long 0x780++0x3
line.long 0x0 "chip_interleave_enable_and_allow_int_reads,"
eventfld.long 0x0 8. "cmd_dma_error_enable,This bit informs the CDMA channels to stop working on any new MAP10 Command DMAcommands from the host after encountering an" "0,1"
eventfld.long 0x0 4. "allow_int_reads_within_luns,This bit informs the controller to enable or disable simultaneous read accesses" "0,1"
newline
eventfld.long 0x0 0. "chip_interleave_enable,This bit informs the controller to enable or disable interleaving" "0,1"
group.long 0x790++0x3
line.long 0x0 "rescan_buffer_flag,Rescan buffer flag."
hexmask.long.byte 0x0 0.--3. 1. "flag,This register can be used to force rescan of buffer flags in any of the cmd-dma channels."
group.long 0x7A0++0x3
line.long 0x0 "no_of_blocks_per_lun,"
eventfld.long 0x0 28. "issue_read_before_sync,Issue LOAD cmd to flash core even if SYNC condition is not satisfied. But the data is read" "0,1"
eventfld.long 0x0 24. "update_sync_before_prog_comp,Update SYNC Pointer after the data is written to flash and dont wait for program" "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "value,Indicates the first block of next LUN. This information is used for extracting the target LUN during LUN interleaving."
group.long 0x7B0++0x3
line.long 0x0 "lun_status_cmd,Indicates the command to be sent while checking status of the next LUN."
hexmask.long.word 0x0 0.--15. 1. "value,[list][*]7:0 - Indicates the command to check the"
group.long 0x7C0++0x3
line.long 0x0 "cmd_dma_channel_error,Bits indicating CMD-DMA channel receiving an error condition. To get more information on the error. s/w needs to read the status field of the descriptor."
bitfld.long 0x0 3. "channel3,CMD-DMA channel 3 received an error." "0,1"
bitfld.long 0x0 2. "channel2,CMD-DMA channel 2 received an error." "0,1"
newline
bitfld.long 0x0 1. "channel1,CMD-DMA channel 1 received an error." "0,1"
bitfld.long 0x0 0. "channel0,CMD-DMA channel 0 received an error." "0,1"
group.long 0x7D0++0x3
line.long 0x0 "cmd_dma_channel_error_en,Enable bits indicating CMD-DMA channel receiving an error condition. To get more information on the error. s/w needs to read the status field of the descriptor."
bitfld.long 0x0 3. "channel3,enable bit for CMD-DMA channel 3 receiving an error" "0,1"
bitfld.long 0x0 2. "channel2,enable bit for CMD-DMA channel 2 receiving an error" "0,1"
newline
bitfld.long 0x0 1. "channel1,enable bit for CMD-DMA channel 1 receiving an error" "0,1"
bitfld.long 0x0 0. "channel0,enable bit for CMD-DMA channel 0 receiving an error" "0,1"
tree.end
tree "OSC1TIMER (OSC Timer Module)"
base ad:0x0
tree "OSC1TIMER0 (OSC1 Timer0 Module)"
base ad:0xFFD00000
group.long 0x0++0x3
line.long 0x0 "TIMER1LOADCOUNT,Name: Timer1 Load Count Register"
hexmask.long 0x0 0.--31. 1. "TIMER1LOADCOUNT,Value to be loaded into Timer1. This is the value from which counting"
rgroup.long 0x4++0x3
line.long 0x0 "TIMER1CURRENTVAL,Name: Timer1 Current Value"
hexmask.long 0x0 0.--31. 1. "TIMER1CURRENTVAL,Current Value of Timer1. This register is supported only"
group.long 0x8++0x3
line.long 0x0 "TIMER1CONTROLREG,Name: Timer1 Control Register"
bitfld.long 0x0 2. "TIMER_INTERRUPT_MASK,Timer interrupt mask for Timer1." "0: not masked,1: masked"
bitfld.long 0x0 1. "TIMER_MODE,Timer mode for Timer1." "0: free_running mode,1: user_defined count mode"
newline
bitfld.long 0x0 0. "TIMER_ENABLE,Timer enable bit for Timer1." "0: disable,1: enable"
rgroup.long 0xC++0x7
line.long 0x0 "TIMER1EOI,Name: Timer1 End-of-Interrupt Register"
bitfld.long 0x0 0. "TIMER1EOI,Reading from this register" "0,1"
line.long 0x4 "TIMER1INTSTAT,Name: Timer1 Interrupt Status Register"
bitfld.long 0x4 0. "TIMER1INTSTAT,Contains the interrupt status for Timer1." "0,1"
rgroup.long 0xA0++0xF
line.long 0x0 "TIMERSINTSTAT,Name: Timers Interrupt Status Register"
bitfld.long 0x0 0. "TIMERSINTSTAT,Contains the interrupt status of all timers in the component. If a bit of" "0: either timer_intr or timer_intr_n is not active..,1: either timer_intr or timer_intr_n is active.."
line.long 0x4 "TIMERSEOI,Name: Timers End-of-Interrupt Register"
bitfld.long 0x4 0. "TIMERSEOI,Reading this register returns all zeroes (0) and clears all active" "0,1"
line.long 0x8 "TIMERSRAWINTSTAT,Name: Timers Raw Interrupt Status Register"
bitfld.long 0x8 0. "TIMERSRAWINTSTAT,The register contains the unmasked interrupt status of all timers in" "0: either timer_intr or timer_intr_n is not active..,1: either timer_intr or timer_intr_n is active.."
line.long 0xC "TIMERSCOMPVERSION,Name: Timers Component Version"
hexmask.long 0xC 0.--31. 1. "TIMERSCOMPVERSION,Current revision number of the DW_apb_timers component."
tree.end
tree "OSC1TIMER1 (OSC1 Timer1 Module)"
base ad:0xFFD00100
group.long 0x0++0x3
line.long 0x0 "TIMER1LOADCOUNT,Name: Timer1 Load Count Register"
hexmask.long 0x0 0.--31. 1. "TIMER1LOADCOUNT,Value to be loaded into Timer1. This is the value from which counting"
rgroup.long 0x4++0x3
line.long 0x0 "TIMER1CURRENTVAL,Name: Timer1 Current Value"
hexmask.long 0x0 0.--31. 1. "TIMER1CURRENTVAL,Current Value of Timer1. This register is supported only"
group.long 0x8++0x3
line.long 0x0 "TIMER1CONTROLREG,Name: Timer1 Control Register"
bitfld.long 0x0 2. "TIMER_INTERRUPT_MASK,Timer interrupt mask for Timer1." "0: not masked,1: masked"
bitfld.long 0x0 1. "TIMER_MODE,Timer mode for Timer1." "0: free_running mode,1: user_defined count mode"
newline
bitfld.long 0x0 0. "TIMER_ENABLE,Timer enable bit for Timer1." "0: disable,1: enable"
rgroup.long 0xC++0x7
line.long 0x0 "TIMER1EOI,Name: Timer1 End-of-Interrupt Register"
bitfld.long 0x0 0. "TIMER1EOI,Reading from this register" "0,1"
line.long 0x4 "TIMER1INTSTAT,Name: Timer1 Interrupt Status Register"
bitfld.long 0x4 0. "TIMER1INTSTAT,Contains the interrupt status for Timer1." "0,1"
rgroup.long 0xA0++0xF
line.long 0x0 "TIMERSINTSTAT,Name: Timers Interrupt Status Register"
bitfld.long 0x0 0. "TIMERSINTSTAT,Contains the interrupt status of all timers in the component. If a bit of" "0: either timer_intr or timer_intr_n is not active..,1: either timer_intr or timer_intr_n is active.."
line.long 0x4 "TIMERSEOI,Name: Timers End-of-Interrupt Register"
bitfld.long 0x4 0. "TIMERSEOI,Reading this register returns all zeroes (0) and clears all active" "0,1"
line.long 0x8 "TIMERSRAWINTSTAT,Name: Timers Raw Interrupt Status Register"
bitfld.long 0x8 0. "TIMERSRAWINTSTAT,The register contains the unmasked interrupt status of all timers in" "0: either timer_intr or timer_intr_n is not active..,1: either timer_intr or timer_intr_n is active.."
line.long 0xC "TIMERSCOMPVERSION,Name: Timers Component Version"
hexmask.long 0xC 0.--31. 1. "TIMERSCOMPVERSION,Current revision number of the DW_apb_timers component."
tree.end
tree.end
tree "RSTMGR (Reset Manager Module)"
base ad:0xFFD11000
group.long 0x0++0xB
line.long 0x0 "stat,The 'stat' register contains bits that indicate the reset source. A field is 1 if its associated reset requester caused the reset."
eventfld.long 0x0 25. "csdaprst,This bit indicates that CS DAP block has been reset. This bit is reset to its reset value on POR  not on warm or cold reset." "0,1"
eventfld.long 0x0 24. "debugrst,'debugrst' indicates if the debug reset has been asserted. This bit is reset to its reset value on POR  not on warm or cold reset." "0,1"
eventfld.long 0x0 19. "l4wd3rst,L4 Watchdog3 triggered a hardware sequenced warm reset." "0,1"
eventfld.long 0x0 18. "l4wd2rst,L4 Watchdog2 triggered a hardware sequenced warm reset." "0,1"
newline
eventfld.long 0x0 17. "l4wd1rst,L4 Watchdog1 triggered a hardware sequenced warm reset." "0,1"
eventfld.long 0x0 16. "l4wd0rst,L4 Watchdog0 triggered a hardware sequenced warm reset." "0,1"
eventfld.long 0x0 11. "mpu3rst,MPU3 triggered a hardware sequenced warm reset." "0,1"
eventfld.long 0x0 10. "mpu2rst,MPU2 triggered a hardware sequenced warm reset." "0,1"
newline
eventfld.long 0x0 9. "mpu1rst,MPU1 triggered a hardware sequenced warm reset." "0,1"
eventfld.long 0x0 8. "mpu0rst,MPU0 triggered a hardware sequenced warm reset." "0,1"
eventfld.long 0x0 2. "sdmlastporrst,SDM triggered last por reset. This bit is reset to its reset value on POR  not on warm or cold reset." "0,1"
eventfld.long 0x0 1. "sdmwarmrst,SDM triggered warm reset." "0,1"
newline
eventfld.long 0x0 0. "sdmcoldrst,SDM triggered cold reset. This bit is reset to its reset value on POR  not on warm or cold reset." "0,1"
line.long 0x4 "mpurststat,The 'mpurststat' register contains bits which indicate SDM that a CPU and/or Core reset has been asserted by MPU Software which is triggered by writing to the 'mpumodrst' register and cpupor* fields of 'coldmodrst' register."
eventfld.long 0x4 11. "core3_irq,This bit indicates SDM that MPU software has asserted reset to core3 by writing to 'mpumodrst' register." "0,1"
eventfld.long 0x4 10. "core2_irq,This bit indicates SDM that MPU software has asserted reset to core2 by writing to 'mpumodrst' register." "0,1"
eventfld.long 0x4 9. "core1_irq,This bit indicates SDM that MPU software has asserted reset to core1 by writing to 'mpumodrst' register." "0,1"
eventfld.long 0x4 8. "core0_irq,This bit indicates SDM that MPU software has asserted reset to core0 by writing to 'mpumodrst' register." "0,1"
newline
eventfld.long 0x4 3. "cpupor3_irq,This bit indicates SDM that MPU software has asserted reset to CPU3 by writing to the 'cpupor3' bit of register 'coldmodrst'." "0,1"
eventfld.long 0x4 2. "cpupor2_irq,This bit indicates SDM that MPU software has asserted reset to CPU2 by writing to the 'cpupor2' bit of register 'coldmodrst'." "0,1"
eventfld.long 0x4 1. "cpupor1_irq,This bit indicates SDM that MPU software has asserted reset to CPU1 by writing to the 'cpupor1' bit of register 'coldmodrst'." "0,1"
eventfld.long 0x4 0. "cpupor0_irq,This bit indicates SDM that MPU software has asserted reset to CPU0 by writing to the 'cpupor0' bit of register 'coldmodrst'." "0,1"
line.long 0x8 "miscstat,The 'miscstat' register contains bits that indicate the timeout event. For timeout events. a field is 1 if its associated timeout occured as part of a hardware sequenced warm/debug reset."
eventfld.long 0x8 16. "l3nocdbgtimeout,A 1 indicates that Reset Manager's request to the NOC before starting a hardware sequenced warm/watchdog reset timed-out and the Reset Manager had to proceed with the warm/watchdog reset anyway. Reset Manager performs this handshake with.." "0,1"
eventfld.long 0x8 8. "mpul2flushtimeout,A 1 indicates that Reset Manager's handshake request to L2 Flush timed-out and the Reset Manager had to proceed with reset anyway." "0,1"
eventfld.long 0x8 3. "etrstalltimeout,A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to stall its AXI master port before starting a hardware sequenced warm/watchdog reset timed-out and the Reset Manager had to proceed with the warm/watchdog.." "0,1"
eventfld.long 0x8 2. "fpgahstimeout,A 1 indicates that Reset Manager's handshake request to FPGA before starting a hardware sequenced warm/watchdog reset timed-out and the Reset Manager had to proceed with the warm/watchdog reset anyway." "0,1"
newline
eventfld.long 0x8 0. "mpfe_hmca_draintimeout,A 1 indicates that Reset Manager's handshake request to the SDRAM Controller Subsystem timed out and the Reset Manager had to proceed with the warm/watchdog reset anyway." "0,1"
group.long 0x10++0x1F
line.long 0x0 "hdsken,This register allows software to control whether or not to perform a handshake with certain peripherals before issuing a reset. These bits are cleared on a cold reset. If these bits are not set. writing to the 'hdskreq' register to request a.."
bitfld.long 0x0 17. "debug_l3noc,This field controls whether to perform handshake with L3 NOC before asserting the csdap_rst or/and dbg_rst. If set to 1  the Reset Manager makes a request to the L3 NOC before issuing a reset. If set to 0  the handshake is not performed." "0,1"
bitfld.long 0x0 16. "l3noc_dbg,This field controls whether to perform handshake with L3 NOC before issuing a reset. If set to 1  the Reset Manager makes a request to the L3 NOC before issuing a reset. If set to 0  the handshake is not performed." "0,1"
bitfld.long 0x0 8. "l2flushen,This field controls whether the L2 cache should be flushed before the L2 cache is reset by a watchdog reset or a software-requested L2 cache reset." "0,1"
bitfld.long 0x0 3. "etrstallen,Software writes this field 1 to request to the ETR that it stalls its AXI master to the L3 Interconnect." "0,1"
newline
bitfld.long 0x0 2. "fpgahsen,This field controls whether to perform handshake with FPGA before issuing a reset. If set to 1  the Reset Manager makes a request to the FPGA before issuing a reset. If set to 0  the handshake is not performed." "0,1"
bitfld.long 0x0 0. "mpfe_hmca_drainen,This field controls whether to perform handshake with the SDRAM memory interface before issuing a reset. If set to 1  the Reset Manager makes a request to the SDRAM memory interface before issuing a reset. If set to 0  the handshake is.." "0,1"
line.long 0x4 "hdskreq,This register includes fields for software to initiate the handshake with certain peripherals. Software must clear the request bit except for 'debug_l3noc_req' once it sees the corresponding acknowledge bit has been set in the hdskack register."
bitfld.long 0x4 5. "debug_l3noc_req,Software writes this field 1 to initiate a handshake request to L3 NOC. This handshake is done to stop L3NOC accept any new transactions and allow all outstanding transactions to drain." "0,1"
bitfld.long 0x4 4. "l3noc_dbg_req,Software writes this field 1 to initiate a handshake request to L3 NOC. This handshake is done to stop L3NOC accept any new transactions and allow all outstanding transactions to drain. Software waits for the L3NOC_DBG_ACK to be active and.." "0,1"
bitfld.long 0x4 3. "etrstallreq,Software sets bit field to 1 to ask the ETR to that stall its AXI master to the L3 Interconnect." "0,1"
bitfld.long 0x4 2. "fpgahsreq,Software writes this field 1 to initiate a handshake request to FPGA. Software waits for the FPGAHSACK to be active and then writes this field to 0. Note that it is possible for the FPGA to never assert FPGAHSACK so software should timeout in.." "0,1"
newline
bitfld.long 0x4 0. "mpfe_hmca_drainreq,Software writes this field 1 to request that the SDRAM Controller Subsystem to stop accepting any new transactions and allows all outstanding transactions to drain." "0,1"
line.long 0x8 "hdskack,This register includes fields for software to detect the completion of the handshake with certain peripherals. Once the peripheral has completed the handshake. it will set the appropriate bit in this register. Once software has detected that the.."
eventfld.long 0x8 5. "debug_l3noc_ack,This field indicates that L3NOC handshake acknowledge has been received by Reset Manager. A 1 indicates that the L3NOC has acknowledged the handshake request." "0,1"
eventfld.long 0x8 4. "l3noc_dbg_ack,This field indicates that L3NOC handshake acknowledge has been received by Reset Manager. A 1 indicates that the L3NOC has acknowledged the handshake request." "0,1"
eventfld.long 0x8 3. "etrstallack,This is the acknowlege for a ETR AXI master stall initiated as a part of the ETR handshake. A 1 indicates that the ETR has stalled its AXI master." "0,1"
eventfld.long 0x8 2. "fpgahsack,This is the acknowledge that the FPGA handshake acknowledge has been received by Reset Manager. A 1 indicates that the FPGA has acknowledged the handshake request." "0,1"
newline
eventfld.long 0x8 0. "mpfe_hmca_drainack,This is the acknowledge that SDRAM handshake acknowledge has been received by Reset Manager. A 1 indicates that the SDRAM Controller Subsystem has acknowledged the handshake request." "0,1"
line.long 0xC "hdskstall,This register keeps the ETR stalled after a warm/watchdog reset occurs. If the ETR handshake is enabled in the bit field ETRSTALLEN of HDSKEN register. then the hardware will perform a handshake with the ETR before asserting a warm or watchdog.."
eventfld.long 0xC 0. "etrstallwarmrst,If ETRSTALLEN bit field is 1 and Reset manager generates the handshake request to ETR  hardware sets this bit to 1 to indicate that the stall of the ETR AXI master. Hardware leaves the ETR stalled after a warm or watchdog reset until.." "0,1"
line.long 0x10 "mpumodrst,The MPUMODRST register is used by software to trigger module resets (individual module reset signals). Writing 1 to any of these fields will cause the CPU core reset signal to be asserted if that CPU is in WFI mode. The Reset Manager hardware.."
bitfld.long 0x10 3. "core3,Resets ncorereset port of CPU3." "0,1"
bitfld.long 0x10 2. "core2,Resets ncorereset port of CPU2." "0,1"
bitfld.long 0x10 1. "core1,Resets ncorereset port of CPU1." "0,1"
bitfld.long 0x10 0. "core0,Resets ncorereset port of CPU0." "0,1"
line.long 0x14 "per0modrst,The PER0MODRST register is used by software to control module resets for Peripheral Group and Fast Peripheral Group. Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST register. It is up.."
bitfld.long 0x14 31. "dmaif7,Resets DMA channel 7 interface adapter between FPGA Fabric and HPS DMA Controller" "0,1"
bitfld.long 0x14 30. "dmaif6,Resets DMA channel 6 interface adapter between FPGA Fabric and HPS DMA Controller" "0,1"
bitfld.long 0x14 29. "dmaif5,Resets DMA channel 5 interface adapter between FPGA Fabric and HPS DMA Controller" "0,1"
bitfld.long 0x14 28. "dmaif4,Resets DMA channel 4 interface adapter between FPGA Fabric and HPS DMA Controller" "0,1"
newline
bitfld.long 0x14 27. "dmaif3,Resets DMA channel 3 interface adapter between FPGA Fabric and HPS DMA Controller." "0,1"
bitfld.long 0x14 26. "dmaif2,Resets DMA channel 2 interface adapter between FPGA Fabric and HPS DMA Controller." "0,1"
bitfld.long 0x14 25. "dmaif1,Resets DMA channel 1 interface adapter between FPGA Fabric and HPS DMA Controller" "0,1"
bitfld.long 0x14 24. "dmaif0,Resets DMA channel 0 interface adapter between FPGA Fabric and HPS DMA Controller." "0,1"
newline
bitfld.long 0x14 22. "emacptp,Resets EMAC PTP." "0,1"
bitfld.long 0x14 21. "dmaocp,Resets DMA Controller ECC OCP DIagnostics modules." "0,1"
bitfld.long 0x14 20. "spis1,Resets SPIS1 controller." "0,1"
bitfld.long 0x14 19. "spis0,Resets SPIS0 controller." "0,1"
newline
bitfld.long 0x14 18. "spim1,Resets SPIM1 controller." "0,1"
bitfld.long 0x14 17. "spim0,Resets SPIM0 controller." "0,1"
bitfld.long 0x14 16. "dma,Resets DMA controller." "0,1"
bitfld.long 0x14 15. "sdmmcocp,Resets SDMMC ECC OCP DIagnostics modules." "0,1"
newline
bitfld.long 0x14 13. "nandocp,Resets NAND ECC OCP DIagnostics modules." "0,1"
bitfld.long 0x14 12. "usb1ocp,Resets USB1 ECC OCP DIagnostics modules." "0,1"
bitfld.long 0x14 11. "usb0ocp,Resets USB0 ECC OCP DIagnostics modules." "0,1"
bitfld.long 0x14 10. "emac2ocp,Resets EMAC0 ECC OCP DIagnostics modules." "0,1"
newline
bitfld.long 0x14 9. "emac1ocp,Resets EMAC1 ECC OCP DIagnostics modules." "0,1"
bitfld.long 0x14 8. "emac0ocp,Resets EMAC0 ECC OCP DIagnostics modules." "0,1"
bitfld.long 0x14 7. "sdmmc,Resets SD/MMC controller." "0,1"
bitfld.long 0x14 5. "nand,Resets NAND flash controller." "0,1"
newline
bitfld.long 0x14 4. "usb1,Resets USB1." "0,1"
bitfld.long 0x14 3. "usb0,Resets USB0." "0,1"
bitfld.long 0x14 2. "emac2,Resets EMAC2." "0,1"
bitfld.long 0x14 1. "emac1,Resets EMAC1." "0,1"
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bitfld.long 0x14 0. "emac0,Resets EMAC0." "0,1"
line.long 0x18 "per1modrst,The PER1MODRST register is used by software to trigger module resets for Slow Peripheral Group. Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST register. It is up to software to ensure.."
bitfld.long 0x18 25. "gpio1,Resets GPIO1" "0,1"
bitfld.long 0x18 24. "gpio0,Resets GPIO0" "0,1"
bitfld.long 0x18 17. "uart1,Resets UART1" "0,1"
bitfld.long 0x18 16. "uart0,Resets UART0" "0,1"
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bitfld.long 0x18 12. "i2c4,Resets I2C4 controller" "0,1"
bitfld.long 0x18 11. "i2c3,Resets I2C3 controller" "0,1"
bitfld.long 0x18 10. "i2c2,Resets I2C2 controller" "0,1"
bitfld.long 0x18 9. "i2c1,Resets I2C1 controller" "0,1"
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bitfld.long 0x18 8. "i2c0,Resets I2C0 controller" "0,1"
bitfld.long 0x18 7. "sptimer1,Resets SP timer 1 connected to L4" "0,1"
bitfld.long 0x18 6. "sptimer0,Resets SP timer 0 connected to L4" "0,1"
bitfld.long 0x18 5. "l4systimer1,Resets l4sys_timer1" "0,1"
newline
bitfld.long 0x18 4. "l4systimer0,Resets l4sys_timer0" "0,1"
bitfld.long 0x18 3. "watchdog3,Resets Watchdog 3" "0,1"
bitfld.long 0x18 2. "watchdog2,Resets Watchdog 2" "0,1"
bitfld.long 0x18 1. "watchdog1,Resets Watchdog 1" "0,1"
newline
bitfld.long 0x18 0. "watchdog0,Resets Watchdog 0" "0,1"
line.long 0x1C "brgmodrst,The BRGMODRST register is used by software to control the bridge module resets. Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST register. It is up to software to ensure module reset.."
bitfld.long 0x1C 6. "mpfe,Resets logic in the MPFE." "0,1"
bitfld.long 0x1C 2. "fpga2soc,Resets FPGA2SOC Bridge." "0,1"
bitfld.long 0x1C 1. "lwhps2fpga,Resets LWHPS2FPGA Bridge." "0,1"
bitfld.long 0x1C 0. "soc2fpga,Resets SOC2FPGA Bridge." "0,1"
group.long 0x34++0x3
line.long 0x0 "coldmodrst,The COLDMODRST register is used by software to trigger module resets. Writing 1 to any of these fields will cause the L2 or CPU POR reset signal to be asserted if that module is in WFI mode. The Reset Manager hardware will bring the module.."
bitfld.long 0x0 8. "l2,Resets L2 shared memory system contoller." "0,1"
bitfld.long 0x0 3. "cpupor3,Resets ncpuporreset port of CPU3." "0,1"
bitfld.long 0x0 2. "cpupor2,Resets ncpuporreset port of CPU2." "0,1"
bitfld.long 0x0 1. "cpupor1,Resets ncpuporreset port of CPU1." "0,1"
newline
bitfld.long 0x0 0. "cpupor0,Resets ncpuporreset port of CPU0." "0,1"
group.long 0x3C++0x3
line.long 0x0 "dbgmodrst,The DBGMODRST register is used by software to control module resets."
bitfld.long 0x0 1. "csdap_rst,Resets logic located in the DAP domain." "0,1"
bitfld.long 0x0 0. "dbg_rst,Resets logic located in the debug domain." "0,1"
group.long 0x4C++0x3
line.long 0x0 "brgwarmmask,The 'BRGWARMMASK' register is used by software to mask the assertion of module reset signals on a warm reset. If the bit is 1. the module reset signal is asserted during a warm reset. If the bit is 0. the module reset signal is not asserted.."
bitfld.long 0x0 6. "mpfe,Masks hardware sequenced warm reset for the MPFE." "0,1"
bitfld.long 0x0 2. "fpga2soc,Masks hardware sequenced warm reset for FPGA2SOC Bridge" "0,1"
bitfld.long 0x0 1. "lwhps2fpga,Masks hardware sequenced warm reset for LWHPS2FPGA Bridge" "0,1"
bitfld.long 0x0 0. "soc2fpga,Masks hardware sequenced warm reset for SOC2FPGA Bridge." "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "tststa,Status fields used for testing the Reset Manager."
hexmask.long.byte 0x0 0.--4. 1. "rstst,Warm/cold reset control FSM state."
group.long 0x64++0xB
line.long 0x0 "hdsktimeout,The Warm Reset handshake time-out controls the amount of time to wait for the ETR. FPGA and SDRAM interface to respond to a reset handshake request. The register defaults to 10.240 l4_sys_free_clk cycles. which at 100 MHz will be 102.4.."
hexmask.long 0x0 0.--31. 1. "val,ETR  FPGA and SDRAM interface handshake time-out value."
line.long 0x4 "mpul2flushtimeout,The MPU L2 FLUSH handshake timeout will default to 1.048.576 which at 100 MHz for l4_sys_free_clk will 1048 micro-seconds. This value will be a 32 bit programmable value in SW."
hexmask.long 0x4 0.--31. 1. "val,MPU L2 flush handshake time-out value."
line.long 0x8 "dbghdsktimeout,The reset handshake time-out register controls the amount of time to wait for the L3NOC interface to respond to a reset handshake request."
hexmask.long 0x8 0.--31. 1. "val,L3NOC interface handshake time-out value."
group.long 0x80++0x3
line.long 0x0 "ocramload,SDM will set this register bit to 1 to indicate that the Onchip RAM content loading is complete. The Reset Manager will wait for this bit to be set before releasing the MPU warm resets."
bitfld.long 0x0 0. "done,SDM sets this bit to indicate the Reset Manager that the on chip ram loading is done and it is safe to proceed with the MPU reset de-assertion sequence." "0,1"
tree.end
tree "SDM (Secure Device Manager)"
base ad:0x0
tree "SDM_I2C0"
base ad:0xFF8D0100
group.long 0x0++0xB
line.long 0x0 "IC_CON,Name: I2C Control Register"
hexmask.long.word 0x0 20.--31. 1. "RSVD_IC_CON_2,Reserved bits - Read Only"
newline
rbitfld.long 0x0 19. "RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 18. "RSVD_SMBUS_ARP_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_QUICK_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 16. "RSVD_OPTIONAL_SAR_CTRL,Reserved bits - Read Only" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_CON_1,Reserved bits - Read Only"
newline
rbitfld.long 0x0 11. "RSVD_BUS_CLEAR_FEATURE_CTRL,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 10. "STOP_DET_IF_MASTER_ACTIVE,In Master mode:" "0: issues the STOP_DET irrespective of whether..,1: issues the STOP_DET interrupt only when master.."
newline
rbitfld.long 0x0 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether" "0,1"
newline
bitfld.long 0x0 8. "TX_EMPTY_CTRL,This bit controls the generation" "0,1"
newline
bitfld.long 0x0 7. "STOP_DET_IFADDRESSED,In slave mode:" "0: issues the STOP_DET irrespective of whether it's..,1: issues the STOP_DET interrrupt only when it is.."
newline
bitfld.long 0x0 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled " "0: slave is enabled,1: slave is disabled"
newline
bitfld.long 0x0 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when" "0: disable,1: enable"
newline
rbitfld.long 0x0 4. "IC_10BITADDR_MASTER_rd_only,If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.long 0x0 3. "IC_10BITADDR_SLAVE,When acting as a slave  this bit controls whether the DW_apb_i2c" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.long 0x0 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates; its" "?,1: standard mode,2: fast mode,3: high speed mode"
newline
bitfld.long 0x0 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled." "0: master disabled,1: master enabled"
line.long 0x4 "IC_TAR,Name: I2C Target Address Register"
hexmask.long.word 0x4 17.--31. 1. "RSVD_IC_TAR_2,Reserved bits - Read Only"
newline
rbitfld.long 0x4 16. "RSVD_SMBUS_QUICK_CMD,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x4 14.--15. "RSVD_IC_TAR_1,Reserved bits - Read Only" "0,1,2,3"
newline
rbitfld.long 0x4 13. "RSVD_DEVICE_ID,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x4 12. "IC_10BITADDR_MASTER,This bit controls whether the DW_apb_i2c starts its transfers in 7-" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.long 0x4 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or" "0: ignore bit 10 GC_OR_START and use IC_TAR normally,1: perform special I2C command as specified in.."
newline
bitfld.long 0x4 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0  then this bit indicates whether a" "0: General Call Address after issuing a General Call,1: START BYTE"
newline
hexmask.long.word 0x4 0.--9. 1. "IC_TAR,This is the target address for any master transaction. When"
line.long 0x8 "IC_SAR,Name: I2C Slave Address Register"
hexmask.long.tbyte 0x8 10.--31. 1. "RSVD_IC_SAR,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit"
group.long 0x10++0x13
line.long 0x0 "IC_DATA_CMD,Name: I2C Rx/Tx Data Buffer and Command Register;"
hexmask.long.tbyte 0x0 12.--31. 1. "RSVD_IC_DATA_CMD,Reserved bits - Read Only"
newline
rbitfld.long 0x0 11. "FIRST_DATA_BYTE,Indicates the first data byte" "0,1"
newline
bitfld.long 0x0 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received." "0,1"
newline
bitfld.long 0x0 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received." "0,1"
newline
bitfld.long 0x0 8. "CMD,This bit controls whether a read or a write is performed." "0: Write,1: Read"
newline
hexmask.long.byte 0x0 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus."
line.long 0x4 "IC_SS_SCL_HCNT,Name: Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x4 16.--31. 1. "RSVD_IC_SS_SCL_HIGH_COUNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x8 "IC_SS_SCL_LCNT,Name: Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x8 16.--31. 1. "RSVD_IC_SS_SCL_LOW_COUNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0xC "IC_FS_SCL_HCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"
hexmask.long.word 0xC 16.--31. 1. "RSVD_IC_FS_SCL_HCNT,Reserved bits - Read Only"
newline
hexmask.long.word 0xC 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x10 "IC_FS_SCL_LCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"
hexmask.long.word 0x10 16.--31. 1. "RSVD_IC_FS_SCL_LCNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x10 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0x2C++0x3
line.long 0x0 "IC_INTR_STAT,Name: I2C Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "RSVD_R_SCL_STUCK_AT_LOW,Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT number of ic_clk periods." "0,1"
newline
bitfld.long 0x0 13. "R_MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
newline
bitfld.long 0x0 12. "R_RESTART_DET,Indicates a RESTART condition has occurred on the I2C" "0,1"
newline
bitfld.long 0x0 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
newline
bitfld.long 0x0 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
newline
bitfld.long 0x0 9. "R_STOP_DET,The behavior of the STOP_DET interrupt status differs based on the" "0: Indicates whether a STOP condition has occurred..,1: In Master Mode"
newline
bitfld.long 0x0 8. "R_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
newline
bitfld.long 0x0 7. "R_RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "R_TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
newline
bitfld.long 0x0 5. "R_RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
newline
bitfld.long 0x0 4. "R_TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the" "0: This bit is set to 1 when the transmit buffer is..,1: This bit is set to 1 when the transmit buffer is.."
newline
bitfld.long 0x0 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
newline
bitfld.long 0x0 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
newline
bitfld.long 0x0 1. "R_RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
newline
bitfld.long 0x0 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x30++0x3
line.long 0x0 "IC_INTR_MASK,Name: I2C Interrupt Mask Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
newline
rbitfld.long 0x0 14. "RSVD_M_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 13. "M_MASTER_ON_HOLD,This bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register." "0,1"
rgroup.long 0x34++0x3
line.long 0x0 "IC_RAW_INTR_STAT,Name: I2C Raw Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_RAW_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "RSVD_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 13. "MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
newline
bitfld.long 0x0 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface" "0,1"
newline
bitfld.long 0x0 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
newline
bitfld.long 0x0 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
newline
bitfld.long 0x0 9. "STOP_DET,Indicates whether a STOP condition" "0,1"
newline
bitfld.long 0x0 8. "RAW_INTR_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
newline
bitfld.long 0x0 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
newline
bitfld.long 0x0 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
newline
bitfld.long 0x0 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status" "0: This bit is set to 1 when the transmit buffer..,1: This bit is set to 1 when the transmit buffer.."
newline
bitfld.long 0x0 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
newline
bitfld.long 0x0 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
newline
bitfld.long 0x0 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
newline
bitfld.long 0x0 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x38++0x7
line.long 0x0 "IC_RX_TL,Name: I2C Receive FIFO Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_RX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "RX_TL,Receive FIFO Threshold Level"
line.long 0x4 "IC_TX_TL,Name: I2C Transmit FIFO Threshold Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IC_TX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level"
rgroup.long 0x40++0x2B
line.long 0x0 "IC_CLR_INTR,Name: Clear Combined and Individual Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_INTR,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_INTR,Read this register to clear the combined interrupt " "0,1"
line.long 0x4 "IC_CLR_RX_UNDER,Name: Clear RX_UNDER Interrupt Register"
hexmask.long 0x4 1.--31. 1. "RSVD_IC_CLR_RX_UNDER,Reserved bits - Read Only"
newline
bitfld.long 0x4 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER" "0,1"
line.long 0x8 "IC_CLR_RX_OVER,Name: Clear RX_OVER Interrupt Register"
hexmask.long 0x8 1.--31. 1. "RSVD_IC_CLR_RX_OVER,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "CLR_RX_OVER,Read this register to clear the RX_OVER" "0,1"
line.long 0xC "IC_CLR_TX_OVER,Name: Clear TX_OVER Interrupt Register"
hexmask.long 0xC 1.--31. 1. "RSVD_IC_CLR_TX_OVER,Reserved bits - Read Only"
newline
bitfld.long 0xC 0. "CLR_TX_OVER,Read this register to clear the TX_OVER" "0,1"
line.long 0x10 "IC_CLR_RD_REQ,Name: Clear RD_REQ Interrupt Register"
hexmask.long 0x10 1.--31. 1. "RSVD_IC_CLR_RD_REQ,Reserved bits - Read Only"
newline
bitfld.long 0x10 0. "CLR_RD_REQ,Read this register to clear the RD_REQ" "0,1"
line.long 0x14 "IC_CLR_TX_ABRT,Name: Clear TX_ABRT Interrupt Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_CLR_TX_ABRT,Reserved bits - Read Only"
newline
bitfld.long 0x14 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT" "0,1"
line.long 0x18 "IC_CLR_RX_DONE,Name: Clear RX_DONE Interrupt Register"
hexmask.long 0x18 1.--31. 1. "RSVD_IC_CLR_RX_DONE,Reserved bits - Read Only"
newline
bitfld.long 0x18 0. "CLR_RX_DONE,Read this register to clear the RX_DONE" "0,1"
line.long 0x1C "IC_CLR_ACTIVITY,Name: Clear ACTIVITY Interrupt Register"
hexmask.long 0x1C 1.--31. 1. "RSVD_IC_CLR_ACTIVITY,Reserved bits - Read Only"
newline
bitfld.long 0x1C 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY" "0,1"
line.long 0x20 "IC_CLR_STOP_DET,Name: Clear STOP_DET Interrupt Register"
hexmask.long 0x20 1.--31. 1. "RSVD_IC_CLR_STOP_DET,Reserved bits - Read Only"
newline
bitfld.long 0x20 0. "CLR_STOP_DET,Read this register to clear the STOP_DET" "0,1"
line.long 0x24 "IC_CLR_START_DET,Name: Clear START_DET Interrupt Register"
hexmask.long 0x24 1.--31. 1. "RSVD_IC_CLR_START_DET,Reserved bits - Read Only"
newline
bitfld.long 0x24 0. "CLR_START_DET,Read this register to clear the START_DET" "0,1"
line.long 0x28 "IC_CLR_GEN_CALL,Name: Clear GEN_CALL Interrupt Register"
hexmask.long 0x28 1.--31. 1. "RSVD_IC_CLR_GEN_CALL,Reserved bits - Read Only"
newline
bitfld.long 0x28 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL" "0,1"
group.long 0x6C++0x3
line.long 0x0 "IC_ENABLE,Name: I2C Enable Register"
hexmask.long.word 0x0 19.--31. 1. "RSVD_IC_ENABLE_2,Reserved bits - Read Only"
newline
rbitfld.long 0x0 18. "RSVD_SMBUS_ALERT_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 17. "RSVD_SMBUS_SUSPEND_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 16. "RSVD_SMBUS_CLK_RESET,Reserved bits - Read Only" "0,1"
newline
hexmask.long.word 0x0 4.--15. 1. "RSVD_IC_ENABLE_1,Reserved bits - Read Only"
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rbitfld.long 0x0 3. "RSVD_SDA_STUCK_RECOVERY_ENABLE,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 2. "TX_CMD_BLOCK,In Master mode" "0,1"
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bitfld.long 0x0 1. "ABORT,When set  the controller initiates the transfer abort." "0: ABORT not initiated or ABORT done,1: ABORT operation in progress"
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bitfld.long 0x0 0. "ENABLE,Controls whether the DW_apb_i2c is enabled." "0: Disables DW_apb_i2c,1: Enables DW_apb_i2c"
rgroup.long 0x70++0xB
line.long 0x0 "IC_STATUS,Name: I2C Status Register"
hexmask.long.word 0x0 21.--31. 1. "RSVD_IC_STATUS_2,Reserved bits - Read Only"
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bitfld.long 0x0 20. "RSVD_SMBUS_ALERT_STATUS,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 19. "RSVD_SMBUS_SUSPEND_STATUS,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 18. "RSVD_SMBUS_SLAVE_ADDR_RESOLVED,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_ADDR_VALID,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 16. "RSVD_SMBUS_QUICK_CMD_BIT,Reserved bits - Read Only" "0,1"
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hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_STATUS_1,Reserved bits - Read Only"
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bitfld.long 0x0 11. "RSVD_SDA_STUCK_NOT_RECOVERED,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 10. "RSVD_SLV_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 9. "RSVD_SLV_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 8. "RSVD_MST_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 7. "RSVD_MST_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 6. "SLV_ACTIVITY,Slave FSM Activity Status." "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave part"
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bitfld.long 0x0 5. "MST_ACTIVITY,Master FSM Activity Status." "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
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bitfld.long 0x0 4. "RFF,Receive FIFO Completely Full." "0: Receive FIFO is not full,1: Receive FIFO is full"
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bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
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bitfld.long 0x0 2. "TFE,Transmit FIFO Completely Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
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bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 0. "IC_STATUS_ACTIVITY,I2C Activity Status." "0,1"
line.long 0x4 "IC_TXFLR,Name: I2C Transmit FIFO Level Register"
hexmask.long 0x4 7.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
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hexmask.long.byte 0x4 0.--6. 1. "TXFLR,Transmit FIFO Level."
line.long 0x8 "IC_RXFLR,Name: I2C Receive FIFO Level Register"
hexmask.long 0x8 7.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
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hexmask.long.byte 0x8 0.--6. 1. "RXFLR,Receive FIFO Level."
group.long 0x7C++0x3
line.long 0x0 "IC_SDA_HOLD,Name: I2C SDA Hold Time Length Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_SDA_HOLD,Reserved bits - Read Only"
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hexmask.long.byte 0x0 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time"
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hexmask.long.word 0x0 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time"
rgroup.long 0x80++0x3
line.long 0x0 "IC_TX_ABRT_SOURCE,Name: I2C Transmit Abort Source Register"
hexmask.long.word 0x0 23.--31. 1. "TX_FLUSH_CNT,This field indicates the"
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bitfld.long 0x0 21.--22. "RSVD_IC_TX_ABRT_SOURCE,Reserved bits - Read Only" "0,1,2,3"
newline
bitfld.long 0x0 18.--20. "RSVD_ABRT_DEVICE_WRITE,Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 17. "RSVD_ABRT_SDA_STUCK_AT_LOW," "0,1"
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bitfld.long 0x0 16. "ABRT_USER_ABRT,This is a master-mode-only bit. Master has" "0,1"
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bitfld.long 0x0 15. "ABRT_SLVRD_INTX,1: When the processor side responds to" "?,1: When the processor side responds to"
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bitfld.long 0x0 14. "ABRT_SLV_ARBLOST,1: Slave lost the bus while transmitting" "?,1: Slave lost the bus while transmitting"
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bitfld.long 0x0 13. "ABRT_SLVFLUSH_TXFIFO,1: Slave has received a read command" "?,1: Slave has received a read command"
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bitfld.long 0x0 12. "ARB_LOST,1: Master has lost arbitration  or if" "?,1: Master has lost arbitration"
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bitfld.long 0x0 11. "ABRT_MASTER_DIS,1: User tries to initiate a Master" "?,1: User tries to initiate a Master"
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bitfld.long 0x0 10. "ABRT_10B_RD_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
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bitfld.long 0x0 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9  the source of the" "?,1: The restart is disabled"
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bitfld.long 0x0 8. "ABRT_HS_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
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bitfld.long 0x0 7. "ABRT_SBYTE_ACKDET,1: Master has sent a START Byte and" "?,1: Master has sent a START Byte and"
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bitfld.long 0x0 6. "ABRT_HS_ACKDET,1: Master is in High Speed mode and" "?,1: Master is in High Speed mode and"
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bitfld.long 0x0 5. "ABRT_GCALL_READ,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
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bitfld.long 0x0 4. "ABRT_GCALL_NOACK,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
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bitfld.long 0x0 3. "ABRT_TXDATA_NOACK,1: This is a master-mode only bit." "?,1: This is a master-mode only bit"
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bitfld.long 0x0 2. "ABRT_10ADDR2_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
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bitfld.long 0x0 1. "ABRT_10ADDR1_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
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bitfld.long 0x0 0. "ABRT_7B_ADDR_NOACK,1: Master is in 7-bit addressing mode" "?,1: Master is in 7-bit addressing mode"
group.long 0x84++0x17
line.long 0x0 "IC_SLV_DATA_NACK_ONLY,Name: Generate Slave Data NACK Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_SLV_DATA_NACK_ONLY,Reserved bits - Read Only"
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bitfld.long 0x0 0. "NACK,Generate NACK." "0: generate NACK/ACK normally,1: generate NACK after data byte received"
line.long 0x4 "IC_DMA_CR,Name: DMA Control Register"
hexmask.long 0x4 2.--31. 1. "RSVD_IC_DMA_CR_2_31,Reserved bits [31:1] - Read Only"
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bitfld.long 0x4 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
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bitfld.long 0x4 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x8 "IC_DMA_TDLR,Name: DMA Transmit Data Level Register"
hexmask.long 0x8 6.--31. 1. "RSVD_DMA_TDLR,Reserved bits - Read Only"
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hexmask.long.byte 0x8 0.--5. 1. "DMATDL,Transmit Data Level."
line.long 0xC "IC_DMA_RDLR,Name: I2C Receive Data Level Register"
hexmask.long 0xC 6.--31. 1. "RSVD_DMA_RDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0xC 0.--5. 1. "DMARDL,Receive Data Level."
line.long 0x10 "IC_SDA_SETUP,Name: I2C SDA Setup Register"
hexmask.long.tbyte 0x10 8.--31. 1. "RSVD_IC_SDA_SETUP,Reserved bits - Read Only"
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hexmask.long.byte 0x10 0.--7. 1. "SDA_SETUP,SDA Setup."
line.long 0x14 "IC_ACK_GENERAL_CALL,Name: I2C ACK General Call Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_ACK_GEN_1_31,Reserved bits [31:1] - Read Only"
newline
bitfld.long 0x14 0. "ACK_GEN_CALL,ACK General Call." "0,1"
rgroup.long 0x9C++0x3
line.long 0x0 "IC_ENABLE_STATUS,Name: I2C Enable Status Register"
hexmask.long 0x0 3.--31. 1. "RSVD_IC_ENABLE_STATUS,Reserved bits - Read Only"
newline
bitfld.long 0x0 2. "SLV_RX_DATA_LOST,Slave Received Data Lost." "0,1"
newline
bitfld.long 0x0 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit  Receive)." "0,1"
newline
bitfld.long 0x0 0. "IC_EN,ic_en Status." "0,1"
group.long 0xA0++0x3
line.long 0x0 "IC_FS_SPKLEN,Name: I2C SS. FS or FM+ spike suppression limit"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_FS_SPKLEN,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0xA8++0x3
line.long 0x0 "IC_CLR_RESTART_DET,Name: Clear RESTART_DET Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_RESTART_DET,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "IC_COMP_PARAM_1,Name: Component Parameter Register 1"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_COMP_PARAM_1,Reserved bits - Read Only"
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hexmask.long.byte 0x0 16.--23. 1. "TX_BUFFER_DEPTH,The value of this register is derived"
newline
hexmask.long.byte 0x0 8.--15. 1. "RX_BUFFER_DEPTH,The value of this register is"
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bitfld.long 0x0 7. "ADD_ENCODED_PARAMS,The value of this register is derived" "0: False,1: True"
newline
bitfld.long 0x0 6. "HAS_DMA,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 5. "INTR_IO,The value of this register is" "0: Individual,1: Combined"
newline
bitfld.long 0x0 4. "HC_COUNT_VALUES,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 2.--3. "MAX_SPEED_MODE,The value of this register is" "0: Reserved,1: Standard,2: Fast,3: High"
newline
bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,The value of this register is" "0: 8 bits,1: 16 bits,2: 32 bits,3: Reserved"
line.long 0x4 "IC_COMP_VERSION,Name: I2C Component Version Register"
hexmask.long 0x4 0.--31. 1. "IC_COMP_VERSION,Specific values for this register are"
line.long 0x8 "IC_COMP_TYPE,Name: I2C Component Type Register"
hexmask.long 0x8 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number"
tree.end
tree "SDM_I2C1"
base ad:0xFF8D0200
group.long 0x0++0xB
line.long 0x0 "IC_CON,Name: I2C Control Register"
hexmask.long.word 0x0 20.--31. 1. "RSVD_IC_CON_2,Reserved bits - Read Only"
newline
rbitfld.long 0x0 19. "RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 18. "RSVD_SMBUS_ARP_EN,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 17. "SMBUS_SLAVE_QUICK_EN,If this bit is set to 1  DW_apb_i2c slave only receives Quick commands in SMBus Mode." "0,1"
newline
rbitfld.long 0x0 16. "RSVD_OPTIONAL_SAR_CTRL,Reserved bits - Read Only" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_CON_1,Reserved bits - Read Only"
newline
bitfld.long 0x0 11. "BUS_CLEAR_FEATURE_CTRL,In Master mode:" "0: Bus Clear Feature is Disabled,1: Bus Clear Feature is enabled"
newline
rbitfld.long 0x0 10. "STOP_DET_IF_MASTER_ACTIVE,In Master mode:" "0: issues the STOP_DET irrespective of whether..,1: issues the STOP_DET interrupt only when master.."
newline
rbitfld.long 0x0 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether" "0,1"
newline
bitfld.long 0x0 8. "TX_EMPTY_CTRL,This bit controls the generation" "0,1"
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bitfld.long 0x0 7. "STOP_DET_IFADDRESSED,In slave mode:" "0: issues the STOP_DET irrespective of whether it's..,1: issues the STOP_DET interrrupt only when it is.."
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bitfld.long 0x0 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled " "0: slave is enabled,1: slave is disabled"
newline
bitfld.long 0x0 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when" "0: disable,1: enable"
newline
rbitfld.long 0x0 4. "IC_10BITADDR_MASTER_rd_only,If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is" "0: 7-bit addressing,1: 10-bit addressing"
newline
bitfld.long 0x0 3. "IC_10BITADDR_SLAVE,When acting as a slave  this bit controls whether the DW_apb_i2c" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates; its" "?,1: standard mode,2: fast mode,3: high speed mode"
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bitfld.long 0x0 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled." "0: master disabled,1: master enabled"
line.long 0x4 "IC_TAR,Name: I2C Target Address Register"
hexmask.long.word 0x4 17.--31. 1. "RSVD_IC_TAR_2,Reserved bits - Read Only"
newline
bitfld.long 0x4 16. "SMBUS_QUICK_CMD,If bit 11 (SPECIAL) is set to 1  then this bit indicates whether a Quick command is to be performed by the DW_apb_i2c." "0,1"
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rbitfld.long 0x4 14.--15. "RSVD_IC_TAR_1,Reserved bits - Read Only" "0,1,2,3"
newline
rbitfld.long 0x4 13. "RSVD_DEVICE_ID,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x4 12. "IC_10BITADDR_MASTER,This bit controls whether the DW_apb_i2c starts its transfers in 7-" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x4 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or" "0: ignore bit 10 GC_OR_START and use IC_TAR normally,1: perform special I2C command as specified in.."
newline
bitfld.long 0x4 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0  then this bit indicates whether a" "0: General Call Address after issuing a General Call,1: START BYTE"
newline
hexmask.long.word 0x4 0.--9. 1. "IC_TAR,This is the target address for any master transaction. When"
line.long 0x8 "IC_SAR,Name: I2C Slave Address Register"
hexmask.long.tbyte 0x8 10.--31. 1. "RSVD_IC_SAR,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit"
group.long 0x10++0x13
line.long 0x0 "IC_DATA_CMD,Name: I2C Rx/Tx Data Buffer and Command Register;"
hexmask.long.tbyte 0x0 12.--31. 1. "RSVD_IC_DATA_CMD,Reserved bits - Read Only"
newline
rbitfld.long 0x0 11. "FIRST_DATA_BYTE,Indicates the first data byte" "0,1"
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bitfld.long 0x0 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received." "0,1"
newline
bitfld.long 0x0 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received." "0,1"
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bitfld.long 0x0 8. "CMD,This bit controls whether a read or a write is performed." "0: Write,1: Read"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus."
line.long 0x4 "IC_SS_SCL_HCNT,Name: Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x4 16.--31. 1. "RSVD_IC_SS_SCL_HIGH_COUNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x8 "IC_SS_SCL_LCNT,Name: Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x8 16.--31. 1. "RSVD_IC_SS_SCL_LOW_COUNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0xC "IC_FS_SCL_HCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"
hexmask.long.word 0xC 16.--31. 1. "RSVD_IC_FS_SCL_HCNT,Reserved bits - Read Only"
newline
hexmask.long.word 0xC 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x10 "IC_FS_SCL_LCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"
hexmask.long.word 0x10 16.--31. 1. "RSVD_IC_FS_SCL_LCNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x10 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0x2C++0x3
line.long 0x0 "IC_INTR_STAT,Name: I2C Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "R_SCL_STUCK_AT_LOW,Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT number of ic_clk periods." "0,1"
newline
bitfld.long 0x0 13. "R_MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
newline
bitfld.long 0x0 12. "R_RESTART_DET,Indicates a RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
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bitfld.long 0x0 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 9. "R_STOP_DET,The behavior of the STOP_DET interrupt status differs based on the" "0: Indicates whether a STOP condition has occurred..,1: In Master Mode"
newline
bitfld.long 0x0 8. "R_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
newline
bitfld.long 0x0 7. "R_RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "R_TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
newline
bitfld.long 0x0 5. "R_RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
newline
bitfld.long 0x0 4. "R_TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the" "0: This bit is set to 1 when the transmit buffer is..,1: This bit is set to 1 when the transmit buffer is.."
newline
bitfld.long 0x0 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
newline
bitfld.long 0x0 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
newline
bitfld.long 0x0 1. "R_RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
newline
bitfld.long 0x0 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x30++0x3
line.long 0x0 "IC_INTR_MASK,Name: I2C Interrupt Mask Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "M_SCL_STUCK_AT_LOW,This bit masks the R_SCL_STUCK_AT_LOW interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 13. "M_MASTER_ON_HOLD,This bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register." "0,1"
rgroup.long 0x34++0x3
line.long 0x0 "IC_RAW_INTR_STAT,Name: I2C Raw Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_RAW_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "SCL_STUCK_AT_LOW,Indicates" "0,1"
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bitfld.long 0x0 13. "MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
newline
bitfld.long 0x0 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface" "0,1"
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bitfld.long 0x0 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
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bitfld.long 0x0 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 9. "STOP_DET,Indicates whether a STOP condition" "0,1"
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bitfld.long 0x0 8. "RAW_INTR_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
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bitfld.long 0x0 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
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bitfld.long 0x0 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
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bitfld.long 0x0 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status" "0: This bit is set to 1 when the transmit buffer..,1: This bit is set to 1 when the transmit buffer.."
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bitfld.long 0x0 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
newline
bitfld.long 0x0 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
newline
bitfld.long 0x0 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
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bitfld.long 0x0 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x38++0x7
line.long 0x0 "IC_RX_TL,Name: I2C Receive FIFO Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_RX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "RX_TL,Receive FIFO Threshold Level"
line.long 0x4 "IC_TX_TL,Name: I2C Transmit FIFO Threshold Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IC_TX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level"
rgroup.long 0x40++0x2B
line.long 0x0 "IC_CLR_INTR,Name: Clear Combined and Individual Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_INTR,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_INTR,Read this register to clear the combined interrupt " "0,1"
line.long 0x4 "IC_CLR_RX_UNDER,Name: Clear RX_UNDER Interrupt Register"
hexmask.long 0x4 1.--31. 1. "RSVD_IC_CLR_RX_UNDER,Reserved bits - Read Only"
newline
bitfld.long 0x4 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER" "0,1"
line.long 0x8 "IC_CLR_RX_OVER,Name: Clear RX_OVER Interrupt Register"
hexmask.long 0x8 1.--31. 1. "RSVD_IC_CLR_RX_OVER,Reserved bits - Read Only"
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bitfld.long 0x8 0. "CLR_RX_OVER,Read this register to clear the RX_OVER" "0,1"
line.long 0xC "IC_CLR_TX_OVER,Name: Clear TX_OVER Interrupt Register"
hexmask.long 0xC 1.--31. 1. "RSVD_IC_CLR_TX_OVER,Reserved bits - Read Only"
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bitfld.long 0xC 0. "CLR_TX_OVER,Read this register to clear the TX_OVER" "0,1"
line.long 0x10 "IC_CLR_RD_REQ,Name: Clear RD_REQ Interrupt Register"
hexmask.long 0x10 1.--31. 1. "RSVD_IC_CLR_RD_REQ,Reserved bits - Read Only"
newline
bitfld.long 0x10 0. "CLR_RD_REQ,Read this register to clear the RD_REQ" "0,1"
line.long 0x14 "IC_CLR_TX_ABRT,Name: Clear TX_ABRT Interrupt Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_CLR_TX_ABRT,Reserved bits - Read Only"
newline
bitfld.long 0x14 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT" "0,1"
line.long 0x18 "IC_CLR_RX_DONE,Name: Clear RX_DONE Interrupt Register"
hexmask.long 0x18 1.--31. 1. "RSVD_IC_CLR_RX_DONE,Reserved bits - Read Only"
newline
bitfld.long 0x18 0. "CLR_RX_DONE,Read this register to clear the RX_DONE" "0,1"
line.long 0x1C "IC_CLR_ACTIVITY,Name: Clear ACTIVITY Interrupt Register"
hexmask.long 0x1C 1.--31. 1. "RSVD_IC_CLR_ACTIVITY,Reserved bits - Read Only"
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bitfld.long 0x1C 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY" "0,1"
line.long 0x20 "IC_CLR_STOP_DET,Name: Clear STOP_DET Interrupt Register"
hexmask.long 0x20 1.--31. 1. "RSVD_IC_CLR_STOP_DET,Reserved bits - Read Only"
newline
bitfld.long 0x20 0. "CLR_STOP_DET,Read this register to clear the STOP_DET" "0,1"
line.long 0x24 "IC_CLR_START_DET,Name: Clear START_DET Interrupt Register"
hexmask.long 0x24 1.--31. 1. "RSVD_IC_CLR_START_DET,Reserved bits - Read Only"
newline
bitfld.long 0x24 0. "CLR_START_DET,Read this register to clear the START_DET" "0,1"
line.long 0x28 "IC_CLR_GEN_CALL,Name: Clear GEN_CALL Interrupt Register"
hexmask.long 0x28 1.--31. 1. "RSVD_IC_CLR_GEN_CALL,Reserved bits - Read Only"
newline
bitfld.long 0x28 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL" "0,1"
group.long 0x6C++0x3
line.long 0x0 "IC_ENABLE,Name: I2C Enable Register"
hexmask.long.word 0x0 19.--31. 1. "RSVD_IC_ENABLE_2,Reserved bits - Read Only"
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bitfld.long 0x0 18. "SMBUS_ALERT_EN,The SMBUS_ALERT_CTRL register bit is used to control assertion of SMBALERT signal." "?,1: Assert SMBALERT signal"
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bitfld.long 0x0 17. "SMBUS_SUSPEND_EN,The SMBUS_SUSPEND_EN register bit is used to control assertion and de-assertion of SMBSUS signal." "0: De-assert SMBSUS signal,1: Assert SMBSUS signal"
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bitfld.long 0x0 16. "SMBUS_CLK_RESET,This bit is used in SMBus Host mode to initiate the SMBus Master Clock Reset." "0,1"
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hexmask.long.word 0x0 4.--15. 1. "RSVD_IC_ENABLE_1,Reserved bits - Read Only"
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bitfld.long 0x0 3. "SDA_STUCK_RECOVERY_ENABLE,If SDA is stuck at low indicated through the ABRT interrupt (IC_TX_ABRT_SOURCE[17]) " "0,1"
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bitfld.long 0x0 2. "TX_CMD_BLOCK,In Master mode" "0,1"
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bitfld.long 0x0 1. "ABORT,When set  the controller initiates the transfer abort." "0: ABORT not initiated or ABORT done,1: ABORT operation in progress"
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bitfld.long 0x0 0. "ENABLE,Controls whether the DW_apb_i2c is enabled." "0: Disables DW_apb_i2c,1: Enables DW_apb_i2c"
rgroup.long 0x70++0xB
line.long 0x0 "IC_STATUS,Name: I2C Status Register"
hexmask.long.word 0x0 21.--31. 1. "RSVD_IC_STATUS_2,Reserved bits - Read Only"
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bitfld.long 0x0 20. "SMBUS_ALERT_STATUS,This bit indicates the status of the SMBus Alert signal (ic_smbalert_in_n) inverted." "0,1"
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bitfld.long 0x0 19. "SMBUS_SUSPEND_STATUS,This bit indicates the status of the SMBus Suspend signal (ic_smbsus_in_n)eived." "0,1"
newline
bitfld.long 0x0 18. "RSVD_SMBUS_SLAVE_ADDR_RESOLVED,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_ADDR_VALID,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 16. "SMBUS_QUICK_CMD_BIT,This bit indicates the R/W bit of the Quick command received." "0,1"
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hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_STATUS_1,Reserved bits - Read Only"
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bitfld.long 0x0 11. "SDA_STUCK_NOT_RECOVERED,This bit indicates that SDA stuck at low is not recovered after the recovery mechanism." "0,1"
newline
bitfld.long 0x0 10. "RSVD_SLV_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 9. "RSVD_SLV_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 8. "RSVD_MST_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 7. "RSVD_MST_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 6. "SLV_ACTIVITY,Slave FSM Activity Status." "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave part"
newline
bitfld.long 0x0 5. "MST_ACTIVITY,Master FSM Activity Status." "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
newline
bitfld.long 0x0 4. "RFF,Receive FIFO Completely Full." "0: Receive FIFO is not full,1: Receive FIFO is full"
newline
bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
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bitfld.long 0x0 2. "TFE,Transmit FIFO Completely Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
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bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 0. "IC_STATUS_ACTIVITY,I2C Activity Status." "0,1"
line.long 0x4 "IC_TXFLR,Name: I2C Transmit FIFO Level Register"
hexmask.long 0x4 7.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
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hexmask.long.byte 0x4 0.--6. 1. "TXFLR,Transmit FIFO Level."
line.long 0x8 "IC_RXFLR,Name: I2C Receive FIFO Level Register"
hexmask.long 0x8 7.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
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hexmask.long.byte 0x8 0.--6. 1. "RXFLR,Receive FIFO Level."
group.long 0x7C++0x3
line.long 0x0 "IC_SDA_HOLD,Name: I2C SDA Hold Time Length Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_SDA_HOLD,Reserved bits - Read Only"
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hexmask.long.byte 0x0 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time"
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hexmask.long.word 0x0 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time"
rgroup.long 0x80++0x3
line.long 0x0 "IC_TX_ABRT_SOURCE,Name: I2C Transmit Abort Source Register"
hexmask.long.word 0x0 23.--31. 1. "TX_FLUSH_CNT,This field indicates the"
newline
bitfld.long 0x0 21.--22. "RSVD_IC_TX_ABRT_SOURCE,Reserved bits - Read Only" "0,1,2,3"
newline
bitfld.long 0x0 18.--20. "RSVD_ABRT_DEVICE_WRITE,Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 17. "ABRT_SDA_STUCK_AT_LOW,Master detects the SDA Stuck at low for the IC_SDA_STUCK_AT_LOW_TIMEOUT value of ic_clks." "0,1"
newline
bitfld.long 0x0 16. "ABRT_USER_ABRT,This is a master-mode-only bit. Master has" "0,1"
newline
bitfld.long 0x0 15. "ABRT_SLVRD_INTX,1: When the processor side responds to" "?,1: When the processor side responds to"
newline
bitfld.long 0x0 14. "ABRT_SLV_ARBLOST,1: Slave lost the bus while transmitting" "?,1: Slave lost the bus while transmitting"
newline
bitfld.long 0x0 13. "ABRT_SLVFLUSH_TXFIFO,1: Slave has received a read command" "?,1: Slave has received a read command"
newline
bitfld.long 0x0 12. "ARB_LOST,1: Master has lost arbitration  or if" "?,1: Master has lost arbitration"
newline
bitfld.long 0x0 11. "ABRT_MASTER_DIS,1: User tries to initiate a Master" "?,1: User tries to initiate a Master"
newline
bitfld.long 0x0 10. "ABRT_10B_RD_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
newline
bitfld.long 0x0 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9  the source of the" "?,1: The restart is disabled"
newline
bitfld.long 0x0 8. "ABRT_HS_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
newline
bitfld.long 0x0 7. "ABRT_SBYTE_ACKDET,1: Master has sent a START Byte and" "?,1: Master has sent a START Byte and"
newline
bitfld.long 0x0 6. "ABRT_HS_ACKDET,1: Master is in High Speed mode and" "?,1: Master is in High Speed mode and"
newline
bitfld.long 0x0 5. "ABRT_GCALL_READ,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
newline
bitfld.long 0x0 4. "ABRT_GCALL_NOACK,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
newline
bitfld.long 0x0 3. "ABRT_TXDATA_NOACK,1: This is a master-mode only bit." "?,1: This is a master-mode only bit"
newline
bitfld.long 0x0 2. "ABRT_10ADDR2_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
newline
bitfld.long 0x0 1. "ABRT_10ADDR1_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
newline
bitfld.long 0x0 0. "ABRT_7B_ADDR_NOACK,1: Master is in 7-bit addressing mode" "?,1: Master is in 7-bit addressing mode"
group.long 0x84++0x17
line.long 0x0 "IC_SLV_DATA_NACK_ONLY,Name: Generate Slave Data NACK Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_SLV_DATA_NACK_ONLY,Reserved bits - Read Only"
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bitfld.long 0x0 0. "NACK,Generate NACK." "0: generate NACK/ACK normally,1: generate NACK after data byte received"
line.long 0x4 "IC_DMA_CR,Name: DMA Control Register"
hexmask.long 0x4 2.--31. 1. "RSVD_IC_DMA_CR_2_31,Reserved bits [31:1] - Read Only"
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bitfld.long 0x4 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
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bitfld.long 0x4 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x8 "IC_DMA_TDLR,Name: DMA Transmit Data Level Register"
hexmask.long 0x8 6.--31. 1. "RSVD_DMA_TDLR,Reserved bits - Read Only"
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hexmask.long.byte 0x8 0.--5. 1. "DMATDL,Transmit Data Level."
line.long 0xC "IC_DMA_RDLR,Name: I2C Receive Data Level Register"
hexmask.long 0xC 6.--31. 1. "RSVD_DMA_RDLR,Reserved bits - Read Only"
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hexmask.long.byte 0xC 0.--5. 1. "DMARDL,Receive Data Level."
line.long 0x10 "IC_SDA_SETUP,Name: I2C SDA Setup Register"
hexmask.long.tbyte 0x10 8.--31. 1. "RSVD_IC_SDA_SETUP,Reserved bits - Read Only"
newline
hexmask.long.byte 0x10 0.--7. 1. "SDA_SETUP,SDA Setup."
line.long 0x14 "IC_ACK_GENERAL_CALL,Name: I2C ACK General Call Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_ACK_GEN_1_31,Reserved bits [31:1] - Read Only"
newline
bitfld.long 0x14 0. "ACK_GEN_CALL,ACK General Call." "0,1"
rgroup.long 0x9C++0x3
line.long 0x0 "IC_ENABLE_STATUS,Name: I2C Enable Status Register"
hexmask.long 0x0 3.--31. 1. "RSVD_IC_ENABLE_STATUS,Reserved bits - Read Only"
newline
bitfld.long 0x0 2. "SLV_RX_DATA_LOST,Slave Received Data Lost." "0,1"
newline
bitfld.long 0x0 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit  Receive)." "0,1"
newline
bitfld.long 0x0 0. "IC_EN,ic_en Status." "0,1"
group.long 0xA0++0x3
line.long 0x0 "IC_FS_SPKLEN,Name: I2C SS. FS or FM+ spike suppression limit"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_FS_SPKLEN,Reserved bits - Read Only"
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hexmask.long.byte 0x0 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0xA8++0x3
line.long 0x0 "IC_CLR_RESTART_DET,Name: Clear RESTART_DET Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_RESTART_DET,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET" "0,1"
group.long 0xAC++0x7
line.long 0x0 "IC_SCL_STUCK_AT_LOW_TIMEOUT,Name: I2C SCL Stuck at Low Timeout"
hexmask.long 0x0 0.--31. 1. "IC_SCL_STUCK_LOW_TIMEOUT,DW_apb_i2c generate the interrupt to indicate SCL stuck at low"
line.long 0x4 "IC_SDA_STUCK_AT_LOW_TIMEOUT,Name: I2C SDA Stuck at Low Timeout"
hexmask.long 0x4 0.--31. 1. "IC_SDA_STUCK_LOW_TIMEOUT,DW_apb_i2c generate the interrupt to an tx abort interrupt"
rgroup.long 0xB4++0x3
line.long 0x0 "IC_CLR_SCL_STUCK_DET,Name: Clear SCL Stuck at Low Detect Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_CLR_SCL_STUCK_DET,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_SCL_STUCK_DET,Read this register to clear the SCL_STUCT_AT_LOW interrupt (bit 15) of the IC_RAW_INTR_STAT register." "0,1"
group.long 0xBC++0xB
line.long 0x0 "IC_SMBUS_CLK_LOW_SEXT,Name: SMBus Slave Clock Extend Timeout Register"
hexmask.long 0x0 0.--31. 1. "SMBUS_CLK_LOW_SEXT_TIMEOUT,This field is used to detect the Slave Clock Extend timeout (tLOW:SEXT) in master mode"
line.long 0x4 "IC_SMBUS_CLK_LOW_MEXT,Name: SMBus Master Clock Extend Timeout Register"
hexmask.long 0x4 0.--31. 1. "SMBUS_CLK_LOW_MEXT_TIMEOUT,This field is used to detect the Master extend SMBus clock (SMBCLK) timeout defined"
line.long 0x8 "IC_SMBUS_THIGH_MAX_IDLE_COUNT,Name: SMBus Master Idle Count After Reset Register"
hexmask.long.word 0x8 16.--31. 1. "RSVD_SMBUS_THIGH_MAX_BUS_IDLE_CNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--15. 1. "SMBUS_THIGH_MAX_BUS_IDLE_CNT,This field is used to set the required Bus-Idle time period used when a master has been dynamically added to the bus and may"
rgroup.long 0xC8++0x3
line.long 0x0 "IC_SMBUS_INTR_STAT,Name: SMBUS Interrupt Status Register"
hexmask.long.tbyte 0x0 11.--31. 1. "RSVD_IC_SMBUS_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 10. "R_SMBUS_ALERT_DET,Indicates whether a SMBALERT (ic_smbalert_in_n) signal is driven low by the slave." "0,1"
newline
bitfld.long 0x0 9. "R_SMBUS_SUSPEND_DET,Indicates whether a SMBSUS (ic_smbsus_in_n) signal is driven low by the Host." "0,1"
newline
bitfld.long 0x0 8. "RSVD_R_SLV_RX_PEC_NACK,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 7. "RSVD_R_ARP_ASSGN_ADDR_CMD_DET,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 6. "RSVD_R_ARP_GET_UDID_CMD_DET,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 5. "RSVD_R_ARP_RST_CMD_DET,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 4. "RSVD_R_ARP_PREPARE_CMD_DET,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 3. "R_HOST_NOTIFY_MST_DET,Indicates whether a Notify ARP Master ARP command has been received." "0,1"
newline
bitfld.long 0x0 2. "R_QUICK_CMD_DET,Indicates whether a Quick command has been received on the SMBus interface regardless of whether DW_apb_i2c is operating in slave or master mode." "0,1"
newline
bitfld.long 0x0 1. "R_MST_CLOCK_EXTND_TIMEOUT,Indicates whether the Master device transaction (START-to-ACK  ACK-to-ACK  or ACK-to-STOP) from START to STOP exceeds IC_SMBUS_CLOCK_LOW_MEXT time with in each byte of message." "0,1"
newline
bitfld.long 0x0 0. "R_SLV_CLOCK_EXTND_TIMEOUT,Indicates whether the transaction from Slave (i.e from START to STOP) exceeds IC_SMBUS_CLOCK_LOW_SEXT time." "0,1"
group.long 0xCC++0x3
line.long 0x0 "IC_SMBUS_INTR_MASK,Name: SMBus Interrupt Mask Register"
hexmask.long.tbyte 0x0 11.--31. 1. "RSVD_IC_SMBUS_INTR_MASK,Reserved bits - Read Only"
newline
bitfld.long 0x0 10. "M_SMBUS_ALERT_DET,This bit masks the R_SMBUS_ALERT_DET interrupt in IC_SMBUS_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 9. "M_SMBUS_SUSPEND_DET,This bit masks the R_SMBUS_SUSPEND_DET interrupt in IC_SMBUS_INTR_STAT register." "0,1"
newline
hexmask.long.byte 0x0 4.--8. 1. "RSVD_M_ARP_4_8,Reserved For ARP Related Mask bits."
newline
bitfld.long 0x0 3. "M_HOST_NOTIFY_MST_DET,This bit masks the R_HOST_NOTIFY_MST_DET interrupt in IC_SMBUS_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 2. "M_QUICK_CMD_DET,This bit masks the R_QUICK_CMD_DET interrupt in IC_SMBUS_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 1. "M_MST_CLOCK_EXTND_TIMEOUT,This bit masks the R_MST_CLOCK_EXTND_TIMEOUT interrupt in IC_SMBUS_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 0. "M_SLV_CLOCK_EXTND_TIMEOUT,This bit masks the R_SLV_CLOCK_EXTND_TIMEOUT interrupt in IC_SMBUS_INTR_STAT register." "0,1"
rgroup.long 0xD0++0x3
line.long 0x0 "IC_SMBUS_RAW_INTR_STAT,Name: SMBus Raw Interrupt Status Register"
hexmask.long.tbyte 0x0 11.--31. 1. "RSVD_IC_SMBUS_RAW_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 10. "SMBUS_ALERT_DET,Indicates whether a SMBALERT (ic_smbalert_in_n) signal is driven low by the slave." "0,1"
newline
bitfld.long 0x0 9. "SMBUS_SUSPEND_DET,Indicates whether a SMBSUS (ic_smbsus_in_n) signal is driven low by the Host." "0,1"
newline
bitfld.long 0x0 8. "RSVD_SLV_RX_PEC_NACK,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 7. "RSVD_ARP_ASSGN_ADDR_CMD_DET,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 6. "RSVD_ARP_GET_UDID_CMD_DET,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 5. "RSVD_ARP_RST_CMD_DET,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 4. "RSVD_ARP_PREPARE_CMD_DET,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 3. "HOST_NTFY_MST_DET,Indicates whether a Notify ARP Master ARP command has been received." "0,1"
newline
bitfld.long 0x0 2. "QUICK_CMD_DET,Indicates whether a Quick command has been received on the SMBus interface regardless of" "0,1"
newline
bitfld.long 0x0 1. "MST_CLOCK_EXTND_TIMEOUT,Indicates whether the Master device transaction (START-to-ACK  ACK-to-ACK  or ACK-to-STOP)" "0,1"
newline
bitfld.long 0x0 0. "SLV_CLOCK_EXTND_TIMEOUT,Indicates whether the transaction from Slave (i.e from START to STOP) exceeds IC_SMBUS_CLOCK_LOW_SEXT time." "0,1"
wgroup.long 0xD4++0x3
line.long 0x0 "IC_CLR_SMBUS_INTR,Name: SMBus Clear Interrupt Register"
hexmask.long.tbyte 0x0 11.--31. 1. "RSVD_IC_CLR_SMBUS_INTR,Reserved bits - Read Only"
newline
bitfld.long 0x0 10. "CLR_SMBUS_ALERT_DET,Write this register bit to clear the SMBUS_ALERT_DET" "0,1"
newline
bitfld.long 0x0 9. "CLR_SMBUS_SUSPEND_DET,Write this register bit to clear the SMBUS_SUSPEND_DET" "0,1"
newline
bitfld.long 0x0 8. "RSVD_CLR_SLV_RX_PEC_NACK,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 7. "RSVD_CLR_ARP_ASSGN_ADDR_CMD_DET,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 6. "RSVD_CLR_ARP_GET_UDID_CMD_DET,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 5. "RSVD_CLR_ARP_RST_CMD_DET,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 4. "RSVD_CLR_ARP_PREPARE_CMD_DET,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 3. "CLR_HOST_NOTIFY_MST_DET,Write this register bit to clear the HOST_NOTIFY_MST_DET" "0,1"
newline
bitfld.long 0x0 2. "CLR_QUICK_CMD_DET,Write this register bit to clear the QUICK_CMD_DET" "0,1"
newline
bitfld.long 0x0 1. "CLR_MST_CLOCK_EXTND_TIMEOUT,Write this register bit to clear the MST_CLOCK_EXTND_TIMEOUT" "0,1"
newline
bitfld.long 0x0 0. "CLR_SLV_CLOCK_EXTND_TIMEOUT,Write this register bit to clear the SLV_CLOCK_EXTND_TIMEOUT" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "IC_COMP_PARAM_1,Name: Component Parameter Register 1"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_COMP_PARAM_1,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 16.--23. 1. "TX_BUFFER_DEPTH,The value of this register is derived"
newline
hexmask.long.byte 0x0 8.--15. 1. "RX_BUFFER_DEPTH,The value of this register is"
newline
bitfld.long 0x0 7. "ADD_ENCODED_PARAMS,The value of this register is derived" "0: False,1: True"
newline
bitfld.long 0x0 6. "HAS_DMA,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 5. "INTR_IO,The value of this register is" "0: Individual,1: Combined"
newline
bitfld.long 0x0 4. "HC_COUNT_VALUES,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 2.--3. "MAX_SPEED_MODE,The value of this register is" "0: Reserved,1: Standard,2: Fast,3: High"
newline
bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,The value of this register is" "0: 8 bits,1: 16 bits,2: 32 bits,3: Reserved"
line.long 0x4 "IC_COMP_VERSION,Name: I2C Component Version Register"
hexmask.long 0x4 0.--31. 1. "IC_COMP_VERSION,Specific values for this register are"
line.long 0x8 "IC_COMP_TYPE,Name: I2C Component Type Register"
hexmask.long 0x8 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number"
tree.end
tree "SDM_NAND_CSR"
base ad:0xFFA10000
group.long 0x0++0x3
line.long 0x0 "device_reset,Device reset. Controller sends a RESET command to device."
bitfld.long 0x0 3. "bank3,Issues reset to bank 3. Controller resets the bit after" "0,1"
bitfld.long 0x0 2. "bank2,Issues reset to bank 2. Controller resets the bit after" "0,1"
newline
bitfld.long 0x0 1. "bank1,Issues reset to bank 1. Controller resets the bit after" "0,1"
bitfld.long 0x0 0. "bank0,Issues reset to bank 0. Controller resets the bit after" "0,1"
group.long 0x10++0x3
line.long 0x0 "transfer_spare_reg,Default data transfer mode. (Ignored during Spare only mode)"
bitfld.long 0x0 0. "flag,On all read or write commands through Map 01  if this bit is set " "0,1"
group.long 0x20++0x3
line.long 0x0 "load_wait_cnt,Wait count value for Load operation"
hexmask.long.word 0x0 0.--15. 1. "value,Number of clock cycles after issue of load operation before"
group.long 0x30++0x3
line.long 0x0 "program_wait_cnt,Wait count value for Program operation"
hexmask.long.word 0x0 0.--15. 1. "value,Number of clock cycles after issue of program operation before"
group.long 0x40++0x3
line.long 0x0 "erase_wait_cnt,Wait count value for Erase operation"
hexmask.long.word 0x0 0.--15. 1. "value,Number of clock cycles after issue of erase operation before"
group.long 0x50++0x3
line.long 0x0 "int_mon_cyccnt,Interrupt monitor cycle count value"
hexmask.long.word 0x0 0.--15. 1. "value,In polling mode  sets the number of cycles Cadence Flash Controller"
group.long 0x60++0x3
line.long 0x0 "rb_pin_enabled,Interrupt or polling mode. Ready/Busy pin is enabled from device."
bitfld.long 0x0 3. "bank3,Sets Cadence Flash Controller in interrupt pin or polling mode" "0,1"
bitfld.long 0x0 2. "bank2,Sets Cadence Flash Controller in interrupt pin or polling mode" "0,1"
newline
bitfld.long 0x0 1. "bank1,Sets Cadence Flash Controller in interrupt pin or polling mode" "0,1"
bitfld.long 0x0 0. "bank0,Sets Cadence Flash Controller in interrupt pin or polling mode" "0,1"
group.long 0x70++0x3
line.long 0x0 "multiplane_operation,Multiplane transfer mode. Pipelined read. copyback. erase"
bitfld.long 0x0 0. "flag,[list][*]1 - Multiplane operation enabled" "0,1"
group.long 0x80++0x3
line.long 0x0 "multiplane_read_enable,Device supports multiplane read command sequence"
bitfld.long 0x0 0. "flag,Certain devices support dedicated multiplane read command sequences" "0,1"
group.long 0x90++0x3
line.long 0x0 "copyback_disable,Device does not support copyback command sequence"
bitfld.long 0x0 0. "flag,[list][*]1 - Copyback disabled [*]0 - Copyback enabled[/list]" "0,1"
group.long 0xA0++0x3
line.long 0x0 "cache_write_enable,Device supports cache write command sequence"
bitfld.long 0x0 0. "flag,[list][*]1 - Cache write supported [*]0 - Cache write not supported[/list]" "0,1"
group.long 0xB0++0x3
line.long 0x0 "cache_read_enable,Device supports cache read command sequence"
bitfld.long 0x0 0. "flag,[list][*]1 - Cache read supported [*]0 - Cache read not supported[/list]" "0,1"
group.long 0xC0++0x3
line.long 0x0 "prefetch_mode,Enables read data prefetching to faster performance"
hexmask.long.word 0x0 4.--15. 1. "prefetch_burst_length,If prefetch_en is set and prefetch_burst_length is set to ZERO  the controller will"
bitfld.long 0x0 0. "prefetch_en,Enable prefetch of Data" "0,1"
group.long 0xD0++0x3
line.long 0x0 "chip_enable_dont_care,Device can work in the chip enable dont care mode"
bitfld.long 0x0 0. "flag,Controller can interleave commands between banks when this feature is enabled." "0,1"
group.long 0xE0++0x3
line.long 0x0 "ecc_enable,Enable controller ECC check bit generation and correction"
bitfld.long 0x0 0. "flag,Enables or disables controller ECC capabilities. When enabled  controller calculates" "0,1"
group.long 0xF0++0x3
line.long 0x0 "global_int_enable,Global Interrupt enable and Error/Timeout disable."
bitfld.long 0x0 8. "error_rpt_disable,Command and ECC uncorrectable failures will not be" "0,1"
bitfld.long 0x0 4. "timeout_disable,Watchdog timer logic will be de-activated when" "0,1"
newline
bitfld.long 0x0 0. "flag,Host will receive an interrupt only when this bit is set." "0,1"
group.long 0x100++0x3
line.long 0x0 "twhr2_and_we_2_re,"
hexmask.long.byte 0x0 8.--13. 1. "twhr2,Signifies the number of controller clocks that should be introduced between"
hexmask.long.byte 0x0 0.--5. 1. "we_2_re,Signifies the number of bus interface clk_x clocks that should be introduced between"
group.long 0x110++0x3
line.long 0x0 "tcwaw_and_addr_2_data,"
hexmask.long.byte 0x0 8.--13. 1. "tcwaw,Signifies the number of controller clocks that should be introduced between"
hexmask.long.byte 0x0 0.--6. 1. "addr_2_data,Signifies the number of bus interface clk_x clocks that should be introduced"
group.long 0x120++0x3
line.long 0x0 "re_2_we,Timing parameter between re high to we low (Trhw)"
hexmask.long.byte 0x0 0.--5. 1. "value,Signifies the number of bus interface clk_x clocks that should be introduced between"
group.long 0x130++0x3
line.long 0x0 "acc_clks,Timing parameter from read enable going low to capture read data"
hexmask.long.byte 0x0 0.--3. 1. "value,Signifies the number of bus interface clk_x clock cycles  controller"
group.long 0x140++0x3
line.long 0x0 "number_of_planes,Number of planes in the device"
bitfld.long 0x0 0.--2. "value,Controller will read Electronic Signature of devices and populate" "0,1,2,3,4,5,6,7"
group.long 0x150++0x3
line.long 0x0 "pages_per_block,Number of pages in a block"
hexmask.long.word 0x0 0.--15. 1. "value,Controller will read Electronic Signature of devices and populate"
group.long 0x160++0x3
line.long 0x0 "device_width,I/O width of attached devices"
bitfld.long 0x0 0.--1. "value,Controller will read Electronic Signature of devices and populate" "0,1,2,3"
group.long 0x170++0x3
line.long 0x0 "device_main_area_size,Page main area size of device in bytes"
hexmask.long.word 0x0 0.--15. 1. "value,Controller will read Electronic Signature of devices and populate"
group.long 0x180++0x3
line.long 0x0 "device_spare_area_size,Page spare area size of device in bytes"
hexmask.long.word 0x0 0.--15. 1. "value,Controller will read Electronic Signature of devices and populate"
group.long 0x190++0x3
line.long 0x0 "two_row_addr_cycles,Attached device has only 2 ROW address cycles"
bitfld.long 0x0 4. "four,This flag must be set for devices which allow for 4 ROW address cycles instead" "0,1"
bitfld.long 0x0 0. "flag,This flag must be set for devices which allow for 2 ROW address cycles instead" "0,1"
group.long 0x1A0++0x3
line.long 0x0 "multiplane_addr_restrict,Address restriction for multiplane commands"
bitfld.long 0x0 0. "flag,This flag must be set for devices which require that during multiplane" "0,1"
group.long 0x1B0++0x3
line.long 0x0 "ecc_correction,Correction capability required and the Erase threshold value."
hexmask.long.word 0x0 16.--31. 1. "erase_threshold,This value informs the ECC logic of the number of 0's to count"
hexmask.long.byte 0x0 0.--7. 1. "value,The required correction capability. A smaller correction capability will"
group.long 0x1C0++0x3
line.long 0x0 "read_mode,The type of read sequence that the controller will follow for pipe read commands."
hexmask.long.byte 0x0 0.--3. 1. "value,The values in the field should be as follows[list]"
group.long 0x1D0++0x3
line.long 0x0 "write_mode,The type of write sequence that the controller will follow for pipe write commands."
hexmask.long.byte 0x0 0.--3. 1. "value,The values in the field should be as follows[list]"
group.long 0x1E0++0x3
line.long 0x0 "copyback_mode,The type of copyback sequence that the controller will follow."
hexmask.long.byte 0x0 0.--3. 1. "value,The values in the field should be as follows[list]"
group.long 0x1F0++0x3
line.long 0x0 "rdwr_en_lo_cnt,Read/Write Enable low pulse width"
hexmask.long.byte 0x0 0.--4. 1. "value,Number of clk_x cycles that read or write enable will kept low to meet the min"
group.long 0x200++0x3
line.long 0x0 "rdwr_en_hi_cnt,Read/Write Enable high pulse width"
hexmask.long.byte 0x0 0.--4. 1. "value,Number of clk_x cycles that read or write enable will kept high to meet the min"
group.long 0x210++0x3
line.long 0x0 "max_rd_delay,Max round trip read data delay for data capture"
hexmask.long.byte 0x0 0.--3. 1. "value,Number of clk_x cycles after generation of feedback clk_x_out pulse when it is safe"
group.long 0x220++0x3
line.long 0x0 "cs_setup_cnt,Chip select setup/tWB time"
hexmask.long.byte 0x0 12.--17. 1. "twb,Number of clk_x cycles required for meeting the tWB time. This register"
hexmask.long.byte 0x0 0.--4. 1. "value,Number of clk_x cycles required for meeting chip select setup time. This register"
group.long 0x230++0x3
line.long 0x0 "spare_area_skip_bytes,Spare area skip bytes"
hexmask.long.byte 0x0 0.--5. 1. "value,Number of bytes to skip from start of spare area before last ECC sector"
group.long 0x240++0x3
line.long 0x0 "spare_area_marker,Spare area marker value"
hexmask.long.word 0x0 0.--15. 1. "value,A 16bit value that will be written in the spare area skip bytes. This value"
group.long 0x250++0x3
line.long 0x0 "devices_connected,Number of Devices connected on one bank"
bitfld.long 0x0 0.--2. "value,Indicates the number of devices connected to a bank. At POR  the value loaded" "0,1,2,3,4,5,6,7"
group.long 0x260++0x3
line.long 0x0 "die_mask,Indicates the die differentiator in case of NAND devices with stacked dies."
hexmask.long.word 0x0 0.--15. 1. "value,The die_mask register information will be used for devices having address restrictions."
group.long 0x270++0x3
line.long 0x0 "first_block_of_next_plane,The starting block address of the next plane in a multi plane device."
hexmask.long.word 0x0 0.--15. 1. "value,This values informs the controller of the plane structure of the device."
group.long 0x280++0x3
line.long 0x0 "write_protect,This register is used to control the assertion/de-assertion of the WP# pin to the device."
bitfld.long 0x0 0. "flag,When the controller is in reset  the WP# pin is always asserted to the device. Once the" "0,1"
group.long 0x290++0x3
line.long 0x0 "re_2_re,Timing parameter between re high to re low (Trhz) for the next bank"
hexmask.long.byte 0x0 0.--5. 1. "value,Signifies the number of bus interface clk_x clocks that should be introduced between"
group.long 0x2A0++0x3
line.long 0x0 "por_reset_count,The number of cycles the controller waits after POR to issue the first RESET command"
hexmask.long.word 0x0 0.--15. 1. "value,The controller waits for this number of cycles before issuing the first"
group.long 0x2B0++0x3
line.long 0x0 "watchdog_reset_count,The number of cycles the controller waits before flagging a"
hexmask.long.word 0x0 0.--15. 1. "value,The controller waits for this number of cycles before issuing"
group.long 0x300++0x3
line.long 0x0 "manufacturer_id,"
hexmask.long.byte 0x0 0.--7. 1. "value,Manufacturer ID"
rgroup.long 0x310++0x3
line.long 0x0 "device_id,"
hexmask.long.byte 0x0 0.--7. 1. "value,Device ID"
rgroup.long 0x320++0x3
line.long 0x0 "device_param_0,"
hexmask.long.byte 0x0 0.--7. 1. "value,3rd byte relating to Device Signature. This register is"
rgroup.long 0x330++0x3
line.long 0x0 "device_param_1,"
hexmask.long.byte 0x0 0.--7. 1. "value,4th byte relating to Device Signature. This register is"
rgroup.long 0x340++0x3
line.long 0x0 "device_param_2,"
hexmask.long.byte 0x0 0.--7. 1. "value,Reserved."
rgroup.long 0x350++0x3
line.long 0x0 "logical_page_data_size,Logical page data area size in bytes"
hexmask.long.word 0x0 0.--15. 1. "value,Logical page spare area size in bytes. If multiple devices are"
rgroup.long 0x360++0x3
line.long 0x0 "logical_page_spare_size,Logical page data area size in bytes"
hexmask.long.word 0x0 0.--15. 1. "value,Logical page spare area size in bytes. If multiple devices are"
rgroup.long 0x370++0x3
line.long 0x0 "revision,Controller Revision"
hexmask.long.byte 0x0 8.--15. 1. "minor,The Minor revision number of the controller"
hexmask.long.byte 0x0 0.--7. 1. "value,The Major revision number of the controller"
rgroup.long 0x380++0x3
line.long 0x0 "onfi_device_features,Features supported by the connected ONFI device"
hexmask.long.word 0x0 0.--15. 1. "value,The values in the field should be interpreted as follows[list]"
rgroup.long 0x390++0x3
line.long 0x0 "onfi_optional_commands,Optional commands supported by the connected ONFI device"
hexmask.long.word 0x0 0.--15. 1. "value,The values in the field should be interpreted as follows[list]"
rgroup.long 0x3A0++0x3
line.long 0x0 "onfi_timing_mode,Asynchronous Timing modes supported by the connected ONFI device"
hexmask.long.byte 0x0 0.--5. 1. "value,The values in the field should be interpreted as follows[list]"
rgroup.long 0x3B0++0x3
line.long 0x0 "onfi_pgm_cache_timing_mode,Asynchronous Program Cache Timing modes supported by the connected ONFI device"
hexmask.long.byte 0x0 0.--5. 1. "value,The values in the field should be interpreted as follows[list]"
group.long 0x3C0++0x3
line.long 0x0 "onfi_device_no_of_luns,Indicates if the device is an ONFI compliant device and the number"
bitfld.long 0x0 20. "ce_reduction_volume_addr_and_change,Device supports CE pin reduction with volume assignments volume addressing" "0,1"
bitfld.long 0x0 16. "onfi_jedec_multiplane_erase_seq,Device supports ONFI JEDEC Multiplane erase sequence.(Only valid for Onfi devices)" "0,1"
newline
bitfld.long 0x0 12. "prog_page_reg_clear_enhancement,Device supports program page register clear enhancement.In such a device " "0,1"
bitfld.long 0x0 8. "onfi_device,Indicates if the device is an ONFI compliant device.[list]" "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "no_of_luns,Indicates the number of LUNS present in the device"
rgroup.long 0x3D0++0x3
line.long 0x0 "onfi_device_no_of_blocks_per_lun_l,Lower bits of number of blocks per LUN present in"
hexmask.long.word 0x0 0.--15. 1. "value,Indicates the lower bits of number of blocks per"
rgroup.long 0x3E0++0x3
line.long 0x0 "onfi_device_no_of_blocks_per_lun_u,Upper bits of number of blocks per LUN present in"
hexmask.long.word 0x0 0.--15. 1. "value,Indicates the upper bits of number of blocks per"
rgroup.long 0x3F0++0x3
line.long 0x0 "features,Shows Available hardware features or attributes"
bitfld.long 0x0 13. "lba,if set  hardware supports Toshiba LBA devices." "0,1"
bitfld.long 0x0 12. "dfi_intf,if set  hardware supports ONFI2.x synchronous interface." "0,1"
newline
bitfld.long 0x0 11. "index_addr,if set  hardware support only Indexed addressing." "0,1"
bitfld.long 0x0 10. "gpreg,if set  General purpose registers are is present in hardware." "0,1"
newline
bitfld.long 0x0 9. "xdma_sideband,if set  Side band DMA signals are present in hardware." "0,1"
bitfld.long 0x0 8. "partition,if set  Partition logic is present in hardware." "0,1"
newline
bitfld.long 0x0 7. "cmd_dma,if set  CMD-DMA is present in hardware." "0,1"
bitfld.long 0x0 6. "dma,if set  DATA-DMA is present in hardware." "0,1"
newline
bitfld.long 0x0 0.--1. "n_banks,Maximum number of banks supported by hardware. This is an" "0,1,2,3"
rgroup.long 0x400++0x3
line.long 0x0 "transfer_mode,Current data transfer mode is Main only. Spare only or Main+Spare."
bitfld.long 0x0 6.--7. "value3,[list][*]00 - Bank 3 is in Main mode [*]01 - Bank 3 is in Spare mode [*]10 - Bank 3 is in Main+Spare mode[/list]" "0,1,2,3"
bitfld.long 0x0 4.--5. "value2,[list][*]00 - Bank 2 is in Main mode [*]01 - Bank 2 is in Spare mode [*]10 - Bank 2 is in Main+Spare mode[/list]" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "value1,[list][*]00 - Bank 1 is in Main mode [*]01 - Bank 1 is in Spare mode [*]10 - Bank 1 is in Main+Spare mode[/list]" "0,1,2,3"
bitfld.long 0x0 0.--1. "value0,[list][*]00 - Bank 0 is in Main mode [*]01 - Bank 0 is in Spare mode [*]10 - Bank 0 is in Main+Spare mode[/list]" "0,1,2,3"
group.long 0x410++0x3
line.long 0x0 "intr_status0,Interrupt status register for bank 0"
eventfld.long 0x0 16. "erased_page,If an erased page is detected on reads  this bit will be set. The detection of erased" "0,1"
eventfld.long 0x0 15. "page_xfer_inc,For every page of data transfer to or from the device  this bit will be set." "0,1"
newline
eventfld.long 0x0 14. "pipe_cmd_err,A pipeline command sequence has been violated. This occurs when Map 01 page read/write" "0,1"
eventfld.long 0x0 13. "rst_comp,Controller has finished reset and initialization process" "0,1"
newline
eventfld.long 0x0 12. "int_act,R/B pin of device transitioned from low to high" "0,1"
eventfld.long 0x0 11. "unsup_cmd,An unsupported command was received. This interrupt is set when an invalid command is" "0,1"
newline
eventfld.long 0x0 10. "locked_blk,The address to program or erase operation is to a locked block and the operation failed" "0,1"
eventfld.long 0x0 9. "pipe_cpybck_cmd_comp,A pipeline command or a copyback bank command has completed on this particular bank" "0,1"
newline
eventfld.long 0x0 8. "erase_comp,Device erase operation complete" "0,1"
eventfld.long 0x0 7. "program_comp,Device finished the last issued program command." "0,1"
newline
eventfld.long 0x0 6. "load_comp,Device finished the last issued load command." "0,1"
eventfld.long 0x0 5. "erase_fail,Erase failure occurred in the device on issuance of a erase command. err_block_addr" "0,1"
newline
eventfld.long 0x0 4. "program_fail,Program failure occurred in the device on issuance of a program command. err_block_addr" "0,1"
eventfld.long 0x0 3. "time_out,Watchdog timer has triggered in the controller due to one of the reasons like device" "0,1"
newline
eventfld.long 0x0 2. "dma_cmd_comp,A data DMA command has completed on this bank" "0,1"
eventfld.long 0x0 0. "ecc_uncor_err,Ecc logic detected uncorrectable error while reading data from flash device." "0,1"
group.long 0x420++0x3
line.long 0x0 "intr_en0,Enables corresponding interrupt bit in interrupt register"
bitfld.long 0x0 16. "erased_page,If an erased page is detected on reads  this bit will be set. The detection of erased" "0,1"
bitfld.long 0x0 15. "page_xfer_inc,For every page of data transfer to or from the device  this bit will be set." "0,1"
newline
bitfld.long 0x0 14. "pipe_cmd_err,A pipeline command sequence has been violated. This occurs when Map 01 page read/write" "0,1"
bitfld.long 0x0 13. "rst_comp,A reset command has completed on this bank" "0,1"
newline
bitfld.long 0x0 12. "int_act,R/B pin of device transitioned from low to high" "0,1"
bitfld.long 0x0 11. "unsup_cmd,An unsupported command was received. This interrupt is set when an invalid command is" "0,1"
newline
bitfld.long 0x0 10. "locked_blk,The address to program or erase operation is to a locked block and the operation failed" "0,1"
bitfld.long 0x0 9. "pipe_cpybck_cmd_comp,A pipeline command or a copyback bank command has completed on this particular bank" "0,1"
newline
bitfld.long 0x0 8. "erase_comp,Device erase operation complete" "0,1"
bitfld.long 0x0 7. "program_comp,Device finished the last issued program command." "0,1"
newline
bitfld.long 0x0 6. "load_comp,Device finished the last issued load command." "0,1"
bitfld.long 0x0 5. "erase_fail,Erase failure occurred in the device on issuance of a erase command. err_block_addr" "0,1"
newline
bitfld.long 0x0 4. "program_fail,Program failure occurred in the device on issuance of a program command. err_block_addr" "0,1"
bitfld.long 0x0 3. "time_out,Watchdog timer has triggered in the controller due to one of the reasons like device" "0,1"
newline
bitfld.long 0x0 2. "dma_cmd_comp,A data DMA command has completed on this bank" "0,1"
bitfld.long 0x0 0. "ecc_uncor_err,If set  Controller will interrupt processor when Ecc logic detects uncorrectable error." "0,1"
rgroup.long 0x430++0x3
line.long 0x0 "page_cnt0,Decrementing page count bank 0"
hexmask.long.byte 0x0 0.--7. 1. "value,Maintains a decrementing count of the number of pages in"
rgroup.long 0x440++0x3
line.long 0x0 "err_page_addr0,Erred page address bank 0"
hexmask.long.word 0x0 0.--15. 1. "value,Holds the page address that resulted in a failure on program"
rgroup.long 0x450++0x3
line.long 0x0 "err_block_addr0,Erred block address bank 0"
hexmask.long.word 0x0 0.--15. 1. "value,Holds the block address that resulted in a failure on program"
group.long 0x460++0x3
line.long 0x0 "intr_status1,Interrupt status register for bank 1"
eventfld.long 0x0 16. "erased_page,If an erased page is detected on reads  this bit will be set. The detection of erased" "0,1"
eventfld.long 0x0 15. "page_xfer_inc,For every page of data transfer to or from the device  this bit will be set." "0,1"
newline
eventfld.long 0x0 14. "pipe_cmd_err,A pipeline command sequence has been violated. This occurs when Map 01 page read/write" "0,1"
eventfld.long 0x0 13. "rst_comp,The Cadence NAND Flash Memory Controller has completed its reset and initialization process" "0,1"
newline
eventfld.long 0x0 12. "int_act,R/B pin of device transitioned from low to high" "0,1"
eventfld.long 0x0 11. "unsup_cmd,An unsupported command was received. This interrupt is set when an invalid command is" "0,1"
newline
eventfld.long 0x0 10. "locked_blk,The address to program or erase operation is to a locked block and the operation failed" "0,1"
eventfld.long 0x0 9. "pipe_cpybck_cmd_comp,A pipeline command or a copyback bank command has completed on this particular bank" "0,1"
newline
eventfld.long 0x0 8. "erase_comp,Device erase operation complete" "0,1"
eventfld.long 0x0 7. "program_comp,Device finished the last issued program command." "0,1"
newline
eventfld.long 0x0 6. "load_comp,Device finished the last issued load command." "0,1"
eventfld.long 0x0 5. "erase_fail,Erase failure occurred in the device on issuance of a erase command. err_block_addr" "0,1"
newline
eventfld.long 0x0 4. "program_fail,Program failure occurred in the device on issuance of a program command. err_block_addr" "0,1"
eventfld.long 0x0 3. "time_out,Watchdog timer has triggered in the controller due to one of the reasons like device" "0,1"
newline
eventfld.long 0x0 2. "dma_cmd_comp,A data DMA command has completed on this bank" "0,1"
eventfld.long 0x0 0. "ecc_uncor_err,Ecc logic detected uncorrectable error while reading data from flash device." "0,1"
group.long 0x470++0x3
line.long 0x0 "intr_en1,Enables corresponding interrupt bit in interrupt register"
bitfld.long 0x0 16. "erased_page,If an erased page is detected on reads  this bit will be set. The detection of erased" "0,1"
bitfld.long 0x0 15. "page_xfer_inc,For every page of data transfer to or from the device  this bit will be set." "0,1"
newline
bitfld.long 0x0 14. "pipe_cmd_err,A pipeline command sequence has been violated. This occurs when Map 01 page read/write" "0,1"
bitfld.long 0x0 13. "rst_comp,A reset command has completed on this bank" "0,1"
newline
bitfld.long 0x0 12. "int_act,R/B pin of device transitioned from low to high" "0,1"
bitfld.long 0x0 11. "unsup_cmd,An unsupported command was received. This interrupt is set when an invalid command is" "0,1"
newline
bitfld.long 0x0 10. "locked_blk,The address to program or erase operation is to a locked block and the operation failed" "0,1"
bitfld.long 0x0 9. "pipe_cpybck_cmd_comp,A pipeline command or a copyback bank command has completed on this particular bank" "0,1"
newline
bitfld.long 0x0 8. "erase_comp,Device erase operation complete" "0,1"
bitfld.long 0x0 7. "program_comp,Device finished the last issued program command." "0,1"
newline
bitfld.long 0x0 6. "load_comp,Device finished the last issued load command." "0,1"
bitfld.long 0x0 5. "erase_fail,Erase failure occurred in the device on issuance of a erase command. err_block_addr" "0,1"
newline
bitfld.long 0x0 4. "program_fail,Program failure occurred in the device on issuance of a program command. err_block_addr" "0,1"
bitfld.long 0x0 3. "time_out,Watchdog timer has triggered in the controller due to one of the reasons like device" "0,1"
newline
bitfld.long 0x0 2. "dma_cmd_comp,A data DMA command has completed on this bank" "0,1"
bitfld.long 0x0 0. "ecc_uncor_err,If set  Controller will interrupt processor when Ecc logic detects uncorrectable error." "0,1"
rgroup.long 0x480++0x3
line.long 0x0 "page_cnt1,Decrementing page count bank 1"
hexmask.long.byte 0x0 0.--7. 1. "value,Maintains a decrementing count of the number of pages in"
rgroup.long 0x490++0x3
line.long 0x0 "err_page_addr1,Erred page address bank 1"
hexmask.long.word 0x0 0.--15. 1. "value,Holds the page address that resulted in a failure on program"
rgroup.long 0x4A0++0x3
line.long 0x0 "err_block_addr1,Erred block address bank 1"
hexmask.long.word 0x0 0.--15. 1. "value,Holds the block address that resulted in a failure on program"
group.long 0x4B0++0x3
line.long 0x0 "intr_status2,Interrupt status register for bank 2"
eventfld.long 0x0 16. "erased_page,If an erased page is detected on reads  this bit will be set. The detection of erased" "0,1"
eventfld.long 0x0 15. "page_xfer_inc,For every page of data transfer to or from the device  this bit will be set." "0,1"
newline
eventfld.long 0x0 14. "pipe_cmd_err,A pipeline command sequence has been violated. This occurs when Map 01 page read/write" "0,1"
eventfld.long 0x0 13. "rst_comp,The Cadence NAND Flash Memory Controller has completed its reset and initialization process" "0,1"
newline
eventfld.long 0x0 12. "int_act,R/B pin of device transitioned from low to high" "0,1"
eventfld.long 0x0 11. "unsup_cmd,An unsupported command was received. This interrupt is set when an invalid command is" "0,1"
newline
eventfld.long 0x0 10. "locked_blk,The address to program or erase operation is to a locked block and the operation failed" "0,1"
eventfld.long 0x0 9. "pipe_cpybck_cmd_comp,A pipeline command or a copyback bank command has completed on this particular bank" "0,1"
newline
eventfld.long 0x0 8. "erase_comp,Device erase operation complete" "0,1"
eventfld.long 0x0 7. "program_comp,Device finished the last issued program command." "0,1"
newline
eventfld.long 0x0 6. "load_comp,Device finished the last issued load command." "0,1"
eventfld.long 0x0 5. "erase_fail,Erase failure occurred in the device on issuance of a erase command. err_block_addr" "0,1"
newline
eventfld.long 0x0 4. "program_fail,Program failure occurred in the device on issuance of a program command. err_block_addr" "0,1"
eventfld.long 0x0 3. "time_out,Watchdog timer has triggered in the controller due to one of the reasons like device" "0,1"
newline
eventfld.long 0x0 2. "dma_cmd_comp,A data DMA command has completed on this bank" "0,1"
eventfld.long 0x0 0. "ecc_uncor_err,Ecc logic detected uncorrectable error while reading data from flash device." "0,1"
group.long 0x4C0++0x3
line.long 0x0 "intr_en2,Enables corresponding interrupt bit in interrupt register"
bitfld.long 0x0 16. "erased_page,If an erased page is detected on reads  this bit will be set. The detection of erased" "0,1"
bitfld.long 0x0 15. "page_xfer_inc,For every page of data transfer to or from the device  this bit will be set." "0,1"
newline
bitfld.long 0x0 14. "pipe_cmd_err,A pipeline command sequence has been violated. This occurs when Map 01 page read/write" "0,1"
bitfld.long 0x0 13. "rst_comp,A reset command has completed on this bank" "0,1"
newline
bitfld.long 0x0 12. "int_act,R/B pin of device transitioned from low to high" "0,1"
bitfld.long 0x0 11. "unsup_cmd,An unsupported command was received. This interrupt is set when an invalid command is" "0,1"
newline
bitfld.long 0x0 10. "locked_blk,The address to program or erase operation is to a locked block and the operation failed" "0,1"
bitfld.long 0x0 9. "pipe_cpybck_cmd_comp,A pipeline command or a copyback bank command has completed on this particular bank" "0,1"
newline
bitfld.long 0x0 8. "erase_comp,Device erase operation complete" "0,1"
bitfld.long 0x0 7. "program_comp,Device finished the last issued program command." "0,1"
newline
bitfld.long 0x0 6. "load_comp,Device finished the last issued load command." "0,1"
bitfld.long 0x0 5. "erase_fail,Erase failure occurred in the device on issuance of a erase command. err_block_addr" "0,1"
newline
bitfld.long 0x0 4. "program_fail,Program failure occurred in the device on issuance of a program command. err_block_addr" "0,1"
bitfld.long 0x0 3. "time_out,Watchdog timer has triggered in the controller due to one of the reasons like device" "0,1"
newline
bitfld.long 0x0 2. "dma_cmd_comp,A data DMA command has completed on this bank" "0,1"
bitfld.long 0x0 0. "ecc_uncor_err,If set  Controller will interrupt processor when Ecc logic detects uncorrectable error." "0,1"
rgroup.long 0x4D0++0x3
line.long 0x0 "page_cnt2,Decrementing page count bank 2"
hexmask.long.byte 0x0 0.--7. 1. "value,Maintains a decrementing count of the number of pages in"
rgroup.long 0x4E0++0x3
line.long 0x0 "err_page_addr2,Erred page address bank 2"
hexmask.long.word 0x0 0.--15. 1. "value,Holds the page address that resulted in a failure on program"
rgroup.long 0x4F0++0x3
line.long 0x0 "err_block_addr2,Erred block address bank 2"
hexmask.long.word 0x0 0.--15. 1. "value,Holds the block address that resulted in a failure on program"
group.long 0x500++0x3
line.long 0x0 "intr_status3,Interrupt status register for bank 3"
eventfld.long 0x0 16. "erased_page,If an erased page is detected on reads  this bit will be set. The detection of erased" "0,1"
eventfld.long 0x0 15. "page_xfer_inc,For every page of data transfer to or from the device  this bit will be set." "0,1"
newline
eventfld.long 0x0 14. "pipe_cmd_err,A pipeline command sequence has been violated. This occurs when Map 01 page read/write" "0,1"
eventfld.long 0x0 13. "rst_comp,The Cadence NAND Flash Memory Controller has completed its reset and initialization process" "0,1"
newline
eventfld.long 0x0 12. "int_act,R/B pin of device transitioned from low to high" "0,1"
eventfld.long 0x0 11. "unsup_cmd,An unsupported command was received. This interrupt is set when an invalid command is" "0,1"
newline
eventfld.long 0x0 10. "locked_blk,The address to program or erase operation is to a locked block and the operation failed" "0,1"
eventfld.long 0x0 9. "pipe_cpybck_cmd_comp,A pipeline command or a copyback bank command has completed on this particular bank" "0,1"
newline
eventfld.long 0x0 8. "erase_comp,Device erase operation complete" "0,1"
eventfld.long 0x0 7. "program_comp,Device finished the last issued program command." "0,1"
newline
eventfld.long 0x0 6. "load_comp,Device finished the last issued load command." "0,1"
eventfld.long 0x0 5. "erase_fail,Erase failure occurred in the device on issuance of a erase command. err_block_addr" "0,1"
newline
eventfld.long 0x0 4. "program_fail,Program failure occurred in the device on issuance of a program command. err_block_addr" "0,1"
eventfld.long 0x0 3. "time_out,Watchdog timer has triggered in the controller due to one of the reasons like device" "0,1"
newline
eventfld.long 0x0 2. "dma_cmd_comp,A data DMA command has completed on this bank" "0,1"
eventfld.long 0x0 0. "ecc_uncor_err,Ecc logic detected uncorrectable error while reading data from flash device." "0,1"
group.long 0x510++0x3
line.long 0x0 "intr_en3,Enables corresponding interrupt bit in interrupt register"
bitfld.long 0x0 16. "erased_page,If an erased page is detected on reads  this bit will be set. The detection of erased" "0,1"
bitfld.long 0x0 15. "page_xfer_inc,For every page of data transfer to or from the device  this bit will be set." "0,1"
newline
bitfld.long 0x0 14. "pipe_cmd_err,A pipeline command sequence has been violated. This occurs when Map 01 page read/write" "0,1"
bitfld.long 0x0 13. "rst_comp,A reset command has completed on this bank" "0,1"
newline
bitfld.long 0x0 12. "int_act,R/B pin of device transitioned from low to high" "0,1"
bitfld.long 0x0 11. "unsup_cmd,An unsupported command was received. This interrupt is set when an invalid command is" "0,1"
newline
bitfld.long 0x0 10. "locked_blk,The address to program or erase operation is to a locked block and the operation failed" "0,1"
bitfld.long 0x0 9. "pipe_cpybck_cmd_comp,A pipeline command or a copyback bank command has completed on this particular bank" "0,1"
newline
bitfld.long 0x0 8. "erase_comp,Device erase operation complete" "0,1"
bitfld.long 0x0 7. "program_comp,Device finished the last issued program command." "0,1"
newline
bitfld.long 0x0 6. "load_comp,Device finished the last issued load command." "0,1"
bitfld.long 0x0 5. "erase_fail,Erase failure occurred in the device on issuance of a erase command. err_block_addr" "0,1"
newline
bitfld.long 0x0 4. "program_fail,Program failure occurred in the device on issuance of a program command. err_block_addr" "0,1"
bitfld.long 0x0 3. "time_out,Watchdog timer has triggered in the controller due to one of the reasons like device" "0,1"
newline
bitfld.long 0x0 2. "dma_cmd_comp,A data DMA command has completed on this bank" "0,1"
bitfld.long 0x0 0. "ecc_uncor_err,If set  Controller will interrupt processor when Ecc logic detects uncorrectable error." "0,1"
rgroup.long 0x520++0x3
line.long 0x0 "page_cnt3,Decrementing page count bank 3"
hexmask.long.byte 0x0 0.--7. 1. "value,Maintains a decrementing count of the number of pages in"
rgroup.long 0x530++0x3
line.long 0x0 "err_page_addr3,Erred page address bank 3"
hexmask.long.word 0x0 0.--15. 1. "value,Holds the page address that resulted in a failure on program"
rgroup.long 0x540++0x3
line.long 0x0 "err_block_addr3,Erred block address bank 3"
hexmask.long.word 0x0 0.--15. 1. "value,Holds the block address that resulted in a failure on program"
rgroup.long 0x650++0x3
line.long 0x0 "ecccorinfo_b01,ECC Error correction Information register. Controller updates this register when it completes"
bitfld.long 0x0 15. "uncor_err_b1,Uncorrectable error occurred while reading pages for last transaction in Bank1. Uncorrectable" "0,1"
hexmask.long.byte 0x0 8.--14. 1. "max_errors_b1,Maximum of number of errors corrected per sector in Bank1. This field is not valid for"
newline
bitfld.long 0x0 7. "uncor_err_b0,Uncorrectable error occurred while reading pages for last transaction in Bank0. Uncorrectable" "0,1"
hexmask.long.byte 0x0 0.--6. 1. "max_errors_b0,Maximum of number of errors corrected per sector in Bank0. This field is not valid for"
rgroup.long 0x660++0x3
line.long 0x0 "ecccorinfo_b23,ECC Error correction Information register. Controller updates this register when it completes"
bitfld.long 0x0 15. "uncor_err_b3,Uncorrectable error occurred while reading pages for last transaction in Bank3. Uncorrectable" "0,1"
hexmask.long.byte 0x0 8.--14. 1. "max_errors_b3,Maximum of number of errors corrected per sector in Bank3. This field is not valid for"
newline
bitfld.long 0x0 7. "uncor_err_b2,Uncorrectable error occurred while reading pages for last transaction in Bank2. Uncorrectable" "0,1"
hexmask.long.byte 0x0 0.--6. 1. "max_errors_b2,Maximum of number of errors corrected per sector in Bank2. This field is not valid for"
group.long 0x700++0x3
line.long 0x0 "dma_enable,"
bitfld.long 0x0 0. "flag,Enables data DMA operation in the controller" "0,1"
group.long 0x720++0x3
line.long 0x0 "dma_intr,DMA interrupt register"
eventfld.long 0x0 6. "cmddma_idle,Command DMA became IDLE after completing all descriptors" "0,1"
eventfld.long 0x0 4. "desc_comp_channel3,Indicates CMD-DMA channel 3 descriptor execution done (updated when interrupt bit in cmd flags set)." "0,1"
newline
eventfld.long 0x0 3. "desc_comp_channel2,Indicates CMD-DMA channel 2 descriptor execution done (updated when interrupt bit in cmd flags set)." "0,1"
eventfld.long 0x0 2. "desc_comp_channel1,Indicates CMD-DMA channel 1 descriptor execution done (updated when interrupt bit in cmd flags set)." "0,1"
newline
eventfld.long 0x0 1. "desc_comp_channel0,Indicates CMD-DMA channel 0 descriptor execution done (updated when interrupt bit in cmd flags set)." "0,1"
eventfld.long 0x0 0. "target_error,Controller initiator interface received an ERROR target response for a transaction." "0,1"
group.long 0x730++0x3
line.long 0x0 "dma_intr_en,Enables corresponding interrupt bit in dma interrupt register"
bitfld.long 0x0 6. "cmddma_idle,Interrupt processor when command DMA becomes IDLE after completing all" "0,1"
bitfld.long 0x0 4. "desc_comp_channel3,Enable bit to indicates CMD-DMA channel 3 descriptor execution done (updated when interrupt bit in cmd flags set)." "0,1"
newline
bitfld.long 0x0 3. "desc_comp_channel2,Enable bit to indicates CMD-DMA channel 2 descriptor execution done (updated when interrupt bit in cmd flags set)." "0,1"
bitfld.long 0x0 2. "desc_comp_channel1,Enable bit to indicates CMD-DMA channel 1 descriptor execution done (updated when interrupt bit in cmd flags set)." "0,1"
newline
bitfld.long 0x0 1. "desc_comp_channel0,Enable bit to indicates CMD-DMA channel 0 descriptor execution done (updated when interrupt bit in cmd flags set)." "0,1"
bitfld.long 0x0 0. "target_error,Controller initiator interface received an ERROR target response for a transaction." "0,1"
rgroup.long 0x740++0x3
line.long 0x0 "target_err_addr_lo,Transaction address for which controller initiator interface received an ERROR target response."
hexmask.long.word 0x0 0.--15. 1. "value,Least significant 16 bits"
rgroup.long 0x750++0x3
line.long 0x0 "target_err_addr_hi,Transaction address for which controller initiator interface received an ERROR target response."
hexmask.long.word 0x0 0.--15. 1. "value,Most significant 16 bits"
rgroup.long 0x760++0x3
line.long 0x0 "chnl_active,Indicates CMD-DMA channel activity status"
bitfld.long 0x0 3. "channel3,CMD-DMA channel 3 is active" "0,1"
bitfld.long 0x0 2. "channel2,CMD-DMA channel 2 is active" "0,1"
newline
bitfld.long 0x0 1. "channel1,CMD-DMA channel 1 is active" "0,1"
bitfld.long 0x0 0. "channel0,CMD-DMA channel 0 is active" "0,1"
group.long 0x770++0x3
line.long 0x0 "flash_burst_length,"
hexmask.long.tbyte 0x0 8.--31. 1. "polling_sync_counter_value,Number of cycles CMDDMA channel has to wait before polling the SYNC Pointer again."
bitfld.long 0x0 4. "continous_burst,When this bit is set  the Data DMA will burst the entire page from/to the" "0,1"
newline
bitfld.long 0x0 0.--1. "value,Sets the burst used by data dma for transferring data to/from flash device." "0,1,2,3"
group.long 0x780++0x3
line.long 0x0 "chip_interleave_enable_and_allow_int_reads,"
bitfld.long 0x0 8. "cmd_dma_error_enable,This bit informs the CDMA channels to stop working on any new MAP10 Command DMAcommands from the host after encountering an" "0,1"
bitfld.long 0x0 4. "allow_int_reads_within_luns,This bit informs the controller to enable or disable simultaneous read accesses" "0,1"
newline
bitfld.long 0x0 0. "chip_interleave_enable,This bit informs the controller to enable or disable interleaving" "0,1"
group.long 0x790++0x3
line.long 0x0 "rescan_buffer_flag,Rescan buffer flag."
hexmask.long.byte 0x0 0.--3. 1. "flag,This register can be used to force rescan of buffer flags in any of the cmd-dma channels."
group.long 0x7A0++0x3
line.long 0x0 "no_of_blocks_per_lun,"
bitfld.long 0x0 28. "issue_read_before_sync,Issue LOAD cmd to flash core even if SYNC condition is not satisfied. But the data is read" "0,1"
bitfld.long 0x0 24. "update_sync_before_prog_comp,Update SYNC Pointer after the data is written to flash and dont wait for program" "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "value,Indicates the first block of next LUN. This information is used for extracting the target LUN during LUN interleaving."
group.long 0x7B0++0x3
line.long 0x0 "lun_status_cmd,Indicates the command to be sent while checking status of the next LUN."
hexmask.long.word 0x0 0.--15. 1. "value,[list][*]7:0 - Indicates the command to check the"
group.long 0x7C0++0x3
line.long 0x0 "cmd_dma_channel_error,Bits indicating CMD-DMA channel receiving an error condition. To get more information on the error. s/w needs to read the status field of the descriptor."
eventfld.long 0x0 3. "channel3,CMD-DMA channel 3 received an error." "0,1"
eventfld.long 0x0 2. "channel2,CMD-DMA channel 2 received an error." "0,1"
newline
eventfld.long 0x0 1. "channel1,CMD-DMA channel 1 received an error." "0,1"
eventfld.long 0x0 0. "channel0,CMD-DMA channel 0 received an error." "0,1"
group.long 0x7D0++0x3
line.long 0x0 "cmd_dma_channel_error_en,Enable bits indicating CMD-DMA channel receiving an error condition. To get more information on the error. s/w needs to read the status field of the descriptor."
bitfld.long 0x0 3. "channel3,enable bit for CMD-DMA channel 3 receiving an error" "0,1"
bitfld.long 0x0 2. "channel2,enable bit for CMD-DMA channel 2 receiving an error" "0,1"
newline
bitfld.long 0x0 1. "channel1,enable bit for CMD-DMA channel 1 receiving an error" "0,1"
bitfld.long 0x0 0. "channel0,enable bit for CMD-DMA channel 0 receiving an error" "0,1"
tree.end
tree "SDM_NANDECC"
base ad:0xFFA21800
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "SDM_NANDREADECC"
base ad:0xFFA21000
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "SDM_NANDWRITEECC"
base ad:0xFFA20800
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "SDM_QSPIECC"
base ad:0xFFA22000
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev#"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
newline
hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
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hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
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hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
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hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
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eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
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eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
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eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
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eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
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eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
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eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
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eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
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eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
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eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
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hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
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eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
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hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "SDM_QSPIREGS"
base ad:0xFF8D2000
group.long 0x0++0x2B
line.long 0x0 "cfg,"
rbitfld.long 0x0 31. "idle,This is a STATUS read-only bit. Note this is a retimed signal  so there will be some inherent delay on the generation of this status signal." "0,1"
newline
hexmask.long.byte 0x0 23.--30. 1. "config_resv2_fld,"
newline
hexmask.long.byte 0x0 19.--22. 1. "bauddiv,SPI baud rae = (master reference clock) baud_rate_divisor"
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bitfld.long 0x0 18. "enterxipimm,Value=0 : If XIP is enabled  then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : Operate the device in XIP mode immediately Use this register when the external device wakes up in XIP mode (as.." "0: If XIP is enabled,1: Operate the device in XIP mode immediately Use.."
newline
bitfld.long 0x0 17. "enterxipnextrd,Value=0 : If XIP is enabled  then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : If XIP is disabled  then setting to ?1? will inform the controller that the device is ready to enter XIP on.." "0: If XIP is enabled,1: If XIP is disabled"
newline
bitfld.long 0x0 16. "enahbremap,(Direct Access Mode Only) When set to 1  the incoming AHB address will be adapted and sent to the FLASH device as (address + N)  where N is the value stored in the remap address register." "0,1"
newline
bitfld.long 0x0 15. "endma,Set to 1 to enable the DMA handshaking logic. When enabled the QSPI will trigger DMA transfer requests via the DMA peripheral interface. Set to 0 to disable" "0,1"
newline
bitfld.long 0x0 14. "wp,Set to drive the Write Protect pin of the FLASH device. This is resynchronized to the generated memory clock as necessary." "0,1"
newline
hexmask.long.byte 0x0 10.--13. 1. "percslines,Peripheral chip select lines If pdec = 0  ss[3:0] are output thus: ss[3:0] n_ss_out[3:0] xxx0 1110 xx01 1101 x011 1011 0111 0111 1111 1111 (no peripheral selected) else ss[3:0] directly drives n_ss_out[3:0]"
newline
bitfld.long 0x0 9. "perseldec,0 : only 1 of 4 selects n_ss_out[3:0] is active 1 : allow external 4-to-16 decode (n_ss_out = ss)" "0: only 1 of 4 selects n_ss_out[3:0] is active,1: allow external 4-to-16 decode"
newline
bitfld.long 0x0 8. "enlegacyip,0 : Use Direct Access Controller/Indirect Access Controller 1 : legacy Mode is enabled. In this mode  any write to the controller via the AHB interface is serialized and sent to the FLASH device. Any valid AHB read will pop the internal.." "0: Use Direct Access Controller/Indirect Access..,1: legacy Mode is enabled"
newline
bitfld.long 0x0 7. "endiracc,0 : disable the Direct Access Controller once current transfer of the data word (FF_W) is complete. 1 : enable the Direct Access Controller When the Direct Access Controller and Indirect Access Controller are both disabled  all AHB requested are.." "0: disable the Direct Access Controller once..,1: enable the Direct Access Controller When the.."
newline
hexmask.long.byte 0x0 3.--6. 1. "config_resv1_fld,"
newline
bitfld.long 0x0 2. "selclkphase,Selects whether the clock is in an active or inactive phase outside the SPI word. 0 : the SPI clock is active outside the word 1 : the SPI clock is inactive outside the word" "0: the SPI clock is active outside the word,1: the SPI clock is inactive outside the word"
newline
bitfld.long 0x0 1. "selclkpol,0 : the SPI clock is quiescent low 1 : the SPI clock is quiescent high" "0: the SPI clock is quiescent low,1: the SPI clock is quiescent high"
newline
bitfld.long 0x0 0. "en,0 : disable the QSPI once current transfer of the data word (FF_W) is complete. 1 : enable the QSPI When spi_enable = 0  all output enables are inactive and all pins are set to input mode." "0: disable the QSPI once current transfer of the..,1: enable the QSPI When spi_enable = 0"
line.long 0x4 "devrd,"
rbitfld.long 0x4 29.--31. "rd_instr_resv5_fld," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 24.--28. 1. "dummyrdclks,Number of dummy clock cycles required by device for read instruction."
newline
rbitfld.long 0x4 21.--23. "rd_instr_resv4_fld," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 20. "enmodebits,Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1"
newline
rbitfld.long 0x4 18.--19. "rd_instr_resv3_fld," "0,1,2,3"
newline
bitfld.long 0x4 16.--17. "datawidth,0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers  DQ0 and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output.." "0: SIO mode data is shifted to the device on DQ0..,1: Used for Dual Input/Output instructions,2: Used for Quad Input/Output instructions,?"
newline
rbitfld.long 0x4 14.--15. "rd_instr_resv2_fld," "0,1,2,3"
newline
bitfld.long 0x4 12.--13. "addrwidth,0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0  DQ1  DQ2 and DQ3" "0: Addresses can be shifted to the device on DQ0 only,1: Addresses can be shifted to the device on DQ0..,2: Addresses can be shifted to the device on DQ0,?"
newline
rbitfld.long 0x4 10.--11. "rd_instr_resv1_fld," "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "instwidth,0 : Use Standard SPI mode (instruction always shifted into the device on DQ0 only) 1 : Use DIO-SPI mode (Instructions  Address and Data always sent on DQ0 and DQ1) 2 : Use QIO-SPI mode (Instructions  Address and Data always sent on DQ0  DQ1 .." "0: Use Standard SPI mode,1: Use DIO-SPI mode,2: Use QIO-SPI mode,?"
newline
hexmask.long.byte 0x4 0.--7. 1. "rdopcode,Read Opcode to use when not in XIP mode"
line.long 0x8 "devwr,"
rbitfld.long 0x8 29.--31. "wr_instr_resv4_fld," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--28. 1. "dummywrclks,Number of dummy clock cycles required by device for write instruction."
newline
hexmask.long.byte 0x8 18.--23. 1. "wr_instr_resv3_fld,"
newline
bitfld.long 0x8 16.--17. "datawidth,0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers  DQ0 and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output.." "0: SIO mode data is shifted to the device on DQ0..,1: Used for Dual Input/Output instructions,2: Used for Quad Input/Output instructions,?"
newline
rbitfld.long 0x8 14.--15. "wr_instr_resv2_fld," "0,1,2,3"
newline
bitfld.long 0x8 12.--13. "addrwidth,0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0  DQ1  DQ2 and DQ3" "0: Addresses can be shifted to the device on DQ0 only,1: Addresses can be shifted to the device on DQ0..,2: Addresses can be shifted to the device on DQ0,?"
newline
hexmask.long.byte 0x8 8.--11. 1. "wr_instr_resv1_fld,"
newline
hexmask.long.byte 0x8 0.--7. 1. "wropcode,Write Opcode"
line.long 0xC "delay,This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the SPI REFERENCE CLOCK/ext_clk. defined in this table as SPI master ref clock."
hexmask.long.byte 0xC 24.--31. 1. "nss,Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never re-asserted within an SCLK period."
newline
hexmask.long.byte 0xC 16.--23. 1. "btwn,Delay in master reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different slaves and requires the transmit FIFO to be empty."
newline
hexmask.long.byte 0xC 8.--15. 1. "after,Delay in master reference clocks between last bit of current transaction and deasserting the device chip select (n_ss_out). By default  the chip select will be deasserted on the cycle following the completion of the current transaction."
newline
hexmask.long.byte 0xC 0.--7. 1. "init,Delay in master reference clocks between setting n_ss_out low and first bit transfer."
line.long 0x10 "rddatacap,"
hexmask.long 0x10 5.--31. 1. "rd_data_resv_fld,"
newline
hexmask.long.byte 0x10 1.--4. 1. "delay,Delay the read data capturing logic by the programmed number of ref_clk cycles"
newline
bitfld.long 0x10 0. "byp,Bypass the adapted loopback clock circuit" "0,1"
line.long 0x14 "devsz,"
hexmask.long.word 0x14 21.--31. 1. "dev_size_resv_fld,"
newline
hexmask.long.byte 0x14 16.--20. 1. "bytespersubsector,Number of bytes per Block. This is required by the controller for performing the write protection logic. The number of bytes per block must be a power of 2 number."
newline
hexmask.long.word 0x14 4.--15. 1. "bytesperdevicepage,Number of bytes per device page. This is required by the controller for performing FLASH writes up to and across page boundaries."
newline
hexmask.long.byte 0x14 0.--3. 1. "numaddrbytes,Number of address bytes. A value of 0 indicates 1 byte."
line.long 0x18 "srampart,"
hexmask.long.tbyte 0x18 10.--31. 1. "resv_fld,"
newline
hexmask.long.word 0x18 0.--9. 1. "addr,Defines the size of the indirect read partition in the SRAM  in units of SRAM locations. By default  half of the SRAM is reserved for indirect read operation  and half for indirect write. The size of this register will scale with the depth of the.."
line.long 0x1C "indaddrtrig,"
hexmask.long 0x1C 0.--31. 1. "addr,This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address + 15  then the AHB request will be completed by fetching data.."
line.long 0x20 "dmaper,"
hexmask.long.tbyte 0x20 12.--31. 1. "dma_periph_resv2_fld,"
newline
hexmask.long.byte 0x20 8.--11. 1. "numburstreqbytes,Number of bytes in a burst type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual number of bytes used is.."
newline
hexmask.long.byte 0x20 4.--7. 1. "dma_periph_resv1_fld,"
newline
hexmask.long.byte 0x20 0.--3. 1. "numsglreqbytes,Number of bytes in a single type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual number of bytes used is.."
line.long 0x24 "remapaddr,"
hexmask.long 0x24 0.--31. 1. "value,This register is used to remap an incoming AHB address to a different address used by the FLASH device."
line.long 0x28 "modebit,"
hexmask.long.tbyte 0x28 8.--31. 1. "mode_resv_fld,"
newline
hexmask.long.byte 0x28 0.--7. 1. "mode,These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled."
rgroup.long 0x2C++0x3
line.long 0x0 "sramfill,"
hexmask.long.word 0x0 16.--31. 1. "indwrpart,Identifies the current fill level of the SRAM Indirect Write partition"
newline
hexmask.long.word 0x0 0.--15. 1. "indrdpart,Identifies the current fill level of the SRAM Indirect Read partition"
group.long 0x30++0x7
line.long 0x0 "txthresh,"
hexmask.long 0x0 4.--31. 1. "tx_thresh_resv_fld,"
newline
hexmask.long.byte 0x0 0.--3. 1. "level,Defines the level at which the small TX FIFO not full interrupt is generated"
line.long 0x4 "rxthresh,Device Instruction Configuration Register"
hexmask.long 0x4 4.--31. 1. "rx_thresh_resv_fld,"
newline
hexmask.long.byte 0x4 0.--3. 1. "level,Defines the level at which the small RX FIFO not empty interrupt is generated"
group.long 0x40++0x7
line.long 0x0 "irqstat,The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of these bit fields are set. the interrupt output is asserted high. The fields are each cleared by writing a 1.."
hexmask.long.tbyte 0x0 13.--31. 1. "irq_stat_resv_fld,"
newline
eventfld.long 0x0 12. "indsramfull,Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation" "0,1"
newline
eventfld.long 0x0 11. "rxfull,Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full" "0: FIFO is not full,1: FIFO is full"
newline
eventfld.long 0x0 10. "rxthreshcmp,Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has less than RX THRESHOLD entries  1 : FIFO has >= THRESHOLD entries" "0: FIFO has less than RX THRESHOLD entries,1: FIFO has >= THRESHOLD entries"
newline
eventfld.long 0x0 9. "txfull,Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full  1 : FIFO is full" "0: FIFO is not full,1: FIFO is full"
newline
eventfld.long 0x0 8. "txthreshcmp,Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has >= THRESHOLD entries  1 : FIFO has less than THRESHOLD entries" "0: FIFO has >= THRESHOLD entries,1: FIFO has less than THRESHOLD entries"
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eventfld.long 0x0 7. "rxover,This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX FIFO occurs coincident with a.." "0: no overflow has been detected,1: an overflow has occurred"
newline
eventfld.long 0x0 6. "indxfrlvl,Indirect Transfer Watermark Level Breached" "0,1"
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eventfld.long 0x0 5. "illegalacc,Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger." "0,1"
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eventfld.long 0x0 4. "protwrattempt,Write to protected area was attempted and rejected." "0,1"
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eventfld.long 0x0 3. "indrdreject,Indirect operation was requested but could not be accepted. Two indirect operations already in storage." "0,1"
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eventfld.long 0x0 2. "indopdone,Controller has completed last triggered indirect operation" "0,1"
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eventfld.long 0x0 1. "underflowdet,0 : no underflow has been detected 1 : underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with the requested write.." "0: no underflow has been detected,1: underflow is detected and an attempt to transfer.."
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eventfld.long 0x0 0. "mode_m_fail_fld,Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI mode. Set =1 if n_ss_in is low in master mode (multi-master contention). These conditions will clear the spi_enable bit and disable the SPI. This bit is.." "0: no mode fault has been detected,1: a mode fault has occurred"
line.long 0x4 "irqmask,0 : the interrupt for the corresponding interrupt status register bit is disabled. 1 : the interrupt for the corresponding interrupt status register bit is enabled."
hexmask.long.tbyte 0x4 13.--31. 1. "irq_mask_resv_fld,"
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bitfld.long 0x4 12. "indsramfull," "0,1"
newline
bitfld.long 0x4 11. "rxfull," "0,1"
newline
bitfld.long 0x4 10. "rxthreshcmp," "0,1"
newline
bitfld.long 0x4 9. "txfull," "0,1"
newline
bitfld.long 0x4 8. "txthreshcmp," "0,1"
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bitfld.long 0x4 7. "rxover," "0,1"
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bitfld.long 0x4 6. "indxfrlvl," "0,1"
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bitfld.long 0x4 5. "illegalacc," "0,1"
newline
bitfld.long 0x4 4. "protwrattempt," "0,1"
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bitfld.long 0x4 3. "indrdreject," "0,1"
newline
bitfld.long 0x4 2. "indopdone," "0,1"
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bitfld.long 0x4 1. "underflowdet," "0,1"
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bitfld.long 0x4 0. "mode_m_fail_mask_fld," "0,1"
group.long 0x50++0xB
line.long 0x0 "lowwrprot,"
hexmask.long 0x0 0.--31. 1. "subsector,The block number that defines the lower block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register."
line.long 0x4 "uppwrprot,"
hexmask.long 0x4 0.--31. 1. "subsector,The block number that defines the upper block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register."
line.long 0x8 "wrprot,"
hexmask.long 0x8 2.--31. 1. "wr_prot_ctrl_resv_fld,"
newline
bitfld.long 0x8 1. "en,When set to 1  any AHB write access with an address within the protection region defined in the lower and upper write protection registers is rejected. An AHB error response is generated and an interrupt source triggered. When set to 0  the protection.." "0,1"
newline
bitfld.long 0x8 0. "inv,When set to 1  the protection region defined in the lower and upper write protection registers is inverted meaning it is the region that the system is permitted to write to. When set to 0  the protection region defined in the lower and upper write.." "0,1"
group.long 0x60++0x1F
line.long 0x0 "indrd,"
hexmask.long.tbyte 0x0 8.--31. 1. "indir_rd_xfer_resv_fld,"
newline
rbitfld.long 0x0 6.--7. "num_ind_ops_done,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed." "0,1,2,3"
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eventfld.long 0x0 5. "ind_ops_done_status,This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1"
newline
rbitfld.long 0x0 4. "rd_queued,Two indirect read operations have been queued" "0,1"
newline
eventfld.long 0x0 3. "sram_full,SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it.'; indirect operation (status)" "0,1"
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rbitfld.long 0x0 2. "rd_status,Indirect read operation in progress (status)" "0,1"
newline
bitfld.long 0x0 1. "cancel,Writing a 1 to this bit will cancel all ongoing indirect read operations." "0,1"
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bitfld.long 0x0 0. "start,Writing a 1 to this bit will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation." "0,1"
line.long 0x4 "indrdwater,"
hexmask.long 0x4 0.--31. 1. "level,This represents the minimum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level passes the watermark  an interrupt is also generated. This field can be disabled by writing a value of all zeroes."
line.long 0x8 "indrdstaddr,"
hexmask.long 0x8 0.--31. 1. "addr,This is the start address from which the indirect access will commence its READ operation."
line.long 0xC "indrdcnt,"
hexmask.long 0xC 0.--31. 1. "value,This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM."
line.long 0x10 "indwr,"
hexmask.long.tbyte 0x10 8.--31. 1. "indir_wr_xfer_resv2_fld,"
newline
rbitfld.long 0x10 6.--7. "indcnt,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed. Write a 1 to.." "0,1,2,3"
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eventfld.long 0x10 5. "inddone,This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1"
newline
rbitfld.long 0x10 4. "rdqueued,Two indirect write operations have been queued" "0,1"
newline
rbitfld.long 0x10 3. "indir_wr_rsvd_fld," "0,1"
newline
rbitfld.long 0x10 2. "rdstat,Indirect write operation in progress (status)" "0,1"
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bitfld.long 0x10 1. "cancel,Writing a 1 to this bit will cancel all ongoing indirect write operations." "0,1"
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bitfld.long 0x10 0. "start,Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation." "0,1"
line.long 0x14 "indwrwater,"
hexmask.long 0x14 0.--31. 1. "level,This represents the maximum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level falls below the watermark  an interrupt is also generated. This field can be disabled by writing a value of all ones."
line.long 0x18 "indwrstaddr,"
hexmask.long 0x18 0.--31. 1. "addr,This is the start address from which the indirect access will commence its READ operation."
line.long 0x1C "indwrcnt,"
hexmask.long 0x1C 0.--31. 1. "value,This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM."
group.long 0x90++0x7
line.long 0x0 "flashcmd,"
hexmask.long.byte 0x0 24.--31. 1. "cmdopcode,The command opcode field should be setup before triggering the command. For example  0x20 maps to SubSector Erase. Writeing to the execute field (bit 0) of this register launches the command. NOTE : Using this approach to issue commands to the.."
newline
bitfld.long 0x0 23. "enrddata,Set to 1 if the command specified in the command opcode field (bits 31:24) requires read data bytes to be received from the device." "0,1"
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bitfld.long 0x0 20.--22. "numrddatabytes,Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for 8 bytes." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 19. "encmdaddr,Set to 1 if the command specified in bits 31:24 requires an address. This should be setup before triggering the command via writing a 1 to the execute field." "0,1"
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bitfld.long 0x0 18. "enmodebit,Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1"
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bitfld.long 0x0 16.--17. "numaddrbytes,Set to the number of address bytes required (the address itself is programmed in the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address.." "0: 1 address byte,1: 2 address bytes,2: 3 address bytes,3: 4 address bytes"
newline
bitfld.long 0x0 15. "enwrdata,Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device." "0,1"
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bitfld.long 0x0 12.--14. "numwrdatabytes,Up to 8 Data bytes may be written using this command Set to 0 for 1 byte  7 for 8 bytes." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 7.--11. 1. "numdummybytes,Set to the number of dummy bytes required This should be setup before triggering the command via the execute field of this register."
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hexmask.long.byte 0x0 2.--6. 1. "flash_cmd_cntrl_resv1_fld,"
newline
rbitfld.long 0x0 1. "cmdexecstat,Command execution in progress." "0,1"
newline
bitfld.long 0x0 0. "execcmd,Execute the command." "0,1"
line.long 0x4 "flashcmdaddr,"
hexmask.long 0x4 0.--31. 1. "addr,This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the address used by the command specified in the opcode field (bits 31:24) of the Flash Command Control register."
rgroup.long 0xA0++0x7
line.long 0x0 "flashcmdrddatalo,"
hexmask.long 0x0 0.--31. 1. "data,This is the data that is returned by the flash device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low."
line.long 0x4 "flashcmdrddataup,Device Instruction Configuration Register"
hexmask.long 0x4 0.--31. 1. "data,This is the data that is returned by the FLASH device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low."
group.long 0xA8++0x7
line.long 0x0 "flashcmdwrdatalo,"
hexmask.long 0x0 0.--31. 1. "data,This is the command write data lower byte. This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the data that is to be written to the flash for any status or configuration write.."
line.long 0x4 "flashcmdwrdataup,"
hexmask.long 0x4 0.--31. 1. "data,This is the command write data upper byte. This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the data that is to be written to the flash for any status or configuration write.."
rgroup.long 0xFC++0x3
line.long 0x0 "moduleid,"
hexmask.long.byte 0x0 25.--31. 1. "mod_id_resv_fld,"
newline
hexmask.long 0x0 0.--24. 1. "value,"
tree.end
tree "SDM_SDMMC"
base ad:0xFF8D1000
group.long 0x0++0xB
line.long 0x0 "CTRL,Control register"
bitfld.long 0x0 25. "USE_INTERNAL_DMAC,Present only for the Internal DMAC configuration; else  it is reserved." "0,1"
bitfld.long 0x0 24. "ENABLE_OD_PULLUP,External open-drain pullup" "0,1"
hexmask.long.byte 0x0 20.--23. 1. "CARD_VOLTAGE_B,Card regulator-B voltage setting; output to card_volt_b port."
newline
hexmask.long.byte 0x0 16.--19. 1. "CARD_VOLTAGE_A,Card regulator-A voltage setting; output to card_volt_a port."
bitfld.long 0x0 11. "CEATA_DEVICE_INTERRUPT_STATUS,0-Interrupts not enabled in CE-ATA device" "0,1"
bitfld.long 0x0 10. "SEND_AUTO_STOP_CCSD,0-Clear bit if DWC_mobile_storage does not reset the bit" "0,1"
newline
bitfld.long 0x0 9. "SEND_CCSD,0-Clear this bit if DWC_mobile_storage does not reset the bit" "0,1"
bitfld.long 0x0 8. "ABORT_READ_DATA,0-No change" "0,1"
bitfld.long 0x0 7. "SEND_IRQ_RESPONSE,0-No Change in this" "0,1"
newline
bitfld.long 0x0 6. "READ_WAIT,0-Clear read wait" "0,1"
bitfld.long 0x0 5. "DMA_ENABLE,0-Disable DMA transfer mode" "0,1"
bitfld.long 0x0 4. "INT_ENABLE,Global interrupt enable/disable bit:" "0,1"
newline
bitfld.long 0x0 2. "DMA_RESET,0-No change" "0,1"
bitfld.long 0x0 1. "FIFO_RESET,0-No change" "0,1"
bitfld.long 0x0 0. "CONTROLLER_RESET,0-No change" "0,1"
line.long 0x4 "PWREN,Power Enable Register"
bitfld.long 0x4 0. "POWER_ENABLE_0,Power on/off switch for up to 16 cards; for example  bit[0] controls card 0.Once power is turned on  firmware should wait for regulator/switch ramp-up time before trying to initialize card." "0,1"
line.long 0x8 "CLKDIV,Clock Divider Register"
hexmask.long.byte 0x8 24.--31. 1. "CLK_DIVIDER3,Clock divider-3 value. Clock division is 2*n. For example  value of 0 means divide by 2*0 = 0 (no division  bypass)  a value of 1 means divide by 2*1 = 2  a value of 'ff' means divide by 2*255 = 510  and so on. In MMC-Ver3.3-only mode  bits.."
hexmask.long.byte 0x8 16.--23. 1. "CLK_DIVIDER2,Clock divider-2 value. Clock division is 2*n. For example  value of 0 means divide by 2*0 = 0 (no division  bypass)  value of 1 means divide by 2*1 = 2  value of 'ff' means divide by 2*255 = 510  and so on. In MMC-Ver3.3-only mode  bits not.."
hexmask.long.byte 0x8 8.--15. 1. "CLK_DIVIDER1,Clock divider-1 value. Clock division is 2*n. For example  value of 0 means divide by 2*0 = 0 (no division  bypass)  value of 1 means divide by 2*1 = 2  value of 'ff' means divide by 2*255 = 510  and so on. In MMC-Ver3.3-only mode  bits not.."
newline
hexmask.long.byte 0x8 0.--7. 1. "CLK_DIVIDER0,Clock divider-0 value. Clock division is 2*n. For example  value of 0 means divide by 2*0 = 0 (no division  bypass)  value of 1 means divide by 2*1 = 2  value of 'ff' means divide by 2*255 = 510  and so on."
rgroup.long 0xC++0x3
line.long 0x0 "CLKSRC,Clock Source Register"
bitfld.long 0x0 30.--31. "CARD15_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on.." "0,1,2,3"
bitfld.long 0x0 28.--29. "CARD14_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on.." "0,1,2,3"
bitfld.long 0x0 26.--27. "CARD13_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on.." "0,1,2,3"
newline
bitfld.long 0x0 24.--25. "CARD12_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on.." "0,1,2,3"
bitfld.long 0x0 22.--23. "CARD11_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on.." "0,1,2,3"
bitfld.long 0x0 20.--21. "CARD10_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on.." "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "CARD9_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
bitfld.long 0x0 16.--17. "CARD8_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
bitfld.long 0x0 14.--15. "CARD7_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "CARD6_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
bitfld.long 0x0 10.--11. "CARD5_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
bitfld.long 0x0 8.--9. "CARD4_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "CARD3_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
bitfld.long 0x0 4.--5. "CARD2_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
bitfld.long 0x0 2.--3. "CARD1_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "CARD0_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
group.long 0x10++0x1F
line.long 0x0 "CLKENA,Clock Enable Register"
bitfld.long 0x0 16. "CCLK_LOW_POWER_0,Low-power control for up to 16 SD card clocks and one MMC card clock supported." "0,1"
bitfld.long 0x0 0. "CCLK_ENABLE_0,Clock-enable control for up to 16 SD card clocks and one MMC card clock supported." "0,1"
line.long 0x4 "TMOUT,Timeout Register"
hexmask.long.tbyte 0x4 8.--31. 1. "DATA_TIMEOUT,Value for card Data Read Timeout; same value also used for Data"
hexmask.long.byte 0x4 0.--7. 1. "RESPONSE_TIMEOUT,Response timeout value."
line.long 0x8 "CTYPE,Card Type Register"
bitfld.long 0x8 16. "CARD0_WIDTH1,One bit per card indicates if card is 8-bit:" "0,1"
bitfld.long 0x8 0. "CARD0_WIDTH2,One bit per card indicates if card is 1-bit or 4-bit:" "0,1"
line.long 0xC "BLKSIZ,Block Size Register"
hexmask.long.word 0xC 0.--15. 1. "BLOCK_SIZE,Block size"
line.long 0x10 "BYTCNT,Byte Count Register"
hexmask.long 0x10 0.--31. 1. "BYTE_COUNT,Number of bytes to be transferred; should be integer multiple of Block Size for block transfers."
line.long 0x14 "INTMASK,Interrupt Mask Register"
bitfld.long 0x14 31. "SDIO_INT_MASK_CARD15,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 30. "SDIO_INT_MASK_CARD14,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 29. "SDIO_INT_MASK_CARD13,Mask SDIO interrupts" "0,1"
newline
bitfld.long 0x14 28. "SDIO_INT_MASK_CARD12,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 27. "SDIO_INT_MASK_CARD11,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 26. "SDIO_INT_MASK_CARD10,Mask SDIO interrupts" "0,1"
newline
bitfld.long 0x14 25. "SDIO_INT_MASK_CARD9,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 24. "SDIO_INT_MASK_CARD8,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 23. "SDIO_INT_MASK_CARD7,Mask SDIO interrupts" "0,1"
newline
bitfld.long 0x14 22. "SDIO_INT_MASK_CARD6,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 21. "SDIO_INT_MASK_CARD5,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 20. "SDIO_INT_MASK_CARD4,Mask SDIO interrupts" "0,1"
newline
bitfld.long 0x14 19. "SDIO_INT_MASK_CARD3,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 18. "SDIO_INT_MASK_CARD2,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 17. "SDIO_INT_MASK_CARD1,Mask SDIO interrupts" "0,1"
newline
bitfld.long 0x14 16. "SDIO_INT_MASK_CARD0,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 15. "EBE_INT_MASK,End-bit error (read)/Write no CRC (EBE) interrupt enable." "0,1"
bitfld.long 0x14 14. "ACD_INT_MASK,Auto command done (ACD) interrupt enable." "0,1"
newline
bitfld.long 0x14 13. "SBE_BCI_INT_MASK,Start Bit Error(SBE)/Busy Complete Interrupt (BCI) interrupt enable." "0,1"
bitfld.long 0x14 12. "HLE_INT_MASK,Hardware locked write error (HLE) interrupt enable." "0,1"
bitfld.long 0x14 11. "FRUN_INT_MASK,FIFO underrun/overrun error (FRUN) interrupt enable." "0,1"
newline
bitfld.long 0x14 10. "HTO_INT_MASK,Data starvation-by-host timeout (HTO) /Volt_switch_int interrupt enable." "0,1"
bitfld.long 0x14 9. "DRTO_INT_MASK,Data read timeout (DRTO) interrupt enable." "0,1"
bitfld.long 0x14 8. "RTO_INT_MASK,Response timeout (RTO) interrupt enable." "0,1"
newline
bitfld.long 0x14 7. "DCRC_INT_MASK,Data CRC error (DCRC) interrupt enable." "0,1"
bitfld.long 0x14 6. "RCRC_INT_MASK,Response CRC error (RCRC) interrupt enable." "0,1"
bitfld.long 0x14 5. "RXDR_INT_MASK,Receive FIFO data request (RXDR) interrupt enable." "0,1"
newline
bitfld.long 0x14 4. "TXDR_INT_MASK,Transmit FIFO data request (TXDR) interrupt enable." "0,1"
bitfld.long 0x14 3. "DTO_INT_MASK,Data transfer over (DTO) interrupt enable." "0,1"
bitfld.long 0x14 2. "CMD_INT_MASK,Command done (CD) interrupt enable" "0,1"
newline
bitfld.long 0x14 1. "RE_INT_MASK,Response error (RE) interrupt enable." "0,1"
bitfld.long 0x14 0. "CD_INT_MASK,Card detect (CD) interrupt enable." "0,1"
line.long 0x18 "CMDARG,Command Argument Register"
hexmask.long 0x18 0.--31. 1. "CMD_ARG,Value indicates command argument to be passed to card"
line.long 0x1C "CMD,Command Register"
bitfld.long 0x1C 31. "START_CMD,Start command. Once command is taken by CIU  bit is cleared." "0,1"
bitfld.long 0x1C 29. "USE_HOLD_REG,Use Hold Register" "0,1"
bitfld.long 0x1C 28. "VOLT_SWITCH,Voltage switch bit" "0,1"
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bitfld.long 0x1C 27. "BOOT_MODE,Boot Mode" "0,1"
bitfld.long 0x1C 26. "DISABLE_BOOT,Disable Boot. When software sets this bit along with start_cmd  CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together." "0,1"
bitfld.long 0x1C 25. "EXPECT_BOOT_ACK,Expect Boot Acknowledge. When Software sets this bit along with" "0,1"
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bitfld.long 0x1C 24. "ENABLE_BOOT,Enable Boot this bit should be set only for mandatory boot mode." "0,1"
bitfld.long 0x1C 23. "CCS_EXPECTED,0-Interrupts are not enabled in CE-ATA device (nIEN = 1 in" "0,1"
bitfld.long 0x1C 22. "READ_CEATA_DEVICE,0-Host is not performing read access (RW_REG or RW_BLK)" "0,1"
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bitfld.long 0x1C 21. "UPDATE_CLOCK_REGISTERS_ONLY,0-Normal command sequence" "0,1"
hexmask.long.byte 0x1C 16.--20. 1. "CARD_NUMBER,Card number in use. Represents physical slot number of card being"
bitfld.long 0x1C 15. "SEND_INITIALIZATION,0-Do not send initialization sequence (80 clocks of 1) before" "0,1"
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bitfld.long 0x1C 14. "STOP_ABORT_CMD,0-Neither stop nor abort command to stop current data transfer" "0,1"
bitfld.long 0x1C 13. "WAIT_PRVDATA_COMPLETE,0-Send command at once  even if previous data transfer has not" "0,1"
bitfld.long 0x1C 12. "SEND_AUTO_STOP,0-No stop command sent at end of data transfer" "0,1"
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bitfld.long 0x1C 11. "TRANSFER_MODE,0-Block data transfer command" "0,1"
bitfld.long 0x1C 10. "READ_WRITE,0-Read from card" "0,1"
bitfld.long 0x1C 9. "DATA_EXPECTED,0-No data transfer expected (read/write)" "0,1"
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bitfld.long 0x1C 8. "CHECK_RESPONSE_CRC,0-Do not check response CRC" "0,1"
bitfld.long 0x1C 7. "RESPONSE_LENGTH,0-Short response expected from card" "0,1"
bitfld.long 0x1C 6. "RESPONSE_EXPECT,0-No response expected from card" "0,1"
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hexmask.long.byte 0x1C 0.--5. 1. "CMD_INDEX,Command index"
rgroup.long 0x30++0x13
line.long 0x0 "RESP0,Response Register 0"
hexmask.long 0x0 0.--31. 1. "RESPONSE0,Bit[31:0] of response"
line.long 0x4 "RESP1,Response Register 1"
hexmask.long 0x4 0.--31. 1. "RESPONSE1,Register represents bit[63:32] of long response."
line.long 0x8 "RESP2,Response Register 2"
hexmask.long 0x8 0.--31. 1. "RESPONSE2,Bit[95:64] of long response"
line.long 0xC "RESP3,Response Register 3"
hexmask.long 0xC 0.--31. 1. "RESPONSE3,Bit[127:96] of long response"
line.long 0x10 "MINTSTS,Name: Masked Interrupt Status Register"
bitfld.long 0x10 31. "SDIO_INTERRUPT_CARD15,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 30. "SDIO_INTERRUPT_CARD14,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 29. "SDIO_INTERRUPT_CARD13,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
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bitfld.long 0x10 28. "SDIO_INTERRUPT_CARD12,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 27. "SDIO_INTERRUPT_CARD11,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 26. "SDIO_INTERRUPT_CARD10,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
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bitfld.long 0x10 25. "SDIO_INTERRUPT_CARD9,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 24. "SDIO_INTERRUPT_CARD8,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 23. "SDIO_INTERRUPT_CARD7,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
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bitfld.long 0x10 22. "SDIO_INTERRUPT_CARD6,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 21. "SDIO_INTERRUPT_CARD5,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 20. "SDIO_INTERRUPT_CARD4,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
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bitfld.long 0x10 19. "SDIO_INTERRUPT_CARD3,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 18. "SDIO_INTERRUPT_CARD2,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 17. "SDIO_INTERRUPT_CARD1,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
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bitfld.long 0x10 16. "SDIO_INTERRUPT_CARD0,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 15. "END_BIT_ERROR_INTERRUPT,Interrupt enabled only if corresponding bit in interrupt mask register is set." "0,1"
bitfld.long 0x10 14. "AUTO_COMMAND_DONE_INTERRUPT,bit 14 Auto command done (ACD)" "0,1"
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bitfld.long 0x10 13. "BUSY_COMPLETE_INTERRUPT_INTERRUPT,bit 13 Start Bit Error(SBE)/Busy Complete Interrupt (BCI)" "0,1"
bitfld.long 0x10 12. "HARDWARE_LOCKED_WRITE_INTERRUPT,bit 12 Hardware locked write error (HLE)" "0,1"
bitfld.long 0x10 11. "FIFO_UNDER_OVER_RUN_INTERRUPT,bit 11 FIFO underrun/overrun error (FRUN)" "0,1"
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bitfld.long 0x10 10. "HOST_TIMEOUT_INTERRUPT,bit 10 Data starvation by host timeout (HTO)/Volt_switch_int" "0,1"
bitfld.long 0x10 9. "DATA_READ_TIMEOUT_INTERRUPT,bit 9 Data read timeout (DRTO)" "0,1"
bitfld.long 0x10 8. "RESPONSE_TIMEOUT_INTERRUPT,bit 8 Response timeout (RTO)" "0,1"
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bitfld.long 0x10 7. "DATA_CRC_ERROR_INTERRUPT,bit 7 Data CRC error (DCRC)" "0,1"
bitfld.long 0x10 6. "RESPONSE_CRC_ERROR_INTERRUPT,bit 6 Response CRC error (RCRC)" "0,1"
bitfld.long 0x10 5. "RECEIVE_FIFO_DATA_REQUEST_INTERRUPT,bit 5 Receive FIFO data request (RXDR)" "0,1"
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bitfld.long 0x10 4. "TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT,bit 4 Transmit FIFO data request (TXDR)" "0,1"
bitfld.long 0x10 3. "DATA_TRANSFER_OVER_INTERRUPT,bit 3 Data transfer over (DTO)" "0,1"
bitfld.long 0x10 2. "COMMAND_DONE_INTERRUPT,bit 2 Command done (CD)" "0,1"
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bitfld.long 0x10 1. "RESPONSE_ERROR_INTERRUPT,bit 1 Response error (RE)" "0,1"
bitfld.long 0x10 0. "CARD_DETECT_INTERRUPT,bit 0 Card detect (CD)" "0,1"
group.long 0x44++0x3
line.long 0x0 "RINTSTS,Name: Raw Interrupt Status Register"
eventfld.long 0x0 31. "SDIO_INTERRUPT_CARD15,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 30. "SDIO_INTERRUPT_CARD14,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 29. "SDIO_INTERRUPT_CARD13,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
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eventfld.long 0x0 28. "SDIO_INTERRUPT_CARD12,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 27. "SDIO_INTERRUPT_CARD11,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 26. "SDIO_INTERRUPT_CARD10,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
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eventfld.long 0x0 25. "SDIO_INTERRUPT_CARD9,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 24. "SDIO_INTERRUPT_CARD8,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 23. "SDIO_INTERRUPT_CARD7,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
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eventfld.long 0x0 22. "SDIO_INTERRUPT_CARD6,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 21. "SDIO_INTERRUPT_CARD5,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 20. "SDIO_INTERRUPT_CARD4,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
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eventfld.long 0x0 19. "SDIO_INTERRUPT_CARD3,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 18. "SDIO_INTERRUPT_CARD2,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 17. "SDIO_INTERRUPT_CARD1,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
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eventfld.long 0x0 16. "SDIO_INTERRUPT_CARD0,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 15. "END_BIT_ERROR_STATUS,STATUS ." "0,1"
eventfld.long 0x0 14. "AUTO_COMMAND_DONE_STATUS,bit 14 Auto command done (ACD)" "0,1"
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eventfld.long 0x0 13. "BUSY_COMPLETE_STATUS,bit 13 Start Bit Error(SBE)/Busy Complete STATUS (BCI)" "0,1"
eventfld.long 0x0 12. "HARDWARE_LOCKED_WRITE_STATUS,bit 12 Hardware locked write error (HLE)" "0,1"
eventfld.long 0x0 11. "FIFO_UNDER_OVER_RUN_STATUS,bit 11 FIFO underrun/overrun error (FRUN)" "0,1"
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eventfld.long 0x0 10. "HOST_TIMEOUT_STATUS,bit 10 Data starvation by host timeout (HTO)/Volt_switch_int" "0,1"
eventfld.long 0x0 9. "DATA_READ_TIMEOUT_STATUS,bit 9 Data read timeout (DRTO)" "0,1"
eventfld.long 0x0 8. "RESPONSE_TIMEOUT_STATUS,bit 8 Response timeout (RTO)" "0,1"
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eventfld.long 0x0 7. "DATA_CRC_ERROR_STATUS,bit 7 Data CRC error (DCRC)" "0,1"
eventfld.long 0x0 6. "RESPONSE_CRC_ERROR_STATUS,bit 6 Response CRC error (RCRC)" "0,1"
eventfld.long 0x0 5. "RECEIVE_FIFO_DATA_REQUEST_STATUS,bit 5 Receive FIFO data request (RXDR)" "0,1"
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eventfld.long 0x0 4. "TRANSMIT_RECEIVE_FIFO_DATA_STATUS,bit 4 Transmit FIFO data request (TXDR)" "0,1"
eventfld.long 0x0 3. "DATA_TRANSFER_OVER_STATUS,bit 3 Data transfer over (DTO)" "0,1"
eventfld.long 0x0 2. "COMMAND_DONE_STATUS,bit 2 Command done (CD)" "0,1"
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eventfld.long 0x0 1. "RESPONSE_ERROR_STATUS,bit 1 Response error (RE)" "0,1"
eventfld.long 0x0 0. "CARD_DETECT_STATUS,bit 0 Card detect (CD)" "0,1"
rgroup.long 0x48++0x3
line.long 0x0 "STATUS,Name: Status Register"
bitfld.long 0x0 31. "DMA_REQ,DMA request signal state; either dw_dma_req or ge_dma_req " "0,1"
bitfld.long 0x0 30. "DMA_ACK,DMA acknowledge signal state; either dw_dma_ack or" "0,1"
hexmask.long.word 0x0 17.--29. 1. "FIFO_COUNT,FIFO count Number of filled locations in FIFO"
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hexmask.long.byte 0x0 11.--16. 1. "RESPONSE_INDEX,Index of previous response  including any auto-stop sent by core"
bitfld.long 0x0 10. "DATA_STATE_MC_BUSY,Data transmit or receive state-machine is busy" "0,1"
bitfld.long 0x0 9. "DATA_BUSY,Inverted version of raw selected card_data[0]" "0,1"
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bitfld.long 0x0 8. "DATA_3_STATUS,Raw selected card_data[3]; checks whether card is present" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "COMMAND_FSM_STATES,Command FSM states:"
bitfld.long 0x0 3. "FIFO_FULL,FIFO is full status" "0,1"
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bitfld.long 0x0 2. "FIFO_EMPTY,FIFO is empty status" "0,1"
bitfld.long 0x0 1. "FIFO_TX_WATERMARK,FIFO reached Transmit watermark level; not qualified with data" "0,1"
bitfld.long 0x0 0. "FIFO_RX_WATERMARK,FIFO reached Receive watermark level; not qualified with data" "0,1"
group.long 0x4C++0x3
line.long 0x0 "FIFOTH,Name: FIFO Threshold Watermark Register"
bitfld.long 0x0 28.--30. "DW_DMA_Multiple_Transaction_Size,Burst size of multiple transaction; should be programmed same as" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0 16.--27. 1. "RX_WMark,FIFO threshold watermark level when receiving data to card."
hexmask.long.word 0x0 0.--11. 1. "TX_WMark,FIFO threshold watermark level when transmitting data to card."
rgroup.long 0x50++0x7
line.long 0x0 "CDETECT,Name: Card Detect Register"
bitfld.long 0x0 0. "CARD0_DETECT_N,Value on card_detect_n input ports (1 bit per card); read-only bits.0 represents presence of card. Only NUM_CARDS number of bits are implemented." "0,1"
line.long 0x4 "WRTPRT,Name: Write Protect Register"
bitfld.long 0x4 0. "WRITE_PROTECT_0,Value on card_write_prt input ports (1 bit per card)." "0,1"
group.long 0x58++0x3
line.long 0x0 "GPIO,Name: General Purpose Input/Output Register"
hexmask.long.word 0x0 8.--23. 1. "GPO,Value needed to be driven to gpo pins; this portion of register is read/write. Valid only when AREA_OPTIMIZED parameter is 0."
hexmask.long.byte 0x0 0.--7. 1. "GPI,Value on gpi input ports; this portion of register is read-only. Valid only when AREA_OPTIMIZED parameter is 0."
rgroup.long 0x5C++0x7
line.long 0x0 "TCBCNT,Name: Transferred CIU Card Byte Count Register"
hexmask.long 0x0 0.--31. 1. "TRANS_CARD_BYTE_COUNT,Number of bytes transferred by CIU unit to card."
line.long 0x4 "TBBCNT,Name: Transferred Host to BIU-FIFO Byte Count Register"
hexmask.long 0x4 0.--31. 1. "TRANS_FIFO_BYTE_COUNT,Number of bytes transferred between Host/DMA memory and BIU FIFO."
group.long 0x64++0x7
line.long 0x0 "DEBNCE,Name: Debounce Count Register"
hexmask.long.tbyte 0x0 0.--23. 1. "DEBOUNCE_COUNT,Number of host clocks (clk) used by debounce filter logic; typical"
line.long 0x4 "USRID,Name: User ID Register"
hexmask.long 0x4 0.--31. 1. "USR_ID,User identification register; value set by user. Default reset value can be picked by user while configuring core before synthesis."
rgroup.long 0x6C++0x7
line.long 0x0 "VERID,Name: Version ID Register"
hexmask.long 0x0 0.--31. 1. "VER_ID,Synopsys version identification register; register value is hard-wired.Can be read by firmware to support different versions of core."
line.long 0x4 "HCON,Name: Hardware Configuration Register"
bitfld.long 0x4 27. "ADDR_CONFIG,Address configuration" "0,1"
bitfld.long 0x4 26. "AREA_OPT,Area Optimization" "0,1"
bitfld.long 0x4 24.--25. "NUM_CLK_DIC,NUM_CLK_DIVIDER - 1" "0,1,2,3"
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bitfld.long 0x4 23. "FALSE_PATH,Set Clock False Path" "0,1"
bitfld.long 0x4 22. "HOLD_REG,Implement HOLD register" "0,1"
bitfld.long 0x4 21. "FIFO_RAM_IN,FIFO Ram Inside" "0,1"
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bitfld.long 0x4 18.--20. "GE_DMA_DATA_WIDTH,Generic DMA Data Width" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 16.--17. "DMA_IF,DMA Interface" "0,1,2,3"
hexmask.long.byte 0x4 10.--15. 1. "H_ADDR_WIDTH,H Address Width"
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bitfld.long 0x4 7.--9. "H_DATA_WIDTH,H Data Width" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 6. "BUS_TYPE,Bus type" "0,1"
hexmask.long.byte 0x4 1.--5. 1. "NUM_CARD,NUM_CARD - 1"
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bitfld.long 0x4 0. "CARD_TYPE,Card type" "0,1"
group.long 0x74++0x7
line.long 0x0 "UHS_REG,Name: UHS-1 Register"
bitfld.long 0x0 31. "DDR_REG_15,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 30. "DDR_REG_14,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 29. "DDR_REG_13,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
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bitfld.long 0x0 28. "DDR_REG_12,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 27. "DDR_REG_11,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 26. "DDR_REG_10,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
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bitfld.long 0x0 25. "DDR_REG_9,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 24. "DDR_REG_8,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 23. "DDR_REG_7,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
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bitfld.long 0x0 22. "DDR_REG_6,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 21. "DDR_REG_5,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 20. "DDR_REG_4,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
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bitfld.long 0x0 19. "DDR_REG_3,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 18. "DDR_REG_2,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 17. "DDR_REG_1,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
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bitfld.long 0x0 16. "DDR_REG_0,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 15. "VOLT_REG_15,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 14. "VOLT_REG_14,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
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bitfld.long 0x0 13. "VOLT_REG_13,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 12. "VOLT_REG_12,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 11. "VOLT_REG_11,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
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bitfld.long 0x0 10. "VOLT_REG_10,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 9. "VOLT_REG_9,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 8. "VOLT_REG_8,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
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bitfld.long 0x0 7. "VOLT_REG_7,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 6. "VOLT_REG_6,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 5. "VOLT_REG_5,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
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bitfld.long 0x0 4. "VOLT_REG_4,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 3. "VOLT_REG_3,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 2. "VOLT_REG_2,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
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bitfld.long 0x0 1. "VOLT_REG_1,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 0. "VOLT_REG_0,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
line.long 0x4 "RST_n,Name: H/W Reset"
bitfld.long 0x4 0. "CARD0_RESET,Hardware reset." "0,1"
group.long 0x80++0x3
line.long 0x0 "BMOD,Name: Bus Mode Register"
rbitfld.long 0x0 8.--10. "PBL,Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible.." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 7. "DE,IDMAC Enable. When set  the IDMAC is enabled." "0,1"
hexmask.long.byte 0x0 2.--6. 1. "DSL,Descriptor Skip Length. Specifies the number of HWord/Word/Dword (depending on 16/32/64-bit bus) to skip between two unchained descriptors. This is applicable only for dual buffer structure."
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bitfld.long 0x0 1. "FB,Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set the AHB will use only SINGLE  INCR4  INCR8 or" "0,1"
bitfld.long 0x0 0. "SWR,Software Reset.When set the DMA Controller resets all its internal registers." "0,1"
wgroup.long 0x84++0x3
line.long 0x0 "PLDMND,Name: Poll Demand Register"
hexmask.long 0x0 0.--31. 1. "PD,Poll Demand. If the OWN bit of a descriptor is not set  the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal"
group.long 0x88++0xB
line.long 0x0 "DBADDR,Name: Descriptor List Base Address Register"
hexmask.long 0x0 0.--31. 1. "SDL,Start of Descriptor List. Contains the base address of the First Descriptor."
line.long 0x4 "IDSTS,Name: Internal DMAC Status Register"
hexmask.long.byte 0x4 13.--16. 1. "FSM,DMAC FSM present state."
rbitfld.long 0x4 10.--12. "EB,Error Bits. Indicates the type of error that caused a Bus Error." "0,1,2,3,4,5,6,7"
eventfld.long 0x4 9. "AIS,Abnormal Interrupt Summary. Logical OR of the following:" "0,1"
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eventfld.long 0x4 8. "NIS,Normal Interrupt Summary. Logical OR of the following:" "0,1"
eventfld.long 0x4 5. "CES,Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits:" "0,1"
eventfld.long 0x4 4. "DU,Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit." "0,1"
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eventfld.long 0x4 2. "FBE,Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set  the DMA disables all its bus accesses. Writing a 1 clears this bit." "0,1"
eventfld.long 0x4 1. "RI,Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit." "0,1"
eventfld.long 0x4 0. "TI,Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a '1' clears this bit." "0,1"
line.long 0x8 "IDINTEN,Name: Internal DMAC Interrupt Enable Register"
bitfld.long 0x8 9. "AI,Abnormal Interrupt Summary Enable. When set  an abnormal interrupt is enabled. This bit enables the following bits:" "0,1"
bitfld.long 0x8 8. "NI,Normal Interrupt Summary Enable. When set  a normal interrupt is enabled. When reset  a normal interrupt is disabled. This bit enables the following bits:" "0,1"
bitfld.long 0x8 5. "CES,Card Error summary Interrupt Enable. When set  it enables the Card Interrupt summary." "0,1"
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bitfld.long 0x8 4. "DU,Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable  the DU interrupt is enabled." "0,1"
bitfld.long 0x8 2. "FBE,Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable  the Fatal Bus Error Interrupt is enabled. When reset  Fatal Bus Error Enable Interrupt is disabled." "0,1"
bitfld.long 0x8 1. "RI,Receive Interrupt Enable. When set with Normal Interrupt Summary Enable  Receive Interrupt is enabled. When reset  Receive Interrupt is disabled." "0,1"
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bitfld.long 0x8 0. "TI,Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable  Transmit Interrupt is enabled. When reset  Transmit Interrupt is disabled." "0,1"
rgroup.long 0x94++0x7
line.long 0x0 "DSCADDR,Name: Current Host Descriptor Address Register"
hexmask.long 0x0 0.--31. 1. "HDA,Host Descriptor Address Pointer. Cleared on reset. Pointer updated by IDMAC during operation. This register points to the start address of the current descriptor read by the IDMAC."
line.long 0x4 "BUFADDR,Name: Current Buffer Descriptor Address Register"
hexmask.long 0x4 0.--31. 1. "HBA,Host Buffer Address Pointer. Cleared on Reset. Pointer updated by IDMAC during operation. This register points to the current Data Buffer Address being accessed by the IDMAC."
group.long 0x100++0x13
line.long 0x0 "CARDTHRCTL,Name: Card Threshold Control Register"
hexmask.long.word 0x0 16.--28. 1. "CARDRDTHRESHOLD,Card Read Threshold size; N depends on the FIFO size:"
rbitfld.long 0x0 2. "CARDWRTHREN,Card Write Threshold Enable" "0,1"
bitfld.long 0x0 1. "BUSY_CLR_INT_EN,Busy Clear Interrupt generation:" "0,1"
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bitfld.long 0x0 0. "CARDRDTHREN,Card Read Threshold Enable" "0,1"
line.long 0x4 "BACK_END_POWER_R,Name: Back End Power Register"
bitfld.long 0x4 15. "BACK_END_POWER_15,Back end power" "0,1"
bitfld.long 0x4 14. "BACK_END_POWER_14,Back end power" "0,1"
bitfld.long 0x4 13. "BACK_END_POWER_13,Back end power" "0,1"
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bitfld.long 0x4 12. "BACK_END_POWER_12,Back end power" "0,1"
bitfld.long 0x4 11. "BACK_END_POWER_11,Back end power" "0,1"
bitfld.long 0x4 10. "BACK_END_POWER_10,Back end power" "0,1"
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bitfld.long 0x4 9. "BACK_END_POWER_9,Back end power" "0,1"
bitfld.long 0x4 8. "BACK_END_POWER_8,Back end power" "0,1"
bitfld.long 0x4 7. "BACK_END_POWER_7,Back end power" "0,1"
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bitfld.long 0x4 6. "BACK_END_POWER_6,Back end power" "0,1"
bitfld.long 0x4 5. "BACK_END_POWER_5,Back end power" "0,1"
bitfld.long 0x4 4. "BACK_END_POWER_4,Back end power" "0,1"
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bitfld.long 0x4 3. "BACK_END_POWER_3,Back end power" "0,1"
bitfld.long 0x4 2. "BACK_END_POWER_2,Back end power" "0,1"
bitfld.long 0x4 1. "BACK_END_POWER_1,Back end power" "0,1"
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bitfld.long 0x4 0. "BACK_END_POWER_0,Back end power" "0,1"
line.long 0x8 "UHS_REG_EXT,Name: UHS Register Extention"
bitfld.long 0x8 30.--31. "EXT_CLK_MUX_CTRL,Input clock control for cclk_in. The MUX controlled by these bits exists outside DWC_mobile_storage IP." "0,1,2,3"
hexmask.long.byte 0x8 23.--29. 1. "CLK_DRV_PHASE_CTRL,Control for amount of phase shift on cclk_in_drv clock. Can choose three MSBs to control delay lines and four LSBs to control phase shift; alternatively  use only LSBs."
hexmask.long.byte 0x8 16.--22. 1. "CLK_SMPL_PHASE_CTRL,Control for amount of phase shift on cclk_in_sample clock. Can choose three MSBs to control delay lines and four LSBs to control phase shift; alternatively  use only LSBs."
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bitfld.long 0x8 15. "MMC_VOLT_REG_15,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 14. "MMC_VOLT_REG_14,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 13. "MMC_VOLT_REG_13,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
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bitfld.long 0x8 12. "MMC_VOLT_REG_12,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 11. "MMC_VOLT_REG_11,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 10. "MMC_VOLT_REG_10,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
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bitfld.long 0x8 9. "MMC_VOLT_REG_9,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 8. "MMC_VOLT_REG_8,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 7. "MMC_VOLT_REG_7,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
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bitfld.long 0x8 6. "MMC_VOLT_REG_6,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 5. "MMC_VOLT_REG_5,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 4. "MMC_VOLT_REG_4,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
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bitfld.long 0x8 3. "MMC_VOLT_REG_3,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 2. "MMC_VOLT_REG_2,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 1. "MMC_VOLT_REG_1,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
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bitfld.long 0x8 0. "MMC_VOLT_REG_0,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
line.long 0xC "EMMC_DDR_REG,Name: EMMC DDR Register"
rbitfld.long 0xC 31. "HS400_MODE,HS400 Mode Enable" "0,1"
bitfld.long 0xC 0. "HALF_START_BIT_0,Control for start bit detection mechanism inside" "0,1"
line.long 0x10 "ENABLE_SHIFT,Name: Enable Phase Shift Register"
bitfld.long 0x10 0.--1. "ENABLE_SHIFT_CARD0,Control for the amount of phase shift provided on the default" "0,1,2,3"
group.long 0x200++0x3
line.long 0x0 "DATA,Provides read/write access to data FIFO. Addresses 0x200 and above are mapped to the data FIFO. More than one address is mapped to data FIFO so that FIFO can be accessed using bursts."
hexmask.long 0x0 0.--31. 1. "value,Provides read/write access to data FIFO."
tree.end
tree "SDM_SDMMCECC"
base ad:0xFFA20000
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,IP slicon revision ID"
hexmask.long.word 0x0 0.--15. 1. "SIREV,IP Rev #"
line.long 0x4 "IP_REV_ID2,IP memory configuration"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,Lookup Table Depth."
bitfld.long 0x4 13.--15. "RAM_TYPE,Defines RAM type." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 10.--12. "ECC_SIZE,ECC Size. Total number of ECC bits is dependent on the number of encoder/decoder implemented. This is specifying the width of the ECC syndrome." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 5.--9. 1. "DAT,Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size."
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hexmask.long.byte 0x4 0.--4. 1. "ADDR,Number of address bits (This represent the memory size)  Support 32 - 0 address bits."
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
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bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
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bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
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bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
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eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
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bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,Mode status flag"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
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eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
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eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
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hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
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hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
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hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
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hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
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bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,Individual decoder flags for single and double bits errors."
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
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eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
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eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
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eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
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eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8," "0,1"
eventfld.long 0x0 30. "VALID7," "0,1"
newline
eventfld.long 0x0 29. "VALID6," "0,1"
eventfld.long 0x0 28. "VALID5," "0,1"
newline
eventfld.long 0x0 27. "VALID4," "0,1"
eventfld.long 0x0 26. "VALID3," "0,1"
newline
eventfld.long 0x0 25. "VALID2," "0,1"
eventfld.long 0x0 24. "VALID1," "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "SDM_UART"
base ad:0xFF8D0000
rgroup.long 0x0++0x3
line.long 0x0 "RBR,Receive Buffer Register. reading this register when the DLAB bit is zero;"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_RBR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "rbr,Receive Buffer Register:"
group.long 0x0++0x3
line.long 0x0 "DLL,Receive Buffer Register. reading this register when the DLAB bit is zero;"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_DLL_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "dll,Divisor Latch (Low):"
group.long 0x0++0x7
line.long 0x0 "THR,Receive Buffer Register. reading this register when the DLAB bit is zero;"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_THR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "thr,Transmit Holding Register:"
line.long 0x4 "IER,Interrupt Enable Register:"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IER_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x4 7. "PTIME,Interrupt Enable Register: PTIME  Programmable THRE Interrupt Mode Enable." "0: disabled,1: enabled"
newline
rbitfld.long 0x4 4.--6. "RSVD_IER_6to4,Reserved bits [6:4] - Read Only" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "EDSSI,Interrupt Enable Register: EDSSI  Enable Modem Status Interrupt." "0: disabled,1: enabled"
newline
bitfld.long 0x4 2. "ELSI,Interrupt Enable Register: ELSI  Enable Receiver Line Status Interrupt." "0: disabled,1: enabled"
bitfld.long 0x4 1. "ETBEI,Interrupt Enable Register: ETBEI  Enable Transmit Holding Register Empty Interrupt." "0: disabled,1: enabled"
newline
bitfld.long 0x4 0. "ERBFI,Interrupt Enable Register: ERBFI  Enable Received Data Available Interrupt." "0: disabled,1: enabled"
group.long 0x4++0x3
line.long 0x0 "DLH,Divisor Latch High (DLH) Register."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_DLH_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "dlh,Divisor Latch High 8-bit register field - used to set the UART baud-rate"
rgroup.long 0x8++0x3
line.long 0x0 "IIR,Interrupt Identification Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IIR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x0 6.--7. "FIFOSE,Bits[7:6]  FIFO's Enabled (or FIFOSE):" "0: disabled,?,?,?"
newline
bitfld.long 0x0 4.--5. "RSVD_IIR_5to4,Reserved bits [5:4] - Read Only" "0,1,2,3"
hexmask.long.byte 0x0 0.--3. 1. "IID,Bits[3:0]  Interrupt ID (or IID):"
group.long 0x8++0xB
line.long 0x0 "FCR,FIFO Control Register."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_FCR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x0 6.--7. "RT,Bits[7:6]  RCVR Trigger (or RT):." "0: 1 character in the FIFO,1: FIFO 1/4 full,?,?"
newline
bitfld.long 0x0 4.--5. "TET,Bits[5:4]  TX Empty Trigger (or TET):" "0: FIFO empty,1: 2 characters in the FIFO,?,?"
bitfld.long 0x0 3. "DMAM,Bit[3]  DMA Mode (or DMAM):" "0: mode 0,1: mode 1"
newline
bitfld.long 0x0 2. "XFIFOR,Bit[2]  XMIT FIFO Reset (or XFIFOR):" "0,1"
bitfld.long 0x0 1. "RFIFOR,Bit[1]  RCVR FIFO Reset (or RFIFOR):" "0,1"
newline
bitfld.long 0x0 0. "FIFOE,Bit[0]  FIFO Enable (or FIFOE):" "0,1"
line.long 0x4 "LCR,Line Control Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_LCR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x4 7. "DLAB,Divisor Latch Access Bit." "0,1"
newline
bitfld.long 0x4 6. "Break,Break Control Bit." "0,1"
bitfld.long 0x4 5. "SP,From DW_apb_uart_regfile.sv:" "0,1"
newline
bitfld.long 0x4 4. "EPS,Even Parity Select." "0,1"
bitfld.long 0x4 3. "PEN,Parity Enable." "0: parity disabled,1: parity enabled"
newline
bitfld.long 0x4 2. "STOP,Number of stop bits." "0: 1 stop bit,1: 1"
bitfld.long 0x4 0.--1. "DLS,Data Length Select." "0: 5 bits,1: 6 bits,?,?"
line.long 0x8 "MCR,Modem Control Register"
hexmask.long 0x8 7.--31. 1. "RSVD_MCR_31to7,Reserved bits [31:7] - Read Only"
rbitfld.long 0x8 6. "SIRE,SIR Mode Enable." "0: IrDA SIR Mode disabled,1: IrDA SIR Mode enabled"
newline
bitfld.long 0x8 5. "AFCE,Auto Flow Control Enable." "0: Auto Flow Control Mode disabled,1: Auto Flow Control Mode enabled"
bitfld.long 0x8 4. "LoopBack,LoopBack Bit." "0,1"
newline
bitfld.long 0x8 3. "OUT2,OUT2." "0: out2_n de-asserted,1: out2_n asserted"
bitfld.long 0x8 2. "OUT1,OUT1." "0: out1_n de-asserted,1: out1_n asserted"
newline
bitfld.long 0x8 1. "RTS,Request to Send." "0,1"
bitfld.long 0x8 0. "DTR,Data Terminal Ready." "0: dtr_n de-asserted,1: dtr_n asserted"
rgroup.long 0x14++0x7
line.long 0x0 "LSR,Line Status Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_LSR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x0 7. "RFE,Receiver FIFO Error bit." "0: no error in RX FIFO,1: error in RX FIFO"
newline
bitfld.long 0x0 6. "TEMT,Transmitter Empty bit." "0,1"
bitfld.long 0x0 5. "THRE,Transmit Holding Register Empty bit." "0,1"
newline
bitfld.long 0x0 4. "BI,Break Interrupt bit." "0,1"
bitfld.long 0x0 3. "FE,Framing Error bit." "0: no framing error,1: framing error"
newline
bitfld.long 0x0 2. "PE,Parity Error bit." "0: no parity error,1: parity error"
bitfld.long 0x0 1. "OE,Overrun error bit." "0: no overrun error,1: overrun error"
newline
bitfld.long 0x0 0. "DR,Data Ready bit." "0: no data ready,1: data ready"
line.long 0x4 "MSR,Modem Status Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_MSR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x4 7. "DCD,Data Carrier Detect." "0: dcd_n input is de-asserted,1: dcd_n input is asserted"
newline
bitfld.long 0x4 6. "RI,Ring Indicator." "0: ri_n input is de-asserted,1: ri_n input is asserted"
bitfld.long 0x4 5. "DSR,Data Set Ready." "0: dsr_n input is de-asserted,1: dsr_n input is asserted"
newline
bitfld.long 0x4 4. "CTS,Clear to Send." "0: cts_n input is de-asserted,1: cts_n input is asserted"
bitfld.long 0x4 3. "DDCD,Delta Data Carrier Detect." "0: no change on dcd_n since last read of MSR,1: change on dcd_n since last read of MSR"
newline
bitfld.long 0x4 2. "TERI,Trailing Edge of Ring Indicator." "0: no change on ri_n since last read of MSR,1: change on ri_n since last read of MSR"
bitfld.long 0x4 1. "DDSR,Delta Data Set Ready." "0: no change on dsr_n since last read of MSR,1: change on dsr_n since last read of MSR"
newline
bitfld.long 0x4 0. "DCTS,Delta Clear to Send." "0: no change on cts_n since last read of MSR,1: change on cts_n since last read of MSR"
group.long 0x1C++0x3
line.long 0x0 "SCR,Scratchpad Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SCR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "scr,This register is for programmers to use as a temporary storage space. It has no"
rgroup.long 0x30++0x3
line.long 0x0 "SRBR0,Shadow Receive Buffer Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR0_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr0,Shadow Receive Buffer Register 0:"
group.long 0x30++0x3
line.long 0x0 "STHR0,Shadow Transmit Holding Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR0_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr0,Shadow Transmit Holding Register 0:"
rgroup.long 0x34++0x3
line.long 0x0 "SRBR1,Shadow Receive Buffer Register 1"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR1_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr1,See srbr0 description"
group.long 0x34++0x3
line.long 0x0 "STHR1,Shadow Transmit Holding Register 1"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR1_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr1,See sthr0 description."
rgroup.long 0x38++0x3
line.long 0x0 "SRBR2,Shadow Receive Buffer Register 2"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR2_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr2,See srbr0 description"
group.long 0x38++0x3
line.long 0x0 "STHR2,Shadow Transmit Holding Register 2"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR2_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr2,See sthr0 description."
rgroup.long 0x3C++0x3
line.long 0x0 "SRBR3,Shadow Receive Buffer Register 3"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR3_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr3,See srbr0 description"
group.long 0x3C++0x3
line.long 0x0 "STHR3,Shadow Transmit Holding Register 3"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR3_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr3,See sthr0 description."
rgroup.long 0x40++0x3
line.long 0x0 "SRBR4,Shadow Receive Buffer Register 4"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR4_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr4,See srbr0 description"
group.long 0x40++0x3
line.long 0x0 "STHR4,Shadow Transmit Holding Register 4"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR4_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr4,See sthr0 description."
rgroup.long 0x44++0x3
line.long 0x0 "SRBR5,Shadow Receive Buffer Register 5"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR5_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr5,See srbr0 description"
group.long 0x44++0x3
line.long 0x0 "STHR5,Shadow Transmit Holding Register 5"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR5_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr5,See sthr0 description."
rgroup.long 0x48++0x3
line.long 0x0 "SRBR6,Shadow Receive Buffer Register 6"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR6_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr6,See srbr0 description"
group.long 0x48++0x3
line.long 0x0 "STHR6,Shadow Transmit Holding Register 6"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR6_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr6,See sthr0 description."
rgroup.long 0x4C++0x3
line.long 0x0 "SRBR7,Shadow Receive Buffer Register 7"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR7_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr7,See srbr0 description"
group.long 0x4C++0x3
line.long 0x0 "STHR7,Shadow Transmit Holding Register 7"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR7_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr7,See sthr0 description."
rgroup.long 0x50++0x3
line.long 0x0 "SRBR8,Shadow Receive Buffer Register 8"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR8_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr8,See srbr0 description"
group.long 0x50++0x3
line.long 0x0 "STHR8,Shadow Transmit Holding Register 8"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR8_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr8,See sthr0 description."
rgroup.long 0x54++0x3
line.long 0x0 "SRBR9,Shadow Receive Buffer Register 9"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR9_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr9,See srbr0 description"
group.long 0x54++0x3
line.long 0x0 "STHR9,Shadow Transmit Holding Register 9"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR9_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr9,See sthr0 description."
rgroup.long 0x58++0x3
line.long 0x0 "SRBR10,Shadow Receive Buffer Register 10"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR10_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr10,See srbr0 description"
group.long 0x58++0x3
line.long 0x0 "STHR10,Shadow Transmit Holding Register 10"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR10_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr10,See sthr0 description."
rgroup.long 0x5C++0x3
line.long 0x0 "SRBR11,Shadow Receive Buffer Register 11"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR11_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr11,See srbr0 description"
group.long 0x5C++0x3
line.long 0x0 "STHR11,Shadow Transmit Holding Register 11"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR11_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr11,See sthr0 description."
rgroup.long 0x60++0x3
line.long 0x0 "SRBR12,Shadow Receive Buffer Register 12"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR12_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr12,See srbr0 description"
group.long 0x60++0x3
line.long 0x0 "STHR12,Shadow Transmit Holding Register 12"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR12_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr12,See sthr0 description."
rgroup.long 0x64++0x3
line.long 0x0 "SRBR13,Shadow Receive Buffer Register 13"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR13_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr13,See srbr0 description"
group.long 0x64++0x3
line.long 0x0 "STHR13,Shadow Transmit Holding Register 13"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR13_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr13,See sthr0 description."
rgroup.long 0x68++0x3
line.long 0x0 "SRBR14,Shadow Receive Buffer Register 14"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR14_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr14,See srbr0 description"
group.long 0x68++0x3
line.long 0x0 "STHR14,Shadow Transmit Holding Register 14"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR14_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr14,See sthr0 description."
rgroup.long 0x6C++0x3
line.long 0x0 "SRBR15,Shadow Receive Buffer Register 15"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR15_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr15,See srbr0 description"
group.long 0x6C++0x7
line.long 0x0 "STHR15,Shadow Transmit Holding Register 15"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR15_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr15,See sthr0 description."
line.long 0x4 "FAR,FIFO Access Register"
hexmask.long 0x4 1.--31. 1. "RSVD_FAR_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x4 0. "far,Writes will have no effect when FIFO_ACCESS == No  always readable. This register" "0: FIFO access mode disabled,1: FIFO access mode enabled"
rgroup.long 0x74++0x3
line.long 0x0 "TFR,Transmit FIFO Read"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_TFR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "tfr,Transmit FIFO Read."
group.long 0x78++0x3
line.long 0x0 "RFW,Receive FIFO Write"
hexmask.long.tbyte 0x0 10.--31. 1. "RSVD_RFW_31to10,Reserved bits [31:10] - Read Only"
bitfld.long 0x0 9. "RFFE,Receive FIFO Framing Error." "0,1"
newline
bitfld.long 0x0 8. "RFPE,Receive FIFO Parity Error." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "RFWD,Receive FIFO Write Data."
rgroup.long 0x7C++0xB
line.long 0x0 "USR,UART Status register."
hexmask.long 0x0 5.--31. 1. "RSVD_USR_31to5,Reserved bits [31:5] - Read Only"
bitfld.long 0x0 4. "RFF,Receive FIFO Full." "0: Receive FIFO not full,1: Receive FIFO Full"
newline
bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
bitfld.long 0x0 2. "TFE,Transmit FIFO Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
newline
bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
bitfld.long 0x0 0. "RSVD_BUSY,UART Busy." "0,1"
line.long 0x4 "TFL,Transmit FIFO Level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_TFL_31toADDR_WIDTH,Reserved bits: 31 downto addr bus width + 1 - Read Only"
hexmask.long.byte 0x4 0.--7. 1. "tfl,Transmit FIFO Level."
line.long 0x8 "RFL,Receive FIFO Level."
hexmask.long.tbyte 0x8 8.--31. 1. "RSVD_RFL_31toADDR_WIDTH,Reserved bits: 31 downnto addr bus width + 1 - Read Only"
hexmask.long.byte 0x8 0.--7. 1. "rfl,Receive FIFO Level."
group.long 0x88++0x23
line.long 0x0 "SRR,Software Reset Register."
hexmask.long 0x0 3.--31. 1. "RSVD_SRR_31to3,Reserved bits [31:3] - Read Only"
bitfld.long 0x0 2. "XFR,XMIT FIFO Reset." "0,1"
newline
bitfld.long 0x0 1. "RFR,RCVR FIFO Reset." "0,1"
bitfld.long 0x0 0. "UR,UART Reset." "0,1"
line.long 0x4 "SRTS,Shadow Request to Send."
hexmask.long 0x4 1.--31. 1. "RSVD_SRTS_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x4 0. "srts,Shadow Request to Send." "0,1"
line.long 0x8 "SBCR,Shadow Break Control Register."
hexmask.long 0x8 1.--31. 1. "RSVD_SBCR_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x8 0. "sbcb,Shadow Break Control Bit." "0,1"
line.long 0xC "SDMAM,Shadow DMA Mode."
hexmask.long 0xC 1.--31. 1. "RSVD_SDMAM_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0xC 0. "sdmam,Shadow DMA Mode." "0: mode 0,1: mode 1"
line.long 0x10 "SFE,Shadow FIFO Enable"
hexmask.long 0x10 1.--31. 1. "RSVD_SFE_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x10 0. "sfe,Shadow FIFO Enable." "0,1"
line.long 0x14 "SRT,Shadow RCVR Trigger"
hexmask.long 0x14 2.--31. 1. "RSVD_SRT_31to2,Reserved bits [31:2] - Read Only"
bitfld.long 0x14 0.--1. "srt,Shadow RCVR Trigger." "0: 1 character in the FIFO,1: FIFO 1/4 full,?,?"
line.long 0x18 "STET,Shadow TX Empty Trigger"
hexmask.long 0x18 2.--31. 1. "RSVD_STET_31to2,Reserved bits [31:2] - Read Only"
bitfld.long 0x18 0.--1. "stet,Shadow TX Empty Trigger." "0: FIFO empty,1: 2 characters in the FIFO,?,?"
line.long 0x1C "HTX,Halt TX"
hexmask.long 0x1C 1.--31. 1. "RSVD_HTX_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x1C 0. "htx,Halt TX." "0: Halt TX disabled,1: Halt TX enabled"
line.long 0x20 "DMASA,DMA Software Acknowledge"
hexmask.long 0x20 1.--31. 1. "RSVD_DMASA_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x20 0. "dmasa,DMA Software Acknowledge." "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "CPR,Component Parameter Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_CPR_31to24,Reserved bits [31:24] - Read Only"
hexmask.long.byte 0x0 16.--23. 1. "FIFO_MODE,Encoding of FIFO_MODE configuration parameter value.DW_apb_uart.ralf"
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bitfld.long 0x0 14.--15. "RSVD_CPR_15to14,Reserved bits [15:14] - Read Only" "0,1,2,3"
bitfld.long 0x0 13. "DMA_EXTRA,Encoding of DMA_EXTRA configuration parameter value." "0: FALSE,1: TRUE"
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bitfld.long 0x0 12. "UART_ADD_ENCODED_PARAMS,Encoding of UART_ADD_ENCODED_PARAMS configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 11. "SHADOW,Encoding of SHADOW configuration parameter value." "0: FALSE,1: TRUE"
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bitfld.long 0x0 10. "FIFO_STAT,Encoding of FIFO_STAT configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 9. "FIFO_ACCESS,Encoding of FIFO_ACCESS configuration parameter value." "0: FALSE,1: TRUE"
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bitfld.long 0x0 8. "ADDITIONAL_FEAT,Encoding of ADDITIONAL_FEATURES configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 7. "SIR_LP_MODE,Encoding of SIR_LP_MODE configuration parameter value." "0: FALSE,1: TRUE"
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bitfld.long 0x0 6. "SIR_MODE,Encoding of SIR_MODE configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 5. "THRE_MODE,Encoding of THRE_MODE configuration parameter value." "0: FALSE,1: TRUE"
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bitfld.long 0x0 4. "AFCE_MODE,Encoding of AFCE_MODE configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 2.--3. "RSVD_CPR_3to2,Reserved bits [3:2] - Read Only" "0,1,2,3"
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bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,Encoding of APB_DATA_WIDTH configuration parameter value." "0: 8 bits,1: 16 bits,?,?"
line.long 0x4 "UCV,Component Version"
hexmask.long 0x4 0.--31. 1. "UART_Component_Version,ASCII value for each number in the version  followed by *."
line.long 0x8 "CTR,Component Type Register"
hexmask.long 0x8 0.--31. 1. "Peripheral_ID,This register contains the peripherals identification code."
tree.end
tree.end
tree "SDMMC (SD/MMC Module)"
base ad:0xFF808000
group.long 0x0++0xB
line.long 0x0 "CTRL,Control register"
bitfld.long 0x0 25. "USE_INTERNAL_DMAC,Present only for the Internal DMAC configuration; else  it is reserved." "0,1"
bitfld.long 0x0 24. "ENABLE_OD_PULLUP,External open-drain pullup" "0,1"
hexmask.long.byte 0x0 20.--23. 1. "CARD_VOLTAGE_B,Card regulator-B voltage setting; output to card_volt_b port."
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hexmask.long.byte 0x0 16.--19. 1. "CARD_VOLTAGE_A,Card regulator-A voltage setting; output to card_volt_a port."
bitfld.long 0x0 11. "CEATA_DEVICE_INTERRUPT_STATUS,0-Interrupts not enabled in CE-ATA device" "0,1"
bitfld.long 0x0 10. "SEND_AUTO_STOP_CCSD,0-Clear bit if DWC_mobile_storage does not reset the bit" "0,1"
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bitfld.long 0x0 9. "SEND_CCSD,0-Clear this bit if DWC_mobile_storage does not reset the bit" "0,1"
bitfld.long 0x0 8. "ABORT_READ_DATA,0-No change" "0,1"
bitfld.long 0x0 7. "SEND_IRQ_RESPONSE,0-No Change in this" "0,1"
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bitfld.long 0x0 6. "READ_WAIT,0-Clear read wait" "0,1"
bitfld.long 0x0 5. "DMA_ENABLE,0-Disable DMA transfer mode" "0,1"
bitfld.long 0x0 4. "INT_ENABLE,Global interrupt enable/disable bit:" "0,1"
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bitfld.long 0x0 2. "DMA_RESET,0-No change" "0,1"
bitfld.long 0x0 1. "FIFO_RESET,0-No change" "0,1"
bitfld.long 0x0 0. "CONTROLLER_RESET,0-No change" "0,1"
line.long 0x4 "PWREN,Power Enable Register"
bitfld.long 0x4 0. "POWER_ENABLE_0,Power on/off switch for up to 16 cards; for example  bit[0] controls card 0.Once power is turned on  firmware should wait for regulator/switch ramp-up time before trying to initialize card." "0,1"
line.long 0x8 "CLKDIV,Clock Divider Register"
hexmask.long.byte 0x8 24.--31. 1. "CLK_DIVIDER3,Clock divider-3 value. Clock division is 2*n. For example  value of 0 means divide by 2*0 = 0 (no division  bypass)  a value of 1 means divide by 2*1 = 2  a value of 'ff' means divide by 2*255 = 510  and so on. In MMC-Ver3.3-only mode  bits.."
hexmask.long.byte 0x8 16.--23. 1. "CLK_DIVIDER2,Clock divider-2 value. Clock division is 2*n. For example  value of 0 means divide by 2*0 = 0 (no division  bypass)  value of 1 means divide by 2*1 = 2  value of 'ff' means divide by 2*255 = 510  and so on. In MMC-Ver3.3-only mode  bits not.."
hexmask.long.byte 0x8 8.--15. 1. "CLK_DIVIDER1,Clock divider-1 value. Clock division is 2*n. For example  value of 0 means divide by 2*0 = 0 (no division  bypass)  value of 1 means divide by 2*1 = 2  value of 'ff' means divide by 2*255 = 510  and so on. In MMC-Ver3.3-only mode  bits not.."
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hexmask.long.byte 0x8 0.--7. 1. "CLK_DIVIDER0,Clock divider-0 value. Clock division is 2*n. For example  value of 0 means divide by 2*0 = 0 (no division  bypass)  value of 1 means divide by 2*1 = 2  value of 'ff' means divide by 2*255 = 510  and so on."
rgroup.long 0xC++0x3
line.long 0x0 "CLKSRC,Clock Source Register"
bitfld.long 0x0 30.--31. "CARD15_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on.." "0,1,2,3"
bitfld.long 0x0 28.--29. "CARD14_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on.." "0,1,2,3"
bitfld.long 0x0 26.--27. "CARD13_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on.." "0,1,2,3"
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bitfld.long 0x0 24.--25. "CARD12_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on.." "0,1,2,3"
bitfld.long 0x0 22.--23. "CARD11_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on.." "0,1,2,3"
bitfld.long 0x0 20.--21. "CARD10_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on.." "0,1,2,3"
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bitfld.long 0x0 18.--19. "CARD9_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
bitfld.long 0x0 16.--17. "CARD8_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
bitfld.long 0x0 14.--15. "CARD7_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
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bitfld.long 0x0 12.--13. "CARD6_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
bitfld.long 0x0 10.--11. "CARD5_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
bitfld.long 0x0 8.--9. "CARD4_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
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bitfld.long 0x0 6.--7. "CARD3_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
bitfld.long 0x0 4.--5. "CARD2_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
bitfld.long 0x0 2.--3. "CARD1_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
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bitfld.long 0x0 0.--1. "CARD0_CLK_SOURCE,Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example  bits[1:0] assigned for card-0  which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins  depending on bit.." "0,1,2,3"
group.long 0x10++0x1F
line.long 0x0 "CLKENA,Clock Enable Register"
bitfld.long 0x0 16. "CCLK_LOW_POWER_0,Low-power control for up to 16 SD card clocks and one MMC card clock supported." "0,1"
bitfld.long 0x0 0. "CCLK_ENABLE_0,Clock-enable control for up to 16 SD card clocks and one MMC card clock supported." "0,1"
line.long 0x4 "TMOUT,Timeout Register"
hexmask.long.tbyte 0x4 8.--31. 1. "DATA_TIMEOUT,Value for card Data Read Timeout; same value also used for Data"
hexmask.long.byte 0x4 0.--7. 1. "RESPONSE_TIMEOUT,Response timeout value."
line.long 0x8 "CTYPE,Card Type Register"
bitfld.long 0x8 16. "CARD0_WIDTH1,One bit per card indicates if card is 8-bit:" "0,1"
bitfld.long 0x8 0. "CARD0_WIDTH2,One bit per card indicates if card is 1-bit or 4-bit:" "0,1"
line.long 0xC "BLKSIZ,Block Size Register"
hexmask.long.word 0xC 0.--15. 1. "BLOCK_SIZE,Block size"
line.long 0x10 "BYTCNT,Byte Count Register"
hexmask.long 0x10 0.--31. 1. "BYTE_COUNT,Number of bytes to be transferred; should be integer multiple of Block Size for block transfers."
line.long 0x14 "INTMASK,Interrupt Mask Register"
bitfld.long 0x14 31. "SDIO_INT_MASK_CARD15,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 30. "SDIO_INT_MASK_CARD14,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 29. "SDIO_INT_MASK_CARD13,Mask SDIO interrupts" "0,1"
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bitfld.long 0x14 28. "SDIO_INT_MASK_CARD12,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 27. "SDIO_INT_MASK_CARD11,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 26. "SDIO_INT_MASK_CARD10,Mask SDIO interrupts" "0,1"
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bitfld.long 0x14 25. "SDIO_INT_MASK_CARD9,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 24. "SDIO_INT_MASK_CARD8,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 23. "SDIO_INT_MASK_CARD7,Mask SDIO interrupts" "0,1"
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bitfld.long 0x14 22. "SDIO_INT_MASK_CARD6,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 21. "SDIO_INT_MASK_CARD5,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 20. "SDIO_INT_MASK_CARD4,Mask SDIO interrupts" "0,1"
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bitfld.long 0x14 19. "SDIO_INT_MASK_CARD3,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 18. "SDIO_INT_MASK_CARD2,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 17. "SDIO_INT_MASK_CARD1,Mask SDIO interrupts" "0,1"
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bitfld.long 0x14 16. "SDIO_INT_MASK_CARD0,Mask SDIO interrupts" "0,1"
bitfld.long 0x14 15. "EBE_INT_MASK,End-bit error (read)/Write no CRC (EBE) interrupt enable." "0,1"
bitfld.long 0x14 14. "ACD_INT_MASK,Auto command done (ACD) interrupt enable." "0,1"
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bitfld.long 0x14 13. "SBE_BCI_INT_MASK,Start Bit Error(SBE)/Busy Complete Interrupt (BCI) interrupt enable." "0,1"
bitfld.long 0x14 12. "HLE_INT_MASK,Hardware locked write error (HLE) interrupt enable." "0,1"
bitfld.long 0x14 11. "FRUN_INT_MASK,FIFO underrun/overrun error (FRUN) interrupt enable." "0,1"
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bitfld.long 0x14 10. "HTO_INT_MASK,Data starvation-by-host timeout (HTO) /Volt_switch_int interrupt enable." "0,1"
bitfld.long 0x14 9. "DRTO_INT_MASK,Data read timeout (DRTO) interrupt enable." "0,1"
bitfld.long 0x14 8. "RTO_INT_MASK,Response timeout (RTO) interrupt enable." "0,1"
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bitfld.long 0x14 7. "DCRC_INT_MASK,Data CRC error (DCRC) interrupt enable." "0,1"
bitfld.long 0x14 6. "RCRC_INT_MASK,Response CRC error (RCRC) interrupt enable." "0,1"
bitfld.long 0x14 5. "RXDR_INT_MASK,Receive FIFO data request (RXDR) interrupt enable." "0,1"
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bitfld.long 0x14 4. "TXDR_INT_MASK,Transmit FIFO data request (TXDR) interrupt enable." "0,1"
bitfld.long 0x14 3. "DTO_INT_MASK,Data transfer over (DTO) interrupt enable." "0,1"
bitfld.long 0x14 2. "CMD_INT_MASK,Command done (CD) interrupt enable" "0,1"
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bitfld.long 0x14 1. "RE_INT_MASK,Response error (RE) interrupt enable." "0,1"
bitfld.long 0x14 0. "CD_INT_MASK,Card detect (CD) interrupt enable." "0,1"
line.long 0x18 "CMDARG,Command Argument Register"
hexmask.long 0x18 0.--31. 1. "CMD_ARG,Value indicates command argument to be passed to card"
line.long 0x1C "CMD,Command Register"
bitfld.long 0x1C 31. "START_CMD,Start command. Once command is taken by CIU  bit is cleared." "0,1"
bitfld.long 0x1C 29. "USE_HOLD_REG,Use Hold Register" "0,1"
bitfld.long 0x1C 28. "VOLT_SWITCH,Voltage switch bit" "0,1"
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bitfld.long 0x1C 27. "BOOT_MODE,Boot Mode" "0,1"
bitfld.long 0x1C 26. "DISABLE_BOOT,Disable Boot. When software sets this bit along with start_cmd  CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together." "0,1"
bitfld.long 0x1C 25. "EXPECT_BOOT_ACK,Expect Boot Acknowledge. When Software sets this bit along with" "0,1"
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bitfld.long 0x1C 24. "ENABLE_BOOT,Enable Boot this bit should be set only for mandatory boot mode." "0,1"
bitfld.long 0x1C 23. "CCS_EXPECTED,0-Interrupts are not enabled in CE-ATA device (nIEN = 1 in" "0,1"
bitfld.long 0x1C 22. "READ_CEATA_DEVICE,0-Host is not performing read access (RW_REG or RW_BLK)" "0,1"
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bitfld.long 0x1C 21. "UPDATE_CLOCK_REGISTERS_ONLY,0-Normal command sequence" "0,1"
hexmask.long.byte 0x1C 16.--20. 1. "CARD_NUMBER,Card number in use. Represents physical slot number of card being"
bitfld.long 0x1C 15. "SEND_INITIALIZATION,0-Do not send initialization sequence (80 clocks of 1) before" "0,1"
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bitfld.long 0x1C 14. "STOP_ABORT_CMD,0-Neither stop nor abort command to stop current data transfer" "0,1"
bitfld.long 0x1C 13. "WAIT_PRVDATA_COMPLETE,0-Send command at once  even if previous data transfer has not" "0,1"
bitfld.long 0x1C 12. "SEND_AUTO_STOP,0-No stop command sent at end of data transfer" "0,1"
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bitfld.long 0x1C 11. "TRANSFER_MODE,0-Block data transfer command" "0,1"
bitfld.long 0x1C 10. "READ_WRITE,0-Read from card" "0,1"
bitfld.long 0x1C 9. "DATA_EXPECTED,0-No data transfer expected (read/write)" "0,1"
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bitfld.long 0x1C 8. "CHECK_RESPONSE_CRC,0-Do not check response CRC" "0,1"
bitfld.long 0x1C 7. "RESPONSE_LENGTH,0-Short response expected from card" "0,1"
bitfld.long 0x1C 6. "RESPONSE_EXPECT,0-No response expected from card" "0,1"
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hexmask.long.byte 0x1C 0.--5. 1. "CMD_INDEX,Command index"
rgroup.long 0x30++0x13
line.long 0x0 "RESP0,Response Register 0"
hexmask.long 0x0 0.--31. 1. "RESPONSE0,Bit[31:0] of response"
line.long 0x4 "RESP1,Response Register 1"
hexmask.long 0x4 0.--31. 1. "RESPONSE1,Register represents bit[63:32] of long response."
line.long 0x8 "RESP2,Response Register 2"
hexmask.long 0x8 0.--31. 1. "RESPONSE2,Bit[95:64] of long response"
line.long 0xC "RESP3,Response Register 3"
hexmask.long 0xC 0.--31. 1. "RESPONSE3,Bit[127:96] of long response"
line.long 0x10 "MINTSTS,Name: Masked Interrupt Status Register"
bitfld.long 0x10 31. "SDIO_INTERRUPT_CARD15,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 30. "SDIO_INTERRUPT_CARD14,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 29. "SDIO_INTERRUPT_CARD13,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
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bitfld.long 0x10 28. "SDIO_INTERRUPT_CARD12,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 27. "SDIO_INTERRUPT_CARD11,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 26. "SDIO_INTERRUPT_CARD10,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
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bitfld.long 0x10 25. "SDIO_INTERRUPT_CARD9,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 24. "SDIO_INTERRUPT_CARD8,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 23. "SDIO_INTERRUPT_CARD7,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
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bitfld.long 0x10 22. "SDIO_INTERRUPT_CARD6,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 21. "SDIO_INTERRUPT_CARD5,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 20. "SDIO_INTERRUPT_CARD4,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
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bitfld.long 0x10 19. "SDIO_INTERRUPT_CARD3,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 18. "SDIO_INTERRUPT_CARD2,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 17. "SDIO_INTERRUPT_CARD1,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
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bitfld.long 0x10 16. "SDIO_INTERRUPT_CARD0,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1.." "0,1"
bitfld.long 0x10 15. "END_BIT_ERROR_INTERRUPT,Interrupt enabled only if corresponding bit in interrupt mask register is set." "0,1"
bitfld.long 0x10 14. "AUTO_COMMAND_DONE_INTERRUPT,bit 14 Auto command done (ACD)" "0,1"
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bitfld.long 0x10 13. "BUSY_COMPLETE_INTERRUPT_INTERRUPT,bit 13 Start Bit Error(SBE)/Busy Complete Interrupt (BCI)" "0,1"
bitfld.long 0x10 12. "HARDWARE_LOCKED_WRITE_INTERRUPT,bit 12 Hardware locked write error (HLE)" "0,1"
bitfld.long 0x10 11. "FIFO_UNDER_OVER_RUN_INTERRUPT,bit 11 FIFO underrun/overrun error (FRUN)" "0,1"
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bitfld.long 0x10 10. "HOST_TIMEOUT_INTERRUPT,bit 10 Data starvation by host timeout (HTO)/Volt_switch_int" "0,1"
bitfld.long 0x10 9. "DATA_READ_TIMEOUT_INTERRUPT,bit 9 Data read timeout (DRTO)" "0,1"
bitfld.long 0x10 8. "RESPONSE_TIMEOUT_INTERRUPT,bit 8 Response timeout (RTO)" "0,1"
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bitfld.long 0x10 7. "DATA_CRC_ERROR_INTERRUPT,bit 7 Data CRC error (DCRC)" "0,1"
bitfld.long 0x10 6. "RESPONSE_CRC_ERROR_INTERRUPT,bit 6 Response CRC error (RCRC)" "0,1"
bitfld.long 0x10 5. "RECEIVE_FIFO_DATA_REQUEST_INTERRUPT,bit 5 Receive FIFO data request (RXDR)" "0,1"
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bitfld.long 0x10 4. "TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT,bit 4 Transmit FIFO data request (TXDR)" "0,1"
bitfld.long 0x10 3. "DATA_TRANSFER_OVER_INTERRUPT,bit 3 Data transfer over (DTO)" "0,1"
bitfld.long 0x10 2. "COMMAND_DONE_INTERRUPT,bit 2 Command done (CD)" "0,1"
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bitfld.long 0x10 1. "RESPONSE_ERROR_INTERRUPT,bit 1 Response error (RE)" "0,1"
bitfld.long 0x10 0. "CARD_DETECT_INTERRUPT,bit 0 Card detect (CD)" "0,1"
group.long 0x44++0x3
line.long 0x0 "RINTSTS,Name: Raw Interrupt Status Register"
eventfld.long 0x0 31. "SDIO_INTERRUPT_CARD15,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 30. "SDIO_INTERRUPT_CARD14,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 29. "SDIO_INTERRUPT_CARD13,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
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eventfld.long 0x0 28. "SDIO_INTERRUPT_CARD12,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 27. "SDIO_INTERRUPT_CARD11,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 26. "SDIO_INTERRUPT_CARD10,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
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eventfld.long 0x0 25. "SDIO_INTERRUPT_CARD9,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 24. "SDIO_INTERRUPT_CARD8,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 23. "SDIO_INTERRUPT_CARD7,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
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eventfld.long 0x0 22. "SDIO_INTERRUPT_CARD6,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 21. "SDIO_INTERRUPT_CARD5,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 20. "SDIO_INTERRUPT_CARD4,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
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eventfld.long 0x0 19. "SDIO_INTERRUPT_CARD3,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 18. "SDIO_INTERRUPT_CARD2,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 17. "SDIO_INTERRUPT_CARD1,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
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eventfld.long 0x0 16. "SDIO_INTERRUPT_CARD0,Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15]  and bit[16] is for Card[0]. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact." "0,1"
eventfld.long 0x0 15. "END_BIT_ERROR_STATUS,STATUS ." "0,1"
eventfld.long 0x0 14. "AUTO_COMMAND_DONE_STATUS,bit 14 Auto command done (ACD)" "0,1"
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eventfld.long 0x0 13. "BUSY_COMPLETE_STATUS,bit 13 Start Bit Error(SBE)/Busy Complete STATUS (BCI)" "0,1"
eventfld.long 0x0 12. "HARDWARE_LOCKED_WRITE_STATUS,bit 12 Hardware locked write error (HLE)" "0,1"
eventfld.long 0x0 11. "FIFO_UNDER_OVER_RUN_STATUS,bit 11 FIFO underrun/overrun error (FRUN)" "0,1"
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eventfld.long 0x0 10. "HOST_TIMEOUT_STATUS,bit 10 Data starvation by host timeout (HTO)/Volt_switch_int" "0,1"
eventfld.long 0x0 9. "DATA_READ_TIMEOUT_STATUS,bit 9 Data read timeout (DRTO)" "0,1"
eventfld.long 0x0 8. "RESPONSE_TIMEOUT_STATUS,bit 8 Response timeout (RTO)" "0,1"
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eventfld.long 0x0 7. "DATA_CRC_ERROR_STATUS,bit 7 Data CRC error (DCRC)" "0,1"
eventfld.long 0x0 6. "RESPONSE_CRC_ERROR_STATUS,bit 6 Response CRC error (RCRC)" "0,1"
eventfld.long 0x0 5. "RECEIVE_FIFO_DATA_REQUEST_STATUS,bit 5 Receive FIFO data request (RXDR)" "0,1"
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eventfld.long 0x0 4. "TRANSMIT_RECEIVE_FIFO_DATA_STATUS,bit 4 Transmit FIFO data request (TXDR)" "0,1"
eventfld.long 0x0 3. "DATA_TRANSFER_OVER_STATUS,bit 3 Data transfer over (DTO)" "0,1"
eventfld.long 0x0 2. "COMMAND_DONE_STATUS,bit 2 Command done (CD)" "0,1"
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eventfld.long 0x0 1. "RESPONSE_ERROR_STATUS,bit 1 Response error (RE)" "0,1"
eventfld.long 0x0 0. "CARD_DETECT_STATUS,bit 0 Card detect (CD)" "0,1"
rgroup.long 0x48++0x3
line.long 0x0 "STATUS,Name: Status Register"
bitfld.long 0x0 31. "DMA_REQ,DMA request signal state; either dw_dma_req or ge_dma_req " "0,1"
bitfld.long 0x0 30. "DMA_ACK,DMA acknowledge signal state; either dw_dma_ack or" "0,1"
hexmask.long.word 0x0 17.--29. 1. "FIFO_COUNT,FIFO count Number of filled locations in FIFO"
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hexmask.long.byte 0x0 11.--16. 1. "RESPONSE_INDEX,Index of previous response  including any auto-stop sent by core"
bitfld.long 0x0 10. "DATA_STATE_MC_BUSY,Data transmit or receive state-machine is busy" "0,1"
bitfld.long 0x0 9. "DATA_BUSY,Inverted version of raw selected card_data[0]" "0,1"
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bitfld.long 0x0 8. "DATA_3_STATUS,Raw selected card_data[3]; checks whether card is present" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "COMMAND_FSM_STATES,Command FSM states:"
bitfld.long 0x0 3. "FIFO_FULL,FIFO is full status" "0,1"
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bitfld.long 0x0 2. "FIFO_EMPTY,FIFO is empty status" "0,1"
bitfld.long 0x0 1. "FIFO_TX_WATERMARK,FIFO reached Transmit watermark level; not qualified with data" "0,1"
bitfld.long 0x0 0. "FIFO_RX_WATERMARK,FIFO reached Receive watermark level; not qualified with data" "0,1"
group.long 0x4C++0x3
line.long 0x0 "FIFOTH,Name: FIFO Threshold Watermark Register"
bitfld.long 0x0 28.--30. "DW_DMA_Multiple_Transaction_Size,Burst size of multiple transaction; should be programmed same as" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0 16.--27. 1. "RX_WMark,FIFO threshold watermark level when receiving data to card."
hexmask.long.word 0x0 0.--11. 1. "TX_WMark,FIFO threshold watermark level when transmitting data to card."
rgroup.long 0x50++0x7
line.long 0x0 "CDETECT,Name: Card Detect Register"
bitfld.long 0x0 0. "CARD0_DETECT_N,Value on card_detect_n input ports (1 bit per card); read-only bits.0 represents presence of card. Only NUM_CARDS number of bits are implemented." "0,1"
line.long 0x4 "WRTPRT,Name: Write Protect Register"
bitfld.long 0x4 0. "WRITE_PROTECT_0,Value on card_write_prt input ports (1 bit per card)." "0,1"
group.long 0x58++0x3
line.long 0x0 "GPIO,Name: General Purpose Input/Output Register"
hexmask.long.word 0x0 8.--23. 1. "GPO,Value needed to be driven to gpo pins; this portion of register is read/write. Valid only when AREA_OPTIMIZED parameter is 0."
hexmask.long.byte 0x0 0.--7. 1. "GPI,Value on gpi input ports; this portion of register is read-only. Valid only when AREA_OPTIMIZED parameter is 0."
rgroup.long 0x5C++0x7
line.long 0x0 "TCBCNT,Name: Transferred CIU Card Byte Count Register"
hexmask.long 0x0 0.--31. 1. "TRANS_CARD_BYTE_COUNT,Number of bytes transferred by CIU unit to card."
line.long 0x4 "TBBCNT,Name: Transferred Host to BIU-FIFO Byte Count Register"
hexmask.long 0x4 0.--31. 1. "TRANS_FIFO_BYTE_COUNT,Number of bytes transferred between Host/DMA memory and BIU FIFO."
group.long 0x64++0x7
line.long 0x0 "DEBNCE,Name: Debounce Count Register"
hexmask.long.tbyte 0x0 0.--23. 1. "DEBOUNCE_COUNT,Number of host clocks (clk) used by debounce filter logic; typical"
line.long 0x4 "USRID,Name: User ID Register"
hexmask.long 0x4 0.--31. 1. "USR_ID,User identification register; value set by user. Default reset value can be picked by user while configuring core before synthesis."
rgroup.long 0x6C++0x7
line.long 0x0 "VERID,Name: Version ID Register"
hexmask.long 0x0 0.--31. 1. "VER_ID,Synopsys version identification register; register value is hard-wired.Can be read by firmware to support different versions of core."
line.long 0x4 "HCON,Name: Hardware Configuration Register"
bitfld.long 0x4 27. "ADDR_CONFIG,Address configuration" "0,1"
bitfld.long 0x4 26. "AREA_OPT,Area Optimization" "0,1"
bitfld.long 0x4 24.--25. "NUM_CLK_DIC,NUM_CLK_DIVIDER - 1" "0,1,2,3"
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bitfld.long 0x4 23. "FALSE_PATH,Set Clock False Path" "0,1"
bitfld.long 0x4 22. "HOLD_REG,Implement HOLD register" "0,1"
bitfld.long 0x4 21. "FIFO_RAM_IN,FIFO Ram Inside" "0,1"
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bitfld.long 0x4 18.--20. "GE_DMA_DATA_WIDTH,Generic DMA Data Width" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 16.--17. "DMA_IF,DMA Interface" "0,1,2,3"
hexmask.long.byte 0x4 10.--15. 1. "H_ADDR_WIDTH,H Address Width"
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bitfld.long 0x4 7.--9. "H_DATA_WIDTH,H Data Width" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 6. "BUS_TYPE,Bus type" "0,1"
hexmask.long.byte 0x4 1.--5. 1. "NUM_CARD,NUM_CARD - 1"
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bitfld.long 0x4 0. "CARD_TYPE,Card type" "0,1"
group.long 0x74++0x7
line.long 0x0 "UHS_REG,Name: UHS-1 Register"
bitfld.long 0x0 31. "DDR_REG_15,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 30. "DDR_REG_14,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 29. "DDR_REG_13,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
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bitfld.long 0x0 28. "DDR_REG_12,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 27. "DDR_REG_11,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 26. "DDR_REG_10,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
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bitfld.long 0x0 25. "DDR_REG_9,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 24. "DDR_REG_8,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 23. "DDR_REG_7,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
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bitfld.long 0x0 22. "DDR_REG_6,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 21. "DDR_REG_5,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 20. "DDR_REG_4,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
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bitfld.long 0x0 19. "DDR_REG_3,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 18. "DDR_REG_2,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 17. "DDR_REG_1,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
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bitfld.long 0x0 16. "DDR_REG_0,DDR mode. These bits indicate DDR mode of operation to the core for the data transfer." "0,1"
bitfld.long 0x0 15. "VOLT_REG_15,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 14. "VOLT_REG_14,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
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bitfld.long 0x0 13. "VOLT_REG_13,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 12. "VOLT_REG_12,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 11. "VOLT_REG_11,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
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bitfld.long 0x0 10. "VOLT_REG_10,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 9. "VOLT_REG_9,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 8. "VOLT_REG_8,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
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bitfld.long 0x0 7. "VOLT_REG_7,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 6. "VOLT_REG_6,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 5. "VOLT_REG_5,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
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bitfld.long 0x0 4. "VOLT_REG_4,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 3. "VOLT_REG_3,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 2. "VOLT_REG_2,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
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bitfld.long 0x0 1. "VOLT_REG_1,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
bitfld.long 0x0 0. "VOLT_REG_0,High Voltage mode. Determines the voltage fed to the buffers by an" "0,1"
line.long 0x4 "RST_n,Name: H/W Reset"
bitfld.long 0x4 0. "CARD0_RESET,Hardware reset." "0,1"
group.long 0x80++0x3
line.long 0x0 "BMOD,Name: Bus Mode Register"
rbitfld.long 0x0 8.--10. "PBL,Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible.." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 7. "DE,IDMAC Enable. When set  the IDMAC is enabled." "0,1"
hexmask.long.byte 0x0 2.--6. 1. "DSL,Descriptor Skip Length. Specifies the number of HWord/Word/Dword (depending on 16/32/64-bit bus) to skip between two unchained descriptors. This is applicable only for dual buffer structure."
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bitfld.long 0x0 1. "FB,Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set the AHB will use only SINGLE  INCR4  INCR8 or" "0,1"
bitfld.long 0x0 0. "SWR,Software Reset.When set the DMA Controller resets all its internal registers." "0,1"
wgroup.long 0x84++0x3
line.long 0x0 "PLDMND,Name: Poll Demand Register"
hexmask.long 0x0 0.--31. 1. "PD,Poll Demand. If the OWN bit of a descriptor is not set  the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal"
group.long 0x88++0xB
line.long 0x0 "DBADDR,Name: Descriptor List Base Address Register"
hexmask.long 0x0 0.--31. 1. "SDL,Start of Descriptor List. Contains the base address of the First Descriptor."
line.long 0x4 "IDSTS,Name: Internal DMAC Status Register"
hexmask.long.byte 0x4 13.--16. 1. "FSM,DMAC FSM present state."
rbitfld.long 0x4 10.--12. "EB,Error Bits. Indicates the type of error that caused a Bus Error." "0,1,2,3,4,5,6,7"
eventfld.long 0x4 9. "AIS,Abnormal Interrupt Summary. Logical OR of the following:" "0,1"
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eventfld.long 0x4 8. "NIS,Normal Interrupt Summary. Logical OR of the following:" "0,1"
eventfld.long 0x4 5. "CES,Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits:" "0,1"
eventfld.long 0x4 4. "DU,Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit." "0,1"
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eventfld.long 0x4 2. "FBE,Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set  the DMA disables all its bus accesses. Writing a 1 clears this bit." "0,1"
eventfld.long 0x4 1. "RI,Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit." "0,1"
eventfld.long 0x4 0. "TI,Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a '1' clears this bit." "0,1"
line.long 0x8 "IDINTEN,Name: Internal DMAC Interrupt Enable Register"
bitfld.long 0x8 9. "AI,Abnormal Interrupt Summary Enable. When set  an abnormal interrupt is enabled. This bit enables the following bits:" "0,1"
bitfld.long 0x8 8. "NI,Normal Interrupt Summary Enable. When set  a normal interrupt is enabled. When reset  a normal interrupt is disabled. This bit enables the following bits:" "0,1"
bitfld.long 0x8 5. "CES,Card Error summary Interrupt Enable. When set  it enables the Card Interrupt summary." "0,1"
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bitfld.long 0x8 4. "DU,Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable  the DU interrupt is enabled." "0,1"
bitfld.long 0x8 2. "FBE,Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable  the Fatal Bus Error Interrupt is enabled. When reset  Fatal Bus Error Enable Interrupt is disabled." "0,1"
bitfld.long 0x8 1. "RI,Receive Interrupt Enable. When set with Normal Interrupt Summary Enable  Receive Interrupt is enabled. When reset  Receive Interrupt is disabled." "0,1"
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bitfld.long 0x8 0. "TI,Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable  Transmit Interrupt is enabled. When reset  Transmit Interrupt is disabled." "0,1"
rgroup.long 0x94++0x7
line.long 0x0 "DSCADDR,Name: Current Host Descriptor Address Register"
hexmask.long 0x0 0.--31. 1. "HDA,Host Descriptor Address Pointer. Cleared on reset. Pointer updated by IDMAC during operation. This register points to the start address of the current descriptor read by the IDMAC."
line.long 0x4 "BUFADDR,Name: Current Buffer Descriptor Address Register"
hexmask.long 0x4 0.--31. 1. "HBA,Host Buffer Address Pointer. Cleared on Reset. Pointer updated by IDMAC during operation. This register points to the current Data Buffer Address being accessed by the IDMAC."
group.long 0x100++0x13
line.long 0x0 "CARDTHRCTL,Name: Card Threshold Control Register"
hexmask.long.word 0x0 16.--28. 1. "CARDRDTHRESHOLD,Card Read Threshold size; N depends on the FIFO size:"
rbitfld.long 0x0 2. "CARDWRTHREN,Card Write Threshold Enable" "0,1"
bitfld.long 0x0 1. "BUSY_CLR_INT_EN,Busy Clear Interrupt generation:" "0,1"
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bitfld.long 0x0 0. "CARDRDTHREN,Card Read Threshold Enable" "0,1"
line.long 0x4 "BACK_END_POWER_R,Name: Back End Power Register"
bitfld.long 0x4 15. "BACK_END_POWER_15,Back end power" "0,1"
bitfld.long 0x4 14. "BACK_END_POWER_14,Back end power" "0,1"
bitfld.long 0x4 13. "BACK_END_POWER_13,Back end power" "0,1"
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bitfld.long 0x4 12. "BACK_END_POWER_12,Back end power" "0,1"
bitfld.long 0x4 11. "BACK_END_POWER_11,Back end power" "0,1"
bitfld.long 0x4 10. "BACK_END_POWER_10,Back end power" "0,1"
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bitfld.long 0x4 9. "BACK_END_POWER_9,Back end power" "0,1"
bitfld.long 0x4 8. "BACK_END_POWER_8,Back end power" "0,1"
bitfld.long 0x4 7. "BACK_END_POWER_7,Back end power" "0,1"
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bitfld.long 0x4 6. "BACK_END_POWER_6,Back end power" "0,1"
bitfld.long 0x4 5. "BACK_END_POWER_5,Back end power" "0,1"
bitfld.long 0x4 4. "BACK_END_POWER_4,Back end power" "0,1"
newline
bitfld.long 0x4 3. "BACK_END_POWER_3,Back end power" "0,1"
bitfld.long 0x4 2. "BACK_END_POWER_2,Back end power" "0,1"
bitfld.long 0x4 1. "BACK_END_POWER_1,Back end power" "0,1"
newline
bitfld.long 0x4 0. "BACK_END_POWER_0,Back end power" "0,1"
line.long 0x8 "UHS_REG_EXT,Name: UHS Register Extention"
bitfld.long 0x8 30.--31. "EXT_CLK_MUX_CTRL,Input clock control for cclk_in. The MUX controlled by these bits exists outside DWC_mobile_storage IP." "0,1,2,3"
hexmask.long.byte 0x8 23.--29. 1. "CLK_DRV_PHASE_CTRL,Control for amount of phase shift on cclk_in_drv clock. Can choose three MSBs to control delay lines and four LSBs to control phase shift; alternatively  use only LSBs."
hexmask.long.byte 0x8 16.--22. 1. "CLK_SMPL_PHASE_CTRL,Control for amount of phase shift on cclk_in_sample clock. Can choose three MSBs to control delay lines and four LSBs to control phase shift; alternatively  use only LSBs."
newline
bitfld.long 0x8 15. "MMC_VOLT_REG_15,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 14. "MMC_VOLT_REG_14,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 13. "MMC_VOLT_REG_13,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
newline
bitfld.long 0x8 12. "MMC_VOLT_REG_12,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 11. "MMC_VOLT_REG_11,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 10. "MMC_VOLT_REG_10,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
newline
bitfld.long 0x8 9. "MMC_VOLT_REG_9,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 8. "MMC_VOLT_REG_8,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 7. "MMC_VOLT_REG_7,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
newline
bitfld.long 0x8 6. "MMC_VOLT_REG_6,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 5. "MMC_VOLT_REG_5,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 4. "MMC_VOLT_REG_4,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
newline
bitfld.long 0x8 3. "MMC_VOLT_REG_3,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 2. "MMC_VOLT_REG_2,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
bitfld.long 0x8 1. "MMC_VOLT_REG_1,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
newline
bitfld.long 0x8 0. "MMC_VOLT_REG_0,Support for 1.2V. MMC_VOLT_REG bits; must be read in combination" "0,1"
line.long 0xC "EMMC_DDR_REG,Name: EMMC DDR Register"
rbitfld.long 0xC 31. "HS400_MODE,HS400 Mode Enable" "0,1"
bitfld.long 0xC 0. "HALF_START_BIT_0,Control for start bit detection mechanism inside" "0,1"
line.long 0x10 "ENABLE_SHIFT,Name: Enable Phase Shift Register"
bitfld.long 0x10 0.--1. "ENABLE_SHIFT_CARD0,Control for the amount of phase shift provided on the default" "0,1,2,3"
group.long 0x200++0x3
line.long 0x0 "DATA,Provides read/write access to data FIFO. Addresses 0x200 and above are mapped to the data FIFO. More than one address is mapped to data FIFO so that FIFO can be accessed using bursts."
hexmask.long 0x0 0.--31. 1. "value,Provides read/write access to data FIFO."
tree.end
tree "SPI (Serial Peripheral Interface Controller)"
base ad:0x0
tree "SPI0 (SPI 0 Module Slave)"
base ad:0xFFDA2000
group.long 0x0++0x3
line.long 0x0 "CTRLR0,Control Register 0:"
hexmask.long.word 0x0 23.--31. 1. "RSVD_CTRLR0,Reserved bits - Read Only"
newline
rbitfld.long 0x0 21.--22. "SPI_FRF,SPI Frame Format:" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--20. 1. "DFS_32,Data Frame Size in 32-bit transfer size mode."
newline
hexmask.long.byte 0x0 12.--15. 1. "CFS,Control Frame Size. Selects the length of the control word for the"
newline
bitfld.long 0x0 11. "SRL,Shift Register Loop. Used for testing purposes only. When internally" "0,1"
newline
bitfld.long 0x0 10. "SLV_OE,Slave Output Enable." "0,1"
newline
bitfld.long 0x0 8.--9. "TMOD,Transfer Mode." "0,1,2,3"
newline
bitfld.long 0x0 7. "SCPOL,Serial Clock Polarity." "0,1"
newline
bitfld.long 0x0 6. "SCPH,Serial Clock Phase." "0: Serial clock toggles in middle of first data bit,1: Serial clock toggles at start of first data bit"
newline
bitfld.long 0x0 4.--5. "FRF,Frame Format." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "DFS,Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is"
group.long 0x8++0x7
line.long 0x0 "SSIENR,SSI Enable Register"
hexmask.long 0x0 1.--31. 1. "RSVD_SSIENR,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "SSI_EN,SSI Enable. Enables and disables all DW_apb_ssi operations. When" "0,1"
line.long 0x4 "MWCR,Microwire Control Register."
hexmask.long 0x4 3.--31. 1. "RSVD_MWCR,Reserved bits - Read Only"
newline
rbitfld.long 0x4 2. "RSVD_MHS,Reserved field- read-only" "0,1"
newline
bitfld.long 0x4 1. "MDD,Microwire Control." "0,1"
newline
bitfld.long 0x4 0. "MWMOD,Microwire Transfer Mode." "0: non-sequential transfer,1: sequential transfer"
group.long 0x18++0x7
line.long 0x0 "TXFTLR,Transmit FIFO Threshold Level."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_TXFTLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "TFT,Transmit FIFO Threshold."
line.long 0x4 "RXFTLR,Receive FIFO Threshold level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_RXFTLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "RFT,Receive FIFO Threshold."
rgroup.long 0x20++0xB
line.long 0x0 "TXFLR,Transmit FIFO Level Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
newline
hexmask.long.word 0x0 0.--8. 1. "TXTFL,Transmit FIFO Level."
line.long 0x4 "RXFLR,Receive FIFO Level Register"
hexmask.long.tbyte 0x4 9.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--8. 1. "RXTFL,Receive FIFO Level."
line.long 0x8 "SR,Status Register."
hexmask.long 0x8 7.--31. 1. "RSVD_SR,Reserved bits - Read Only"
newline
bitfld.long 0x8 6. "RSVD_DCOL,Reserved field- read-only" "0,1"
newline
bitfld.long 0x8 5. "TXE,Transmission Error." "0,1"
newline
bitfld.long 0x8 4. "RFF,Receive FIFO Full. When the receive FIFO is completely full  this bit" "0,1"
newline
bitfld.long 0x8 3. "RFNE,Receive FIFO Not Empty." "0,1"
newline
bitfld.long 0x8 2. "TFE,Transmit FIFO Empty." "0,1"
newline
bitfld.long 0x8 1. "TFNF,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more" "0,1"
newline
bitfld.long 0x8 0. "BUSY,SSI Busy Flag." "0,1"
group.long 0x2C++0x3
line.long 0x0 "IMR,Interrupt Mask Register"
hexmask.long 0x0 6.--31. 1. "RSVD_IMR,Reserved bits - Read Only"
newline
rbitfld.long 0x0 5. "RSVD_MSTIM,Reserved field- read-only" "0,1"
newline
bitfld.long 0x0 4. "RXFIM,Receive FIFO Full Interrupt Mask" "0,1"
newline
bitfld.long 0x0 3. "RXOIM,Receive FIFO Overflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "RXUIM,Receive FIFO Underflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "TXOIM,Transmit FIFO Overflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "TXEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
rgroup.long 0x30++0x1B
line.long 0x0 "ISR,Interrupt Status Register"
hexmask.long 0x0 6.--31. 1. "RSVD_ISR,Reserved bits - Read Only"
newline
bitfld.long 0x0 5. "RSVD_MSTIS,Reserved field- read-only" "0,1"
newline
bitfld.long 0x0 4. "RXFIS,Receive FIFO Full Interrupt Status" "0: ssi_rxf_intr interrupt is not active after masking,1: ssi_rxf_intr interrupt is full after masking"
newline
bitfld.long 0x0 3. "RXOIS,Receive FIFO Overflow Interrupt Status" "0: ssi_rxo_intr interrupt is not active after masking,1: ssi_rxo_intr interrupt is active after masking"
newline
bitfld.long 0x0 2. "RXUIS,Receive FIFO Underflow Interrupt Status" "0: ssi_rxu_intr interrupt is not active after masking,1: ssi_rxu_intr interrupt is active after masking"
newline
bitfld.long 0x0 1. "TXOIS,Transmit FIFO Overflow Interrupt Status" "0: ssi_txo_intr interrupt is not active after masking,1: ssi_txo_intr interrupt is active after masking"
newline
bitfld.long 0x0 0. "TXEIS,Transmit FIFO Empty Interrupt Status" "0: ssi_txe_intr interrupt is not active after masking,1: ssi_txe_intr interrupt is active after masking"
line.long 0x4 "RISR,Raw Interrupt Status Register"
hexmask.long 0x4 6.--31. 1. "RSVD_RISR,Reserved bits - Read Only"
newline
bitfld.long 0x4 5. "RSVD_MSTIR,Reserved field- read-only" "0,1"
newline
bitfld.long 0x4 4. "RXFIR,Receive FIFO Full Raw Interrupt Status" "0: ssi_rxf_intr interrupt is not active prior to..,1: ssi_rxf_intr interrupt is active prior to masking"
newline
bitfld.long 0x4 3. "RXOIR,Receive FIFO Overflow Raw Interrupt Status" "0: ssi_rxo_intr interrupt is not active prior to..,1: ssi_rxo_intr interrupt is active prior masking"
newline
bitfld.long 0x4 2. "RXUIR,Receive FIFO Underflow Raw Interrupt Status" "0: ssi_rxu_intr interrupt is not active prior to..,1: ssi_rxu_intr interrupt is active prior to masking"
newline
bitfld.long 0x4 1. "TXOIR,Transmit FIFO Overflow Raw Interrupt Status" "0: ssi_txo_intr interrupt is not active prior to..,1: ssi_txo_intr interrupt is active prior masking"
newline
bitfld.long 0x4 0. "TXEIR,Transmit FIFO Empty Raw Interrupt Status" "0: ssi_txe_intr interrupt is not active prior to..,1: ssi_txe_intr interrupt is active prior masking"
line.long 0x8 "TXOICR,Transmit FIFO Overflow Interrupt Clear Register"
hexmask.long 0x8 1.--31. 1. "RSVD_TXOICR,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "TXOICR,Clear Transmit FIFO Overflow Interrupt." "0,1"
line.long 0xC "RXOICR,Receive FIFO Overflow Interrupt Clear Register"
hexmask.long 0xC 1.--31. 1. "RSVD_RXOICR,Reserved bits - Read Only"
newline
bitfld.long 0xC 0. "RXOICR,Clear Receive FIFO Overflow Interrupt." "0,1"
line.long 0x10 "RXUICR,Receive FIFO Underflow Interrupt Clear Register"
hexmask.long 0x10 1.--31. 1. "RSVD_RXUICR,Reserved bits - Read Only"
newline
bitfld.long 0x10 0. "RXUICR,Clear Receive FIFO Underflow Interrupt." "0,1"
line.long 0x14 "MSTICR,Multi-Master Interrupt Clear Register"
hexmask.long 0x14 1.--31. 1. "RSVD_MSTICR,Reserved bits - Read Only"
newline
bitfld.long 0x14 0. "MSTICR,Clear Multi-Master Contention Interrupt." "0,1"
line.long 0x18 "ICR,Interrupt Clear Register"
hexmask.long 0x18 1.--31. 1. "RSVD_ICR,Reserved bits - Read Only"
newline
bitfld.long 0x18 0. "ICR,Clear Interrupts." "0,1"
group.long 0x4C++0xB
line.long 0x0 "DMACR,DMA Control Register."
hexmask.long 0x0 2.--31. 1. "RSVD_DMACR,Reserved bits - Read Only"
newline
bitfld.long 0x0 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
newline
bitfld.long 0x0 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x4 "DMATDLR,DMA Transmit Data Level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_DMATDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "DMATDL,Transmit Data Level."
line.long 0x8 "DMARDLR,DMA Receive Data Level."
hexmask.long.tbyte 0x8 8.--31. 1. "RSVD_DMARDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x8 0.--7. 1. "DMARDL,Receive Data Level."
rgroup.long 0x58++0x7
line.long 0x0 "IDR,Identification Register."
hexmask.long 0x0 0.--31. 1. "IDCODE,Identification code. The register contains the peripheral's identification code  which is written into the register at configuration time using CoreConsultant."
line.long 0x4 "SSI_VERSION_ID,coreKit Version ID Register"
hexmask.long 0x4 0.--31. 1. "SSI_COMP_VERSION,Contains the hex representation of the Synopsys component version. Consists of ASCII value for each number in the version  followed by *. For example 32_30_31_2A represents the version 2.01*."
group.long 0x60++0x8F
line.long 0x0 "DR0,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x0 0.--31. 1. "dr0,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x4 "DR1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x4 0.--31. 1. "dr1,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x8 "DR2,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x8 0.--31. 1. "dr2,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0xC "DR3,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0xC 0.--31. 1. "dr3,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x10 "DR4,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x10 0.--31. 1. "dr4,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x14 "DR5,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x14 0.--31. 1. "dr5,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x18 "DR6,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x18 0.--31. 1. "dr6,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x1C "DR7,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x1C 0.--31. 1. "dr7,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x20 "DR8,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x20 0.--31. 1. "dr8,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x24 "DR9,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x24 0.--31. 1. "dr9,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x28 "DR10,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x28 0.--31. 1. "dr10,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x2C "DR11,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x2C 0.--31. 1. "dr11,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x30 "DR12,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x30 0.--31. 1. "dr12,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x34 "DR13,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x34 0.--31. 1. "dr13,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x38 "DR14,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x38 0.--31. 1. "dr14,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x3C "DR15,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x3C 0.--31. 1. "dr15,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x40 "DR16,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x40 0.--31. 1. "dr16,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x44 "DR17,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x44 0.--31. 1. "dr17,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x48 "DR18,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x48 0.--31. 1. "dr18,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x4C "DR19,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x4C 0.--31. 1. "dr19,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x50 "DR20,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x50 0.--31. 1. "dr20,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x54 "DR21,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x54 0.--31. 1. "dr21,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x58 "DR22,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x58 0.--31. 1. "dr22,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x5C "DR23,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x5C 0.--31. 1. "dr23,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x60 "DR24,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x60 0.--31. 1. "dr24,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x64 "DR25,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x64 0.--31. 1. "dr25,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x68 "DR26,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x68 0.--31. 1. "dr26,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x6C "DR27,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x6C 0.--31. 1. "dr27,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x70 "DR28,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x70 0.--31. 1. "dr28,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x74 "DR29,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x74 0.--31. 1. "dr29,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x78 "DR30,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x78 0.--31. 1. "dr30,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x7C "DR31,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x7C 0.--31. 1. "dr31,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x80 "DR32,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x80 0.--31. 1. "dr32,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x84 "DR33,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x84 0.--31. 1. "dr33,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x88 "DR34,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x88 0.--31. 1. "dr34,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x8C "DR35,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x8C 0.--31. 1. "dr35,Data Register. When writing to this register  you must right-justify the data. Read"
rgroup.long 0xF8++0x7
line.long 0x0 "RSVD_1,RSVD_1 - Reserved address location"
hexmask.long 0x0 0.--31. 1. "RSVD1,Reserved address location"
line.long 0x4 "RSVD_2,RSVD_2 - Reserved address location"
hexmask.long 0x4 0.--31. 1. "RSVD2,Reserved address location"
tree.end
tree "SPI1 (SPI 1 Module Slave)"
base ad:0xFFDA3000
group.long 0x0++0x3
line.long 0x0 "CTRLR0,Control Register 0:"
hexmask.long.word 0x0 23.--31. 1. "RSVD_CTRLR0,Reserved bits - Read Only"
newline
rbitfld.long 0x0 21.--22. "SPI_FRF,SPI Frame Format:" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--20. 1. "DFS_32,Data Frame Size in 32-bit transfer size mode."
newline
hexmask.long.byte 0x0 12.--15. 1. "CFS,Control Frame Size. Selects the length of the control word for the"
newline
bitfld.long 0x0 11. "SRL,Shift Register Loop. Used for testing purposes only. When internally" "0,1"
newline
bitfld.long 0x0 10. "SLV_OE,Slave Output Enable." "0,1"
newline
bitfld.long 0x0 8.--9. "TMOD,Transfer Mode." "0,1,2,3"
newline
bitfld.long 0x0 7. "SCPOL,Serial Clock Polarity." "0,1"
newline
bitfld.long 0x0 6. "SCPH,Serial Clock Phase." "0: Serial clock toggles in middle of first data bit,1: Serial clock toggles at start of first data bit"
newline
bitfld.long 0x0 4.--5. "FRF,Frame Format." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "DFS,Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is"
group.long 0x8++0x7
line.long 0x0 "SSIENR,SSI Enable Register"
hexmask.long 0x0 1.--31. 1. "RSVD_SSIENR,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "SSI_EN,SSI Enable. Enables and disables all DW_apb_ssi operations. When" "0,1"
line.long 0x4 "MWCR,Microwire Control Register."
hexmask.long 0x4 3.--31. 1. "RSVD_MWCR,Reserved bits - Read Only"
newline
rbitfld.long 0x4 2. "RSVD_MHS,Reserved field- read-only" "0,1"
newline
bitfld.long 0x4 1. "MDD,Microwire Control." "0,1"
newline
bitfld.long 0x4 0. "MWMOD,Microwire Transfer Mode." "0: non-sequential transfer,1: sequential transfer"
group.long 0x18++0x7
line.long 0x0 "TXFTLR,Transmit FIFO Threshold Level."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_TXFTLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "TFT,Transmit FIFO Threshold."
line.long 0x4 "RXFTLR,Receive FIFO Threshold level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_RXFTLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "RFT,Receive FIFO Threshold."
rgroup.long 0x20++0xB
line.long 0x0 "TXFLR,Transmit FIFO Level Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
newline
hexmask.long.word 0x0 0.--8. 1. "TXTFL,Transmit FIFO Level."
line.long 0x4 "RXFLR,Receive FIFO Level Register"
hexmask.long.tbyte 0x4 9.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--8. 1. "RXTFL,Receive FIFO Level."
line.long 0x8 "SR,Status Register."
hexmask.long 0x8 7.--31. 1. "RSVD_SR,Reserved bits - Read Only"
newline
bitfld.long 0x8 6. "RSVD_DCOL,Reserved field- read-only" "0,1"
newline
bitfld.long 0x8 5. "TXE,Transmission Error." "0,1"
newline
bitfld.long 0x8 4. "RFF,Receive FIFO Full. When the receive FIFO is completely full  this bit" "0,1"
newline
bitfld.long 0x8 3. "RFNE,Receive FIFO Not Empty." "0,1"
newline
bitfld.long 0x8 2. "TFE,Transmit FIFO Empty." "0,1"
newline
bitfld.long 0x8 1. "TFNF,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more" "0,1"
newline
bitfld.long 0x8 0. "BUSY,SSI Busy Flag." "0,1"
group.long 0x2C++0x3
line.long 0x0 "IMR,Interrupt Mask Register"
hexmask.long 0x0 6.--31. 1. "RSVD_IMR,Reserved bits - Read Only"
newline
rbitfld.long 0x0 5. "RSVD_MSTIM,Reserved field- read-only" "0,1"
newline
bitfld.long 0x0 4. "RXFIM,Receive FIFO Full Interrupt Mask" "0,1"
newline
bitfld.long 0x0 3. "RXOIM,Receive FIFO Overflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "RXUIM,Receive FIFO Underflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "TXOIM,Transmit FIFO Overflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "TXEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
rgroup.long 0x30++0x1B
line.long 0x0 "ISR,Interrupt Status Register"
hexmask.long 0x0 6.--31. 1. "RSVD_ISR,Reserved bits - Read Only"
newline
bitfld.long 0x0 5. "RSVD_MSTIS,Reserved field- read-only" "0,1"
newline
bitfld.long 0x0 4. "RXFIS,Receive FIFO Full Interrupt Status" "0: ssi_rxf_intr interrupt is not active after masking,1: ssi_rxf_intr interrupt is full after masking"
newline
bitfld.long 0x0 3. "RXOIS,Receive FIFO Overflow Interrupt Status" "0: ssi_rxo_intr interrupt is not active after masking,1: ssi_rxo_intr interrupt is active after masking"
newline
bitfld.long 0x0 2. "RXUIS,Receive FIFO Underflow Interrupt Status" "0: ssi_rxu_intr interrupt is not active after masking,1: ssi_rxu_intr interrupt is active after masking"
newline
bitfld.long 0x0 1. "TXOIS,Transmit FIFO Overflow Interrupt Status" "0: ssi_txo_intr interrupt is not active after masking,1: ssi_txo_intr interrupt is active after masking"
newline
bitfld.long 0x0 0. "TXEIS,Transmit FIFO Empty Interrupt Status" "0: ssi_txe_intr interrupt is not active after masking,1: ssi_txe_intr interrupt is active after masking"
line.long 0x4 "RISR,Raw Interrupt Status Register"
hexmask.long 0x4 6.--31. 1. "RSVD_RISR,Reserved bits - Read Only"
newline
bitfld.long 0x4 5. "RSVD_MSTIR,Reserved field- read-only" "0,1"
newline
bitfld.long 0x4 4. "RXFIR,Receive FIFO Full Raw Interrupt Status" "0: ssi_rxf_intr interrupt is not active prior to..,1: ssi_rxf_intr interrupt is active prior to masking"
newline
bitfld.long 0x4 3. "RXOIR,Receive FIFO Overflow Raw Interrupt Status" "0: ssi_rxo_intr interrupt is not active prior to..,1: ssi_rxo_intr interrupt is active prior masking"
newline
bitfld.long 0x4 2. "RXUIR,Receive FIFO Underflow Raw Interrupt Status" "0: ssi_rxu_intr interrupt is not active prior to..,1: ssi_rxu_intr interrupt is active prior to masking"
newline
bitfld.long 0x4 1. "TXOIR,Transmit FIFO Overflow Raw Interrupt Status" "0: ssi_txo_intr interrupt is not active prior to..,1: ssi_txo_intr interrupt is active prior masking"
newline
bitfld.long 0x4 0. "TXEIR,Transmit FIFO Empty Raw Interrupt Status" "0: ssi_txe_intr interrupt is not active prior to..,1: ssi_txe_intr interrupt is active prior masking"
line.long 0x8 "TXOICR,Transmit FIFO Overflow Interrupt Clear Register"
hexmask.long 0x8 1.--31. 1. "RSVD_TXOICR,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "TXOICR,Clear Transmit FIFO Overflow Interrupt." "0,1"
line.long 0xC "RXOICR,Receive FIFO Overflow Interrupt Clear Register"
hexmask.long 0xC 1.--31. 1. "RSVD_RXOICR,Reserved bits - Read Only"
newline
bitfld.long 0xC 0. "RXOICR,Clear Receive FIFO Overflow Interrupt." "0,1"
line.long 0x10 "RXUICR,Receive FIFO Underflow Interrupt Clear Register"
hexmask.long 0x10 1.--31. 1. "RSVD_RXUICR,Reserved bits - Read Only"
newline
bitfld.long 0x10 0. "RXUICR,Clear Receive FIFO Underflow Interrupt." "0,1"
line.long 0x14 "MSTICR,Multi-Master Interrupt Clear Register"
hexmask.long 0x14 1.--31. 1. "RSVD_MSTICR,Reserved bits - Read Only"
newline
bitfld.long 0x14 0. "MSTICR,Clear Multi-Master Contention Interrupt." "0,1"
line.long 0x18 "ICR,Interrupt Clear Register"
hexmask.long 0x18 1.--31. 1. "RSVD_ICR,Reserved bits - Read Only"
newline
bitfld.long 0x18 0. "ICR,Clear Interrupts." "0,1"
group.long 0x4C++0xB
line.long 0x0 "DMACR,DMA Control Register."
hexmask.long 0x0 2.--31. 1. "RSVD_DMACR,Reserved bits - Read Only"
newline
bitfld.long 0x0 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
newline
bitfld.long 0x0 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x4 "DMATDLR,DMA Transmit Data Level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_DMATDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "DMATDL,Transmit Data Level."
line.long 0x8 "DMARDLR,DMA Receive Data Level."
hexmask.long.tbyte 0x8 8.--31. 1. "RSVD_DMARDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x8 0.--7. 1. "DMARDL,Receive Data Level."
rgroup.long 0x58++0x7
line.long 0x0 "IDR,Identification Register."
hexmask.long 0x0 0.--31. 1. "IDCODE,Identification code. The register contains the peripheral's identification code  which is written into the register at configuration time using CoreConsultant."
line.long 0x4 "SSI_VERSION_ID,coreKit Version ID Register"
hexmask.long 0x4 0.--31. 1. "SSI_COMP_VERSION,Contains the hex representation of the Synopsys component version. Consists of ASCII value for each number in the version  followed by *. For example 32_30_31_2A represents the version 2.01*."
group.long 0x60++0x8F
line.long 0x0 "DR0,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x0 0.--31. 1. "dr0,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x4 "DR1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x4 0.--31. 1. "dr1,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x8 "DR2,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x8 0.--31. 1. "dr2,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0xC "DR3,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0xC 0.--31. 1. "dr3,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x10 "DR4,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x10 0.--31. 1. "dr4,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x14 "DR5,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x14 0.--31. 1. "dr5,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x18 "DR6,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x18 0.--31. 1. "dr6,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x1C "DR7,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x1C 0.--31. 1. "dr7,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x20 "DR8,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x20 0.--31. 1. "dr8,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x24 "DR9,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x24 0.--31. 1. "dr9,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x28 "DR10,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x28 0.--31. 1. "dr10,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x2C "DR11,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x2C 0.--31. 1. "dr11,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x30 "DR12,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x30 0.--31. 1. "dr12,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x34 "DR13,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x34 0.--31. 1. "dr13,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x38 "DR14,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x38 0.--31. 1. "dr14,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x3C "DR15,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x3C 0.--31. 1. "dr15,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x40 "DR16,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x40 0.--31. 1. "dr16,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x44 "DR17,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x44 0.--31. 1. "dr17,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x48 "DR18,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x48 0.--31. 1. "dr18,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x4C "DR19,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x4C 0.--31. 1. "dr19,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x50 "DR20,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x50 0.--31. 1. "dr20,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x54 "DR21,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x54 0.--31. 1. "dr21,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x58 "DR22,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x58 0.--31. 1. "dr22,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x5C "DR23,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x5C 0.--31. 1. "dr23,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x60 "DR24,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x60 0.--31. 1. "dr24,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x64 "DR25,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x64 0.--31. 1. "dr25,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x68 "DR26,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x68 0.--31. 1. "dr26,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x6C "DR27,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x6C 0.--31. 1. "dr27,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x70 "DR28,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x70 0.--31. 1. "dr28,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x74 "DR29,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x74 0.--31. 1. "dr29,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x78 "DR30,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x78 0.--31. 1. "dr30,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x7C "DR31,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x7C 0.--31. 1. "dr31,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x80 "DR32,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x80 0.--31. 1. "dr32,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x84 "DR33,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x84 0.--31. 1. "dr33,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x88 "DR34,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x88 0.--31. 1. "dr34,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x8C "DR35,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x8C 0.--31. 1. "dr35,Data Register. When writing to this register  you must right-justify the data. Read"
rgroup.long 0xF8++0x7
line.long 0x0 "RSVD_1,RSVD_1 - Reserved address location"
hexmask.long 0x0 0.--31. 1. "RSVD1,Reserved address location"
line.long 0x4 "RSVD_2,RSVD_2 - Reserved address location"
hexmask.long 0x4 0.--31. 1. "RSVD2,Reserved address location"
tree.end
tree "SPI2 (SPI 2 Module Master)"
base ad:0xFFDA4000
group.long 0x0++0x1F
line.long 0x0 "CTRLR0,Control Register 0:"
hexmask.long.word 0x0 23.--31. 1. "RSVD_CTRLR0,Reserved bits - Read Only"
newline
rbitfld.long 0x0 21.--22. "SPI_FRF,SPI Frame Format:" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--20. 1. "DFS_32,Data Frame Size in 32-bit transfer size mode."
newline
hexmask.long.byte 0x0 12.--15. 1. "CFS,Control Frame Size. Selects the length of the control word for the"
newline
bitfld.long 0x0 11. "SRL,Shift Register Loop. Used for testing purposes only. When internally" "0,1"
newline
rbitfld.long 0x0 10. "RSVD_SLV_OE,Reserved field- Read-only" "0,1"
newline
bitfld.long 0x0 8.--9. "TMOD,Transfer Mode." "0,1,2,3"
newline
bitfld.long 0x0 7. "SCPOL,Serial Clock Polarity." "0,1"
newline
bitfld.long 0x0 6. "SCPH,Serial Clock Phase." "0: Serial clock toggles in middle of first data bit,1: Serial clock toggles at start of first data bit"
newline
bitfld.long 0x0 4.--5. "FRF,Frame Format." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "DFS,Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is"
line.long 0x4 "CTRLR1,Control Register 1"
hexmask.long.word 0x4 16.--31. 1. "RSVD_CTRLR1,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--15. 1. "NDF,Number of Data Frames."
line.long 0x8 "SSIENR,SSI Enable Register"
hexmask.long 0x8 1.--31. 1. "RSVD_SSIENR,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "SSI_EN,SSI Enable. Enables and disables all DW_apb_ssi operations. When" "0,1"
line.long 0xC "MWCR,Microwire Control Register."
hexmask.long 0xC 3.--31. 1. "RSVD_MWCR,Reserved bits - Read Only"
newline
bitfld.long 0xC 2. "MHS,Microwire Handshaking." "0: handshaking interface is disabled,1: handshaking interface is enabled"
newline
bitfld.long 0xC 1. "MDD,Microwire Control." "0,1"
newline
bitfld.long 0xC 0. "MWMOD,Microwire Transfer Mode." "0: non-sequential transfer,1: sequential transfer"
line.long 0x10 "SER,Slave Enable Register."
hexmask.long 0x10 4.--31. 1. "RSVD_SER,Reserved bits - Read Only"
newline
hexmask.long.byte 0x10 0.--3. 1. "SER,Slave Select Enable Flag."
line.long 0x14 "BAUDR,Baud Rate Select."
hexmask.long.word 0x14 16.--31. 1. "RSVD_BAUDR,Reserved bits - Read Only"
newline
hexmask.long.word 0x14 0.--15. 1. "SCKDV,SSI Clock Divider."
line.long 0x18 "TXFTLR,Transmit FIFO Threshold Level."
hexmask.long.tbyte 0x18 8.--31. 1. "RSVD_TXFTLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x18 0.--7. 1. "TFT,Transmit FIFO Threshold."
line.long 0x1C "RXFTLR,Receive FIFO Threshold level."
hexmask.long.tbyte 0x1C 8.--31. 1. "RSVD_RXFTLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x1C 0.--7. 1. "RFT,Receive FIFO Threshold."
rgroup.long 0x20++0xB
line.long 0x0 "TXFLR,Transmit FIFO Level Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
newline
hexmask.long.word 0x0 0.--8. 1. "TXTFL,Transmit FIFO Level."
line.long 0x4 "RXFLR,Receive FIFO Level Register"
hexmask.long.tbyte 0x4 9.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--8. 1. "RXTFL,Receive FIFO Level."
line.long 0x8 "SR,Status Register."
hexmask.long 0x8 7.--31. 1. "RSVD_SR,Reserved bits - Read Only"
newline
bitfld.long 0x8 6. "DCOL,Data Collision Error." "0,1"
newline
bitfld.long 0x8 5. "RSVD_TXE,Reserved field- read-only" "0,1"
newline
bitfld.long 0x8 4. "RFF,Receive FIFO Full. When the receive FIFO is completely full  this bit" "0,1"
newline
bitfld.long 0x8 3. "RFNE,Receive FIFO Not Empty." "0,1"
newline
bitfld.long 0x8 2. "TFE,Transmit FIFO Empty." "0,1"
newline
bitfld.long 0x8 1. "TFNF,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more" "0,1"
newline
bitfld.long 0x8 0. "BUSY,SSI Busy Flag." "0,1"
group.long 0x2C++0x3
line.long 0x0 "IMR,Interrupt Mask Register"
hexmask.long 0x0 6.--31. 1. "RSVD_IMR,Reserved bits - Read Only"
newline
bitfld.long 0x0 5. "MSTIM,Multi-Master Contention Interrupt Mask. This bit field is not present if" "0,1"
newline
bitfld.long 0x0 4. "RXFIM,Receive FIFO Full Interrupt Mask" "0,1"
newline
bitfld.long 0x0 3. "RXOIM,Receive FIFO Overflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "RXUIM,Receive FIFO Underflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "TXOIM,Transmit FIFO Overflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "TXEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
rgroup.long 0x30++0x1B
line.long 0x0 "ISR,Interrupt Status Register"
hexmask.long 0x0 6.--31. 1. "RSVD_ISR,Reserved bits - Read Only"
newline
bitfld.long 0x0 5. "MSTIS,Multi-Master Contention Interrupt Status. This bit field is not present" "0: ssi_mst_intr interrupt not active after masking,1: ssi_mst_intr interrupt is active after masking"
newline
bitfld.long 0x0 4. "RXFIS,Receive FIFO Full Interrupt Status" "0: ssi_rxf_intr interrupt is not active after masking,1: ssi_rxf_intr interrupt is full after masking"
newline
bitfld.long 0x0 3. "RXOIS,Receive FIFO Overflow Interrupt Status" "0: ssi_rxo_intr interrupt is not active after masking,1: ssi_rxo_intr interrupt is active after masking"
newline
bitfld.long 0x0 2. "RXUIS,Receive FIFO Underflow Interrupt Status" "0: ssi_rxu_intr interrupt is not active after masking,1: ssi_rxu_intr interrupt is active after masking"
newline
bitfld.long 0x0 1. "TXOIS,Transmit FIFO Overflow Interrupt Status" "0: ssi_txo_intr interrupt is not active after masking,1: ssi_txo_intr interrupt is active after masking"
newline
bitfld.long 0x0 0. "TXEIS,Transmit FIFO Empty Interrupt Status" "0: ssi_txe_intr interrupt is not active after masking,1: ssi_txe_intr interrupt is active after masking"
line.long 0x4 "RISR,Raw Interrupt Status Register"
hexmask.long 0x4 6.--31. 1. "RSVD_RISR,Reserved bits - Read Only"
newline
bitfld.long 0x4 5. "MSTIR,Multi-Master Contention Raw Interrupt Status." "0: ssi_mst_intr interrupt is not active prior to..,1: ssi_mst_intr interrupt is active prior masking"
newline
bitfld.long 0x4 4. "RXFIR,Receive FIFO Full Raw Interrupt Status" "0: ssi_rxf_intr interrupt is not active prior to..,1: ssi_rxf_intr interrupt is active prior to masking"
newline
bitfld.long 0x4 3. "RXOIR,Receive FIFO Overflow Raw Interrupt Status" "0: ssi_rxo_intr interrupt is not active prior to..,1: ssi_rxo_intr interrupt is active prior masking"
newline
bitfld.long 0x4 2. "RXUIR,Receive FIFO Underflow Raw Interrupt Status" "0: ssi_rxu_intr interrupt is not active prior to..,1: ssi_rxu_intr interrupt is active prior to masking"
newline
bitfld.long 0x4 1. "TXOIR,Transmit FIFO Overflow Raw Interrupt Status" "0: ssi_txo_intr interrupt is not active prior to..,1: ssi_txo_intr interrupt is active prior masking"
newline
bitfld.long 0x4 0. "TXEIR,Transmit FIFO Empty Raw Interrupt Status" "0: ssi_txe_intr interrupt is not active prior to..,1: ssi_txe_intr interrupt is active prior masking"
line.long 0x8 "TXOICR,Transmit FIFO Overflow Interrupt Clear Register"
hexmask.long 0x8 1.--31. 1. "RSVD_TXOICR,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "TXOICR,Clear Transmit FIFO Overflow Interrupt." "0,1"
line.long 0xC "RXOICR,Receive FIFO Overflow Interrupt Clear Register"
hexmask.long 0xC 1.--31. 1. "RSVD_RXOICR,Reserved bits - Read Only"
newline
bitfld.long 0xC 0. "RXOICR,Clear Receive FIFO Overflow Interrupt." "0,1"
line.long 0x10 "RXUICR,Receive FIFO Underflow Interrupt Clear Register"
hexmask.long 0x10 1.--31. 1. "RSVD_RXUICR,Reserved bits - Read Only"
newline
bitfld.long 0x10 0. "RXUICR,Clear Receive FIFO Underflow Interrupt." "0,1"
line.long 0x14 "MSTICR,Multi-Master Interrupt Clear Register"
hexmask.long 0x14 1.--31. 1. "RSVD_MSTICR,Reserved bits - Read Only"
newline
bitfld.long 0x14 0. "MSTICR,Clear Multi-Master Contention Interrupt." "0,1"
line.long 0x18 "ICR,Interrupt Clear Register"
hexmask.long 0x18 1.--31. 1. "RSVD_ICR,Reserved bits - Read Only"
newline
bitfld.long 0x18 0. "ICR,Clear Interrupts." "0,1"
group.long 0x4C++0xB
line.long 0x0 "DMACR,DMA Control Register."
hexmask.long 0x0 2.--31. 1. "RSVD_DMACR,Reserved bits - Read Only"
newline
bitfld.long 0x0 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
newline
bitfld.long 0x0 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x4 "DMATDLR,DMA Transmit Data Level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_DMATDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "DMATDL,Transmit Data Level."
line.long 0x8 "DMARDLR,DMA Receive Data Level."
hexmask.long.tbyte 0x8 8.--31. 1. "RSVD_DMARDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x8 0.--7. 1. "DMARDL,Receive Data Level."
rgroup.long 0x58++0x7
line.long 0x0 "IDR,Identification Register."
hexmask.long 0x0 0.--31. 1. "IDCODE,Identification code. The register contains the peripheral's identification code  which is written into the register at configuration time using CoreConsultant."
line.long 0x4 "SSI_VERSION_ID,coreKit Version ID Register"
hexmask.long 0x4 0.--31. 1. "SSI_COMP_VERSION,Contains the hex representation of the Synopsys component version. Consists of ASCII value for each number in the version  followed by *. For example 32_30_31_2A represents the version 2.01*."
group.long 0x60++0x93
line.long 0x0 "DR0,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x0 0.--31. 1. "dr0,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x4 "DR1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x4 0.--31. 1. "dr1,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x8 "DR2,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x8 0.--31. 1. "dr2,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0xC "DR3,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0xC 0.--31. 1. "dr3,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x10 "DR4,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x10 0.--31. 1. "dr4,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x14 "DR5,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x14 0.--31. 1. "dr5,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x18 "DR6,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x18 0.--31. 1. "dr6,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x1C "DR7,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x1C 0.--31. 1. "dr7,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x20 "DR8,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x20 0.--31. 1. "dr8,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x24 "DR9,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x24 0.--31. 1. "dr9,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x28 "DR10,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x28 0.--31. 1. "dr10,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x2C "DR11,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x2C 0.--31. 1. "dr11,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x30 "DR12,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x30 0.--31. 1. "dr12,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x34 "DR13,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x34 0.--31. 1. "dr13,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x38 "DR14,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x38 0.--31. 1. "dr14,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x3C "DR15,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x3C 0.--31. 1. "dr15,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x40 "DR16,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x40 0.--31. 1. "dr16,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x44 "DR17,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x44 0.--31. 1. "dr17,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x48 "DR18,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x48 0.--31. 1. "dr18,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x4C "DR19,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x4C 0.--31. 1. "dr19,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x50 "DR20,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x50 0.--31. 1. "dr20,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x54 "DR21,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x54 0.--31. 1. "dr21,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x58 "DR22,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x58 0.--31. 1. "dr22,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x5C "DR23,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x5C 0.--31. 1. "dr23,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x60 "DR24,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x60 0.--31. 1. "dr24,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x64 "DR25,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x64 0.--31. 1. "dr25,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x68 "DR26,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x68 0.--31. 1. "dr26,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x6C "DR27,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x6C 0.--31. 1. "dr27,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x70 "DR28,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x70 0.--31. 1. "dr28,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x74 "DR29,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x74 0.--31. 1. "dr29,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x78 "DR30,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x78 0.--31. 1. "dr30,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x7C "DR31,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x7C 0.--31. 1. "dr31,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x80 "DR32,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x80 0.--31. 1. "dr32,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x84 "DR33,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x84 0.--31. 1. "dr33,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x88 "DR34,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x88 0.--31. 1. "dr34,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x8C "DR35,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x8C 0.--31. 1. "dr35,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x90 "RX_SAMPLE_DLY,RX Sample Delay."
hexmask.long.tbyte 0x90 8.--31. 1. "RSVD_RX_SAMPLE_DLY,Reserved bits - Read Only"
newline
hexmask.long.byte 0x90 0.--7. 1. "RSD,Rxd Sample Delay."
rgroup.long 0xF8++0x7
line.long 0x0 "RSVD_1,RSVD_1 - Reserved address location"
hexmask.long 0x0 0.--31. 1. "RSVD1,Reserved address location"
line.long 0x4 "RSVD_2,RSVD_2 - Reserved address location"
hexmask.long 0x4 0.--31. 1. "RSVD2,Reserved address location"
tree.end
tree "SPI3 (SPI 3 Module Master)"
base ad:0xFFDA5000
group.long 0x0++0x1F
line.long 0x0 "CTRLR0,Control Register 0:"
hexmask.long.word 0x0 23.--31. 1. "RSVD_CTRLR0,Reserved bits - Read Only"
newline
rbitfld.long 0x0 21.--22. "SPI_FRF,SPI Frame Format:" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--20. 1. "DFS_32,Data Frame Size in 32-bit transfer size mode."
newline
hexmask.long.byte 0x0 12.--15. 1. "CFS,Control Frame Size. Selects the length of the control word for the"
newline
bitfld.long 0x0 11. "SRL,Shift Register Loop. Used for testing purposes only. When internally" "0,1"
newline
rbitfld.long 0x0 10. "RSVD_SLV_OE,Reserved field- Read-only" "0,1"
newline
bitfld.long 0x0 8.--9. "TMOD,Transfer Mode." "0,1,2,3"
newline
bitfld.long 0x0 7. "SCPOL,Serial Clock Polarity." "0,1"
newline
bitfld.long 0x0 6. "SCPH,Serial Clock Phase." "0: Serial clock toggles in middle of first data bit,1: Serial clock toggles at start of first data bit"
newline
bitfld.long 0x0 4.--5. "FRF,Frame Format." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "DFS,Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is"
line.long 0x4 "CTRLR1,Control Register 1"
hexmask.long.word 0x4 16.--31. 1. "RSVD_CTRLR1,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--15. 1. "NDF,Number of Data Frames."
line.long 0x8 "SSIENR,SSI Enable Register"
hexmask.long 0x8 1.--31. 1. "RSVD_SSIENR,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "SSI_EN,SSI Enable. Enables and disables all DW_apb_ssi operations. When" "0,1"
line.long 0xC "MWCR,Microwire Control Register."
hexmask.long 0xC 3.--31. 1. "RSVD_MWCR,Reserved bits - Read Only"
newline
bitfld.long 0xC 2. "MHS,Microwire Handshaking." "0: handshaking interface is disabled,1: handshaking interface is enabled"
newline
bitfld.long 0xC 1. "MDD,Microwire Control." "0,1"
newline
bitfld.long 0xC 0. "MWMOD,Microwire Transfer Mode." "0: non-sequential transfer,1: sequential transfer"
line.long 0x10 "SER,Slave Enable Register."
hexmask.long 0x10 4.--31. 1. "RSVD_SER,Reserved bits - Read Only"
newline
hexmask.long.byte 0x10 0.--3. 1. "SER,Slave Select Enable Flag."
line.long 0x14 "BAUDR,Baud Rate Select."
hexmask.long.word 0x14 16.--31. 1. "RSVD_BAUDR,Reserved bits - Read Only"
newline
hexmask.long.word 0x14 0.--15. 1. "SCKDV,SSI Clock Divider."
line.long 0x18 "TXFTLR,Transmit FIFO Threshold Level."
hexmask.long.tbyte 0x18 8.--31. 1. "RSVD_TXFTLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x18 0.--7. 1. "TFT,Transmit FIFO Threshold."
line.long 0x1C "RXFTLR,Receive FIFO Threshold level."
hexmask.long.tbyte 0x1C 8.--31. 1. "RSVD_RXFTLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x1C 0.--7. 1. "RFT,Receive FIFO Threshold."
rgroup.long 0x20++0xB
line.long 0x0 "TXFLR,Transmit FIFO Level Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
newline
hexmask.long.word 0x0 0.--8. 1. "TXTFL,Transmit FIFO Level."
line.long 0x4 "RXFLR,Receive FIFO Level Register"
hexmask.long.tbyte 0x4 9.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--8. 1. "RXTFL,Receive FIFO Level."
line.long 0x8 "SR,Status Register."
hexmask.long 0x8 7.--31. 1. "RSVD_SR,Reserved bits - Read Only"
newline
bitfld.long 0x8 6. "DCOL,Data Collision Error." "0,1"
newline
bitfld.long 0x8 5. "RSVD_TXE,Reserved field- read-only" "0,1"
newline
bitfld.long 0x8 4. "RFF,Receive FIFO Full. When the receive FIFO is completely full  this bit" "0,1"
newline
bitfld.long 0x8 3. "RFNE,Receive FIFO Not Empty." "0,1"
newline
bitfld.long 0x8 2. "TFE,Transmit FIFO Empty." "0,1"
newline
bitfld.long 0x8 1. "TFNF,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more" "0,1"
newline
bitfld.long 0x8 0. "BUSY,SSI Busy Flag." "0,1"
group.long 0x2C++0x3
line.long 0x0 "IMR,Interrupt Mask Register"
hexmask.long 0x0 6.--31. 1. "RSVD_IMR,Reserved bits - Read Only"
newline
bitfld.long 0x0 5. "MSTIM,Multi-Master Contention Interrupt Mask. This bit field is not present if" "0,1"
newline
bitfld.long 0x0 4. "RXFIM,Receive FIFO Full Interrupt Mask" "0,1"
newline
bitfld.long 0x0 3. "RXOIM,Receive FIFO Overflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "RXUIM,Receive FIFO Underflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "TXOIM,Transmit FIFO Overflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "TXEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
rgroup.long 0x30++0x1B
line.long 0x0 "ISR,Interrupt Status Register"
hexmask.long 0x0 6.--31. 1. "RSVD_ISR,Reserved bits - Read Only"
newline
bitfld.long 0x0 5. "MSTIS,Multi-Master Contention Interrupt Status. This bit field is not present" "0: ssi_mst_intr interrupt not active after masking,1: ssi_mst_intr interrupt is active after masking"
newline
bitfld.long 0x0 4. "RXFIS,Receive FIFO Full Interrupt Status" "0: ssi_rxf_intr interrupt is not active after masking,1: ssi_rxf_intr interrupt is full after masking"
newline
bitfld.long 0x0 3. "RXOIS,Receive FIFO Overflow Interrupt Status" "0: ssi_rxo_intr interrupt is not active after masking,1: ssi_rxo_intr interrupt is active after masking"
newline
bitfld.long 0x0 2. "RXUIS,Receive FIFO Underflow Interrupt Status" "0: ssi_rxu_intr interrupt is not active after masking,1: ssi_rxu_intr interrupt is active after masking"
newline
bitfld.long 0x0 1. "TXOIS,Transmit FIFO Overflow Interrupt Status" "0: ssi_txo_intr interrupt is not active after masking,1: ssi_txo_intr interrupt is active after masking"
newline
bitfld.long 0x0 0. "TXEIS,Transmit FIFO Empty Interrupt Status" "0: ssi_txe_intr interrupt is not active after masking,1: ssi_txe_intr interrupt is active after masking"
line.long 0x4 "RISR,Raw Interrupt Status Register"
hexmask.long 0x4 6.--31. 1. "RSVD_RISR,Reserved bits - Read Only"
newline
bitfld.long 0x4 5. "MSTIR,Multi-Master Contention Raw Interrupt Status." "0: ssi_mst_intr interrupt is not active prior to..,1: ssi_mst_intr interrupt is active prior masking"
newline
bitfld.long 0x4 4. "RXFIR,Receive FIFO Full Raw Interrupt Status" "0: ssi_rxf_intr interrupt is not active prior to..,1: ssi_rxf_intr interrupt is active prior to masking"
newline
bitfld.long 0x4 3. "RXOIR,Receive FIFO Overflow Raw Interrupt Status" "0: ssi_rxo_intr interrupt is not active prior to..,1: ssi_rxo_intr interrupt is active prior masking"
newline
bitfld.long 0x4 2. "RXUIR,Receive FIFO Underflow Raw Interrupt Status" "0: ssi_rxu_intr interrupt is not active prior to..,1: ssi_rxu_intr interrupt is active prior to masking"
newline
bitfld.long 0x4 1. "TXOIR,Transmit FIFO Overflow Raw Interrupt Status" "0: ssi_txo_intr interrupt is not active prior to..,1: ssi_txo_intr interrupt is active prior masking"
newline
bitfld.long 0x4 0. "TXEIR,Transmit FIFO Empty Raw Interrupt Status" "0: ssi_txe_intr interrupt is not active prior to..,1: ssi_txe_intr interrupt is active prior masking"
line.long 0x8 "TXOICR,Transmit FIFO Overflow Interrupt Clear Register"
hexmask.long 0x8 1.--31. 1. "RSVD_TXOICR,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "TXOICR,Clear Transmit FIFO Overflow Interrupt." "0,1"
line.long 0xC "RXOICR,Receive FIFO Overflow Interrupt Clear Register"
hexmask.long 0xC 1.--31. 1. "RSVD_RXOICR,Reserved bits - Read Only"
newline
bitfld.long 0xC 0. "RXOICR,Clear Receive FIFO Overflow Interrupt." "0,1"
line.long 0x10 "RXUICR,Receive FIFO Underflow Interrupt Clear Register"
hexmask.long 0x10 1.--31. 1. "RSVD_RXUICR,Reserved bits - Read Only"
newline
bitfld.long 0x10 0. "RXUICR,Clear Receive FIFO Underflow Interrupt." "0,1"
line.long 0x14 "MSTICR,Multi-Master Interrupt Clear Register"
hexmask.long 0x14 1.--31. 1. "RSVD_MSTICR,Reserved bits - Read Only"
newline
bitfld.long 0x14 0. "MSTICR,Clear Multi-Master Contention Interrupt." "0,1"
line.long 0x18 "ICR,Interrupt Clear Register"
hexmask.long 0x18 1.--31. 1. "RSVD_ICR,Reserved bits - Read Only"
newline
bitfld.long 0x18 0. "ICR,Clear Interrupts." "0,1"
group.long 0x4C++0xB
line.long 0x0 "DMACR,DMA Control Register."
hexmask.long 0x0 2.--31. 1. "RSVD_DMACR,Reserved bits - Read Only"
newline
bitfld.long 0x0 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
newline
bitfld.long 0x0 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x4 "DMATDLR,DMA Transmit Data Level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_DMATDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "DMATDL,Transmit Data Level."
line.long 0x8 "DMARDLR,DMA Receive Data Level."
hexmask.long.tbyte 0x8 8.--31. 1. "RSVD_DMARDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x8 0.--7. 1. "DMARDL,Receive Data Level."
rgroup.long 0x58++0x7
line.long 0x0 "IDR,Identification Register."
hexmask.long 0x0 0.--31. 1. "IDCODE,Identification code. The register contains the peripheral's identification code  which is written into the register at configuration time using CoreConsultant."
line.long 0x4 "SSI_VERSION_ID,coreKit Version ID Register"
hexmask.long 0x4 0.--31. 1. "SSI_COMP_VERSION,Contains the hex representation of the Synopsys component version. Consists of ASCII value for each number in the version  followed by *. For example 32_30_31_2A represents the version 2.01*."
group.long 0x60++0x93
line.long 0x0 "DR0,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x0 0.--31. 1. "dr0,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x4 "DR1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x4 0.--31. 1. "dr1,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x8 "DR2,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x8 0.--31. 1. "dr2,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0xC "DR3,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0xC 0.--31. 1. "dr3,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x10 "DR4,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x10 0.--31. 1. "dr4,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x14 "DR5,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x14 0.--31. 1. "dr5,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x18 "DR6,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x18 0.--31. 1. "dr6,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x1C "DR7,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x1C 0.--31. 1. "dr7,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x20 "DR8,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x20 0.--31. 1. "dr8,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x24 "DR9,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x24 0.--31. 1. "dr9,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x28 "DR10,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x28 0.--31. 1. "dr10,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x2C "DR11,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x2C 0.--31. 1. "dr11,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x30 "DR12,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x30 0.--31. 1. "dr12,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x34 "DR13,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x34 0.--31. 1. "dr13,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x38 "DR14,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x38 0.--31. 1. "dr14,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x3C "DR15,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x3C 0.--31. 1. "dr15,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x40 "DR16,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x40 0.--31. 1. "dr16,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x44 "DR17,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x44 0.--31. 1. "dr17,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x48 "DR18,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x48 0.--31. 1. "dr18,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x4C "DR19,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x4C 0.--31. 1. "dr19,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x50 "DR20,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x50 0.--31. 1. "dr20,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x54 "DR21,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x54 0.--31. 1. "dr21,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x58 "DR22,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x58 0.--31. 1. "dr22,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x5C "DR23,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x5C 0.--31. 1. "dr23,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x60 "DR24,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x60 0.--31. 1. "dr24,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x64 "DR25,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x64 0.--31. 1. "dr25,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x68 "DR26,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x68 0.--31. 1. "dr26,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x6C "DR27,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x6C 0.--31. 1. "dr27,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x70 "DR28,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x70 0.--31. 1. "dr28,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x74 "DR29,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x74 0.--31. 1. "dr29,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x78 "DR30,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x78 0.--31. 1. "dr30,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x7C "DR31,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x7C 0.--31. 1. "dr31,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x80 "DR32,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x80 0.--31. 1. "dr32,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x84 "DR33,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x84 0.--31. 1. "dr33,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x88 "DR34,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x88 0.--31. 1. "dr34,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x8C "DR35,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x8C 0.--31. 1. "dr35,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x90 "RX_SAMPLE_DLY,RX Sample Delay."
hexmask.long.tbyte 0x90 8.--31. 1. "RSVD_RX_SAMPLE_DLY,Reserved bits - Read Only"
newline
hexmask.long.byte 0x90 0.--7. 1. "RSD,Rxd Sample Delay."
rgroup.long 0xF8++0x7
line.long 0x0 "RSVD_1,RSVD_1 - Reserved address location"
hexmask.long 0x0 0.--31. 1. "RSVD1,Reserved address location"
line.long 0x4 "RSVD_2,RSVD_2 - Reserved address location"
hexmask.long 0x4 0.--31. 1. "RSVD2,Reserved address location"
tree.end
tree.end
tree "SPTIMER (SP Timer Module)"
base ad:0x0
tree "SPTIMER0 (SP Timer0 Module)"
base ad:0xFFC03000
group.long 0x0++0x3
line.long 0x0 "TIMER1LOADCOUNT,Name: Timer1 Load Count Register"
hexmask.long 0x0 0.--31. 1. "TIMER1LOADCOUNT,Value to be loaded into Timer1. This is the value from which counting"
rgroup.long 0x4++0x3
line.long 0x0 "TIMER1CURRENTVAL,Name: Timer1 Current Value"
hexmask.long 0x0 0.--31. 1. "TIMER1CURRENTVAL,Current Value of Timer1. This register is supported only"
group.long 0x8++0x3
line.long 0x0 "TIMER1CONTROLREG,Name: Timer1 Control Register"
bitfld.long 0x0 2. "TIMER_INTERRUPT_MASK,Timer interrupt mask for Timer1." "0: not masked,1: masked"
bitfld.long 0x0 1. "TIMER_MODE,Timer mode for Timer1." "0: free_running mode,1: user_defined count mode"
newline
bitfld.long 0x0 0. "TIMER_ENABLE,Timer enable bit for Timer1." "0: disable,1: enable"
rgroup.long 0xC++0x7
line.long 0x0 "TIMER1EOI,Name: Timer1 End-of-Interrupt Register"
bitfld.long 0x0 0. "TIMER1EOI,Reading from this register" "0,1"
line.long 0x4 "TIMER1INTSTAT,Name: Timer1 Interrupt Status Register"
bitfld.long 0x4 0. "TIMER1INTSTAT,Contains the interrupt status for Timer1." "0,1"
rgroup.long 0xA0++0xF
line.long 0x0 "TIMERSINTSTAT,Name: Timers Interrupt Status Register"
bitfld.long 0x0 0. "TIMERSINTSTAT,Contains the interrupt status of all timers in the component. If a bit of" "0: either timer_intr or timer_intr_n is not active..,1: either timer_intr or timer_intr_n is active.."
line.long 0x4 "TIMERSEOI,Name: Timers End-of-Interrupt Register"
bitfld.long 0x4 0. "TIMERSEOI,Reading this register returns all zeroes (0) and clears all active" "0,1"
line.long 0x8 "TIMERSRAWINTSTAT,Name: Timers Raw Interrupt Status Register"
bitfld.long 0x8 0. "TIMERSRAWINTSTAT,The register contains the unmasked interrupt status of all timers in" "0: either timer_intr or timer_intr_n is not active..,1: either timer_intr or timer_intr_n is active.."
line.long 0xC "TIMERSCOMPVERSION,Name: Timers Component Version"
hexmask.long 0xC 0.--31. 1. "TIMERSCOMPVERSION,Current revision number of the DW_apb_timers component."
tree.end
tree "SPTIMER1 (SP Timer1 Module)"
base ad:0xFFC03100
group.long 0x0++0x3
line.long 0x0 "TIMER1LOADCOUNT,Name: Timer1 Load Count Register"
hexmask.long 0x0 0.--31. 1. "TIMER1LOADCOUNT,Value to be loaded into Timer1. This is the value from which counting"
rgroup.long 0x4++0x3
line.long 0x0 "TIMER1CURRENTVAL,Name: Timer1 Current Value"
hexmask.long 0x0 0.--31. 1. "TIMER1CURRENTVAL,Current Value of Timer1. This register is supported only"
group.long 0x8++0x3
line.long 0x0 "TIMER1CONTROLREG,Name: Timer1 Control Register"
bitfld.long 0x0 2. "TIMER_INTERRUPT_MASK,Timer interrupt mask for Timer1." "0: not masked,1: masked"
bitfld.long 0x0 1. "TIMER_MODE,Timer mode for Timer1." "0: free_running mode,1: user_defined count mode"
newline
bitfld.long 0x0 0. "TIMER_ENABLE,Timer enable bit for Timer1." "0: disable,1: enable"
rgroup.long 0xC++0x7
line.long 0x0 "TIMER1EOI,Name: Timer1 End-of-Interrupt Register"
bitfld.long 0x0 0. "TIMER1EOI,Reading from this register" "0,1"
line.long 0x4 "TIMER1INTSTAT,Name: Timer1 Interrupt Status Register"
bitfld.long 0x4 0. "TIMER1INTSTAT,Contains the interrupt status for Timer1." "0,1"
rgroup.long 0xA0++0xF
line.long 0x0 "TIMERSINTSTAT,Name: Timers Interrupt Status Register"
bitfld.long 0x0 0. "TIMERSINTSTAT,Contains the interrupt status of all timers in the component. If a bit of" "0: either timer_intr or timer_intr_n is not active..,1: either timer_intr or timer_intr_n is active.."
line.long 0x4 "TIMERSEOI,Name: Timers End-of-Interrupt Register"
bitfld.long 0x4 0. "TIMERSEOI,Reading this register returns all zeroes (0) and clears all active" "0,1"
line.long 0x8 "TIMERSRAWINTSTAT,Name: Timers Raw Interrupt Status Register"
bitfld.long 0x8 0. "TIMERSRAWINTSTAT,The register contains the unmasked interrupt status of all timers in" "0: either timer_intr or timer_intr_n is not active..,1: either timer_intr or timer_intr_n is active.."
line.long 0xC "TIMERSCOMPVERSION,Name: Timers Component Version"
hexmask.long 0xC 0.--31. 1. "TIMERSCOMPVERSION,Current revision number of the DW_apb_timers component."
tree.end
tree.end
tree "SYSMGR (System Manager Module)"
base ad:0xFFD12000
rgroup.long 0x0++0x7
line.long 0x0 "siliconid1,Specifies Silicon ID and revision number."
hexmask.long.word 0x0 16.--31. 1. "id,Silicon ID"
newline
hexmask.long.word 0x0 0.--15. 1. "rev,Silicon revision number."
line.long 0x4 "siliconid2,Reserved for future use."
hexmask.long 0x4 4.--31. 1. "rsv,Reserved for future use."
newline
hexmask.long.byte 0x4 0.--3. 1. "device_revision,SDM writes the device revision value from fuses to HPS secure manager."
group.long 0x8++0x3
line.long 0x0 "wddbg,Controls the behavior of the L4 watchdogs when the CPUs are in debug mode. These control registers are used to drive the pause input signal of the L4 watchdogs. Note that the watchdogs built into the MPU automatically are paused when their.."
hexmask.long.byte 0x0 24.--27. 1. "mode_3,Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index."
newline
hexmask.long.byte 0x0 16.--19. 1. "mode_2,Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index."
newline
hexmask.long.byte 0x0 8.--11. 1. "mode_1,Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index."
newline
hexmask.long.byte 0x0 0.--3. 1. "mode_0,Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index."
rgroup.long 0x10++0x3
line.long 0x0 "mpu_status,This is MPU control register"
bitfld.long 0x0 0. "uncorrerr,MPU sends 1 bit of ECC error signal(mpu_interrir_irq) to system manager. System manager synchronizes this" "0,1"
group.long 0x14++0x3
line.long 0x0 "mpu_ace,This is MPU control register"
hexmask.long.byte 0x0 8.--12. 1. "arqos,Sets the Priority of all write transactions originating from the MPU ACE socket. Priority is used by interconnects and memory scheduler on the HPS. Defaults to the highest priority (>=2)"
newline
hexmask.long.byte 0x0 0.--3. 1. "awqos,Sets the Priority of all write transactions originating from the MPU ACE socket. Priority is used by interconnects and memory scheduler on the HPS. Defaults to the highest priority (>=2)"
group.long 0x20++0x3F
line.long 0x0 "dma,Registers used by the DMA Controller. All fields are reset by a cold or warm reset."
hexmask.long.byte 0x0 24.--31. 1. "irq_ns,Specifies the security state of an event-interrupt resource."
newline
bitfld.long 0x0 16. "mgr_ns,Specifies the security state of the DMA manager thread." "0: assigns DMA manager to the Secure state,1: assigns DMA manager to the Non-secure state"
newline
bitfld.long 0x0 4. "chansel_1,Channel 1 selects between FPGA and I2C4_EMAC_RX" "0,1"
newline
bitfld.long 0x0 0. "chansel_0,Channel 0 selects between FPGA and I2C4_EMAC_TX" "0,1"
line.long 0x4 "dma_periph,Controls the security state of a peripheral request interface. Sampled by the DMA controller when it exits from reset."
hexmask.long 0x4 0.--31. 1. "ns,If bit index [x] is 0  the DMA controller assigns peripheral request interface x to the Secure state."
line.long 0x8 "sdmmc,Registers used by the SDMMC Controller. All fields are reset by a cold or warm reset."
bitfld.long 0x8 4.--6. "smplsel,Select which phase shift of the clock for cclk_in_sample." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0.--2. "drvsel,Select which phase shift of the clock for cclk_in_drv." "0,1,2,3,4,5,6,7"
line.long 0xC "sdmmc_l3master,Controls the L3 master HPROT AHB-Lite signal."
hexmask.long.word 0xC 16.--25. 1. "hauser22_13,bit[22:13] xsid"
newline
bitfld.long 0xC 8.--9. "hauser7_6,bit[7:6] domai" "0,1,2,3"
newline
bitfld.long 0xC 4.--5. "hauser0_1,bit[1] secure bit[0] allocate" "0,1,2,3"
newline
hexmask.long.byte 0xC 0.--3. 1. "hprot,HPROT[3] Cachable"
line.long 0x10 "nand_bootstrap,Bootstrap fields sampled by NAND Flash Controller when released from reset."
bitfld.long 0x10 28. "page512_x16,Reset value - 0" "0,1"
newline
bitfld.long 0x10 24. "page512,If 1  NAND device has a 512 byte page size." "0,1"
newline
bitfld.long 0x10 16. "tworowaddr,If 1  NAND device requires only 2 row address cycles instead of the normal 3 row address cycles." "0,1"
newline
bitfld.long 0x10 8. "noloadb0p0,If 1  inhibits NAND Flash Controller from loading page 0 of block 0 of the NAND device as part of the initialization procedure." "0,1"
newline
bitfld.long 0x10 0. "noinit,If 1  inhibits NAND Flash Controller from performing initialization when coming out of reset. Instead  software must program all registers pertaining to device parameters like page size  width  etc." "0,1"
line.long 0x14 "nand_l3master,Controls the L3 master ARCACHE and AWCACHE AXI signals."
bitfld.long 0x14 20.--22. "arprot,ar prot register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 16.--18. "awprot,aw prot register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 12.--13. "ardomain,ar domain register" "0,1,2,3"
newline
bitfld.long 0x14 8.--9. "awdomain,aw domain register" "0,1,2,3"
newline
hexmask.long.byte 0x14 4.--7. 1. "awcache_0,Specifies the value of the module AWCACHE signal."
newline
hexmask.long.byte 0x14 0.--3. 1. "arcache_0,Specifies the value of the module ARCACHE signal."
line.long 0x18 "usb0_l3master,Controls the L3 master HPROT AHB-Lite signal."
hexmask.long.word 0x18 16.--25. 1. "hauser22_13,hauser[22:13]"
newline
bitfld.long 0x18 12.--13. "hauser7_6,hauser[7:6]" "0,1,2,3"
newline
bitfld.long 0x18 9. "hauser_1,hauser[1] secure" "0,1"
newline
bitfld.long 0x18 8. "hauser_0,hauser[0] allocate" "0,1"
newline
hexmask.long.byte 0x18 0.--3. 1. "hprot,HPROT[0]: Opcode/Data"
line.long 0x1C "usb1_l3master,Controls the L3 master HPROT AHB-Lite signal."
hexmask.long.word 0x1C 16.--25. 1. "hauser22_13,hauser[22:13] sid"
newline
bitfld.long 0x1C 12.--13. "hauser7_6,hauser[7:6] domain" "0,1,2,3"
newline
bitfld.long 0x1C 9. "hauser_1,hauser[1] secure" "0,1"
newline
bitfld.long 0x1C 8. "hauser_0,hauser[0] allocate" "0,1"
newline
hexmask.long.byte 0x1C 0.--3. 1. "hprot,HPROT[0]: Opcode/Data"
line.long 0x20 "emac_global,Controls the L3 master ARCACHE and AWCACHE AXI signals."
bitfld.long 0x20 0. "ptp_clk_sel,Selects the source of the PTP reference clock between emac_ptp_clk from the Clock Manager or f2s_ptp_ref_clk from the FPGA Fabric." "0,1"
line.long 0x24 "emac0,Registers used by the EMAC. All fields are reset by a cold or warm reset."
bitfld.long 0x24 31. "axi_disable,AXI Disable" "0,1"
newline
bitfld.long 0x24 30. "sbd_data_endianness,Specifies the endianness of the EMAC DMA transfers." "0,1"
newline
bitfld.long 0x24 27.--29. "awprot,Specifies the values of the 2 EMAC AWCACHE signals." "0: Secure Normal(non-privileged) access,1: Secure Privileged access,2: Non-Secure Normal(non-privileged) access,3: Non-Secure Privileged access,?,?,?,?"
newline
bitfld.long 0x24 24.--26. "arprot,Specifies the values of the ARPROT signals." "0: Secure Normal(non-privileged) access,1: Secure Privileged access,2: Non-Secure Normal(non-privileged) access,3: Non-Secure Privileged access,?,?,?,?"
newline
hexmask.long.byte 0x24 20.--23. 1. "awcache,Specifies the values of the 2 EMAC AWCACHE signals."
newline
hexmask.long.byte 0x24 16.--19. 1. "arcache,Specifies the values of the 2 EMAC ARCACHE signals."
newline
bitfld.long 0x24 8. "ptp_ref_sel,This field selects if the Timestamp reference is internally or externally generated. EMAC0 may be the master to generate the timestamp for EMAC1 and EMAC2. EMAC0 must be set to Internal Timestamp. EMAC1/2 may be set to either Internal or.." "0,1"
newline
bitfld.long 0x24 0.--1. "phy_intf_sel,PHY Interface Select" "0,1,2,3"
line.long 0x28 "emac1,Registers used by the EMAC. All fields are reset by a cold or warm reset."
bitfld.long 0x28 31. "axi_disable,AXI Disable" "0,1"
newline
bitfld.long 0x28 30. "sbd_data_endianness,Specifies the endianness of the EMAC DMA transfers." "0,1"
newline
bitfld.long 0x28 27.--29. "awprot,Specifies the values of the 2 EMAC AWCACHE signals." "0: Secure Normal(non-privileged) access,1: Secure Privileged access,2: Non-Secure Normal(non-privileged) access,3: Non-Secure Privileged access,?,?,?,?"
newline
bitfld.long 0x28 24.--26. "arprot,Specifies the values of the ARPROT signals." "0: Secure Normal(non-privileged) access,1: Secure Privileged access,2: Non-Secure Normal(non-privileged) access,3: Non-Secure Privileged access,?,?,?,?"
newline
hexmask.long.byte 0x28 20.--23. 1. "awcache,Specifies the values of the 2 EMAC AWCACHE signals."
newline
hexmask.long.byte 0x28 16.--19. 1. "arcache,Specifies the values of the 2 EMAC ARCACHE signals."
newline
bitfld.long 0x28 8. "ptp_ref_sel,This field selects if the Timestamp reference is internally or externally generated. EMAC0 may be the master to generate the timestamp for EMAC1 and EMAC2. EMAC0 must be set to Internal Timestamp. EMAC1/2 may be set to either Internal or.." "0,1"
newline
bitfld.long 0x28 0.--1. "phy_intf_sel,PHY Interface Select" "0,1,2,3"
line.long 0x2C "emac2,Registers used by the EMAC. All fields are reset by a cold or warm reset."
bitfld.long 0x2C 31. "axi_disable,AXI Disable" "0,1"
newline
bitfld.long 0x2C 30. "sbd_data_endianness,Specifies the endianness of the EMAC DMA transfers." "0,1"
newline
bitfld.long 0x2C 27.--29. "awprot,Specifies the values of the 2 EMAC AWCACHE signals." "0: Secure Normal(non-privileged) access,1: Secure Privileged access,2: Non-Secure Normal(non-privileged) access,3: Non-Secure Privileged access,?,?,?,?"
newline
bitfld.long 0x2C 24.--26. "arprot,Specifies the values of the ARPROT signals." "0: Secure Normal(non-privileged) access,1: Secure Privileged access,2: Non-Secure Normal(non-privileged) access,3: Non-Secure Privileged access,?,?,?,?"
newline
hexmask.long.byte 0x2C 20.--23. 1. "awcache,Specifies the values of the 2 EMAC AWCACHE signals."
newline
hexmask.long.byte 0x2C 16.--19. 1. "arcache,Specifies the values of the 2 EMAC ARCACHE signals."
newline
bitfld.long 0x2C 8. "ptp_ref_sel,This field selects if the Timestamp reference is internally or externally generated. EMAC0 may be the master to generate the timestamp for EMAC1 and EMAC2. EMAC0 must be set to Internal Timestamp. EMAC1/2 may be set to either Internal or.." "0,1"
newline
bitfld.long 0x2C 0.--1. "phy_intf_sel,PHY Interface Select" "0,1,2,3"
line.long 0x30 "emac0_ace,The EMAC0 ACE-lite control register"
hexmask.long.word 0x30 20.--29. 1. "awsid,awsid"
newline
hexmask.long.word 0x30 8.--17. 1. "arsid,arsid"
newline
bitfld.long 0x30 4.--5. "awdomain,aw domain" "0,1,2,3"
newline
bitfld.long 0x30 0.--1. "ardomain,ar domain" "0,1,2,3"
line.long 0x34 "emac1_ace,The EMAC1 ACE-lite control register"
hexmask.long.word 0x34 20.--29. 1. "awsid,awsid register"
newline
hexmask.long.word 0x34 8.--17. 1. "arsid,arsid register"
newline
bitfld.long 0x34 4.--5. "awdomain,aw domain register" "0,1,2,3"
newline
bitfld.long 0x34 0.--1. "ardomain,ar domain register" "0,1,2,3"
line.long 0x38 "emac2_ace,The EMAC2 ACE-lite control register"
hexmask.long.word 0x38 20.--29. 1. "awsid,awsid register"
newline
hexmask.long.word 0x38 8.--17. 1. "arsid,arsid register"
newline
bitfld.long 0x38 4.--5. "awdomain,aw domain register" "0,1,2,3"
newline
bitfld.long 0x38 0.--1. "ardomain,ar domain register" "0,1,2,3"
line.long 0x3C "nand_axuser,The NAND ACE-lite contrl a(w/r)user register"
hexmask.long.word 0x3C 16.--25. 1. "aruser,aw user register sid"
newline
hexmask.long.word 0x3C 0.--9. 1. "awuser,ar user register sid"
group.long 0x68++0x13
line.long 0x0 "fpgaintf_en_1,Used to disable individual interfaces between the FPGA and HPS."
bitfld.long 0x0 24. "ctmtrigger,Used to disable the FPGA Fabric from sending triggers to HPS debug logic. Note that this doesn't prevent the HPS debug logic from sending triggers to the FPGA Fabric." "0,1"
newline
bitfld.long 0x0 16. "stmevent,Used to disable the STM event interface. This interface allows logic in the FPGA fabric to trigger events to the STM debug module in the HPS." "0,1"
newline
bitfld.long 0x0 8. "dbgapb,Used to disable the debug APB interface. This interface allows the HPS debug logic to communicate with debug APB slaves in the FPGA fabric." "0,1"
newline
bitfld.long 0x0 4. "traceout,Gates the isolator of CoreSight" "0,1"
newline
bitfld.long 0x0 0. "tracein,Gates the isolator of TPIU" "0,1"
line.long 0x4 "fpgaintf_en_2,Used to disable individual interfaces between the FPGA and HPS."
bitfld.long 0x4 24. "spim_1,Used to disable signals from the FPGA fabric to the SPI master modules that could potentially interfere with their normal operation." "0,1"
newline
bitfld.long 0x4 16. "spim_0,Used to disable signals from the FPGA fabric to the SPI master modules that could potentially interfere with their normal operation." "0,1"
newline
bitfld.long 0x4 8. "sdmmc,Used to disable signals from the FPGA fabric to the SD/MMC controller module that could potentially interfere with its normal operation." "0,1"
newline
bitfld.long 0x4 4. "nand,Used to disable signals from the FPGA fabric to the NAND flash controller module that could potentially interfere with its normal operation." "0,1"
line.long 0x8 "fpgaintf_en_3,Used to disable individual interfaces between the FPGA and HPS."
bitfld.long 0x8 16. "emac_2,Used to disable signals from the FPGA fabric to the EMAC modules that could potentially interfere with their normal operation." "0,1"
newline
bitfld.long 0x8 8. "emac_1,Used to disable signals from the FPGA fabric to the EMAC modules that could potentially interfere with their normal operation." "0,1"
newline
bitfld.long 0x8 0. "emac_0,Used to disable signals from the FPGA fabric to the EMAC modules that could potentially interfere with their normal operation." "0,1"
line.long 0xC "dma_l3master,Register for ACE-lite control - dma_l3master"
hexmask.long.word 0xC 16.--25. 1. "aruser,ar sid register"
newline
bitfld.long 0xC 14.--15. "ardomain,ar domain regisger" "0,1,2,3"
newline
bitfld.long 0xC 12.--13. "awdomain,aw domain register" "0,1,2,3"
newline
hexmask.long.word 0xC 0.--9. 1. "awuser,aw sid register"
line.long 0x10 "etr_l3master,Register for ACE-lite control - etr_l3master"
hexmask.long.word 0x10 16.--25. 1. "aruser,ar sid register"
newline
bitfld.long 0x10 14.--15. "ardomain,ar domain regisger" "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "awdomain,aw domain register" "0,1,2,3"
newline
hexmask.long.word 0x10 0.--9. 1. "awuser,aw sid register"
rgroup.long 0x80++0x7
line.long 0x0 "sec_ctrl_slt,This is the clock selection register. The APS oscillator selection is read only register. This value is driven from secure manager FS."
bitfld.long 0x0 0. "val,1 bit register to read the value secure clock selection: secure internal oscillator and eosc1" "0,1"
line.long 0x4 "osc_trim,This is the osc_trim register to show internal oscillator"
hexmask.long.byte 0x4 0.--7. 1. "val,RO 8 bit register that shows trim of internal oscillator"
group.long 0x90++0xB
line.long 0x0 "ecc_intmask_value,ECC interrupt mask register."
bitfld.long 0x0 17. "ddr1," "0,1"
newline
bitfld.long 0x0 16. "ddr0," "0,1"
newline
bitfld.long 0x0 15. "sdmmcb," "0,1"
newline
bitfld.long 0x0 14. "sdmmca," "0,1"
newline
bitfld.long 0x0 13. "nand_rd," "0,1"
newline
bitfld.long 0x0 12. "nand_wr," "0,1"
newline
bitfld.long 0x0 11. "nand_buf," "0,1"
newline
bitfld.long 0x0 10. "dma," "0,1"
newline
bitfld.long 0x0 9. "emac2_tx," "0,1"
newline
bitfld.long 0x0 8. "emac2_rx," "0,1"
newline
bitfld.long 0x0 7. "emac1_tx," "0,1"
newline
bitfld.long 0x0 6. "emac1_rx," "0,1"
newline
bitfld.long 0x0 5. "emac0_tx," "0,1"
newline
bitfld.long 0x0 4. "emac0_rx," "0,1"
newline
bitfld.long 0x0 3. "usb1," "0,1"
newline
bitfld.long 0x0 2. "usb0," "0,1"
newline
bitfld.long 0x0 1. "ocram," "0,1"
line.long 0x4 "ecc_intmask_set,Write 1 to set a specific modules interrupt mask."
bitfld.long 0x4 17. "ddr1," "0,1"
newline
bitfld.long 0x4 16. "ddr0," "0,1"
newline
bitfld.long 0x4 15. "sdmmcb," "0,1"
newline
bitfld.long 0x4 14. "sdmmca," "0,1"
newline
bitfld.long 0x4 13. "nand_rd," "0,1"
newline
bitfld.long 0x4 12. "nand_wr," "0,1"
newline
bitfld.long 0x4 11. "nand_buf," "0,1"
newline
bitfld.long 0x4 10. "dma," "0,1"
newline
bitfld.long 0x4 9. "emac2_tx," "0,1"
newline
bitfld.long 0x4 8. "emac2_rx," "0,1"
newline
bitfld.long 0x4 7. "emac1_tx," "0,1"
newline
bitfld.long 0x4 6. "emac1_rx," "0,1"
newline
bitfld.long 0x4 5. "emac0_tx," "0,1"
newline
bitfld.long 0x4 4. "emac0_rx," "0,1"
newline
bitfld.long 0x4 3. "usb1," "0,1"
newline
bitfld.long 0x4 2. "usb0," "0,1"
newline
bitfld.long 0x4 1. "ocram," "0,1"
line.long 0x8 "ecc_intmask_clr,Write 1 to Clear a specific modules interrupt mask."
eventfld.long 0x8 17. "ddr1," "0,1"
newline
eventfld.long 0x8 16. "ddr0," "0,1"
newline
eventfld.long 0x8 15. "sdmmcb," "0,1"
newline
eventfld.long 0x8 14. "sdmmca," "0,1"
newline
eventfld.long 0x8 13. "nand_rd," "0,1"
newline
eventfld.long 0x8 12. "nand_wr," "0,1"
newline
eventfld.long 0x8 11. "nand_buf," "0,1"
newline
eventfld.long 0x8 10. "dma," "0,1"
newline
eventfld.long 0x8 9. "emac2_tx," "0,1"
newline
eventfld.long 0x8 8. "emac2_rx," "0,1"
newline
eventfld.long 0x8 7. "emac1_tx," "0,1"
newline
eventfld.long 0x8 6. "emac1_rx," "0,1"
newline
eventfld.long 0x8 5. "emac0_tx," "0,1"
newline
eventfld.long 0x8 4. "emac0_rx," "0,1"
newline
eventfld.long 0x8 3. "usb1," "0,1"
newline
eventfld.long 0x8 2. "usb0," "0,1"
newline
eventfld.long 0x8 1. "ocram," "0,1"
rgroup.long 0x9C++0x7
line.long 0x0 "ecc_intstatus_serr,ECC single bit error status of individual modules."
bitfld.long 0x0 17. "ddr1," "0,1"
newline
bitfld.long 0x0 16. "ddr0," "0,1"
newline
bitfld.long 0x0 15. "sdmmcb," "0,1"
newline
bitfld.long 0x0 14. "sdmmca," "0,1"
newline
bitfld.long 0x0 13. "nand_rd," "0,1"
newline
bitfld.long 0x0 12. "nand_wr," "0,1"
newline
bitfld.long 0x0 11. "nand_buf," "0,1"
newline
bitfld.long 0x0 10. "dma," "0,1"
newline
bitfld.long 0x0 9. "emac2_tx," "0,1"
newline
bitfld.long 0x0 8. "emac2_rx," "0,1"
newline
bitfld.long 0x0 7. "emac1_tx," "0,1"
newline
bitfld.long 0x0 6. "emac1_rx," "0,1"
newline
bitfld.long 0x0 5. "emac0_tx," "0,1"
newline
bitfld.long 0x0 4. "emac0_rx," "0,1"
newline
bitfld.long 0x0 3. "usb1," "0,1"
newline
bitfld.long 0x0 2. "usb0," "0,1"
newline
bitfld.long 0x0 1. "ocram," "0,1"
line.long 0x4 "ecc_intstatus_derr,ECC double bit error status of individual modules."
bitfld.long 0x4 17. "ddr1," "0,1"
newline
bitfld.long 0x4 16. "ddr0," "0,1"
newline
bitfld.long 0x4 15. "sdmmcb," "0,1"
newline
bitfld.long 0x4 14. "sdmmca," "0,1"
newline
bitfld.long 0x4 13. "nand_rd," "0,1"
newline
bitfld.long 0x4 12. "nand_wr," "0,1"
newline
bitfld.long 0x4 11. "nand_buf," "0,1"
newline
bitfld.long 0x4 10. "dma," "0,1"
newline
bitfld.long 0x4 9. "emac2_tx," "0,1"
newline
bitfld.long 0x4 8. "emac2_rx," "0,1"
newline
bitfld.long 0x4 7. "emac1_tx," "0,1"
newline
bitfld.long 0x4 6. "emac1_rx," "0,1"
newline
bitfld.long 0x4 5. "emac0_tx," "0,1"
newline
bitfld.long 0x4 4. "emac0_rx," "0,1"
newline
bitfld.long 0x4 3. "usb1," "0,1"
newline
bitfld.long 0x4 2. "usb0," "0,1"
newline
bitfld.long 0x4 1. "ocram," "0,1"
group.long 0xB0++0x3
line.long 0x0 "noc_addr_remap,The noc_addr_repmap register to view the HPS memory map (specifically on-chip RAM)"
bitfld.long 0x0 0. "sdm2hps_be,0: lowest 1 MB of SDM2HPS_BE memory view decodes to on-chip RAM. The rest is DRAM." "0: lowest 1 MB of SDM2HPS_BE memory view decodes to..,1: lowest 1 MB of SDM2HPS_BE memory view decodes to.."
rgroup.long 0xB4++0x3
line.long 0x0 "hmc_clk,HMC Clock and IO Lock status indicator"
bitfld.long 0x0 18. "io_cpa_lock_c,CPA Lock C status" "0,1"
newline
bitfld.long 0x0 17. "io_cpa_lock_b,CPA Lock B status" "0,1"
newline
bitfld.long 0x0 16. "io_cpa_lock_a,CPA Lock A status" "0,1"
newline
bitfld.long 0x0 10. "io_pll_lock_c,PLL Lock C status" "0,1"
newline
bitfld.long 0x0 9. "io_pll_lock_b,PLL Lock B status" "0,1"
newline
bitfld.long 0x0 8. "io_pll_lock_a,PLL Lock A status" "0,1"
newline
bitfld.long 0x0 0. "status,HMC clock status: HMC clock not running = 0; HMC clock running = 1." "0,1"
group.long 0xB8++0x3
line.long 0x0 "io_pa_ctrl,HMC clock status indicator"
bitfld.long 0x0 2. "io_pa_reset_n_c,This will allow HPS software to control when it wants to start receiving the IO48 clock." "0,1"
newline
bitfld.long 0x0 1. "io_pa_reset_n_b,This will allow HPS software to control when it wants to start receiving the IO48 clock." "0,1"
newline
bitfld.long 0x0 0. "io_pa_reset_n_a,This will allow HPS software to control when it wants to start receiving the IO48 clock." "0,1"
group.long 0xC0++0xB
line.long 0x0 "noc_timeout,"
bitfld.long 0x0 0. "en,NOC Timeout Enable. Write 1 to enable noc timeout." "0,1"
line.long 0x4 "noc_idlereq_set,Set IDLE request to each NOC master."
bitfld.long 0x4 4. "lwsoc2fpga," "0,1"
newline
bitfld.long 0x4 0. "soc2fpga," "0,1"
line.long 0x8 "noc_idlereq_clr,Clear IDLE request to each NOC master."
eventfld.long 0x8 4. "lwsoc2fpga," "0,1"
newline
eventfld.long 0x8 0. "soc2fpga," "0,1"
wgroup.long 0xCC++0x3
line.long 0x0 "noc_idlereq_value,IDLE request to each NOC master."
bitfld.long 0x0 4. "lwsoc2fpga," "0,1"
newline
bitfld.long 0x0 0. "soc2fpga," "0,1"
rgroup.long 0xD0++0x7
line.long 0x0 "noc_idleack,Idle acknowledge value from NOC Masters. This is asserted (value 1 in the field) in response to the IDLE requests asserted by software."
bitfld.long 0x0 4. "lwsoc2fpga," "0,1"
newline
bitfld.long 0x0 0. "soc2fpga," "0,1"
line.long 0x4 "noc_idlestatus,Status of IDLE from the NOC masters. A 1 in the field means the specific master is idle."
bitfld.long 0x4 4. "lwsoc2fpga," "0,1"
newline
bitfld.long 0x4 0. "soc2fpga," "0,1"
group.long 0xD8++0x3
line.long 0x0 "fpga2soc_ctrl,"
bitfld.long 0x0 0. "allow_secure,0 - All Transactions from FPGA2SOC is converted to be Non-Secure" "0,1"
rgroup.long 0xDC++0x3
line.long 0x0 "fpga_config,FPGA configuration read only register"
bitfld.long 0x0 1. "early_usermode,FGPA configuration complete" "0,1"
newline
bitfld.long 0x0 0. "fpga_complete,FGPA configuration complete" "0,1"
group.long 0xE0++0x7
line.long 0x0 "iocsrclk_gate,IO Clock control"
bitfld.long 0x0 16. "tilec,Tile C clock control" "0,1"
newline
bitfld.long 0x0 8. "tileb,Tile B clock control" "0,1"
newline
bitfld.long 0x0 0. "tilea,Tile A clock control" "0,1"
line.long 0x4 "gpo,Provides a low-latency. low-performance. and simple way to drive general-purpose signals to the FPGA fabric"
hexmask.long 0x4 0.--31. 1. "val,Drives s2f_gp[31:0] with specified value. When read  returns the current value being driven to the FPGA fabric"
rgroup.long 0xE8++0x3
line.long 0x0 "gpi,Provides a low-latency. low-performance. and simple way to read general-purpose signals driven from the FPGA fabric."
hexmask.long 0x0 0.--31. 1. "val,The value being driven from the FPGA fabric on f2s_gp[31:0]. If the FPGA is not in User Mode  the value of this field is undefined."
group.long 0xF0++0xB
line.long 0x0 "mpu,Provides a low-latency. low-performance. and simple way to read general-purpose signals driven from the FPGA fabric."
bitfld.long 0x0 0. "mpu_cfgsdisable,CFGSDISABLE is typically de-asserted (0) from reset until Secure software has configured the GIC-400 and then subsequently asserted permanently to provide extra security." "0,1"
line.long 0x4 "sdm_hps_spare,SDM to HPS spare signals are mapped to a system manager register. PSI side band signals will set these bits and HPS SW will clear this register"
eventfld.long 0x4 11. "bit_11," "0,1"
newline
eventfld.long 0x4 10. "bit_10," "0,1"
newline
eventfld.long 0x4 9. "bit_9," "0,1"
newline
eventfld.long 0x4 8. "bit_8," "0,1"
newline
eventfld.long 0x4 7. "bit_7," "0,1"
newline
eventfld.long 0x4 6. "bit_6," "0,1"
newline
eventfld.long 0x4 5. "bit_5," "0,1"
newline
eventfld.long 0x4 4. "bit_4," "0,1"
newline
eventfld.long 0x4 3. "bit_3," "0,1"
newline
eventfld.long 0x4 2. "bit_2," "0,1"
newline
eventfld.long 0x4 1. "bit_1," "0,1"
newline
eventfld.long 0x4 0. "bit_0," "0,1"
line.long 0x8 "hps_sdm_spare,HPS to SDM spare signals are mapped to a system manager register."
hexmask.long.tbyte 0x8 0.--18. 1. "val,write to this register will drive the value PSI spare ports."
group.long 0x200++0x2B
line.long 0x0 "boot_scratch_cold0,Boot scratch register 0"
hexmask.long 0x0 0.--31. 1. "val,the scratch register value"
line.long 0x4 "boot_scratch_cold1,Boot scratch register 1"
hexmask.long 0x4 0.--31. 1. "val,the scratch register value"
line.long 0x8 "boot_scratch_cold2,Boot scratch register 2"
hexmask.long 0x8 0.--31. 1. "val,the scratch register value"
line.long 0xC "boot_scratch_cold3,Boot scratch register 3"
hexmask.long 0xC 0.--31. 1. "val,the scratch register value"
line.long 0x10 "boot_scratch_cold4,Boot scratch register 4"
hexmask.long 0x10 0.--31. 1. "val,the scratch register value"
line.long 0x14 "boot_scratch_cold5,Boot scratch register 5"
hexmask.long 0x14 0.--31. 1. "val,the scratch register value"
line.long 0x18 "boot_scratch_cold6,Boot scratch register 6"
hexmask.long 0x18 0.--31. 1. "val,the scratch register value"
line.long 0x1C "boot_scratch_cold7,Boot scratch register 7"
hexmask.long 0x1C 0.--31. 1. "val,the scratch register value"
line.long 0x20 "boot_scratch_cold8,Boot scratch register 8"
hexmask.long 0x20 0.--31. 1. "val,the scratch register value"
line.long 0x24 "boot_scratch_cold9,Boot scratch register 9"
hexmask.long 0x24 0.--31. 1. "val,the scratch register value"
line.long 0x28 "mpfe_config,MPFE Interface Select"
hexmask.long.word 0x28 2.--15. 1. "mpfeintfcsel_spare_out,The spare MPFE - HPS spare ports and registers are implemented as a contingency in the event MPFE-Fabric-IO96-HMC issues arise that need management by HPS or SDM firmware."
newline
bitfld.long 0x28 1. "mpfeintfcsel_C,To select if Fabric bypass path or MPFE path of signals conect to Tile C" "0: select the Fabric bypass path for the IO48 in..,1: select the MPFE path for the IO48 in the IO96.."
newline
bitfld.long 0x28 0. "mpfeintfcsel_AB,To select if Fabric bypass path or MPFE path of signals conect to Tile A/B" "0: select the Fabric bypass path for the IO48 in..,1: select the MPFE path for the IO48 in the IO96.."
rgroup.long 0x22C++0x3
line.long 0x0 "mpfe_status,"
hexmask.long.word 0x0 0.--15. 1. "mpfeintfc_stat_spare_in,"
tree.end
tree "TCU (TCU Configuration)"
base ad:0xFA000000
group.long 0x0++0x7
line.long 0x0 "SMMU_SCR0,Provides top-level control of the SMMU."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
rbitfld.long 0x0 21. "SMCFCFG," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "BSU," "0,1,2,3"
bitfld.long 0x0 13. "FB," "0,1"
newline
bitfld.long 0x0 12. "PTM," "0,1"
bitfld.long 0x0 10. "USFCFG," "0,1"
rbitfld.long 0x0 9. "GSE," "0,1"
newline
rbitfld.long 0x0 8. "STALLD," "0,1"
bitfld.long 0x0 6.--7. "TRANSIENTCFG," "0,1,2,3"
rbitfld.long 0x0 5. "GCFGFIE," "0,1"
newline
rbitfld.long 0x0 4. "GCFGFRE," "0,1"
bitfld.long 0x0 2. "GFIE," "0,1"
bitfld.long 0x0 1. "GFRE," "0,1"
newline
bitfld.long 0x0 0. "CLIENTPD," "0,1"
line.long 0x4 "SMMU_SCR1,Provides top-level Secure control of the SMMU."
rbitfld.long 0x4 28. "NSCAFRO," "0,1"
bitfld.long 0x4 27. "SPMEN," "0,1"
bitfld.long 0x4 26. "SIF," "0,1"
newline
bitfld.long 0x4 25. "GEFRO," "0,1"
bitfld.long 0x4 24. "GASRAE," "0,1"
hexmask.long.byte 0x4 16.--23. 1. "NSNUMIRPTO,"
newline
hexmask.long.byte 0x4 8.--14. 1. "NSNUMSMRGO,"
hexmask.long.byte 0x4 0.--5. 1. "NSNUMCBO,"
group.long 0x10++0x3
line.long 0x0 "SMMU_SACR,Provides IMPLEMENTATION DEFINED functionality."
bitfld.long 0x0 27. "NORMALIZE," "0,1"
bitfld.long 0x0 26. "CACHE_LOCK," "0,1"
bitfld.long 0x0 16. "PAGESIZE," "0,1"
newline
bitfld.long 0x0 10. "S2CRB_TLBEN," "0,1"
bitfld.long 0x0 9. "MMUDISB_TLBEN," "0,1"
bitfld.long 0x0 8. "SMTNMB_TLBEN," "0,1"
newline
bitfld.long 0x0 2. "S1WC2EN," "0,1"
rgroup.long 0x20++0xB
line.long 0x0 "SMMU_SIDR0,Provides SMMU capability information."
bitfld.long 0x0 31. "SES," "0,1"
bitfld.long 0x0 30. "S1TS," "0,1"
bitfld.long 0x0 29. "S2TS," "0,1"
newline
bitfld.long 0x0 28. "NTS," "0,1"
bitfld.long 0x0 27. "SMS," "0,1"
bitfld.long 0x0 26. "ATOSNS," "0,1"
newline
bitfld.long 0x0 24.--25. "PTFS," "0,1,2,3"
hexmask.long.byte 0x0 16.--23. 1. "NUMIRPT,"
bitfld.long 0x0 14. "CTTW," "0,1"
newline
bitfld.long 0x0 13. "BTM," "0,1"
hexmask.long.byte 0x0 9.--12. 1. "NUMSIDB,"
hexmask.long.byte 0x0 0.--7. 1. "NUMSMRG,"
line.long 0x4 "SMMU_SIDR1,Provides SMMU capability information."
bitfld.long 0x4 31. "PAGESIZE," "0,1"
bitfld.long 0x4 28.--30. "NUMPAGENDXB," "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 16.--23. 1. "NUMS2CB,"
newline
bitfld.long 0x4 15. "SMCD," "0,1"
bitfld.long 0x4 12. "SSDTP," "0,1"
hexmask.long.byte 0x4 8.--11. 1. "NUMSSDNDXB,"
newline
hexmask.long.byte 0x4 0.--7. 1. "NUMCB,"
line.long 0x8 "SMMU_SIDR2,Provides SMMU capability information."
bitfld.long 0x8 14. "PTFSV8_64Kb," "0,1"
bitfld.long 0x8 13. "PTFSV8_16Kb," "0,1"
bitfld.long 0x8 12. "TFSV8_4Kb," "0,1"
newline
hexmask.long.byte 0x8 8.--11. 1. "UBS,"
hexmask.long.byte 0x8 4.--7. 1. "OAS,"
hexmask.long.byte 0x8 0.--3. 1. "IAS,"
rgroup.long 0x3C++0x3
line.long 0x0 "SMMU_SIDR7,Provides SMMU capability information."
hexmask.long.byte 0x0 4.--7. 1. "MAJOR,"
hexmask.long.byte 0x0 0.--3. 1. "MINOR,"
group.long 0x40++0x7
line.long 0x0 "SMMU_SGFAR_low,Contains the input address of an erroneous request reported by SMMU_sGFSR."
hexmask.long 0x0 0.--31. 1. "FADDR,"
line.long 0x4 "SMMU_SGFAR_high,Contains the input address of an erroneous request reported by SMMU_sGFSR."
hexmask.long.tbyte 0x4 0.--16. 1. "FADDR,"
wgroup.long 0x48++0x7
line.long 0x0 "SMMU_SGFSR,Gives the fault status for each of the following possible faults."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "PF," "0,1"
newline
bitfld.long 0x0 6. "EF," "0,1"
bitfld.long 0x0 5. "CAF," "0,1"
bitfld.long 0x0 4. "UCIF," "0,1"
newline
bitfld.long 0x0 3. "UCBF," "0,1"
bitfld.long 0x0 2. "SMCF," "0,1"
bitfld.long 0x0 1. "USF," "0,1"
newline
bitfld.long 0x0 0. "ICF," "0,1"
line.long 0x4 "SMMU_SGFSRRESTORE,Restores the state of SMMU_sGFSR. after a reset. for example."
bitfld.long 0x4 31. "MULTI," "0,1"
bitfld.long 0x4 8. "UUT," "0,1"
bitfld.long 0x4 7. "PF," "0,1"
newline
bitfld.long 0x4 6. "EF," "0,1"
bitfld.long 0x4 5. "CAF," "0,1"
bitfld.long 0x4 4. "UCIF," "0,1"
newline
bitfld.long 0x4 3. "UCBF," "0,1"
bitfld.long 0x4 2. "SMCF," "0,1"
bitfld.long 0x4 1. "USF," "0,1"
newline
bitfld.long 0x4 0. "ICF," "0,1"
group.long 0x50++0x7
line.long 0x0 "SMMU_SGFSYNR0,Contains fault syndrome information relating to SMMU_sGFSR."
rbitfld.long 0x0 6. "ATS," "0,1"
bitfld.long 0x0 5. "NSATTR," "0,1"
bitfld.long 0x0 4. "NSSTATE," "0,1"
newline
bitfld.long 0x0 3. "IND," "0,1"
bitfld.long 0x0 2. "PNU," "0,1"
bitfld.long 0x0 1. "WNR," "0,1"
line.long 0x4 "SMMU_SGFSYNR1,Contains fault syndrome information relating to SMMU_sGFSR."
hexmask.long.word 0x4 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x4 0.--14. 1. "StreamID,"
wgroup.long 0x60++0xB
line.long 0x0 "SMMU_STLBIALL,Invalidates all unlocked Secure entries in the TLB."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_TLBIVMID,Invalidates all Non-secure non-Hyp TLB entries having the specified VMID."
hexmask.long.byte 0x4 0.--7. 1. "VMID,"
line.long 0x8 "SMMU_TLBIALLNSNH,Invalidates all Non-secure non-Hyp tagged entries in the TLB."
hexmask.long 0x8 0.--31. 1. "bits,"
wgroup.long 0x70++0x3
line.long 0x0 "SMMU_STLBGSYNC,Starts a global synchronization operation that ensures the completion of any previously accepted TLB Invalidate operation. As a minimum. the operation applies to the specified security state. and includes all TLB Invalidate operations.."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x74++0x3
line.long 0x0 "SMMU_STLBGSTATUS,Gives the status of a TLB maintenance operation."
bitfld.long 0x0 0. "GSACTIVE," "0,1"
group.long 0x80++0x3
line.long 0x0 "SMMU_DBGRPTRTBU,Address of TLB entry in a specific TBU."
bitfld.long 0x0 24.--26. "TBU_ID," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0 4.--15. 1. "TLB_Pointer,"
hexmask.long.byte 0x0 0.--3. 1. "TLB_Entry_Pointer,"
rgroup.long 0x84++0x3
line.long 0x0 "SMMU_DBGRDATATBU,TLB entry data addressed by TBU debug read pointer."
hexmask.long 0x0 0.--31. 1. "bits,"
group.long 0x88++0x3
line.long 0x0 "SMMU_DBGRPTRTCU,Address of an entry from a specific cache in TCU."
bitfld.long 0x0 26.--27. "DATASRC," "0,1,2,3"
bitfld.long 0x0 24.--25. "WAY_RAM," "0,1,2,3"
hexmask.long.byte 0x0 4.--10. 1. "TLB_Pointer,"
newline
hexmask.long.byte 0x0 0.--3. 1. "TLB_Entry_Pointer,"
rgroup.long 0x8C++0x3
line.long 0x0 "SMMU_DBGRDATATCU,Cache entry data addressed by TCU debug read pointer."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0xA0++0xF
line.long 0x0 "SMMU_STLBIVALM_low,Invalidates all unlocked entries associated with MONC banks. that match the specified virtual address."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_STLBIVALM_high,Invalidates all unlocked entries associated with MONC banks. that match the specified virtual address."
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_STLBIVAM_low,Invalidates all unlocked entries associated with MONC banks. that match the specified virtual address."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_STLBIVAM_high,Invalidates all unlocked entries associated with MONC banks. that match the specified virtual address."
hexmask.long.byte 0xC 0.--4. 1. "Address,"
wgroup.long 0xBC++0x3
line.long 0x0 "SMMU_STLBIALLM,Invalidates all unlocked entries associated with MONC banks in the TLB."
hexmask.long 0x0 0.--31. 1. "bits,"
group.long 0x400++0x3
line.long 0x0 "SMMU_NSCR0,Provides top-level control of the SMMU."
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
newline
rbitfld.long 0x0 21. "SMCFCFG," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
newline
bitfld.long 0x0 14.--15. "BSU," "0,1,2,3"
bitfld.long 0x0 13. "FB," "0,1"
bitfld.long 0x0 12. "PTM," "0,1"
newline
bitfld.long 0x0 11. "VMIDPNE," "0,1"
bitfld.long 0x0 10. "USFCFG," "0,1"
rbitfld.long 0x0 9. "GSE," "0,1"
newline
rbitfld.long 0x0 8. "STALLD," "0,1"
bitfld.long 0x0 6.--7. "TRANSIENTCFG," "0,1,2,3"
rbitfld.long 0x0 5. "GCFGFIE," "0,1"
newline
rbitfld.long 0x0 4. "GCFGFRE," "0,1"
bitfld.long 0x0 2. "GFIE," "0,1"
bitfld.long 0x0 1. "GFRE," "0,1"
newline
bitfld.long 0x0 0. "CLIENTPD," "0,1"
group.long 0x410++0x3
line.long 0x0 "SMMU_NSACR,Provides IMPLEMENTATION DEFINED functionality."
bitfld.long 0x0 26. "CACHE_LOCK," "0,1"
bitfld.long 0x0 25. "DP4K_TBUDISB," "0,1"
bitfld.long 0x0 24. "DP4K_TCUDISB," "0,1"
newline
bitfld.long 0x0 10. "S2CRB_TLBEN," "0,1"
bitfld.long 0x0 9. "MMUDISB_TLBEN," "0,1"
bitfld.long 0x0 8. "SMTNMB_TLBEN," "0,1"
newline
bitfld.long 0x0 4. "IPA2PA_CEN," "0,1"
bitfld.long 0x0 3. "S2WC2EN," "0,1"
bitfld.long 0x0 2. "S1WC2EN," "0,1"
group.long 0x440++0x7
line.long 0x0 "SMMU_NSGFAR_low,Contains the input address of an erroneous request reported by SMMU_GFSR."
hexmask.long 0x0 0.--31. 1. "FADDR,"
line.long 0x4 "SMMU_NSGFAR_high,Contains the input address of an erroneous request reported by SMMU_GFSR."
hexmask.long.tbyte 0x4 0.--16. 1. "FADDR,"
wgroup.long 0x448++0x7
line.long 0x0 "SMMU_NSGFSR,Gives the fault status for each of the following possible faults."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 6. "EF," "0,1"
newline
bitfld.long 0x0 5. "CAF," "0,1"
bitfld.long 0x0 4. "UCIF," "0,1"
bitfld.long 0x0 3. "UCBF," "0,1"
newline
bitfld.long 0x0 2. "SMCF," "0,1"
bitfld.long 0x0 1. "USF," "0,1"
bitfld.long 0x0 0. "ICF," "0,1"
line.long 0x4 "SMMU_NSGFSRRESTORE,Restores the state of SMMU_GFSR. after a reset. for example."
bitfld.long 0x4 31. "MULTI," "0,1"
bitfld.long 0x4 8. "UUT," "0,1"
bitfld.long 0x4 6. "EF," "0,1"
newline
bitfld.long 0x4 5. "CAF," "0,1"
bitfld.long 0x4 4. "UCIF," "0,1"
bitfld.long 0x4 3. "UCBF," "0,1"
newline
bitfld.long 0x4 2. "SMCF," "0,1"
bitfld.long 0x4 1. "USF," "0,1"
bitfld.long 0x4 0. "ICF," "0,1"
group.long 0x450++0x7
line.long 0x0 "SMMU_NSGFSYNR0,Contains fault syndrome information relating to SMMU_GFSR."
rbitfld.long 0x0 6. "ATS," "0,1"
bitfld.long 0x0 3. "IND," "0,1"
bitfld.long 0x0 2. "PNU," "0,1"
newline
bitfld.long 0x0 1. "WNR," "0,1"
bitfld.long 0x0 0. "Nested," "0,1"
line.long 0x4 "SMMU_NSGFSYNDR1,Contains fault syndrome information relating to SMMU_GFSR."
hexmask.long.word 0x4 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x4 0.--14. 1. "StreamID,"
wgroup.long 0x470++0x3
line.long 0x0 "SMMU_NSTLBGSYNC,Starts a global synchronization operation that ensures the completion of any previously accepted TLB Invalidate operation. As a minimum. the operation applies to the specified security state. and includes all TLB Invalidate operations.."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x474++0x3
line.long 0x0 "SMMU_NSTLBGSTATUS,Gives the status of a TLB maintenance operation."
bitfld.long 0x0 0. "GSACTIVE," "0,1"
group.long 0x800++0xFF
line.long 0x0 "SMMU_SMR0,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x0 31. "VALID," "0,1"
hexmask.long.word 0x0 16.--30. 1. "MASK,"
hexmask.long.word 0x0 0.--14. 1. "ID,"
line.long 0x4 "SMMU_SMR1,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x4 31. "VALID," "0,1"
hexmask.long.word 0x4 16.--30. 1. "MASK,"
hexmask.long.word 0x4 0.--14. 1. "ID,"
line.long 0x8 "SMMU_SMR2,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x8 31. "VALID," "0,1"
hexmask.long.word 0x8 16.--30. 1. "MASK,"
hexmask.long.word 0x8 0.--14. 1. "ID,"
line.long 0xC "SMMU_SMR3,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xC 31. "VALID," "0,1"
hexmask.long.word 0xC 16.--30. 1. "MASK,"
hexmask.long.word 0xC 0.--14. 1. "ID,"
line.long 0x10 "SMMU_SMR4,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x10 31. "VALID," "0,1"
hexmask.long.word 0x10 16.--30. 1. "MASK,"
hexmask.long.word 0x10 0.--14. 1. "ID,"
line.long 0x14 "SMMU_SMR5,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x14 31. "VALID," "0,1"
hexmask.long.word 0x14 16.--30. 1. "MASK,"
hexmask.long.word 0x14 0.--14. 1. "ID,"
line.long 0x18 "SMMU_SMR6,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x18 31. "VALID," "0,1"
hexmask.long.word 0x18 16.--30. 1. "MASK,"
hexmask.long.word 0x18 0.--14. 1. "ID,"
line.long 0x1C "SMMU_SMR7,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x1C 31. "VALID," "0,1"
hexmask.long.word 0x1C 16.--30. 1. "MASK,"
hexmask.long.word 0x1C 0.--14. 1. "ID,"
line.long 0x20 "SMMU_SMR8,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x20 31. "VALID," "0,1"
hexmask.long.word 0x20 16.--30. 1. "MASK,"
hexmask.long.word 0x20 0.--14. 1. "ID,"
line.long 0x24 "SMMU_SMR9,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x24 31. "VALID," "0,1"
hexmask.long.word 0x24 16.--30. 1. "MASK,"
hexmask.long.word 0x24 0.--14. 1. "ID,"
line.long 0x28 "SMMU_SMR10,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x28 31. "VALID," "0,1"
hexmask.long.word 0x28 16.--30. 1. "MASK,"
hexmask.long.word 0x28 0.--14. 1. "ID,"
line.long 0x2C "SMMU_SMR11,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x2C 31. "VALID," "0,1"
hexmask.long.word 0x2C 16.--30. 1. "MASK,"
hexmask.long.word 0x2C 0.--14. 1. "ID,"
line.long 0x30 "SMMU_SMR12,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x30 31. "VALID," "0,1"
hexmask.long.word 0x30 16.--30. 1. "MASK,"
hexmask.long.word 0x30 0.--14. 1. "ID,"
line.long 0x34 "SMMU_SMR13,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x34 31. "VALID," "0,1"
hexmask.long.word 0x34 16.--30. 1. "MASK,"
hexmask.long.word 0x34 0.--14. 1. "ID,"
line.long 0x38 "SMMU_SMR14,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x38 31. "VALID," "0,1"
hexmask.long.word 0x38 16.--30. 1. "MASK,"
hexmask.long.word 0x38 0.--14. 1. "ID,"
line.long 0x3C "SMMU_SMR15,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x3C 31. "VALID," "0,1"
hexmask.long.word 0x3C 16.--30. 1. "MASK,"
hexmask.long.word 0x3C 0.--14. 1. "ID,"
line.long 0x40 "SMMU_SMR16,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x40 31. "VALID," "0,1"
hexmask.long.word 0x40 16.--30. 1. "MASK,"
hexmask.long.word 0x40 0.--14. 1. "ID,"
line.long 0x44 "SMMU_SMR17,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x44 31. "VALID," "0,1"
hexmask.long.word 0x44 16.--30. 1. "MASK,"
hexmask.long.word 0x44 0.--14. 1. "ID,"
line.long 0x48 "SMMU_SMR18,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x48 31. "VALID," "0,1"
hexmask.long.word 0x48 16.--30. 1. "MASK,"
hexmask.long.word 0x48 0.--14. 1. "ID,"
line.long 0x4C "SMMU_SMR19,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x4C 31. "VALID," "0,1"
hexmask.long.word 0x4C 16.--30. 1. "MASK,"
hexmask.long.word 0x4C 0.--14. 1. "ID,"
line.long 0x50 "SMMU_SMR20,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x50 31. "VALID," "0,1"
hexmask.long.word 0x50 16.--30. 1. "MASK,"
hexmask.long.word 0x50 0.--14. 1. "ID,"
line.long 0x54 "SMMU_SMR21,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x54 31. "VALID," "0,1"
hexmask.long.word 0x54 16.--30. 1. "MASK,"
hexmask.long.word 0x54 0.--14. 1. "ID,"
line.long 0x58 "SMMU_SMR22,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x58 31. "VALID," "0,1"
hexmask.long.word 0x58 16.--30. 1. "MASK,"
hexmask.long.word 0x58 0.--14. 1. "ID,"
line.long 0x5C "SMMU_SMR23,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x5C 31. "VALID," "0,1"
hexmask.long.word 0x5C 16.--30. 1. "MASK,"
hexmask.long.word 0x5C 0.--14. 1. "ID,"
line.long 0x60 "SMMU_SMR24,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x60 31. "VALID," "0,1"
hexmask.long.word 0x60 16.--30. 1. "MASK,"
hexmask.long.word 0x60 0.--14. 1. "ID,"
line.long 0x64 "SMMU_SMR25,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x64 31. "VALID," "0,1"
hexmask.long.word 0x64 16.--30. 1. "MASK,"
hexmask.long.word 0x64 0.--14. 1. "ID,"
line.long 0x68 "SMMU_SMR26,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x68 31. "VALID," "0,1"
hexmask.long.word 0x68 16.--30. 1. "MASK,"
hexmask.long.word 0x68 0.--14. 1. "ID,"
line.long 0x6C "SMMU_SMR27,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x6C 31. "VALID," "0,1"
hexmask.long.word 0x6C 16.--30. 1. "MASK,"
hexmask.long.word 0x6C 0.--14. 1. "ID,"
line.long 0x70 "SMMU_SMR28,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x70 31. "VALID," "0,1"
hexmask.long.word 0x70 16.--30. 1. "MASK,"
hexmask.long.word 0x70 0.--14. 1. "ID,"
line.long 0x74 "SMMU_SMR29,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x74 31. "VALID," "0,1"
hexmask.long.word 0x74 16.--30. 1. "MASK,"
hexmask.long.word 0x74 0.--14. 1. "ID,"
line.long 0x78 "SMMU_SMR30,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x78 31. "VALID," "0,1"
hexmask.long.word 0x78 16.--30. 1. "MASK,"
hexmask.long.word 0x78 0.--14. 1. "ID,"
line.long 0x7C "SMMU_SMR31,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x7C 31. "VALID," "0,1"
hexmask.long.word 0x7C 16.--30. 1. "MASK,"
hexmask.long.word 0x7C 0.--14. 1. "ID,"
line.long 0x80 "SMMU_SMR32,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x80 31. "VALID," "0,1"
hexmask.long.word 0x80 16.--30. 1. "MASK,"
hexmask.long.word 0x80 0.--14. 1. "ID,"
line.long 0x84 "SMMU_SMR33,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x84 31. "VALID," "0,1"
hexmask.long.word 0x84 16.--30. 1. "MASK,"
hexmask.long.word 0x84 0.--14. 1. "ID,"
line.long 0x88 "SMMU_SMR34,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x88 31. "VALID," "0,1"
hexmask.long.word 0x88 16.--30. 1. "MASK,"
hexmask.long.word 0x88 0.--14. 1. "ID,"
line.long 0x8C "SMMU_SMR35,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x8C 31. "VALID," "0,1"
hexmask.long.word 0x8C 16.--30. 1. "MASK,"
hexmask.long.word 0x8C 0.--14. 1. "ID,"
line.long 0x90 "SMMU_SMR36,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x90 31. "VALID," "0,1"
hexmask.long.word 0x90 16.--30. 1. "MASK,"
hexmask.long.word 0x90 0.--14. 1. "ID,"
line.long 0x94 "SMMU_SMR37,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x94 31. "VALID," "0,1"
hexmask.long.word 0x94 16.--30. 1. "MASK,"
hexmask.long.word 0x94 0.--14. 1. "ID,"
line.long 0x98 "SMMU_SMR38,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x98 31. "VALID," "0,1"
hexmask.long.word 0x98 16.--30. 1. "MASK,"
hexmask.long.word 0x98 0.--14. 1. "ID,"
line.long 0x9C "SMMU_SMR39,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0x9C 31. "VALID," "0,1"
hexmask.long.word 0x9C 16.--30. 1. "MASK,"
hexmask.long.word 0x9C 0.--14. 1. "ID,"
line.long 0xA0 "SMMU_SMR40,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xA0 31. "VALID," "0,1"
hexmask.long.word 0xA0 16.--30. 1. "MASK,"
hexmask.long.word 0xA0 0.--14. 1. "ID,"
line.long 0xA4 "SMMU_SMR41,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xA4 31. "VALID," "0,1"
hexmask.long.word 0xA4 16.--30. 1. "MASK,"
hexmask.long.word 0xA4 0.--14. 1. "ID,"
line.long 0xA8 "SMMU_SMR42,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xA8 31. "VALID," "0,1"
hexmask.long.word 0xA8 16.--30. 1. "MASK,"
hexmask.long.word 0xA8 0.--14. 1. "ID,"
line.long 0xAC "SMMU_SMR43,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xAC 31. "VALID," "0,1"
hexmask.long.word 0xAC 16.--30. 1. "MASK,"
hexmask.long.word 0xAC 0.--14. 1. "ID,"
line.long 0xB0 "SMMU_SMR44,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xB0 31. "VALID," "0,1"
hexmask.long.word 0xB0 16.--30. 1. "MASK,"
hexmask.long.word 0xB0 0.--14. 1. "ID,"
line.long 0xB4 "SMMU_SMR45,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xB4 31. "VALID," "0,1"
hexmask.long.word 0xB4 16.--30. 1. "MASK,"
hexmask.long.word 0xB4 0.--14. 1. "ID,"
line.long 0xB8 "SMMU_SMR46,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xB8 31. "VALID," "0,1"
hexmask.long.word 0xB8 16.--30. 1. "MASK,"
hexmask.long.word 0xB8 0.--14. 1. "ID,"
line.long 0xBC "SMMU_SMR47,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xBC 31. "VALID," "0,1"
hexmask.long.word 0xBC 16.--30. 1. "MASK,"
hexmask.long.word 0xBC 0.--14. 1. "ID,"
line.long 0xC0 "SMMU_SMR48,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xC0 31. "VALID," "0,1"
hexmask.long.word 0xC0 16.--30. 1. "MASK,"
hexmask.long.word 0xC0 0.--14. 1. "ID,"
line.long 0xC4 "SMMU_SMR49,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xC4 31. "VALID," "0,1"
hexmask.long.word 0xC4 16.--30. 1. "MASK,"
hexmask.long.word 0xC4 0.--14. 1. "ID,"
line.long 0xC8 "SMMU_SMR50,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xC8 31. "VALID," "0,1"
hexmask.long.word 0xC8 16.--30. 1. "MASK,"
hexmask.long.word 0xC8 0.--14. 1. "ID,"
line.long 0xCC "SMMU_SMR51,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xCC 31. "VALID," "0,1"
hexmask.long.word 0xCC 16.--30. 1. "MASK,"
hexmask.long.word 0xCC 0.--14. 1. "ID,"
line.long 0xD0 "SMMU_SMR52,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xD0 31. "VALID," "0,1"
hexmask.long.word 0xD0 16.--30. 1. "MASK,"
hexmask.long.word 0xD0 0.--14. 1. "ID,"
line.long 0xD4 "SMMU_SMR53,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xD4 31. "VALID," "0,1"
hexmask.long.word 0xD4 16.--30. 1. "MASK,"
hexmask.long.word 0xD4 0.--14. 1. "ID,"
line.long 0xD8 "SMMU_SMR54,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xD8 31. "VALID," "0,1"
hexmask.long.word 0xD8 16.--30. 1. "MASK,"
hexmask.long.word 0xD8 0.--14. 1. "ID,"
line.long 0xDC "SMMU_SMR55,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xDC 31. "VALID," "0,1"
hexmask.long.word 0xDC 16.--30. 1. "MASK,"
hexmask.long.word 0xDC 0.--14. 1. "ID,"
line.long 0xE0 "SMMU_SMR56,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xE0 31. "VALID," "0,1"
hexmask.long.word 0xE0 16.--30. 1. "MASK,"
hexmask.long.word 0xE0 0.--14. 1. "ID,"
line.long 0xE4 "SMMU_SMR57,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xE4 31. "VALID," "0,1"
hexmask.long.word 0xE4 16.--30. 1. "MASK,"
hexmask.long.word 0xE4 0.--14. 1. "ID,"
line.long 0xE8 "SMMU_SMR58,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xE8 31. "VALID," "0,1"
hexmask.long.word 0xE8 16.--30. 1. "MASK,"
hexmask.long.word 0xE8 0.--14. 1. "ID,"
line.long 0xEC "SMMU_SMR59,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xEC 31. "VALID," "0,1"
hexmask.long.word 0xEC 16.--30. 1. "MASK,"
hexmask.long.word 0xEC 0.--14. 1. "ID,"
line.long 0xF0 "SMMU_SMR60,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xF0 31. "VALID," "0,1"
hexmask.long.word 0xF0 16.--30. 1. "MASK,"
hexmask.long.word 0xF0 0.--14. 1. "ID,"
line.long 0xF4 "SMMU_SMR61,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xF4 31. "VALID," "0,1"
hexmask.long.word 0xF4 16.--30. 1. "MASK,"
hexmask.long.word 0xF4 0.--14. 1. "ID,"
line.long 0xF8 "SMMU_SMR62,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xF8 31. "VALID," "0,1"
hexmask.long.word 0xF8 16.--30. 1. "MASK,"
hexmask.long.word 0xF8 0.--14. 1. "ID,"
line.long 0xFC "SMMU_SMR63,Matches a transaction with a particular Stream mapping register group."
bitfld.long 0xFC 31. "VALID," "0,1"
hexmask.long.word 0xFC 16.--30. 1. "MASK,"
hexmask.long.word 0xFC 0.--14. 1. "ID,"
group.long 0xC00++0xFF
line.long 0x0 "SMMU_S2CR0,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x0 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 27. "INSTCFG_1," "0,1"
bitfld.long 0x0 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x0 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x0 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x0 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x0 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x0 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x0 11. "MTCFG," "0,1"
bitfld.long 0x0 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x0 0.--7. 1. "CBNDX_VMID,"
line.long 0x4 "SMMU_S2CR1,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x4 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x4 27. "INSTCFG_1," "0,1"
bitfld.long 0x4 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x4 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x4 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x4 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x4 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x4 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x4 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x4 11. "MTCFG," "0,1"
bitfld.long 0x4 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x4 0.--7. 1. "CBNDX_VMID,"
line.long 0x8 "SMMU_S2CR2,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x8 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x8 27. "INSTCFG_1," "0,1"
bitfld.long 0x8 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x8 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x8 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x8 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x8 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x8 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x8 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x8 11. "MTCFG," "0,1"
bitfld.long 0x8 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x8 0.--7. 1. "CBNDX_VMID,"
line.long 0xC "SMMU_S2CR3,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xC 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xC 27. "INSTCFG_1," "0,1"
bitfld.long 0xC 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xC 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xC 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xC 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xC 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xC 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xC 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xC 11. "MTCFG," "0,1"
bitfld.long 0xC 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xC 0.--7. 1. "CBNDX_VMID,"
line.long 0x10 "SMMU_S2CR4,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x10 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x10 27. "INSTCFG_1," "0,1"
bitfld.long 0x10 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x10 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x10 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x10 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x10 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x10 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x10 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x10 11. "MTCFG," "0,1"
bitfld.long 0x10 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x10 0.--7. 1. "CBNDX_VMID,"
line.long 0x14 "SMMU_S2CR5,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x14 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x14 27. "INSTCFG_1," "0,1"
bitfld.long 0x14 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x14 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x14 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x14 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x14 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x14 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x14 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x14 11. "MTCFG," "0,1"
bitfld.long 0x14 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x14 0.--7. 1. "CBNDX_VMID,"
line.long 0x18 "SMMU_S2CR6,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x18 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x18 27. "INSTCFG_1," "0,1"
bitfld.long 0x18 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x18 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x18 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x18 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x18 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x18 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x18 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x18 11. "MTCFG," "0,1"
bitfld.long 0x18 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x18 0.--7. 1. "CBNDX_VMID,"
line.long 0x1C "SMMU_S2CR7,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x1C 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x1C 27. "INSTCFG_1," "0,1"
bitfld.long 0x1C 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x1C 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x1C 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x1C 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x1C 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x1C 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x1C 11. "MTCFG," "0,1"
bitfld.long 0x1C 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x1C 0.--7. 1. "CBNDX_VMID,"
line.long 0x20 "SMMU_S2CR8,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x20 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x20 27. "INSTCFG_1," "0,1"
bitfld.long 0x20 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x20 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x20 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x20 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x20 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x20 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x20 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x20 11. "MTCFG," "0,1"
bitfld.long 0x20 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x20 0.--7. 1. "CBNDX_VMID,"
line.long 0x24 "SMMU_S2CR9,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x24 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x24 27. "INSTCFG_1," "0,1"
bitfld.long 0x24 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x24 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x24 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x24 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x24 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x24 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x24 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x24 11. "MTCFG," "0,1"
bitfld.long 0x24 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x24 0.--7. 1. "CBNDX_VMID,"
line.long 0x28 "SMMU_S2CR10,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x28 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x28 27. "INSTCFG_1," "0,1"
bitfld.long 0x28 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x28 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x28 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x28 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x28 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x28 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x28 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x28 11. "MTCFG," "0,1"
bitfld.long 0x28 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x28 0.--7. 1. "CBNDX_VMID,"
line.long 0x2C "SMMU_S2CR11,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x2C 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x2C 27. "INSTCFG_1," "0,1"
bitfld.long 0x2C 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x2C 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x2C 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x2C 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x2C 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x2C 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x2C 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x2C 11. "MTCFG," "0,1"
bitfld.long 0x2C 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x2C 0.--7. 1. "CBNDX_VMID,"
line.long 0x30 "SMMU_S2CR12,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x30 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x30 27. "INSTCFG_1," "0,1"
bitfld.long 0x30 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x30 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x30 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x30 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x30 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x30 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x30 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x30 11. "MTCFG," "0,1"
bitfld.long 0x30 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x30 0.--7. 1. "CBNDX_VMID,"
line.long 0x34 "SMMU_S2CR13,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x34 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x34 27. "INSTCFG_1," "0,1"
bitfld.long 0x34 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x34 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x34 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x34 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x34 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x34 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x34 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x34 11. "MTCFG," "0,1"
bitfld.long 0x34 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x34 0.--7. 1. "CBNDX_VMID,"
line.long 0x38 "SMMU_S2CR14,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x38 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x38 27. "INSTCFG_1," "0,1"
bitfld.long 0x38 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x38 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x38 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x38 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x38 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x38 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x38 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x38 11. "MTCFG," "0,1"
bitfld.long 0x38 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x38 0.--7. 1. "CBNDX_VMID,"
line.long 0x3C "SMMU_S2CR15,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x3C 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x3C 27. "INSTCFG_1," "0,1"
bitfld.long 0x3C 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x3C 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x3C 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x3C 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x3C 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x3C 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x3C 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x3C 11. "MTCFG," "0,1"
bitfld.long 0x3C 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x3C 0.--7. 1. "CBNDX_VMID,"
line.long 0x40 "SMMU_S2CR16,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x40 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x40 27. "INSTCFG_1," "0,1"
bitfld.long 0x40 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x40 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x40 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x40 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x40 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x40 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x40 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x40 11. "MTCFG," "0,1"
bitfld.long 0x40 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x40 0.--7. 1. "CBNDX_VMID,"
line.long 0x44 "SMMU_S2CR17,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x44 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x44 27. "INSTCFG_1," "0,1"
bitfld.long 0x44 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x44 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x44 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x44 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x44 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x44 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x44 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x44 11. "MTCFG," "0,1"
bitfld.long 0x44 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x44 0.--7. 1. "CBNDX_VMID,"
line.long 0x48 "SMMU_S2CR18,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x48 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x48 27. "INSTCFG_1," "0,1"
bitfld.long 0x48 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x48 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x48 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x48 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x48 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x48 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x48 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x48 11. "MTCFG," "0,1"
bitfld.long 0x48 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x48 0.--7. 1. "CBNDX_VMID,"
line.long 0x4C "SMMU_S2CR19,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x4C 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x4C 27. "INSTCFG_1," "0,1"
bitfld.long 0x4C 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x4C 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x4C 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x4C 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x4C 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x4C 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x4C 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x4C 11. "MTCFG," "0,1"
bitfld.long 0x4C 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x4C 0.--7. 1. "CBNDX_VMID,"
line.long 0x50 "SMMU_S2CR20,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x50 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x50 27. "INSTCFG_1," "0,1"
bitfld.long 0x50 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x50 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x50 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x50 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x50 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x50 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x50 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x50 11. "MTCFG," "0,1"
bitfld.long 0x50 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x50 0.--7. 1. "CBNDX_VMID,"
line.long 0x54 "SMMU_S2CR21,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x54 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x54 27. "INSTCFG_1," "0,1"
bitfld.long 0x54 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x54 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x54 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x54 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x54 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x54 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x54 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x54 11. "MTCFG," "0,1"
bitfld.long 0x54 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x54 0.--7. 1. "CBNDX_VMID,"
line.long 0x58 "SMMU_S2CR22,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x58 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x58 27. "INSTCFG_1," "0,1"
bitfld.long 0x58 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x58 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x58 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x58 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x58 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x58 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x58 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x58 11. "MTCFG," "0,1"
bitfld.long 0x58 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x58 0.--7. 1. "CBNDX_VMID,"
line.long 0x5C "SMMU_S2CR23,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x5C 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x5C 27. "INSTCFG_1," "0,1"
bitfld.long 0x5C 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x5C 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x5C 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x5C 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x5C 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x5C 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x5C 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x5C 11. "MTCFG," "0,1"
bitfld.long 0x5C 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x5C 0.--7. 1. "CBNDX_VMID,"
line.long 0x60 "SMMU_S2CR24,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x60 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x60 27. "INSTCFG_1," "0,1"
bitfld.long 0x60 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x60 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x60 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x60 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x60 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x60 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x60 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x60 11. "MTCFG," "0,1"
bitfld.long 0x60 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x60 0.--7. 1. "CBNDX_VMID,"
line.long 0x64 "SMMU_S2CR25,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x64 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x64 27. "INSTCFG_1," "0,1"
bitfld.long 0x64 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x64 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x64 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x64 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x64 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x64 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x64 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x64 11. "MTCFG," "0,1"
bitfld.long 0x64 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x64 0.--7. 1. "CBNDX_VMID,"
line.long 0x68 "SMMU_S2CR26,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x68 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x68 27. "INSTCFG_1," "0,1"
bitfld.long 0x68 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x68 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x68 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x68 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x68 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x68 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x68 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x68 11. "MTCFG," "0,1"
bitfld.long 0x68 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x68 0.--7. 1. "CBNDX_VMID,"
line.long 0x6C "SMMU_S2CR27,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x6C 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x6C 27. "INSTCFG_1," "0,1"
bitfld.long 0x6C 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x6C 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x6C 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x6C 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x6C 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x6C 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x6C 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x6C 11. "MTCFG," "0,1"
bitfld.long 0x6C 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x6C 0.--7. 1. "CBNDX_VMID,"
line.long 0x70 "SMMU_S2CR28,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x70 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x70 27. "INSTCFG_1," "0,1"
bitfld.long 0x70 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x70 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x70 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x70 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x70 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x70 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x70 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x70 11. "MTCFG," "0,1"
bitfld.long 0x70 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x70 0.--7. 1. "CBNDX_VMID,"
line.long 0x74 "SMMU_S2CR29,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x74 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x74 27. "INSTCFG_1," "0,1"
bitfld.long 0x74 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x74 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x74 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x74 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x74 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x74 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x74 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x74 11. "MTCFG," "0,1"
bitfld.long 0x74 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x74 0.--7. 1. "CBNDX_VMID,"
line.long 0x78 "SMMU_S2CR30,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x78 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x78 27. "INSTCFG_1," "0,1"
bitfld.long 0x78 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x78 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x78 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x78 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x78 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x78 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x78 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x78 11. "MTCFG," "0,1"
bitfld.long 0x78 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x78 0.--7. 1. "CBNDX_VMID,"
line.long 0x7C "SMMU_S2CR31,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x7C 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x7C 27. "INSTCFG_1," "0,1"
bitfld.long 0x7C 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x7C 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x7C 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x7C 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x7C 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x7C 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x7C 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x7C 11. "MTCFG," "0,1"
bitfld.long 0x7C 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x7C 0.--7. 1. "CBNDX_VMID,"
line.long 0x80 "SMMU_S2CR32,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x80 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x80 27. "INSTCFG_1," "0,1"
bitfld.long 0x80 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x80 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x80 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x80 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x80 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x80 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x80 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x80 11. "MTCFG," "0,1"
bitfld.long 0x80 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x80 0.--7. 1. "CBNDX_VMID,"
line.long 0x84 "SMMU_S2CR33,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x84 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x84 27. "INSTCFG_1," "0,1"
bitfld.long 0x84 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x84 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x84 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x84 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x84 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x84 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x84 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x84 11. "MTCFG," "0,1"
bitfld.long 0x84 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x84 0.--7. 1. "CBNDX_VMID,"
line.long 0x88 "SMMU_S2CR34,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x88 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x88 27. "INSTCFG_1," "0,1"
bitfld.long 0x88 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x88 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x88 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x88 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x88 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x88 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x88 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x88 11. "MTCFG," "0,1"
bitfld.long 0x88 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x88 0.--7. 1. "CBNDX_VMID,"
line.long 0x8C "SMMU_S2CR35,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x8C 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x8C 27. "INSTCFG_1," "0,1"
bitfld.long 0x8C 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x8C 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x8C 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x8C 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x8C 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x8C 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x8C 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x8C 11. "MTCFG," "0,1"
bitfld.long 0x8C 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x8C 0.--7. 1. "CBNDX_VMID,"
line.long 0x90 "SMMU_S2CR36,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x90 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x90 27. "INSTCFG_1," "0,1"
bitfld.long 0x90 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x90 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x90 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x90 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x90 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x90 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x90 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x90 11. "MTCFG," "0,1"
bitfld.long 0x90 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x90 0.--7. 1. "CBNDX_VMID,"
line.long 0x94 "SMMU_S2CR37,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x94 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x94 27. "INSTCFG_1," "0,1"
bitfld.long 0x94 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x94 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x94 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x94 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x94 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x94 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x94 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x94 11. "MTCFG," "0,1"
bitfld.long 0x94 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x94 0.--7. 1. "CBNDX_VMID,"
line.long 0x98 "SMMU_S2CR38,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x98 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x98 27. "INSTCFG_1," "0,1"
bitfld.long 0x98 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x98 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x98 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x98 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x98 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x98 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x98 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x98 11. "MTCFG," "0,1"
bitfld.long 0x98 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x98 0.--7. 1. "CBNDX_VMID,"
line.long 0x9C "SMMU_S2CR39,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0x9C 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x9C 27. "INSTCFG_1," "0,1"
bitfld.long 0x9C 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0x9C 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0x9C 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x9C 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x9C 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0x9C 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x9C 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0x9C 11. "MTCFG," "0,1"
bitfld.long 0x9C 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0x9C 0.--7. 1. "CBNDX_VMID,"
line.long 0xA0 "SMMU_S2CR40,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xA0 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xA0 27. "INSTCFG_1," "0,1"
bitfld.long 0xA0 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xA0 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xA0 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xA0 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xA0 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xA0 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xA0 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xA0 11. "MTCFG," "0,1"
bitfld.long 0xA0 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xA0 0.--7. 1. "CBNDX_VMID,"
line.long 0xA4 "SMMU_S2CR41,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xA4 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xA4 27. "INSTCFG_1," "0,1"
bitfld.long 0xA4 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xA4 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xA4 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xA4 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xA4 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xA4 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xA4 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xA4 11. "MTCFG," "0,1"
bitfld.long 0xA4 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xA4 0.--7. 1. "CBNDX_VMID,"
line.long 0xA8 "SMMU_S2CR42,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xA8 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xA8 27. "INSTCFG_1," "0,1"
bitfld.long 0xA8 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xA8 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xA8 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xA8 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xA8 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xA8 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xA8 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xA8 11. "MTCFG," "0,1"
bitfld.long 0xA8 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xA8 0.--7. 1. "CBNDX_VMID,"
line.long 0xAC "SMMU_S2CR43,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xAC 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xAC 27. "INSTCFG_1," "0,1"
bitfld.long 0xAC 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xAC 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xAC 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xAC 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xAC 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xAC 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xAC 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xAC 11. "MTCFG," "0,1"
bitfld.long 0xAC 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xAC 0.--7. 1. "CBNDX_VMID,"
line.long 0xB0 "SMMU_S2CR44,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xB0 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xB0 27. "INSTCFG_1," "0,1"
bitfld.long 0xB0 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xB0 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xB0 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xB0 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xB0 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xB0 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xB0 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xB0 11. "MTCFG," "0,1"
bitfld.long 0xB0 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xB0 0.--7. 1. "CBNDX_VMID,"
line.long 0xB4 "SMMU_S2CR45,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xB4 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xB4 27. "INSTCFG_1," "0,1"
bitfld.long 0xB4 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xB4 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xB4 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xB4 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xB4 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xB4 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xB4 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xB4 11. "MTCFG," "0,1"
bitfld.long 0xB4 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xB4 0.--7. 1. "CBNDX_VMID,"
line.long 0xB8 "SMMU_S2CR46,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xB8 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xB8 27. "INSTCFG_1," "0,1"
bitfld.long 0xB8 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xB8 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xB8 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xB8 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xB8 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xB8 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xB8 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xB8 11. "MTCFG," "0,1"
bitfld.long 0xB8 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xB8 0.--7. 1. "CBNDX_VMID,"
line.long 0xBC "SMMU_S2CR47,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xBC 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xBC 27. "INSTCFG_1," "0,1"
bitfld.long 0xBC 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xBC 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xBC 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xBC 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xBC 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xBC 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xBC 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xBC 11. "MTCFG," "0,1"
bitfld.long 0xBC 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xBC 0.--7. 1. "CBNDX_VMID,"
line.long 0xC0 "SMMU_S2CR48,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xC0 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xC0 27. "INSTCFG_1," "0,1"
bitfld.long 0xC0 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xC0 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xC0 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xC0 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xC0 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xC0 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xC0 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xC0 11. "MTCFG," "0,1"
bitfld.long 0xC0 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xC0 0.--7. 1. "CBNDX_VMID,"
line.long 0xC4 "SMMU_S2CR49,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xC4 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xC4 27. "INSTCFG_1," "0,1"
bitfld.long 0xC4 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xC4 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xC4 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xC4 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xC4 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xC4 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xC4 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xC4 11. "MTCFG," "0,1"
bitfld.long 0xC4 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xC4 0.--7. 1. "CBNDX_VMID,"
line.long 0xC8 "SMMU_S2CR50,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xC8 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xC8 27. "INSTCFG_1," "0,1"
bitfld.long 0xC8 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xC8 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xC8 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xC8 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xC8 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xC8 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xC8 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xC8 11. "MTCFG," "0,1"
bitfld.long 0xC8 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xC8 0.--7. 1. "CBNDX_VMID,"
line.long 0xCC "SMMU_S2CR51,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xCC 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xCC 27. "INSTCFG_1," "0,1"
bitfld.long 0xCC 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xCC 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xCC 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xCC 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xCC 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xCC 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xCC 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xCC 11. "MTCFG," "0,1"
bitfld.long 0xCC 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xCC 0.--7. 1. "CBNDX_VMID,"
line.long 0xD0 "SMMU_S2CR52,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xD0 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xD0 27. "INSTCFG_1," "0,1"
bitfld.long 0xD0 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xD0 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xD0 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xD0 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xD0 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xD0 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xD0 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xD0 11. "MTCFG," "0,1"
bitfld.long 0xD0 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xD0 0.--7. 1. "CBNDX_VMID,"
line.long 0xD4 "SMMU_S2CR53,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xD4 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xD4 27. "INSTCFG_1," "0,1"
bitfld.long 0xD4 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xD4 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xD4 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xD4 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xD4 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xD4 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xD4 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xD4 11. "MTCFG," "0,1"
bitfld.long 0xD4 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xD4 0.--7. 1. "CBNDX_VMID,"
line.long 0xD8 "SMMU_S2CR54,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xD8 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xD8 27. "INSTCFG_1," "0,1"
bitfld.long 0xD8 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xD8 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xD8 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xD8 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xD8 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xD8 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xD8 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xD8 11. "MTCFG," "0,1"
bitfld.long 0xD8 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xD8 0.--7. 1. "CBNDX_VMID,"
line.long 0xDC "SMMU_S2CR55,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xDC 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xDC 27. "INSTCFG_1," "0,1"
bitfld.long 0xDC 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xDC 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xDC 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xDC 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xDC 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xDC 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xDC 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xDC 11. "MTCFG," "0,1"
bitfld.long 0xDC 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xDC 0.--7. 1. "CBNDX_VMID,"
line.long 0xE0 "SMMU_S2CR56,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xE0 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xE0 27. "INSTCFG_1," "0,1"
bitfld.long 0xE0 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xE0 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xE0 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xE0 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xE0 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xE0 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xE0 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xE0 11. "MTCFG," "0,1"
bitfld.long 0xE0 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xE0 0.--7. 1. "CBNDX_VMID,"
line.long 0xE4 "SMMU_S2CR57,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xE4 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xE4 27. "INSTCFG_1," "0,1"
bitfld.long 0xE4 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xE4 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xE4 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xE4 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xE4 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xE4 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xE4 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xE4 11. "MTCFG," "0,1"
bitfld.long 0xE4 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xE4 0.--7. 1. "CBNDX_VMID,"
line.long 0xE8 "SMMU_S2CR58,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xE8 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xE8 27. "INSTCFG_1," "0,1"
bitfld.long 0xE8 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xE8 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xE8 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xE8 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xE8 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xE8 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xE8 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xE8 11. "MTCFG," "0,1"
bitfld.long 0xE8 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xE8 0.--7. 1. "CBNDX_VMID,"
line.long 0xEC "SMMU_S2CR59,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xEC 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xEC 27. "INSTCFG_1," "0,1"
bitfld.long 0xEC 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xEC 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xEC 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xEC 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xEC 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xEC 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xEC 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xEC 11. "MTCFG," "0,1"
bitfld.long 0xEC 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xEC 0.--7. 1. "CBNDX_VMID,"
line.long 0xF0 "SMMU_S2CR60,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xF0 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xF0 27. "INSTCFG_1," "0,1"
bitfld.long 0xF0 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xF0 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xF0 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xF0 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xF0 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xF0 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xF0 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xF0 11. "MTCFG," "0,1"
bitfld.long 0xF0 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xF0 0.--7. 1. "CBNDX_VMID,"
line.long 0xF4 "SMMU_S2CR61,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xF4 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xF4 27. "INSTCFG_1," "0,1"
bitfld.long 0xF4 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xF4 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xF4 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xF4 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xF4 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xF4 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xF4 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xF4 11. "MTCFG," "0,1"
bitfld.long 0xF4 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xF4 0.--7. 1. "CBNDX_VMID,"
line.long 0xF8 "SMMU_S2CR62,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xF8 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xF8 27. "INSTCFG_1," "0,1"
bitfld.long 0xF8 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xF8 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xF8 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xF8 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xF8 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xF8 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xF8 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xF8 11. "MTCFG," "0,1"
bitfld.long 0xF8 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xF8 0.--7. 1. "CBNDX_VMID,"
line.long 0xFC "SMMU_S2CR63,Specifies an initial context for processing a transaction. where the transaction matches the Stream mapping group that this register belongs to."
bitfld.long 0xFC 28.--29. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0xFC 27. "INSTCFG_1," "0,1"
bitfld.long 0xFC 26. "INSTCFG_0_FB," "0,1"
newline
bitfld.long 0xFC 24.--25. "PRIVCFG_BSU," "0,1,2,3"
bitfld.long 0xFC 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xFC 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xFC 18.--19. "NSCFG," "0,1,2,3"
bitfld.long 0xFC 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xFC 12.--15. 1. "MEM_ATTR,"
newline
bitfld.long 0xFC 11. "MTCFG," "0,1"
bitfld.long 0xFC 8.--9. "SHCFG," "0,1,2,3"
hexmask.long.byte 0xFC 0.--7. 1. "CBNDX_VMID,"
rgroup.long 0xFD0++0x2F
line.long 0x0 "SMMU_PIDR4,Peripheral Identificaation register 4"
hexmask.long.byte 0x0 4.--7. 1. "FourKB_Count,"
hexmask.long.byte 0x0 0.--3. 1. "JEP106_Continuation_code,"
line.long 0x4 "SMMU_PIDR5,Peripheral Identificaation register 5"
hexmask.long 0x4 0.--31. 1. "SMMU_PIDR5,Peripheral Identificaation register 5"
line.long 0x8 "SMMU_PIDR6,Peripheral Identificaation register 6"
hexmask.long 0x8 0.--31. 1. "SMMU_PIDR6,Peripheral Identificaation register 6"
line.long 0xC "SMMU_PIDR7,Peripheral Identificaation register 7"
hexmask.long 0xC 0.--31. 1. "SMMU_PIDR7,Peripheral Identificaation register 7"
line.long 0x10 "SMMU_PIDR0,Peripheral Identificaation register 0"
hexmask.long.byte 0x10 0.--7. 1. "PartNumber0,"
line.long 0x14 "SMMU_PIDR1,Peripheral Identificaation register 1"
hexmask.long.byte 0x14 4.--7. 1. "JEP106_identity_code,"
hexmask.long.byte 0x14 0.--3. 1. "PartNumber1,"
line.long 0x18 "SMMU_PIDR2,Peripheral Identificaation register 2"
hexmask.long.byte 0x18 4.--7. 1. "Architecture_Revision,"
bitfld.long 0x18 3. "JEDEC," "0,1"
bitfld.long 0x18 0.--2. "JEP106_identity_code," "0,1,2,3,4,5,6,7"
line.long 0x1C "SMMU_PIDR3,Peripheral Identificaation register 3"
hexmask.long.byte 0x1C 4.--7. 1. "RevAnd,"
hexmask.long.byte 0x1C 0.--3. 1. "Customer_modified,"
line.long 0x20 "SMMU_CIDR0,Component Identification register 0"
hexmask.long.byte 0x20 0.--7. 1. "PREAMBLE,"
line.long 0x24 "SMMU_CIDR1,Component Identification register 1"
hexmask.long.byte 0x24 0.--7. 1. "PREAMBLE,"
line.long 0x28 "SMMU_CIDR2,Component Identification register 2"
hexmask.long.byte 0x28 0.--7. 1. "PREAMBLE,"
line.long 0x2C "SMMU_CIDR3,Component Identification register 3"
hexmask.long.byte 0x2C 0.--7. 1. "PREAMBLE,"
group.long 0x1000++0x7F
line.long 0x0 "SMMU_CBAR0,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x0 24.--31. 1. "IRPTNDX,"
bitfld.long 0x0 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x0 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x0 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x0 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x0 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x0 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x0 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--7. 1. "VMID,"
line.long 0x4 "SMMU_CBAR1,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x4 24.--31. 1. "IRPTNDX,"
bitfld.long 0x4 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x4 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x4 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x4 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x4 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x4 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x4 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x4 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x4 0.--7. 1. "VMID,"
line.long 0x8 "SMMU_CBAR2,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x8 24.--31. 1. "IRPTNDX,"
bitfld.long 0x8 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x8 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x8 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x8 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x8 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x8 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x8 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x8 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x8 0.--7. 1. "VMID,"
line.long 0xC "SMMU_CBAR3,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0xC 24.--31. 1. "IRPTNDX,"
bitfld.long 0xC 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0xC 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0xC 18.--19. "BSU," "0,1,2,3"
bitfld.long 0xC 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0xC 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0xC 11. "FB_CBNDX_3," "0,1"
bitfld.long 0xC 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0xC 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0xC 0.--7. 1. "VMID,"
line.long 0x10 "SMMU_CBAR4,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x10 24.--31. 1. "IRPTNDX,"
bitfld.long 0x10 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x10 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x10 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x10 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x10 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x10 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x10 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x10 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x10 0.--7. 1. "VMID,"
line.long 0x14 "SMMU_CBAR5,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x14 24.--31. 1. "IRPTNDX,"
bitfld.long 0x14 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x14 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x14 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x14 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x14 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x14 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x14 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x14 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x14 0.--7. 1. "VMID,"
line.long 0x18 "SMMU_CBAR6,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x18 24.--31. 1. "IRPTNDX,"
bitfld.long 0x18 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x18 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x18 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x18 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x18 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x18 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x18 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x18 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x18 0.--7. 1. "VMID,"
line.long 0x1C "SMMU_CBAR7,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x1C 24.--31. 1. "IRPTNDX,"
bitfld.long 0x1C 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x1C 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x1C 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x1C 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x1C 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x1C 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x1C 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x1C 0.--7. 1. "VMID,"
line.long 0x20 "SMMU_CBAR8,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x20 24.--31. 1. "IRPTNDX,"
bitfld.long 0x20 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x20 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x20 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x20 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x20 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x20 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x20 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x20 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x20 0.--7. 1. "VMID,"
line.long 0x24 "SMMU_CBAR9,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x24 24.--31. 1. "IRPTNDX,"
bitfld.long 0x24 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x24 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x24 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x24 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x24 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x24 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x24 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x24 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x24 0.--7. 1. "VMID,"
line.long 0x28 "SMMU_CBAR10,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x28 24.--31. 1. "IRPTNDX,"
bitfld.long 0x28 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x28 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x28 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x28 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x28 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x28 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x28 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x28 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x28 0.--7. 1. "VMID,"
line.long 0x2C "SMMU_CBAR11,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x2C 24.--31. 1. "IRPTNDX,"
bitfld.long 0x2C 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x2C 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x2C 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x2C 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x2C 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x2C 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x2C 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x2C 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x2C 0.--7. 1. "VMID,"
line.long 0x30 "SMMU_CBAR12,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x30 24.--31. 1. "IRPTNDX,"
bitfld.long 0x30 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x30 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x30 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x30 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x30 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x30 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x30 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x30 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x30 0.--7. 1. "VMID,"
line.long 0x34 "SMMU_CBAR13,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x34 24.--31. 1. "IRPTNDX,"
bitfld.long 0x34 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x34 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x34 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x34 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x34 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x34 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x34 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x34 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x34 0.--7. 1. "VMID,"
line.long 0x38 "SMMU_CBAR14,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x38 24.--31. 1. "IRPTNDX,"
bitfld.long 0x38 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x38 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x38 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x38 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x38 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x38 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x38 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x38 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x38 0.--7. 1. "VMID,"
line.long 0x3C "SMMU_CBAR15,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x3C 24.--31. 1. "IRPTNDX,"
bitfld.long 0x3C 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x3C 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x3C 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x3C 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x3C 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x3C 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x3C 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x3C 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x3C 0.--7. 1. "VMID,"
line.long 0x40 "SMMU_CBAR16,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x40 24.--31. 1. "IRPTNDX,"
bitfld.long 0x40 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x40 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x40 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x40 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x40 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x40 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x40 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x40 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x40 0.--7. 1. "VMID,"
line.long 0x44 "SMMU_CBAR17,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x44 24.--31. 1. "IRPTNDX,"
bitfld.long 0x44 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x44 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x44 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x44 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x44 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x44 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x44 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x44 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x44 0.--7. 1. "VMID,"
line.long 0x48 "SMMU_CBAR18,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x48 24.--31. 1. "IRPTNDX,"
bitfld.long 0x48 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x48 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x48 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x48 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x48 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x48 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x48 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x48 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x48 0.--7. 1. "VMID,"
line.long 0x4C "SMMU_CBAR19,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x4C 24.--31. 1. "IRPTNDX,"
bitfld.long 0x4C 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x4C 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x4C 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x4C 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x4C 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x4C 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x4C 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x4C 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x4C 0.--7. 1. "VMID,"
line.long 0x50 "SMMU_CBAR20,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x50 24.--31. 1. "IRPTNDX,"
bitfld.long 0x50 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x50 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x50 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x50 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x50 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x50 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x50 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x50 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x50 0.--7. 1. "VMID,"
line.long 0x54 "SMMU_CBAR21,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x54 24.--31. 1. "IRPTNDX,"
bitfld.long 0x54 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x54 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x54 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x54 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x54 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x54 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x54 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x54 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x54 0.--7. 1. "VMID,"
line.long 0x58 "SMMU_CBAR22,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x58 24.--31. 1. "IRPTNDX,"
bitfld.long 0x58 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x58 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x58 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x58 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x58 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x58 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x58 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x58 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x58 0.--7. 1. "VMID,"
line.long 0x5C "SMMU_CBAR23,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x5C 24.--31. 1. "IRPTNDX,"
bitfld.long 0x5C 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x5C 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x5C 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x5C 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x5C 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x5C 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x5C 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x5C 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x5C 0.--7. 1. "VMID,"
line.long 0x60 "SMMU_CBAR24,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x60 24.--31. 1. "IRPTNDX,"
bitfld.long 0x60 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x60 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x60 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x60 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x60 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x60 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x60 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x60 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x60 0.--7. 1. "VMID,"
line.long 0x64 "SMMU_CBAR25,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x64 24.--31. 1. "IRPTNDX,"
bitfld.long 0x64 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x64 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x64 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x64 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x64 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x64 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x64 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x64 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x64 0.--7. 1. "VMID,"
line.long 0x68 "SMMU_CBAR26,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x68 24.--31. 1. "IRPTNDX,"
bitfld.long 0x68 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x68 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x68 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x68 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x68 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x68 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x68 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x68 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x68 0.--7. 1. "VMID,"
line.long 0x6C "SMMU_CBAR27,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x6C 24.--31. 1. "IRPTNDX,"
bitfld.long 0x6C 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x6C 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x6C 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x6C 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x6C 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x6C 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x6C 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x6C 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x6C 0.--7. 1. "VMID,"
line.long 0x70 "SMMU_CBAR28,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x70 24.--31. 1. "IRPTNDX,"
bitfld.long 0x70 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x70 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x70 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x70 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x70 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x70 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x70 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x70 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x70 0.--7. 1. "VMID,"
line.long 0x74 "SMMU_CBAR29,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x74 24.--31. 1. "IRPTNDX,"
bitfld.long 0x74 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x74 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x74 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x74 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x74 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x74 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x74 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x74 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x74 0.--7. 1. "VMID,"
line.long 0x78 "SMMU_CBAR30,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x78 24.--31. 1. "IRPTNDX,"
bitfld.long 0x78 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x78 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x78 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x78 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x78 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x78 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x78 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x78 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x78 0.--7. 1. "VMID,"
line.long 0x7C "SMMU_CBAR31,Specifies configuration attributes for translation context bank."
hexmask.long.byte 0x7C 24.--31. 1. "IRPTNDX,"
bitfld.long 0x7C 22.--23. "WACFG," "0,1,2,3"
bitfld.long 0x7C 20.--21. "RACFG," "0,1,2,3"
newline
bitfld.long 0x7C 18.--19. "BSU," "0,1,2,3"
bitfld.long 0x7C 16.--17. "TYPE," "0,1,2,3"
hexmask.long.byte 0x7C 12.--15. 1. "MEMATTR_CBNDX_7_4,"
newline
bitfld.long 0x7C 11. "FB_CBNDX_3," "0,1"
bitfld.long 0x7C 10. "HYPC_CBNDX_2," "0,1"
bitfld.long 0x7C 8.--9. "BPSHCFG_CBNDX_1_0," "0,1,2,3"
newline
hexmask.long.byte 0x7C 0.--7. 1. "VMID,"
group.long 0x1400++0x7F
line.long 0x0 "SMMU_CBFRSYNRA0,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x0 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x0 0.--14. 1. "StreamID,"
line.long 0x4 "SMMU_CBFRSYNRA1,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x4 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x4 0.--14. 1. "StreamID,"
line.long 0x8 "SMMU_CBFRSYNRA2,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x8 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x8 0.--14. 1. "StreamID,"
line.long 0xC "SMMU_CBFRSYNRA3,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0xC 16.--30. 1. "SSD_Index,"
hexmask.long.word 0xC 0.--14. 1. "StreamID,"
line.long 0x10 "SMMU_CBFRSYNRA4,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x10 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x10 0.--14. 1. "StreamID,"
line.long 0x14 "SMMU_CBFRSYNRA5,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x14 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x14 0.--14. 1. "StreamID,"
line.long 0x18 "SMMU_CBFRSYNRA6,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x18 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x18 0.--14. 1. "StreamID,"
line.long 0x1C "SMMU_CBFRSYNRA7,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x1C 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x1C 0.--14. 1. "StreamID,"
line.long 0x20 "SMMU_CBFRSYNRA8,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x20 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x20 0.--14. 1. "StreamID,"
line.long 0x24 "SMMU_CBFRSYNRA9,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x24 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x24 0.--14. 1. "StreamID,"
line.long 0x28 "SMMU_CBFRSYNRA10,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x28 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x28 0.--14. 1. "StreamID,"
line.long 0x2C "SMMU_CBFRSYNRA11,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x2C 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x2C 0.--14. 1. "StreamID,"
line.long 0x30 "SMMU_CBFRSYNRA12,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x30 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x30 0.--14. 1. "StreamID,"
line.long 0x34 "SMMU_CBFRSYNRA13,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x34 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x34 0.--14. 1. "StreamID,"
line.long 0x38 "SMMU_CBFRSYNRA14,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x38 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x38 0.--14. 1. "StreamID,"
line.long 0x3C "SMMU_CBFRSYNRA15,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x3C 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x3C 0.--14. 1. "StreamID,"
line.long 0x40 "SMMU_CBFRSYNRA16,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x40 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x40 0.--14. 1. "StreamID,"
line.long 0x44 "SMMU_CBFRSYNRA17,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x44 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x44 0.--14. 1. "StreamID,"
line.long 0x48 "SMMU_CBFRSYNRA18,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x48 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x48 0.--14. 1. "StreamID,"
line.long 0x4C "SMMU_CBFRSYNRA19,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x4C 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x4C 0.--14. 1. "StreamID,"
line.long 0x50 "SMMU_CBFRSYNRA20,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x50 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x50 0.--14. 1. "StreamID,"
line.long 0x54 "SMMU_CBFRSYNRA21,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x54 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x54 0.--14. 1. "StreamID,"
line.long 0x58 "SMMU_CBFRSYNRA22,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x58 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x58 0.--14. 1. "StreamID,"
line.long 0x5C "SMMU_CBFRSYNRA23,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x5C 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x5C 0.--14. 1. "StreamID,"
line.long 0x60 "SMMU_CBFRSYNRA24,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x60 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x60 0.--14. 1. "StreamID,"
line.long 0x64 "SMMU_CBFRSYNRA25,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x64 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x64 0.--14. 1. "StreamID,"
line.long 0x68 "SMMU_CBFRSYNRA26,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x68 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x68 0.--14. 1. "StreamID,"
line.long 0x6C "SMMU_CBFRSYNRA27,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x6C 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x6C 0.--14. 1. "StreamID,"
line.long 0x70 "SMMU_CBFRSYNRA28,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x70 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x70 0.--14. 1. "StreamID,"
line.long 0x74 "SMMU_CBFRSYNRA29,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x74 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x74 0.--14. 1. "StreamID,"
line.long 0x78 "SMMU_CBFRSYNRA30,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x78 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x78 0.--14. 1. "StreamID,"
line.long 0x7C "SMMU_CBFRSYNRA31,Gives fault syndrome information about the access that caused an exception in the associated translation context bank."
hexmask.long.word 0x7C 16.--30. 1. "SSD_Index,"
hexmask.long.word 0x7C 0.--14. 1. "StreamID,"
group.long 0x1800++0x7F
line.long 0x0 "SMMU_CBA2R0,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x0 1. "MONC," "0,1"
bitfld.long 0x0 0. "VA64," "0,1"
line.long 0x4 "SMMU_CBA2R1,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x4 1. "MONC," "0,1"
bitfld.long 0x4 0. "VA64," "0,1"
line.long 0x8 "SMMU_CBA2R2,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x8 1. "MONC," "0,1"
bitfld.long 0x8 0. "VA64," "0,1"
line.long 0xC "SMMU_CBA2R3,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0xC 1. "MONC," "0,1"
bitfld.long 0xC 0. "VA64," "0,1"
line.long 0x10 "SMMU_CBA2R4,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x10 1. "MONC," "0,1"
bitfld.long 0x10 0. "VA64," "0,1"
line.long 0x14 "SMMU_CBA2R5,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x14 1. "MONC," "0,1"
bitfld.long 0x14 0. "VA64," "0,1"
line.long 0x18 "SMMU_CBA2R6,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x18 1. "MONC," "0,1"
bitfld.long 0x18 0. "VA64," "0,1"
line.long 0x1C "SMMU_CBA2R7,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x1C 1. "MONC," "0,1"
bitfld.long 0x1C 0. "VA64," "0,1"
line.long 0x20 "SMMU_CBA2R8,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x20 1. "MONC," "0,1"
bitfld.long 0x20 0. "VA64," "0,1"
line.long 0x24 "SMMU_CBA2R9,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x24 1. "MONC," "0,1"
bitfld.long 0x24 0. "VA64," "0,1"
line.long 0x28 "SMMU_CBA2R10,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x28 1. "MONC," "0,1"
bitfld.long 0x28 0. "VA64," "0,1"
line.long 0x2C "SMMU_CBA2R11,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x2C 1. "MONC," "0,1"
bitfld.long 0x2C 0. "VA64," "0,1"
line.long 0x30 "SMMU_CBA2R12,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x30 1. "MONC," "0,1"
bitfld.long 0x30 0. "VA64," "0,1"
line.long 0x34 "SMMU_CBA2R13,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x34 1. "MONC," "0,1"
bitfld.long 0x34 0. "VA64," "0,1"
line.long 0x38 "SMMU_CBA2R14,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x38 1. "MONC," "0,1"
bitfld.long 0x38 0. "VA64," "0,1"
line.long 0x3C "SMMU_CBA2R15,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x3C 1. "MONC," "0,1"
bitfld.long 0x3C 0. "VA64," "0,1"
line.long 0x40 "SMMU_CBA2R16,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x40 1. "MONC," "0,1"
bitfld.long 0x40 0. "VA64," "0,1"
line.long 0x44 "SMMU_CBA2R17,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x44 1. "MONC," "0,1"
bitfld.long 0x44 0. "VA64," "0,1"
line.long 0x48 "SMMU_CBA2R18,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x48 1. "MONC," "0,1"
bitfld.long 0x48 0. "VA64," "0,1"
line.long 0x4C "SMMU_CBA2R19,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x4C 1. "MONC," "0,1"
bitfld.long 0x4C 0. "VA64," "0,1"
line.long 0x50 "SMMU_CBA2R20,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x50 1. "MONC," "0,1"
bitfld.long 0x50 0. "VA64," "0,1"
line.long 0x54 "SMMU_CBA2R21,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x54 1. "MONC," "0,1"
bitfld.long 0x54 0. "VA64," "0,1"
line.long 0x58 "SMMU_CBA2R22,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x58 1. "MONC," "0,1"
bitfld.long 0x58 0. "VA64," "0,1"
line.long 0x5C "SMMU_CBA2R23,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x5C 1. "MONC," "0,1"
bitfld.long 0x5C 0. "VA64," "0,1"
line.long 0x60 "SMMU_CBA2R24,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x60 1. "MONC," "0,1"
bitfld.long 0x60 0. "VA64," "0,1"
line.long 0x64 "SMMU_CBA2R25,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x64 1. "MONC," "0,1"
bitfld.long 0x64 0. "VA64," "0,1"
line.long 0x68 "SMMU_CBA2R26,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x68 1. "MONC," "0,1"
bitfld.long 0x68 0. "VA64," "0,1"
line.long 0x6C "SMMU_CBA2R27,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x6C 1. "MONC," "0,1"
bitfld.long 0x6C 0. "VA64," "0,1"
line.long 0x70 "SMMU_CBA2R28,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x70 1. "MONC," "0,1"
bitfld.long 0x70 0. "VA64," "0,1"
line.long 0x74 "SMMU_CBA2R29,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x74 1. "MONC," "0,1"
bitfld.long 0x74 0. "VA64," "0,1"
line.long 0x78 "SMMU_CBA2R30,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x78 1. "MONC," "0,1"
bitfld.long 0x78 0. "VA64," "0,1"
line.long 0x7C "SMMU_CBA2R31,Extends the configuration attributes for the translation context bank that SMMU_CBARn specifies."
bitfld.long 0x7C 1. "MONC," "0,1"
bitfld.long 0x7C 0. "VA64," "0,1"
group.long 0x2000++0x3
line.long 0x0 "SMMU_ITCTRL,This register enables the component to switch from functional mode to integration mode. You can directly control the inputs and outputs in integration mode."
bitfld.long 0x0 4.--6. "tbu_index," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "MODULE," "0,1"
bitfld.long 0x0 2. "RAM_DATA," "0,1"
newline
bitfld.long 0x0 1. "RAM_MODE," "0,1"
bitfld.long 0x0 0. "INTGMODE," "0,1"
rgroup.long 0x2004++0x3
line.long 0x0 "SMMU_ITIP,Enables the MMU-500 to read the status of the spniden signal."
bitfld.long 0x0 0. "SPINDEN," "0,1"
group.long 0x2008++0x3
line.long 0x0 "SMMU_ITOP_GLBL,For integration test purposes. allows to enable or disable secure and nonsecure interrupts and write or read most significant bits of TCU MTLB and IPA RAMS."
hexmask.long.byte 0x0 16.--20. 1. "TCU_RAM_DATA,"
rbitfld.long 0x0 9. "GLBLSF1," "0,1"
rbitfld.long 0x0 1. "GLBLNSF1," "0,1"
wgroup.long 0x200C++0x7
line.long 0x0 "SMMU_ITOP_PERF_INDEX,Enables TBU performance interrupts."
bitfld.long 0x0 30.--31. "WAY_IPA2PA_PF," "0,1,2,3"
hexmask.long.byte 0x0 16.--22. 1. "IPA2PA_PF_INDEX,"
bitfld.long 0x0 14.--15. "WAY_MTLB_WC," "0,1,2,3"
newline
hexmask.long.word 0x0 0.--11. 1. "MTLB_WC_INDEX,"
line.long 0x4 "SMMU_ITOP_CXT0TO31_RAM0,Enable the context performance interrupts."
hexmask.long 0x4 0.--31. 1. "RAM_DATA,"
group.long 0x2100++0x3
line.long 0x0 "SMMU_TBUQOS0,Specify the QoS for TBUs.when the TBUn is in the range of 0-7."
hexmask.long.byte 0x0 16.--19. 1. "QOSTBU4,"
hexmask.long.byte 0x0 12.--15. 1. "QOSTBU3,"
hexmask.long.byte 0x0 8.--11. 1. "QOSTBU2,"
newline
hexmask.long.byte 0x0 4.--7. 1. "QOSTBU1,"
hexmask.long.byte 0x0 0.--3. 1. "QOSTBU0,"
rgroup.long 0x2200++0x7
line.long 0x0 "SMMU_PER,Checks for parity errors in TCU and TBU RAMs."
hexmask.long.byte 0x0 8.--15. 1. "PER_TCU,"
hexmask.long.byte 0x0 0.--7. 1. "PER_TBU,"
line.long 0x4 "SMMU_TBU_PWR_STATUS,Provides the power status of TBUs."
hexmask.long 0x4 0.--31. 1. "state,"
group.long 0x3000++0x4F
line.long 0x0 "PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "PMN0,"
line.long 0x4 "PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "PMN1,"
line.long 0x8 "PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "PMN2,"
line.long 0xC "PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "PMN3,"
line.long 0x10 "PMEVCNTR4,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x10 0.--31. 1. "PMN0,"
line.long 0x14 "PMEVCNTR5,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x14 0.--31. 1. "PMN1,"
line.long 0x18 "PMEVCNTR6,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x18 0.--31. 1. "PMN2,"
line.long 0x1C "PMEVCNTR7,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x1C 0.--31. 1. "PMN3,"
line.long 0x20 "PMEVCNTR8,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x20 0.--31. 1. "PMN0,"
line.long 0x24 "PMEVCNTR9,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x24 0.--31. 1. "PMN1,"
line.long 0x28 "PMEVCNTR10,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x28 0.--31. 1. "PMN2,"
line.long 0x2C "PMEVCNTR11,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x2C 0.--31. 1. "PMN3,"
line.long 0x30 "PMEVCNTR12,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x30 0.--31. 1. "PMN0,"
line.long 0x34 "PMEVCNTR13,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x34 0.--31. 1. "PMN1,"
line.long 0x38 "PMEVCNTR14,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x38 0.--31. 1. "PMN2,"
line.long 0x3C "PMEVCNTR15,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x3C 0.--31. 1. "PMN3,"
line.long 0x40 "PMEVCNTR16,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x40 0.--31. 1. "PMN0,"
line.long 0x44 "PMEVCNTR17,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x44 0.--31. 1. "PMN1,"
line.long 0x48 "PMEVCNTR18,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x48 0.--31. 1. "PMN2,"
line.long 0x4C "PMEVCNTR19,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4C 0.--31. 1. "PMN3,"
group.long 0x3400++0x4F
line.long 0x0 "PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
line.long 0x10 "PMEVTYPER4,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x10 31. "P," "0,1"
bitfld.long 0x10 30. "U," "0,1"
bitfld.long 0x10 29. "NSP," "0,1"
newline
bitfld.long 0x10 28. "NSU," "0,1"
hexmask.long.byte 0x10 0.--4. 1. "EVENT,"
line.long 0x14 "PMEVTYPER5,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x14 31. "P," "0,1"
bitfld.long 0x14 30. "U," "0,1"
bitfld.long 0x14 29. "NSP," "0,1"
newline
bitfld.long 0x14 28. "NSU," "0,1"
hexmask.long.byte 0x14 0.--4. 1. "EVENT,"
line.long 0x18 "PMEVTYPER6,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x18 31. "P," "0,1"
bitfld.long 0x18 30. "U," "0,1"
bitfld.long 0x18 29. "NSP," "0,1"
newline
bitfld.long 0x18 28. "NSU," "0,1"
hexmask.long.byte 0x18 0.--4. 1. "EVENT,"
line.long 0x1C "PMEVTYPER7,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x1C 31. "P," "0,1"
bitfld.long 0x1C 30. "U," "0,1"
bitfld.long 0x1C 29. "NSP," "0,1"
newline
bitfld.long 0x1C 28. "NSU," "0,1"
hexmask.long.byte 0x1C 0.--4. 1. "EVENT,"
line.long 0x20 "PMEVTYPER8,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x20 31. "P," "0,1"
bitfld.long 0x20 30. "U," "0,1"
bitfld.long 0x20 29. "NSP," "0,1"
newline
bitfld.long 0x20 28. "NSU," "0,1"
hexmask.long.byte 0x20 0.--4. 1. "EVENT,"
line.long 0x24 "PMEVTYPER9,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x24 31. "P," "0,1"
bitfld.long 0x24 30. "U," "0,1"
bitfld.long 0x24 29. "NSP," "0,1"
newline
bitfld.long 0x24 28. "NSU," "0,1"
hexmask.long.byte 0x24 0.--4. 1. "EVENT,"
line.long 0x28 "PMEVTYPER10,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x28 31. "P," "0,1"
bitfld.long 0x28 30. "U," "0,1"
bitfld.long 0x28 29. "NSP," "0,1"
newline
bitfld.long 0x28 28. "NSU," "0,1"
hexmask.long.byte 0x28 0.--4. 1. "EVENT,"
line.long 0x2C "PMEVTYPER11,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x2C 31. "P," "0,1"
bitfld.long 0x2C 30. "U," "0,1"
bitfld.long 0x2C 29. "NSP," "0,1"
newline
bitfld.long 0x2C 28. "NSU," "0,1"
hexmask.long.byte 0x2C 0.--4. 1. "EVENT,"
line.long 0x30 "PMEVTYPER12,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x30 31. "P," "0,1"
bitfld.long 0x30 30. "U," "0,1"
bitfld.long 0x30 29. "NSP," "0,1"
newline
bitfld.long 0x30 28. "NSU," "0,1"
hexmask.long.byte 0x30 0.--4. 1. "EVENT,"
line.long 0x34 "PMEVTYPER13,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x34 31. "P," "0,1"
bitfld.long 0x34 30. "U," "0,1"
bitfld.long 0x34 29. "NSP," "0,1"
newline
bitfld.long 0x34 28. "NSU," "0,1"
hexmask.long.byte 0x34 0.--4. 1. "EVENT,"
line.long 0x38 "PMEVTYPER14,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x38 31. "P," "0,1"
bitfld.long 0x38 30. "U," "0,1"
bitfld.long 0x38 29. "NSP," "0,1"
newline
bitfld.long 0x38 28. "NSU," "0,1"
hexmask.long.byte 0x38 0.--4. 1. "EVENT,"
line.long 0x3C "PMEVTYPER15,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x3C 31. "P," "0,1"
bitfld.long 0x3C 30. "U," "0,1"
bitfld.long 0x3C 29. "NSP," "0,1"
newline
bitfld.long 0x3C 28. "NSU," "0,1"
hexmask.long.byte 0x3C 0.--4. 1. "EVENT,"
line.long 0x40 "PMEVTYPER16,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x40 31. "P," "0,1"
bitfld.long 0x40 30. "U," "0,1"
bitfld.long 0x40 29. "NSP," "0,1"
newline
bitfld.long 0x40 28. "NSU," "0,1"
hexmask.long.byte 0x40 0.--4. 1. "EVENT,"
line.long 0x44 "PMEVTYPER17,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x44 31. "P," "0,1"
bitfld.long 0x44 30. "U," "0,1"
bitfld.long 0x44 29. "NSP," "0,1"
newline
bitfld.long 0x44 28. "NSU," "0,1"
hexmask.long.byte 0x44 0.--4. 1. "EVENT,"
line.long 0x48 "PMEVTYPER18,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x48 31. "P," "0,1"
bitfld.long 0x48 30. "U," "0,1"
bitfld.long 0x48 29. "NSP," "0,1"
newline
bitfld.long 0x48 28. "NSU," "0,1"
hexmask.long.byte 0x48 0.--4. 1. "EVENT,"
line.long 0x4C "PMEVTYPER19,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4C 31. "P," "0,1"
bitfld.long 0x4C 30. "U," "0,1"
bitfld.long 0x4C 29. "NSP," "0,1"
newline
bitfld.long 0x4C 28. "NSU," "0,1"
hexmask.long.byte 0x4C 0.--4. 1. "EVENT,"
group.long 0x3800++0x13
line.long 0x0 "PMCGCR0,Controls Counter group behavior."
hexmask.long.byte 0x0 24.--27. 1. "CGNC,"
hexmask.long.byte 0x0 16.--22. 1. "SIDG,"
bitfld.long 0x0 12. "X," "0,1"
newline
bitfld.long 0x0 11. "E," "0,1"
bitfld.long 0x0 10. "CBAEN," "0,1"
bitfld.long 0x0 8.--9. "TCEFCFG," "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--4. 1. "NDX,"
line.long 0x4 "PMCGCR1,Controls Counter group behavior."
hexmask.long.byte 0x4 24.--27. 1. "CGNC,"
hexmask.long.byte 0x4 16.--22. 1. "SIDG,"
bitfld.long 0x4 12. "X," "0,1"
newline
bitfld.long 0x4 11. "E," "0,1"
bitfld.long 0x4 10. "CBAEN," "0,1"
bitfld.long 0x4 8.--9. "TCEFCFG," "0,1,2,3"
newline
hexmask.long.byte 0x4 0.--4. 1. "NDX,"
line.long 0x8 "PMCGCR2,Controls Counter group behavior."
hexmask.long.byte 0x8 24.--27. 1. "CGNC,"
hexmask.long.byte 0x8 16.--22. 1. "SIDG,"
bitfld.long 0x8 12. "X," "0,1"
newline
bitfld.long 0x8 11. "E," "0,1"
bitfld.long 0x8 10. "CBAEN," "0,1"
bitfld.long 0x8 8.--9. "TCEFCFG," "0,1,2,3"
newline
hexmask.long.byte 0x8 0.--4. 1. "NDX,"
line.long 0xC "PMCGCR3,Controls Counter group behavior."
hexmask.long.byte 0xC 24.--27. 1. "CGNC,"
hexmask.long.byte 0xC 16.--22. 1. "SIDG,"
bitfld.long 0xC 12. "X," "0,1"
newline
bitfld.long 0xC 11. "E," "0,1"
bitfld.long 0xC 10. "CBAEN," "0,1"
bitfld.long 0xC 8.--9. "TCEFCFG," "0,1,2,3"
newline
hexmask.long.byte 0xC 0.--4. 1. "NDX,"
line.long 0x10 "PMCGCR4,Controls Counter group behavior."
hexmask.long.byte 0x10 24.--27. 1. "CGNC,"
hexmask.long.byte 0x10 16.--22. 1. "SIDG,"
bitfld.long 0x10 12. "X," "0,1"
newline
bitfld.long 0x10 11. "E," "0,1"
bitfld.long 0x10 10. "CBAEN," "0,1"
bitfld.long 0x10 8.--9. "TCEFCFG," "0,1,2,3"
newline
hexmask.long.byte 0x10 0.--4. 1. "NDX,"
group.long 0x3A00++0x13
line.long 0x0 "PMCGSMR0,Specifies StreamID filtering of the events counted in a Counter group"
hexmask.long.word 0x0 16.--25. 1. "MASK,"
hexmask.long.word 0x0 0.--9. 1. "ID,"
line.long 0x4 "PMCGSMR1,Specifies StreamID filtering of the events counted in a Counter group"
hexmask.long.word 0x4 16.--25. 1. "MASK,"
hexmask.long.word 0x4 0.--9. 1. "ID,"
line.long 0x8 "PMCGSMR2,Specifies StreamID filtering of the events counted in a Counter group"
hexmask.long.word 0x8 16.--25. 1. "MASK,"
hexmask.long.word 0x8 0.--9. 1. "ID,"
line.long 0xC "PMCGSMR3,Specifies StreamID filtering of the events counted in a Counter group"
hexmask.long.word 0xC 16.--25. 1. "MASK,"
hexmask.long.word 0xC 0.--9. 1. "ID,"
line.long 0x10 "PMCGSMR4,Specifies StreamID filtering of the events counted in a Counter group"
hexmask.long.word 0x10 16.--25. 1. "MASK,"
hexmask.long.word 0x10 0.--9. 1. "ID,"
wgroup.long 0x3C00++0x3
line.long 0x0 "PMCNTENSET,Performance Monitor Counter Enable Set registers are used to enable the event counters PMEVCNTRxx."
bitfld.long 0x0 19. "P19," "0,1"
bitfld.long 0x0 18. "P18," "0,1"
bitfld.long 0x0 17. "P17," "0,1"
newline
bitfld.long 0x0 16. "P16," "0,1"
bitfld.long 0x0 15. "P15," "0,1"
bitfld.long 0x0 14. "P14," "0,1"
newline
bitfld.long 0x0 13. "P13," "0,1"
bitfld.long 0x0 12. "P12," "0,1"
bitfld.long 0x0 11. "P11," "0,1"
newline
bitfld.long 0x0 10. "P10," "0,1"
bitfld.long 0x0 9. "P9," "0,1"
bitfld.long 0x0 8. "P8," "0,1"
newline
bitfld.long 0x0 7. "P7," "0,1"
bitfld.long 0x0 6. "P6," "0,1"
bitfld.long 0x0 5. "P5," "0,1"
newline
bitfld.long 0x0 4. "P4," "0,1"
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
newline
bitfld.long 0x0 1. "P1," "0,1"
bitfld.long 0x0 0. "P0," "0,1"
wgroup.long 0x3C20++0x3
line.long 0x0 "PMCNTENCLR,Performance Monitor Counter Enable Clear registers are used to disable the event counters PMEVCNTRxx."
bitfld.long 0x0 19. "P19," "0,1"
bitfld.long 0x0 18. "P18," "0,1"
bitfld.long 0x0 17. "P17," "0,1"
newline
bitfld.long 0x0 16. "P16," "0,1"
bitfld.long 0x0 15. "P15," "0,1"
bitfld.long 0x0 14. "P14," "0,1"
newline
bitfld.long 0x0 13. "P13," "0,1"
bitfld.long 0x0 12. "P12," "0,1"
bitfld.long 0x0 11. "P11," "0,1"
newline
bitfld.long 0x0 10. "P10," "0,1"
bitfld.long 0x0 9. "P9," "0,1"
bitfld.long 0x0 8. "P8," "0,1"
newline
bitfld.long 0x0 7. "P7," "0,1"
bitfld.long 0x0 6. "P6," "0,1"
bitfld.long 0x0 5. "P5," "0,1"
newline
bitfld.long 0x0 4. "P4," "0,1"
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
newline
bitfld.long 0x0 1. "P1," "0,1"
bitfld.long 0x0 0. "P0," "0,1"
wgroup.long 0x3C40++0x3
line.long 0x0 "PMINTENSET,Performance Monitor Interrupt Enable Set registers are used enable the generation of interrupts on overflows of the event counters."
bitfld.long 0x0 19. "P19," "0,1"
bitfld.long 0x0 18. "P18," "0,1"
bitfld.long 0x0 17. "P17," "0,1"
newline
bitfld.long 0x0 16. "P16," "0,1"
bitfld.long 0x0 15. "P15," "0,1"
bitfld.long 0x0 14. "P14," "0,1"
newline
bitfld.long 0x0 13. "P13," "0,1"
bitfld.long 0x0 12. "P12," "0,1"
bitfld.long 0x0 11. "P11," "0,1"
newline
bitfld.long 0x0 10. "P10," "0,1"
bitfld.long 0x0 9. "P9," "0,1"
bitfld.long 0x0 8. "P8," "0,1"
newline
bitfld.long 0x0 7. "P7," "0,1"
bitfld.long 0x0 6. "P6," "0,1"
bitfld.long 0x0 5. "P5," "0,1"
newline
bitfld.long 0x0 4. "P4," "0,1"
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
newline
bitfld.long 0x0 1. "P1," "0,1"
bitfld.long 0x0 0. "P0," "0,1"
wgroup.long 0x3C60++0x3
line.long 0x0 "PMINTENCLR,Performance Monitor Interrupt Enable Clear registers are used disable the generation of interrupts on overflows of the event counters."
bitfld.long 0x0 19. "P19," "0,1"
bitfld.long 0x0 18. "P18," "0,1"
bitfld.long 0x0 17. "P17," "0,1"
newline
bitfld.long 0x0 16. "P16," "0,1"
bitfld.long 0x0 15. "P15," "0,1"
bitfld.long 0x0 14. "P14," "0,1"
newline
bitfld.long 0x0 13. "P13," "0,1"
bitfld.long 0x0 12. "P12," "0,1"
bitfld.long 0x0 11. "P11," "0,1"
newline
bitfld.long 0x0 10. "P10," "0,1"
bitfld.long 0x0 9. "P9," "0,1"
bitfld.long 0x0 8. "P8," "0,1"
newline
bitfld.long 0x0 7. "P7," "0,1"
bitfld.long 0x0 6. "P6," "0,1"
bitfld.long 0x0 5. "P5," "0,1"
newline
bitfld.long 0x0 4. "P4," "0,1"
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
newline
bitfld.long 0x0 1. "P1," "0,1"
bitfld.long 0x0 0. "P0," "0,1"
wgroup.long 0x3C80++0x3
line.long 0x0 "PMOVSCLR,Performance Monitor Overflow Status Clear registers are used to clear the overflow status of the event registers."
bitfld.long 0x0 19. "P19," "0,1"
bitfld.long 0x0 18. "P18," "0,1"
bitfld.long 0x0 17. "P17," "0,1"
newline
bitfld.long 0x0 16. "P16," "0,1"
bitfld.long 0x0 15. "P15," "0,1"
bitfld.long 0x0 14. "P14," "0,1"
newline
bitfld.long 0x0 13. "P13," "0,1"
bitfld.long 0x0 12. "P12," "0,1"
bitfld.long 0x0 11. "P11," "0,1"
newline
bitfld.long 0x0 10. "P10," "0,1"
bitfld.long 0x0 9. "P9," "0,1"
bitfld.long 0x0 8. "P8," "0,1"
newline
bitfld.long 0x0 7. "P7," "0,1"
bitfld.long 0x0 6. "P6," "0,1"
bitfld.long 0x0 5. "P5," "0,1"
newline
bitfld.long 0x0 4. "P4," "0,1"
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
newline
bitfld.long 0x0 1. "P1," "0,1"
bitfld.long 0x0 0. "P0," "0,1"
wgroup.long 0x3CC0++0x3
line.long 0x0 "PMOVSSET,Performance Monitor Overflow Status Set registers contain overflow status for the event counters ."
bitfld.long 0x0 19. "P19," "0,1"
bitfld.long 0x0 18. "P18," "0,1"
bitfld.long 0x0 17. "P17," "0,1"
newline
bitfld.long 0x0 16. "P16," "0,1"
bitfld.long 0x0 15. "P15," "0,1"
bitfld.long 0x0 14. "P14," "0,1"
newline
bitfld.long 0x0 13. "P13," "0,1"
bitfld.long 0x0 12. "P12," "0,1"
bitfld.long 0x0 11. "P11," "0,1"
newline
bitfld.long 0x0 10. "P10," "0,1"
bitfld.long 0x0 9. "P9," "0,1"
bitfld.long 0x0 8. "P8," "0,1"
newline
bitfld.long 0x0 7. "P7," "0,1"
bitfld.long 0x0 6. "P6," "0,1"
bitfld.long 0x0 5. "P5," "0,1"
newline
bitfld.long 0x0 4. "P4," "0,1"
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
newline
bitfld.long 0x0 1. "P1," "0,1"
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x3E00++0x3
line.long 0x0 "PMCFGR,Performance Monitor Configuration register containss PMU specific configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x3E04++0x3
line.long 0x0 "PMCR,Performance Monitor Configuration register controls the behaviour of the event counters."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x3E20++0x3
line.long 0x0 "PMCEID0,Performance Monitor Common Event Identification register 0 describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
rgroup.long 0x3FB8++0x3
line.long 0x0 "PMAUTHSTATUS,Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
rgroup.long 0x3FCC++0x3
line.long 0x0 "PMDEVTYPE,Performance Monitor Device Type register provides the Coresight device type information for the PerformanceMonitors."
hexmask.long.byte 0x0 4.--7. 1. "T,"
hexmask.long.byte 0x0 0.--3. 1. "C,"
group.long 0x4000++0x3
line.long 0x0 "smmu_ssd_reg_0,SSD Register 0"
hexmask.long.tbyte 0x0 8.--31. 1. "ssd_index_8_31,"
bitfld.long 0x0 7. "ssd_index_7," "0,1"
bitfld.long 0x0 6. "ssd_index_6," "0,1"
newline
bitfld.long 0x0 5. "ssd_index_5," "0,1"
bitfld.long 0x0 4. "ssd_index_4," "0,1"
bitfld.long 0x0 3. "ssd_index_3," "0,1"
newline
bitfld.long 0x0 2. "ssd_index_2," "0,1"
bitfld.long 0x0 1. "ssd_index_1," "0,1"
bitfld.long 0x0 0. "ssd_index_0," "0,1"
rgroup.long 0x4004++0x7B
line.long 0x0 "smmu_ssd_reg_1,SSD Register 1"
hexmask.long 0x0 0.--31. 1. "ssd_index_32_63,"
line.long 0x4 "smmu_ssd_reg_2,SSD Register 2"
hexmask.long 0x4 0.--31. 1. "ssd_index_64_95,"
line.long 0x8 "smmu_ssd_reg_3,SSD Register 3"
hexmask.long 0x8 0.--31. 1. "ssd_index_96_127,"
line.long 0xC "smmu_ssd_reg_4,SSD Register 4"
hexmask.long 0xC 0.--31. 1. "ssd_index_128_159,"
line.long 0x10 "smmu_ssd_reg_5,SSD Register 5"
hexmask.long 0x10 0.--31. 1. "ssd_index_160_191,"
line.long 0x14 "smmu_ssd_reg_6,SSD Register 6"
hexmask.long 0x14 0.--31. 1. "ssd_index_192_223,"
line.long 0x18 "smmu_ssd_reg_7,SSD Register 7"
hexmask.long 0x18 0.--31. 1. "ssd_index_224_255,"
line.long 0x1C "smmu_ssd_reg_8,SSD Register 8"
hexmask.long 0x1C 0.--31. 1. "ssd_index_256_287,"
line.long 0x20 "smmu_ssd_reg_9,SSD Register 9"
hexmask.long 0x20 0.--31. 1. "ssd_index_288_319,"
line.long 0x24 "smmu_ssd_reg_10,SSD Register 10"
hexmask.long 0x24 0.--31. 1. "ssd_index_320_351,"
line.long 0x28 "smmu_ssd_reg_11,SSD Register 11"
hexmask.long 0x28 0.--31. 1. "ssd_index_352_383,"
line.long 0x2C "smmu_ssd_reg_12,SSD Register 12"
hexmask.long 0x2C 0.--31. 1. "ssd_index_384_415,"
line.long 0x30 "smmu_ssd_reg_13,SSD Register 13"
hexmask.long 0x30 0.--31. 1. "ssd_index_416_447,"
line.long 0x34 "smmu_ssd_reg_14,SSD Register 14"
hexmask.long 0x34 0.--31. 1. "ssd_index_448_479,"
line.long 0x38 "smmu_ssd_reg_15,SSD Register 15"
hexmask.long 0x38 0.--31. 1. "ssd_index_480_511,"
line.long 0x3C "smmu_ssd_reg_16,SSD Register 16"
hexmask.long 0x3C 0.--31. 1. "ssd_index_512_543,"
line.long 0x40 "smmu_ssd_reg_17,SSD Register 17"
hexmask.long 0x40 0.--31. 1. "ssd_index_544_575,"
line.long 0x44 "smmu_ssd_reg_18,SSD Register 18"
hexmask.long 0x44 0.--31. 1. "ssd_index_576_607,"
line.long 0x48 "smmu_ssd_reg_19,SSD Register 19"
hexmask.long 0x48 0.--31. 1. "ssd_index_608_639,"
line.long 0x4C "smmu_ssd_reg_20,SSD Register 20"
hexmask.long 0x4C 0.--31. 1. "ssd_index_640_671,"
line.long 0x50 "smmu_ssd_reg_21,SSD Register 21"
hexmask.long 0x50 0.--31. 1. "ssd_index_672_703,"
line.long 0x54 "smmu_ssd_reg_22,SSD Register 22"
hexmask.long 0x54 0.--31. 1. "ssd_index_704_735,"
line.long 0x58 "smmu_ssd_reg_23,SSD Register 23"
hexmask.long 0x58 0.--31. 1. "ssd_index_736_767,"
line.long 0x5C "smmu_ssd_reg_24,SSD Register 24"
hexmask.long 0x5C 0.--31. 1. "ssd_index_768_799,"
line.long 0x60 "smmu_ssd_reg_25,SSD Register 25"
hexmask.long 0x60 0.--31. 1. "ssd_index_800_831,"
line.long 0x64 "smmu_ssd_reg_26,SSD Register 26"
hexmask.long 0x64 0.--31. 1. "ssd_index_832_863,"
line.long 0x68 "smmu_ssd_reg_27,SSD Register 27"
hexmask.long 0x68 0.--31. 1. "ssd_index_864_895,"
line.long 0x6C "smmu_ssd_reg_28,SSD Register 28"
hexmask.long 0x6C 0.--31. 1. "ssd_index_896_927,"
line.long 0x70 "smmu_ssd_reg_29,SSD Register 29"
hexmask.long 0x70 0.--31. 1. "ssd_index_928_959,"
line.long 0x74 "smmu_ssd_reg_30,SSD Register 30"
hexmask.long 0x74 0.--31. 1. "ssd_index_960_991,"
line.long 0x78 "smmu_ssd_reg_31,SSD Register 31"
hexmask.long 0x78 0.--31. 1. "ssd_index_992_1023,"
group.long 0x4080++0x3
line.long 0x0 "smmu_ssd_reg_32,SSD Register 32"
hexmask.long.tbyte 0x0 8.--31. 1. "ssd_index_1032_1055,"
bitfld.long 0x0 7. "ssd_index_1031," "0,1"
bitfld.long 0x0 6. "ssd_index_1030," "0,1"
newline
bitfld.long 0x0 5. "ssd_index_1029," "0,1"
bitfld.long 0x0 4. "ssd_index_1028," "0,1"
bitfld.long 0x0 3. "ssd_index_1027," "0,1"
newline
bitfld.long 0x0 2. "ssd_index_1026," "0,1"
bitfld.long 0x0 1. "ssd_index_1025," "0,1"
bitfld.long 0x0 0. "ssd_index_1024," "0,1"
rgroup.long 0x4084++0x7B
line.long 0x0 "smmu_ssd_reg_33,SSD Register 33"
hexmask.long 0x0 0.--31. 1. "ssd_index_1056_1087,"
line.long 0x4 "smmu_ssd_reg_34,SSD Register 34"
hexmask.long 0x4 0.--31. 1. "ssd_index_1088_1119,"
line.long 0x8 "smmu_ssd_reg_35,SSD Register 35"
hexmask.long 0x8 0.--31. 1. "ssd_index_1120_1151,"
line.long 0xC "smmu_ssd_reg_36,SSD Register 36"
hexmask.long 0xC 0.--31. 1. "ssd_index_1152_1183,"
line.long 0x10 "smmu_ssd_reg_37,SSD Register 37"
hexmask.long 0x10 0.--31. 1. "ssd_index_1184_1215,"
line.long 0x14 "smmu_ssd_reg_38,SSD Register 38"
hexmask.long 0x14 0.--31. 1. "ssd_index_1216_1247,"
line.long 0x18 "smmu_ssd_reg_39,SSD Register 39"
hexmask.long 0x18 0.--31. 1. "ssd_index_1248_1279,"
line.long 0x1C "smmu_ssd_reg_40,SSD Register 40"
hexmask.long 0x1C 0.--31. 1. "ssd_index_1280_1311,"
line.long 0x20 "smmu_ssd_reg_41,SSD Register 41"
hexmask.long 0x20 0.--31. 1. "ssd_index_1312_1343,"
line.long 0x24 "smmu_ssd_reg_42,SSD Register 42"
hexmask.long 0x24 0.--31. 1. "ssd_index_1344_1375,"
line.long 0x28 "smmu_ssd_reg_43,SSD Register 43"
hexmask.long 0x28 0.--31. 1. "ssd_index_1376_1407,"
line.long 0x2C "smmu_ssd_reg_44,SSD Register 44"
hexmask.long 0x2C 0.--31. 1. "ssd_index_1408_1439,"
line.long 0x30 "smmu_ssd_reg_45,SSD Register 45"
hexmask.long 0x30 0.--31. 1. "ssd_index_1440_1471,"
line.long 0x34 "smmu_ssd_reg_46,SSD Register 46"
hexmask.long 0x34 0.--31. 1. "ssd_index_1472_1503,"
line.long 0x38 "smmu_ssd_reg_47,SSD Register 47"
hexmask.long 0x38 0.--31. 1. "ssd_index_1504_1535,"
line.long 0x3C "smmu_ssd_reg_48,SSD Register 48"
hexmask.long 0x3C 0.--31. 1. "ssd_index_1536_1567,"
line.long 0x40 "smmu_ssd_reg_49,SSD Register 49"
hexmask.long 0x40 0.--31. 1. "ssd_index_1568_1599,"
line.long 0x44 "smmu_ssd_reg_50,SSD Register 50"
hexmask.long 0x44 0.--31. 1. "ssd_index_1600_1631,"
line.long 0x48 "smmu_ssd_reg_51,SSD Register 51"
hexmask.long 0x48 0.--31. 1. "ssd_index_1632_1663,"
line.long 0x4C "smmu_ssd_reg_52,SSD Register 52"
hexmask.long 0x4C 0.--31. 1. "ssd_index_1664_1695,"
line.long 0x50 "smmu_ssd_reg_53,SSD Register 53"
hexmask.long 0x50 0.--31. 1. "ssd_index_1696_1727,"
line.long 0x54 "smmu_ssd_reg_54,SSD Register 54"
hexmask.long 0x54 0.--31. 1. "ssd_index_1728_1759,"
line.long 0x58 "smmu_ssd_reg_55,SSD Register 55"
hexmask.long 0x58 0.--31. 1. "ssd_index_1760_1791,"
line.long 0x5C "smmu_ssd_reg_56,SSD Register 56"
hexmask.long 0x5C 0.--31. 1. "ssd_index_1792_1823,"
line.long 0x60 "smmu_ssd_reg_57,SSD Register 57"
hexmask.long 0x60 0.--31. 1. "ssd_index_1824_1855,"
line.long 0x64 "smmu_ssd_reg_58,SSD Register 58"
hexmask.long 0x64 0.--31. 1. "ssd_index_1856_1887,"
line.long 0x68 "smmu_ssd_reg_59,SSD Register 59"
hexmask.long 0x68 0.--31. 1. "ssd_index_1888_1919,"
line.long 0x6C "smmu_ssd_reg_60,SSD Register 60"
hexmask.long 0x6C 0.--31. 1. "ssd_index_1920_1951,"
line.long 0x70 "smmu_ssd_reg_61,SSD Register 61"
hexmask.long 0x70 0.--31. 1. "ssd_index_1952_1983,"
line.long 0x74 "smmu_ssd_reg_62,SSD Register 62"
hexmask.long 0x74 0.--31. 1. "ssd_index_1984_2015,"
line.long 0x78 "smmu_ssd_reg_63,SSD Register 63"
hexmask.long 0x78 0.--31. 1. "ssd_index_2016_2047,"
group.long 0x4100++0x3
line.long 0x0 "smmu_ssd_reg_64,SSD Register 64"
hexmask.long.tbyte 0x0 8.--31. 1. "ssd_index_2056_2079,"
bitfld.long 0x0 7. "ssd_index_2055," "0,1"
bitfld.long 0x0 6. "ssd_index_2054," "0,1"
newline
bitfld.long 0x0 5. "ssd_index_2053," "0,1"
bitfld.long 0x0 4. "ssd_index_2052," "0,1"
bitfld.long 0x0 3. "ssd_index_2051," "0,1"
newline
bitfld.long 0x0 2. "ssd_index_2050," "0,1"
bitfld.long 0x0 1. "ssd_index_2049," "0,1"
bitfld.long 0x0 0. "ssd_index_2048," "0,1"
rgroup.long 0x4104++0x7B
line.long 0x0 "smmu_ssd_reg_65,SSD Register 65"
hexmask.long 0x0 0.--31. 1. "ssd_index_2080_2111,"
line.long 0x4 "smmu_ssd_reg_66,SSD Register 66"
hexmask.long 0x4 0.--31. 1. "ssd_index_2112_2143,"
line.long 0x8 "smmu_ssd_reg_67,SSD Register 67"
hexmask.long 0x8 0.--31. 1. "ssd_index_2144_2175,"
line.long 0xC "smmu_ssd_reg_68,SSD Register 68"
hexmask.long 0xC 0.--31. 1. "ssd_index_2176_2207,"
line.long 0x10 "smmu_ssd_reg_69,SSD Register 69"
hexmask.long 0x10 0.--31. 1. "ssd_index_2208_2239,"
line.long 0x14 "smmu_ssd_reg_70,SSD Register 70"
hexmask.long 0x14 0.--31. 1. "ssd_index_2240_2271,"
line.long 0x18 "smmu_ssd_reg_71,SSD Register 71"
hexmask.long 0x18 0.--31. 1. "ssd_index_2272_2303,"
line.long 0x1C "smmu_ssd_reg_72,SSD Register 72"
hexmask.long 0x1C 0.--31. 1. "ssd_index_2304_2335,"
line.long 0x20 "smmu_ssd_reg_73,SSD Register 73"
hexmask.long 0x20 0.--31. 1. "ssd_index_2336_2367,"
line.long 0x24 "smmu_ssd_reg_74,SSD Register 74"
hexmask.long 0x24 0.--31. 1. "ssd_index_2368_2399,"
line.long 0x28 "smmu_ssd_reg_75,SSD Register 75"
hexmask.long 0x28 0.--31. 1. "ssd_index_2400_2431,"
line.long 0x2C "smmu_ssd_reg_76,SSD Register 76"
hexmask.long 0x2C 0.--31. 1. "ssd_index_2432_2463,"
line.long 0x30 "smmu_ssd_reg_77,SSD Register 77"
hexmask.long 0x30 0.--31. 1. "ssd_index_2464_2495,"
line.long 0x34 "smmu_ssd_reg_78,SSD Register 78"
hexmask.long 0x34 0.--31. 1. "ssd_index_2496_2527,"
line.long 0x38 "smmu_ssd_reg_79,SSD Register 79"
hexmask.long 0x38 0.--31. 1. "ssd_index_2528_2559,"
line.long 0x3C "smmu_ssd_reg_80,SSD Register 80"
hexmask.long 0x3C 0.--31. 1. "ssd_index_2560_2591,"
line.long 0x40 "smmu_ssd_reg_81,SSD Register 81"
hexmask.long 0x40 0.--31. 1. "ssd_index_2592_2623,"
line.long 0x44 "smmu_ssd_reg_82,SSD Register 82"
hexmask.long 0x44 0.--31. 1. "ssd_index_2624_2655,"
line.long 0x48 "smmu_ssd_reg_83,SSD Register 83"
hexmask.long 0x48 0.--31. 1. "ssd_index_2656_2687,"
line.long 0x4C "smmu_ssd_reg_84,SSD Register 84"
hexmask.long 0x4C 0.--31. 1. "ssd_index_2688_2719,"
line.long 0x50 "smmu_ssd_reg_85,SSD Register 85"
hexmask.long 0x50 0.--31. 1. "ssd_index_2720_2751,"
line.long 0x54 "smmu_ssd_reg_86,SSD Register 86"
hexmask.long 0x54 0.--31. 1. "ssd_index_2752_2783,"
line.long 0x58 "smmu_ssd_reg_87,SSD Register 87"
hexmask.long 0x58 0.--31. 1. "ssd_index_2784_2815,"
line.long 0x5C "smmu_ssd_reg_88,SSD Register 88"
hexmask.long 0x5C 0.--31. 1. "ssd_index_2816_2847,"
line.long 0x60 "smmu_ssd_reg_89,SSD Register 89"
hexmask.long 0x60 0.--31. 1. "ssd_index_2848_2879,"
line.long 0x64 "smmu_ssd_reg_90,SSD Register 90"
hexmask.long 0x64 0.--31. 1. "ssd_index_2880_2911,"
line.long 0x68 "smmu_ssd_reg_91,SSD Register 91"
hexmask.long 0x68 0.--31. 1. "ssd_index_2912_2943,"
line.long 0x6C "smmu_ssd_reg_92,SSD Register 92"
hexmask.long 0x6C 0.--31. 1. "ssd_index_2944_2975,"
line.long 0x70 "smmu_ssd_reg_93,SSD Register 93"
hexmask.long 0x70 0.--31. 1. "ssd_index_2976_3007,"
line.long 0x74 "smmu_ssd_reg_94,SSD Register 94"
hexmask.long 0x74 0.--31. 1. "ssd_index_3008_3039,"
line.long 0x78 "smmu_ssd_reg_95,SSD Register 95"
hexmask.long 0x78 0.--31. 1. "ssd_index_3040_3071,"
group.long 0x4180++0x3
line.long 0x0 "smmu_ssd_reg_96,SSD Register 96"
hexmask.long.tbyte 0x0 8.--31. 1. "ssd_index_3080_3103,"
bitfld.long 0x0 7. "ssd_index_3079," "0,1"
bitfld.long 0x0 6. "ssd_index_3078," "0,1"
newline
bitfld.long 0x0 5. "ssd_index_3077," "0,1"
bitfld.long 0x0 4. "ssd_index_3076," "0,1"
bitfld.long 0x0 3. "ssd_index_3075," "0,1"
newline
bitfld.long 0x0 2. "ssd_index_3074," "0,1"
bitfld.long 0x0 1. "ssd_index_3073," "0,1"
bitfld.long 0x0 0. "ssd_index_3072," "0,1"
rgroup.long 0x4184++0x7B
line.long 0x0 "smmu_ssd_reg_97,SSD Register 97"
hexmask.long 0x0 0.--31. 1. "ssd_index_3104_3135,"
line.long 0x4 "smmu_ssd_reg_98,SSD Register 98"
hexmask.long 0x4 0.--31. 1. "ssd_index_3136_3167,"
line.long 0x8 "smmu_ssd_reg_99,SSD Register 99"
hexmask.long 0x8 0.--31. 1. "ssd_index_3168_3199,"
line.long 0xC "smmu_ssd_reg_100,SSD Register 100"
hexmask.long 0xC 0.--31. 1. "ssd_index_3200_3231,"
line.long 0x10 "smmu_ssd_reg_101,SSD Register 101"
hexmask.long 0x10 0.--31. 1. "ssd_index_3232_3263,"
line.long 0x14 "smmu_ssd_reg_102,SSD Register 102"
hexmask.long 0x14 0.--31. 1. "ssd_index_3264_3295,"
line.long 0x18 "smmu_ssd_reg_103,SSD Register 103"
hexmask.long 0x18 0.--31. 1. "ssd_index_3296_3327,"
line.long 0x1C "smmu_ssd_reg_104,SSD Register 104"
hexmask.long 0x1C 0.--31. 1. "ssd_index_3328_3359,"
line.long 0x20 "smmu_ssd_reg_105,SSD Register 105"
hexmask.long 0x20 0.--31. 1. "ssd_index_3360_3391,"
line.long 0x24 "smmu_ssd_reg_106,SSD Register 106"
hexmask.long 0x24 0.--31. 1. "ssd_index_3392_3423,"
line.long 0x28 "smmu_ssd_reg_107,SSD Register 107"
hexmask.long 0x28 0.--31. 1. "ssd_index_3424_3455,"
line.long 0x2C "smmu_ssd_reg_108,SSD Register 108"
hexmask.long 0x2C 0.--31. 1. "ssd_index_3456_3487,"
line.long 0x30 "smmu_ssd_reg_109,SSD Register 109"
hexmask.long 0x30 0.--31. 1. "ssd_index_3488_3519,"
line.long 0x34 "smmu_ssd_reg_110,SSD Register 110"
hexmask.long 0x34 0.--31. 1. "ssd_index_3520_3551,"
line.long 0x38 "smmu_ssd_reg_111,SSD Register 111"
hexmask.long 0x38 0.--31. 1. "ssd_index_3552_3583,"
line.long 0x3C "smmu_ssd_reg_112,SSD Register 112"
hexmask.long 0x3C 0.--31. 1. "ssd_index_3584_3615,"
line.long 0x40 "smmu_ssd_reg_113,SSD Register 113"
hexmask.long 0x40 0.--31. 1. "ssd_index_3616_3647,"
line.long 0x44 "smmu_ssd_reg_114,SSD Register 114"
hexmask.long 0x44 0.--31. 1. "ssd_index_3648_3679,"
line.long 0x48 "smmu_ssd_reg_115,SSD Register 115"
hexmask.long 0x48 0.--31. 1. "ssd_index_3680_3711,"
line.long 0x4C "smmu_ssd_reg_116,SSD Register 116"
hexmask.long 0x4C 0.--31. 1. "ssd_index_3712_3743,"
line.long 0x50 "smmu_ssd_reg_117,SSD Register 117"
hexmask.long 0x50 0.--31. 1. "ssd_index_3744_3775,"
line.long 0x54 "smmu_ssd_reg_118,SSD Register 118"
hexmask.long 0x54 0.--31. 1. "ssd_index_3776_3807,"
line.long 0x58 "smmu_ssd_reg_119,SSD Register 119"
hexmask.long 0x58 0.--31. 1. "ssd_index_3808_3839,"
line.long 0x5C "smmu_ssd_reg_120,SSD Register 120"
hexmask.long 0x5C 0.--31. 1. "ssd_index_3840_3871,"
line.long 0x60 "smmu_ssd_reg_121,SSD Register 121"
hexmask.long 0x60 0.--31. 1. "ssd_index_3872_3903,"
line.long 0x64 "smmu_ssd_reg_122,SSD Register 122"
hexmask.long 0x64 0.--31. 1. "ssd_index_3904_3935,"
line.long 0x68 "smmu_ssd_reg_123,SSD Register 123"
hexmask.long 0x68 0.--31. 1. "ssd_index_3936_3967,"
line.long 0x6C "smmu_ssd_reg_124,SSD Register 124"
hexmask.long 0x6C 0.--31. 1. "ssd_index_3968_3999,"
line.long 0x70 "smmu_ssd_reg_125,SSD Register 125"
hexmask.long 0x70 0.--31. 1. "ssd_index_4000_4031,"
line.long 0x74 "smmu_ssd_reg_126,SSD Register 126"
hexmask.long 0x74 0.--31. 1. "ssd_index_4032_4063,"
line.long 0x78 "smmu_ssd_reg_127,SSD Register 127"
hexmask.long 0x78 0.--31. 1. "ssd_index_4064_4095,"
group.long 0x4200++0x3
line.long 0x0 "smmu_ssd_reg_128,SSD Register 128"
hexmask.long.tbyte 0x0 8.--31. 1. "ssd_index_4104_4127,"
bitfld.long 0x0 7. "ssd_index_4103," "0,1"
bitfld.long 0x0 6. "ssd_index_4102," "0,1"
newline
bitfld.long 0x0 5. "ssd_index_4101," "0,1"
bitfld.long 0x0 4. "ssd_index_4100," "0,1"
bitfld.long 0x0 3. "ssd_index_4099," "0,1"
newline
bitfld.long 0x0 2. "ssd_index_4098," "0,1"
bitfld.long 0x0 1. "ssd_index_4097," "0,1"
bitfld.long 0x0 0. "ssd_index_4096," "0,1"
rgroup.long 0x4204++0xDFB
line.long 0x0 "smmu_ssd_reg_129,SSD Register 129"
hexmask.long 0x0 0.--31. 1. "ssd_index_4128_4159,"
line.long 0x4 "smmu_ssd_reg_130,SSD Register 130"
hexmask.long 0x4 0.--31. 1. "ssd_index_4160_4191,"
line.long 0x8 "smmu_ssd_reg_131,SSD Register 131"
hexmask.long 0x8 0.--31. 1. "ssd_index_4192_4223,"
line.long 0xC "smmu_ssd_reg_132,SSD Register 132"
hexmask.long 0xC 0.--31. 1. "ssd_index_4224_4255,"
line.long 0x10 "smmu_ssd_reg_133,SSD Register 133"
hexmask.long 0x10 0.--31. 1. "ssd_index_4256_4287,"
line.long 0x14 "smmu_ssd_reg_134,SSD Register 134"
hexmask.long 0x14 0.--31. 1. "ssd_index_4288_4319,"
line.long 0x18 "smmu_ssd_reg_135,SSD Register 135"
hexmask.long 0x18 0.--31. 1. "ssd_index_4320_4351,"
line.long 0x1C "smmu_ssd_reg_136,SSD Register 136"
hexmask.long 0x1C 0.--31. 1. "ssd_index_4352_4383,"
line.long 0x20 "smmu_ssd_reg_137,SSD Register 137"
hexmask.long 0x20 0.--31. 1. "ssd_index_4384_4415,"
line.long 0x24 "smmu_ssd_reg_138,SSD Register 138"
hexmask.long 0x24 0.--31. 1. "ssd_index_4416_4447,"
line.long 0x28 "smmu_ssd_reg_139,SSD Register 139"
hexmask.long 0x28 0.--31. 1. "ssd_index_4448_4479,"
line.long 0x2C "smmu_ssd_reg_140,SSD Register 140"
hexmask.long 0x2C 0.--31. 1. "ssd_index_4480_4511,"
line.long 0x30 "smmu_ssd_reg_141,SSD Register 141"
hexmask.long 0x30 0.--31. 1. "ssd_index_4512_4543,"
line.long 0x34 "smmu_ssd_reg_142,SSD Register 142"
hexmask.long 0x34 0.--31. 1. "ssd_index_4544_4575,"
line.long 0x38 "smmu_ssd_reg_143,SSD Register 143"
hexmask.long 0x38 0.--31. 1. "ssd_index_4576_4607,"
line.long 0x3C "smmu_ssd_reg_144,SSD Register 144"
hexmask.long 0x3C 0.--31. 1. "ssd_index_4608_4639,"
line.long 0x40 "smmu_ssd_reg_145,SSD Register 145"
hexmask.long 0x40 0.--31. 1. "ssd_index_4640_4671,"
line.long 0x44 "smmu_ssd_reg_146,SSD Register 146"
hexmask.long 0x44 0.--31. 1. "ssd_index_4672_4703,"
line.long 0x48 "smmu_ssd_reg_147,SSD Register 147"
hexmask.long 0x48 0.--31. 1. "ssd_index_4704_4735,"
line.long 0x4C "smmu_ssd_reg_148,SSD Register 148"
hexmask.long 0x4C 0.--31. 1. "ssd_index_4736_4767,"
line.long 0x50 "smmu_ssd_reg_149,SSD Register 149"
hexmask.long 0x50 0.--31. 1. "ssd_index_4768_4799,"
line.long 0x54 "smmu_ssd_reg_150,SSD Register 150"
hexmask.long 0x54 0.--31. 1. "ssd_index_4800_4831,"
line.long 0x58 "smmu_ssd_reg_151,SSD Register 151"
hexmask.long 0x58 0.--31. 1. "ssd_index_4832_4863,"
line.long 0x5C "smmu_ssd_reg_152,SSD Register 152"
hexmask.long 0x5C 0.--31. 1. "ssd_index_4864_4895,"
line.long 0x60 "smmu_ssd_reg_153,SSD Register 153"
hexmask.long 0x60 0.--31. 1. "ssd_index_4896_4927,"
line.long 0x64 "smmu_ssd_reg_154,SSD Register 154"
hexmask.long 0x64 0.--31. 1. "ssd_index_4928_4959,"
line.long 0x68 "smmu_ssd_reg_155,SSD Register 155"
hexmask.long 0x68 0.--31. 1. "ssd_index_4960_4991,"
line.long 0x6C "smmu_ssd_reg_156,SSD Register 156"
hexmask.long 0x6C 0.--31. 1. "ssd_index_4992_5023,"
line.long 0x70 "smmu_ssd_reg_157,SSD Register 157"
hexmask.long 0x70 0.--31. 1. "ssd_index_5024_5055,"
line.long 0x74 "smmu_ssd_reg_158,SSD Register 158"
hexmask.long 0x74 0.--31. 1. "ssd_index_5056_5087,"
line.long 0x78 "smmu_ssd_reg_159,SSD Register 159"
hexmask.long 0x78 0.--31. 1. "ssd_index_5088_5119,"
line.long 0x7C "smmu_ssd_reg_160,SSD Register 160"
hexmask.long 0x7C 0.--31. 1. "ssd_index_5120_5151,"
line.long 0x80 "smmu_ssd_reg_161,SSD Register 161"
hexmask.long 0x80 0.--31. 1. "ssd_index_5152_5183,"
line.long 0x84 "smmu_ssd_reg_162,SSD Register 162"
hexmask.long 0x84 0.--31. 1. "ssd_index_5184_5215,"
line.long 0x88 "smmu_ssd_reg_163,SSD Register 163"
hexmask.long 0x88 0.--31. 1. "ssd_index_5216_5247,"
line.long 0x8C "smmu_ssd_reg_164,SSD Register 164"
hexmask.long 0x8C 0.--31. 1. "ssd_index_5248_5279,"
line.long 0x90 "smmu_ssd_reg_165,SSD Register 165"
hexmask.long 0x90 0.--31. 1. "ssd_index_5280_5311,"
line.long 0x94 "smmu_ssd_reg_166,SSD Register 166"
hexmask.long 0x94 0.--31. 1. "ssd_index_5312_5343,"
line.long 0x98 "smmu_ssd_reg_167,SSD Register 167"
hexmask.long 0x98 0.--31. 1. "ssd_index_5344_5375,"
line.long 0x9C "smmu_ssd_reg_168,SSD Register 168"
hexmask.long 0x9C 0.--31. 1. "ssd_index_5376_5407,"
line.long 0xA0 "smmu_ssd_reg_169,SSD Register 169"
hexmask.long 0xA0 0.--31. 1. "ssd_index_5408_5439,"
line.long 0xA4 "smmu_ssd_reg_170,SSD Register 170"
hexmask.long 0xA4 0.--31. 1. "ssd_index_5440_5471,"
line.long 0xA8 "smmu_ssd_reg_171,SSD Register 171"
hexmask.long 0xA8 0.--31. 1. "ssd_index_5472_5503,"
line.long 0xAC "smmu_ssd_reg_172,SSD Register 172"
hexmask.long 0xAC 0.--31. 1. "ssd_index_5504_5535,"
line.long 0xB0 "smmu_ssd_reg_173,SSD Register 173"
hexmask.long 0xB0 0.--31. 1. "ssd_index_5536_5567,"
line.long 0xB4 "smmu_ssd_reg_174,SSD Register 174"
hexmask.long 0xB4 0.--31. 1. "ssd_index_5568_5599,"
line.long 0xB8 "smmu_ssd_reg_175,SSD Register 175"
hexmask.long 0xB8 0.--31. 1. "ssd_index_5600_5631,"
line.long 0xBC "smmu_ssd_reg_176,SSD Register 176"
hexmask.long 0xBC 0.--31. 1. "ssd_index_5632_5663,"
line.long 0xC0 "smmu_ssd_reg_177,SSD Register 177"
hexmask.long 0xC0 0.--31. 1. "ssd_index_5664_5695,"
line.long 0xC4 "smmu_ssd_reg_178,SSD Register 178"
hexmask.long 0xC4 0.--31. 1. "ssd_index_5696_5727,"
line.long 0xC8 "smmu_ssd_reg_179,SSD Register 179"
hexmask.long 0xC8 0.--31. 1. "ssd_index_5728_5759,"
line.long 0xCC "smmu_ssd_reg_180,SSD Register 180"
hexmask.long 0xCC 0.--31. 1. "ssd_index_5760_5791,"
line.long 0xD0 "smmu_ssd_reg_181,SSD Register 181"
hexmask.long 0xD0 0.--31. 1. "ssd_index_5792_5823,"
line.long 0xD4 "smmu_ssd_reg_182,SSD Register 182"
hexmask.long 0xD4 0.--31. 1. "ssd_index_5824_5855,"
line.long 0xD8 "smmu_ssd_reg_183,SSD Register 183"
hexmask.long 0xD8 0.--31. 1. "ssd_index_5856_5887,"
line.long 0xDC "smmu_ssd_reg_184,SSD Register 184"
hexmask.long 0xDC 0.--31. 1. "ssd_index_5888_5919,"
line.long 0xE0 "smmu_ssd_reg_185,SSD Register 185"
hexmask.long 0xE0 0.--31. 1. "ssd_index_5920_5951,"
line.long 0xE4 "smmu_ssd_reg_186,SSD Register 186"
hexmask.long 0xE4 0.--31. 1. "ssd_index_5952_5983,"
line.long 0xE8 "smmu_ssd_reg_187,SSD Register 187"
hexmask.long 0xE8 0.--31. 1. "ssd_index_5984_6015,"
line.long 0xEC "smmu_ssd_reg_188,SSD Register 188"
hexmask.long 0xEC 0.--31. 1. "ssd_index_6016_6047,"
line.long 0xF0 "smmu_ssd_reg_189,SSD Register 189"
hexmask.long 0xF0 0.--31. 1. "ssd_index_6048_6079,"
line.long 0xF4 "smmu_ssd_reg_190,SSD Register 190"
hexmask.long 0xF4 0.--31. 1. "ssd_index_6080_6111,"
line.long 0xF8 "smmu_ssd_reg_191,SSD Register 191"
hexmask.long 0xF8 0.--31. 1. "ssd_index_6112_6143,"
line.long 0xFC "smmu_ssd_reg_192,SSD Register 192"
hexmask.long 0xFC 0.--31. 1. "ssd_index_6144_6175,"
line.long 0x100 "smmu_ssd_reg_193,SSD Register 193"
hexmask.long 0x100 0.--31. 1. "ssd_index_6176_6207,"
line.long 0x104 "smmu_ssd_reg_194,SSD Register 194"
hexmask.long 0x104 0.--31. 1. "ssd_index_6208_6239,"
line.long 0x108 "smmu_ssd_reg_195,SSD Register 195"
hexmask.long 0x108 0.--31. 1. "ssd_index_6240_6271,"
line.long 0x10C "smmu_ssd_reg_196,SSD Register 196"
hexmask.long 0x10C 0.--31. 1. "ssd_index_6272_6303,"
line.long 0x110 "smmu_ssd_reg_197,SSD Register 197"
hexmask.long 0x110 0.--31. 1. "ssd_index_6304_6335,"
line.long 0x114 "smmu_ssd_reg_198,SSD Register 198"
hexmask.long 0x114 0.--31. 1. "ssd_index_6336_6367,"
line.long 0x118 "smmu_ssd_reg_199,SSD Register 199"
hexmask.long 0x118 0.--31. 1. "ssd_index_6368_6399,"
line.long 0x11C "smmu_ssd_reg_200,SSD Register 200"
hexmask.long 0x11C 0.--31. 1. "ssd_index_6400_6431,"
line.long 0x120 "smmu_ssd_reg_201,SSD Register 201"
hexmask.long 0x120 0.--31. 1. "ssd_index_6432_6463,"
line.long 0x124 "smmu_ssd_reg_202,SSD Register 202"
hexmask.long 0x124 0.--31. 1. "ssd_index_6464_6495,"
line.long 0x128 "smmu_ssd_reg_203,SSD Register 203"
hexmask.long 0x128 0.--31. 1. "ssd_index_6496_6527,"
line.long 0x12C "smmu_ssd_reg_204,SSD Register 204"
hexmask.long 0x12C 0.--31. 1. "ssd_index_6528_6559,"
line.long 0x130 "smmu_ssd_reg_205,SSD Register 205"
hexmask.long 0x130 0.--31. 1. "ssd_index_6560_6591,"
line.long 0x134 "smmu_ssd_reg_206,SSD Register 206"
hexmask.long 0x134 0.--31. 1. "ssd_index_6592_6623,"
line.long 0x138 "smmu_ssd_reg_207,SSD Register 207"
hexmask.long 0x138 0.--31. 1. "ssd_index_6624_6655,"
line.long 0x13C "smmu_ssd_reg_208,SSD Register 208"
hexmask.long 0x13C 0.--31. 1. "ssd_index_6656_6687,"
line.long 0x140 "smmu_ssd_reg_209,SSD Register 209"
hexmask.long 0x140 0.--31. 1. "ssd_index_6688_6719,"
line.long 0x144 "smmu_ssd_reg_210,SSD Register 210"
hexmask.long 0x144 0.--31. 1. "ssd_index_6720_6751,"
line.long 0x148 "smmu_ssd_reg_211,SSD Register 211"
hexmask.long 0x148 0.--31. 1. "ssd_index_6752_6783,"
line.long 0x14C "smmu_ssd_reg_212,SSD Register 212"
hexmask.long 0x14C 0.--31. 1. "ssd_index_6784_6815,"
line.long 0x150 "smmu_ssd_reg_213,SSD Register 213"
hexmask.long 0x150 0.--31. 1. "ssd_index_6816_6847,"
line.long 0x154 "smmu_ssd_reg_214,SSD Register 214"
hexmask.long 0x154 0.--31. 1. "ssd_index_6848_6879,"
line.long 0x158 "smmu_ssd_reg_215,SSD Register 215"
hexmask.long 0x158 0.--31. 1. "ssd_index_6880_6911,"
line.long 0x15C "smmu_ssd_reg_216,SSD Register 216"
hexmask.long 0x15C 0.--31. 1. "ssd_index_6912_6943,"
line.long 0x160 "smmu_ssd_reg_217,SSD Register 217"
hexmask.long 0x160 0.--31. 1. "ssd_index_6944_6975,"
line.long 0x164 "smmu_ssd_reg_218,SSD Register 218"
hexmask.long 0x164 0.--31. 1. "ssd_index_6976_7007,"
line.long 0x168 "smmu_ssd_reg_219,SSD Register 219"
hexmask.long 0x168 0.--31. 1. "ssd_index_7008_7039,"
line.long 0x16C "smmu_ssd_reg_220,SSD Register 220"
hexmask.long 0x16C 0.--31. 1. "ssd_index_7040_7071,"
line.long 0x170 "smmu_ssd_reg_221,SSD Register 221"
hexmask.long 0x170 0.--31. 1. "ssd_index_7072_7103,"
line.long 0x174 "smmu_ssd_reg_222,SSD Register 222"
hexmask.long 0x174 0.--31. 1. "ssd_index_7104_7135,"
line.long 0x178 "smmu_ssd_reg_223,SSD Register 223"
hexmask.long 0x178 0.--31. 1. "ssd_index_7136_7167,"
line.long 0x17C "smmu_ssd_reg_224,SSD Register 224"
hexmask.long 0x17C 0.--31. 1. "ssd_index_7168_7199,"
line.long 0x180 "smmu_ssd_reg_225,SSD Register 225"
hexmask.long 0x180 0.--31. 1. "ssd_index_7200_7231,"
line.long 0x184 "smmu_ssd_reg_226,SSD Register 226"
hexmask.long 0x184 0.--31. 1. "ssd_index_7232_7263,"
line.long 0x188 "smmu_ssd_reg_227,SSD Register 227"
hexmask.long 0x188 0.--31. 1. "ssd_index_7264_7295,"
line.long 0x18C "smmu_ssd_reg_228,SSD Register 228"
hexmask.long 0x18C 0.--31. 1. "ssd_index_7296_7327,"
line.long 0x190 "smmu_ssd_reg_229,SSD Register 229"
hexmask.long 0x190 0.--31. 1. "ssd_index_7328_7359,"
line.long 0x194 "smmu_ssd_reg_230,SSD Register 230"
hexmask.long 0x194 0.--31. 1. "ssd_index_7360_7391,"
line.long 0x198 "smmu_ssd_reg_231,SSD Register 231"
hexmask.long 0x198 0.--31. 1. "ssd_index_7392_7423,"
line.long 0x19C "smmu_ssd_reg_232,SSD Register 232"
hexmask.long 0x19C 0.--31. 1. "ssd_index_7424_7455,"
line.long 0x1A0 "smmu_ssd_reg_233,SSD Register 233"
hexmask.long 0x1A0 0.--31. 1. "ssd_index_7456_7487,"
line.long 0x1A4 "smmu_ssd_reg_234,SSD Register 234"
hexmask.long 0x1A4 0.--31. 1. "ssd_index_7488_7519,"
line.long 0x1A8 "smmu_ssd_reg_235,SSD Register 235"
hexmask.long 0x1A8 0.--31. 1. "ssd_index_7520_7551,"
line.long 0x1AC "smmu_ssd_reg_236,SSD Register 236"
hexmask.long 0x1AC 0.--31. 1. "ssd_index_7552_7583,"
line.long 0x1B0 "smmu_ssd_reg_237,SSD Register 237"
hexmask.long 0x1B0 0.--31. 1. "ssd_index_7584_7615,"
line.long 0x1B4 "smmu_ssd_reg_238,SSD Register 238"
hexmask.long 0x1B4 0.--31. 1. "ssd_index_7616_7647,"
line.long 0x1B8 "smmu_ssd_reg_239,SSD Register 239"
hexmask.long 0x1B8 0.--31. 1. "ssd_index_7648_7679,"
line.long 0x1BC "smmu_ssd_reg_240,SSD Register 240"
hexmask.long 0x1BC 0.--31. 1. "ssd_index_7680_7711,"
line.long 0x1C0 "smmu_ssd_reg_241,SSD Register 241"
hexmask.long 0x1C0 0.--31. 1. "ssd_index_7712_7743,"
line.long 0x1C4 "smmu_ssd_reg_242,SSD Register 242"
hexmask.long 0x1C4 0.--31. 1. "ssd_index_7744_7775,"
line.long 0x1C8 "smmu_ssd_reg_243,SSD Register 243"
hexmask.long 0x1C8 0.--31. 1. "ssd_index_7776_7807,"
line.long 0x1CC "smmu_ssd_reg_244,SSD Register 244"
hexmask.long 0x1CC 0.--31. 1. "ssd_index_7808_7839,"
line.long 0x1D0 "smmu_ssd_reg_245,SSD Register 245"
hexmask.long 0x1D0 0.--31. 1. "ssd_index_7840_7871,"
line.long 0x1D4 "smmu_ssd_reg_246,SSD Register 246"
hexmask.long 0x1D4 0.--31. 1. "ssd_index_7872_7903,"
line.long 0x1D8 "smmu_ssd_reg_247,SSD Register 247"
hexmask.long 0x1D8 0.--31. 1. "ssd_index_7904_7935,"
line.long 0x1DC "smmu_ssd_reg_248,SSD Register 248"
hexmask.long 0x1DC 0.--31. 1. "ssd_index_7936_7967,"
line.long 0x1E0 "smmu_ssd_reg_249,SSD Register 249"
hexmask.long 0x1E0 0.--31. 1. "ssd_index_7968_7999,"
line.long 0x1E4 "smmu_ssd_reg_250,SSD Register 250"
hexmask.long 0x1E4 0.--31. 1. "ssd_index_8000_8031,"
line.long 0x1E8 "smmu_ssd_reg_251,SSD Register 251"
hexmask.long 0x1E8 0.--31. 1. "ssd_index_8032_8063,"
line.long 0x1EC "smmu_ssd_reg_252,SSD Register 252"
hexmask.long 0x1EC 0.--31. 1. "ssd_index_8064_8095,"
line.long 0x1F0 "smmu_ssd_reg_253,SSD Register 253"
hexmask.long 0x1F0 0.--31. 1. "ssd_index_8096_8127,"
line.long 0x1F4 "smmu_ssd_reg_254,SSD Register 254"
hexmask.long 0x1F4 0.--31. 1. "ssd_index_8128_8159,"
line.long 0x1F8 "smmu_ssd_reg_255,SSD Register 255"
hexmask.long 0x1F8 0.--31. 1. "ssd_index_8160_8191,"
line.long 0x1FC "smmu_ssd_reg_256,SSD Register 256"
hexmask.long 0x1FC 0.--31. 1. "ssd_index_8192_8223,"
line.long 0x200 "smmu_ssd_reg_257,SSD Register 257"
hexmask.long 0x200 0.--31. 1. "ssd_index_8224_8255,"
line.long 0x204 "smmu_ssd_reg_258,SSD Register 258"
hexmask.long 0x204 0.--31. 1. "ssd_index_8256_8287,"
line.long 0x208 "smmu_ssd_reg_259,SSD Register 259"
hexmask.long 0x208 0.--31. 1. "ssd_index_8288_8319,"
line.long 0x20C "smmu_ssd_reg_260,SSD Register 260"
hexmask.long 0x20C 0.--31. 1. "ssd_index_8320_8351,"
line.long 0x210 "smmu_ssd_reg_261,SSD Register 261"
hexmask.long 0x210 0.--31. 1. "ssd_index_8352_8383,"
line.long 0x214 "smmu_ssd_reg_262,SSD Register 262"
hexmask.long 0x214 0.--31. 1. "ssd_index_8384_8415,"
line.long 0x218 "smmu_ssd_reg_263,SSD Register 263"
hexmask.long 0x218 0.--31. 1. "ssd_index_8416_8447,"
line.long 0x21C "smmu_ssd_reg_264,SSD Register 264"
hexmask.long 0x21C 0.--31. 1. "ssd_index_8448_8479,"
line.long 0x220 "smmu_ssd_reg_265,SSD Register 265"
hexmask.long 0x220 0.--31. 1. "ssd_index_8480_8511,"
line.long 0x224 "smmu_ssd_reg_266,SSD Register 266"
hexmask.long 0x224 0.--31. 1. "ssd_index_8512_8543,"
line.long 0x228 "smmu_ssd_reg_267,SSD Register 267"
hexmask.long 0x228 0.--31. 1. "ssd_index_8544_8575,"
line.long 0x22C "smmu_ssd_reg_268,SSD Register 268"
hexmask.long 0x22C 0.--31. 1. "ssd_index_8576_8607,"
line.long 0x230 "smmu_ssd_reg_269,SSD Register 269"
hexmask.long 0x230 0.--31. 1. "ssd_index_8608_8639,"
line.long 0x234 "smmu_ssd_reg_270,SSD Register 270"
hexmask.long 0x234 0.--31. 1. "ssd_index_8640_8671,"
line.long 0x238 "smmu_ssd_reg_271,SSD Register 271"
hexmask.long 0x238 0.--31. 1. "ssd_index_8672_8703,"
line.long 0x23C "smmu_ssd_reg_272,SSD Register 272"
hexmask.long 0x23C 0.--31. 1. "ssd_index_8704_8735,"
line.long 0x240 "smmu_ssd_reg_273,SSD Register 273"
hexmask.long 0x240 0.--31. 1. "ssd_index_8736_8767,"
line.long 0x244 "smmu_ssd_reg_274,SSD Register 274"
hexmask.long 0x244 0.--31. 1. "ssd_index_8768_8799,"
line.long 0x248 "smmu_ssd_reg_275,SSD Register 275"
hexmask.long 0x248 0.--31. 1. "ssd_index_8800_8831,"
line.long 0x24C "smmu_ssd_reg_276,SSD Register 276"
hexmask.long 0x24C 0.--31. 1. "ssd_index_8832_8863,"
line.long 0x250 "smmu_ssd_reg_277,SSD Register 277"
hexmask.long 0x250 0.--31. 1. "ssd_index_8864_8895,"
line.long 0x254 "smmu_ssd_reg_278,SSD Register 278"
hexmask.long 0x254 0.--31. 1. "ssd_index_8896_8927,"
line.long 0x258 "smmu_ssd_reg_279,SSD Register 279"
hexmask.long 0x258 0.--31. 1. "ssd_index_8928_8959,"
line.long 0x25C "smmu_ssd_reg_280,SSD Register 280"
hexmask.long 0x25C 0.--31. 1. "ssd_index_8960_8991,"
line.long 0x260 "smmu_ssd_reg_281,SSD Register 281"
hexmask.long 0x260 0.--31. 1. "ssd_index_8992_9023,"
line.long 0x264 "smmu_ssd_reg_282,SSD Register 282"
hexmask.long 0x264 0.--31. 1. "ssd_index_9024_9055,"
line.long 0x268 "smmu_ssd_reg_283,SSD Register 283"
hexmask.long 0x268 0.--31. 1. "ssd_index_9056_9087,"
line.long 0x26C "smmu_ssd_reg_284,SSD Register 284"
hexmask.long 0x26C 0.--31. 1. "ssd_index_9088_9119,"
line.long 0x270 "smmu_ssd_reg_285,SSD Register 285"
hexmask.long 0x270 0.--31. 1. "ssd_index_9120_9151,"
line.long 0x274 "smmu_ssd_reg_286,SSD Register 286"
hexmask.long 0x274 0.--31. 1. "ssd_index_9152_9183,"
line.long 0x278 "smmu_ssd_reg_287,SSD Register 287"
hexmask.long 0x278 0.--31. 1. "ssd_index_9184_9215,"
line.long 0x27C "smmu_ssd_reg_288,SSD Register 288"
hexmask.long 0x27C 0.--31. 1. "ssd_index_9216_9247,"
line.long 0x280 "smmu_ssd_reg_289,SSD Register 289"
hexmask.long 0x280 0.--31. 1. "ssd_index_9248_9279,"
line.long 0x284 "smmu_ssd_reg_290,SSD Register 290"
hexmask.long 0x284 0.--31. 1. "ssd_index_9280_9311,"
line.long 0x288 "smmu_ssd_reg_291,SSD Register 291"
hexmask.long 0x288 0.--31. 1. "ssd_index_9312_9343,"
line.long 0x28C "smmu_ssd_reg_292,SSD Register 292"
hexmask.long 0x28C 0.--31. 1. "ssd_index_9344_9375,"
line.long 0x290 "smmu_ssd_reg_293,SSD Register 293"
hexmask.long 0x290 0.--31. 1. "ssd_index_9376_9407,"
line.long 0x294 "smmu_ssd_reg_294,SSD Register 294"
hexmask.long 0x294 0.--31. 1. "ssd_index_9408_9439,"
line.long 0x298 "smmu_ssd_reg_295,SSD Register 295"
hexmask.long 0x298 0.--31. 1. "ssd_index_9440_9471,"
line.long 0x29C "smmu_ssd_reg_296,SSD Register 296"
hexmask.long 0x29C 0.--31. 1. "ssd_index_9472_9503,"
line.long 0x2A0 "smmu_ssd_reg_297,SSD Register 297"
hexmask.long 0x2A0 0.--31. 1. "ssd_index_9504_9535,"
line.long 0x2A4 "smmu_ssd_reg_298,SSD Register 298"
hexmask.long 0x2A4 0.--31. 1. "ssd_index_9536_9567,"
line.long 0x2A8 "smmu_ssd_reg_299,SSD Register 299"
hexmask.long 0x2A8 0.--31. 1. "ssd_index_9568_9599,"
line.long 0x2AC "smmu_ssd_reg_300,SSD Register 300"
hexmask.long 0x2AC 0.--31. 1. "ssd_index_9600_9631,"
line.long 0x2B0 "smmu_ssd_reg_301,SSD Register 301"
hexmask.long 0x2B0 0.--31. 1. "ssd_index_9632_9663,"
line.long 0x2B4 "smmu_ssd_reg_302,SSD Register 302"
hexmask.long 0x2B4 0.--31. 1. "ssd_index_9664_9695,"
line.long 0x2B8 "smmu_ssd_reg_303,SSD Register 303"
hexmask.long 0x2B8 0.--31. 1. "ssd_index_9696_9727,"
line.long 0x2BC "smmu_ssd_reg_304,SSD Register 304"
hexmask.long 0x2BC 0.--31. 1. "ssd_index_9728_9759,"
line.long 0x2C0 "smmu_ssd_reg_305,SSD Register 305"
hexmask.long 0x2C0 0.--31. 1. "ssd_index_9760_9791,"
line.long 0x2C4 "smmu_ssd_reg_306,SSD Register 306"
hexmask.long 0x2C4 0.--31. 1. "ssd_index_9792_9823,"
line.long 0x2C8 "smmu_ssd_reg_307,SSD Register 307"
hexmask.long 0x2C8 0.--31. 1. "ssd_index_9824_9855,"
line.long 0x2CC "smmu_ssd_reg_308,SSD Register 308"
hexmask.long 0x2CC 0.--31. 1. "ssd_index_9856_9887,"
line.long 0x2D0 "smmu_ssd_reg_309,SSD Register 309"
hexmask.long 0x2D0 0.--31. 1. "ssd_index_9888_9919,"
line.long 0x2D4 "smmu_ssd_reg_310,SSD Register 310"
hexmask.long 0x2D4 0.--31. 1. "ssd_index_9920_9951,"
line.long 0x2D8 "smmu_ssd_reg_311,SSD Register 311"
hexmask.long 0x2D8 0.--31. 1. "ssd_index_9952_9983,"
line.long 0x2DC "smmu_ssd_reg_312,SSD Register 312"
hexmask.long 0x2DC 0.--31. 1. "ssd_index_9984_10015,"
line.long 0x2E0 "smmu_ssd_reg_313,SSD Register 313"
hexmask.long 0x2E0 0.--31. 1. "ssd_index_10016_10047,"
line.long 0x2E4 "smmu_ssd_reg_314,SSD Register 314"
hexmask.long 0x2E4 0.--31. 1. "ssd_index_10048_10079,"
line.long 0x2E8 "smmu_ssd_reg_315,SSD Register 315"
hexmask.long 0x2E8 0.--31. 1. "ssd_index_10080_10111,"
line.long 0x2EC "smmu_ssd_reg_316,SSD Register 316"
hexmask.long 0x2EC 0.--31. 1. "ssd_index_10112_10143,"
line.long 0x2F0 "smmu_ssd_reg_317,SSD Register 317"
hexmask.long 0x2F0 0.--31. 1. "ssd_index_10144_10175,"
line.long 0x2F4 "smmu_ssd_reg_318,SSD Register 318"
hexmask.long 0x2F4 0.--31. 1. "ssd_index_10176_10207,"
line.long 0x2F8 "smmu_ssd_reg_319,SSD Register 319"
hexmask.long 0x2F8 0.--31. 1. "ssd_index_10208_10239,"
line.long 0x2FC "smmu_ssd_reg_320,SSD Register 320"
hexmask.long 0x2FC 0.--31. 1. "ssd_index_10240_10271,"
line.long 0x300 "smmu_ssd_reg_321,SSD Register 321"
hexmask.long 0x300 0.--31. 1. "ssd_index_10272_10303,"
line.long 0x304 "smmu_ssd_reg_322,SSD Register 322"
hexmask.long 0x304 0.--31. 1. "ssd_index_10304_10335,"
line.long 0x308 "smmu_ssd_reg_323,SSD Register 323"
hexmask.long 0x308 0.--31. 1. "ssd_index_10336_10367,"
line.long 0x30C "smmu_ssd_reg_324,SSD Register 324"
hexmask.long 0x30C 0.--31. 1. "ssd_index_10368_10399,"
line.long 0x310 "smmu_ssd_reg_325,SSD Register 325"
hexmask.long 0x310 0.--31. 1. "ssd_index_10400_10431,"
line.long 0x314 "smmu_ssd_reg_326,SSD Register 326"
hexmask.long 0x314 0.--31. 1. "ssd_index_10432_10463,"
line.long 0x318 "smmu_ssd_reg_327,SSD Register 327"
hexmask.long 0x318 0.--31. 1. "ssd_index_10464_10495,"
line.long 0x31C "smmu_ssd_reg_328,SSD Register 328"
hexmask.long 0x31C 0.--31. 1. "ssd_index_10496_10527,"
line.long 0x320 "smmu_ssd_reg_329,SSD Register 329"
hexmask.long 0x320 0.--31. 1. "ssd_index_10528_10559,"
line.long 0x324 "smmu_ssd_reg_330,SSD Register 330"
hexmask.long 0x324 0.--31. 1. "ssd_index_10560_10591,"
line.long 0x328 "smmu_ssd_reg_331,SSD Register 331"
hexmask.long 0x328 0.--31. 1. "ssd_index_10592_10623,"
line.long 0x32C "smmu_ssd_reg_332,SSD Register 332"
hexmask.long 0x32C 0.--31. 1. "ssd_index_10624_10655,"
line.long 0x330 "smmu_ssd_reg_333,SSD Register 333"
hexmask.long 0x330 0.--31. 1. "ssd_index_10656_10687,"
line.long 0x334 "smmu_ssd_reg_334,SSD Register 334"
hexmask.long 0x334 0.--31. 1. "ssd_index_10688_10719,"
line.long 0x338 "smmu_ssd_reg_335,SSD Register 335"
hexmask.long 0x338 0.--31. 1. "ssd_index_10720_10751,"
line.long 0x33C "smmu_ssd_reg_336,SSD Register 336"
hexmask.long 0x33C 0.--31. 1. "ssd_index_10752_10783,"
line.long 0x340 "smmu_ssd_reg_337,SSD Register 337"
hexmask.long 0x340 0.--31. 1. "ssd_index_10784_10815,"
line.long 0x344 "smmu_ssd_reg_338,SSD Register 338"
hexmask.long 0x344 0.--31. 1. "ssd_index_10816_10847,"
line.long 0x348 "smmu_ssd_reg_339,SSD Register 339"
hexmask.long 0x348 0.--31. 1. "ssd_index_10848_10879,"
line.long 0x34C "smmu_ssd_reg_340,SSD Register 340"
hexmask.long 0x34C 0.--31. 1. "ssd_index_10880_10911,"
line.long 0x350 "smmu_ssd_reg_341,SSD Register 341"
hexmask.long 0x350 0.--31. 1. "ssd_index_10912_10943,"
line.long 0x354 "smmu_ssd_reg_342,SSD Register 342"
hexmask.long 0x354 0.--31. 1. "ssd_index_10944_10975,"
line.long 0x358 "smmu_ssd_reg_343,SSD Register 343"
hexmask.long 0x358 0.--31. 1. "ssd_index_10976_11007,"
line.long 0x35C "smmu_ssd_reg_344,SSD Register 344"
hexmask.long 0x35C 0.--31. 1. "ssd_index_11008_11039,"
line.long 0x360 "smmu_ssd_reg_345,SSD Register 345"
hexmask.long 0x360 0.--31. 1. "ssd_index_11040_11071,"
line.long 0x364 "smmu_ssd_reg_346,SSD Register 346"
hexmask.long 0x364 0.--31. 1. "ssd_index_11072_11103,"
line.long 0x368 "smmu_ssd_reg_347,SSD Register 347"
hexmask.long 0x368 0.--31. 1. "ssd_index_11104_11135,"
line.long 0x36C "smmu_ssd_reg_348,SSD Register 348"
hexmask.long 0x36C 0.--31. 1. "ssd_index_11136_11167,"
line.long 0x370 "smmu_ssd_reg_349,SSD Register 349"
hexmask.long 0x370 0.--31. 1. "ssd_index_11168_11199,"
line.long 0x374 "smmu_ssd_reg_350,SSD Register 350"
hexmask.long 0x374 0.--31. 1. "ssd_index_11200_11231,"
line.long 0x378 "smmu_ssd_reg_351,SSD Register 351"
hexmask.long 0x378 0.--31. 1. "ssd_index_11232_11263,"
line.long 0x37C "smmu_ssd_reg_352,SSD Register 352"
hexmask.long 0x37C 0.--31. 1. "ssd_index_11264_11295,"
line.long 0x380 "smmu_ssd_reg_353,SSD Register 353"
hexmask.long 0x380 0.--31. 1. "ssd_index_11296_11327,"
line.long 0x384 "smmu_ssd_reg_354,SSD Register 354"
hexmask.long 0x384 0.--31. 1. "ssd_index_11328_11359,"
line.long 0x388 "smmu_ssd_reg_355,SSD Register 355"
hexmask.long 0x388 0.--31. 1. "ssd_index_11360_11391,"
line.long 0x38C "smmu_ssd_reg_356,SSD Register 356"
hexmask.long 0x38C 0.--31. 1. "ssd_index_11392_11423,"
line.long 0x390 "smmu_ssd_reg_357,SSD Register 357"
hexmask.long 0x390 0.--31. 1. "ssd_index_11424_11455,"
line.long 0x394 "smmu_ssd_reg_358,SSD Register 358"
hexmask.long 0x394 0.--31. 1. "ssd_index_11456_11487,"
line.long 0x398 "smmu_ssd_reg_359,SSD Register 359"
hexmask.long 0x398 0.--31. 1. "ssd_index_11488_11519,"
line.long 0x39C "smmu_ssd_reg_360,SSD Register 360"
hexmask.long 0x39C 0.--31. 1. "ssd_index_11520_11551,"
line.long 0x3A0 "smmu_ssd_reg_361,SSD Register 361"
hexmask.long 0x3A0 0.--31. 1. "ssd_index_11552_11583,"
line.long 0x3A4 "smmu_ssd_reg_362,SSD Register 362"
hexmask.long 0x3A4 0.--31. 1. "ssd_index_11584_11615,"
line.long 0x3A8 "smmu_ssd_reg_363,SSD Register 363"
hexmask.long 0x3A8 0.--31. 1. "ssd_index_11616_11647,"
line.long 0x3AC "smmu_ssd_reg_364,SSD Register 364"
hexmask.long 0x3AC 0.--31. 1. "ssd_index_11648_11679,"
line.long 0x3B0 "smmu_ssd_reg_365,SSD Register 365"
hexmask.long 0x3B0 0.--31. 1. "ssd_index_11680_11711,"
line.long 0x3B4 "smmu_ssd_reg_366,SSD Register 366"
hexmask.long 0x3B4 0.--31. 1. "ssd_index_11712_11743,"
line.long 0x3B8 "smmu_ssd_reg_367,SSD Register 367"
hexmask.long 0x3B8 0.--31. 1. "ssd_index_11744_11775,"
line.long 0x3BC "smmu_ssd_reg_368,SSD Register 368"
hexmask.long 0x3BC 0.--31. 1. "ssd_index_11776_11807,"
line.long 0x3C0 "smmu_ssd_reg_369,SSD Register 369"
hexmask.long 0x3C0 0.--31. 1. "ssd_index_11808_11839,"
line.long 0x3C4 "smmu_ssd_reg_370,SSD Register 370"
hexmask.long 0x3C4 0.--31. 1. "ssd_index_11840_11871,"
line.long 0x3C8 "smmu_ssd_reg_371,SSD Register 371"
hexmask.long 0x3C8 0.--31. 1. "ssd_index_11872_11903,"
line.long 0x3CC "smmu_ssd_reg_372,SSD Register 372"
hexmask.long 0x3CC 0.--31. 1. "ssd_index_11904_11935,"
line.long 0x3D0 "smmu_ssd_reg_373,SSD Register 373"
hexmask.long 0x3D0 0.--31. 1. "ssd_index_11936_11967,"
line.long 0x3D4 "smmu_ssd_reg_374,SSD Register 374"
hexmask.long 0x3D4 0.--31. 1. "ssd_index_11968_11999,"
line.long 0x3D8 "smmu_ssd_reg_375,SSD Register 375"
hexmask.long 0x3D8 0.--31. 1. "ssd_index_12000_12031,"
line.long 0x3DC "smmu_ssd_reg_376,SSD Register 376"
hexmask.long 0x3DC 0.--31. 1. "ssd_index_12032_12063,"
line.long 0x3E0 "smmu_ssd_reg_377,SSD Register 377"
hexmask.long 0x3E0 0.--31. 1. "ssd_index_12064_12095,"
line.long 0x3E4 "smmu_ssd_reg_378,SSD Register 378"
hexmask.long 0x3E4 0.--31. 1. "ssd_index_12096_12127,"
line.long 0x3E8 "smmu_ssd_reg_379,SSD Register 379"
hexmask.long 0x3E8 0.--31. 1. "ssd_index_12128_12159,"
line.long 0x3EC "smmu_ssd_reg_380,SSD Register 380"
hexmask.long 0x3EC 0.--31. 1. "ssd_index_12160_12191,"
line.long 0x3F0 "smmu_ssd_reg_381,SSD Register 381"
hexmask.long 0x3F0 0.--31. 1. "ssd_index_12192_12223,"
line.long 0x3F4 "smmu_ssd_reg_382,SSD Register 382"
hexmask.long 0x3F4 0.--31. 1. "ssd_index_12224_12255,"
line.long 0x3F8 "smmu_ssd_reg_383,SSD Register 383"
hexmask.long 0x3F8 0.--31. 1. "ssd_index_12256_12287,"
line.long 0x3FC "smmu_ssd_reg_384,SSD Register 384"
hexmask.long 0x3FC 0.--31. 1. "ssd_index_12288_12319,"
line.long 0x400 "smmu_ssd_reg_385,SSD Register 385"
hexmask.long 0x400 0.--31. 1. "ssd_index_12320_12351,"
line.long 0x404 "smmu_ssd_reg_386,SSD Register 386"
hexmask.long 0x404 0.--31. 1. "ssd_index_12352_12383,"
line.long 0x408 "smmu_ssd_reg_387,SSD Register 387"
hexmask.long 0x408 0.--31. 1. "ssd_index_12384_12415,"
line.long 0x40C "smmu_ssd_reg_388,SSD Register 388"
hexmask.long 0x40C 0.--31. 1. "ssd_index_12416_12447,"
line.long 0x410 "smmu_ssd_reg_389,SSD Register 389"
hexmask.long 0x410 0.--31. 1. "ssd_index_12448_12479,"
line.long 0x414 "smmu_ssd_reg_390,SSD Register 390"
hexmask.long 0x414 0.--31. 1. "ssd_index_12480_12511,"
line.long 0x418 "smmu_ssd_reg_391,SSD Register 391"
hexmask.long 0x418 0.--31. 1. "ssd_index_12512_12543,"
line.long 0x41C "smmu_ssd_reg_392,SSD Register 392"
hexmask.long 0x41C 0.--31. 1. "ssd_index_12544_12575,"
line.long 0x420 "smmu_ssd_reg_393,SSD Register 393"
hexmask.long 0x420 0.--31. 1. "ssd_index_12576_12607,"
line.long 0x424 "smmu_ssd_reg_394,SSD Register 394"
hexmask.long 0x424 0.--31. 1. "ssd_index_12608_12639,"
line.long 0x428 "smmu_ssd_reg_395,SSD Register 395"
hexmask.long 0x428 0.--31. 1. "ssd_index_12640_12671,"
line.long 0x42C "smmu_ssd_reg_396,SSD Register 396"
hexmask.long 0x42C 0.--31. 1. "ssd_index_12672_12703,"
line.long 0x430 "smmu_ssd_reg_397,SSD Register 397"
hexmask.long 0x430 0.--31. 1. "ssd_index_12704_12735,"
line.long 0x434 "smmu_ssd_reg_398,SSD Register 398"
hexmask.long 0x434 0.--31. 1. "ssd_index_12736_12767,"
line.long 0x438 "smmu_ssd_reg_399,SSD Register 399"
hexmask.long 0x438 0.--31. 1. "ssd_index_12768_12799,"
line.long 0x43C "smmu_ssd_reg_400,SSD Register 400"
hexmask.long 0x43C 0.--31. 1. "ssd_index_12800_12831,"
line.long 0x440 "smmu_ssd_reg_401,SSD Register 401"
hexmask.long 0x440 0.--31. 1. "ssd_index_12832_12863,"
line.long 0x444 "smmu_ssd_reg_402,SSD Register 402"
hexmask.long 0x444 0.--31. 1. "ssd_index_12864_12895,"
line.long 0x448 "smmu_ssd_reg_403,SSD Register 403"
hexmask.long 0x448 0.--31. 1. "ssd_index_12896_12927,"
line.long 0x44C "smmu_ssd_reg_404,SSD Register 404"
hexmask.long 0x44C 0.--31. 1. "ssd_index_12928_12959,"
line.long 0x450 "smmu_ssd_reg_405,SSD Register 405"
hexmask.long 0x450 0.--31. 1. "ssd_index_12960_12991,"
line.long 0x454 "smmu_ssd_reg_406,SSD Register 406"
hexmask.long 0x454 0.--31. 1. "ssd_index_12992_13023,"
line.long 0x458 "smmu_ssd_reg_407,SSD Register 407"
hexmask.long 0x458 0.--31. 1. "ssd_index_13024_13055,"
line.long 0x45C "smmu_ssd_reg_408,SSD Register 408"
hexmask.long 0x45C 0.--31. 1. "ssd_index_13056_13087,"
line.long 0x460 "smmu_ssd_reg_409,SSD Register 409"
hexmask.long 0x460 0.--31. 1. "ssd_index_13088_13119,"
line.long 0x464 "smmu_ssd_reg_410,SSD Register 410"
hexmask.long 0x464 0.--31. 1. "ssd_index_13120_13151,"
line.long 0x468 "smmu_ssd_reg_411,SSD Register 411"
hexmask.long 0x468 0.--31. 1. "ssd_index_13152_13183,"
line.long 0x46C "smmu_ssd_reg_412,SSD Register 412"
hexmask.long 0x46C 0.--31. 1. "ssd_index_13184_13215,"
line.long 0x470 "smmu_ssd_reg_413,SSD Register 413"
hexmask.long 0x470 0.--31. 1. "ssd_index_13216_13247,"
line.long 0x474 "smmu_ssd_reg_414,SSD Register 414"
hexmask.long 0x474 0.--31. 1. "ssd_index_13248_13279,"
line.long 0x478 "smmu_ssd_reg_415,SSD Register 415"
hexmask.long 0x478 0.--31. 1. "ssd_index_13280_13311,"
line.long 0x47C "smmu_ssd_reg_416,SSD Register 416"
hexmask.long 0x47C 0.--31. 1. "ssd_index_13312_13343,"
line.long 0x480 "smmu_ssd_reg_417,SSD Register 417"
hexmask.long 0x480 0.--31. 1. "ssd_index_13344_13375,"
line.long 0x484 "smmu_ssd_reg_418,SSD Register 418"
hexmask.long 0x484 0.--31. 1. "ssd_index_13376_13407,"
line.long 0x488 "smmu_ssd_reg_419,SSD Register 419"
hexmask.long 0x488 0.--31. 1. "ssd_index_13408_13439,"
line.long 0x48C "smmu_ssd_reg_420,SSD Register 420"
hexmask.long 0x48C 0.--31. 1. "ssd_index_13440_13471,"
line.long 0x490 "smmu_ssd_reg_421,SSD Register 421"
hexmask.long 0x490 0.--31. 1. "ssd_index_13472_13503,"
line.long 0x494 "smmu_ssd_reg_422,SSD Register 422"
hexmask.long 0x494 0.--31. 1. "ssd_index_13504_13535,"
line.long 0x498 "smmu_ssd_reg_423,SSD Register 423"
hexmask.long 0x498 0.--31. 1. "ssd_index_13536_13567,"
line.long 0x49C "smmu_ssd_reg_424,SSD Register 424"
hexmask.long 0x49C 0.--31. 1. "ssd_index_13568_13599,"
line.long 0x4A0 "smmu_ssd_reg_425,SSD Register 425"
hexmask.long 0x4A0 0.--31. 1. "ssd_index_13600_13631,"
line.long 0x4A4 "smmu_ssd_reg_426,SSD Register 426"
hexmask.long 0x4A4 0.--31. 1. "ssd_index_13632_13663,"
line.long 0x4A8 "smmu_ssd_reg_427,SSD Register 427"
hexmask.long 0x4A8 0.--31. 1. "ssd_index_13664_13695,"
line.long 0x4AC "smmu_ssd_reg_428,SSD Register 428"
hexmask.long 0x4AC 0.--31. 1. "ssd_index_13696_13727,"
line.long 0x4B0 "smmu_ssd_reg_429,SSD Register 429"
hexmask.long 0x4B0 0.--31. 1. "ssd_index_13728_13759,"
line.long 0x4B4 "smmu_ssd_reg_430,SSD Register 430"
hexmask.long 0x4B4 0.--31. 1. "ssd_index_13760_13791,"
line.long 0x4B8 "smmu_ssd_reg_431,SSD Register 431"
hexmask.long 0x4B8 0.--31. 1. "ssd_index_13792_13823,"
line.long 0x4BC "smmu_ssd_reg_432,SSD Register 432"
hexmask.long 0x4BC 0.--31. 1. "ssd_index_13824_13855,"
line.long 0x4C0 "smmu_ssd_reg_433,SSD Register 433"
hexmask.long 0x4C0 0.--31. 1. "ssd_index_13856_13887,"
line.long 0x4C4 "smmu_ssd_reg_434,SSD Register 434"
hexmask.long 0x4C4 0.--31. 1. "ssd_index_13888_13919,"
line.long 0x4C8 "smmu_ssd_reg_435,SSD Register 435"
hexmask.long 0x4C8 0.--31. 1. "ssd_index_13920_13951,"
line.long 0x4CC "smmu_ssd_reg_436,SSD Register 436"
hexmask.long 0x4CC 0.--31. 1. "ssd_index_13952_13983,"
line.long 0x4D0 "smmu_ssd_reg_437,SSD Register 437"
hexmask.long 0x4D0 0.--31. 1. "ssd_index_13984_14015,"
line.long 0x4D4 "smmu_ssd_reg_438,SSD Register 438"
hexmask.long 0x4D4 0.--31. 1. "ssd_index_14016_14047,"
line.long 0x4D8 "smmu_ssd_reg_439,SSD Register 439"
hexmask.long 0x4D8 0.--31. 1. "ssd_index_14048_14079,"
line.long 0x4DC "smmu_ssd_reg_440,SSD Register 440"
hexmask.long 0x4DC 0.--31. 1. "ssd_index_14080_14111,"
line.long 0x4E0 "smmu_ssd_reg_441,SSD Register 441"
hexmask.long 0x4E0 0.--31. 1. "ssd_index_14112_14143,"
line.long 0x4E4 "smmu_ssd_reg_442,SSD Register 442"
hexmask.long 0x4E4 0.--31. 1. "ssd_index_14144_14175,"
line.long 0x4E8 "smmu_ssd_reg_443,SSD Register 443"
hexmask.long 0x4E8 0.--31. 1. "ssd_index_14176_14207,"
line.long 0x4EC "smmu_ssd_reg_444,SSD Register 444"
hexmask.long 0x4EC 0.--31. 1. "ssd_index_14208_14239,"
line.long 0x4F0 "smmu_ssd_reg_445,SSD Register 445"
hexmask.long 0x4F0 0.--31. 1. "ssd_index_14240_14271,"
line.long 0x4F4 "smmu_ssd_reg_446,SSD Register 446"
hexmask.long 0x4F4 0.--31. 1. "ssd_index_14272_14303,"
line.long 0x4F8 "smmu_ssd_reg_447,SSD Register 447"
hexmask.long 0x4F8 0.--31. 1. "ssd_index_14304_14335,"
line.long 0x4FC "smmu_ssd_reg_448,SSD Register 448"
hexmask.long 0x4FC 0.--31. 1. "ssd_index_14336_14367,"
line.long 0x500 "smmu_ssd_reg_449,SSD Register 449"
hexmask.long 0x500 0.--31. 1. "ssd_index_14368_14399,"
line.long 0x504 "smmu_ssd_reg_450,SSD Register 450"
hexmask.long 0x504 0.--31. 1. "ssd_index_14400_14431,"
line.long 0x508 "smmu_ssd_reg_451,SSD Register 451"
hexmask.long 0x508 0.--31. 1. "ssd_index_14432_14463,"
line.long 0x50C "smmu_ssd_reg_452,SSD Register 452"
hexmask.long 0x50C 0.--31. 1. "ssd_index_14464_14495,"
line.long 0x510 "smmu_ssd_reg_453,SSD Register 453"
hexmask.long 0x510 0.--31. 1. "ssd_index_14496_14527,"
line.long 0x514 "smmu_ssd_reg_454,SSD Register 454"
hexmask.long 0x514 0.--31. 1. "ssd_index_14528_14559,"
line.long 0x518 "smmu_ssd_reg_455,SSD Register 455"
hexmask.long 0x518 0.--31. 1. "ssd_index_14560_14591,"
line.long 0x51C "smmu_ssd_reg_456,SSD Register 456"
hexmask.long 0x51C 0.--31. 1. "ssd_index_14592_14623,"
line.long 0x520 "smmu_ssd_reg_457,SSD Register 457"
hexmask.long 0x520 0.--31. 1. "ssd_index_14624_14655,"
line.long 0x524 "smmu_ssd_reg_458,SSD Register 458"
hexmask.long 0x524 0.--31. 1. "ssd_index_14656_14687,"
line.long 0x528 "smmu_ssd_reg_459,SSD Register 459"
hexmask.long 0x528 0.--31. 1. "ssd_index_14688_14719,"
line.long 0x52C "smmu_ssd_reg_460,SSD Register 460"
hexmask.long 0x52C 0.--31. 1. "ssd_index_14720_14751,"
line.long 0x530 "smmu_ssd_reg_461,SSD Register 461"
hexmask.long 0x530 0.--31. 1. "ssd_index_14752_14783,"
line.long 0x534 "smmu_ssd_reg_462,SSD Register 462"
hexmask.long 0x534 0.--31. 1. "ssd_index_14784_14815,"
line.long 0x538 "smmu_ssd_reg_463,SSD Register 463"
hexmask.long 0x538 0.--31. 1. "ssd_index_14816_14847,"
line.long 0x53C "smmu_ssd_reg_464,SSD Register 464"
hexmask.long 0x53C 0.--31. 1. "ssd_index_14848_14879,"
line.long 0x540 "smmu_ssd_reg_465,SSD Register 465"
hexmask.long 0x540 0.--31. 1. "ssd_index_14880_14911,"
line.long 0x544 "smmu_ssd_reg_466,SSD Register 466"
hexmask.long 0x544 0.--31. 1. "ssd_index_14912_14943,"
line.long 0x548 "smmu_ssd_reg_467,SSD Register 467"
hexmask.long 0x548 0.--31. 1. "ssd_index_14944_14975,"
line.long 0x54C "smmu_ssd_reg_468,SSD Register 468"
hexmask.long 0x54C 0.--31. 1. "ssd_index_14976_15007,"
line.long 0x550 "smmu_ssd_reg_469,SSD Register 469"
hexmask.long 0x550 0.--31. 1. "ssd_index_15008_15039,"
line.long 0x554 "smmu_ssd_reg_470,SSD Register 470"
hexmask.long 0x554 0.--31. 1. "ssd_index_15040_15071,"
line.long 0x558 "smmu_ssd_reg_471,SSD Register 471"
hexmask.long 0x558 0.--31. 1. "ssd_index_15072_15103,"
line.long 0x55C "smmu_ssd_reg_472,SSD Register 472"
hexmask.long 0x55C 0.--31. 1. "ssd_index_15104_15135,"
line.long 0x560 "smmu_ssd_reg_473,SSD Register 473"
hexmask.long 0x560 0.--31. 1. "ssd_index_15136_15167,"
line.long 0x564 "smmu_ssd_reg_474,SSD Register 474"
hexmask.long 0x564 0.--31. 1. "ssd_index_15168_15199,"
line.long 0x568 "smmu_ssd_reg_475,SSD Register 475"
hexmask.long 0x568 0.--31. 1. "ssd_index_15200_15231,"
line.long 0x56C "smmu_ssd_reg_476,SSD Register 476"
hexmask.long 0x56C 0.--31. 1. "ssd_index_15232_15263,"
line.long 0x570 "smmu_ssd_reg_477,SSD Register 477"
hexmask.long 0x570 0.--31. 1. "ssd_index_15264_15295,"
line.long 0x574 "smmu_ssd_reg_478,SSD Register 478"
hexmask.long 0x574 0.--31. 1. "ssd_index_15296_15327,"
line.long 0x578 "smmu_ssd_reg_479,SSD Register 479"
hexmask.long 0x578 0.--31. 1. "ssd_index_15328_15359,"
line.long 0x57C "smmu_ssd_reg_480,SSD Register 480"
hexmask.long 0x57C 0.--31. 1. "ssd_index_15360_15391,"
line.long 0x580 "smmu_ssd_reg_481,SSD Register 481"
hexmask.long 0x580 0.--31. 1. "ssd_index_15392_15423,"
line.long 0x584 "smmu_ssd_reg_482,SSD Register 482"
hexmask.long 0x584 0.--31. 1. "ssd_index_15424_15455,"
line.long 0x588 "smmu_ssd_reg_483,SSD Register 483"
hexmask.long 0x588 0.--31. 1. "ssd_index_15456_15487,"
line.long 0x58C "smmu_ssd_reg_484,SSD Register 484"
hexmask.long 0x58C 0.--31. 1. "ssd_index_15488_15519,"
line.long 0x590 "smmu_ssd_reg_485,SSD Register 485"
hexmask.long 0x590 0.--31. 1. "ssd_index_15520_15551,"
line.long 0x594 "smmu_ssd_reg_486,SSD Register 486"
hexmask.long 0x594 0.--31. 1. "ssd_index_15552_15583,"
line.long 0x598 "smmu_ssd_reg_487,SSD Register 487"
hexmask.long 0x598 0.--31. 1. "ssd_index_15584_15615,"
line.long 0x59C "smmu_ssd_reg_488,SSD Register 488"
hexmask.long 0x59C 0.--31. 1. "ssd_index_15616_15647,"
line.long 0x5A0 "smmu_ssd_reg_489,SSD Register 489"
hexmask.long 0x5A0 0.--31. 1. "ssd_index_15648_15679,"
line.long 0x5A4 "smmu_ssd_reg_490,SSD Register 490"
hexmask.long 0x5A4 0.--31. 1. "ssd_index_15680_15711,"
line.long 0x5A8 "smmu_ssd_reg_491,SSD Register 491"
hexmask.long 0x5A8 0.--31. 1. "ssd_index_15712_15743,"
line.long 0x5AC "smmu_ssd_reg_492,SSD Register 492"
hexmask.long 0x5AC 0.--31. 1. "ssd_index_15744_15775,"
line.long 0x5B0 "smmu_ssd_reg_493,SSD Register 493"
hexmask.long 0x5B0 0.--31. 1. "ssd_index_15776_15807,"
line.long 0x5B4 "smmu_ssd_reg_494,SSD Register 494"
hexmask.long 0x5B4 0.--31. 1. "ssd_index_15808_15839,"
line.long 0x5B8 "smmu_ssd_reg_495,SSD Register 495"
hexmask.long 0x5B8 0.--31. 1. "ssd_index_15840_15871,"
line.long 0x5BC "smmu_ssd_reg_496,SSD Register 496"
hexmask.long 0x5BC 0.--31. 1. "ssd_index_15872_15903,"
line.long 0x5C0 "smmu_ssd_reg_497,SSD Register 497"
hexmask.long 0x5C0 0.--31. 1. "ssd_index_15904_15935,"
line.long 0x5C4 "smmu_ssd_reg_498,SSD Register 498"
hexmask.long 0x5C4 0.--31. 1. "ssd_index_15936_15967,"
line.long 0x5C8 "smmu_ssd_reg_499,SSD Register 499"
hexmask.long 0x5C8 0.--31. 1. "ssd_index_15968_15999,"
line.long 0x5CC "smmu_ssd_reg_500,SSD Register 500"
hexmask.long 0x5CC 0.--31. 1. "ssd_index_16000_16031,"
line.long 0x5D0 "smmu_ssd_reg_501,SSD Register 501"
hexmask.long 0x5D0 0.--31. 1. "ssd_index_16032_16063,"
line.long 0x5D4 "smmu_ssd_reg_502,SSD Register 502"
hexmask.long 0x5D4 0.--31. 1. "ssd_index_16064_16095,"
line.long 0x5D8 "smmu_ssd_reg_503,SSD Register 503"
hexmask.long 0x5D8 0.--31. 1. "ssd_index_16096_16127,"
line.long 0x5DC "smmu_ssd_reg_504,SSD Register 504"
hexmask.long 0x5DC 0.--31. 1. "ssd_index_16128_16159,"
line.long 0x5E0 "smmu_ssd_reg_505,SSD Register 505"
hexmask.long 0x5E0 0.--31. 1. "ssd_index_16160_16191,"
line.long 0x5E4 "smmu_ssd_reg_506,SSD Register 506"
hexmask.long 0x5E4 0.--31. 1. "ssd_index_16192_16223,"
line.long 0x5E8 "smmu_ssd_reg_507,SSD Register 507"
hexmask.long 0x5E8 0.--31. 1. "ssd_index_16224_16255,"
line.long 0x5EC "smmu_ssd_reg_508,SSD Register 508"
hexmask.long 0x5EC 0.--31. 1. "ssd_index_16256_16287,"
line.long 0x5F0 "smmu_ssd_reg_509,SSD Register 509"
hexmask.long 0x5F0 0.--31. 1. "ssd_index_16288_16319,"
line.long 0x5F4 "smmu_ssd_reg_510,SSD Register 510"
hexmask.long 0x5F4 0.--31. 1. "ssd_index_16320_16351,"
line.long 0x5F8 "smmu_ssd_reg_511,SSD Register 511"
hexmask.long 0x5F8 0.--31. 1. "ssd_index_16352_16383,"
line.long 0x5FC "smmu_ssd_reg_512,SSD Register 512"
hexmask.long 0x5FC 0.--31. 1. "ssd_index_16384_16415,"
line.long 0x600 "smmu_ssd_reg_513,SSD Register 513"
hexmask.long 0x600 0.--31. 1. "ssd_index_16416_16447,"
line.long 0x604 "smmu_ssd_reg_514,SSD Register 514"
hexmask.long 0x604 0.--31. 1. "ssd_index_16448_16479,"
line.long 0x608 "smmu_ssd_reg_515,SSD Register 515"
hexmask.long 0x608 0.--31. 1. "ssd_index_16480_16511,"
line.long 0x60C "smmu_ssd_reg_516,SSD Register 516"
hexmask.long 0x60C 0.--31. 1. "ssd_index_16512_16543,"
line.long 0x610 "smmu_ssd_reg_517,SSD Register 517"
hexmask.long 0x610 0.--31. 1. "ssd_index_16544_16575,"
line.long 0x614 "smmu_ssd_reg_518,SSD Register 518"
hexmask.long 0x614 0.--31. 1. "ssd_index_16576_16607,"
line.long 0x618 "smmu_ssd_reg_519,SSD Register 519"
hexmask.long 0x618 0.--31. 1. "ssd_index_16608_16639,"
line.long 0x61C "smmu_ssd_reg_520,SSD Register 520"
hexmask.long 0x61C 0.--31. 1. "ssd_index_16640_16671,"
line.long 0x620 "smmu_ssd_reg_521,SSD Register 521"
hexmask.long 0x620 0.--31. 1. "ssd_index_16672_16703,"
line.long 0x624 "smmu_ssd_reg_522,SSD Register 522"
hexmask.long 0x624 0.--31. 1. "ssd_index_16704_16735,"
line.long 0x628 "smmu_ssd_reg_523,SSD Register 523"
hexmask.long 0x628 0.--31. 1. "ssd_index_16736_16767,"
line.long 0x62C "smmu_ssd_reg_524,SSD Register 524"
hexmask.long 0x62C 0.--31. 1. "ssd_index_16768_16799,"
line.long 0x630 "smmu_ssd_reg_525,SSD Register 525"
hexmask.long 0x630 0.--31. 1. "ssd_index_16800_16831,"
line.long 0x634 "smmu_ssd_reg_526,SSD Register 526"
hexmask.long 0x634 0.--31. 1. "ssd_index_16832_16863,"
line.long 0x638 "smmu_ssd_reg_527,SSD Register 527"
hexmask.long 0x638 0.--31. 1. "ssd_index_16864_16895,"
line.long 0x63C "smmu_ssd_reg_528,SSD Register 528"
hexmask.long 0x63C 0.--31. 1. "ssd_index_16896_16927,"
line.long 0x640 "smmu_ssd_reg_529,SSD Register 529"
hexmask.long 0x640 0.--31. 1. "ssd_index_16928_16959,"
line.long 0x644 "smmu_ssd_reg_530,SSD Register 530"
hexmask.long 0x644 0.--31. 1. "ssd_index_16960_16991,"
line.long 0x648 "smmu_ssd_reg_531,SSD Register 531"
hexmask.long 0x648 0.--31. 1. "ssd_index_16992_17023,"
line.long 0x64C "smmu_ssd_reg_532,SSD Register 532"
hexmask.long 0x64C 0.--31. 1. "ssd_index_17024_17055,"
line.long 0x650 "smmu_ssd_reg_533,SSD Register 533"
hexmask.long 0x650 0.--31. 1. "ssd_index_17056_17087,"
line.long 0x654 "smmu_ssd_reg_534,SSD Register 534"
hexmask.long 0x654 0.--31. 1. "ssd_index_17088_17119,"
line.long 0x658 "smmu_ssd_reg_535,SSD Register 535"
hexmask.long 0x658 0.--31. 1. "ssd_index_17120_17151,"
line.long 0x65C "smmu_ssd_reg_536,SSD Register 536"
hexmask.long 0x65C 0.--31. 1. "ssd_index_17152_17183,"
line.long 0x660 "smmu_ssd_reg_537,SSD Register 537"
hexmask.long 0x660 0.--31. 1. "ssd_index_17184_17215,"
line.long 0x664 "smmu_ssd_reg_538,SSD Register 538"
hexmask.long 0x664 0.--31. 1. "ssd_index_17216_17247,"
line.long 0x668 "smmu_ssd_reg_539,SSD Register 539"
hexmask.long 0x668 0.--31. 1. "ssd_index_17248_17279,"
line.long 0x66C "smmu_ssd_reg_540,SSD Register 540"
hexmask.long 0x66C 0.--31. 1. "ssd_index_17280_17311,"
line.long 0x670 "smmu_ssd_reg_541,SSD Register 541"
hexmask.long 0x670 0.--31. 1. "ssd_index_17312_17343,"
line.long 0x674 "smmu_ssd_reg_542,SSD Register 542"
hexmask.long 0x674 0.--31. 1. "ssd_index_17344_17375,"
line.long 0x678 "smmu_ssd_reg_543,SSD Register 543"
hexmask.long 0x678 0.--31. 1. "ssd_index_17376_17407,"
line.long 0x67C "smmu_ssd_reg_544,SSD Register 544"
hexmask.long 0x67C 0.--31. 1. "ssd_index_17408_17439,"
line.long 0x680 "smmu_ssd_reg_545,SSD Register 545"
hexmask.long 0x680 0.--31. 1. "ssd_index_17440_17471,"
line.long 0x684 "smmu_ssd_reg_546,SSD Register 546"
hexmask.long 0x684 0.--31. 1. "ssd_index_17472_17503,"
line.long 0x688 "smmu_ssd_reg_547,SSD Register 547"
hexmask.long 0x688 0.--31. 1. "ssd_index_17504_17535,"
line.long 0x68C "smmu_ssd_reg_548,SSD Register 548"
hexmask.long 0x68C 0.--31. 1. "ssd_index_17536_17567,"
line.long 0x690 "smmu_ssd_reg_549,SSD Register 549"
hexmask.long 0x690 0.--31. 1. "ssd_index_17568_17599,"
line.long 0x694 "smmu_ssd_reg_550,SSD Register 550"
hexmask.long 0x694 0.--31. 1. "ssd_index_17600_17631,"
line.long 0x698 "smmu_ssd_reg_551,SSD Register 551"
hexmask.long 0x698 0.--31. 1. "ssd_index_17632_17663,"
line.long 0x69C "smmu_ssd_reg_552,SSD Register 552"
hexmask.long 0x69C 0.--31. 1. "ssd_index_17664_17695,"
line.long 0x6A0 "smmu_ssd_reg_553,SSD Register 553"
hexmask.long 0x6A0 0.--31. 1. "ssd_index_17696_17727,"
line.long 0x6A4 "smmu_ssd_reg_554,SSD Register 554"
hexmask.long 0x6A4 0.--31. 1. "ssd_index_17728_17759,"
line.long 0x6A8 "smmu_ssd_reg_555,SSD Register 555"
hexmask.long 0x6A8 0.--31. 1. "ssd_index_17760_17791,"
line.long 0x6AC "smmu_ssd_reg_556,SSD Register 556"
hexmask.long 0x6AC 0.--31. 1. "ssd_index_17792_17823,"
line.long 0x6B0 "smmu_ssd_reg_557,SSD Register 557"
hexmask.long 0x6B0 0.--31. 1. "ssd_index_17824_17855,"
line.long 0x6B4 "smmu_ssd_reg_558,SSD Register 558"
hexmask.long 0x6B4 0.--31. 1. "ssd_index_17856_17887,"
line.long 0x6B8 "smmu_ssd_reg_559,SSD Register 559"
hexmask.long 0x6B8 0.--31. 1. "ssd_index_17888_17919,"
line.long 0x6BC "smmu_ssd_reg_560,SSD Register 560"
hexmask.long 0x6BC 0.--31. 1. "ssd_index_17920_17951,"
line.long 0x6C0 "smmu_ssd_reg_561,SSD Register 561"
hexmask.long 0x6C0 0.--31. 1. "ssd_index_17952_17983,"
line.long 0x6C4 "smmu_ssd_reg_562,SSD Register 562"
hexmask.long 0x6C4 0.--31. 1. "ssd_index_17984_18015,"
line.long 0x6C8 "smmu_ssd_reg_563,SSD Register 563"
hexmask.long 0x6C8 0.--31. 1. "ssd_index_18016_18047,"
line.long 0x6CC "smmu_ssd_reg_564,SSD Register 564"
hexmask.long 0x6CC 0.--31. 1. "ssd_index_18048_18079,"
line.long 0x6D0 "smmu_ssd_reg_565,SSD Register 565"
hexmask.long 0x6D0 0.--31. 1. "ssd_index_18080_18111,"
line.long 0x6D4 "smmu_ssd_reg_566,SSD Register 566"
hexmask.long 0x6D4 0.--31. 1. "ssd_index_18112_18143,"
line.long 0x6D8 "smmu_ssd_reg_567,SSD Register 567"
hexmask.long 0x6D8 0.--31. 1. "ssd_index_18144_18175,"
line.long 0x6DC "smmu_ssd_reg_568,SSD Register 568"
hexmask.long 0x6DC 0.--31. 1. "ssd_index_18176_18207,"
line.long 0x6E0 "smmu_ssd_reg_569,SSD Register 569"
hexmask.long 0x6E0 0.--31. 1. "ssd_index_18208_18239,"
line.long 0x6E4 "smmu_ssd_reg_570,SSD Register 570"
hexmask.long 0x6E4 0.--31. 1. "ssd_index_18240_18271,"
line.long 0x6E8 "smmu_ssd_reg_571,SSD Register 571"
hexmask.long 0x6E8 0.--31. 1. "ssd_index_18272_18303,"
line.long 0x6EC "smmu_ssd_reg_572,SSD Register 572"
hexmask.long 0x6EC 0.--31. 1. "ssd_index_18304_18335,"
line.long 0x6F0 "smmu_ssd_reg_573,SSD Register 573"
hexmask.long 0x6F0 0.--31. 1. "ssd_index_18336_18367,"
line.long 0x6F4 "smmu_ssd_reg_574,SSD Register 574"
hexmask.long 0x6F4 0.--31. 1. "ssd_index_18368_18399,"
line.long 0x6F8 "smmu_ssd_reg_575,SSD Register 575"
hexmask.long 0x6F8 0.--31. 1. "ssd_index_18400_18431,"
line.long 0x6FC "smmu_ssd_reg_576,SSD Register 576"
hexmask.long 0x6FC 0.--31. 1. "ssd_index_18432_18463,"
line.long 0x700 "smmu_ssd_reg_577,SSD Register 577"
hexmask.long 0x700 0.--31. 1. "ssd_index_18464_18495,"
line.long 0x704 "smmu_ssd_reg_578,SSD Register 578"
hexmask.long 0x704 0.--31. 1. "ssd_index_18496_18527,"
line.long 0x708 "smmu_ssd_reg_579,SSD Register 579"
hexmask.long 0x708 0.--31. 1. "ssd_index_18528_18559,"
line.long 0x70C "smmu_ssd_reg_580,SSD Register 580"
hexmask.long 0x70C 0.--31. 1. "ssd_index_18560_18591,"
line.long 0x710 "smmu_ssd_reg_581,SSD Register 581"
hexmask.long 0x710 0.--31. 1. "ssd_index_18592_18623,"
line.long 0x714 "smmu_ssd_reg_582,SSD Register 582"
hexmask.long 0x714 0.--31. 1. "ssd_index_18624_18655,"
line.long 0x718 "smmu_ssd_reg_583,SSD Register 583"
hexmask.long 0x718 0.--31. 1. "ssd_index_18656_18687,"
line.long 0x71C "smmu_ssd_reg_584,SSD Register 584"
hexmask.long 0x71C 0.--31. 1. "ssd_index_18688_18719,"
line.long 0x720 "smmu_ssd_reg_585,SSD Register 585"
hexmask.long 0x720 0.--31. 1. "ssd_index_18720_18751,"
line.long 0x724 "smmu_ssd_reg_586,SSD Register 586"
hexmask.long 0x724 0.--31. 1. "ssd_index_18752_18783,"
line.long 0x728 "smmu_ssd_reg_587,SSD Register 587"
hexmask.long 0x728 0.--31. 1. "ssd_index_18784_18815,"
line.long 0x72C "smmu_ssd_reg_588,SSD Register 588"
hexmask.long 0x72C 0.--31. 1. "ssd_index_18816_18847,"
line.long 0x730 "smmu_ssd_reg_589,SSD Register 589"
hexmask.long 0x730 0.--31. 1. "ssd_index_18848_18879,"
line.long 0x734 "smmu_ssd_reg_590,SSD Register 590"
hexmask.long 0x734 0.--31. 1. "ssd_index_18880_18911,"
line.long 0x738 "smmu_ssd_reg_591,SSD Register 591"
hexmask.long 0x738 0.--31. 1. "ssd_index_18912_18943,"
line.long 0x73C "smmu_ssd_reg_592,SSD Register 592"
hexmask.long 0x73C 0.--31. 1. "ssd_index_18944_18975,"
line.long 0x740 "smmu_ssd_reg_593,SSD Register 593"
hexmask.long 0x740 0.--31. 1. "ssd_index_18976_19007,"
line.long 0x744 "smmu_ssd_reg_594,SSD Register 594"
hexmask.long 0x744 0.--31. 1. "ssd_index_19008_19039,"
line.long 0x748 "smmu_ssd_reg_595,SSD Register 595"
hexmask.long 0x748 0.--31. 1. "ssd_index_19040_19071,"
line.long 0x74C "smmu_ssd_reg_596,SSD Register 596"
hexmask.long 0x74C 0.--31. 1. "ssd_index_19072_19103,"
line.long 0x750 "smmu_ssd_reg_597,SSD Register 597"
hexmask.long 0x750 0.--31. 1. "ssd_index_19104_19135,"
line.long 0x754 "smmu_ssd_reg_598,SSD Register 598"
hexmask.long 0x754 0.--31. 1. "ssd_index_19136_19167,"
line.long 0x758 "smmu_ssd_reg_599,SSD Register 599"
hexmask.long 0x758 0.--31. 1. "ssd_index_19168_19199,"
line.long 0x75C "smmu_ssd_reg_600,SSD Register 600"
hexmask.long 0x75C 0.--31. 1. "ssd_index_19200_19231,"
line.long 0x760 "smmu_ssd_reg_601,SSD Register 601"
hexmask.long 0x760 0.--31. 1. "ssd_index_19232_19263,"
line.long 0x764 "smmu_ssd_reg_602,SSD Register 602"
hexmask.long 0x764 0.--31. 1. "ssd_index_19264_19295,"
line.long 0x768 "smmu_ssd_reg_603,SSD Register 603"
hexmask.long 0x768 0.--31. 1. "ssd_index_19296_19327,"
line.long 0x76C "smmu_ssd_reg_604,SSD Register 604"
hexmask.long 0x76C 0.--31. 1. "ssd_index_19328_19359,"
line.long 0x770 "smmu_ssd_reg_605,SSD Register 605"
hexmask.long 0x770 0.--31. 1. "ssd_index_19360_19391,"
line.long 0x774 "smmu_ssd_reg_606,SSD Register 606"
hexmask.long 0x774 0.--31. 1. "ssd_index_19392_19423,"
line.long 0x778 "smmu_ssd_reg_607,SSD Register 607"
hexmask.long 0x778 0.--31. 1. "ssd_index_19424_19455,"
line.long 0x77C "smmu_ssd_reg_608,SSD Register 608"
hexmask.long 0x77C 0.--31. 1. "ssd_index_19456_19487,"
line.long 0x780 "smmu_ssd_reg_609,SSD Register 609"
hexmask.long 0x780 0.--31. 1. "ssd_index_19488_19519,"
line.long 0x784 "smmu_ssd_reg_610,SSD Register 610"
hexmask.long 0x784 0.--31. 1. "ssd_index_19520_19551,"
line.long 0x788 "smmu_ssd_reg_611,SSD Register 611"
hexmask.long 0x788 0.--31. 1. "ssd_index_19552_19583,"
line.long 0x78C "smmu_ssd_reg_612,SSD Register 612"
hexmask.long 0x78C 0.--31. 1. "ssd_index_19584_19615,"
line.long 0x790 "smmu_ssd_reg_613,SSD Register 613"
hexmask.long 0x790 0.--31. 1. "ssd_index_19616_19647,"
line.long 0x794 "smmu_ssd_reg_614,SSD Register 614"
hexmask.long 0x794 0.--31. 1. "ssd_index_19648_19679,"
line.long 0x798 "smmu_ssd_reg_615,SSD Register 615"
hexmask.long 0x798 0.--31. 1. "ssd_index_19680_19711,"
line.long 0x79C "smmu_ssd_reg_616,SSD Register 616"
hexmask.long 0x79C 0.--31. 1. "ssd_index_19712_19743,"
line.long 0x7A0 "smmu_ssd_reg_617,SSD Register 617"
hexmask.long 0x7A0 0.--31. 1. "ssd_index_19744_19775,"
line.long 0x7A4 "smmu_ssd_reg_618,SSD Register 618"
hexmask.long 0x7A4 0.--31. 1. "ssd_index_19776_19807,"
line.long 0x7A8 "smmu_ssd_reg_619,SSD Register 619"
hexmask.long 0x7A8 0.--31. 1. "ssd_index_19808_19839,"
line.long 0x7AC "smmu_ssd_reg_620,SSD Register 620"
hexmask.long 0x7AC 0.--31. 1. "ssd_index_19840_19871,"
line.long 0x7B0 "smmu_ssd_reg_621,SSD Register 621"
hexmask.long 0x7B0 0.--31. 1. "ssd_index_19872_19903,"
line.long 0x7B4 "smmu_ssd_reg_622,SSD Register 622"
hexmask.long 0x7B4 0.--31. 1. "ssd_index_19904_19935,"
line.long 0x7B8 "smmu_ssd_reg_623,SSD Register 623"
hexmask.long 0x7B8 0.--31. 1. "ssd_index_19936_19967,"
line.long 0x7BC "smmu_ssd_reg_624,SSD Register 624"
hexmask.long 0x7BC 0.--31. 1. "ssd_index_19968_19999,"
line.long 0x7C0 "smmu_ssd_reg_625,SSD Register 625"
hexmask.long 0x7C0 0.--31. 1. "ssd_index_20000_20031,"
line.long 0x7C4 "smmu_ssd_reg_626,SSD Register 626"
hexmask.long 0x7C4 0.--31. 1. "ssd_index_20032_20063,"
line.long 0x7C8 "smmu_ssd_reg_627,SSD Register 627"
hexmask.long 0x7C8 0.--31. 1. "ssd_index_20064_20095,"
line.long 0x7CC "smmu_ssd_reg_628,SSD Register 628"
hexmask.long 0x7CC 0.--31. 1. "ssd_index_20096_20127,"
line.long 0x7D0 "smmu_ssd_reg_629,SSD Register 629"
hexmask.long 0x7D0 0.--31. 1. "ssd_index_20128_20159,"
line.long 0x7D4 "smmu_ssd_reg_630,SSD Register 630"
hexmask.long 0x7D4 0.--31. 1. "ssd_index_20160_20191,"
line.long 0x7D8 "smmu_ssd_reg_631,SSD Register 631"
hexmask.long 0x7D8 0.--31. 1. "ssd_index_20192_20223,"
line.long 0x7DC "smmu_ssd_reg_632,SSD Register 632"
hexmask.long 0x7DC 0.--31. 1. "ssd_index_20224_20255,"
line.long 0x7E0 "smmu_ssd_reg_633,SSD Register 633"
hexmask.long 0x7E0 0.--31. 1. "ssd_index_20256_20287,"
line.long 0x7E4 "smmu_ssd_reg_634,SSD Register 634"
hexmask.long 0x7E4 0.--31. 1. "ssd_index_20288_20319,"
line.long 0x7E8 "smmu_ssd_reg_635,SSD Register 635"
hexmask.long 0x7E8 0.--31. 1. "ssd_index_20320_20351,"
line.long 0x7EC "smmu_ssd_reg_636,SSD Register 636"
hexmask.long 0x7EC 0.--31. 1. "ssd_index_20352_20383,"
line.long 0x7F0 "smmu_ssd_reg_637,SSD Register 637"
hexmask.long 0x7F0 0.--31. 1. "ssd_index_20384_20415,"
line.long 0x7F4 "smmu_ssd_reg_638,SSD Register 638"
hexmask.long 0x7F4 0.--31. 1. "ssd_index_20416_20447,"
line.long 0x7F8 "smmu_ssd_reg_639,SSD Register 639"
hexmask.long 0x7F8 0.--31. 1. "ssd_index_20448_20479,"
line.long 0x7FC "smmu_ssd_reg_640,SSD Register 640"
hexmask.long 0x7FC 0.--31. 1. "ssd_index_20480_20511,"
line.long 0x800 "smmu_ssd_reg_641,SSD Register 641"
hexmask.long 0x800 0.--31. 1. "ssd_index_20512_20543,"
line.long 0x804 "smmu_ssd_reg_642,SSD Register 642"
hexmask.long 0x804 0.--31. 1. "ssd_index_20544_20575,"
line.long 0x808 "smmu_ssd_reg_643,SSD Register 643"
hexmask.long 0x808 0.--31. 1. "ssd_index_20576_20607,"
line.long 0x80C "smmu_ssd_reg_644,SSD Register 644"
hexmask.long 0x80C 0.--31. 1. "ssd_index_20608_20639,"
line.long 0x810 "smmu_ssd_reg_645,SSD Register 645"
hexmask.long 0x810 0.--31. 1. "ssd_index_20640_20671,"
line.long 0x814 "smmu_ssd_reg_646,SSD Register 646"
hexmask.long 0x814 0.--31. 1. "ssd_index_20672_20703,"
line.long 0x818 "smmu_ssd_reg_647,SSD Register 647"
hexmask.long 0x818 0.--31. 1. "ssd_index_20704_20735,"
line.long 0x81C "smmu_ssd_reg_648,SSD Register 648"
hexmask.long 0x81C 0.--31. 1. "ssd_index_20736_20767,"
line.long 0x820 "smmu_ssd_reg_649,SSD Register 649"
hexmask.long 0x820 0.--31. 1. "ssd_index_20768_20799,"
line.long 0x824 "smmu_ssd_reg_650,SSD Register 650"
hexmask.long 0x824 0.--31. 1. "ssd_index_20800_20831,"
line.long 0x828 "smmu_ssd_reg_651,SSD Register 651"
hexmask.long 0x828 0.--31. 1. "ssd_index_20832_20863,"
line.long 0x82C "smmu_ssd_reg_652,SSD Register 652"
hexmask.long 0x82C 0.--31. 1. "ssd_index_20864_20895,"
line.long 0x830 "smmu_ssd_reg_653,SSD Register 653"
hexmask.long 0x830 0.--31. 1. "ssd_index_20896_20927,"
line.long 0x834 "smmu_ssd_reg_654,SSD Register 654"
hexmask.long 0x834 0.--31. 1. "ssd_index_20928_20959,"
line.long 0x838 "smmu_ssd_reg_655,SSD Register 655"
hexmask.long 0x838 0.--31. 1. "ssd_index_20960_20991,"
line.long 0x83C "smmu_ssd_reg_656,SSD Register 656"
hexmask.long 0x83C 0.--31. 1. "ssd_index_20992_21023,"
line.long 0x840 "smmu_ssd_reg_657,SSD Register 657"
hexmask.long 0x840 0.--31. 1. "ssd_index_21024_21055,"
line.long 0x844 "smmu_ssd_reg_658,SSD Register 658"
hexmask.long 0x844 0.--31. 1. "ssd_index_21056_21087,"
line.long 0x848 "smmu_ssd_reg_659,SSD Register 659"
hexmask.long 0x848 0.--31. 1. "ssd_index_21088_21119,"
line.long 0x84C "smmu_ssd_reg_660,SSD Register 660"
hexmask.long 0x84C 0.--31. 1. "ssd_index_21120_21151,"
line.long 0x850 "smmu_ssd_reg_661,SSD Register 661"
hexmask.long 0x850 0.--31. 1. "ssd_index_21152_21183,"
line.long 0x854 "smmu_ssd_reg_662,SSD Register 662"
hexmask.long 0x854 0.--31. 1. "ssd_index_21184_21215,"
line.long 0x858 "smmu_ssd_reg_663,SSD Register 663"
hexmask.long 0x858 0.--31. 1. "ssd_index_21216_21247,"
line.long 0x85C "smmu_ssd_reg_664,SSD Register 664"
hexmask.long 0x85C 0.--31. 1. "ssd_index_21248_21279,"
line.long 0x860 "smmu_ssd_reg_665,SSD Register 665"
hexmask.long 0x860 0.--31. 1. "ssd_index_21280_21311,"
line.long 0x864 "smmu_ssd_reg_666,SSD Register 666"
hexmask.long 0x864 0.--31. 1. "ssd_index_21312_21343,"
line.long 0x868 "smmu_ssd_reg_667,SSD Register 667"
hexmask.long 0x868 0.--31. 1. "ssd_index_21344_21375,"
line.long 0x86C "smmu_ssd_reg_668,SSD Register 668"
hexmask.long 0x86C 0.--31. 1. "ssd_index_21376_21407,"
line.long 0x870 "smmu_ssd_reg_669,SSD Register 669"
hexmask.long 0x870 0.--31. 1. "ssd_index_21408_21439,"
line.long 0x874 "smmu_ssd_reg_670,SSD Register 670"
hexmask.long 0x874 0.--31. 1. "ssd_index_21440_21471,"
line.long 0x878 "smmu_ssd_reg_671,SSD Register 671"
hexmask.long 0x878 0.--31. 1. "ssd_index_21472_21503,"
line.long 0x87C "smmu_ssd_reg_672,SSD Register 672"
hexmask.long 0x87C 0.--31. 1. "ssd_index_21504_21535,"
line.long 0x880 "smmu_ssd_reg_673,SSD Register 673"
hexmask.long 0x880 0.--31. 1. "ssd_index_21536_21567,"
line.long 0x884 "smmu_ssd_reg_674,SSD Register 674"
hexmask.long 0x884 0.--31. 1. "ssd_index_21568_21599,"
line.long 0x888 "smmu_ssd_reg_675,SSD Register 675"
hexmask.long 0x888 0.--31. 1. "ssd_index_21600_21631,"
line.long 0x88C "smmu_ssd_reg_676,SSD Register 676"
hexmask.long 0x88C 0.--31. 1. "ssd_index_21632_21663,"
line.long 0x890 "smmu_ssd_reg_677,SSD Register 677"
hexmask.long 0x890 0.--31. 1. "ssd_index_21664_21695,"
line.long 0x894 "smmu_ssd_reg_678,SSD Register 678"
hexmask.long 0x894 0.--31. 1. "ssd_index_21696_21727,"
line.long 0x898 "smmu_ssd_reg_679,SSD Register 679"
hexmask.long 0x898 0.--31. 1. "ssd_index_21728_21759,"
line.long 0x89C "smmu_ssd_reg_680,SSD Register 680"
hexmask.long 0x89C 0.--31. 1. "ssd_index_21760_21791,"
line.long 0x8A0 "smmu_ssd_reg_681,SSD Register 681"
hexmask.long 0x8A0 0.--31. 1. "ssd_index_21792_21823,"
line.long 0x8A4 "smmu_ssd_reg_682,SSD Register 682"
hexmask.long 0x8A4 0.--31. 1. "ssd_index_21824_21855,"
line.long 0x8A8 "smmu_ssd_reg_683,SSD Register 683"
hexmask.long 0x8A8 0.--31. 1. "ssd_index_21856_21887,"
line.long 0x8AC "smmu_ssd_reg_684,SSD Register 684"
hexmask.long 0x8AC 0.--31. 1. "ssd_index_21888_21919,"
line.long 0x8B0 "smmu_ssd_reg_685,SSD Register 685"
hexmask.long 0x8B0 0.--31. 1. "ssd_index_21920_21951,"
line.long 0x8B4 "smmu_ssd_reg_686,SSD Register 686"
hexmask.long 0x8B4 0.--31. 1. "ssd_index_21952_21983,"
line.long 0x8B8 "smmu_ssd_reg_687,SSD Register 687"
hexmask.long 0x8B8 0.--31. 1. "ssd_index_21984_22015,"
line.long 0x8BC "smmu_ssd_reg_688,SSD Register 688"
hexmask.long 0x8BC 0.--31. 1. "ssd_index_22016_22047,"
line.long 0x8C0 "smmu_ssd_reg_689,SSD Register 689"
hexmask.long 0x8C0 0.--31. 1. "ssd_index_22048_22079,"
line.long 0x8C4 "smmu_ssd_reg_690,SSD Register 690"
hexmask.long 0x8C4 0.--31. 1. "ssd_index_22080_22111,"
line.long 0x8C8 "smmu_ssd_reg_691,SSD Register 691"
hexmask.long 0x8C8 0.--31. 1. "ssd_index_22112_22143,"
line.long 0x8CC "smmu_ssd_reg_692,SSD Register 692"
hexmask.long 0x8CC 0.--31. 1. "ssd_index_22144_22175,"
line.long 0x8D0 "smmu_ssd_reg_693,SSD Register 693"
hexmask.long 0x8D0 0.--31. 1. "ssd_index_22176_22207,"
line.long 0x8D4 "smmu_ssd_reg_694,SSD Register 694"
hexmask.long 0x8D4 0.--31. 1. "ssd_index_22208_22239,"
line.long 0x8D8 "smmu_ssd_reg_695,SSD Register 695"
hexmask.long 0x8D8 0.--31. 1. "ssd_index_22240_22271,"
line.long 0x8DC "smmu_ssd_reg_696,SSD Register 696"
hexmask.long 0x8DC 0.--31. 1. "ssd_index_22272_22303,"
line.long 0x8E0 "smmu_ssd_reg_697,SSD Register 697"
hexmask.long 0x8E0 0.--31. 1. "ssd_index_22304_22335,"
line.long 0x8E4 "smmu_ssd_reg_698,SSD Register 698"
hexmask.long 0x8E4 0.--31. 1. "ssd_index_22336_22367,"
line.long 0x8E8 "smmu_ssd_reg_699,SSD Register 699"
hexmask.long 0x8E8 0.--31. 1. "ssd_index_22368_22399,"
line.long 0x8EC "smmu_ssd_reg_700,SSD Register 700"
hexmask.long 0x8EC 0.--31. 1. "ssd_index_22400_22431,"
line.long 0x8F0 "smmu_ssd_reg_701,SSD Register 701"
hexmask.long 0x8F0 0.--31. 1. "ssd_index_22432_22463,"
line.long 0x8F4 "smmu_ssd_reg_702,SSD Register 702"
hexmask.long 0x8F4 0.--31. 1. "ssd_index_22464_22495,"
line.long 0x8F8 "smmu_ssd_reg_703,SSD Register 703"
hexmask.long 0x8F8 0.--31. 1. "ssd_index_22496_22527,"
line.long 0x8FC "smmu_ssd_reg_704,SSD Register 704"
hexmask.long 0x8FC 0.--31. 1. "ssd_index_22528_22559,"
line.long 0x900 "smmu_ssd_reg_705,SSD Register 705"
hexmask.long 0x900 0.--31. 1. "ssd_index_22560_22591,"
line.long 0x904 "smmu_ssd_reg_706,SSD Register 706"
hexmask.long 0x904 0.--31. 1. "ssd_index_22592_22623,"
line.long 0x908 "smmu_ssd_reg_707,SSD Register 707"
hexmask.long 0x908 0.--31. 1. "ssd_index_22624_22655,"
line.long 0x90C "smmu_ssd_reg_708,SSD Register 708"
hexmask.long 0x90C 0.--31. 1. "ssd_index_22656_22687,"
line.long 0x910 "smmu_ssd_reg_709,SSD Register 709"
hexmask.long 0x910 0.--31. 1. "ssd_index_22688_22719,"
line.long 0x914 "smmu_ssd_reg_710,SSD Register 710"
hexmask.long 0x914 0.--31. 1. "ssd_index_22720_22751,"
line.long 0x918 "smmu_ssd_reg_711,SSD Register 711"
hexmask.long 0x918 0.--31. 1. "ssd_index_22752_22783,"
line.long 0x91C "smmu_ssd_reg_712,SSD Register 712"
hexmask.long 0x91C 0.--31. 1. "ssd_index_22784_22815,"
line.long 0x920 "smmu_ssd_reg_713,SSD Register 713"
hexmask.long 0x920 0.--31. 1. "ssd_index_22816_22847,"
line.long 0x924 "smmu_ssd_reg_714,SSD Register 714"
hexmask.long 0x924 0.--31. 1. "ssd_index_22848_22879,"
line.long 0x928 "smmu_ssd_reg_715,SSD Register 715"
hexmask.long 0x928 0.--31. 1. "ssd_index_22880_22911,"
line.long 0x92C "smmu_ssd_reg_716,SSD Register 716"
hexmask.long 0x92C 0.--31. 1. "ssd_index_22912_22943,"
line.long 0x930 "smmu_ssd_reg_717,SSD Register 717"
hexmask.long 0x930 0.--31. 1. "ssd_index_22944_22975,"
line.long 0x934 "smmu_ssd_reg_718,SSD Register 718"
hexmask.long 0x934 0.--31. 1. "ssd_index_22976_23007,"
line.long 0x938 "smmu_ssd_reg_719,SSD Register 719"
hexmask.long 0x938 0.--31. 1. "ssd_index_23008_23039,"
line.long 0x93C "smmu_ssd_reg_720,SSD Register 720"
hexmask.long 0x93C 0.--31. 1. "ssd_index_23040_23071,"
line.long 0x940 "smmu_ssd_reg_721,SSD Register 721"
hexmask.long 0x940 0.--31. 1. "ssd_index_23072_23103,"
line.long 0x944 "smmu_ssd_reg_722,SSD Register 722"
hexmask.long 0x944 0.--31. 1. "ssd_index_23104_23135,"
line.long 0x948 "smmu_ssd_reg_723,SSD Register 723"
hexmask.long 0x948 0.--31. 1. "ssd_index_23136_23167,"
line.long 0x94C "smmu_ssd_reg_724,SSD Register 724"
hexmask.long 0x94C 0.--31. 1. "ssd_index_23168_23199,"
line.long 0x950 "smmu_ssd_reg_725,SSD Register 725"
hexmask.long 0x950 0.--31. 1. "ssd_index_23200_23231,"
line.long 0x954 "smmu_ssd_reg_726,SSD Register 726"
hexmask.long 0x954 0.--31. 1. "ssd_index_23232_23263,"
line.long 0x958 "smmu_ssd_reg_727,SSD Register 727"
hexmask.long 0x958 0.--31. 1. "ssd_index_23264_23295,"
line.long 0x95C "smmu_ssd_reg_728,SSD Register 728"
hexmask.long 0x95C 0.--31. 1. "ssd_index_23296_23327,"
line.long 0x960 "smmu_ssd_reg_729,SSD Register 729"
hexmask.long 0x960 0.--31. 1. "ssd_index_23328_23359,"
line.long 0x964 "smmu_ssd_reg_730,SSD Register 730"
hexmask.long 0x964 0.--31. 1. "ssd_index_23360_23391,"
line.long 0x968 "smmu_ssd_reg_731,SSD Register 731"
hexmask.long 0x968 0.--31. 1. "ssd_index_23392_23423,"
line.long 0x96C "smmu_ssd_reg_732,SSD Register 732"
hexmask.long 0x96C 0.--31. 1. "ssd_index_23424_23455,"
line.long 0x970 "smmu_ssd_reg_733,SSD Register 733"
hexmask.long 0x970 0.--31. 1. "ssd_index_23456_23487,"
line.long 0x974 "smmu_ssd_reg_734,SSD Register 734"
hexmask.long 0x974 0.--31. 1. "ssd_index_23488_23519,"
line.long 0x978 "smmu_ssd_reg_735,SSD Register 735"
hexmask.long 0x978 0.--31. 1. "ssd_index_23520_23551,"
line.long 0x97C "smmu_ssd_reg_736,SSD Register 736"
hexmask.long 0x97C 0.--31. 1. "ssd_index_23552_23583,"
line.long 0x980 "smmu_ssd_reg_737,SSD Register 737"
hexmask.long 0x980 0.--31. 1. "ssd_index_23584_23615,"
line.long 0x984 "smmu_ssd_reg_738,SSD Register 738"
hexmask.long 0x984 0.--31. 1. "ssd_index_23616_23647,"
line.long 0x988 "smmu_ssd_reg_739,SSD Register 739"
hexmask.long 0x988 0.--31. 1. "ssd_index_23648_23679,"
line.long 0x98C "smmu_ssd_reg_740,SSD Register 740"
hexmask.long 0x98C 0.--31. 1. "ssd_index_23680_23711,"
line.long 0x990 "smmu_ssd_reg_741,SSD Register 741"
hexmask.long 0x990 0.--31. 1. "ssd_index_23712_23743,"
line.long 0x994 "smmu_ssd_reg_742,SSD Register 742"
hexmask.long 0x994 0.--31. 1. "ssd_index_23744_23775,"
line.long 0x998 "smmu_ssd_reg_743,SSD Register 743"
hexmask.long 0x998 0.--31. 1. "ssd_index_23776_23807,"
line.long 0x99C "smmu_ssd_reg_744,SSD Register 744"
hexmask.long 0x99C 0.--31. 1. "ssd_index_23808_23839,"
line.long 0x9A0 "smmu_ssd_reg_745,SSD Register 745"
hexmask.long 0x9A0 0.--31. 1. "ssd_index_23840_23871,"
line.long 0x9A4 "smmu_ssd_reg_746,SSD Register 746"
hexmask.long 0x9A4 0.--31. 1. "ssd_index_23872_23903,"
line.long 0x9A8 "smmu_ssd_reg_747,SSD Register 747"
hexmask.long 0x9A8 0.--31. 1. "ssd_index_23904_23935,"
line.long 0x9AC "smmu_ssd_reg_748,SSD Register 748"
hexmask.long 0x9AC 0.--31. 1. "ssd_index_23936_23967,"
line.long 0x9B0 "smmu_ssd_reg_749,SSD Register 749"
hexmask.long 0x9B0 0.--31. 1. "ssd_index_23968_23999,"
line.long 0x9B4 "smmu_ssd_reg_750,SSD Register 750"
hexmask.long 0x9B4 0.--31. 1. "ssd_index_24000_24031,"
line.long 0x9B8 "smmu_ssd_reg_751,SSD Register 751"
hexmask.long 0x9B8 0.--31. 1. "ssd_index_24032_24063,"
line.long 0x9BC "smmu_ssd_reg_752,SSD Register 752"
hexmask.long 0x9BC 0.--31. 1. "ssd_index_24064_24095,"
line.long 0x9C0 "smmu_ssd_reg_753,SSD Register 753"
hexmask.long 0x9C0 0.--31. 1. "ssd_index_24096_24127,"
line.long 0x9C4 "smmu_ssd_reg_754,SSD Register 754"
hexmask.long 0x9C4 0.--31. 1. "ssd_index_24128_24159,"
line.long 0x9C8 "smmu_ssd_reg_755,SSD Register 755"
hexmask.long 0x9C8 0.--31. 1. "ssd_index_24160_24191,"
line.long 0x9CC "smmu_ssd_reg_756,SSD Register 756"
hexmask.long 0x9CC 0.--31. 1. "ssd_index_24192_24223,"
line.long 0x9D0 "smmu_ssd_reg_757,SSD Register 757"
hexmask.long 0x9D0 0.--31. 1. "ssd_index_24224_24255,"
line.long 0x9D4 "smmu_ssd_reg_758,SSD Register 758"
hexmask.long 0x9D4 0.--31. 1. "ssd_index_24256_24287,"
line.long 0x9D8 "smmu_ssd_reg_759,SSD Register 759"
hexmask.long 0x9D8 0.--31. 1. "ssd_index_24288_24319,"
line.long 0x9DC "smmu_ssd_reg_760,SSD Register 760"
hexmask.long 0x9DC 0.--31. 1. "ssd_index_24320_24351,"
line.long 0x9E0 "smmu_ssd_reg_761,SSD Register 761"
hexmask.long 0x9E0 0.--31. 1. "ssd_index_24352_24383,"
line.long 0x9E4 "smmu_ssd_reg_762,SSD Register 762"
hexmask.long 0x9E4 0.--31. 1. "ssd_index_24384_24415,"
line.long 0x9E8 "smmu_ssd_reg_763,SSD Register 763"
hexmask.long 0x9E8 0.--31. 1. "ssd_index_24416_24447,"
line.long 0x9EC "smmu_ssd_reg_764,SSD Register 764"
hexmask.long 0x9EC 0.--31. 1. "ssd_index_24448_24479,"
line.long 0x9F0 "smmu_ssd_reg_765,SSD Register 765"
hexmask.long 0x9F0 0.--31. 1. "ssd_index_24480_24511,"
line.long 0x9F4 "smmu_ssd_reg_766,SSD Register 766"
hexmask.long 0x9F4 0.--31. 1. "ssd_index_24512_24543,"
line.long 0x9F8 "smmu_ssd_reg_767,SSD Register 767"
hexmask.long 0x9F8 0.--31. 1. "ssd_index_24544_24575,"
line.long 0x9FC "smmu_ssd_reg_768,SSD Register 768"
hexmask.long 0x9FC 0.--31. 1. "ssd_index_24576_24607,"
line.long 0xA00 "smmu_ssd_reg_769,SSD Register 769"
hexmask.long 0xA00 0.--31. 1. "ssd_index_24608_24639,"
line.long 0xA04 "smmu_ssd_reg_770,SSD Register 770"
hexmask.long 0xA04 0.--31. 1. "ssd_index_24640_24671,"
line.long 0xA08 "smmu_ssd_reg_771,SSD Register 771"
hexmask.long 0xA08 0.--31. 1. "ssd_index_24672_24703,"
line.long 0xA0C "smmu_ssd_reg_772,SSD Register 772"
hexmask.long 0xA0C 0.--31. 1. "ssd_index_24704_24735,"
line.long 0xA10 "smmu_ssd_reg_773,SSD Register 773"
hexmask.long 0xA10 0.--31. 1. "ssd_index_24736_24767,"
line.long 0xA14 "smmu_ssd_reg_774,SSD Register 774"
hexmask.long 0xA14 0.--31. 1. "ssd_index_24768_24799,"
line.long 0xA18 "smmu_ssd_reg_775,SSD Register 775"
hexmask.long 0xA18 0.--31. 1. "ssd_index_24800_24831,"
line.long 0xA1C "smmu_ssd_reg_776,SSD Register 776"
hexmask.long 0xA1C 0.--31. 1. "ssd_index_24832_24863,"
line.long 0xA20 "smmu_ssd_reg_777,SSD Register 777"
hexmask.long 0xA20 0.--31. 1. "ssd_index_24864_24895,"
line.long 0xA24 "smmu_ssd_reg_778,SSD Register 778"
hexmask.long 0xA24 0.--31. 1. "ssd_index_24896_24927,"
line.long 0xA28 "smmu_ssd_reg_779,SSD Register 779"
hexmask.long 0xA28 0.--31. 1. "ssd_index_24928_24959,"
line.long 0xA2C "smmu_ssd_reg_780,SSD Register 780"
hexmask.long 0xA2C 0.--31. 1. "ssd_index_24960_24991,"
line.long 0xA30 "smmu_ssd_reg_781,SSD Register 781"
hexmask.long 0xA30 0.--31. 1. "ssd_index_24992_25023,"
line.long 0xA34 "smmu_ssd_reg_782,SSD Register 782"
hexmask.long 0xA34 0.--31. 1. "ssd_index_25024_25055,"
line.long 0xA38 "smmu_ssd_reg_783,SSD Register 783"
hexmask.long 0xA38 0.--31. 1. "ssd_index_25056_25087,"
line.long 0xA3C "smmu_ssd_reg_784,SSD Register 784"
hexmask.long 0xA3C 0.--31. 1. "ssd_index_25088_25119,"
line.long 0xA40 "smmu_ssd_reg_785,SSD Register 785"
hexmask.long 0xA40 0.--31. 1. "ssd_index_25120_25151,"
line.long 0xA44 "smmu_ssd_reg_786,SSD Register 786"
hexmask.long 0xA44 0.--31. 1. "ssd_index_25152_25183,"
line.long 0xA48 "smmu_ssd_reg_787,SSD Register 787"
hexmask.long 0xA48 0.--31. 1. "ssd_index_25184_25215,"
line.long 0xA4C "smmu_ssd_reg_788,SSD Register 788"
hexmask.long 0xA4C 0.--31. 1. "ssd_index_25216_25247,"
line.long 0xA50 "smmu_ssd_reg_789,SSD Register 789"
hexmask.long 0xA50 0.--31. 1. "ssd_index_25248_25279,"
line.long 0xA54 "smmu_ssd_reg_790,SSD Register 790"
hexmask.long 0xA54 0.--31. 1. "ssd_index_25280_25311,"
line.long 0xA58 "smmu_ssd_reg_791,SSD Register 791"
hexmask.long 0xA58 0.--31. 1. "ssd_index_25312_25343,"
line.long 0xA5C "smmu_ssd_reg_792,SSD Register 792"
hexmask.long 0xA5C 0.--31. 1. "ssd_index_25344_25375,"
line.long 0xA60 "smmu_ssd_reg_793,SSD Register 793"
hexmask.long 0xA60 0.--31. 1. "ssd_index_25376_25407,"
line.long 0xA64 "smmu_ssd_reg_794,SSD Register 794"
hexmask.long 0xA64 0.--31. 1. "ssd_index_25408_25439,"
line.long 0xA68 "smmu_ssd_reg_795,SSD Register 795"
hexmask.long 0xA68 0.--31. 1. "ssd_index_25440_25471,"
line.long 0xA6C "smmu_ssd_reg_796,SSD Register 796"
hexmask.long 0xA6C 0.--31. 1. "ssd_index_25472_25503,"
line.long 0xA70 "smmu_ssd_reg_797,SSD Register 797"
hexmask.long 0xA70 0.--31. 1. "ssd_index_25504_25535,"
line.long 0xA74 "smmu_ssd_reg_798,SSD Register 798"
hexmask.long 0xA74 0.--31. 1. "ssd_index_25536_25567,"
line.long 0xA78 "smmu_ssd_reg_799,SSD Register 799"
hexmask.long 0xA78 0.--31. 1. "ssd_index_25568_25599,"
line.long 0xA7C "smmu_ssd_reg_800,SSD Register 800"
hexmask.long 0xA7C 0.--31. 1. "ssd_index_25600_25631,"
line.long 0xA80 "smmu_ssd_reg_801,SSD Register 801"
hexmask.long 0xA80 0.--31. 1. "ssd_index_25632_25663,"
line.long 0xA84 "smmu_ssd_reg_802,SSD Register 802"
hexmask.long 0xA84 0.--31. 1. "ssd_index_25664_25695,"
line.long 0xA88 "smmu_ssd_reg_803,SSD Register 803"
hexmask.long 0xA88 0.--31. 1. "ssd_index_25696_25727,"
line.long 0xA8C "smmu_ssd_reg_804,SSD Register 804"
hexmask.long 0xA8C 0.--31. 1. "ssd_index_25728_25759,"
line.long 0xA90 "smmu_ssd_reg_805,SSD Register 805"
hexmask.long 0xA90 0.--31. 1. "ssd_index_25760_25791,"
line.long 0xA94 "smmu_ssd_reg_806,SSD Register 806"
hexmask.long 0xA94 0.--31. 1. "ssd_index_25792_25823,"
line.long 0xA98 "smmu_ssd_reg_807,SSD Register 807"
hexmask.long 0xA98 0.--31. 1. "ssd_index_25824_25855,"
line.long 0xA9C "smmu_ssd_reg_808,SSD Register 808"
hexmask.long 0xA9C 0.--31. 1. "ssd_index_25856_25887,"
line.long 0xAA0 "smmu_ssd_reg_809,SSD Register 809"
hexmask.long 0xAA0 0.--31. 1. "ssd_index_25888_25919,"
line.long 0xAA4 "smmu_ssd_reg_810,SSD Register 810"
hexmask.long 0xAA4 0.--31. 1. "ssd_index_25920_25951,"
line.long 0xAA8 "smmu_ssd_reg_811,SSD Register 811"
hexmask.long 0xAA8 0.--31. 1. "ssd_index_25952_25983,"
line.long 0xAAC "smmu_ssd_reg_812,SSD Register 812"
hexmask.long 0xAAC 0.--31. 1. "ssd_index_25984_26015,"
line.long 0xAB0 "smmu_ssd_reg_813,SSD Register 813"
hexmask.long 0xAB0 0.--31. 1. "ssd_index_26016_26047,"
line.long 0xAB4 "smmu_ssd_reg_814,SSD Register 814"
hexmask.long 0xAB4 0.--31. 1. "ssd_index_26048_26079,"
line.long 0xAB8 "smmu_ssd_reg_815,SSD Register 815"
hexmask.long 0xAB8 0.--31. 1. "ssd_index_26080_26111,"
line.long 0xABC "smmu_ssd_reg_816,SSD Register 816"
hexmask.long 0xABC 0.--31. 1. "ssd_index_26112_26143,"
line.long 0xAC0 "smmu_ssd_reg_817,SSD Register 817"
hexmask.long 0xAC0 0.--31. 1. "ssd_index_26144_26175,"
line.long 0xAC4 "smmu_ssd_reg_818,SSD Register 818"
hexmask.long 0xAC4 0.--31. 1. "ssd_index_26176_26207,"
line.long 0xAC8 "smmu_ssd_reg_819,SSD Register 819"
hexmask.long 0xAC8 0.--31. 1. "ssd_index_26208_26239,"
line.long 0xACC "smmu_ssd_reg_820,SSD Register 820"
hexmask.long 0xACC 0.--31. 1. "ssd_index_26240_26271,"
line.long 0xAD0 "smmu_ssd_reg_821,SSD Register 821"
hexmask.long 0xAD0 0.--31. 1. "ssd_index_26272_26303,"
line.long 0xAD4 "smmu_ssd_reg_822,SSD Register 822"
hexmask.long 0xAD4 0.--31. 1. "ssd_index_26304_26335,"
line.long 0xAD8 "smmu_ssd_reg_823,SSD Register 823"
hexmask.long 0xAD8 0.--31. 1. "ssd_index_26336_26367,"
line.long 0xADC "smmu_ssd_reg_824,SSD Register 824"
hexmask.long 0xADC 0.--31. 1. "ssd_index_26368_26399,"
line.long 0xAE0 "smmu_ssd_reg_825,SSD Register 825"
hexmask.long 0xAE0 0.--31. 1. "ssd_index_26400_26431,"
line.long 0xAE4 "smmu_ssd_reg_826,SSD Register 826"
hexmask.long 0xAE4 0.--31. 1. "ssd_index_26432_26463,"
line.long 0xAE8 "smmu_ssd_reg_827,SSD Register 827"
hexmask.long 0xAE8 0.--31. 1. "ssd_index_26464_26495,"
line.long 0xAEC "smmu_ssd_reg_828,SSD Register 828"
hexmask.long 0xAEC 0.--31. 1. "ssd_index_26496_26527,"
line.long 0xAF0 "smmu_ssd_reg_829,SSD Register 829"
hexmask.long 0xAF0 0.--31. 1. "ssd_index_26528_26559,"
line.long 0xAF4 "smmu_ssd_reg_830,SSD Register 830"
hexmask.long 0xAF4 0.--31. 1. "ssd_index_26560_26591,"
line.long 0xAF8 "smmu_ssd_reg_831,SSD Register 831"
hexmask.long 0xAF8 0.--31. 1. "ssd_index_26592_26623,"
line.long 0xAFC "smmu_ssd_reg_832,SSD Register 832"
hexmask.long 0xAFC 0.--31. 1. "ssd_index_26624_26655,"
line.long 0xB00 "smmu_ssd_reg_833,SSD Register 833"
hexmask.long 0xB00 0.--31. 1. "ssd_index_26656_26687,"
line.long 0xB04 "smmu_ssd_reg_834,SSD Register 834"
hexmask.long 0xB04 0.--31. 1. "ssd_index_26688_26719,"
line.long 0xB08 "smmu_ssd_reg_835,SSD Register 835"
hexmask.long 0xB08 0.--31. 1. "ssd_index_26720_26751,"
line.long 0xB0C "smmu_ssd_reg_836,SSD Register 836"
hexmask.long 0xB0C 0.--31. 1. "ssd_index_26752_26783,"
line.long 0xB10 "smmu_ssd_reg_837,SSD Register 837"
hexmask.long 0xB10 0.--31. 1. "ssd_index_26784_26815,"
line.long 0xB14 "smmu_ssd_reg_838,SSD Register 838"
hexmask.long 0xB14 0.--31. 1. "ssd_index_26816_26847,"
line.long 0xB18 "smmu_ssd_reg_839,SSD Register 839"
hexmask.long 0xB18 0.--31. 1. "ssd_index_26848_26879,"
line.long 0xB1C "smmu_ssd_reg_840,SSD Register 840"
hexmask.long 0xB1C 0.--31. 1. "ssd_index_26880_26911,"
line.long 0xB20 "smmu_ssd_reg_841,SSD Register 841"
hexmask.long 0xB20 0.--31. 1. "ssd_index_26912_26943,"
line.long 0xB24 "smmu_ssd_reg_842,SSD Register 842"
hexmask.long 0xB24 0.--31. 1. "ssd_index_26944_26975,"
line.long 0xB28 "smmu_ssd_reg_843,SSD Register 843"
hexmask.long 0xB28 0.--31. 1. "ssd_index_26976_27007,"
line.long 0xB2C "smmu_ssd_reg_844,SSD Register 844"
hexmask.long 0xB2C 0.--31. 1. "ssd_index_27008_27039,"
line.long 0xB30 "smmu_ssd_reg_845,SSD Register 845"
hexmask.long 0xB30 0.--31. 1. "ssd_index_27040_27071,"
line.long 0xB34 "smmu_ssd_reg_846,SSD Register 846"
hexmask.long 0xB34 0.--31. 1. "ssd_index_27072_27103,"
line.long 0xB38 "smmu_ssd_reg_847,SSD Register 847"
hexmask.long 0xB38 0.--31. 1. "ssd_index_27104_27135,"
line.long 0xB3C "smmu_ssd_reg_848,SSD Register 848"
hexmask.long 0xB3C 0.--31. 1. "ssd_index_27136_27167,"
line.long 0xB40 "smmu_ssd_reg_849,SSD Register 849"
hexmask.long 0xB40 0.--31. 1. "ssd_index_27168_27199,"
line.long 0xB44 "smmu_ssd_reg_850,SSD Register 850"
hexmask.long 0xB44 0.--31. 1. "ssd_index_27200_27231,"
line.long 0xB48 "smmu_ssd_reg_851,SSD Register 851"
hexmask.long 0xB48 0.--31. 1. "ssd_index_27232_27263,"
line.long 0xB4C "smmu_ssd_reg_852,SSD Register 852"
hexmask.long 0xB4C 0.--31. 1. "ssd_index_27264_27295,"
line.long 0xB50 "smmu_ssd_reg_853,SSD Register 853"
hexmask.long 0xB50 0.--31. 1. "ssd_index_27296_27327,"
line.long 0xB54 "smmu_ssd_reg_854,SSD Register 854"
hexmask.long 0xB54 0.--31. 1. "ssd_index_27328_27359,"
line.long 0xB58 "smmu_ssd_reg_855,SSD Register 855"
hexmask.long 0xB58 0.--31. 1. "ssd_index_27360_27391,"
line.long 0xB5C "smmu_ssd_reg_856,SSD Register 856"
hexmask.long 0xB5C 0.--31. 1. "ssd_index_27392_27423,"
line.long 0xB60 "smmu_ssd_reg_857,SSD Register 857"
hexmask.long 0xB60 0.--31. 1. "ssd_index_27424_27455,"
line.long 0xB64 "smmu_ssd_reg_858,SSD Register 858"
hexmask.long 0xB64 0.--31. 1. "ssd_index_27456_27487,"
line.long 0xB68 "smmu_ssd_reg_859,SSD Register 859"
hexmask.long 0xB68 0.--31. 1. "ssd_index_27488_27519,"
line.long 0xB6C "smmu_ssd_reg_860,SSD Register 860"
hexmask.long 0xB6C 0.--31. 1. "ssd_index_27520_27551,"
line.long 0xB70 "smmu_ssd_reg_861,SSD Register 861"
hexmask.long 0xB70 0.--31. 1. "ssd_index_27552_27583,"
line.long 0xB74 "smmu_ssd_reg_862,SSD Register 862"
hexmask.long 0xB74 0.--31. 1. "ssd_index_27584_27615,"
line.long 0xB78 "smmu_ssd_reg_863,SSD Register 863"
hexmask.long 0xB78 0.--31. 1. "ssd_index_27616_27647,"
line.long 0xB7C "smmu_ssd_reg_864,SSD Register 864"
hexmask.long 0xB7C 0.--31. 1. "ssd_index_27648_27679,"
line.long 0xB80 "smmu_ssd_reg_865,SSD Register 865"
hexmask.long 0xB80 0.--31. 1. "ssd_index_27680_27711,"
line.long 0xB84 "smmu_ssd_reg_866,SSD Register 866"
hexmask.long 0xB84 0.--31. 1. "ssd_index_27712_27743,"
line.long 0xB88 "smmu_ssd_reg_867,SSD Register 867"
hexmask.long 0xB88 0.--31. 1. "ssd_index_27744_27775,"
line.long 0xB8C "smmu_ssd_reg_868,SSD Register 868"
hexmask.long 0xB8C 0.--31. 1. "ssd_index_27776_27807,"
line.long 0xB90 "smmu_ssd_reg_869,SSD Register 869"
hexmask.long 0xB90 0.--31. 1. "ssd_index_27808_27839,"
line.long 0xB94 "smmu_ssd_reg_870,SSD Register 870"
hexmask.long 0xB94 0.--31. 1. "ssd_index_27840_27871,"
line.long 0xB98 "smmu_ssd_reg_871,SSD Register 871"
hexmask.long 0xB98 0.--31. 1. "ssd_index_27872_27903,"
line.long 0xB9C "smmu_ssd_reg_872,SSD Register 872"
hexmask.long 0xB9C 0.--31. 1. "ssd_index_27904_27935,"
line.long 0xBA0 "smmu_ssd_reg_873,SSD Register 873"
hexmask.long 0xBA0 0.--31. 1. "ssd_index_27936_27967,"
line.long 0xBA4 "smmu_ssd_reg_874,SSD Register 874"
hexmask.long 0xBA4 0.--31. 1. "ssd_index_27968_27999,"
line.long 0xBA8 "smmu_ssd_reg_875,SSD Register 875"
hexmask.long 0xBA8 0.--31. 1. "ssd_index_28000_28031,"
line.long 0xBAC "smmu_ssd_reg_876,SSD Register 876"
hexmask.long 0xBAC 0.--31. 1. "ssd_index_28032_28063,"
line.long 0xBB0 "smmu_ssd_reg_877,SSD Register 877"
hexmask.long 0xBB0 0.--31. 1. "ssd_index_28064_28095,"
line.long 0xBB4 "smmu_ssd_reg_878,SSD Register 878"
hexmask.long 0xBB4 0.--31. 1. "ssd_index_28096_28127,"
line.long 0xBB8 "smmu_ssd_reg_879,SSD Register 879"
hexmask.long 0xBB8 0.--31. 1. "ssd_index_28128_28159,"
line.long 0xBBC "smmu_ssd_reg_880,SSD Register 880"
hexmask.long 0xBBC 0.--31. 1. "ssd_index_28160_28191,"
line.long 0xBC0 "smmu_ssd_reg_881,SSD Register 881"
hexmask.long 0xBC0 0.--31. 1. "ssd_index_28192_28223,"
line.long 0xBC4 "smmu_ssd_reg_882,SSD Register 882"
hexmask.long 0xBC4 0.--31. 1. "ssd_index_28224_28255,"
line.long 0xBC8 "smmu_ssd_reg_883,SSD Register 883"
hexmask.long 0xBC8 0.--31. 1. "ssd_index_28256_28287,"
line.long 0xBCC "smmu_ssd_reg_884,SSD Register 884"
hexmask.long 0xBCC 0.--31. 1. "ssd_index_28288_28319,"
line.long 0xBD0 "smmu_ssd_reg_885,SSD Register 885"
hexmask.long 0xBD0 0.--31. 1. "ssd_index_28320_28351,"
line.long 0xBD4 "smmu_ssd_reg_886,SSD Register 886"
hexmask.long 0xBD4 0.--31. 1. "ssd_index_28352_28383,"
line.long 0xBD8 "smmu_ssd_reg_887,SSD Register 887"
hexmask.long 0xBD8 0.--31. 1. "ssd_index_28384_28415,"
line.long 0xBDC "smmu_ssd_reg_888,SSD Register 888"
hexmask.long 0xBDC 0.--31. 1. "ssd_index_28416_28447,"
line.long 0xBE0 "smmu_ssd_reg_889,SSD Register 889"
hexmask.long 0xBE0 0.--31. 1. "ssd_index_28448_28479,"
line.long 0xBE4 "smmu_ssd_reg_890,SSD Register 890"
hexmask.long 0xBE4 0.--31. 1. "ssd_index_28480_28511,"
line.long 0xBE8 "smmu_ssd_reg_891,SSD Register 891"
hexmask.long 0xBE8 0.--31. 1. "ssd_index_28512_28543,"
line.long 0xBEC "smmu_ssd_reg_892,SSD Register 892"
hexmask.long 0xBEC 0.--31. 1. "ssd_index_28544_28575,"
line.long 0xBF0 "smmu_ssd_reg_893,SSD Register 893"
hexmask.long 0xBF0 0.--31. 1. "ssd_index_28576_28607,"
line.long 0xBF4 "smmu_ssd_reg_894,SSD Register 894"
hexmask.long 0xBF4 0.--31. 1. "ssd_index_28608_28639,"
line.long 0xBF8 "smmu_ssd_reg_895,SSD Register 895"
hexmask.long 0xBF8 0.--31. 1. "ssd_index_28640_28671,"
line.long 0xBFC "smmu_ssd_reg_896,SSD Register 896"
hexmask.long 0xBFC 0.--31. 1. "ssd_index_28672_28703,"
line.long 0xC00 "smmu_ssd_reg_897,SSD Register 897"
hexmask.long 0xC00 0.--31. 1. "ssd_index_28704_28735,"
line.long 0xC04 "smmu_ssd_reg_898,SSD Register 898"
hexmask.long 0xC04 0.--31. 1. "ssd_index_28736_28767,"
line.long 0xC08 "smmu_ssd_reg_899,SSD Register 899"
hexmask.long 0xC08 0.--31. 1. "ssd_index_28768_28799,"
line.long 0xC0C "smmu_ssd_reg_900,SSD Register 900"
hexmask.long 0xC0C 0.--31. 1. "ssd_index_28800_28831,"
line.long 0xC10 "smmu_ssd_reg_901,SSD Register 901"
hexmask.long 0xC10 0.--31. 1. "ssd_index_28832_28863,"
line.long 0xC14 "smmu_ssd_reg_902,SSD Register 902"
hexmask.long 0xC14 0.--31. 1. "ssd_index_28864_28895,"
line.long 0xC18 "smmu_ssd_reg_903,SSD Register 903"
hexmask.long 0xC18 0.--31. 1. "ssd_index_28896_28927,"
line.long 0xC1C "smmu_ssd_reg_904,SSD Register 904"
hexmask.long 0xC1C 0.--31. 1. "ssd_index_28928_28959,"
line.long 0xC20 "smmu_ssd_reg_905,SSD Register 905"
hexmask.long 0xC20 0.--31. 1. "ssd_index_28960_28991,"
line.long 0xC24 "smmu_ssd_reg_906,SSD Register 906"
hexmask.long 0xC24 0.--31. 1. "ssd_index_28992_29023,"
line.long 0xC28 "smmu_ssd_reg_907,SSD Register 907"
hexmask.long 0xC28 0.--31. 1. "ssd_index_29024_29055,"
line.long 0xC2C "smmu_ssd_reg_908,SSD Register 908"
hexmask.long 0xC2C 0.--31. 1. "ssd_index_29056_29087,"
line.long 0xC30 "smmu_ssd_reg_909,SSD Register 909"
hexmask.long 0xC30 0.--31. 1. "ssd_index_29088_29119,"
line.long 0xC34 "smmu_ssd_reg_910,SSD Register 910"
hexmask.long 0xC34 0.--31. 1. "ssd_index_29120_29151,"
line.long 0xC38 "smmu_ssd_reg_911,SSD Register 911"
hexmask.long 0xC38 0.--31. 1. "ssd_index_29152_29183,"
line.long 0xC3C "smmu_ssd_reg_912,SSD Register 912"
hexmask.long 0xC3C 0.--31. 1. "ssd_index_29184_29215,"
line.long 0xC40 "smmu_ssd_reg_913,SSD Register 913"
hexmask.long 0xC40 0.--31. 1. "ssd_index_29216_29247,"
line.long 0xC44 "smmu_ssd_reg_914,SSD Register 914"
hexmask.long 0xC44 0.--31. 1. "ssd_index_29248_29279,"
line.long 0xC48 "smmu_ssd_reg_915,SSD Register 915"
hexmask.long 0xC48 0.--31. 1. "ssd_index_29280_29311,"
line.long 0xC4C "smmu_ssd_reg_916,SSD Register 916"
hexmask.long 0xC4C 0.--31. 1. "ssd_index_29312_29343,"
line.long 0xC50 "smmu_ssd_reg_917,SSD Register 917"
hexmask.long 0xC50 0.--31. 1. "ssd_index_29344_29375,"
line.long 0xC54 "smmu_ssd_reg_918,SSD Register 918"
hexmask.long 0xC54 0.--31. 1. "ssd_index_29376_29407,"
line.long 0xC58 "smmu_ssd_reg_919,SSD Register 919"
hexmask.long 0xC58 0.--31. 1. "ssd_index_29408_29439,"
line.long 0xC5C "smmu_ssd_reg_920,SSD Register 920"
hexmask.long 0xC5C 0.--31. 1. "ssd_index_29440_29471,"
line.long 0xC60 "smmu_ssd_reg_921,SSD Register 921"
hexmask.long 0xC60 0.--31. 1. "ssd_index_29472_29503,"
line.long 0xC64 "smmu_ssd_reg_922,SSD Register 922"
hexmask.long 0xC64 0.--31. 1. "ssd_index_29504_29535,"
line.long 0xC68 "smmu_ssd_reg_923,SSD Register 923"
hexmask.long 0xC68 0.--31. 1. "ssd_index_29536_29567,"
line.long 0xC6C "smmu_ssd_reg_924,SSD Register 924"
hexmask.long 0xC6C 0.--31. 1. "ssd_index_29568_29599,"
line.long 0xC70 "smmu_ssd_reg_925,SSD Register 925"
hexmask.long 0xC70 0.--31. 1. "ssd_index_29600_29631,"
line.long 0xC74 "smmu_ssd_reg_926,SSD Register 926"
hexmask.long 0xC74 0.--31. 1. "ssd_index_29632_29663,"
line.long 0xC78 "smmu_ssd_reg_927,SSD Register 927"
hexmask.long 0xC78 0.--31. 1. "ssd_index_29664_29695,"
line.long 0xC7C "smmu_ssd_reg_928,SSD Register 928"
hexmask.long 0xC7C 0.--31. 1. "ssd_index_29696_29727,"
line.long 0xC80 "smmu_ssd_reg_929,SSD Register 929"
hexmask.long 0xC80 0.--31. 1. "ssd_index_29728_29759,"
line.long 0xC84 "smmu_ssd_reg_930,SSD Register 930"
hexmask.long 0xC84 0.--31. 1. "ssd_index_29760_29791,"
line.long 0xC88 "smmu_ssd_reg_931,SSD Register 931"
hexmask.long 0xC88 0.--31. 1. "ssd_index_29792_29823,"
line.long 0xC8C "smmu_ssd_reg_932,SSD Register 932"
hexmask.long 0xC8C 0.--31. 1. "ssd_index_29824_29855,"
line.long 0xC90 "smmu_ssd_reg_933,SSD Register 933"
hexmask.long 0xC90 0.--31. 1. "ssd_index_29856_29887,"
line.long 0xC94 "smmu_ssd_reg_934,SSD Register 934"
hexmask.long 0xC94 0.--31. 1. "ssd_index_29888_29919,"
line.long 0xC98 "smmu_ssd_reg_935,SSD Register 935"
hexmask.long 0xC98 0.--31. 1. "ssd_index_29920_29951,"
line.long 0xC9C "smmu_ssd_reg_936,SSD Register 936"
hexmask.long 0xC9C 0.--31. 1. "ssd_index_29952_29983,"
line.long 0xCA0 "smmu_ssd_reg_937,SSD Register 937"
hexmask.long 0xCA0 0.--31. 1. "ssd_index_29984_30015,"
line.long 0xCA4 "smmu_ssd_reg_938,SSD Register 938"
hexmask.long 0xCA4 0.--31. 1. "ssd_index_30016_30047,"
line.long 0xCA8 "smmu_ssd_reg_939,SSD Register 939"
hexmask.long 0xCA8 0.--31. 1. "ssd_index_30048_30079,"
line.long 0xCAC "smmu_ssd_reg_940,SSD Register 940"
hexmask.long 0xCAC 0.--31. 1. "ssd_index_30080_30111,"
line.long 0xCB0 "smmu_ssd_reg_941,SSD Register 941"
hexmask.long 0xCB0 0.--31. 1. "ssd_index_30112_30143,"
line.long 0xCB4 "smmu_ssd_reg_942,SSD Register 942"
hexmask.long 0xCB4 0.--31. 1. "ssd_index_30144_30175,"
line.long 0xCB8 "smmu_ssd_reg_943,SSD Register 943"
hexmask.long 0xCB8 0.--31. 1. "ssd_index_30176_30207,"
line.long 0xCBC "smmu_ssd_reg_944,SSD Register 944"
hexmask.long 0xCBC 0.--31. 1. "ssd_index_30208_30239,"
line.long 0xCC0 "smmu_ssd_reg_945,SSD Register 945"
hexmask.long 0xCC0 0.--31. 1. "ssd_index_30240_30271,"
line.long 0xCC4 "smmu_ssd_reg_946,SSD Register 946"
hexmask.long 0xCC4 0.--31. 1. "ssd_index_30272_30303,"
line.long 0xCC8 "smmu_ssd_reg_947,SSD Register 947"
hexmask.long 0xCC8 0.--31. 1. "ssd_index_30304_30335,"
line.long 0xCCC "smmu_ssd_reg_948,SSD Register 948"
hexmask.long 0xCCC 0.--31. 1. "ssd_index_30336_30367,"
line.long 0xCD0 "smmu_ssd_reg_949,SSD Register 949"
hexmask.long 0xCD0 0.--31. 1. "ssd_index_30368_30399,"
line.long 0xCD4 "smmu_ssd_reg_950,SSD Register 950"
hexmask.long 0xCD4 0.--31. 1. "ssd_index_30400_30431,"
line.long 0xCD8 "smmu_ssd_reg_951,SSD Register 951"
hexmask.long 0xCD8 0.--31. 1. "ssd_index_30432_30463,"
line.long 0xCDC "smmu_ssd_reg_952,SSD Register 952"
hexmask.long 0xCDC 0.--31. 1. "ssd_index_30464_30495,"
line.long 0xCE0 "smmu_ssd_reg_953,SSD Register 953"
hexmask.long 0xCE0 0.--31. 1. "ssd_index_30496_30527,"
line.long 0xCE4 "smmu_ssd_reg_954,SSD Register 954"
hexmask.long 0xCE4 0.--31. 1. "ssd_index_30528_30559,"
line.long 0xCE8 "smmu_ssd_reg_955,SSD Register 955"
hexmask.long 0xCE8 0.--31. 1. "ssd_index_30560_30591,"
line.long 0xCEC "smmu_ssd_reg_956,SSD Register 956"
hexmask.long 0xCEC 0.--31. 1. "ssd_index_30592_30623,"
line.long 0xCF0 "smmu_ssd_reg_957,SSD Register 957"
hexmask.long 0xCF0 0.--31. 1. "ssd_index_30624_30655,"
line.long 0xCF4 "smmu_ssd_reg_958,SSD Register 958"
hexmask.long 0xCF4 0.--31. 1. "ssd_index_30656_30687,"
line.long 0xCF8 "smmu_ssd_reg_959,SSD Register 959"
hexmask.long 0xCF8 0.--31. 1. "ssd_index_30688_30719,"
line.long 0xCFC "smmu_ssd_reg_960,SSD Register 960"
hexmask.long 0xCFC 0.--31. 1. "ssd_index_30720_30751,"
line.long 0xD00 "smmu_ssd_reg_961,SSD Register 961"
hexmask.long 0xD00 0.--31. 1. "ssd_index_30752_30783,"
line.long 0xD04 "smmu_ssd_reg_962,SSD Register 962"
hexmask.long 0xD04 0.--31. 1. "ssd_index_30784_30815,"
line.long 0xD08 "smmu_ssd_reg_963,SSD Register 963"
hexmask.long 0xD08 0.--31. 1. "ssd_index_30816_30847,"
line.long 0xD0C "smmu_ssd_reg_964,SSD Register 964"
hexmask.long 0xD0C 0.--31. 1. "ssd_index_30848_30879,"
line.long 0xD10 "smmu_ssd_reg_965,SSD Register 965"
hexmask.long 0xD10 0.--31. 1. "ssd_index_30880_30911,"
line.long 0xD14 "smmu_ssd_reg_966,SSD Register 966"
hexmask.long 0xD14 0.--31. 1. "ssd_index_30912_30943,"
line.long 0xD18 "smmu_ssd_reg_967,SSD Register 967"
hexmask.long 0xD18 0.--31. 1. "ssd_index_30944_30975,"
line.long 0xD1C "smmu_ssd_reg_968,SSD Register 968"
hexmask.long 0xD1C 0.--31. 1. "ssd_index_30976_31007,"
line.long 0xD20 "smmu_ssd_reg_969,SSD Register 969"
hexmask.long 0xD20 0.--31. 1. "ssd_index_31008_31039,"
line.long 0xD24 "smmu_ssd_reg_970,SSD Register 970"
hexmask.long 0xD24 0.--31. 1. "ssd_index_31040_31071,"
line.long 0xD28 "smmu_ssd_reg_971,SSD Register 971"
hexmask.long 0xD28 0.--31. 1. "ssd_index_31072_31103,"
line.long 0xD2C "smmu_ssd_reg_972,SSD Register 972"
hexmask.long 0xD2C 0.--31. 1. "ssd_index_31104_31135,"
line.long 0xD30 "smmu_ssd_reg_973,SSD Register 973"
hexmask.long 0xD30 0.--31. 1. "ssd_index_31136_31167,"
line.long 0xD34 "smmu_ssd_reg_974,SSD Register 974"
hexmask.long 0xD34 0.--31. 1. "ssd_index_31168_31199,"
line.long 0xD38 "smmu_ssd_reg_975,SSD Register 975"
hexmask.long 0xD38 0.--31. 1. "ssd_index_31200_31231,"
line.long 0xD3C "smmu_ssd_reg_976,SSD Register 976"
hexmask.long 0xD3C 0.--31. 1. "ssd_index_31232_31263,"
line.long 0xD40 "smmu_ssd_reg_977,SSD Register 977"
hexmask.long 0xD40 0.--31. 1. "ssd_index_31264_31295,"
line.long 0xD44 "smmu_ssd_reg_978,SSD Register 978"
hexmask.long 0xD44 0.--31. 1. "ssd_index_31296_31327,"
line.long 0xD48 "smmu_ssd_reg_979,SSD Register 979"
hexmask.long 0xD48 0.--31. 1. "ssd_index_31328_31359,"
line.long 0xD4C "smmu_ssd_reg_980,SSD Register 980"
hexmask.long 0xD4C 0.--31. 1. "ssd_index_31360_31391,"
line.long 0xD50 "smmu_ssd_reg_981,SSD Register 981"
hexmask.long 0xD50 0.--31. 1. "ssd_index_31392_31423,"
line.long 0xD54 "smmu_ssd_reg_982,SSD Register 982"
hexmask.long 0xD54 0.--31. 1. "ssd_index_31424_31455,"
line.long 0xD58 "smmu_ssd_reg_983,SSD Register 983"
hexmask.long 0xD58 0.--31. 1. "ssd_index_31456_31487,"
line.long 0xD5C "smmu_ssd_reg_984,SSD Register 984"
hexmask.long 0xD5C 0.--31. 1. "ssd_index_31488_31519,"
line.long 0xD60 "smmu_ssd_reg_985,SSD Register 985"
hexmask.long 0xD60 0.--31. 1. "ssd_index_31520_31551,"
line.long 0xD64 "smmu_ssd_reg_986,SSD Register 986"
hexmask.long 0xD64 0.--31. 1. "ssd_index_31552_31583,"
line.long 0xD68 "smmu_ssd_reg_987,SSD Register 987"
hexmask.long 0xD68 0.--31. 1. "ssd_index_31584_31615,"
line.long 0xD6C "smmu_ssd_reg_988,SSD Register 988"
hexmask.long 0xD6C 0.--31. 1. "ssd_index_31616_31647,"
line.long 0xD70 "smmu_ssd_reg_989,SSD Register 989"
hexmask.long 0xD70 0.--31. 1. "ssd_index_31648_31679,"
line.long 0xD74 "smmu_ssd_reg_990,SSD Register 990"
hexmask.long 0xD74 0.--31. 1. "ssd_index_31680_31711,"
line.long 0xD78 "smmu_ssd_reg_991,SSD Register 991"
hexmask.long 0xD78 0.--31. 1. "ssd_index_31712_31743,"
line.long 0xD7C "smmu_ssd_reg_992,SSD Register 992"
hexmask.long 0xD7C 0.--31. 1. "ssd_index_31744_31775,"
line.long 0xD80 "smmu_ssd_reg_993,SSD Register 993"
hexmask.long 0xD80 0.--31. 1. "ssd_index_31776_31807,"
line.long 0xD84 "smmu_ssd_reg_994,SSD Register 994"
hexmask.long 0xD84 0.--31. 1. "ssd_index_31808_31839,"
line.long 0xD88 "smmu_ssd_reg_995,SSD Register 995"
hexmask.long 0xD88 0.--31. 1. "ssd_index_31840_31871,"
line.long 0xD8C "smmu_ssd_reg_996,SSD Register 996"
hexmask.long 0xD8C 0.--31. 1. "ssd_index_31872_31903,"
line.long 0xD90 "smmu_ssd_reg_997,SSD Register 997"
hexmask.long 0xD90 0.--31. 1. "ssd_index_31904_31935,"
line.long 0xD94 "smmu_ssd_reg_998,SSD Register 998"
hexmask.long 0xD94 0.--31. 1. "ssd_index_31936_31967,"
line.long 0xD98 "smmu_ssd_reg_999,SSD Register 999"
hexmask.long 0xD98 0.--31. 1. "ssd_index_31968_31999,"
line.long 0xD9C "smmu_ssd_reg_1000,SSD Register 1000"
hexmask.long 0xD9C 0.--31. 1. "ssd_index_32000_32031,"
line.long 0xDA0 "smmu_ssd_reg_1001,SSD Register 1001"
hexmask.long 0xDA0 0.--31. 1. "ssd_index_32032_32063,"
line.long 0xDA4 "smmu_ssd_reg_1002,SSD Register 1002"
hexmask.long 0xDA4 0.--31. 1. "ssd_index_32064_32095,"
line.long 0xDA8 "smmu_ssd_reg_1003,SSD Register 1003"
hexmask.long 0xDA8 0.--31. 1. "ssd_index_32096_32127,"
line.long 0xDAC "smmu_ssd_reg_1004,SSD Register 1004"
hexmask.long 0xDAC 0.--31. 1. "ssd_index_32128_32159,"
line.long 0xDB0 "smmu_ssd_reg_1005,SSD Register 1005"
hexmask.long 0xDB0 0.--31. 1. "ssd_index_32160_32191,"
line.long 0xDB4 "smmu_ssd_reg_1006,SSD Register 1006"
hexmask.long 0xDB4 0.--31. 1. "ssd_index_32192_32223,"
line.long 0xDB8 "smmu_ssd_reg_1007,SSD Register 1007"
hexmask.long 0xDB8 0.--31. 1. "ssd_index_32224_32255,"
line.long 0xDBC "smmu_ssd_reg_1008,SSD Register 1008"
hexmask.long 0xDBC 0.--31. 1. "ssd_index_32256_32287,"
line.long 0xDC0 "smmu_ssd_reg_1009,SSD Register 1009"
hexmask.long 0xDC0 0.--31. 1. "ssd_index_32288_32319,"
line.long 0xDC4 "smmu_ssd_reg_1010,SSD Register 1010"
hexmask.long 0xDC4 0.--31. 1. "ssd_index_32320_32351,"
line.long 0xDC8 "smmu_ssd_reg_1011,SSD Register 1011"
hexmask.long 0xDC8 0.--31. 1. "ssd_index_32352_32383,"
line.long 0xDCC "smmu_ssd_reg_1012,SSD Register 1012"
hexmask.long 0xDCC 0.--31. 1. "ssd_index_32384_32415,"
line.long 0xDD0 "smmu_ssd_reg_1013,SSD Register 1013"
hexmask.long 0xDD0 0.--31. 1. "ssd_index_32416_32447,"
line.long 0xDD4 "smmu_ssd_reg_1014,SSD Register 1014"
hexmask.long 0xDD4 0.--31. 1. "ssd_index_32448_32479,"
line.long 0xDD8 "smmu_ssd_reg_1015,SSD Register 1015"
hexmask.long 0xDD8 0.--31. 1. "ssd_index_32480_32511,"
line.long 0xDDC "smmu_ssd_reg_1016,SSD Register 1016"
hexmask.long 0xDDC 0.--31. 1. "ssd_index_32512_32543,"
line.long 0xDE0 "smmu_ssd_reg_1017,SSD Register 1017"
hexmask.long 0xDE0 0.--31. 1. "ssd_index_32544_32575,"
line.long 0xDE4 "smmu_ssd_reg_1018,SSD Register 1018"
hexmask.long 0xDE4 0.--31. 1. "ssd_index_32576_32607,"
line.long 0xDE8 "smmu_ssd_reg_1019,SSD Register 1019"
hexmask.long 0xDE8 0.--31. 1. "ssd_index_32608_32639,"
line.long 0xDEC "smmu_ssd_reg_1020,SSD Register 1020"
hexmask.long 0xDEC 0.--31. 1. "ssd_index_32640_32671,"
line.long 0xDF0 "smmu_ssd_reg_1021,SSD Register 1021"
hexmask.long 0xDF0 0.--31. 1. "ssd_index_32672_32703,"
line.long 0xDF4 "smmu_ssd_reg_1022,SSD Register 1022"
hexmask.long 0xDF4 0.--31. 1. "ssd_index_32704_32735,"
line.long 0xDF8 "smmu_ssd_reg_1023,SSD Register 1023"
hexmask.long 0xDF8 0.--31. 1. "ssd_index_32736_32767,"
group.long 0x20000++0x7
line.long 0x0 "SMMU_CB0_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB0_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x20008++0x3
line.long 0x0 "SMMU_CB0_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x20010++0x3
line.long 0x0 "SMMU_CB0_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x20020++0x1F
line.long 0x0 "SMMU_CB0_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB0_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB0_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB0_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB0_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB0_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB0_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB0_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x20058++0x7
line.long 0x0 "SMMU_CB0_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB0_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x20060++0xB
line.long 0x0 "SMMU_CB0_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB0_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB0_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x20070++0x7
line.long 0x0 "SMMU_CB0_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB0_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x20600++0x13
line.long 0x0 "SMMU_CB0_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB0_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB0_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB0_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB0_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x20618++0x3
line.long 0x0 "SMMU_CB0_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context banks."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x20620++0x1F
line.long 0x0 "SMMU_CB0_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB0_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB0_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB0_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB0_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB0_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB0_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB0_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x207F0++0x3
line.long 0x0 "SMMU_CB0_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x207F4++0x3
line.long 0x0 "SMMU_CB0_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x20E00++0xF
line.long 0x0 "SMMU_CB0_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB0_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB0_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB0_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x20E80++0xF
line.long 0x0 "SMMU_CB0_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB0_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB0_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB0_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x20F00++0x3
line.long 0x0 "SMMU_CB0_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x20F04++0x3
line.long 0x0 "SMMU_CB0_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x20F20++0x3
line.long 0x0 "SMMU_CB0_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x20F40++0x13
line.long 0x0 "SMMU_CB0_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB0_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB0_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB0_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB0_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x20F58++0x3
line.long 0x0 "SMMU_CB0_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x20FB8++0x3
line.long 0x0 "smmu_cb0_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x21000++0x7
line.long 0x0 "SMMU_CB1_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB1_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x21008++0x3
line.long 0x0 "SMMU_CB1_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x21010++0x3
line.long 0x0 "SMMU_CB1_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x21020++0x1F
line.long 0x0 "SMMU_CB1_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB1_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB1_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB1_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB1_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB1_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB1_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB1_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x21058++0x7
line.long 0x0 "SMMU_CB1_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB1_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x21060++0xB
line.long 0x0 "SMMU_CB1_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB1_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB1_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x21070++0x7
line.long 0x0 "SMMU_CB1_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB1_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x21600++0x13
line.long 0x0 "SMMU_CB1_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB1_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB1_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB1_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB1_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x21618++0x3
line.long 0x0 "SMMU_CB1_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context banks."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x21620++0x1F
line.long 0x0 "SMMU_CB1_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB1_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB1_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB1_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB1_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB1_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB1_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB1_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x217F0++0x3
line.long 0x0 "SMMU_CB1_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x217F4++0x3
line.long 0x0 "SMMU_CB1_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x21E00++0xF
line.long 0x0 "SMMU_CB1_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB1_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB1_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB1_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x21E80++0xF
line.long 0x0 "SMMU_CB1_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB1_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB1_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB1_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x21F00++0x3
line.long 0x0 "SMMU_CB1_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x21F04++0x3
line.long 0x0 "SMMU_CB1_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x21F20++0x3
line.long 0x0 "SMMU_CB1_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x21F40++0x13
line.long 0x0 "SMMU_CB1_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB1_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB1_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB1_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB1_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x21F58++0x3
line.long 0x0 "SMMU_CB1_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x21FB8++0x3
line.long 0x0 "smmu_cb1_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x22000++0x7
line.long 0x0 "SMMU_CB2_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB2_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x22008++0x3
line.long 0x0 "SMMU_CB2_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x22010++0x3
line.long 0x0 "SMMU_CB2_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x22020++0x1F
line.long 0x0 "SMMU_CB2_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB2_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB2_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB2_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB2_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB2_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB2_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB2_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x22058++0x7
line.long 0x0 "SMMU_CB2_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB2_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x22060++0xB
line.long 0x0 "SMMU_CB2_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB2_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB2_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x22070++0x7
line.long 0x0 "SMMU_CB2_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB2_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x22600++0x13
line.long 0x0 "SMMU_CB2_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB2_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB2_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB2_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB2_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x22618++0x3
line.long 0x0 "SMMU_CB2_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context banks."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x22620++0x1F
line.long 0x0 "SMMU_CB2_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB2_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB2_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB2_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB2_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB2_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB2_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB2_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x227F0++0x3
line.long 0x0 "SMMU_CB2_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x227F4++0x3
line.long 0x0 "SMMU_CB2_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x22E00++0xF
line.long 0x0 "SMMU_CB2_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB2_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB2_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB2_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x22E80++0xF
line.long 0x0 "SMMU_CB2_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB2_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB2_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB2_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x22F00++0x3
line.long 0x0 "SMMU_CB2_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x22F04++0x3
line.long 0x0 "SMMU_CB2_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x22F20++0x3
line.long 0x0 "SMMU_CB2_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x22F40++0x13
line.long 0x0 "SMMU_CB2_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB2_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB2_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB2_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB2_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x22F58++0x3
line.long 0x0 "SMMU_CB2_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x22FB8++0x3
line.long 0x0 "smmu_cb2_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x23000++0x7
line.long 0x0 "SMMU_CB3_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB3_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x23008++0x3
line.long 0x0 "SMMU_CB3_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x23010++0x3
line.long 0x0 "SMMU_CB3_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x23020++0x1F
line.long 0x0 "SMMU_CB3_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB3_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB3_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB3_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB3_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB3_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB3_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB3_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x23058++0x7
line.long 0x0 "SMMU_CB3_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB3_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x23060++0xB
line.long 0x0 "SMMU_CB3_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB3_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB3_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x23070++0x7
line.long 0x0 "SMMU_CB3_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB3_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x23600++0x13
line.long 0x0 "SMMU_CB3_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB3_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB3_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB3_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB3_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x23618++0x3
line.long 0x0 "SMMU_CB3_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context banks."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x23620++0x1F
line.long 0x0 "SMMU_CB3_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB3_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB3_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB3_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB3_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB3_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB3_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB3_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x237F0++0x3
line.long 0x0 "SMMU_CB3_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x237F4++0x3
line.long 0x0 "SMMU_CB3_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x23E00++0xF
line.long 0x0 "SMMU_CB3_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB3_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB3_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB3_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x23E80++0xF
line.long 0x0 "SMMU_CB3_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB3_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB3_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB3_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x23F00++0x3
line.long 0x0 "SMMU_CB3_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x23F04++0x3
line.long 0x0 "SMMU_CB3_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x23F20++0x3
line.long 0x0 "SMMU_CB3_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x23F40++0x13
line.long 0x0 "SMMU_CB3_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB3_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB3_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB3_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB3_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x23F58++0x3
line.long 0x0 "SMMU_CB3_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x23FB8++0x3
line.long 0x0 "smmu_cb3_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x24000++0x7
line.long 0x0 "SMMU_CB4_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB4_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x24008++0x3
line.long 0x0 "SMMU_CB4_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x24010++0x3
line.long 0x0 "SMMU_CB4_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x24020++0x1F
line.long 0x0 "SMMU_CB4_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB4_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB4_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB4_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB4_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB4_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB4_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB4_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x24058++0x7
line.long 0x0 "SMMU_CB4_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB4_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x24060++0xB
line.long 0x0 "SMMU_CB4_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB4_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB4_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x24070++0x7
line.long 0x0 "SMMU_CB4_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB4_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x24600++0x13
line.long 0x0 "SMMU_CB4_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB4_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB4_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB4_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB4_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x24618++0x3
line.long 0x0 "SMMU_CB4_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context banks."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x24620++0x1F
line.long 0x0 "SMMU_CB4_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB4_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB4_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB4_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB4_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB4_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB4_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB4_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x247F0++0x3
line.long 0x0 "SMMU_CB4_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x247F4++0x3
line.long 0x0 "SMMU_CB4_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x24E00++0xF
line.long 0x0 "SMMU_CB4_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB4_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB4_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB4_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x24E80++0xF
line.long 0x0 "SMMU_CB4_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB4_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB4_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB4_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x24F00++0x3
line.long 0x0 "SMMU_CB4_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x24F04++0x3
line.long 0x0 "SMMU_CB4_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x24F20++0x3
line.long 0x0 "SMMU_CB4_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x24F40++0x13
line.long 0x0 "SMMU_CB4_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB4_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB4_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB4_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB4_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x24F58++0x3
line.long 0x0 "SMMU_CB4_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x24FB8++0x3
line.long 0x0 "smmu_cb4_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x25000++0x7
line.long 0x0 "SMMU_CB5_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB5_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x25008++0x3
line.long 0x0 "SMMU_CB5_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x25010++0x3
line.long 0x0 "SMMU_CB5_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x25020++0x1F
line.long 0x0 "SMMU_CB5_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB5_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB5_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB5_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB5_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB5_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB5_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB5_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x25058++0x7
line.long 0x0 "SMMU_CB5_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB5_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x25060++0xB
line.long 0x0 "SMMU_CB5_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB5_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB5_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x25070++0x7
line.long 0x0 "SMMU_CB5_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB5_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x25600++0x13
line.long 0x0 "SMMU_CB5_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB5_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB5_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB5_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB5_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x25618++0x3
line.long 0x0 "SMMU_CB5_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context banks."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x25620++0x1F
line.long 0x0 "SMMU_CB5_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB5_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB5_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB5_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB5_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB5_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB5_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB5_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x257F0++0x3
line.long 0x0 "SMMU_CB5_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x257F4++0x3
line.long 0x0 "SMMU_CB5_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x25E00++0xF
line.long 0x0 "SMMU_CB5_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB5_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB5_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB5_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x25E80++0xF
line.long 0x0 "SMMU_CB5_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB5_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB5_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB5_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x25F00++0x3
line.long 0x0 "SMMU_CB5_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x25F04++0x3
line.long 0x0 "SMMU_CB5_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x25F20++0x3
line.long 0x0 "SMMU_CB5_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x25F40++0x13
line.long 0x0 "SMMU_CB5_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB5_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB5_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB5_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB5_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x25F58++0x3
line.long 0x0 "SMMU_CB5_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x25FB8++0x3
line.long 0x0 "smmu_cb5_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x26000++0x7
line.long 0x0 "SMMU_CB6_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB6_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x26008++0x3
line.long 0x0 "SMMU_CB6_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x26010++0x3
line.long 0x0 "SMMU_CB6_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x26020++0x1F
line.long 0x0 "SMMU_CB6_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB6_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB6_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB6_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB6_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB6_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB6_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB6_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x26058++0x7
line.long 0x0 "SMMU_CB6_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB6_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x26060++0xB
line.long 0x0 "SMMU_CB6_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB6_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB6_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x26070++0x7
line.long 0x0 "SMMU_CB6_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB6_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x26600++0x13
line.long 0x0 "SMMU_CB6_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB6_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB6_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB6_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB6_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x26618++0x3
line.long 0x0 "SMMU_CB6_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context banks."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x26620++0x1F
line.long 0x0 "SMMU_CB6_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB6_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB6_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB6_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB6_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB6_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB6_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB6_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x267F0++0x3
line.long 0x0 "SMMU_CB6_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x267F4++0x3
line.long 0x0 "SMMU_CB6_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x26E00++0xF
line.long 0x0 "SMMU_CB6_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB6_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB6_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB6_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x26E80++0xF
line.long 0x0 "SMMU_CB6_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB6_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB6_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB6_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x26F00++0x3
line.long 0x0 "SMMU_CB6_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x26F04++0x3
line.long 0x0 "SMMU_CB6_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x26F20++0x3
line.long 0x0 "SMMU_CB6_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x26F40++0x13
line.long 0x0 "SMMU_CB6_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB6_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB6_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB6_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB6_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x26F58++0x3
line.long 0x0 "SMMU_CB6_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x26FB8++0x3
line.long 0x0 "smmu_cb6_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x27000++0x7
line.long 0x0 "SMMU_CB7_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB7_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x27008++0x3
line.long 0x0 "SMMU_CB7_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x27010++0x3
line.long 0x0 "SMMU_CB7_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x27020++0x1F
line.long 0x0 "SMMU_CB7_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB7_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB7_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB7_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB7_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB7_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB7_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB7_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x27058++0x7
line.long 0x0 "SMMU_CB7_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB7_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x27060++0xB
line.long 0x0 "SMMU_CB7_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB7_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB7_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x27070++0x7
line.long 0x0 "SMMU_CB7_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB7_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x27600++0x13
line.long 0x0 "SMMU_CB7_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB7_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB7_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB7_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB7_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x27618++0x3
line.long 0x0 "SMMU_CB7_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context banks."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x27620++0x1F
line.long 0x0 "SMMU_CB7_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB7_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB7_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB7_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB7_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB7_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB7_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB7_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x277F0++0x3
line.long 0x0 "SMMU_CB7_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x277F4++0x3
line.long 0x0 "SMMU_CB7_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x27E00++0xF
line.long 0x0 "SMMU_CB7_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB7_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB7_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB7_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x27E80++0xF
line.long 0x0 "SMMU_CB7_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB7_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB7_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB7_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x27F00++0x3
line.long 0x0 "SMMU_CB7_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x27F04++0x3
line.long 0x0 "SMMU_CB7_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x27F20++0x3
line.long 0x0 "SMMU_CB7_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x27F40++0x13
line.long 0x0 "SMMU_CB7_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB7_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB7_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB7_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB7_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x27F58++0x3
line.long 0x0 "SMMU_CB7_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x27FB8++0x3
line.long 0x0 "smmu_cb7_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x28000++0x7
line.long 0x0 "SMMU_CB8_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB8_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x28008++0x3
line.long 0x0 "SMMU_CB8_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x28010++0x3
line.long 0x0 "SMMU_CB8_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x28020++0x1F
line.long 0x0 "SMMU_CB8_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB8_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB8_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB8_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB8_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB8_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB8_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB8_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x28058++0x7
line.long 0x0 "SMMU_CB8_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB8_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x28060++0xB
line.long 0x0 "SMMU_CB8_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB8_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB8_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x28070++0x7
line.long 0x0 "SMMU_CB8_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB8_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x28600++0x13
line.long 0x0 "SMMU_CB8_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB8_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB8_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB8_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB8_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x28618++0x3
line.long 0x0 "SMMU_CB8_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context banks."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x28620++0x1F
line.long 0x0 "SMMU_CB8_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB8_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB8_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB8_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB8_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB8_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB8_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB8_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x287F0++0x3
line.long 0x0 "SMMU_CB8_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x287F4++0x3
line.long 0x0 "SMMU_CB8_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x28E00++0xF
line.long 0x0 "SMMU_CB8_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB8_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB8_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB8_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x28E80++0xF
line.long 0x0 "SMMU_CB8_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB8_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB8_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB8_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x28F00++0x3
line.long 0x0 "SMMU_CB8_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x28F04++0x3
line.long 0x0 "SMMU_CB8_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x28F20++0x3
line.long 0x0 "SMMU_CB8_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x28F40++0x13
line.long 0x0 "SMMU_CB8_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB8_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB8_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB8_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB8_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x28F58++0x3
line.long 0x0 "SMMU_CB8_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x28FB8++0x3
line.long 0x0 "smmu_cb8_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x29000++0x7
line.long 0x0 "SMMU_CB9_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB9_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x29008++0x3
line.long 0x0 "SMMU_CB9_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x29010++0x3
line.long 0x0 "SMMU_CB9_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x29020++0x1F
line.long 0x0 "SMMU_CB9_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB9_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB9_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB9_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB9_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB9_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB9_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB9_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x29058++0x7
line.long 0x0 "SMMU_CB9_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB9_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x29060++0xB
line.long 0x0 "SMMU_CB9_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB9_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB9_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x29070++0x7
line.long 0x0 "SMMU_CB9_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB9_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x29600++0x13
line.long 0x0 "SMMU_CB9_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB9_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB9_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB9_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB9_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x29618++0x3
line.long 0x0 "SMMU_CB9_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context banks."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x29620++0x1F
line.long 0x0 "SMMU_CB9_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB9_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB9_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB9_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB9_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB9_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB9_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB9_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x297F0++0x3
line.long 0x0 "SMMU_CB9_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x297F4++0x3
line.long 0x0 "SMMU_CB9_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x29E00++0xF
line.long 0x0 "SMMU_CB9_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB9_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB9_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB9_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x29E80++0xF
line.long 0x0 "SMMU_CB9_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB9_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB9_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB9_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x29F00++0x3
line.long 0x0 "SMMU_CB9_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x29F04++0x3
line.long 0x0 "SMMU_CB9_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x29F20++0x3
line.long 0x0 "SMMU_CB9_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x29F40++0x13
line.long 0x0 "SMMU_CB9_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB9_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB9_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB9_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB9_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x29F58++0x3
line.long 0x0 "SMMU_CB9_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x29FB8++0x3
line.long 0x0 "smmu_cb9_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x2A000++0x7
line.long 0x0 "SMMU_CB10_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB10_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x2A008++0x3
line.long 0x0 "SMMU_CB10_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x2A010++0x3
line.long 0x0 "SMMU_CB10_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x2A020++0x1F
line.long 0x0 "SMMU_CB10_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB10_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB10_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB10_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB10_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB10_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB10_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB10_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x2A058++0x7
line.long 0x0 "SMMU_CB10_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB10_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x2A060++0xB
line.long 0x0 "SMMU_CB10_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB10_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB10_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x2A070++0x7
line.long 0x0 "SMMU_CB10_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB10_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x2A600++0x13
line.long 0x0 "SMMU_CB10_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB10_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB10_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB10_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB10_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x2A618++0x3
line.long 0x0 "SMMU_CB10_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x2A620++0x1F
line.long 0x0 "SMMU_CB10_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB10_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB10_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB10_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB10_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB10_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB10_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB10_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x2A7F0++0x3
line.long 0x0 "SMMU_CB10_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x2A7F4++0x3
line.long 0x0 "SMMU_CB10_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x2AE00++0xF
line.long 0x0 "SMMU_CB10_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB10_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB10_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB10_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x2AE80++0xF
line.long 0x0 "SMMU_CB10_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB10_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB10_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB10_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x2AF00++0x3
line.long 0x0 "SMMU_CB10_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x2AF04++0x3
line.long 0x0 "SMMU_CB10_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x2AF20++0x3
line.long 0x0 "SMMU_CB10_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x2AF40++0x13
line.long 0x0 "SMMU_CB10_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB10_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB10_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB10_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB10_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x2AF58++0x3
line.long 0x0 "SMMU_CB10_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x2AFB8++0x3
line.long 0x0 "smmu_cb10_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x2B000++0x7
line.long 0x0 "SMMU_CB11_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB11_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x2B008++0x3
line.long 0x0 "SMMU_CB11_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x2B010++0x3
line.long 0x0 "SMMU_CB11_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x2B020++0x1F
line.long 0x0 "SMMU_CB11_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB11_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB11_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB11_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB11_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB11_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB11_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB11_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x2B058++0x7
line.long 0x0 "SMMU_CB11_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB11_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x2B060++0xB
line.long 0x0 "SMMU_CB11_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB11_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB11_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x2B070++0x7
line.long 0x0 "SMMU_CB11_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB11_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x2B600++0x13
line.long 0x0 "SMMU_CB11_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB11_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB11_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB11_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB11_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x2B618++0x3
line.long 0x0 "SMMU_CB11_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x2B620++0x1F
line.long 0x0 "SMMU_CB11_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB11_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB11_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB11_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB11_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB11_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB11_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB11_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x2B7F0++0x3
line.long 0x0 "SMMU_CB11_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x2B7F4++0x3
line.long 0x0 "SMMU_CB11_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x2BE00++0xF
line.long 0x0 "SMMU_CB11_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB11_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB11_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB11_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x2BE80++0xF
line.long 0x0 "SMMU_CB11_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB11_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB11_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB11_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x2BF00++0x3
line.long 0x0 "SMMU_CB11_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x2BF04++0x3
line.long 0x0 "SMMU_CB11_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x2BF20++0x3
line.long 0x0 "SMMU_CB11_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x2BF40++0x13
line.long 0x0 "SMMU_CB11_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB11_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB11_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB11_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB11_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x2BF58++0x3
line.long 0x0 "SMMU_CB11_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x2BFB8++0x3
line.long 0x0 "smmu_cb11_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x2C000++0x7
line.long 0x0 "SMMU_CB12_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB12_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x2C008++0x3
line.long 0x0 "SMMU_CB12_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x2C010++0x3
line.long 0x0 "SMMU_CB12_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x2C020++0x1F
line.long 0x0 "SMMU_CB12_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB12_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB12_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB12_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB12_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB12_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB12_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB12_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x2C058++0x7
line.long 0x0 "SMMU_CB12_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB12_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x2C060++0xB
line.long 0x0 "SMMU_CB12_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB12_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB12_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x2C070++0x7
line.long 0x0 "SMMU_CB12_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB12_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x2C600++0x13
line.long 0x0 "SMMU_CB12_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB12_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB12_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB12_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB12_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x2C618++0x3
line.long 0x0 "SMMU_CB12_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x2C620++0x1F
line.long 0x0 "SMMU_CB12_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB12_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB12_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB12_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB12_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB12_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB12_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB12_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x2C7F0++0x3
line.long 0x0 "SMMU_CB12_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x2C7F4++0x3
line.long 0x0 "SMMU_CB12_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x2CE00++0xF
line.long 0x0 "SMMU_CB12_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB12_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB12_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB12_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x2CE80++0xF
line.long 0x0 "SMMU_CB12_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB12_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB12_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB12_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x2CF00++0x3
line.long 0x0 "SMMU_CB12_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x2CF04++0x3
line.long 0x0 "SMMU_CB12_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x2CF20++0x3
line.long 0x0 "SMMU_CB12_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x2CF40++0x13
line.long 0x0 "SMMU_CB12_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB12_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB12_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB12_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB12_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x2CF58++0x3
line.long 0x0 "SMMU_CB12_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x2CFB8++0x3
line.long 0x0 "smmu_cb12_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x2D000++0x7
line.long 0x0 "SMMU_CB13_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB13_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x2D008++0x3
line.long 0x0 "SMMU_CB13_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x2D010++0x3
line.long 0x0 "SMMU_CB13_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x2D020++0x1F
line.long 0x0 "SMMU_CB13_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB13_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB13_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB13_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB13_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB13_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB13_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB13_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x2D058++0x7
line.long 0x0 "SMMU_CB13_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB13_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x2D060++0xB
line.long 0x0 "SMMU_CB13_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB13_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB13_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x2D070++0x7
line.long 0x0 "SMMU_CB13_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB13_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x2D600++0x13
line.long 0x0 "SMMU_CB13_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB13_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB13_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB13_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB13_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x2D618++0x3
line.long 0x0 "SMMU_CB13_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x2D620++0x1F
line.long 0x0 "SMMU_CB13_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB13_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB13_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB13_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB13_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB13_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB13_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB13_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x2D7F0++0x3
line.long 0x0 "SMMU_CB13_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x2D7F4++0x3
line.long 0x0 "SMMU_CB13_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x2DE00++0xF
line.long 0x0 "SMMU_CB13_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB13_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB13_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB13_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x2DE80++0xF
line.long 0x0 "SMMU_CB13_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB13_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB13_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB13_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x2DF00++0x3
line.long 0x0 "SMMU_CB13_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x2DF04++0x3
line.long 0x0 "SMMU_CB13_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x2DF20++0x3
line.long 0x0 "SMMU_CB13_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x2DF40++0x13
line.long 0x0 "SMMU_CB13_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB13_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB13_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB13_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB13_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x2DF58++0x3
line.long 0x0 "SMMU_CB13_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x2DFB8++0x3
line.long 0x0 "smmu_cb13_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x2E000++0x7
line.long 0x0 "SMMU_CB14_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB14_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x2E008++0x3
line.long 0x0 "SMMU_CB14_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x2E010++0x3
line.long 0x0 "SMMU_CB14_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x2E020++0x1F
line.long 0x0 "SMMU_CB14_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB14_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB14_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB14_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB14_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB14_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB14_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB14_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x2E058++0x7
line.long 0x0 "SMMU_CB14_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB14_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x2E060++0xB
line.long 0x0 "SMMU_CB14_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB14_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB14_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x2E070++0x7
line.long 0x0 "SMMU_CB14_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB14_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x2E600++0x13
line.long 0x0 "SMMU_CB14_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB14_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB14_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB14_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB14_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x2E618++0x3
line.long 0x0 "SMMU_CB14_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x2E620++0x1F
line.long 0x0 "SMMU_CB14_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB14_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB14_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB14_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB14_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB14_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB14_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB14_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x2E7F0++0x3
line.long 0x0 "SMMU_CB14_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x2E7F4++0x3
line.long 0x0 "SMMU_CB14_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x2EE00++0xF
line.long 0x0 "SMMU_CB14_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB14_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB14_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB14_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x2EE80++0xF
line.long 0x0 "SMMU_CB14_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB14_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB14_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB14_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x2EF00++0x3
line.long 0x0 "SMMU_CB14_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x2EF04++0x3
line.long 0x0 "SMMU_CB14_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x2EF20++0x3
line.long 0x0 "SMMU_CB14_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x2EF40++0x13
line.long 0x0 "SMMU_CB14_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB14_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB14_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB14_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB14_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x2EF58++0x3
line.long 0x0 "SMMU_CB14_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x2EFB8++0x3
line.long 0x0 "smmu_cb14_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x2F000++0x7
line.long 0x0 "SMMU_CB15_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB15_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x2F008++0x3
line.long 0x0 "SMMU_CB15_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x2F010++0x3
line.long 0x0 "SMMU_CB15_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x2F020++0x1F
line.long 0x0 "SMMU_CB15_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB15_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB15_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB15_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB15_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB15_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB15_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB15_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x2F058++0x7
line.long 0x0 "SMMU_CB15_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB15_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x2F060++0xB
line.long 0x0 "SMMU_CB15_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB15_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB15_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x2F070++0x7
line.long 0x0 "SMMU_CB15_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB15_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x2F600++0x13
line.long 0x0 "SMMU_CB15_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB15_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB15_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB15_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB15_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x2F618++0x3
line.long 0x0 "SMMU_CB15_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x2F620++0x1F
line.long 0x0 "SMMU_CB15_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB15_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB15_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB15_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB15_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB15_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB15_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB15_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x2F7F0++0x3
line.long 0x0 "SMMU_CB15_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x2F7F4++0x3
line.long 0x0 "SMMU_CB15_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x2FE00++0xF
line.long 0x0 "SMMU_CB15_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB15_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB15_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB15_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x2FE80++0xF
line.long 0x0 "SMMU_CB15_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB15_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB15_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB15_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x2FF00++0x3
line.long 0x0 "SMMU_CB15_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x2FF04++0x3
line.long 0x0 "SMMU_CB15_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x2FF20++0x3
line.long 0x0 "SMMU_CB15_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x2FF40++0x13
line.long 0x0 "SMMU_CB15_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB15_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB15_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB15_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB15_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x2FF58++0x3
line.long 0x0 "SMMU_CB15_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x2FFB8++0x3
line.long 0x0 "smmu_cb15_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x30000++0x7
line.long 0x0 "SMMU_CB16_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB16_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x30008++0x3
line.long 0x0 "SMMU_CB16_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x30010++0x3
line.long 0x0 "SMMU_CB16_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x30020++0x1F
line.long 0x0 "SMMU_CB16_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB16_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB16_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB16_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB16_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB16_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB16_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB16_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x30058++0x7
line.long 0x0 "SMMU_CB16_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB16_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x30060++0xB
line.long 0x0 "SMMU_CB16_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB16_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB16_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x30070++0x7
line.long 0x0 "SMMU_CB16_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB16_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x30600++0x13
line.long 0x0 "SMMU_CB16_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB16_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB16_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB16_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB16_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x30618++0x3
line.long 0x0 "SMMU_CB16_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x30620++0x1F
line.long 0x0 "SMMU_CB16_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB16_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB16_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB16_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB16_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB16_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB16_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB16_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x307F0++0x3
line.long 0x0 "SMMU_CB16_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x307F4++0x3
line.long 0x0 "SMMU_CB16_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x30E00++0xF
line.long 0x0 "SMMU_CB16_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB16_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB16_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB16_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x30E80++0xF
line.long 0x0 "SMMU_CB16_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB16_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB16_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB16_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x30F00++0x3
line.long 0x0 "SMMU_CB16_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x30F04++0x3
line.long 0x0 "SMMU_CB16_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x30F20++0x3
line.long 0x0 "SMMU_CB16_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x30F40++0x13
line.long 0x0 "SMMU_CB16_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB16_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB16_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB16_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB16_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x30F58++0x3
line.long 0x0 "SMMU_CB16_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x30FB8++0x3
line.long 0x0 "smmu_cb16_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x31000++0x7
line.long 0x0 "SMMU_CB17_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB17_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x31008++0x3
line.long 0x0 "SMMU_CB17_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x31010++0x3
line.long 0x0 "SMMU_CB17_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x31020++0x1F
line.long 0x0 "SMMU_CB17_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB17_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB17_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB17_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB17_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB17_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB17_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB17_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x31058++0x7
line.long 0x0 "SMMU_CB17_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB17_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x31060++0xB
line.long 0x0 "SMMU_CB17_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB17_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB17_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x31070++0x7
line.long 0x0 "SMMU_CB17_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB17_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x31600++0x13
line.long 0x0 "SMMU_CB17_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB17_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB17_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB17_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB17_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x31618++0x3
line.long 0x0 "SMMU_CB17_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x31620++0x1F
line.long 0x0 "SMMU_CB17_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB17_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB17_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB17_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB17_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB17_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB17_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB17_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x317F0++0x3
line.long 0x0 "SMMU_CB17_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x317F4++0x3
line.long 0x0 "SMMU_CB17_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x31E00++0xF
line.long 0x0 "SMMU_CB17_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB17_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB17_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB17_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x31E80++0xF
line.long 0x0 "SMMU_CB17_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB17_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB17_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB17_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x31F00++0x3
line.long 0x0 "SMMU_CB17_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x31F04++0x3
line.long 0x0 "SMMU_CB17_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x31F20++0x3
line.long 0x0 "SMMU_CB17_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x31F40++0x13
line.long 0x0 "SMMU_CB17_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB17_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB17_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB17_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB17_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x31F58++0x3
line.long 0x0 "SMMU_CB17_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x31FB8++0x3
line.long 0x0 "smmu_cb17_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x32000++0x7
line.long 0x0 "SMMU_CB18_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB18_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x32008++0x3
line.long 0x0 "SMMU_CB18_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x32010++0x3
line.long 0x0 "SMMU_CB18_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x32020++0x1F
line.long 0x0 "SMMU_CB18_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB18_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB18_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB18_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB18_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB18_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB18_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB18_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x32058++0x7
line.long 0x0 "SMMU_CB18_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB18_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x32060++0xB
line.long 0x0 "SMMU_CB18_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB18_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB18_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x32070++0x7
line.long 0x0 "SMMU_CB18_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB18_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x32600++0x13
line.long 0x0 "SMMU_CB18_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB18_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB18_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB18_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB18_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x32618++0x3
line.long 0x0 "SMMU_CB18_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x32620++0x1F
line.long 0x0 "SMMU_CB18_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB18_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB18_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB18_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB18_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB18_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB18_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB18_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x327F0++0x3
line.long 0x0 "SMMU_CB18_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x327F4++0x3
line.long 0x0 "SMMU_CB18_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x32E00++0xF
line.long 0x0 "SMMU_CB18_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB18_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB18_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB18_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x32E80++0xF
line.long 0x0 "SMMU_CB18_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB18_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB18_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB18_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x32F00++0x3
line.long 0x0 "SMMU_CB18_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x32F04++0x3
line.long 0x0 "SMMU_CB18_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x32F20++0x3
line.long 0x0 "SMMU_CB18_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x32F40++0x13
line.long 0x0 "SMMU_CB18_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB18_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB18_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB18_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB18_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x32F58++0x3
line.long 0x0 "SMMU_CB18_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x32FB8++0x3
line.long 0x0 "smmu_cb18_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x33000++0x7
line.long 0x0 "SMMU_CB19_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB19_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x33008++0x3
line.long 0x0 "SMMU_CB19_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x33010++0x3
line.long 0x0 "SMMU_CB19_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x33020++0x1F
line.long 0x0 "SMMU_CB19_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB19_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB19_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB19_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB19_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB19_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB19_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB19_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x33058++0x7
line.long 0x0 "SMMU_CB19_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB19_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x33060++0xB
line.long 0x0 "SMMU_CB19_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB19_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB19_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x33070++0x7
line.long 0x0 "SMMU_CB19_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB19_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x33600++0x13
line.long 0x0 "SMMU_CB19_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB19_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB19_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB19_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB19_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x33618++0x3
line.long 0x0 "SMMU_CB19_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x33620++0x1F
line.long 0x0 "SMMU_CB19_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB19_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB19_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB19_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB19_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB19_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB19_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB19_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x337F0++0x3
line.long 0x0 "SMMU_CB19_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x337F4++0x3
line.long 0x0 "SMMU_CB19_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x33E00++0xF
line.long 0x0 "SMMU_CB19_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB19_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB19_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB19_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x33E80++0xF
line.long 0x0 "SMMU_CB19_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB19_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB19_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB19_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x33F00++0x3
line.long 0x0 "SMMU_CB19_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x33F04++0x3
line.long 0x0 "SMMU_CB19_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x33F20++0x3
line.long 0x0 "SMMU_CB19_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x33F40++0x13
line.long 0x0 "SMMU_CB19_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB19_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB19_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB19_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB19_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x33F58++0x3
line.long 0x0 "SMMU_CB19_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x33FB8++0x3
line.long 0x0 "smmu_cb19_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x34000++0x7
line.long 0x0 "SMMU_CB20_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB20_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x34008++0x3
line.long 0x0 "SMMU_CB20_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x34010++0x3
line.long 0x0 "SMMU_CB20_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x34020++0x1F
line.long 0x0 "SMMU_CB20_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB20_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB20_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB20_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB20_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB20_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB20_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB20_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x34058++0x7
line.long 0x0 "SMMU_CB20_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB20_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x34060++0xB
line.long 0x0 "SMMU_CB20_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB20_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB20_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x34070++0x7
line.long 0x0 "SMMU_CB20_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB20_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x34600++0x13
line.long 0x0 "SMMU_CB20_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB20_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB20_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB20_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB20_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x34618++0x3
line.long 0x0 "SMMU_CB20_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x34620++0x1F
line.long 0x0 "SMMU_CB20_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB20_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB20_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB20_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB20_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB20_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB20_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB20_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x347F0++0x3
line.long 0x0 "SMMU_CB20_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x347F4++0x3
line.long 0x0 "SMMU_CB20_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x34E00++0xF
line.long 0x0 "SMMU_CB20_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB20_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB20_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB20_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x34E80++0xF
line.long 0x0 "SMMU_CB20_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB20_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB20_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB20_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x34F00++0x3
line.long 0x0 "SMMU_CB20_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x34F04++0x3
line.long 0x0 "SMMU_CB20_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x34F20++0x3
line.long 0x0 "SMMU_CB20_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x34F40++0x13
line.long 0x0 "SMMU_CB20_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB20_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB20_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB20_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB20_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x34F58++0x3
line.long 0x0 "SMMU_CB20_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x34FB8++0x3
line.long 0x0 "smmu_cb20_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x35000++0x7
line.long 0x0 "SMMU_CB21_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB21_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x35008++0x3
line.long 0x0 "SMMU_CB21_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x35010++0x3
line.long 0x0 "SMMU_CB21_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x35020++0x1F
line.long 0x0 "SMMU_CB21_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB21_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB21_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB21_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB21_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB21_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB21_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB21_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x35058++0x7
line.long 0x0 "SMMU_CB21_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB21_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x35060++0xB
line.long 0x0 "SMMU_CB21_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB21_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB21_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x35070++0x7
line.long 0x0 "SMMU_CB21_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB21_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x35600++0x13
line.long 0x0 "SMMU_CB21_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB21_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB21_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB21_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB21_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x35618++0x3
line.long 0x0 "SMMU_CB21_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x35620++0x1F
line.long 0x0 "SMMU_CB21_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB21_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB21_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB21_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB21_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB21_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB21_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB21_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x357F0++0x3
line.long 0x0 "SMMU_CB21_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x357F4++0x3
line.long 0x0 "SMMU_CB21_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x35E00++0xF
line.long 0x0 "SMMU_CB21_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB21_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB21_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB21_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x35E80++0xF
line.long 0x0 "SMMU_CB21_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB21_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB21_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB21_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x35F00++0x3
line.long 0x0 "SMMU_CB21_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x35F04++0x3
line.long 0x0 "SMMU_CB21_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x35F20++0x3
line.long 0x0 "SMMU_CB21_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x35F40++0x13
line.long 0x0 "SMMU_CB21_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB21_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB21_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB21_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB21_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x35F58++0x3
line.long 0x0 "SMMU_CB21_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x35FB8++0x3
line.long 0x0 "smmu_cb21_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x36000++0x7
line.long 0x0 "SMMU_CB22_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB22_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x36008++0x3
line.long 0x0 "SMMU_CB22_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x36010++0x3
line.long 0x0 "SMMU_CB22_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x36020++0x1F
line.long 0x0 "SMMU_CB22_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB22_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB22_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB22_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB22_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB22_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB22_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB22_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x36058++0x7
line.long 0x0 "SMMU_CB22_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB22_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x36060++0xB
line.long 0x0 "SMMU_CB22_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB22_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB22_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x36070++0x7
line.long 0x0 "SMMU_CB22_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB22_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x36600++0x13
line.long 0x0 "SMMU_CB22_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB22_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB22_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB22_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB22_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x36618++0x3
line.long 0x0 "SMMU_CB22_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x36620++0x1F
line.long 0x0 "SMMU_CB22_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB22_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB22_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB22_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB22_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB22_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB22_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB22_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x367F0++0x3
line.long 0x0 "SMMU_CB22_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x367F4++0x3
line.long 0x0 "SMMU_CB22_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x36E00++0xF
line.long 0x0 "SMMU_CB22_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB22_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB22_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB22_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x36E80++0xF
line.long 0x0 "SMMU_CB22_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB22_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB22_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB22_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x36F00++0x3
line.long 0x0 "SMMU_CB22_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x36F04++0x3
line.long 0x0 "SMMU_CB22_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x36F20++0x3
line.long 0x0 "SMMU_CB22_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x36F40++0x13
line.long 0x0 "SMMU_CB22_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB22_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB22_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB22_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB22_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x36F58++0x3
line.long 0x0 "SMMU_CB22_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x36FB8++0x3
line.long 0x0 "smmu_cb22_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x37000++0x7
line.long 0x0 "SMMU_CB23_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB23_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x37008++0x3
line.long 0x0 "SMMU_CB23_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x37010++0x3
line.long 0x0 "SMMU_CB23_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x37020++0x1F
line.long 0x0 "SMMU_CB23_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB23_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB23_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB23_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB23_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB23_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB23_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB23_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x37058++0x7
line.long 0x0 "SMMU_CB23_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB23_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x37060++0xB
line.long 0x0 "SMMU_CB23_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB23_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB23_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x37070++0x7
line.long 0x0 "SMMU_CB23_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB23_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x37600++0x13
line.long 0x0 "SMMU_CB23_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB23_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB23_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB23_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB23_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x37618++0x3
line.long 0x0 "SMMU_CB23_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x37620++0x1F
line.long 0x0 "SMMU_CB23_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB23_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB23_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB23_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB23_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB23_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB23_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB23_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x377F0++0x3
line.long 0x0 "SMMU_CB23_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x377F4++0x3
line.long 0x0 "SMMU_CB23_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x37E00++0xF
line.long 0x0 "SMMU_CB23_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB23_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB23_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB23_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x37E80++0xF
line.long 0x0 "SMMU_CB23_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB23_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB23_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB23_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x37F00++0x3
line.long 0x0 "SMMU_CB23_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x37F04++0x3
line.long 0x0 "SMMU_CB23_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x37F20++0x3
line.long 0x0 "SMMU_CB23_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x37F40++0x13
line.long 0x0 "SMMU_CB23_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB23_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB23_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB23_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB23_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x37F58++0x3
line.long 0x0 "SMMU_CB23_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x37FB8++0x3
line.long 0x0 "smmu_cb23_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x38000++0x7
line.long 0x0 "SMMU_CB24_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB24_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x38008++0x3
line.long 0x0 "SMMU_CB24_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x38010++0x3
line.long 0x0 "SMMU_CB24_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x38020++0x1F
line.long 0x0 "SMMU_CB24_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB24_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB24_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB24_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB24_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB24_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB24_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB24_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x38058++0x7
line.long 0x0 "SMMU_CB24_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB24_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x38060++0xB
line.long 0x0 "SMMU_CB24_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB24_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB24_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x38070++0x7
line.long 0x0 "SMMU_CB24_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB24_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x38600++0x13
line.long 0x0 "SMMU_CB24_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB24_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB24_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB24_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB24_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x38618++0x3
line.long 0x0 "SMMU_CB24_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x38620++0x1F
line.long 0x0 "SMMU_CB24_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB24_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB24_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB24_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB24_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB24_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB24_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB24_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x387F0++0x3
line.long 0x0 "SMMU_CB24_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x387F4++0x3
line.long 0x0 "SMMU_CB24_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x38E00++0xF
line.long 0x0 "SMMU_CB24_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB24_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB24_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB24_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x38E80++0xF
line.long 0x0 "SMMU_CB24_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB24_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB24_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB24_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x38F00++0x3
line.long 0x0 "SMMU_CB24_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x38F04++0x3
line.long 0x0 "SMMU_CB24_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x38F20++0x3
line.long 0x0 "SMMU_CB24_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x38F40++0x13
line.long 0x0 "SMMU_CB24_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB24_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB24_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB24_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB24_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x38F58++0x3
line.long 0x0 "SMMU_CB24_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x38FB8++0x3
line.long 0x0 "smmu_cb24_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x39000++0x7
line.long 0x0 "SMMU_CB25_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB25_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x39008++0x3
line.long 0x0 "SMMU_CB25_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x39010++0x3
line.long 0x0 "SMMU_CB25_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x39020++0x1F
line.long 0x0 "SMMU_CB25_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB25_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB25_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB25_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB25_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB25_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB25_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB25_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x39058++0x7
line.long 0x0 "SMMU_CB25_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB25_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x39060++0xB
line.long 0x0 "SMMU_CB25_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB25_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB25_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x39070++0x7
line.long 0x0 "SMMU_CB25_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB25_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x39600++0x13
line.long 0x0 "SMMU_CB25_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB25_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB25_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB25_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB25_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x39618++0x3
line.long 0x0 "SMMU_CB25_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x39620++0x1F
line.long 0x0 "SMMU_CB25_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB25_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB25_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB25_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB25_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB25_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB25_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB25_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x397F0++0x3
line.long 0x0 "SMMU_CB25_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x397F4++0x3
line.long 0x0 "SMMU_CB25_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x39E00++0xF
line.long 0x0 "SMMU_CB25_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB25_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB25_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB25_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x39E80++0xF
line.long 0x0 "SMMU_CB25_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB25_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB25_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB25_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x39F00++0x3
line.long 0x0 "SMMU_CB25_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x39F04++0x3
line.long 0x0 "SMMU_CB25_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x39F20++0x3
line.long 0x0 "SMMU_CB25_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x39F40++0x13
line.long 0x0 "SMMU_CB25_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB25_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB25_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB25_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB25_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x39F58++0x3
line.long 0x0 "SMMU_CB25_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x39FB8++0x3
line.long 0x0 "smmu_cb25_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x3A000++0x7
line.long 0x0 "SMMU_CB26_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB26_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x3A008++0x3
line.long 0x0 "SMMU_CB26_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x3A010++0x3
line.long 0x0 "SMMU_CB26_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x3A020++0x1F
line.long 0x0 "SMMU_CB26_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB26_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB26_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB26_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB26_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB26_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB26_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB26_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x3A058++0x7
line.long 0x0 "SMMU_CB26_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB26_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x3A060++0xB
line.long 0x0 "SMMU_CB26_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB26_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB26_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x3A070++0x7
line.long 0x0 "SMMU_CB26_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB26_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x3A600++0x13
line.long 0x0 "SMMU_CB26_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB26_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB26_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB26_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB26_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x3A618++0x3
line.long 0x0 "SMMU_CB26_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x3A620++0x1F
line.long 0x0 "SMMU_CB26_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB26_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB26_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB26_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB26_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB26_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB26_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB26_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x3A7F0++0x3
line.long 0x0 "SMMU_CB26_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x3A7F4++0x3
line.long 0x0 "SMMU_CB26_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x3AE00++0xF
line.long 0x0 "SMMU_CB26_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB26_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB26_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB26_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x3AE80++0xF
line.long 0x0 "SMMU_CB26_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB26_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB26_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB26_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x3AF00++0x3
line.long 0x0 "SMMU_CB26_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x3AF04++0x3
line.long 0x0 "SMMU_CB26_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x3AF20++0x3
line.long 0x0 "SMMU_CB26_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x3AF40++0x13
line.long 0x0 "SMMU_CB26_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB26_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB26_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB26_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB26_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x3AF58++0x3
line.long 0x0 "SMMU_CB26_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x3AFB8++0x3
line.long 0x0 "smmu_cb26_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x3B000++0x7
line.long 0x0 "SMMU_CB27_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB27_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x3B008++0x3
line.long 0x0 "SMMU_CB27_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x3B010++0x3
line.long 0x0 "SMMU_CB27_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x3B020++0x1F
line.long 0x0 "SMMU_CB27_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB27_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB27_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB27_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB27_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB27_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB27_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB27_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x3B058++0x7
line.long 0x0 "SMMU_CB27_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB27_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x3B060++0xB
line.long 0x0 "SMMU_CB27_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB27_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB27_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x3B070++0x7
line.long 0x0 "SMMU_CB27_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB27_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x3B600++0x13
line.long 0x0 "SMMU_CB27_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB27_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB27_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB27_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB27_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x3B618++0x3
line.long 0x0 "SMMU_CB27_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x3B620++0x1F
line.long 0x0 "SMMU_CB27_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB27_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB27_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB27_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB27_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB27_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB27_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB27_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x3B7F0++0x3
line.long 0x0 "SMMU_CB27_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x3B7F4++0x3
line.long 0x0 "SMMU_CB27_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x3BE00++0xF
line.long 0x0 "SMMU_CB27_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB27_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB27_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB27_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x3BE80++0xF
line.long 0x0 "SMMU_CB27_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB27_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB27_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB27_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x3BF00++0x3
line.long 0x0 "SMMU_CB27_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x3BF04++0x3
line.long 0x0 "SMMU_CB27_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x3BF20++0x3
line.long 0x0 "SMMU_CB27_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x3BF40++0x13
line.long 0x0 "SMMU_CB27_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB27_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB27_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB27_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB27_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x3BF58++0x3
line.long 0x0 "SMMU_CB27_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x3BFB8++0x3
line.long 0x0 "smmu_cb27_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x3C000++0x7
line.long 0x0 "SMMU_CB28_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB28_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x3C008++0x3
line.long 0x0 "SMMU_CB28_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x3C010++0x3
line.long 0x0 "SMMU_CB28_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x3C020++0x1F
line.long 0x0 "SMMU_CB28_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB28_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB28_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB28_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB28_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB28_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB28_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB28_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x3C058++0x7
line.long 0x0 "SMMU_CB28_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB28_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x3C060++0xB
line.long 0x0 "SMMU_CB28_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB28_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB28_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x3C070++0x7
line.long 0x0 "SMMU_CB28_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB28_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x3C600++0x13
line.long 0x0 "SMMU_CB28_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB28_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB28_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB28_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB28_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x3C618++0x3
line.long 0x0 "SMMU_CB28_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x3C620++0x1F
line.long 0x0 "SMMU_CB28_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB28_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB28_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB28_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB28_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB28_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB28_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB28_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x3C7F0++0x3
line.long 0x0 "SMMU_CB28_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x3C7F4++0x3
line.long 0x0 "SMMU_CB28_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x3CE00++0xF
line.long 0x0 "SMMU_CB28_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB28_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB28_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB28_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x3CE80++0xF
line.long 0x0 "SMMU_CB28_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB28_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB28_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB28_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x3CF00++0x3
line.long 0x0 "SMMU_CB28_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x3CF04++0x3
line.long 0x0 "SMMU_CB28_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x3CF20++0x3
line.long 0x0 "SMMU_CB28_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x3CF40++0x13
line.long 0x0 "SMMU_CB28_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB28_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB28_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB28_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB28_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x3CF58++0x3
line.long 0x0 "SMMU_CB28_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x3CFB8++0x3
line.long 0x0 "smmu_cb28_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x3D000++0x7
line.long 0x0 "SMMU_CB29_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB29_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x3D008++0x3
line.long 0x0 "SMMU_CB29_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x3D010++0x3
line.long 0x0 "SMMU_CB29_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x3D020++0x1F
line.long 0x0 "SMMU_CB29_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB29_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB29_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB29_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB29_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB29_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB29_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB29_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x3D058++0x7
line.long 0x0 "SMMU_CB29_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB29_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x3D060++0xB
line.long 0x0 "SMMU_CB29_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB29_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB29_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x3D070++0x7
line.long 0x0 "SMMU_CB29_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB29_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x3D600++0x13
line.long 0x0 "SMMU_CB29_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB29_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB29_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB29_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB29_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x3D618++0x3
line.long 0x0 "SMMU_CB29_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x3D620++0x1F
line.long 0x0 "SMMU_CB29_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB29_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB29_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB29_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB29_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB29_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB29_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB29_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x3D7F0++0x3
line.long 0x0 "SMMU_CB29_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x3D7F4++0x3
line.long 0x0 "SMMU_CB29_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x3DE00++0xF
line.long 0x0 "SMMU_CB29_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB29_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB29_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB29_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x3DE80++0xF
line.long 0x0 "SMMU_CB29_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB29_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB29_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB29_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x3DF00++0x3
line.long 0x0 "SMMU_CB29_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x3DF04++0x3
line.long 0x0 "SMMU_CB29_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x3DF20++0x3
line.long 0x0 "SMMU_CB29_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x3DF40++0x13
line.long 0x0 "SMMU_CB29_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB29_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB29_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB29_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB29_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x3DF58++0x3
line.long 0x0 "SMMU_CB29_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x3DFB8++0x3
line.long 0x0 "smmu_cb29_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x3E000++0x7
line.long 0x0 "SMMU_CB30_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB30_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x3E008++0x3
line.long 0x0 "SMMU_CB30_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x3E010++0x3
line.long 0x0 "SMMU_CB30_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x3E020++0x1F
line.long 0x0 "SMMU_CB30_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB30_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB30_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB30_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB30_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB30_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB30_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB30_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x3E058++0x7
line.long 0x0 "SMMU_CB30_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB30_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x3E060++0xB
line.long 0x0 "SMMU_CB30_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB30_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB30_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x3E070++0x7
line.long 0x0 "SMMU_CB30_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB30_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x3E600++0x13
line.long 0x0 "SMMU_CB30_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB30_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB30_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB30_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB30_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x3E618++0x3
line.long 0x0 "SMMU_CB30_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x3E620++0x1F
line.long 0x0 "SMMU_CB30_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB30_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB30_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB30_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB30_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB30_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB30_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB30_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x3E7F0++0x3
line.long 0x0 "SMMU_CB30_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x3E7F4++0x3
line.long 0x0 "SMMU_CB30_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x3EE00++0xF
line.long 0x0 "SMMU_CB30_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB30_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB30_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB30_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x3EE80++0xF
line.long 0x0 "SMMU_CB30_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB30_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB30_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB30_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x3EF00++0x3
line.long 0x0 "SMMU_CB30_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x3EF04++0x3
line.long 0x0 "SMMU_CB30_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x3EF20++0x3
line.long 0x0 "SMMU_CB30_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x3EF40++0x13
line.long 0x0 "SMMU_CB30_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB30_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB30_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB30_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB30_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x3EF58++0x3
line.long 0x0 "SMMU_CB30_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x3EFB8++0x3
line.long 0x0 "smmu_cb30_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
group.long 0x3F000++0x7
line.long 0x0 "SMMU_CB31_SCTLR,The System Control register provides the top level control of the translation system for the related Context bank."
bitfld.long 0x0 28.--29. "NSCFG," "0,1,2,3"
bitfld.long 0x0 26.--27. "WACFG," "0,1,2,3"
bitfld.long 0x0 24.--25. "RACFG," "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "SHCFG," "0,1,2,3"
bitfld.long 0x0 21. "FB," "0,1"
bitfld.long 0x0 20. "MTCFG," "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "MemAttr,"
bitfld.long 0x0 14.--15. "TRANSIENTCFG," "0,1,2,3"
bitfld.long 0x0 13. "PTW," "0,1"
newline
rbitfld.long 0x0 12. "ASIDPNE," "0,1"
bitfld.long 0x0 10. "UWXN," "0,1"
bitfld.long 0x0 9. "WXN," "0,1"
newline
bitfld.long 0x0 8. "HUPCF," "0,1"
bitfld.long 0x0 7. "CFCFG," "0,1"
bitfld.long 0x0 6. "CFIE," "0,1"
newline
bitfld.long 0x0 5. "CFRE," "0,1"
bitfld.long 0x0 4. "E," "0,1"
bitfld.long 0x0 3. "AFFD," "0,1"
newline
bitfld.long 0x0 2. "AFE," "0,1"
bitfld.long 0x0 1. "TRE," "0,1"
bitfld.long 0x0 0. "M," "0,1"
line.long 0x4 "SMMU_CB31_ACTLR,The Auxillary Control register provides implementation specific configuration and control options."
bitfld.long 0x4 1. "CPRE," "0,1"
bitfld.long 0x4 0. "CMTLB," "0,1"
wgroup.long 0x3F008++0x3
line.long 0x0 "SMMU_CB31_RESUME,The Transaction Resume is used to resume operation of a transaction that is stalled because of an existing fault condition."
bitfld.long 0x0 0. "TnR," "0,1"
group.long 0x3F010++0x3
line.long 0x0 "SMMU_CB31_TCR2,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x0 30. "NSCFG1," "0,1"
bitfld.long 0x0 15.--17. "SEP," "0,1,2,3,4,5,6,7"
bitfld.long 0x0 14. "NSCFG0," "0,1"
newline
rbitfld.long 0x0 6. "TBI1," "0,1"
rbitfld.long 0x0 5. "TBI0," "0,1"
bitfld.long 0x0 4. "AS," "0,1"
newline
bitfld.long 0x0 0.--2. "PASize," "0,1,2,3,4,5,6,7"
group.long 0x3F020++0x1F
line.long 0x0 "SMMU_CB31_TTBR0_low,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long 0x0 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x0 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x0 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x0 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
rbitfld.long 0x0 2. "ADDRESS_2," "0,1"
bitfld.long 0x0 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x0 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0x4 "SMMU_CB31_TTBR0_high,The Translation Table Base register 0 holds the base address of the translation table 0."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.word 0x4 0.--15. 1. "address,"
line.long 0x8 "SMMU_CB31_TTBR1_low,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long 0x8 7.--31. 1. "ADDRESS_31_7,"
bitfld.long 0x8 6. "ADDRESS_6_IRGN0," "0,1"
bitfld.long 0x8 5. "ADDRESS_5_NOS," "0,1"
newline
bitfld.long 0x8 3.--4. "ADDRESS_4_3_RGN," "0,1,2,3"
bitfld.long 0x8 2. "ADDRESS_2," "0,1"
bitfld.long 0x8 1. "ADDRESS_1_S," "0,1"
newline
bitfld.long 0x8 0. "ADDRESS_0_IRGN1," "0,1"
line.long 0xC "SMMU_CB31_TTBR1_high,The Translation Table Base register 0 holds the base address of the translation table 1."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.word 0xC 0.--15. 1. "address,"
line.long 0x10 "SMMU_CB31_TCR_lpae,The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB."
bitfld.long 0x10 31. "EAE," "0,1"
bitfld.long 0x10 30. "NSCFG1_TG1," "0,1"
bitfld.long 0x10 28.--29. "SH1," "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ORGN1," "0,1,2,3"
bitfld.long 0x10 24.--25. "IRGN1," "0,1,2,3"
bitfld.long 0x10 23. "EPD1," "0,1"
newline
bitfld.long 0x10 22. "A1," "0,1"
bitfld.long 0x10 19.--21. "T1SZ_5_3," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--18. "T1SZ_2_0_PASIZE," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 14. "NSCFG0_TG0," "0,1"
bitfld.long 0x10 12.--13. "SH0," "0,1,2,3"
bitfld.long 0x10 10.--11. "ORGN0," "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "IRGN0," "0,1,2,3"
bitfld.long 0x10 7. "SL0_1_EPD0," "0,1"
bitfld.long 0x10 6. "SL0_0," "0,1"
newline
bitfld.long 0x10 5. "PD1_T0SZ_5," "0,1"
bitfld.long 0x10 4. "S_PD0_T0SZ_4," "0,1"
hexmask.long.byte 0x10 0.--3. 1. "T0SZ_3_0,"
line.long 0x14 "SMMU_CB31_CONTEXTIDR,Identifies the current process identifier and the current address space identifier"
hexmask.long.tbyte 0x14 8.--31. 1. "PROCID,"
hexmask.long.byte 0x14 0.--7. 1. "ASID,"
line.long 0x18 "SMMU_CB31_PRRR_MAIR0,Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX. C. and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or.."
bitfld.long 0x18 31. "NOS7," "0,1"
bitfld.long 0x18 30. "NOS6," "0,1"
bitfld.long 0x18 29. "NOS5," "0,1"
newline
bitfld.long 0x18 28. "NOS4," "0,1"
bitfld.long 0x18 27. "NOS3," "0,1"
bitfld.long 0x18 26. "NOS2," "0,1"
newline
bitfld.long 0x18 25. "NOS1," "0,1"
bitfld.long 0x18 24. "NOS0," "0,1"
bitfld.long 0x18 19. "NS1," "0,1"
newline
bitfld.long 0x18 18. "NS0," "0,1"
bitfld.long 0x18 17. "DS1," "0,1"
bitfld.long 0x18 16. "DS0," "0,1"
newline
bitfld.long 0x18 14.--15. "TR7," "0,1,2,3"
bitfld.long 0x18 12.--13. "TR6," "0,1,2,3"
bitfld.long 0x18 10.--11. "TR5," "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "TR4," "0,1,2,3"
bitfld.long 0x18 6.--7. "TR3," "0,1,2,3"
bitfld.long 0x18 4.--5. "TR2," "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "TR1," "0,1,2,3"
bitfld.long 0x18 0.--1. "TR0," "0,1,2,3"
line.long 0x1C "SMMU_CB31_NMRR_MAIR1,Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection.."
bitfld.long 0x1C 30.--31. "OR7," "0,1,2,3"
bitfld.long 0x1C 28.--29. "OR6," "0,1,2,3"
bitfld.long 0x1C 26.--27. "OR5," "0,1,2,3"
newline
bitfld.long 0x1C 24.--25. "OR4," "0,1,2,3"
bitfld.long 0x1C 22.--23. "OR3," "0,1,2,3"
bitfld.long 0x1C 20.--21. "OR2," "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "OR1," "0,1,2,3"
bitfld.long 0x1C 16.--17. "OR0," "0,1,2,3"
bitfld.long 0x1C 14.--15. "IR7," "0,1,2,3"
newline
bitfld.long 0x1C 12.--13. "IR6," "0,1,2,3"
bitfld.long 0x1C 10.--11. "IR5," "0,1,2,3"
bitfld.long 0x1C 8.--9. "IR4," "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "IR3," "0,1,2,3"
bitfld.long 0x1C 4.--5. "IR2," "0,1,2,3"
bitfld.long 0x1C 2.--3. "IR1," "0,1,2,3"
newline
bitfld.long 0x1C 0.--1. "IR0," "0,1,2,3"
wgroup.long 0x3F058++0x7
line.long 0x0 "SMMU_CB31_FSR,Provides memory system fault status information."
bitfld.long 0x0 31. "MULTI," "0,1"
bitfld.long 0x0 30. "SS," "0,1"
bitfld.long 0x0 9.--10. "Format," "0,1,2,3"
newline
bitfld.long 0x0 8. "UUT," "0,1"
bitfld.long 0x0 7. "ASF," "0,1"
bitfld.long 0x0 6. "TLBLKF," "0,1"
newline
bitfld.long 0x0 5. "TLBMCF," "0,1"
bitfld.long 0x0 4. "EF," "0,1"
bitfld.long 0x0 3. "PF," "0,1"
newline
bitfld.long 0x0 2. "AFF," "0,1"
bitfld.long 0x0 1. "TF," "0,1"
line.long 0x4 "SMMU_CB31_FSRRESTORE,Restores the state of SMMU_CBn_FSR. after a reset. for example."
hexmask.long 0x4 0.--31. 1. "bits,"
group.long 0x3F060++0xB
line.long 0x0 "SMMU_CB31_FAR_low,Holds the Lower input address bits [31:0] of the memory access that caused a synchronous abort exception."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB31_FAR_high,Holds the Upper input address bits [63:32] of the memory access that caused a synchronous abort exception."
hexmask.long.tbyte 0x4 0.--16. 1. "bits,"
line.long 0x8 "SMMU_CB31_FSYNR0,Holds fault syndrome information about the memory access that caused a synchronous abort exception"
hexmask.long.byte 0x8 16.--20. 1. "S1CBNDX,"
bitfld.long 0x8 11. "AFR," "0,1"
bitfld.long 0x8 10. "PTWF," "0,1"
newline
rbitfld.long 0x8 9. "ATOF," "0,1"
bitfld.long 0x8 8. "NSATTR," "0,1"
bitfld.long 0x8 6. "IND," "0,1"
newline
bitfld.long 0x8 5. "PNU," "0,1"
bitfld.long 0x8 4. "WNR," "0,1"
bitfld.long 0x8 0.--1. "PLVL," "0,1,2,3"
group.long 0x3F070++0x7
line.long 0x0 "SMMU_CB31_IPAFAR_low,The stage 1 IPA Fault Address Lower bits [31:0] Register."
hexmask.long.tbyte 0x0 12.--31. 1. "ipafar_l,"
hexmask.long.word 0x0 0.--11. 1. "far_ro,"
line.long 0x4 "SMMU_CB31_IPAFAR_high,The stage 1 IPA Fault Address Upper bits [63:32] Register"
hexmask.long.word 0x4 0.--15. 1. "bits,"
wgroup.long 0x3F600++0x13
line.long 0x0 "SMMU_CB31_TLBIVA_low,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB31_TLBIVA_high,Invalidates all of the unlocked TLB entries that match both the VA provided and the TLB tagging scheme of the context bank. including any global entries if appropriate"
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB31_TLBIVAA_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB31_TLBIVAA_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB31_TLBIASID,Invalidates all of the unlocked TLB entries that match the ASID provided as an argument"
hexmask.long.word 0x10 0.--15. 1. "ASID,"
wgroup.long 0x3F618++0x3
line.long 0x0 "SMMU_CB31_TLBIALL,Invalidates all of the unlocked TLB entries that are tagged as: i) Hypervisor. for HYPC banks. ii)Non-secure. using the VMID of the context bank. for Non-secure. non-HYPC context banks.iii) Secure. using any ASID. for Secure context.."
hexmask.long 0x0 0.--31. 1. "bits,"
wgroup.long 0x3F620++0x1F
line.long 0x0 "SMMU_CB31_TLBIVAL_low,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long 0x0 0.--31. 1. "Address,"
line.long 0x4 "SMMU_CB31_TLBIVAL_high,Invalidates all of the unlocked TLB entries that match the VA and ASID provided as arguments. and the VMID of the context bank. This register is similar to SMMU_CBn_TLBIVA. but it is only required to invalidate cached copies of the.."
hexmask.long.word 0x4 16.--31. 1. "ASID,"
hexmask.long.byte 0x4 0.--4. 1. "Address,"
line.long 0x8 "SMMU_CB31_TLBIVAAL_low,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long 0x8 0.--31. 1. "Address,"
line.long 0xC "SMMU_CB31_TLBIVAAL_high,Invalidates all of the unlocked TLB entries that match the VA provided as an argument. and the VMID of the context bank. regardless of the ASID. This operation includes global entries if appropriate.This register is similar to.."
hexmask.long.word 0xC 16.--31. 1. "ASID,"
hexmask.long.byte 0xC 0.--4. 1. "Address,"
line.long 0x10 "SMMU_CB31_TLBIIPAS2_low,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long 0x10 0.--31. 1. "Address,"
line.long 0x14 "SMMU_CB31_TLBIIPAS2_high,Invalidates all unlocked TLB entries that match the IPA provided"
hexmask.long.byte 0x14 0.--3. 1. "Address,"
line.long 0x18 "SMMU_CB31_TLBIIPAS2L_low,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long 0x18 0.--31. 1. "Address,"
line.long 0x1C "SMMU_CB31_TLBIIPAS2L_high,Invalidates any unlocked TLB entries that match the IPA provided and that correspond to the final level of translation table lookup"
hexmask.long.byte 0x1C 0.--3. 1. "Address,"
wgroup.long 0x3F7F0++0x3
line.long 0x0 "SMMU_CB31_TLBSYNC,Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank."
hexmask.long 0x0 0.--31. 1. "bits,"
rgroup.long 0x3F7F4++0x3
line.long 0x0 "SMMU_CB31_TLBSTATUS,Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation"
bitfld.long 0x0 0. "SACTIVE," "0,1"
group.long 0x3FE00++0xF
line.long 0x0 "SMMU_CB31_PMEVCNTR0,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x0 0.--31. 1. "bits,"
line.long 0x4 "SMMU_CB31_PMEVCNTR1,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x4 0.--31. 1. "bits,"
line.long 0x8 "SMMU_CB31_PMEVCNTR2,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0x8 0.--31. 1. "bits,"
line.long 0xC "SMMU_CB31_PMEVCNTR3,Provides event counter resources in the register map of a translation context bank. Reads or writes the value of the selected event counter."
hexmask.long 0xC 0.--31. 1. "bits,"
group.long 0x3FE80++0xF
line.long 0x0 "SMMU_CB31_PMEVTYPER0,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x0 31. "P," "0,1"
bitfld.long 0x0 30. "U," "0,1"
bitfld.long 0x0 29. "NSP," "0,1"
newline
bitfld.long 0x0 28. "NSU," "0,1"
hexmask.long.byte 0x0 0.--4. 1. "EVENT,"
line.long 0x4 "SMMU_CB31_PMEVTYPER1,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x4 31. "P," "0,1"
bitfld.long 0x4 30. "U," "0,1"
bitfld.long 0x4 29. "NSP," "0,1"
newline
bitfld.long 0x4 28. "NSU," "0,1"
hexmask.long.byte 0x4 0.--4. 1. "EVENT,"
line.long 0x8 "SMMU_CB31_PMEVTYPER2,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0x8 31. "P," "0,1"
bitfld.long 0x8 30. "U," "0,1"
bitfld.long 0x8 29. "NSP," "0,1"
newline
bitfld.long 0x8 28. "NSU," "0,1"
hexmask.long.byte 0x8 0.--4. 1. "EVENT,"
line.long 0xC "SMMU_CB31_PMEVTYPER3,Provides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter"
bitfld.long 0xC 31. "P," "0,1"
bitfld.long 0xC 30. "U," "0,1"
bitfld.long 0xC 29. "NSP," "0,1"
newline
bitfld.long 0xC 28. "NSU," "0,1"
hexmask.long.byte 0xC 0.--4. 1. "EVENT,"
rgroup.long 0x3FF00++0x3
line.long 0x0 "SMMU_CB31_PMCFGR,Provides a performance monitoring configuration register in the register map of a translation context bank. Provides Performance Monitoring Unit (PMU) configuration data."
hexmask.long.byte 0x0 24.--31. 1. "NCG,"
bitfld.long 0x0 19. "UEN," "0,1"
bitfld.long 0x0 16. "EX," "0,1"
newline
bitfld.long 0x0 15. "CCD," "0,1"
bitfld.long 0x0 14. "CC," "0,1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,"
newline
hexmask.long.byte 0x0 0.--7. 1. "N,"
group.long 0x3FF04++0x3
line.long 0x0 "SMMU_CB31_PMCR,Provides the equivalent of the PMCR register. in the register map of a translation context bank. PMCR provides controls for the Performance Monitors."
hexmask.long.byte 0x0 24.--31. 1. "IMP,"
bitfld.long 0x0 4. "X," "0,1"
rbitfld.long 0x0 1. "P," "0,1"
newline
bitfld.long 0x0 0. "E," "0,1"
rgroup.long 0x3FF20++0x3
line.long 0x0 "SMMU_CB31_PMCEID,Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register. in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation."
bitfld.long 0x0 17. "Event0x12," "0,1"
bitfld.long 0x0 16. "Event0x11," "0,1"
bitfld.long 0x0 15. "Event0x10," "0,1"
newline
bitfld.long 0x0 9. "Event0x0A," "0,1"
bitfld.long 0x0 8. "Event0x09," "0,1"
bitfld.long 0x0 7. "Event0x08," "0,1"
newline
bitfld.long 0x0 1. "Event0x01," "0,1"
bitfld.long 0x0 0. "Event0x00," "0,1"
wgroup.long 0x3FF40++0x13
line.long 0x0 "SMMU_CB31_PMCNTENSE,Provides the equivalent of the PMCNTENSETx register. in the register map of a translation context bank. Enables any implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
line.long 0x4 "SMMU_CB31_PMCNTENCLR,Provides the equivalent of the PMCNTENCLRx register. in the register map of a translation context bank. Disables any implemented event counter."
bitfld.long 0x4 3. "P3," "0,1"
bitfld.long 0x4 2. "P2," "0,1"
bitfld.long 0x4 1. "P1," "0,1"
newline
bitfld.long 0x4 0. "P0," "0,1"
line.long 0x8 "SMMU_CB31_PMCNTENSET,Provides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter"
bitfld.long 0x8 3. "P3," "0,1"
bitfld.long 0x8 2. "P2," "0,1"
bitfld.long 0x8 1. "P1," "0,1"
newline
bitfld.long 0x8 0. "P0," "0,1"
line.long 0xC "SMMU_CB31_PMINTENCLR,Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter."
bitfld.long 0xC 3. "P3," "0,1"
bitfld.long 0xC 2. "P2," "0,1"
bitfld.long 0xC 1. "P1," "0,1"
newline
bitfld.long 0xC 0. "P0," "0,1"
line.long 0x10 "SMMU_CB31_PMOVSCLR,Provides the equivalent of the PMOVSCLRx register. in the register map of a translation context bank. Clears the state of the overflow bit for each implemented event counter."
bitfld.long 0x10 3. "P3," "0,1"
bitfld.long 0x10 2. "P2," "0,1"
bitfld.long 0x10 1. "P1," "0,1"
newline
bitfld.long 0x10 0. "P0," "0,1"
wgroup.long 0x3FF58++0x3
line.long 0x0 "SMMU_CB31_PMOVSSET,Provides the equivalent of PMOVSSETx. in the register map of a translation context bank. Sets the state of the overflow bit for each of the implemented event counters."
bitfld.long 0x0 3. "P3," "0,1"
bitfld.long 0x0 2. "P2," "0,1"
bitfld.long 0x0 1. "P1," "0,1"
newline
bitfld.long 0x0 0. "P0," "0,1"
rgroup.long 0x3FFB8++0x3
line.long 0x0 "smmu_cb31_pmauthstatus,Provides the equivalent of the PMAUTHSTATUS register. in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug.."
bitfld.long 0x0 7. "SNI," "0,1"
bitfld.long 0x0 6. "SNE," "0,1"
bitfld.long 0x0 5. "SI," "0,1"
newline
bitfld.long 0x0 4. "SE," "0,1"
bitfld.long 0x0 3. "NSNI," "0,1"
bitfld.long 0x0 2. "NSNE," "0,1"
newline
bitfld.long 0x0 1. "NSI," "0,1"
bitfld.long 0x0 0. "NSE," "0,1"
tree.end
tree "UART (Universal Asynchronous Receiver Transmitter)"
base ad:0x0
tree "UART0 (UART0 Module)"
base ad:0xFFC02000
rgroup.long 0x0++0x3
line.long 0x0 "RBR,Receive Buffer Register. reading this register when the DLAB bit is zero;"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_RBR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "rbr,Receive Buffer Register:"
group.long 0x0++0x3
line.long 0x0 "DLL,Receive Buffer Register. reading this register when the DLAB bit is zero;"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_DLL_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "dll,Divisor Latch (Low):"
group.long 0x0++0x7
line.long 0x0 "THR,Receive Buffer Register. reading this register when the DLAB bit is zero;"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_THR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "thr,Transmit Holding Register:"
line.long 0x4 "IER,Interrupt Enable Register:"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IER_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x4 7. "PTIME,Interrupt Enable Register: PTIME  Programmable THRE Interrupt Mode Enable." "0: disabled,1: enabled"
newline
rbitfld.long 0x4 4.--6. "RSVD_IER_6to4,Reserved bits [6:4] - Read Only" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "EDSSI,Interrupt Enable Register: EDSSI  Enable Modem Status Interrupt." "0: disabled,1: enabled"
newline
bitfld.long 0x4 2. "ELSI,Interrupt Enable Register: ELSI  Enable Receiver Line Status Interrupt." "0: disabled,1: enabled"
bitfld.long 0x4 1. "ETBEI,Interrupt Enable Register: ETBEI  Enable Transmit Holding Register Empty Interrupt." "0: disabled,1: enabled"
newline
bitfld.long 0x4 0. "ERBFI,Interrupt Enable Register: ERBFI  Enable Received Data Available Interrupt." "0: disabled,1: enabled"
group.long 0x4++0x3
line.long 0x0 "DLH,Divisor Latch High (DLH) Register."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_DLH_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "dlh,Divisor Latch High 8-bit register field - used to set the UART baud-rate"
rgroup.long 0x8++0x3
line.long 0x0 "IIR,Interrupt Identification Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IIR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x0 6.--7. "FIFOSE,Bits[7:6]  FIFO's Enabled (or FIFOSE):" "0: disabled,?,?,?"
newline
bitfld.long 0x0 4.--5. "RSVD_IIR_5to4,Reserved bits [5:4] - Read Only" "0,1,2,3"
hexmask.long.byte 0x0 0.--3. 1. "IID,Bits[3:0]  Interrupt ID (or IID):"
group.long 0x8++0xB
line.long 0x0 "FCR,FIFO Control Register."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_FCR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x0 6.--7. "RT,Bits[7:6]  RCVR Trigger (or RT):." "0: 1 character in the FIFO,1: FIFO 1/4 full,?,?"
newline
bitfld.long 0x0 4.--5. "TET,Bits[5:4]  TX Empty Trigger (or TET):" "0: FIFO empty,1: 2 characters in the FIFO,?,?"
bitfld.long 0x0 3. "DMAM,Bit[3]  DMA Mode (or DMAM):" "0: mode 0,1: mode 1"
newline
bitfld.long 0x0 2. "XFIFOR,Bit[2]  XMIT FIFO Reset (or XFIFOR):" "0,1"
bitfld.long 0x0 1. "RFIFOR,Bit[1]  RCVR FIFO Reset (or RFIFOR):" "0,1"
newline
bitfld.long 0x0 0. "FIFOE,Bit[0]  FIFO Enable (or FIFOE):" "0,1"
line.long 0x4 "LCR,Line Control Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_LCR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x4 7. "DLAB,Divisor Latch Access Bit." "0,1"
newline
bitfld.long 0x4 6. "Break,Break Control Bit." "0,1"
bitfld.long 0x4 5. "SP,From DW_apb_uart_regfile.sv:" "0,1"
newline
bitfld.long 0x4 4. "EPS,Even Parity Select." "0,1"
bitfld.long 0x4 3. "PEN,Parity Enable." "0: parity disabled,1: parity enabled"
newline
bitfld.long 0x4 2. "STOP,Number of stop bits." "0: 1 stop bit,1: 1"
bitfld.long 0x4 0.--1. "DLS,Data Length Select." "0: 5 bits,1: 6 bits,?,?"
line.long 0x8 "MCR,Modem Control Register"
hexmask.long 0x8 7.--31. 1. "RSVD_MCR_31to7,Reserved bits [31:7] - Read Only"
rbitfld.long 0x8 6. "SIRE,SIR Mode Enable." "0: IrDA SIR Mode disabled,1: IrDA SIR Mode enabled"
newline
bitfld.long 0x8 5. "AFCE,Auto Flow Control Enable." "0: Auto Flow Control Mode disabled,1: Auto Flow Control Mode enabled"
bitfld.long 0x8 4. "LoopBack,LoopBack Bit." "0,1"
newline
bitfld.long 0x8 3. "OUT2,OUT2." "0: out2_n de-asserted,1: out2_n asserted"
bitfld.long 0x8 2. "OUT1,OUT1." "0: out1_n de-asserted,1: out1_n asserted"
newline
bitfld.long 0x8 1. "RTS,Request to Send." "0,1"
bitfld.long 0x8 0. "DTR,Data Terminal Ready." "0: dtr_n de-asserted,1: dtr_n asserted"
rgroup.long 0x14++0x7
line.long 0x0 "LSR,Line Status Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_LSR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x0 7. "RFE,Receiver FIFO Error bit." "0: no error in RX FIFO,1: error in RX FIFO"
newline
bitfld.long 0x0 6. "TEMT,Transmitter Empty bit." "0,1"
bitfld.long 0x0 5. "THRE,Transmit Holding Register Empty bit." "0,1"
newline
bitfld.long 0x0 4. "BI,Break Interrupt bit." "0,1"
bitfld.long 0x0 3. "FE,Framing Error bit." "0: no framing error,1: framing error"
newline
bitfld.long 0x0 2. "PE,Parity Error bit." "0: no parity error,1: parity error"
bitfld.long 0x0 1. "OE,Overrun error bit." "0: no overrun error,1: overrun error"
newline
bitfld.long 0x0 0. "DR,Data Ready bit." "0: no data ready,1: data ready"
line.long 0x4 "MSR,Modem Status Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_MSR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x4 7. "DCD,Data Carrier Detect." "0: dcd_n input is de-asserted,1: dcd_n input is asserted"
newline
bitfld.long 0x4 6. "RI,Ring Indicator." "0: ri_n input is de-asserted,1: ri_n input is asserted"
bitfld.long 0x4 5. "DSR,Data Set Ready." "0: dsr_n input is de-asserted,1: dsr_n input is asserted"
newline
bitfld.long 0x4 4. "CTS,Clear to Send." "0: cts_n input is de-asserted,1: cts_n input is asserted"
bitfld.long 0x4 3. "DDCD,Delta Data Carrier Detect." "0: no change on dcd_n since last read of MSR,1: change on dcd_n since last read of MSR"
newline
bitfld.long 0x4 2. "TERI,Trailing Edge of Ring Indicator." "0: no change on ri_n since last read of MSR,1: change on ri_n since last read of MSR"
bitfld.long 0x4 1. "DDSR,Delta Data Set Ready." "0: no change on dsr_n since last read of MSR,1: change on dsr_n since last read of MSR"
newline
bitfld.long 0x4 0. "DCTS,Delta Clear to Send." "0: no change on cts_n since last read of MSR,1: change on cts_n since last read of MSR"
group.long 0x1C++0x3
line.long 0x0 "SCR,Scratchpad Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SCR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "scr,This register is for programmers to use as a temporary storage space. It has no"
rgroup.long 0x30++0x3
line.long 0x0 "SRBR0,Shadow Receive Buffer Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR0_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr0,Shadow Receive Buffer Register 0:"
group.long 0x30++0x3
line.long 0x0 "STHR0,Shadow Transmit Holding Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR0_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr0,Shadow Transmit Holding Register 0:"
rgroup.long 0x34++0x3
line.long 0x0 "SRBR1,Shadow Receive Buffer Register 1"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR1_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr1,See srbr0 description"
group.long 0x34++0x3
line.long 0x0 "STHR1,Shadow Transmit Holding Register 1"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR1_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr1,See sthr0 description."
rgroup.long 0x38++0x3
line.long 0x0 "SRBR2,Shadow Receive Buffer Register 2"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR2_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr2,See srbr0 description"
group.long 0x38++0x3
line.long 0x0 "STHR2,Shadow Transmit Holding Register 2"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR2_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr2,See sthr0 description."
rgroup.long 0x3C++0x3
line.long 0x0 "SRBR3,Shadow Receive Buffer Register 3"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR3_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr3,See srbr0 description"
group.long 0x3C++0x3
line.long 0x0 "STHR3,Shadow Transmit Holding Register 3"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR3_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr3,See sthr0 description."
rgroup.long 0x40++0x3
line.long 0x0 "SRBR4,Shadow Receive Buffer Register 4"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR4_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr4,See srbr0 description"
group.long 0x40++0x3
line.long 0x0 "STHR4,Shadow Transmit Holding Register 4"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR4_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr4,See sthr0 description."
rgroup.long 0x44++0x3
line.long 0x0 "SRBR5,Shadow Receive Buffer Register 5"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR5_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr5,See srbr0 description"
group.long 0x44++0x3
line.long 0x0 "STHR5,Shadow Transmit Holding Register 5"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR5_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr5,See sthr0 description."
rgroup.long 0x48++0x3
line.long 0x0 "SRBR6,Shadow Receive Buffer Register 6"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR6_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr6,See srbr0 description"
group.long 0x48++0x3
line.long 0x0 "STHR6,Shadow Transmit Holding Register 6"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR6_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr6,See sthr0 description."
rgroup.long 0x4C++0x3
line.long 0x0 "SRBR7,Shadow Receive Buffer Register 7"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR7_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr7,See srbr0 description"
group.long 0x4C++0x3
line.long 0x0 "STHR7,Shadow Transmit Holding Register 7"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR7_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr7,See sthr0 description."
rgroup.long 0x50++0x3
line.long 0x0 "SRBR8,Shadow Receive Buffer Register 8"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR8_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr8,See srbr0 description"
group.long 0x50++0x3
line.long 0x0 "STHR8,Shadow Transmit Holding Register 8"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR8_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr8,See sthr0 description."
rgroup.long 0x54++0x3
line.long 0x0 "SRBR9,Shadow Receive Buffer Register 9"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR9_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr9,See srbr0 description"
group.long 0x54++0x3
line.long 0x0 "STHR9,Shadow Transmit Holding Register 9"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR9_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr9,See sthr0 description."
rgroup.long 0x58++0x3
line.long 0x0 "SRBR10,Shadow Receive Buffer Register 10"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR10_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr10,See srbr0 description"
group.long 0x58++0x3
line.long 0x0 "STHR10,Shadow Transmit Holding Register 10"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR10_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr10,See sthr0 description."
rgroup.long 0x5C++0x3
line.long 0x0 "SRBR11,Shadow Receive Buffer Register 11"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR11_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr11,See srbr0 description"
group.long 0x5C++0x3
line.long 0x0 "STHR11,Shadow Transmit Holding Register 11"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR11_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr11,See sthr0 description."
rgroup.long 0x60++0x3
line.long 0x0 "SRBR12,Shadow Receive Buffer Register 12"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR12_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr12,See srbr0 description"
group.long 0x60++0x3
line.long 0x0 "STHR12,Shadow Transmit Holding Register 12"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR12_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr12,See sthr0 description."
rgroup.long 0x64++0x3
line.long 0x0 "SRBR13,Shadow Receive Buffer Register 13"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR13_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr13,See srbr0 description"
group.long 0x64++0x3
line.long 0x0 "STHR13,Shadow Transmit Holding Register 13"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR13_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr13,See sthr0 description."
rgroup.long 0x68++0x3
line.long 0x0 "SRBR14,Shadow Receive Buffer Register 14"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR14_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr14,See srbr0 description"
group.long 0x68++0x3
line.long 0x0 "STHR14,Shadow Transmit Holding Register 14"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR14_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr14,See sthr0 description."
rgroup.long 0x6C++0x3
line.long 0x0 "SRBR15,Shadow Receive Buffer Register 15"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR15_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr15,See srbr0 description"
group.long 0x6C++0x7
line.long 0x0 "STHR15,Shadow Transmit Holding Register 15"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR15_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr15,See sthr0 description."
line.long 0x4 "FAR,FIFO Access Register"
hexmask.long 0x4 1.--31. 1. "RSVD_FAR_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x4 0. "far,Writes will have no effect when FIFO_ACCESS == No  always readable. This register" "0: FIFO access mode disabled,1: FIFO access mode enabled"
rgroup.long 0x74++0x3
line.long 0x0 "TFR,Transmit FIFO Read"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_TFR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "tfr,Transmit FIFO Read."
group.long 0x78++0x3
line.long 0x0 "RFW,Receive FIFO Write"
hexmask.long.tbyte 0x0 10.--31. 1. "RSVD_RFW_31to10,Reserved bits [31:10] - Read Only"
bitfld.long 0x0 9. "RFFE,Receive FIFO Framing Error." "0,1"
newline
bitfld.long 0x0 8. "RFPE,Receive FIFO Parity Error." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "RFWD,Receive FIFO Write Data."
rgroup.long 0x7C++0xB
line.long 0x0 "USR,UART Status register."
hexmask.long 0x0 5.--31. 1. "RSVD_USR_31to5,Reserved bits [31:5] - Read Only"
bitfld.long 0x0 4. "RFF,Receive FIFO Full." "0: Receive FIFO not full,1: Receive FIFO Full"
newline
bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
bitfld.long 0x0 2. "TFE,Transmit FIFO Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
newline
bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
bitfld.long 0x0 0. "RSVD_BUSY,UART Busy." "0,1"
line.long 0x4 "TFL,Transmit FIFO Level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_TFL_31toADDR_WIDTH,Reserved bits: 31 downto addr bus width + 1 - Read Only"
hexmask.long.byte 0x4 0.--7. 1. "tfl,Transmit FIFO Level."
line.long 0x8 "RFL,Receive FIFO Level."
hexmask.long.tbyte 0x8 8.--31. 1. "RSVD_RFL_31toADDR_WIDTH,Reserved bits: 31 downnto addr bus width + 1 - Read Only"
hexmask.long.byte 0x8 0.--7. 1. "rfl,Receive FIFO Level."
group.long 0x88++0x23
line.long 0x0 "SRR,Software Reset Register."
hexmask.long 0x0 3.--31. 1. "RSVD_SRR_31to3,Reserved bits [31:3] - Read Only"
bitfld.long 0x0 2. "XFR,XMIT FIFO Reset." "0,1"
newline
bitfld.long 0x0 1. "RFR,RCVR FIFO Reset." "0,1"
bitfld.long 0x0 0. "UR,UART Reset." "0,1"
line.long 0x4 "SRTS,Shadow Request to Send."
hexmask.long 0x4 1.--31. 1. "RSVD_SRTS_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x4 0. "srts,Shadow Request to Send." "0,1"
line.long 0x8 "SBCR,Shadow Break Control Register."
hexmask.long 0x8 1.--31. 1. "RSVD_SBCR_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x8 0. "sbcb,Shadow Break Control Bit." "0,1"
line.long 0xC "SDMAM,Shadow DMA Mode."
hexmask.long 0xC 1.--31. 1. "RSVD_SDMAM_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0xC 0. "sdmam,Shadow DMA Mode." "0: mode 0,1: mode 1"
line.long 0x10 "SFE,Shadow FIFO Enable"
hexmask.long 0x10 1.--31. 1. "RSVD_SFE_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x10 0. "sfe,Shadow FIFO Enable." "0,1"
line.long 0x14 "SRT,Shadow RCVR Trigger"
hexmask.long 0x14 2.--31. 1. "RSVD_SRT_31to2,Reserved bits [31:2] - Read Only"
bitfld.long 0x14 0.--1. "srt,Shadow RCVR Trigger." "0: 1 character in the FIFO,1: FIFO 1/4 full,?,?"
line.long 0x18 "STET,Shadow TX Empty Trigger"
hexmask.long 0x18 2.--31. 1. "RSVD_STET_31to2,Reserved bits [31:2] - Read Only"
bitfld.long 0x18 0.--1. "stet,Shadow TX Empty Trigger." "0: FIFO empty,1: 2 characters in the FIFO,?,?"
line.long 0x1C "HTX,Halt TX"
hexmask.long 0x1C 1.--31. 1. "RSVD_HTX_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x1C 0. "htx,Halt TX." "0: Halt TX disabled,1: Halt TX enabled"
line.long 0x20 "DMASA,DMA Software Acknowledge"
hexmask.long 0x20 1.--31. 1. "RSVD_DMASA_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x20 0. "dmasa,DMA Software Acknowledge." "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "CPR,Component Parameter Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_CPR_31to24,Reserved bits [31:24] - Read Only"
hexmask.long.byte 0x0 16.--23. 1. "FIFO_MODE,Encoding of FIFO_MODE configuration parameter value.DW_apb_uart.ralf"
newline
bitfld.long 0x0 14.--15. "RSVD_CPR_15to14,Reserved bits [15:14] - Read Only" "0,1,2,3"
bitfld.long 0x0 13. "DMA_EXTRA,Encoding of DMA_EXTRA configuration parameter value." "0: FALSE,1: TRUE"
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bitfld.long 0x0 12. "UART_ADD_ENCODED_PARAMS,Encoding of UART_ADD_ENCODED_PARAMS configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 11. "SHADOW,Encoding of SHADOW configuration parameter value." "0: FALSE,1: TRUE"
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bitfld.long 0x0 10. "FIFO_STAT,Encoding of FIFO_STAT configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 9. "FIFO_ACCESS,Encoding of FIFO_ACCESS configuration parameter value." "0: FALSE,1: TRUE"
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bitfld.long 0x0 8. "ADDITIONAL_FEAT,Encoding of ADDITIONAL_FEATURES configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 7. "SIR_LP_MODE,Encoding of SIR_LP_MODE configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 6. "SIR_MODE,Encoding of SIR_MODE configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 5. "THRE_MODE,Encoding of THRE_MODE configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 4. "AFCE_MODE,Encoding of AFCE_MODE configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 2.--3. "RSVD_CPR_3to2,Reserved bits [3:2] - Read Only" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,Encoding of APB_DATA_WIDTH configuration parameter value." "0: 8 bits,1: 16 bits,?,?"
line.long 0x4 "UCV,Component Version"
hexmask.long 0x4 0.--31. 1. "UART_Component_Version,ASCII value for each number in the version  followed by *."
line.long 0x8 "CTR,Component Type Register"
hexmask.long 0x8 0.--31. 1. "Peripheral_ID,This register contains the peripherals identification code."
tree.end
tree "UART1 (UART1 Module)"
base ad:0xFFC02100
rgroup.long 0x0++0x3
line.long 0x0 "RBR,Receive Buffer Register. reading this register when the DLAB bit is zero;"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_RBR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "rbr,Receive Buffer Register:"
group.long 0x0++0x3
line.long 0x0 "DLL,Receive Buffer Register. reading this register when the DLAB bit is zero;"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_DLL_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "dll,Divisor Latch (Low):"
group.long 0x0++0x7
line.long 0x0 "THR,Receive Buffer Register. reading this register when the DLAB bit is zero;"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_THR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "thr,Transmit Holding Register:"
line.long 0x4 "IER,Interrupt Enable Register:"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IER_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x4 7. "PTIME,Interrupt Enable Register: PTIME  Programmable THRE Interrupt Mode Enable." "0: disabled,1: enabled"
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rbitfld.long 0x4 4.--6. "RSVD_IER_6to4,Reserved bits [6:4] - Read Only" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "EDSSI,Interrupt Enable Register: EDSSI  Enable Modem Status Interrupt." "0: disabled,1: enabled"
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bitfld.long 0x4 2. "ELSI,Interrupt Enable Register: ELSI  Enable Receiver Line Status Interrupt." "0: disabled,1: enabled"
bitfld.long 0x4 1. "ETBEI,Interrupt Enable Register: ETBEI  Enable Transmit Holding Register Empty Interrupt." "0: disabled,1: enabled"
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bitfld.long 0x4 0. "ERBFI,Interrupt Enable Register: ERBFI  Enable Received Data Available Interrupt." "0: disabled,1: enabled"
group.long 0x4++0x3
line.long 0x0 "DLH,Divisor Latch High (DLH) Register."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_DLH_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "dlh,Divisor Latch High 8-bit register field - used to set the UART baud-rate"
rgroup.long 0x8++0x3
line.long 0x0 "IIR,Interrupt Identification Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IIR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x0 6.--7. "FIFOSE,Bits[7:6]  FIFO's Enabled (or FIFOSE):" "0: disabled,?,?,?"
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bitfld.long 0x0 4.--5. "RSVD_IIR_5to4,Reserved bits [5:4] - Read Only" "0,1,2,3"
hexmask.long.byte 0x0 0.--3. 1. "IID,Bits[3:0]  Interrupt ID (or IID):"
group.long 0x8++0xB
line.long 0x0 "FCR,FIFO Control Register."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_FCR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x0 6.--7. "RT,Bits[7:6]  RCVR Trigger (or RT):." "0: 1 character in the FIFO,1: FIFO 1/4 full,?,?"
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bitfld.long 0x0 4.--5. "TET,Bits[5:4]  TX Empty Trigger (or TET):" "0: FIFO empty,1: 2 characters in the FIFO,?,?"
bitfld.long 0x0 3. "DMAM,Bit[3]  DMA Mode (or DMAM):" "0: mode 0,1: mode 1"
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bitfld.long 0x0 2. "XFIFOR,Bit[2]  XMIT FIFO Reset (or XFIFOR):" "0,1"
bitfld.long 0x0 1. "RFIFOR,Bit[1]  RCVR FIFO Reset (or RFIFOR):" "0,1"
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bitfld.long 0x0 0. "FIFOE,Bit[0]  FIFO Enable (or FIFOE):" "0,1"
line.long 0x4 "LCR,Line Control Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_LCR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x4 7. "DLAB,Divisor Latch Access Bit." "0,1"
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bitfld.long 0x4 6. "Break,Break Control Bit." "0,1"
bitfld.long 0x4 5. "SP,From DW_apb_uart_regfile.sv:" "0,1"
newline
bitfld.long 0x4 4. "EPS,Even Parity Select." "0,1"
bitfld.long 0x4 3. "PEN,Parity Enable." "0: parity disabled,1: parity enabled"
newline
bitfld.long 0x4 2. "STOP,Number of stop bits." "0: 1 stop bit,1: 1"
bitfld.long 0x4 0.--1. "DLS,Data Length Select." "0: 5 bits,1: 6 bits,?,?"
line.long 0x8 "MCR,Modem Control Register"
hexmask.long 0x8 7.--31. 1. "RSVD_MCR_31to7,Reserved bits [31:7] - Read Only"
rbitfld.long 0x8 6. "SIRE,SIR Mode Enable." "0: IrDA SIR Mode disabled,1: IrDA SIR Mode enabled"
newline
bitfld.long 0x8 5. "AFCE,Auto Flow Control Enable." "0: Auto Flow Control Mode disabled,1: Auto Flow Control Mode enabled"
bitfld.long 0x8 4. "LoopBack,LoopBack Bit." "0,1"
newline
bitfld.long 0x8 3. "OUT2,OUT2." "0: out2_n de-asserted,1: out2_n asserted"
bitfld.long 0x8 2. "OUT1,OUT1." "0: out1_n de-asserted,1: out1_n asserted"
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bitfld.long 0x8 1. "RTS,Request to Send." "0,1"
bitfld.long 0x8 0. "DTR,Data Terminal Ready." "0: dtr_n de-asserted,1: dtr_n asserted"
rgroup.long 0x14++0x7
line.long 0x0 "LSR,Line Status Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_LSR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x0 7. "RFE,Receiver FIFO Error bit." "0: no error in RX FIFO,1: error in RX FIFO"
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bitfld.long 0x0 6. "TEMT,Transmitter Empty bit." "0,1"
bitfld.long 0x0 5. "THRE,Transmit Holding Register Empty bit." "0,1"
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bitfld.long 0x0 4. "BI,Break Interrupt bit." "0,1"
bitfld.long 0x0 3. "FE,Framing Error bit." "0: no framing error,1: framing error"
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bitfld.long 0x0 2. "PE,Parity Error bit." "0: no parity error,1: parity error"
bitfld.long 0x0 1. "OE,Overrun error bit." "0: no overrun error,1: overrun error"
newline
bitfld.long 0x0 0. "DR,Data Ready bit." "0: no data ready,1: data ready"
line.long 0x4 "MSR,Modem Status Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_MSR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x4 7. "DCD,Data Carrier Detect." "0: dcd_n input is de-asserted,1: dcd_n input is asserted"
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bitfld.long 0x4 6. "RI,Ring Indicator." "0: ri_n input is de-asserted,1: ri_n input is asserted"
bitfld.long 0x4 5. "DSR,Data Set Ready." "0: dsr_n input is de-asserted,1: dsr_n input is asserted"
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bitfld.long 0x4 4. "CTS,Clear to Send." "0: cts_n input is de-asserted,1: cts_n input is asserted"
bitfld.long 0x4 3. "DDCD,Delta Data Carrier Detect." "0: no change on dcd_n since last read of MSR,1: change on dcd_n since last read of MSR"
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bitfld.long 0x4 2. "TERI,Trailing Edge of Ring Indicator." "0: no change on ri_n since last read of MSR,1: change on ri_n since last read of MSR"
bitfld.long 0x4 1. "DDSR,Delta Data Set Ready." "0: no change on dsr_n since last read of MSR,1: change on dsr_n since last read of MSR"
newline
bitfld.long 0x4 0. "DCTS,Delta Clear to Send." "0: no change on cts_n since last read of MSR,1: change on cts_n since last read of MSR"
group.long 0x1C++0x3
line.long 0x0 "SCR,Scratchpad Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SCR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "scr,This register is for programmers to use as a temporary storage space. It has no"
rgroup.long 0x30++0x3
line.long 0x0 "SRBR0,Shadow Receive Buffer Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR0_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr0,Shadow Receive Buffer Register 0:"
group.long 0x30++0x3
line.long 0x0 "STHR0,Shadow Transmit Holding Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR0_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr0,Shadow Transmit Holding Register 0:"
rgroup.long 0x34++0x3
line.long 0x0 "SRBR1,Shadow Receive Buffer Register 1"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR1_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr1,See srbr0 description"
group.long 0x34++0x3
line.long 0x0 "STHR1,Shadow Transmit Holding Register 1"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR1_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr1,See sthr0 description."
rgroup.long 0x38++0x3
line.long 0x0 "SRBR2,Shadow Receive Buffer Register 2"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR2_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr2,See srbr0 description"
group.long 0x38++0x3
line.long 0x0 "STHR2,Shadow Transmit Holding Register 2"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR2_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr2,See sthr0 description."
rgroup.long 0x3C++0x3
line.long 0x0 "SRBR3,Shadow Receive Buffer Register 3"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR3_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr3,See srbr0 description"
group.long 0x3C++0x3
line.long 0x0 "STHR3,Shadow Transmit Holding Register 3"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR3_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr3,See sthr0 description."
rgroup.long 0x40++0x3
line.long 0x0 "SRBR4,Shadow Receive Buffer Register 4"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR4_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr4,See srbr0 description"
group.long 0x40++0x3
line.long 0x0 "STHR4,Shadow Transmit Holding Register 4"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR4_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr4,See sthr0 description."
rgroup.long 0x44++0x3
line.long 0x0 "SRBR5,Shadow Receive Buffer Register 5"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR5_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr5,See srbr0 description"
group.long 0x44++0x3
line.long 0x0 "STHR5,Shadow Transmit Holding Register 5"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR5_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr5,See sthr0 description."
rgroup.long 0x48++0x3
line.long 0x0 "SRBR6,Shadow Receive Buffer Register 6"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR6_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr6,See srbr0 description"
group.long 0x48++0x3
line.long 0x0 "STHR6,Shadow Transmit Holding Register 6"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR6_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr6,See sthr0 description."
rgroup.long 0x4C++0x3
line.long 0x0 "SRBR7,Shadow Receive Buffer Register 7"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR7_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr7,See srbr0 description"
group.long 0x4C++0x3
line.long 0x0 "STHR7,Shadow Transmit Holding Register 7"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR7_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr7,See sthr0 description."
rgroup.long 0x50++0x3
line.long 0x0 "SRBR8,Shadow Receive Buffer Register 8"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR8_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr8,See srbr0 description"
group.long 0x50++0x3
line.long 0x0 "STHR8,Shadow Transmit Holding Register 8"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR8_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr8,See sthr0 description."
rgroup.long 0x54++0x3
line.long 0x0 "SRBR9,Shadow Receive Buffer Register 9"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR9_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr9,See srbr0 description"
group.long 0x54++0x3
line.long 0x0 "STHR9,Shadow Transmit Holding Register 9"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR9_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr9,See sthr0 description."
rgroup.long 0x58++0x3
line.long 0x0 "SRBR10,Shadow Receive Buffer Register 10"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR10_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr10,See srbr0 description"
group.long 0x58++0x3
line.long 0x0 "STHR10,Shadow Transmit Holding Register 10"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR10_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr10,See sthr0 description."
rgroup.long 0x5C++0x3
line.long 0x0 "SRBR11,Shadow Receive Buffer Register 11"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR11_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr11,See srbr0 description"
group.long 0x5C++0x3
line.long 0x0 "STHR11,Shadow Transmit Holding Register 11"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR11_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr11,See sthr0 description."
rgroup.long 0x60++0x3
line.long 0x0 "SRBR12,Shadow Receive Buffer Register 12"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR12_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr12,See srbr0 description"
group.long 0x60++0x3
line.long 0x0 "STHR12,Shadow Transmit Holding Register 12"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR12_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr12,See sthr0 description."
rgroup.long 0x64++0x3
line.long 0x0 "SRBR13,Shadow Receive Buffer Register 13"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR13_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr13,See srbr0 description"
group.long 0x64++0x3
line.long 0x0 "STHR13,Shadow Transmit Holding Register 13"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR13_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr13,See sthr0 description."
rgroup.long 0x68++0x3
line.long 0x0 "SRBR14,Shadow Receive Buffer Register 14"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR14_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr14,See srbr0 description"
group.long 0x68++0x3
line.long 0x0 "STHR14,Shadow Transmit Holding Register 14"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR14_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr14,See sthr0 description."
rgroup.long 0x6C++0x3
line.long 0x0 "SRBR15,Shadow Receive Buffer Register 15"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR15_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr15,See srbr0 description"
group.long 0x6C++0x7
line.long 0x0 "STHR15,Shadow Transmit Holding Register 15"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR15_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr15,See sthr0 description."
line.long 0x4 "FAR,FIFO Access Register"
hexmask.long 0x4 1.--31. 1. "RSVD_FAR_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x4 0. "far,Writes will have no effect when FIFO_ACCESS == No  always readable. This register" "0: FIFO access mode disabled,1: FIFO access mode enabled"
rgroup.long 0x74++0x3
line.long 0x0 "TFR,Transmit FIFO Read"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_TFR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "tfr,Transmit FIFO Read."
group.long 0x78++0x3
line.long 0x0 "RFW,Receive FIFO Write"
hexmask.long.tbyte 0x0 10.--31. 1. "RSVD_RFW_31to10,Reserved bits [31:10] - Read Only"
bitfld.long 0x0 9. "RFFE,Receive FIFO Framing Error." "0,1"
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bitfld.long 0x0 8. "RFPE,Receive FIFO Parity Error." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "RFWD,Receive FIFO Write Data."
rgroup.long 0x7C++0xB
line.long 0x0 "USR,UART Status register."
hexmask.long 0x0 5.--31. 1. "RSVD_USR_31to5,Reserved bits [31:5] - Read Only"
bitfld.long 0x0 4. "RFF,Receive FIFO Full." "0: Receive FIFO not full,1: Receive FIFO Full"
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bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
bitfld.long 0x0 2. "TFE,Transmit FIFO Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
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bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
bitfld.long 0x0 0. "RSVD_BUSY,UART Busy." "0,1"
line.long 0x4 "TFL,Transmit FIFO Level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_TFL_31toADDR_WIDTH,Reserved bits: 31 downto addr bus width + 1 - Read Only"
hexmask.long.byte 0x4 0.--7. 1. "tfl,Transmit FIFO Level."
line.long 0x8 "RFL,Receive FIFO Level."
hexmask.long.tbyte 0x8 8.--31. 1. "RSVD_RFL_31toADDR_WIDTH,Reserved bits: 31 downnto addr bus width + 1 - Read Only"
hexmask.long.byte 0x8 0.--7. 1. "rfl,Receive FIFO Level."
group.long 0x88++0x23
line.long 0x0 "SRR,Software Reset Register."
hexmask.long 0x0 3.--31. 1. "RSVD_SRR_31to3,Reserved bits [31:3] - Read Only"
bitfld.long 0x0 2. "XFR,XMIT FIFO Reset." "0,1"
newline
bitfld.long 0x0 1. "RFR,RCVR FIFO Reset." "0,1"
bitfld.long 0x0 0. "UR,UART Reset." "0,1"
line.long 0x4 "SRTS,Shadow Request to Send."
hexmask.long 0x4 1.--31. 1. "RSVD_SRTS_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x4 0. "srts,Shadow Request to Send." "0,1"
line.long 0x8 "SBCR,Shadow Break Control Register."
hexmask.long 0x8 1.--31. 1. "RSVD_SBCR_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x8 0. "sbcb,Shadow Break Control Bit." "0,1"
line.long 0xC "SDMAM,Shadow DMA Mode."
hexmask.long 0xC 1.--31. 1. "RSVD_SDMAM_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0xC 0. "sdmam,Shadow DMA Mode." "0: mode 0,1: mode 1"
line.long 0x10 "SFE,Shadow FIFO Enable"
hexmask.long 0x10 1.--31. 1. "RSVD_SFE_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x10 0. "sfe,Shadow FIFO Enable." "0,1"
line.long 0x14 "SRT,Shadow RCVR Trigger"
hexmask.long 0x14 2.--31. 1. "RSVD_SRT_31to2,Reserved bits [31:2] - Read Only"
bitfld.long 0x14 0.--1. "srt,Shadow RCVR Trigger." "0: 1 character in the FIFO,1: FIFO 1/4 full,?,?"
line.long 0x18 "STET,Shadow TX Empty Trigger"
hexmask.long 0x18 2.--31. 1. "RSVD_STET_31to2,Reserved bits [31:2] - Read Only"
bitfld.long 0x18 0.--1. "stet,Shadow TX Empty Trigger." "0: FIFO empty,1: 2 characters in the FIFO,?,?"
line.long 0x1C "HTX,Halt TX"
hexmask.long 0x1C 1.--31. 1. "RSVD_HTX_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x1C 0. "htx,Halt TX." "0: Halt TX disabled,1: Halt TX enabled"
line.long 0x20 "DMASA,DMA Software Acknowledge"
hexmask.long 0x20 1.--31. 1. "RSVD_DMASA_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x20 0. "dmasa,DMA Software Acknowledge." "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "CPR,Component Parameter Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_CPR_31to24,Reserved bits [31:24] - Read Only"
hexmask.long.byte 0x0 16.--23. 1. "FIFO_MODE,Encoding of FIFO_MODE configuration parameter value.DW_apb_uart.ralf"
newline
bitfld.long 0x0 14.--15. "RSVD_CPR_15to14,Reserved bits [15:14] - Read Only" "0,1,2,3"
bitfld.long 0x0 13. "DMA_EXTRA,Encoding of DMA_EXTRA configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 12. "UART_ADD_ENCODED_PARAMS,Encoding of UART_ADD_ENCODED_PARAMS configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 11. "SHADOW,Encoding of SHADOW configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 10. "FIFO_STAT,Encoding of FIFO_STAT configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 9. "FIFO_ACCESS,Encoding of FIFO_ACCESS configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 8. "ADDITIONAL_FEAT,Encoding of ADDITIONAL_FEATURES configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 7. "SIR_LP_MODE,Encoding of SIR_LP_MODE configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 6. "SIR_MODE,Encoding of SIR_MODE configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 5. "THRE_MODE,Encoding of THRE_MODE configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 4. "AFCE_MODE,Encoding of AFCE_MODE configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 2.--3. "RSVD_CPR_3to2,Reserved bits [3:2] - Read Only" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,Encoding of APB_DATA_WIDTH configuration parameter value." "0: 8 bits,1: 16 bits,?,?"
line.long 0x4 "UCV,Component Version"
hexmask.long 0x4 0.--31. 1. "UART_Component_Version,ASCII value for each number in the version  followed by *."
line.long 0x8 "CTR,Component Type Register"
hexmask.long 0x8 0.--31. 1. "Peripheral_ID,This register contains the peripherals identification code."
tree.end
tree.end
tree "USB (Universal Serial Bus 2.0 On-the-Go)"
base ad:0x0
tree "USB0 (USB0 OTG Controller Module Registers)"
base ad:0xFFB00000
group.long 0x0++0x1B
line.long 0x0 "GOTGCTL,OTG Control and Status Register"
hexmask.long.byte 0x0 28.--31. 1. "RESERVED,RESERVED"
newline
rbitfld.long 0x0 21. "CurMod,Mode: Host and Device" "0: Device mode,1: Host mode"
newline
bitfld.long 0x0 20. "OTGVer,OTG Version (OTGVer)" "0: OTG Version 1,1: OTG Version 2"
newline
rbitfld.long 0x0 19. "BSesVld,Mode: Device only" "0: B-session is not valid,1: B-session is valid"
newline
rbitfld.long 0x0 18. "ASesVld,Mode: Host only" "0: A-session is not valid,1: A-session is valid"
newline
rbitfld.long 0x0 17. "DbncTime,Mode: Host only" "0: Long debounce time,1: Short debounce time"
newline
rbitfld.long 0x0 16. "ConIDSts,Mode: Host and Device" "0: The DWC_otg core is in A-Device mode,1: The DWC_otg core is in B-Device mode"
newline
bitfld.long 0x0 12. "EHEn,Mode: SRP Capable Host" "0: Disable Embedded Host Mode,1: Enable Embedded Host Mode"
newline
bitfld.long 0x0 11. "DevHNPEn,Mode: Device only" "0: HNP is not enabled in the application,1: HNP is enabled in the application"
newline
bitfld.long 0x0 10. "HstSetHNPEn,Mode: Host only" "0: Host Set HNP is not enabled,1: Host Set HNP is enabled"
newline
bitfld.long 0x0 9. "HNPReq,Mode: Device only" "0: No HNP request,1: HNP request"
newline
rbitfld.long 0x0 8. "HstNegScs,Mode: Device only" "0: Host negotiation failure,1: Host negotiation success"
newline
bitfld.long 0x0 7. "BvalidOvVal,B-Peripheral Session Valid OverrideValue (BvalidOvVal)" "0: Bvalid value is 1'b0 when GOTGCTL,1: Bvalid value is 1'b1 when GOTGCTL"
newline
bitfld.long 0x0 6. "BvalidOvEn,B-Peripheral Session Valid Override Enable (BvalidOvEn)" "0: Override is disabled and bvalid signal from the..,1: Internally Bvalid received from the PHY is.."
newline
bitfld.long 0x0 5. "AvalidOvVal,A-Peripheral Session Valid OverrideValue (AvalidOvVal)" "0: Avalid value is 1'b0 when GOTGCTL,1: Avalid value is 1'b1 when GOTGCTL"
newline
bitfld.long 0x0 4. "AvalidOvEn,A-Peripheral Session Valid Override Enable (AvalidOvEn)" "0: Override is disabled and avalid signal from the..,1: Internally Avalid received from the PHY is.."
newline
bitfld.long 0x0 3. "VbvalidOvVal,VBUS Valid OverrideValue (VbvalidOvVal)" "0: vbusvalid value is 1'b0 when GOTGCTL,1: vbusvalid value is 1'b1 when GOTGCTL"
newline
bitfld.long 0x0 2. "VbvalidOvEn,VBUS Valid Override Enable (VbvalidOvEn)" "0: Override is disabled and bvalid signal from the..,1: Internally Bvalid received from the PHY is.."
newline
bitfld.long 0x0 1. "SesReq,Mode: Device only" "0: No session request,1: Session request"
newline
rbitfld.long 0x0 0. "SesReqScs,Mode: Device only" "0: Session request failure,1: Session request success"
line.long 0x4 "GOTGINT,OTG Interrupt Register"
hexmask.long.word 0x4 21.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x4 19. "DbnceDone,Mode: Host only" "0,1"
newline
eventfld.long 0x4 18. "ADevTOUTChg,Mode:Host and Device" "0,1"
newline
eventfld.long 0x4 17. "HstNegDet,Mode:Host and Device" "0,1"
newline
hexmask.long.byte 0x4 10.--16. 1. "RESERVED1,RESERVED"
newline
eventfld.long 0x4 9. "HstNegSucStsChng,Mode:Host and Device" "0,1"
newline
eventfld.long 0x4 8. "SesReqSucStsChng,Mode:Host and Device" "0,1"
newline
hexmask.long.byte 0x4 3.--7. 1. "RESERVED2,RESERVED"
newline
eventfld.long 0x4 2. "SesEndDet,Mode:Host and Device" "0,1"
newline
rbitfld.long 0x4 0.--1. "RESERVED3,RESERVED" "0,1,2,3"
line.long 0x8 "GAHBCFG,AHB Configuration Register"
hexmask.long.byte 0x8 25.--31. 1. "RESERVED1,RESERVED"
newline
bitfld.long 0x8 24. "InvDescEndianess,Invert Descriptor Endianess (InvDescEndianess)" "0: Descriptor Endianness is same as AHB Master..,1: Descriptor Endianness is Little Endian if AHB.."
newline
bitfld.long 0x8 23. "AHBSingle,AHB Single Support (AHBSingle)" "0: The remaining data in the transfer is sent using..,1: The remaining data in the transfer is sent using.."
newline
bitfld.long 0x8 22. "NotiAllDmaWrit,Notify All Dma Write Transactions (NotiAllDmaWrit)" "0,1"
newline
bitfld.long 0x8 21. "RemMemSupp,Remote Memory Support (RemMemSupp)" "0,1"
newline
bitfld.long 0x8 8. "PTxFEmpLvl,Mode:Host only" "0: GINTSTS,1: GINTSTS"
newline
bitfld.long 0x8 7. "NPTxFEmpLvl,Mode:Host and device" "0: DIEPINTn,1: DIEPINTn"
newline
rbitfld.long 0x8 6. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x8 5. "DMAEn,Mode:Host and device" "0: Core operates in Slave mode,1: Core operates in a DMA mode"
newline
hexmask.long.byte 0x8 1.--4. 1. "HBstLen,Mode:Host and device"
newline
bitfld.long 0x8 0. "GlblIntrMsk,Mode:Host and device" "0: Mask the interrupt assertion to the application,1: Unmask the interrupt assertion to the application"
line.long 0xC "GUSBCFG,USB Configuration Register"
bitfld.long 0xC 31. "CorruptTxPkt,Mode:Host and device" "0,1"
newline
bitfld.long 0xC 30. "ForceDevMode,Mode:Host and device" "0: Normal Mode,1: Force Device Mode"
newline
bitfld.long 0xC 29. "ForceHstMode,Mode:Host and device" "0: Normal Mode,1: Force Host Mode"
newline
bitfld.long 0xC 28. "TxEndDelay,Mode: Device only" "0: Normal Mode,1: Tx End delay"
newline
rbitfld.long 0xC 26. "IC_USBCap,IC_USB-Capable (IC_USBCap)" "0: IC_USB PHY Interface is not selected,1: IC_USB PHY Interface is selected"
newline
bitfld.long 0xC 25. "ULPI,Mode:Host only" "0: Enables the interface protect circuit,1: Disables the interface protect circuit"
newline
bitfld.long 0xC 24. "Indicator,Mode:Host only" "0: Complement Output signal is qualified with the..,1: Complement Output signal is not qualified with the"
newline
bitfld.long 0xC 23. "Complement,Mode:Host only" "0: PHY does not invert ExternalVbusIndicator signal,1: PHY does invert ExternalVbusIndicator signal"
newline
bitfld.long 0xC 22. "TermSelDLPulse,Mode:Device only" "0: Data line pulsing using utmi_txvalid,1: Data line pulsing using utmi_termsel"
newline
bitfld.long 0xC 21. "ULPIExtVbusIndicator,Mode:Host only" "0: PHY uses internal VBUS valid comparator,1: PHY uses external VBUS valid comparator"
newline
bitfld.long 0xC 20. "ULPIExtVbusDrv,Mode:Host only" "0: PHY drives VBUS using internal charge pump,1: PHY drives VBUS using external supply"
newline
bitfld.long 0xC 19. "ULPIClkSusM,Mode:Host and Device" "0: PHY powers down internal clock during suspend,1: PHY does not power down internal clock"
newline
bitfld.long 0xC 18. "ULPIAutoRes,Mode:Host and Device" "0: PHY does not use AutoResume feature,1: PHY uses AutoResume feature"
newline
rbitfld.long 0xC 14. "RESERVED,RESERVED" "0,1"
newline
hexmask.long.byte 0xC 10.--13. 1. "USBTrdTim,Mode: Device only"
newline
bitfld.long 0xC 9. "HNPCap,Mode:Host and Device" "0: HNP capability is not enabled,1: HNP capability is enabled"
newline
bitfld.long 0xC 8. "SRPCap,Mode:Host and Device" "0: SRP capability is not enabled,1: SRP capability is enabled"
newline
bitfld.long 0xC 7. "DDRSel,Mode:Host and Device" "0: Single Data Rate ULPI Interface,1: Double Data Rate ULPI Interface"
newline
rbitfld.long 0xC 6. "PHYSel,Mode:Host and Device" "0: USB 2,1: USB 1"
newline
rbitfld.long 0xC 5. "FSIntf,Mode:Host and Device" "0: 6-pin unidirectional full-speed serial interface,1: 3-pin bidirectional full-speed serial interface"
newline
rbitfld.long 0xC 4. "ULPI_UTMI_Sel,Mode:Host and Device" "0: UTMI+ Interface,1: ULPI Interface"
newline
rbitfld.long 0xC 3. "PHYIf,Mode:Host and Device" "0: 8 bits,1: 16 bits"
newline
bitfld.long 0xC 0.--2. "TOutCal,Mode:Host and Device" "0,1,2,3,4,5,6,7"
line.long 0x10 "GRSTCTL,Reset Register"
rbitfld.long 0x10 31. "AHBIdle,Mode:Host and Device" "0,1"
newline
rbitfld.long 0x10 30. "DMAReq,Mode:Host and Device" "0,1"
newline
hexmask.long.tbyte 0x10 11.--29. 1. "RESERVED,RESERVED"
newline
hexmask.long.byte 0x10 6.--10. 1. "TxFNum,Mode:Host and Device"
newline
bitfld.long 0x10 5. "TxFFlsh,Mode:Host and Device" "0,1"
newline
bitfld.long 0x10 4. "RxFFlsh,Mode:Host and Device" "0,1"
newline
bitfld.long 0x10 2. "FrmCntrRst,Mode:Host only" "0,1"
newline
bitfld.long 0x10 1. "PIUFSSftRst,Mode:Host and Device" "0,1"
newline
bitfld.long 0x10 0. "CSftRst,Mode:Host and Device" "0,1"
line.long 0x14 "GINTSTS,Interrupt Register"
eventfld.long 0x14 31. "WkUpInt,Mode:Host and Device" "0,1"
newline
eventfld.long 0x14 30. "SessReqInt,Mode:Host and Device" "0,1"
newline
eventfld.long 0x14 29. "DisconnInt,Mode:Host only" "0,1"
newline
eventfld.long 0x14 28. "ConIDStsChng,Mode:Host and Device" "0,1"
newline
rbitfld.long 0x14 26. "PTxFEmp,Mode:Host only" "0,1"
newline
rbitfld.long 0x14 25. "HChInt,Mode:Host only" "0,1"
newline
rbitfld.long 0x14 24. "PrtInt,Mode:Host only" "0,1"
newline
eventfld.long 0x14 23. "ResetDet,Mode: Device only" "0,1"
newline
eventfld.long 0x14 22. "FetSusp,Mode: Device only" "0,1"
newline
eventfld.long 0x14 21. "incomplP,Incomplete Periodic Transfer (incomplP)" "0,1"
newline
eventfld.long 0x14 20. "incompISOIN,Mode: Device only" "0,1"
newline
rbitfld.long 0x14 19. "OEPInt,Mode: Device only" "0,1"
newline
rbitfld.long 0x14 18. "IEPInt,Mode: Device only" "0,1"
newline
eventfld.long 0x14 17. "EPMis,Mode: Device only" "0,1"
newline
eventfld.long 0x14 15. "EOPF,Mode: Device only" "0,1"
newline
eventfld.long 0x14 14. "ISOOutDrop,Mode: Device only" "0,1"
newline
eventfld.long 0x14 13. "EnumDone,Mode: Device only" "0,1"
newline
eventfld.long 0x14 12. "USBRst,Mode: Device only" "0,1"
newline
eventfld.long 0x14 11. "USBSusp,Mode: Device only" "0,1"
newline
eventfld.long 0x14 10. "ErlySusp,Mode: Device only" "0,1"
newline
rbitfld.long 0x14 7. "GOUTNakEff,Mode: Device only" "0,1"
newline
rbitfld.long 0x14 6. "GINNakEff,Mode: Device only" "0,1"
newline
rbitfld.long 0x14 5. "NPTxFEmp,Mode: Host and Device" "0,1"
newline
rbitfld.long 0x14 4. "RxFLvl,Mode: Host and Device" "0,1"
newline
eventfld.long 0x14 3. "Sof,Mode: Host and Device" "0,1"
newline
rbitfld.long 0x14 2. "OTGInt,Mode: Host and Device" "0,1"
newline
eventfld.long 0x14 1. "ModeMis,Mode: Host and Device" "0,1"
newline
rbitfld.long 0x14 0. "CurMod,Mode: Host and Device" "0: Device mode,1: Host mode"
line.long 0x18 "GINTMSK,Interrupt Mask Register"
bitfld.long 0x18 31. "WkUpIntMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 30. "SessReqIntMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 29. "DisconnIntMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 28. "ConIDStsChngMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 26. "PTxFEmpMsk,Mode: Host only" "0,1"
newline
bitfld.long 0x18 25. "HChIntMsk,Mode: Host only" "0,1"
newline
bitfld.long 0x18 24. "PrtIntMsk,Mode: Host only" "0,1"
newline
bitfld.long 0x18 23. "ResetDetMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 22. "FetSuspMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 21. "incomplPMsK,Mode: Host only" "0,1"
newline
bitfld.long 0x18 20. "incompISOINMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 19. "OEPIntMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 18. "IEPIntMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 17. "EPMisMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 15. "EOPFMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 14. "ISOOutDropMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 13. "EnumDoneMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 12. "USBRstMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 11. "USBSuspMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 10. "ErlySuspMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 7. "GOUTNakEffMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 6. "GINNakEffMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 5. "NPTxFEmpMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 4. "RxFLvlMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 3. "SofMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 2. "OTGIntMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 1. "ModeMisMsk,Mode: Host and Device" "0,1"
newline
rbitfld.long 0x18 0. "RESERVED,RESERVED" "0,1"
rgroup.long 0x1C++0x7
line.long 0x0 "GRXSTSR,Receive Status Debug Read Register"
hexmask.long.byte 0x0 25.--30. 1. "RESERVED,RESERVED"
newline
hexmask.long.byte 0x0 21.--24. 1. "FN,Mode: Device only"
newline
hexmask.long.byte 0x0 17.--20. 1. "PktSts,Mode: Host only"
newline
bitfld.long 0x0 15.--16. "DPID,Mode: Host only" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x0 4.--14. 1. "BCnt,Mode: Host only"
newline
hexmask.long.byte 0x0 0.--3. 1. "ChNum,Mode: Host only"
line.long 0x4 "GRXSTSP,Receive Status Read /Pop Register"
hexmask.long.byte 0x4 25.--30. 1. "RESERVED,RESERVED"
newline
hexmask.long.byte 0x4 21.--24. 1. "FN,Mode: Device only"
newline
hexmask.long.byte 0x4 17.--20. 1. "PktSts,Mode: Host only"
newline
bitfld.long 0x4 15.--16. "DPID,Mode: Host only" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x4 4.--14. 1. "BCnt,Mode: Host only"
newline
hexmask.long.byte 0x4 0.--3. 1. "ChNum,Mode: Host only"
group.long 0x24++0x7
line.long 0x0 "GRXFSIZ,Receive FIFO Size Register"
hexmask.long.word 0x0 14.--27. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--13. 1. "RxFDep,Mode: Host and Device"
line.long 0x4 "GNPTXFSIZ,Non-periodic Transmit FIFO Size Register"
hexmask.long.word 0x4 16.--31. 1. "NPTXFDep,Mode: Host only"
newline
hexmask.long.word 0x4 0.--15. 1. "NPTXFStAddr,Mode: Host only"
rgroup.long 0x2C++0x3
line.long 0x0 "GNPTXSTS,Non-periodic Transmit FIFO/Queue Status Register"
bitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
hexmask.long.byte 0x0 24.--30. 1. "NPTxQTop,Top of the Non-periodic Transmit Request Queue (NPTxQTop)"
newline
hexmask.long.byte 0x0 16.--23. 1. "NPTxQSpcAvail,Non-periodic Transmit Request Queue Space Available"
newline
hexmask.long.word 0x0 0.--15. 1. "NPTxFSpcAvail,Non-periodic TxFIFO Space Avail (NPTxFSpcAvail)"
group.long 0x34++0x7
line.long 0x0 "GPVNDCTL,PHY Vendor Control Register"
bitfld.long 0x0 31. "DisUlpiDrvr,Disable ULPI Drivers (DisUlpiDrvr)" "0,1"
newline
rbitfld.long 0x0 28.--30. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x0 27. "VStsDone,VStatus Done (VStsDone)" "0,1"
newline
rbitfld.long 0x0 26. "VStsBsy,VStatus Busy (VStsBsy)" "0,1"
newline
bitfld.long 0x0 25. "NewRegReq,New Register Request (NewRegReq)" "0,1"
newline
rbitfld.long 0x0 23.--24. "RESERVED1,RESERVED" "0,1,2,3"
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bitfld.long 0x0 22. "RegWr,Register Write (RegWr)" "0,1"
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hexmask.long.byte 0x0 16.--21. 1. "RegAddr,Register Address (RegAddr)"
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hexmask.long.byte 0x0 8.--15. 1. "VCtrl,UTMI+ Vendor Control Register Address (VCtrl)"
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hexmask.long.byte 0x0 0.--7. 1. "RegData,Register Data (RegData)"
line.long 0x4 "GGPIO,General Purpose Input/Output Register"
hexmask.long.word 0x4 16.--31. 1. "GPO,General Purpose Output (GPO)"
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hexmask.long.word 0x4 0.--15. 1. "GPI,General Purpose Input (GPI)"
rgroup.long 0x3C++0x17
line.long 0x0 "GUID,User ID Register"
hexmask.long 0x0 0.--31. 1. "GUID,User ID (UserID)"
line.long 0x4 "GSNPSID,Synopsys ID Register"
hexmask.long 0x4 0.--31. 1. "SynopsysID,Release number of the DWC_otg core being used currently"
line.long 0x8 "GHWCFG1,User HW Config1 Register"
hexmask.long 0x8 0.--31. 1. "EpDir,This 32-bit field uses two bits per"
line.long 0xC "GHWCFG2,User HW Config2 Register"
hexmask.long.byte 0xC 26.--30. 1. "TknQDepth,Device Mode IN Token Sequence Learning Queue Depth"
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bitfld.long 0xC 24.--25. "PTxQDepth,Host Mode Periodic Request Queue Depth (PTxQDepth)" "0: 2,1: 4,2: 8,3: 16"
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bitfld.long 0xC 22.--23. "NPTxQDepth,Non-periodic Request Queue Depth (NPTxQDepth)" "0: 2,1: 4,2: 8,?"
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bitfld.long 0xC 21. "RESERVED,RESERVED" "0,1"
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bitfld.long 0xC 20. "MultiProcIntrpt,Multi Processor Interrupt Enabled (MultiProcIntrpt)" "0: No,1: Yes"
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bitfld.long 0xC 19. "DynFifoSizing,Dynamic FIFO Sizing Enabled (DynFifoSizing)" "0: No,1: Yes"
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bitfld.long 0xC 18. "PerioSupport,Periodic OUT Channels Supported in Host Mode (PerioSupport)" "0: No,1: Yes"
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hexmask.long.byte 0xC 14.--17. 1. "NumHstChnl,Number of Host Channels (NumHstChnl)"
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hexmask.long.byte 0xC 10.--13. 1. "NumDevEps,Number of Device Endpoints (NumDevEps)"
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bitfld.long 0xC 8.--9. "FSPhyType,Full-Speed PHY Interface Type (FSPhyType)" "0: Full-speed interface not supported,1: Dedicated full-speed interface,2: FS pins shared with UTMI+ pins,3: FS pins shared with ULPI pins"
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bitfld.long 0xC 6.--7. "HSPhyType,High-Speed PHY Interface Type (HSPhyType)" "0: High-Speed interface not supported,1: UTMI+,2: ULPI,3: UTMI+ and ULPI"
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bitfld.long 0xC 5. "SingPnt,Point-to-Point (SingPnt)" "0: Multi-point application,1: Single-point application"
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bitfld.long 0xC 3.--4. "OtgArch,Architecture (OtgArch)" "0: Slave-Only,1: External DMA,2: Internal DMA,?"
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bitfld.long 0xC 0.--2. "OtgMode,Mode of Operation (OtgMode)" "0: HNP- and SRP-Capable OTG,1: SRP-Capable OTG,2: Non-HNP and Non-SRP Capable OTG,3: SRP-Capable Device,4: Non-OTG Device,5: SRP-Capable Host,6: Non-OTG Host,?"
line.long 0x10 "GHWCFG3,User HW Config3 Register"
hexmask.long.word 0x10 16.--31. 1. "DfifoDepth,DFIFO Depth (DfifoDepth - EP_LOC_CNT)"
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bitfld.long 0x10 15. "LPMMode,LPM mode specified for Mode of Operation." "0,1"
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bitfld.long 0x10 14. "BCSupport,This bit indicates the HS OTG controller support for Battery Charger." "0,1"
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bitfld.long 0x10 13. "HSICMode,HSIC mode specified for Mode of Operation" "0: Non-HSIC-capable,1: HSIC-capable with shared UTMI PHY interface"
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bitfld.long 0x10 12. "ADPSupport,This bit indicates whether ADP logic is present within or external to the HS OTG" "0: No ADP logic present with DWC_otg controller,1: ADP logic is present along with DWC_otg controller"
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bitfld.long 0x10 11. "RstType,Reset Style For Clocked always Blocks in RTL (RstType)" "0: Asynchronous reset is used in the core,1: Synchronous reset is used in the core"
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bitfld.long 0x10 10. "OptFeature,Optional Features Removed (OptFeature)" "0: No,1: Yes"
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bitfld.long 0x10 9. "VndctlSupt,Vendor Control Interface Support (VndctlSupt)" "0: Vendor Control Interface is not available on the..,1: Vendor Control Interface is available"
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bitfld.long 0x10 8. "I2CIntSel,I2C Selection (I2CIntSel)" "0: I2C Interface is not available on the core,1: I2C Interface is available on the core"
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bitfld.long 0x10 7. "OtgEn,OTG Function Enabled (OtgEn)" "0: Not OTG capable,1: OTG Capable"
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bitfld.long 0x10 4.--6. "PktSizeWidth,Width of Packet Size Counters (PktSizeWidth)" "0: 4 bits,1: 5 bits,2: 6 bits,3: 7 bits,4: 8 bits,5: 9 bits,6: 10 bits,?"
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hexmask.long.byte 0x10 0.--3. 1. "XferSizeWidth,Width of Transfer Size Counters (XferSizeWidth)"
line.long 0x14 "GHWCFG4,User HW Config4 Register"
bitfld.long 0x14 31. "DescDMA,Scatter/Gather DMA configuration" "0: Non Dynamic configuration,1: Dynamic configuration"
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bitfld.long 0x14 30. "DescDMAEnabled,Scatter/Gather DMA configuration" "0: Non-Scatter/Gather DMA configuration,1: Scatter/Gather DMA configuration"
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hexmask.long.byte 0x14 26.--29. 1. "INEps,Number of Device Mode IN Endpoints Including Control"
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bitfld.long 0x14 25. "DedFifoMode,Enable Dedicated Transmit FIFO For device IN Endpoints" "0: Dedicated Transmit FIFO Operation not enabled,1: Dedicated Transmit FIFO Operation enabled"
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bitfld.long 0x14 24. "SessEndFltr,session_end Filter Enabled (SessEndFltr)" "0: No filter,1: Filter"
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bitfld.long 0x14 23. "BValidFltr,b_valid Filter Enabled (BValidFltr)" "0: No filter,1: Filter"
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bitfld.long 0x14 22. "AValidFltr,a_valid Filter Enabled (AValidFltr)" "0: No filter,1: Filter"
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bitfld.long 0x14 21. "VBusValidFltr,VBUS Valid Filter Enabled (VBusValidFltr)" "0: No filter,1: Filter"
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bitfld.long 0x14 20. "IddgFltr,IDDIG Filter Enable (IddgFltr)" "0: No filter,1: Filter"
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hexmask.long.byte 0x14 16.--19. 1. "NumCtlEps,Number of Device Mode Control Endpoints in Addition to"
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bitfld.long 0x14 14.--15. "PhyDataWidth,UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width" "0: 8 bits,1: 16 bits,2: 8/16 bits,?"
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hexmask.long.byte 0x14 8.--13. 1. "RESERVED,RESERVED"
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bitfld.long 0x14 7. "ExtendedHibernation,Enable Hibernation" "0: Extended Hibernation feature not enabled,1: Extended Hibernation feature enabled"
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bitfld.long 0x14 6. "Hibernation,Enable Hibernation (Hibernation)" "0: Hibernation feature not enabled,1: Hibernation feature enabled"
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bitfld.long 0x14 5. "AhbFreq,Minimum AHB Frequency Less Than 60 MHz (AhbFreq)" "0: No,1: Yes"
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bitfld.long 0x14 4. "PartialPwrDn,Enable Partial Power Down (PartialPwrDn)" "0: Partial Power Down Not Enabled,1: Partial Power Down Enabled"
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hexmask.long.byte 0x14 0.--3. 1. "NumDevPerioEps,Number of Device Mode Periodic IN Endpoints"
group.long 0x5C++0x3
line.long 0x0 "GDFIFOCFG,Global DFIFO Configuration Register"
hexmask.long.word 0x0 16.--31. 1. "EPInfoBaseAddr,EPInfoBaseAddr"
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hexmask.long.word 0x0 0.--15. 1. "GDFIFOCfg,GDFIFOCfg"
group.long 0x100++0x3F
line.long 0x0 "HPTXFSIZ,Host Periodic Transmit FIFO Size Register"
hexmask.long.word 0x0 16.--29. 1. "PTxFSize,Host Periodic TxFIFO Depth (PTxFSize)"
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hexmask.long.word 0x0 0.--14. 1. "PTxFStAddr,Host Periodic TxFIFO Start Address (PTxFStAddr)"
line.long 0x4 "DIEPTXF1,Device IN Endpoint Transmit FIFO Size Register 1"
hexmask.long.word 0x4 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x4 0.--14. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x8 "DIEPTXF2,Device IN Endpoint Transmit FIFO Size Register 2"
hexmask.long.word 0x8 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x8 0.--14. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0xC "DIEPTXF3,Device IN Endpoint Transmit FIFO Size Register 3"
hexmask.long.word 0xC 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0xC 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x10 "DIEPTXF4,Device IN Endpoint Transmit FIFO Size Register 4"
hexmask.long.word 0x10 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x10 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x14 "DIEPTXF5,Device IN Endpoint Transmit FIFO Size Register 5"
hexmask.long.word 0x14 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x14 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x18 "DIEPTXF6,Device IN Endpoint Transmit FIFO Size Register 6"
hexmask.long.word 0x18 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x18 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x1C "DIEPTXF7,Device IN Endpoint Transmit FIFO Size Register 7"
hexmask.long.word 0x1C 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x1C 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x20 "DIEPTXF8,Device IN Endpoint Transmit FIFO Size Register 8"
hexmask.long.word 0x20 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x20 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x24 "DIEPTXF9,Device IN Endpoint Transmit FIFO Size Register 9"
hexmask.long.word 0x24 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x24 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x28 "DIEPTXF10,Device IN Endpoint Transmit FIFO Size Register 10"
hexmask.long.word 0x28 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x28 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x2C "DIEPTXF11,Device IN Endpoint Transmit FIFO Size Register 11"
hexmask.long.word 0x2C 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x2C 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x30 "DIEPTXF12,Device IN Endpoint Transmit FIFO Size Register 12"
hexmask.long.word 0x30 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x30 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x34 "DIEPTXF13,Device IN Endpoint Transmit FIFO Size Register 13"
hexmask.long.word 0x34 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x34 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x38 "DIEPTXF14,Device IN Endpoint Transmit FIFO Size Register 14"
hexmask.long.word 0x38 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x38 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x3C "DIEPTXF15,Device IN Endpoint Transmit FIFO Size Register 15"
hexmask.long.word 0x3C 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x3C 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
group.long 0x400++0x7
line.long 0x0 "HCFG,Host Configuration Register"
bitfld.long 0x0 31. "ModeChTimEn,Mode Change Ready Timer Enable (ModeChTimEn)" "0: The Host core waits for either 200 PHY clock..,1: The Host core waits only for a linstate of SE0.."
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hexmask.long.byte 0x0 27.--30. 1. "RESERVED,RESERVED"
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bitfld.long 0x0 26. "PerSchedEna,Enable Periodic Scheduling (PerSchedEna):" "0,1"
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bitfld.long 0x0 24.--25. "FrListEn,Frame List Entries(FrListEn). The value in the register specifies the number" "0: 8 Entries,1: 16 Entries,2: 32 Entries,3: 63 Entries"
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bitfld.long 0x0 23. "DescDMA,Enable Scatter/gather DMA in Host mode (DescDMA)." "0: Buffered DMA mode,1: Scatter/Gather DMA mode"
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hexmask.long.byte 0x0 16.--22. 1. "RESERVED1,RESERVED"
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hexmask.long.byte 0x0 8.--15. 1. "ResValid,Resume Validation Period (ResValid)"
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bitfld.long 0x0 7. "Ena32KHzS,Enable 32 KHz Suspend mode (Ena32KHzS)" "0,1"
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hexmask.long.byte 0x0 3.--6. 1. "RESERVED2,RESERVED"
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bitfld.long 0x0 2. "FSLSSupp,FS- and LS-Only Support (FSLSSupp)" "0: HS/FS/LS,1: FS/LS-only"
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bitfld.long 0x0 0.--1. "FSLSPclkSel,FS/LS PHY Clock Select (FSLSPclkSel)" "0: Internal and external clocks have the same..,1: PHY clock is running at 48 MHz,2: Internal clock is the divided by eight version..,3: Reserved"
line.long 0x4 "HFIR,Host Frame Interval Register"
hexmask.long.word 0x4 17.--31. 1. "RESERVED,RESERVED"
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bitfld.long 0x4 16. "HFIRRldCtrl,Reload Control (HFIRRldCtrl)" "0: The HFIR cannot be reloaded dynamically,1: the HFIR can be dynamically reloaded during.."
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hexmask.long.word 0x4 0.--15. 1. "FrInt,Frame Interval (FrInt)"
rgroup.long 0x408++0x3
line.long 0x0 "HFNUM,Host Frame Number/Frame Time Remaining Register"
hexmask.long.word 0x0 16.--31. 1. "FrRem,Frame Time Remaining (FrRem)"
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hexmask.long.word 0x0 0.--15. 1. "FrNum,Frame Number (FrNum)"
rgroup.long 0x410++0x7
line.long 0x0 "HPTXSTS,Host Periodic Transmit FIFO/Queue Status Register"
hexmask.long.byte 0x0 24.--31. 1. "PTxQTop,Top of the Periodic Transmit Request Queue (PTxQTop)"
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hexmask.long.byte 0x0 16.--23. 1. "PTxQSpcAvail,Periodic Transmit Request Queue Space Available"
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hexmask.long.word 0x0 0.--15. 1. "PTxFSpcAvail,Periodic Transmit Data FIFO Space Available"
line.long 0x4 "HAINT,Host All Channels Interrupt Register"
hexmask.long.word 0x4 0.--15. 1. "HAINT,Channel Interrupt for channel no."
group.long 0x418++0x7
line.long 0x0 "HAINTMSK,Host All Channels Interrupt Mask Register"
hexmask.long.word 0x0 0.--15. 1. "HAINTMsk,Channel Interrupt Msk for channel"
line.long 0x4 "HFLBAddr,Host Frame List Base Address Register"
hexmask.long 0x4 0.--31. 1. "HFLBAddr,The starting address of the Frame list."
group.long 0x440++0x3
line.long 0x0 "HPRT,Host Port Control and Status Register"
rbitfld.long 0x0 17.--18. "PrtSpd,Port Speed (PrtSpd)" "0: High speed,1: Full speed,2: Low speed,3: Reserved"
newline
hexmask.long.byte 0x0 13.--16. 1. "PrtTstCtl,Port Test Control (PrtTstCtl)"
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bitfld.long 0x0 12. "PrtPwr,Port Power (PrtPwr)" "0: Power off,1: Power on"
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rbitfld.long 0x0 10.--11. "PrtLnSts,Port Line Status (PrtLnSts)" "0,1,2,3"
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rbitfld.long 0x0 9. "RESERVED,RESERVED" "0,1"
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bitfld.long 0x0 8. "PrtRst,Port Reset (PrtRst)" "0: Port not in reset,1: Port in reset"
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bitfld.long 0x0 7. "PrtSusp,Port Suspend (PrtSusp)" "0: Port not in Suspend mode,1: Port in Suspend mode"
newline
bitfld.long 0x0 6. "PrtRes,Port Resume (PrtRes)" "0: No resume driven,1: Resume driven"
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eventfld.long 0x0 5. "PrtOvrCurrChng,Port Overcurrent Change (PrtOvrCurrChng)" "0,1"
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rbitfld.long 0x0 4. "PrtOvrCurrAct,Port Overcurrent Active (PrtOvrCurrAct)" "0: No overcurrent condition,1: Overcurrent condition"
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eventfld.long 0x0 3. "PrtEnChng,Port Enable/Disable Change (PrtEnChng)" "0,1"
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eventfld.long 0x0 2. "PrtEna,Port Enable (PrtEna)" "0: Port disabled,1: Port enabled"
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eventfld.long 0x0 1. "PrtConnDet,Port Connect Detected (PrtConnDet)" "0,1"
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rbitfld.long 0x0 0. "PrtConnSts,Port Connect Status (PrtConnSts)" "0: No device is attached to the port,1: A device is attached to the port"
group.long 0x500++0x17
line.long 0x0 "HCCHAR0,Host Channel 0 Characteristics Register"
bitfld.long 0x0 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
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bitfld.long 0x0 30. "ChDis,Channel Disable (ChDis)" "0,1"
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bitfld.long 0x0 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
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hexmask.long.byte 0x0 22.--28. 1. "DevAddr,Device Address (DevAddr)"
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bitfld.long 0x0 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
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bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
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bitfld.long 0x0 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
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rbitfld.long 0x0 16. "RESERVED,RESERVED" "0,1"
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bitfld.long 0x0 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
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hexmask.long.byte 0x0 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
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hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x4 "HCSPLT0,Host Channel 0 Split Control Register"
bitfld.long 0x4 31. "SpltEna,Split Enable (SpltEna)" "0,1"
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hexmask.long.word 0x4 17.--30. 1. "RESERVED,RESERVED"
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bitfld.long 0x4 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
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bitfld.long 0x4 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
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hexmask.long.byte 0x4 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
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hexmask.long.byte 0x4 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0x8 "HCINT0,Host Channel 0 Interrupt Register"
hexmask.long.tbyte 0x8 14.--31. 1. "RESERVED,RESERVED"
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eventfld.long 0x8 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
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eventfld.long 0x8 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
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eventfld.long 0x8 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
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eventfld.long 0x8 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
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eventfld.long 0x8 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
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eventfld.long 0x8 8. "BblErr,Babble Error (BblErr)" "0,1"
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eventfld.long 0x8 7. "XactErr,Transaction Error (XactErr)" "0,1"
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eventfld.long 0x8 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
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eventfld.long 0x8 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
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eventfld.long 0x8 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
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eventfld.long 0x8 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
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eventfld.long 0x8 2. "AHBErr,AHB Error (AHBErr)" "0,1"
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eventfld.long 0x8 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
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eventfld.long 0x8 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0xC "HCINTMSK0,Host Channel 0 Interrupt Mask Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0xC 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
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rbitfld.long 0xC 12. "RESERVED1,RESERVED" "0,1"
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bitfld.long 0xC 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
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bitfld.long 0xC 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
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bitfld.long 0xC 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
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bitfld.long 0xC 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
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bitfld.long 0xC 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
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bitfld.long 0xC 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
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bitfld.long 0xC 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
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bitfld.long 0xC 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
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bitfld.long 0xC 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
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bitfld.long 0xC 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
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bitfld.long 0xC 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
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bitfld.long 0xC 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x10 "HCTSIZ0,Host Channel 0 Transfer Size Register"
bitfld.long 0x10 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x10 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x10 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x10 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x14 "HCDMA0,Host Channel 0 DMA Address Register"
hexmask.long 0x14 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x51C++0x1B
line.long 0x0 "HCDMAB0,Host Channel 0 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR1,Host Channel 1 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT1,Host Channel 1 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT1,Host Channel 1 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK1,Host Channel 1 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ1,Host Channel 1 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA1,Host Channel 1 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x53C++0x1B
line.long 0x0 "HCDMAB1,Host Channel 1 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR2,Host Channel 2 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT2,Host Channel 2 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT2,Host Channel 2 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK2,Host Channel 2 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ2,Host Channel 2 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA2,Host Channel 2 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x55C++0x1B
line.long 0x0 "HCDMAB2,Host Channel 2 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR3,Host Channel 3 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT3,Host Channel 3 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT3,Host Channel 3 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK3,Host Channel 3 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ3,Host Channel 3 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA3,Host Channel 3 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x57C++0x1B
line.long 0x0 "HCDMAB3,Host Channel 3 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR4,Host Channel 4 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT4,Host Channel 4 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT4,Host Channel 4 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK4,Host Channel 4 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ4,Host Channel 4 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA4,Host Channel 4 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x59C++0x1B
line.long 0x0 "HCDMAB4,Host Channel 4 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR5,Host Channel 5 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT5,Host Channel 5 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT5,Host Channel 5 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK5,Host Channel 5 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ5,Host Channel 5 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA5,Host Channel 5 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x5BC++0x1B
line.long 0x0 "HCDMAB5,Host Channel 5 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR6,Host Channel 6 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT6,Host Channel 6 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT6,Host Channel 6 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK6,Host Channel 6 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ6,Host Channel 6 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA6,Host Channel 6 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x5DC++0x1B
line.long 0x0 "HCDMAB6,Host Channel 6 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR7,Host Channel 7 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT7,Host Channel 7 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT7,Host Channel 7 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK7,Host Channel 7 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ7,Host Channel 7 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA7,Host Channel 7 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x5FC++0x1B
line.long 0x0 "HCDMAB7,Host Channel 7 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR8,Host Channel 8 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT8,Host Channel 8 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT8,Host Channel 8 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK8,Host Channel 8 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ8,Host Channel 8 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA8,Host Channel 8 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x61C++0x1B
line.long 0x0 "HCDMAB8,Host Channel 8 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR9,Host Channel 9 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT9,Host Channel 9 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT9,Host Channel 9 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK9,Host Channel 9 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ9,Host Channel 9 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA9,Host Channel 9 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x63C++0x1B
line.long 0x0 "HCDMAB9,Host Channel 9 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR10,Host Channel 10 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT10,Host Channel 10 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT10,Host Channel 10 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK10,Host Channel 10 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ10,Host Channel 10 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA10,Host Channel 10 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x65C++0x1B
line.long 0x0 "HCDMAB10,Host Channel 10 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR11,Host Channel 11 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT11,Host Channel 11 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT11,Host Channel 11 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK11,Host Channel 11 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ11,Host Channel 11 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA11,Host Channel 11 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x67C++0x1B
line.long 0x0 "HCDMAB11,Host Channel 11 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR12,Host Channel 12 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT12,Host Channel 12 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT12,Host Channel 12 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK12,Host Channel 12 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ12,Host Channel 12 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA12,Host Channel 12 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x69C++0x1B
line.long 0x0 "HCDMAB12,Host Channel 12 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR13,Host Channel 13 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT13,Host Channel 13 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT13,Host Channel 13 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK13,Host Channel 13 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ13,Host Channel 13 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA13,Host Channel 13 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x6BC++0x1B
line.long 0x0 "HCDMAB13,Host Channel 13 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR14,Host Channel 14 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT14,Host Channel 14 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT14,Host Channel 14 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK14,Host Channel 14 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ14,Host Channel 14 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA14,Host Channel 14 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x6DC++0x1B
line.long 0x0 "HCDMAB14,Host Channel 14 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR15,Host Channel 15 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT15,Host Channel 15 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT15,Host Channel 15 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK15,Host Channel 15 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ15,Host Channel 15 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA15,Host Channel 15 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x6FC++0x3
line.long 0x0 "HCDMAB15,Host Channel 15 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
group.long 0x800++0x7
line.long 0x0 "DCFG,Device Configuration Register"
hexmask.long.byte 0x0 26.--31. 1. "ResValid,Resume Validation Period (ResValid)"
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bitfld.long 0x0 24.--25. "PerSchIntvl,Periodic Scheduling Interval (PerSchIntvl)" "0: 25% of,1: 50% of,2: 75% of,3: Reserved"
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bitfld.long 0x0 23. "DescDMA,Enable Scatter/gather DMA in device mode (DescDMA)." "0: Buffered DMA,1: Scatter/Gather DMA mode"
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rbitfld.long 0x0 16.--17. "RESERVED,RESERVED" "0,1,2,3"
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bitfld.long 0x0 15. "ErraticIntMsk,Erratic Error Interrupt Mask" "0: Early suspend interrupt is generated on erratic..,1: Mask early suspend interrupt on erratic error"
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bitfld.long 0x0 14. "XCVRDLY,1'b1: Enable delay between xcvr_sel and txvalid during Device chirp" "0: No delay between xcvr_sel and txvalid during..,1: Enable delay between xcvr_sel and txvalid during.."
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bitfld.long 0x0 13. "EnDevOutNak,Enable Device OUT NAK (EnDevOutNak)" "0: The core does not set NAK after Bulk OUT..,1: The core sets NAK after Bulk OUT transfer complete"
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bitfld.long 0x0 11.--12. "PerFrInt,Periodic Frame Interval (PerFrInt)" "0: 80% of the,1: 85%,2: 90%,3: 95%"
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hexmask.long.byte 0x0 4.--10. 1. "DevAddr,Device Address (DevAddr)"
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bitfld.long 0x0 3. "Ena32KHzSusp,Enable 32 KHz Suspend mode (Ena32KHzSusp)" "0,1"
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bitfld.long 0x0 2. "NZStsOUTHShk,Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)" "0: Send the received OUT packet to the application,1: Send a STALL handshake on a nonzero-length status"
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bitfld.long 0x0 0.--1. "DevSpd,Device Speed (DevSpd)" "0: High speed,1: Full speed,2: Low speed,3: Full speed"
line.long 0x4 "DCTL,Device Control Register"
hexmask.long.word 0x4 19.--31. 1. "RESERVED,RESERVED"
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bitfld.long 0x4 17. "EnContOnBNA,Enable Continue on BNA (EnContOnBNA)" "0: After receiving BNA interrupt,1: After receiving BNA interrupt"
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bitfld.long 0x4 16. "NakOnBble,NAK on Babble Error (NakOnBble)" "0,1"
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bitfld.long 0x4 15. "IgnrFrmNum,Ignore Frame number For Isochronous End points (IgnrFrmNum)" "0: periodic transfer interrupt feature is disabled,1: periodic transfer interrupt feature is enabled"
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bitfld.long 0x4 13.--14. "GMC,Global Multi Count (GMC)" "0: Invalid,1: 1 packet,2: 2 packets,3: 3 packets"
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bitfld.long 0x4 11. "PWROnPrgDone,Power-On Programming Done (PWROnPrgDone)" "0,1"
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bitfld.long 0x4 10. "CGOUTNak,Clear Global OUT NAK (CGOUTNak)" "0,1"
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bitfld.long 0x4 9. "SGOUTNak,Set Global OUT NAK (SGOUTNak)" "0,1"
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bitfld.long 0x4 8. "CGNPInNak,Clear Global Non-periodic IN NAK (CGNPInNak)" "0,1"
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bitfld.long 0x4 7. "SGNPInNak,Set Global Non-periodic IN NAK (SGNPInNak)" "0,1"
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bitfld.long 0x4 4.--6. "TstCtl,Test Control (TstCtl)" "0: Test mode disabled,1: Test_J mode,2: Test_K mode,3: Test_SE0_NAK mode,4: Test_Packet mode,5: Test_Force_Enable,?,?"
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rbitfld.long 0x4 3. "GOUTNakSts,Global OUT NAK Status (GOUTNakSts)" "0: A handshake is sent based on the FIFO Status and..,1: No data is written to the RxFIFO"
newline
rbitfld.long 0x4 2. "GNPINNakSts,Global Non-periodic IN NAK Status (GNPINNakSts)" "0: A handshake is sent out based on the data..,1: A NAK handshake is sent out on all non-periodic IN"
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bitfld.long 0x4 1. "SftDiscon,Soft Disconnect (SftDiscon)" "0: Normal operation,1: The core drives the phy_opmode_o signal on the"
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bitfld.long 0x4 0. "RmtWkUpSig,Remote Wakeup Signaling (RmtWkUpSig)" "0,1"
rgroup.long 0x808++0x3
line.long 0x0 "DSTS,Device Status Register"
hexmask.long.byte 0x0 24.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x0 22.--23. "DevLnSts,Device Line Status (DevLnSts)" "0,1,2,3"
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hexmask.long.word 0x0 8.--21. 1. "SOFFN,Frame or Microframe Number of the Received SOF (SOFFN)"
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hexmask.long.byte 0x0 4.--7. 1. "RESERVED1,RESERVED"
newline
bitfld.long 0x0 3. "ErrticErr,Erratic Error (ErrticErr)" "0,1"
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bitfld.long 0x0 1.--2. "EnumSpd,Enumerated Speed (EnumSpd)" "0: High speed,1: Full speed,2: Low speed,3: Full speed"
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bitfld.long 0x0 0. "SuspSts,Suspend Status (SuspSts)" "0,1"
group.long 0x810++0x7
line.long 0x0 "DIEPMSK,Device IN Endpoint Common Interrupt Mask Register"
hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED,RESERVED"
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bitfld.long 0x0 13. "NAKMsk,NAK interrupt Mask (NAKMsk)" "0,1"
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bitfld.long 0x0 9. "BNAInIntrMsk,BNA interrupt Mask (BNAInIntrMsk)" "0,1"
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bitfld.long 0x0 8. "TxfifoUndrnMsk,Fifo Underrun Mask (TxfifoUndrnMsk)" "0,1"
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rbitfld.long 0x0 7. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x0 6. "INEPNakEffMsk,IN Endpoint NAK Effective Mask (INEPNakEffMsk)" "0,1"
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bitfld.long 0x0 5. "INTknEPMisMsk,IN Token received with EP Mismatch Mask (INTknEPMisMsk)" "0,1"
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bitfld.long 0x0 4. "INTknTXFEmpMsk,IN Token Received When TxFIFO Empty Mask" "0,1"
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bitfld.long 0x0 3. "TimeOUTMsk,Timeout Condition Mask (TimeOUTMsk)" "0,1"
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bitfld.long 0x0 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
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bitfld.long 0x0 1. "EPDisbldMsk,Endpoint Disabled Interrupt Mask (EPDisbldMsk)" "0,1"
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bitfld.long 0x0 0. "XferComplMsk,Transfer Completed Interrupt Mask (XferComplMsk)" "0,1"
line.long 0x4 "DOEPMSK,Device OUT Endpoint Common Interrupt Mask Register"
hexmask.long.tbyte 0x4 15.--31. 1. "RESERVED,RESERVED"
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bitfld.long 0x4 14. "NYETMsk,NYET interrupt Mask (NYETMsk)" "0,1"
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bitfld.long 0x4 13. "NAKMsk,NAK interrupt Mask (NAKMsk)" "0,1"
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bitfld.long 0x4 12. "BbleErrMsk,Babble Error interrupt Mask (BbleErrMsk)" "0,1"
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bitfld.long 0x4 9. "BnaOutIntrMsk,BNA interrupt Mask (BnaOutIntrMsk)" "0,1"
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bitfld.long 0x4 8. "OutPktErrMsk,OUT Packet Error Mask (OutPktErrMsk)" "0,1"
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rbitfld.long 0x4 7. "RESERVED1,RESERVED" "0,1"
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bitfld.long 0x4 6. "Back2BackSETup,Back-to-Back SETUP Packets Received Mask" "0,1"
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bitfld.long 0x4 5. "StsPhseRcvdMsk,Status Phase Received Mask" "0,1"
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bitfld.long 0x4 4. "OUTTknEPdisMsk,OUT Token Received when Endpoint Disabled Mask" "0,1"
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bitfld.long 0x4 3. "SetUPMsk,SETUP Phase Done Mask (SetUPMsk)" "0,1"
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bitfld.long 0x4 2. "AHBErrMsk,AHB Error (AHBErrMsk)" "0,1"
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bitfld.long 0x4 1. "EPDisbldMsk,Endpoint Disabled Interrupt Mask (EPDisbldMsk)" "0,1"
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bitfld.long 0x4 0. "XferComplMsk,Transfer Completed Interrupt Mask (XferComplMsk)" "0,1"
rgroup.long 0x818++0x3
line.long 0x0 "DAINT,Device All Endpoints Interrupt Register"
bitfld.long 0x0 31. "OutEPInt15,OUT Endpoint 15 Interrupt Bit" "0,1"
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bitfld.long 0x0 30. "OutEPInt14,OUT Endpoint 14 Interrupt Bit" "0,1"
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bitfld.long 0x0 29. "OutEPInt13,OUT Endpoint 13 Interrupt Bit" "0,1"
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bitfld.long 0x0 28. "OutEPInt12,OUT Endpoint 12 Interrupt Bit" "0,1"
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bitfld.long 0x0 27. "OutEPInt11,OUT Endpoint 11 Interrupt Bit" "0,1"
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bitfld.long 0x0 26. "OutEPInt10,OUT Endpoint 10 Interrupt Bit" "0,1"
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bitfld.long 0x0 25. "OutEPInt9,OUT Endpoint 9 Interrupt Bit" "0,1"
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bitfld.long 0x0 24. "OutEPInt8,OUT Endpoint 8 Interrupt Bit" "0,1"
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bitfld.long 0x0 23. "OutEPInt7,OUT Endpoint 7 Interrupt Bit" "0,1"
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bitfld.long 0x0 22. "OutEPInt6,OUT Endpoint 6 Interrupt Bit" "0,1"
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bitfld.long 0x0 21. "OutEPInt5,OUT Endpoint 5 Interrupt Bit" "0,1"
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bitfld.long 0x0 20. "OutEPInt4,OUT Endpoint 4 Interrupt Bit" "0,1"
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bitfld.long 0x0 19. "OutEPInt3,OUT Endpoint 3 Interrupt Bit" "0,1"
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bitfld.long 0x0 18. "OutEPInt2,OUT Endpoint 2 Interrupt Bit" "0,1"
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bitfld.long 0x0 17. "OutEPInt1,OUT Endpoint 1 Interrupt Bit" "0,1"
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bitfld.long 0x0 16. "OutEPInt0,OUT Endpoint 0 Interrupt Bit" "0,1"
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bitfld.long 0x0 15. "InEpInt15,IN Endpoint 15 Interrupt Bit" "0,1"
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bitfld.long 0x0 14. "InEpInt14,IN Endpoint 14 Interrupt Bit" "0,1"
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bitfld.long 0x0 13. "InEpInt13,IN Endpoint 13 Interrupt Bit" "0,1"
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bitfld.long 0x0 12. "InEpInt12,IN Endpoint 12 Interrupt Bit" "0,1"
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bitfld.long 0x0 11. "InEpInt11,IN Endpoint 11 Interrupt Bit" "0,1"
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bitfld.long 0x0 10. "InEpInt10,IN Endpoint 10 Interrupt Bit" "0,1"
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bitfld.long 0x0 9. "InEpInt9,IN Endpoint 9 Interrupt Bit" "0,1"
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bitfld.long 0x0 8. "InEpInt8,IN Endpoint 8 Interrupt Bit" "0,1"
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bitfld.long 0x0 7. "InEpInt7,IN Endpoint 7 Interrupt Bit" "0,1"
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bitfld.long 0x0 6. "InEpInt6,IN Endpoint 6 Interrupt Bit" "0,1"
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bitfld.long 0x0 5. "InEpInt5,IN Endpoint 5 Interrupt Bit" "0,1"
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bitfld.long 0x0 4. "InEpInt4,IN Endpoint 4 Interrupt Bit" "0,1"
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bitfld.long 0x0 3. "InEpInt3,IN Endpoint 3 Interrupt Bit" "0,1"
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bitfld.long 0x0 2. "InEpInt2,IN Endpoint 2 Interrupt Bit" "0,1"
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bitfld.long 0x0 1. "InEpInt1,IN Endpoint 1 Interrupt Bit" "0,1"
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bitfld.long 0x0 0. "InEpInt0,IN Endpoint 0 Interrupt Bit" "0,1"
group.long 0x81C++0x3
line.long 0x0 "DAINTMSK,Device All Endpoints Interrupt Mask Register"
bitfld.long 0x0 31. "OutEPMsk15,OUT Endpoint 15 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 30. "OutEPMsk14,OUT Endpoint 14 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 29. "OutEPMsk13,OUT Endpoint 13 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 28. "OutEPMsk12,OUT Endpoint 12 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 27. "OutEPMsk11,OUT Endpoint 11 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 26. "OutEPMsk10,OUT Endpoint 10 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 25. "OutEPMsk9,OUT Endpoint 9 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 24. "OutEPMsk8,OUT Endpoint 8 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 23. "OutEPMsk7,OUT Endpoint 7 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 22. "OutEPMsk6,OUT Endpoint 6 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 21. "OutEPMsk5,OUT Endpoint 5 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 20. "OutEPMsk4,OUT Endpoint 4 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 19. "OutEPMsk3,OUT Endpoint 3 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 18. "OutEPMsk2,OUT Endpoint 2 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 17. "OutEPMsk1,OUT Endpoint 1 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 16. "OutEPMsk0,OUT Endpoint 0 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 15. "InEpMsk15,IN Endpoint 15 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 14. "InEpMsk14,IN Endpoint 14 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 13. "InEpMsk13,IN Endpoint 13 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 12. "InEpMsk12,IN Endpoint 12 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 11. "InEpMsk11,IN Endpoint 11 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 10. "InEpMsk10,IN Endpoint 10 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 9. "InEpMsk9,IN Endpoint 9 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 8. "InEpMsk8,IN Endpoint 8 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 7. "InEpMsk7,IN Endpoint 7 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 6. "InEpMsk6,IN Endpoint 6 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 5. "InEpMsk5,IN Endpoint 5 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 4. "InEpMsk4,IN Endpoint 4 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 3. "InEpMsk3,IN Endpoint 3 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 2. "InEpMsk2,IN Endpoint 2 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 1. "InEpMsk1,IN Endpoint 1 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 0. "InEpMsk0,IN Endpoint 0 Interrupt mask Bit" "0,1"
group.long 0x828++0xF
line.long 0x0 "DVBUSDIS,Device VBUS Discharge Time Register"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "DVBUSDis,Device VBUS Discharge Time (DVBUSDis)"
line.long 0x4 "DVBUSPULSE,Device VBUS Pulsing Time Register"
hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x4 0.--11. 1. "DVBUSPulse,Device VBUS Pulsing Time (DVBUSPulse)"
line.long 0x8 "DTHRCTL,Device Threshold Control Register"
hexmask.long.byte 0x8 28.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 27. "ArbPrkEn,Arbiter Parking Enable (ArbPrkEn)" "0,1"
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rbitfld.long 0x8 26. "RESERVED1,RESERVED" "0,1"
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hexmask.long.word 0x8 17.--25. 1. "RxThrLen,Receive Threshold Length (RxThrLen)"
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bitfld.long 0x8 16. "RxThrEn,Receive Threshold Enable (RxThrEn)" "0,1"
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rbitfld.long 0x8 13.--15. "RESERVED2,RESERVED" "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 11.--12. "AHBThrRatio,AHB Threshold Ratio (AHBThrRatio)" "0: AHB threshold = MAC threshold,1: AHB threshold = MAC threshold / 2,2: AHB threshold = MAC threshold / 4,3: AHB threshold = MAC threshold / 8"
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hexmask.long.word 0x8 2.--10. 1. "TxThrLen,Transmit Threshold Length (TxThrLen)"
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bitfld.long 0x8 1. "ISOThrEn,ISO IN Endpoints Threshold Enable. (ISOThrEn)" "0,1"
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bitfld.long 0x8 0. "NonISOThrEn,Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn)" "0,1"
line.long 0xC "DIEPEMPMSK,Device IN Endpoint FIFO Empty Interrupt Mask Register"
hexmask.long.word 0xC 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0xC 0.--15. 1. "InEpTxfEmpMsk,IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk)"
group.long 0x900++0x3
line.long 0x0 "DIEPCTL0,Device Control IN Endpoint 0 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
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bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
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rbitfld.long 0x0 28.--29. "RESERVED,RESERVED" "0,1,2,3"
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bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
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bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
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hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
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rbitfld.long 0x0 20. "RESERVED1,RESERVED" "0,1"
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rbitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0,1,2,3"
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rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
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rbitfld.long 0x0 16. "RESERVED2,RESERVED" "0,1"
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rbitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
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hexmask.long.word 0x0 2.--10. 1. "RESERVED3,RESERVED"
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bitfld.long 0x0 0.--1. "MPS,Maximum Packet Size (MPS)" "0: 64 bytes,1: 32 bytes,2: 16 bytes,3: 8 bytes"
group.long 0x908++0x3
line.long 0x0 "DIEPINT0,Device IN Endpoint 0 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
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eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
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eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x910++0x7
line.long 0x0 "DIEPTSIZ0,Device IN Endpoint 0 Transfer Size Register"
hexmask.long.word 0x0 21.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x0 19.--20. "PktCnt,Packet Count (PktCnt)" "0,1,2,3"
newline
hexmask.long.word 0x0 7.--18. 1. "RESERVED1,RESERVED"
newline
hexmask.long.byte 0x0 0.--6. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA0,Device IN Endpoint 0 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x918++0x7
line.long 0x0 "DTXFSTS0,Device IN Endpoint Transmit FIFO Status Register 0"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB0,Device IN Endpoint 16 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x920++0x3
line.long 0x0 "DIEPCTL1,Device Control IN Endpoint 1 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x928++0x3
line.long 0x0 "DIEPINT1,Device IN Endpoint 1 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x930++0x7
line.long 0x0 "DIEPTSIZ1,Device IN Endpoint 1 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA1,Device IN Endpoint 1 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x938++0x7
line.long 0x0 "DTXFSTS1,Device IN Endpoint Transmit FIFO Status Register 1"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB1,Device IN Endpoint 1 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x940++0x3
line.long 0x0 "DIEPCTL2,Device Control IN Endpoint 2 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x948++0x3
line.long 0x0 "DIEPINT2,Device IN Endpoint 2 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x950++0x7
line.long 0x0 "DIEPTSIZ2,Device IN Endpoint 2 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA2,Device IN Endpoint 2 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x958++0x7
line.long 0x0 "DTXFSTS2,Device IN Endpoint Transmit FIFO Status Register 2"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB2,Device IN Endpoint 2 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x960++0x3
line.long 0x0 "DIEPCTL3,Device Control IN Endpoint 3 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x968++0x3
line.long 0x0 "DIEPINT3,Device IN Endpoint 3 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x970++0x7
line.long 0x0 "DIEPTSIZ3,Device IN Endpoint 3 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA3,Device IN Endpoint 3 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x978++0x7
line.long 0x0 "DTXFSTS3,Device IN Endpoint Transmit FIFO Status Register 3"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB3,Device IN Endpoint 3 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x980++0x3
line.long 0x0 "DIEPCTL4,Device Control IN Endpoint 4 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x988++0x3
line.long 0x0 "DIEPINT4,Device IN Endpoint 4 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x990++0x7
line.long 0x0 "DIEPTSIZ4,Device IN Endpoint 4 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA4,Device IN Endpoint 4 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x998++0x7
line.long 0x0 "DTXFSTS4,Device IN Endpoint Transmit FIFO Status Register 4"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB4,Device IN Endpoint 4 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x9A0++0x3
line.long 0x0 "DIEPCTL5,Device Control IN Endpoint 5 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x9A8++0x3
line.long 0x0 "DIEPINT5,Device IN Endpoint 5 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x9B0++0x7
line.long 0x0 "DIEPTSIZ5,Device IN Endpoint 5 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA5,Device IN Endpoint 5 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x9B8++0x7
line.long 0x0 "DTXFSTS5,Device IN Endpoint Transmit FIFO Status Register 5"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB5,Device IN Endpoint 5 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x9C0++0x3
line.long 0x0 "DIEPCTL6,Device Control IN Endpoint 6 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x9C8++0x3
line.long 0x0 "DIEPINT6,Device IN Endpoint 6 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x9D0++0x7
line.long 0x0 "DIEPTSIZ6,Device IN Endpoint 6 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA6,Device IN Endpoint 6 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x9D8++0x7
line.long 0x0 "DTXFSTS6,Device IN Endpoint Transmit FIFO Status Register 6"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB6,Device IN Endpoint 6 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x9E0++0x3
line.long 0x0 "DIEPCTL7,Device Control IN Endpoint 7 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x9E8++0x3
line.long 0x0 "DIEPINT7,Device IN Endpoint 7 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x9F0++0x7
line.long 0x0 "DIEPTSIZ7,Device IN Endpoint 7 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA7,Device IN Endpoint 7 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x9F8++0x7
line.long 0x0 "DTXFSTS7,Device IN Endpoint Transmit FIFO Status Register 7"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB7,Device IN Endpoint 7 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xA00++0x3
line.long 0x0 "DIEPCTL8,Device Control IN Endpoint 8 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xA08++0x3
line.long 0x0 "DIEPINT8,Device IN Endpoint 8 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xA10++0x7
line.long 0x0 "DIEPTSIZ8,Device IN Endpoint 8 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA8,Device IN Endpoint 8 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xA18++0x7
line.long 0x0 "DTXFSTS8,Device IN Endpoint Transmit FIFO Status Register 8"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB8,Device IN Endpoint 8 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xA20++0x3
line.long 0x0 "DIEPCTL9,Device Control IN Endpoint 9 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xA28++0x3
line.long 0x0 "DIEPINT9,Device IN Endpoint 9 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xA30++0x7
line.long 0x0 "DIEPTSIZ9,Device IN Endpoint 9 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA9,Device IN Endpoint 9 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xA38++0x7
line.long 0x0 "DTXFSTS9,Device IN Endpoint Transmit FIFO Status Register 9"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB9,Device IN Endpoint 9 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xA40++0x3
line.long 0x0 "DIEPCTL10,Device Control IN Endpoint 10 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xA48++0x3
line.long 0x0 "DIEPINT10,Device IN Endpoint 10 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xA50++0x7
line.long 0x0 "DIEPTSIZ10,Device IN Endpoint 10 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA10,Device IN Endpoint 10 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xA58++0x7
line.long 0x0 "DTXFSTS10,Device IN Endpoint Transmit FIFO Status Register 10"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB10,Device IN Endpoint 10 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xA60++0x3
line.long 0x0 "DIEPCTL11,Device Control IN Endpoint 11 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xA68++0x3
line.long 0x0 "DIEPINT11,Device IN Endpoint 11 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xA70++0x7
line.long 0x0 "DIEPTSIZ11,Device IN Endpoint 11 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA11,Device IN Endpoint 11 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xA78++0x7
line.long 0x0 "DTXFSTS11,Device IN Endpoint Transmit FIFO Status Register 11"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB11,Device IN Endpoint 11 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xA80++0x3
line.long 0x0 "DIEPCTL12,Device Control IN Endpoint 12 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xA88++0x3
line.long 0x0 "DIEPINT12,Device IN Endpoint 12 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xA90++0x7
line.long 0x0 "DIEPTSIZ12,Device IN Endpoint 12 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA12,Device IN Endpoint 12 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xA98++0x7
line.long 0x0 "DTXFSTS12,Device IN Endpoint Transmit FIFO Status Register 12"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB12,Device IN Endpoint 12 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xAA0++0x3
line.long 0x0 "DIEPCTL13,Device Control IN Endpoint 13 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xAA8++0x3
line.long 0x0 "DIEPINT13,Device IN Endpoint 13 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xAB0++0x7
line.long 0x0 "DIEPTSIZ13,Device IN Endpoint 13 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA13,Device IN Endpoint 13 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xAB8++0x7
line.long 0x0 "DTXFSTS13,Device IN Endpoint Transmit FIFO Status Register 13"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB13,Device IN Endpoint 13 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xAC0++0x3
line.long 0x0 "DIEPCTL14,Device Control IN Endpoint 14 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xAC8++0x3
line.long 0x0 "DIEPINT14,Device IN Endpoint 14 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xAD0++0x7
line.long 0x0 "DIEPTSIZ14,Device IN Endpoint 14 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA14,Device IN Endpoint 14 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xAD8++0x7
line.long 0x0 "DTXFSTS14,Device IN Endpoint Transmit FIFO Status Register 14"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB14,Device IN Endpoint 14 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xAE0++0x3
line.long 0x0 "DIEPCTL15,Device Control IN Endpoint 15 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xAE8++0x3
line.long 0x0 "DIEPINT15,Device IN Endpoint 15 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xAF0++0x7
line.long 0x0 "DIEPTSIZ15,Device IN Endpoint 15 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA15,Device IN Endpoint 15 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xAF8++0x7
line.long 0x0 "DTXFSTS15,Device IN Endpoint Transmit FIFO Status Register 15"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB15,Device IN Endpoint 15 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xB00++0x3
line.long 0x0 "DOEPCTL0,Device Control OUT Endpoint 0 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
rbitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
rbitfld.long 0x0 28.--29. "RESERVED,RESERVED" "0,1,2,3"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "RESERVED1,RESERVED"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
rbitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0,1,2,3"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes based,1: The core is transmitting NAK handshakes on this"
newline
rbitfld.long 0x0 16. "RESERVED2,RESERVED" "0,1"
newline
rbitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 2.--14. 1. "RESERVED3,RESERVED"
newline
rbitfld.long 0x0 0.--1. "MPS,Maximum Packet Size (MPS)" "0: 64 bytes,1: 32 bytes,2: 16 bytes,3: 8 bytes"
group.long 0xB08++0x3
line.long 0x0 "DOEPINT0,Device OUT Endpoint 0 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB10++0x7
line.long 0x0 "DOEPTSIZ0,Device OUT Endpoint 0 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "SUPCnt,SETUP Packet Count (SUPCnt)" "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 20.--28. 1. "RESERVED1,RESERVED"
newline
bitfld.long 0x0 19. "PktCnt,Packet Count (PktCnt)" "0,1"
newline
hexmask.long.word 0x0 7.--18. 1. "RESERVED2,RESERVED"
newline
hexmask.long.byte 0x0 0.--6. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA0,Device OUT Endpoint 0 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xB1C++0x3
line.long 0x0 "DOEPDMAB0,Device OUT Endpoint 16 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xB20++0x3
line.long 0x0 "DOEPCTL1,Device Control OUT Endpoint 1 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xB28++0x3
line.long 0x0 "DOEPINT1,Device OUT Endpoint 1 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB30++0x7
line.long 0x0 "DOEPTSIZ1,Device OUT Endpoint 1 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA1,Device OUT Endpoint 1 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xB3C++0x3
line.long 0x0 "DOEPDMAB1,Device OUT Endpoint 1 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xB40++0x3
line.long 0x0 "DOEPCTL2,Device Control OUT Endpoint 2 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xB48++0x3
line.long 0x0 "DOEPINT2,Device OUT Endpoint 2 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB50++0x7
line.long 0x0 "DOEPTSIZ2,Device OUT Endpoint 2 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA2,Device OUT Endpoint 2 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xB5C++0x3
line.long 0x0 "DOEPDMAB2,Device OUT Endpoint 2 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xB60++0x3
line.long 0x0 "DOEPCTL3,Device Control OUT Endpoint 3 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xB68++0x3
line.long 0x0 "DOEPINT3,Device OUT Endpoint 3 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB70++0x7
line.long 0x0 "DOEPTSIZ3,Device OUT Endpoint 3 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA3,Device OUT Endpoint 3 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xB7C++0x3
line.long 0x0 "DOEPDMAB3,Device OUT Endpoint 3 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xB80++0x3
line.long 0x0 "DOEPCTL4,Device Control OUT Endpoint 4 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xB88++0x3
line.long 0x0 "DOEPINT4,Device OUT Endpoint 4 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB90++0x7
line.long 0x0 "DOEPTSIZ4,Device OUT Endpoint 4 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA4,Device OUT Endpoint 4 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xB9C++0x3
line.long 0x0 "DOEPDMAB4,Device OUT Endpoint 4 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xBA0++0x3
line.long 0x0 "DOEPCTL5,Device Control OUT Endpoint 5 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xBA8++0x3
line.long 0x0 "DOEPINT5,Device OUT Endpoint 5 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xBB0++0x7
line.long 0x0 "DOEPTSIZ5,Device OUT Endpoint 5 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA5,Device OUT Endpoint 5 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xBBC++0x3
line.long 0x0 "DOEPDMAB5,Device OUT Endpoint 5 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xBC0++0x3
line.long 0x0 "DOEPCTL6,Device Control OUT Endpoint 6 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xBC8++0x3
line.long 0x0 "DOEPINT6,Device OUT Endpoint 6 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xBD0++0x7
line.long 0x0 "DOEPTSIZ6,Device OUT Endpoint 6 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA6,Device OUT Endpoint 6 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xBDC++0x3
line.long 0x0 "DOEPDMAB6,Device OUT Endpoint 6 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xBE0++0x3
line.long 0x0 "DOEPCTL7,Device Control OUT Endpoint 7 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xBE8++0x3
line.long 0x0 "DOEPINT7,Device OUT Endpoint 7 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xBF0++0x7
line.long 0x0 "DOEPTSIZ7,Device OUT Endpoint 7 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA7,Device OUT Endpoint 7 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xBFC++0x3
line.long 0x0 "DOEPDMAB7,Device OUT Endpoint 7 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xC00++0x3
line.long 0x0 "DOEPCTL8,Device Control OUT Endpoint 8 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xC08++0x3
line.long 0x0 "DOEPINT8,Device OUT Endpoint 8 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xC10++0x7
line.long 0x0 "DOEPTSIZ8,Device OUT Endpoint 8 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA8,Device OUT Endpoint 8 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xC1C++0x3
line.long 0x0 "DOEPDMAB8,Device OUT Endpoint 8 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xC20++0x3
line.long 0x0 "DOEPCTL9,Device Control OUT Endpoint 9 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xC28++0x3
line.long 0x0 "DOEPINT9,Device OUT Endpoint 9 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xC30++0x7
line.long 0x0 "DOEPTSIZ9,Device OUT Endpoint 9 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA9,Device OUT Endpoint 9 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xC3C++0x3
line.long 0x0 "DOEPDMAB9,Device OUT Endpoint 9 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xC40++0x3
line.long 0x0 "DOEPCTL10,Device Control OUT Endpoint 10 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xC48++0x3
line.long 0x0 "DOEPINT10,Device OUT Endpoint 10 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xC50++0x7
line.long 0x0 "DOEPTSIZ10,Device OUT Endpoint 10 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA10,Device OUT Endpoint 10 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xC5C++0x3
line.long 0x0 "DOEPDMAB10,Device OUT Endpoint 10 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xC60++0x3
line.long 0x0 "DOEPCTL11,Device Control OUT Endpoint 11 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xC68++0x3
line.long 0x0 "DOEPINT11,Device OUT Endpoint 11 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xC70++0x7
line.long 0x0 "DOEPTSIZ11,Device OUT Endpoint 11 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA11,Device OUT Endpoint 11 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xC7C++0x3
line.long 0x0 "DOEPDMAB11,Device OUT Endpoint 11 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xC80++0x3
line.long 0x0 "DOEPCTL12,Device Control OUT Endpoint 12 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xC88++0x3
line.long 0x0 "DOEPINT12,Device OUT Endpoint 12 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xC90++0x7
line.long 0x0 "DOEPTSIZ12,Device OUT Endpoint 12 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA12,Device OUT Endpoint 12 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xC9C++0x3
line.long 0x0 "DOEPDMAB12,Device OUT Endpoint 12 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xCA0++0x3
line.long 0x0 "DOEPCTL13,Device Control OUT Endpoint 13 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xCA8++0x3
line.long 0x0 "DOEPINT13,Device OUT Endpoint 13 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xCB0++0x7
line.long 0x0 "DOEPTSIZ13,Device OUT Endpoint 13 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA13,Device OUT Endpoint 13 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xCBC++0x3
line.long 0x0 "DOEPDMAB13,Device OUT Endpoint 13 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xCC0++0x3
line.long 0x0 "DOEPCTL14,Device Control OUT Endpoint 14 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xCC8++0x3
line.long 0x0 "DOEPINT14,Device OUT Endpoint 14 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xCD0++0x7
line.long 0x0 "DOEPTSIZ14,Device OUT Endpoint 14 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA14,Device OUT Endpoint 14 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xCDC++0x3
line.long 0x0 "DOEPDMAB14,Device OUT Endpoint 14 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xCE0++0x3
line.long 0x0 "DOEPCTL15,Device Control OUT Endpoint 15 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xCE8++0x3
line.long 0x0 "DOEPINT15,Device OUT Endpoint 15 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xCF0++0x7
line.long 0x0 "DOEPTSIZ15,Device OUT Endpoint 15 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA15,Device OUT Endpoint 15 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xCFC++0x3
line.long 0x0 "DOEPDMAB15,Device OUT Endpoint 15 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xE00++0x3
line.long 0x0 "PCGCCTL,Power and Clock Gating Control Register"
rbitfld.long 0x0 7. "L1Suspended,L1 Deep Sleep" "0,1"
newline
rbitfld.long 0x0 6. "PhySleep,PHY In Sleep" "0,1"
newline
bitfld.long 0x0 3. "RstPdwnModule,Reset Power-Down Modules (RstPdwnModule)" "0,1"
newline
bitfld.long 0x0 0. "StopPclk,Stop Pclk (StopPclk)" "0,1"
tree.end
tree "USB1 (USB1 OTG Controller Module Registers)"
base ad:0xFFB40000
group.long 0x0++0x1B
line.long 0x0 "GOTGCTL,OTG Control and Status Register"
hexmask.long.byte 0x0 28.--31. 1. "RESERVED,RESERVED"
newline
rbitfld.long 0x0 21. "CurMod,Mode: Host and Device" "0: Device mode,1: Host mode"
newline
bitfld.long 0x0 20. "OTGVer,OTG Version (OTGVer)" "0: OTG Version 1,1: OTG Version 2"
newline
rbitfld.long 0x0 19. "BSesVld,Mode: Device only" "0: B-session is not valid,1: B-session is valid"
newline
rbitfld.long 0x0 18. "ASesVld,Mode: Host only" "0: A-session is not valid,1: A-session is valid"
newline
rbitfld.long 0x0 17. "DbncTime,Mode: Host only" "0: Long debounce time,1: Short debounce time"
newline
rbitfld.long 0x0 16. "ConIDSts,Mode: Host and Device" "0: The DWC_otg core is in A-Device mode,1: The DWC_otg core is in B-Device mode"
newline
bitfld.long 0x0 12. "EHEn,Mode: SRP Capable Host" "0: Disable Embedded Host Mode,1: Enable Embedded Host Mode"
newline
bitfld.long 0x0 11. "DevHNPEn,Mode: Device only" "0: HNP is not enabled in the application,1: HNP is enabled in the application"
newline
bitfld.long 0x0 10. "HstSetHNPEn,Mode: Host only" "0: Host Set HNP is not enabled,1: Host Set HNP is enabled"
newline
bitfld.long 0x0 9. "HNPReq,Mode: Device only" "0: No HNP request,1: HNP request"
newline
rbitfld.long 0x0 8. "HstNegScs,Mode: Device only" "0: Host negotiation failure,1: Host negotiation success"
newline
bitfld.long 0x0 7. "BvalidOvVal,B-Peripheral Session Valid OverrideValue (BvalidOvVal)" "0: Bvalid value is 1'b0 when GOTGCTL,1: Bvalid value is 1'b1 when GOTGCTL"
newline
bitfld.long 0x0 6. "BvalidOvEn,B-Peripheral Session Valid Override Enable (BvalidOvEn)" "0: Override is disabled and bvalid signal from the..,1: Internally Bvalid received from the PHY is.."
newline
bitfld.long 0x0 5. "AvalidOvVal,A-Peripheral Session Valid OverrideValue (AvalidOvVal)" "0: Avalid value is 1'b0 when GOTGCTL,1: Avalid value is 1'b1 when GOTGCTL"
newline
bitfld.long 0x0 4. "AvalidOvEn,A-Peripheral Session Valid Override Enable (AvalidOvEn)" "0: Override is disabled and avalid signal from the..,1: Internally Avalid received from the PHY is.."
newline
bitfld.long 0x0 3. "VbvalidOvVal,VBUS Valid OverrideValue (VbvalidOvVal)" "0: vbusvalid value is 1'b0 when GOTGCTL,1: vbusvalid value is 1'b1 when GOTGCTL"
newline
bitfld.long 0x0 2. "VbvalidOvEn,VBUS Valid Override Enable (VbvalidOvEn)" "0: Override is disabled and bvalid signal from the..,1: Internally Bvalid received from the PHY is.."
newline
bitfld.long 0x0 1. "SesReq,Mode: Device only" "0: No session request,1: Session request"
newline
rbitfld.long 0x0 0. "SesReqScs,Mode: Device only" "0: Session request failure,1: Session request success"
line.long 0x4 "GOTGINT,OTG Interrupt Register"
hexmask.long.word 0x4 21.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x4 19. "DbnceDone,Mode: Host only" "0,1"
newline
eventfld.long 0x4 18. "ADevTOUTChg,Mode:Host and Device" "0,1"
newline
eventfld.long 0x4 17. "HstNegDet,Mode:Host and Device" "0,1"
newline
hexmask.long.byte 0x4 10.--16. 1. "RESERVED1,RESERVED"
newline
eventfld.long 0x4 9. "HstNegSucStsChng,Mode:Host and Device" "0,1"
newline
eventfld.long 0x4 8. "SesReqSucStsChng,Mode:Host and Device" "0,1"
newline
hexmask.long.byte 0x4 3.--7. 1. "RESERVED2,RESERVED"
newline
eventfld.long 0x4 2. "SesEndDet,Mode:Host and Device" "0,1"
newline
rbitfld.long 0x4 0.--1. "RESERVED3,RESERVED" "0,1,2,3"
line.long 0x8 "GAHBCFG,AHB Configuration Register"
hexmask.long.byte 0x8 25.--31. 1. "RESERVED1,RESERVED"
newline
bitfld.long 0x8 24. "InvDescEndianess,Invert Descriptor Endianess (InvDescEndianess)" "0: Descriptor Endianness is same as AHB Master..,1: Descriptor Endianness is Little Endian if AHB.."
newline
bitfld.long 0x8 23. "AHBSingle,AHB Single Support (AHBSingle)" "0: The remaining data in the transfer is sent using..,1: The remaining data in the transfer is sent using.."
newline
bitfld.long 0x8 22. "NotiAllDmaWrit,Notify All Dma Write Transactions (NotiAllDmaWrit)" "0,1"
newline
bitfld.long 0x8 21. "RemMemSupp,Remote Memory Support (RemMemSupp)" "0,1"
newline
bitfld.long 0x8 8. "PTxFEmpLvl,Mode:Host only" "0: GINTSTS,1: GINTSTS"
newline
bitfld.long 0x8 7. "NPTxFEmpLvl,Mode:Host and device" "0: DIEPINTn,1: DIEPINTn"
newline
rbitfld.long 0x8 6. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x8 5. "DMAEn,Mode:Host and device" "0: Core operates in Slave mode,1: Core operates in a DMA mode"
newline
hexmask.long.byte 0x8 1.--4. 1. "HBstLen,Mode:Host and device"
newline
bitfld.long 0x8 0. "GlblIntrMsk,Mode:Host and device" "0: Mask the interrupt assertion to the application,1: Unmask the interrupt assertion to the application"
line.long 0xC "GUSBCFG,USB Configuration Register"
bitfld.long 0xC 31. "CorruptTxPkt,Mode:Host and device" "0,1"
newline
bitfld.long 0xC 30. "ForceDevMode,Mode:Host and device" "0: Normal Mode,1: Force Device Mode"
newline
bitfld.long 0xC 29. "ForceHstMode,Mode:Host and device" "0: Normal Mode,1: Force Host Mode"
newline
bitfld.long 0xC 28. "TxEndDelay,Mode: Device only" "0: Normal Mode,1: Tx End delay"
newline
rbitfld.long 0xC 26. "IC_USBCap,IC_USB-Capable (IC_USBCap)" "0: IC_USB PHY Interface is not selected,1: IC_USB PHY Interface is selected"
newline
bitfld.long 0xC 25. "ULPI,Mode:Host only" "0: Enables the interface protect circuit,1: Disables the interface protect circuit"
newline
bitfld.long 0xC 24. "Indicator,Mode:Host only" "0: Complement Output signal is qualified with the..,1: Complement Output signal is not qualified with the"
newline
bitfld.long 0xC 23. "Complement,Mode:Host only" "0: PHY does not invert ExternalVbusIndicator signal,1: PHY does invert ExternalVbusIndicator signal"
newline
bitfld.long 0xC 22. "TermSelDLPulse,Mode:Device only" "0: Data line pulsing using utmi_txvalid,1: Data line pulsing using utmi_termsel"
newline
bitfld.long 0xC 21. "ULPIExtVbusIndicator,Mode:Host only" "0: PHY uses internal VBUS valid comparator,1: PHY uses external VBUS valid comparator"
newline
bitfld.long 0xC 20. "ULPIExtVbusDrv,Mode:Host only" "0: PHY drives VBUS using internal charge pump,1: PHY drives VBUS using external supply"
newline
bitfld.long 0xC 19. "ULPIClkSusM,Mode:Host and Device" "0: PHY powers down internal clock during suspend,1: PHY does not power down internal clock"
newline
bitfld.long 0xC 18. "ULPIAutoRes,Mode:Host and Device" "0: PHY does not use AutoResume feature,1: PHY uses AutoResume feature"
newline
rbitfld.long 0xC 14. "RESERVED,RESERVED" "0,1"
newline
hexmask.long.byte 0xC 10.--13. 1. "USBTrdTim,Mode: Device only"
newline
bitfld.long 0xC 9. "HNPCap,Mode:Host and Device" "0: HNP capability is not enabled,1: HNP capability is enabled"
newline
bitfld.long 0xC 8. "SRPCap,Mode:Host and Device" "0: SRP capability is not enabled,1: SRP capability is enabled"
newline
bitfld.long 0xC 7. "DDRSel,Mode:Host and Device" "0: Single Data Rate ULPI Interface,1: Double Data Rate ULPI Interface"
newline
rbitfld.long 0xC 6. "PHYSel,Mode:Host and Device" "0: USB 2,1: USB 1"
newline
rbitfld.long 0xC 5. "FSIntf,Mode:Host and Device" "0: 6-pin unidirectional full-speed serial interface,1: 3-pin bidirectional full-speed serial interface"
newline
rbitfld.long 0xC 4. "ULPI_UTMI_Sel,Mode:Host and Device" "0: UTMI+ Interface,1: ULPI Interface"
newline
rbitfld.long 0xC 3. "PHYIf,Mode:Host and Device" "0: 8 bits,1: 16 bits"
newline
bitfld.long 0xC 0.--2. "TOutCal,Mode:Host and Device" "0,1,2,3,4,5,6,7"
line.long 0x10 "GRSTCTL,Reset Register"
rbitfld.long 0x10 31. "AHBIdle,Mode:Host and Device" "0,1"
newline
rbitfld.long 0x10 30. "DMAReq,Mode:Host and Device" "0,1"
newline
hexmask.long.tbyte 0x10 11.--29. 1. "RESERVED,RESERVED"
newline
hexmask.long.byte 0x10 6.--10. 1. "TxFNum,Mode:Host and Device"
newline
bitfld.long 0x10 5. "TxFFlsh,Mode:Host and Device" "0,1"
newline
bitfld.long 0x10 4. "RxFFlsh,Mode:Host and Device" "0,1"
newline
bitfld.long 0x10 2. "FrmCntrRst,Mode:Host only" "0,1"
newline
bitfld.long 0x10 1. "PIUFSSftRst,Mode:Host and Device" "0,1"
newline
bitfld.long 0x10 0. "CSftRst,Mode:Host and Device" "0,1"
line.long 0x14 "GINTSTS,Interrupt Register"
eventfld.long 0x14 31. "WkUpInt,Mode:Host and Device" "0,1"
newline
eventfld.long 0x14 30. "SessReqInt,Mode:Host and Device" "0,1"
newline
eventfld.long 0x14 29. "DisconnInt,Mode:Host only" "0,1"
newline
eventfld.long 0x14 28. "ConIDStsChng,Mode:Host and Device" "0,1"
newline
rbitfld.long 0x14 26. "PTxFEmp,Mode:Host only" "0,1"
newline
rbitfld.long 0x14 25. "HChInt,Mode:Host only" "0,1"
newline
rbitfld.long 0x14 24. "PrtInt,Mode:Host only" "0,1"
newline
eventfld.long 0x14 23. "ResetDet,Mode: Device only" "0,1"
newline
eventfld.long 0x14 22. "FetSusp,Mode: Device only" "0,1"
newline
eventfld.long 0x14 21. "incomplP,Incomplete Periodic Transfer (incomplP)" "0,1"
newline
eventfld.long 0x14 20. "incompISOIN,Mode: Device only" "0,1"
newline
rbitfld.long 0x14 19. "OEPInt,Mode: Device only" "0,1"
newline
rbitfld.long 0x14 18. "IEPInt,Mode: Device only" "0,1"
newline
eventfld.long 0x14 17. "EPMis,Mode: Device only" "0,1"
newline
eventfld.long 0x14 15. "EOPF,Mode: Device only" "0,1"
newline
eventfld.long 0x14 14. "ISOOutDrop,Mode: Device only" "0,1"
newline
eventfld.long 0x14 13. "EnumDone,Mode: Device only" "0,1"
newline
eventfld.long 0x14 12. "USBRst,Mode: Device only" "0,1"
newline
eventfld.long 0x14 11. "USBSusp,Mode: Device only" "0,1"
newline
eventfld.long 0x14 10. "ErlySusp,Mode: Device only" "0,1"
newline
rbitfld.long 0x14 7. "GOUTNakEff,Mode: Device only" "0,1"
newline
rbitfld.long 0x14 6. "GINNakEff,Mode: Device only" "0,1"
newline
rbitfld.long 0x14 5. "NPTxFEmp,Mode: Host and Device" "0,1"
newline
rbitfld.long 0x14 4. "RxFLvl,Mode: Host and Device" "0,1"
newline
eventfld.long 0x14 3. "Sof,Mode: Host and Device" "0,1"
newline
rbitfld.long 0x14 2. "OTGInt,Mode: Host and Device" "0,1"
newline
eventfld.long 0x14 1. "ModeMis,Mode: Host and Device" "0,1"
newline
rbitfld.long 0x14 0. "CurMod,Mode: Host and Device" "0: Device mode,1: Host mode"
line.long 0x18 "GINTMSK,Interrupt Mask Register"
bitfld.long 0x18 31. "WkUpIntMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 30. "SessReqIntMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 29. "DisconnIntMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 28. "ConIDStsChngMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 26. "PTxFEmpMsk,Mode: Host only" "0,1"
newline
bitfld.long 0x18 25. "HChIntMsk,Mode: Host only" "0,1"
newline
bitfld.long 0x18 24. "PrtIntMsk,Mode: Host only" "0,1"
newline
bitfld.long 0x18 23. "ResetDetMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 22. "FetSuspMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 21. "incomplPMsK,Mode: Host only" "0,1"
newline
bitfld.long 0x18 20. "incompISOINMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 19. "OEPIntMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 18. "IEPIntMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 17. "EPMisMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 15. "EOPFMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 14. "ISOOutDropMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 13. "EnumDoneMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 12. "USBRstMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 11. "USBSuspMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 10. "ErlySuspMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 7. "GOUTNakEffMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 6. "GINNakEffMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 5. "NPTxFEmpMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 4. "RxFLvlMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 3. "SofMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 2. "OTGIntMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 1. "ModeMisMsk,Mode: Host and Device" "0,1"
newline
rbitfld.long 0x18 0. "RESERVED,RESERVED" "0,1"
rgroup.long 0x1C++0x7
line.long 0x0 "GRXSTSR,Receive Status Debug Read Register"
hexmask.long.byte 0x0 25.--30. 1. "RESERVED,RESERVED"
newline
hexmask.long.byte 0x0 21.--24. 1. "FN,Mode: Device only"
newline
hexmask.long.byte 0x0 17.--20. 1. "PktSts,Mode: Host only"
newline
bitfld.long 0x0 15.--16. "DPID,Mode: Host only" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x0 4.--14. 1. "BCnt,Mode: Host only"
newline
hexmask.long.byte 0x0 0.--3. 1. "ChNum,Mode: Host only"
line.long 0x4 "GRXSTSP,Receive Status Read /Pop Register"
hexmask.long.byte 0x4 25.--30. 1. "RESERVED,RESERVED"
newline
hexmask.long.byte 0x4 21.--24. 1. "FN,Mode: Device only"
newline
hexmask.long.byte 0x4 17.--20. 1. "PktSts,Mode: Host only"
newline
bitfld.long 0x4 15.--16. "DPID,Mode: Host only" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x4 4.--14. 1. "BCnt,Mode: Host only"
newline
hexmask.long.byte 0x4 0.--3. 1. "ChNum,Mode: Host only"
group.long 0x24++0x7
line.long 0x0 "GRXFSIZ,Receive FIFO Size Register"
hexmask.long.word 0x0 14.--27. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--13. 1. "RxFDep,Mode: Host and Device"
line.long 0x4 "GNPTXFSIZ,Non-periodic Transmit FIFO Size Register"
hexmask.long.word 0x4 16.--31. 1. "NPTXFDep,Mode: Host only"
newline
hexmask.long.word 0x4 0.--15. 1. "NPTXFStAddr,Mode: Host only"
rgroup.long 0x2C++0x3
line.long 0x0 "GNPTXSTS,Non-periodic Transmit FIFO/Queue Status Register"
bitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
hexmask.long.byte 0x0 24.--30. 1. "NPTxQTop,Top of the Non-periodic Transmit Request Queue (NPTxQTop)"
newline
hexmask.long.byte 0x0 16.--23. 1. "NPTxQSpcAvail,Non-periodic Transmit Request Queue Space Available"
newline
hexmask.long.word 0x0 0.--15. 1. "NPTxFSpcAvail,Non-periodic TxFIFO Space Avail (NPTxFSpcAvail)"
group.long 0x34++0x7
line.long 0x0 "GPVNDCTL,PHY Vendor Control Register"
bitfld.long 0x0 31. "DisUlpiDrvr,Disable ULPI Drivers (DisUlpiDrvr)" "0,1"
newline
rbitfld.long 0x0 28.--30. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x0 27. "VStsDone,VStatus Done (VStsDone)" "0,1"
newline
rbitfld.long 0x0 26. "VStsBsy,VStatus Busy (VStsBsy)" "0,1"
newline
bitfld.long 0x0 25. "NewRegReq,New Register Request (NewRegReq)" "0,1"
newline
rbitfld.long 0x0 23.--24. "RESERVED1,RESERVED" "0,1,2,3"
newline
bitfld.long 0x0 22. "RegWr,Register Write (RegWr)" "0,1"
newline
hexmask.long.byte 0x0 16.--21. 1. "RegAddr,Register Address (RegAddr)"
newline
hexmask.long.byte 0x0 8.--15. 1. "VCtrl,UTMI+ Vendor Control Register Address (VCtrl)"
newline
hexmask.long.byte 0x0 0.--7. 1. "RegData,Register Data (RegData)"
line.long 0x4 "GGPIO,General Purpose Input/Output Register"
hexmask.long.word 0x4 16.--31. 1. "GPO,General Purpose Output (GPO)"
newline
hexmask.long.word 0x4 0.--15. 1. "GPI,General Purpose Input (GPI)"
rgroup.long 0x3C++0x17
line.long 0x0 "GUID,User ID Register"
hexmask.long 0x0 0.--31. 1. "GUID,User ID (UserID)"
line.long 0x4 "GSNPSID,Synopsys ID Register"
hexmask.long 0x4 0.--31. 1. "SynopsysID,Release number of the DWC_otg core being used currently"
line.long 0x8 "GHWCFG1,User HW Config1 Register"
hexmask.long 0x8 0.--31. 1. "EpDir,This 32-bit field uses two bits per"
line.long 0xC "GHWCFG2,User HW Config2 Register"
hexmask.long.byte 0xC 26.--30. 1. "TknQDepth,Device Mode IN Token Sequence Learning Queue Depth"
newline
bitfld.long 0xC 24.--25. "PTxQDepth,Host Mode Periodic Request Queue Depth (PTxQDepth)" "0: 2,1: 4,2: 8,3: 16"
newline
bitfld.long 0xC 22.--23. "NPTxQDepth,Non-periodic Request Queue Depth (NPTxQDepth)" "0: 2,1: 4,2: 8,?"
newline
bitfld.long 0xC 21. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0xC 20. "MultiProcIntrpt,Multi Processor Interrupt Enabled (MultiProcIntrpt)" "0: No,1: Yes"
newline
bitfld.long 0xC 19. "DynFifoSizing,Dynamic FIFO Sizing Enabled (DynFifoSizing)" "0: No,1: Yes"
newline
bitfld.long 0xC 18. "PerioSupport,Periodic OUT Channels Supported in Host Mode (PerioSupport)" "0: No,1: Yes"
newline
hexmask.long.byte 0xC 14.--17. 1. "NumHstChnl,Number of Host Channels (NumHstChnl)"
newline
hexmask.long.byte 0xC 10.--13. 1. "NumDevEps,Number of Device Endpoints (NumDevEps)"
newline
bitfld.long 0xC 8.--9. "FSPhyType,Full-Speed PHY Interface Type (FSPhyType)" "0: Full-speed interface not supported,1: Dedicated full-speed interface,2: FS pins shared with UTMI+ pins,3: FS pins shared with ULPI pins"
newline
bitfld.long 0xC 6.--7. "HSPhyType,High-Speed PHY Interface Type (HSPhyType)" "0: High-Speed interface not supported,1: UTMI+,2: ULPI,3: UTMI+ and ULPI"
newline
bitfld.long 0xC 5. "SingPnt,Point-to-Point (SingPnt)" "0: Multi-point application,1: Single-point application"
newline
bitfld.long 0xC 3.--4. "OtgArch,Architecture (OtgArch)" "0: Slave-Only,1: External DMA,2: Internal DMA,?"
newline
bitfld.long 0xC 0.--2. "OtgMode,Mode of Operation (OtgMode)" "0: HNP- and SRP-Capable OTG,1: SRP-Capable OTG,2: Non-HNP and Non-SRP Capable OTG,3: SRP-Capable Device,4: Non-OTG Device,5: SRP-Capable Host,6: Non-OTG Host,?"
line.long 0x10 "GHWCFG3,User HW Config3 Register"
hexmask.long.word 0x10 16.--31. 1. "DfifoDepth,DFIFO Depth (DfifoDepth - EP_LOC_CNT)"
newline
bitfld.long 0x10 15. "LPMMode,LPM mode specified for Mode of Operation." "0,1"
newline
bitfld.long 0x10 14. "BCSupport,This bit indicates the HS OTG controller support for Battery Charger." "0,1"
newline
bitfld.long 0x10 13. "HSICMode,HSIC mode specified for Mode of Operation" "0: Non-HSIC-capable,1: HSIC-capable with shared UTMI PHY interface"
newline
bitfld.long 0x10 12. "ADPSupport,This bit indicates whether ADP logic is present within or external to the HS OTG" "0: No ADP logic present with DWC_otg controller,1: ADP logic is present along with DWC_otg controller"
newline
bitfld.long 0x10 11. "RstType,Reset Style For Clocked always Blocks in RTL (RstType)" "0: Asynchronous reset is used in the core,1: Synchronous reset is used in the core"
newline
bitfld.long 0x10 10. "OptFeature,Optional Features Removed (OptFeature)" "0: No,1: Yes"
newline
bitfld.long 0x10 9. "VndctlSupt,Vendor Control Interface Support (VndctlSupt)" "0: Vendor Control Interface is not available on the..,1: Vendor Control Interface is available"
newline
bitfld.long 0x10 8. "I2CIntSel,I2C Selection (I2CIntSel)" "0: I2C Interface is not available on the core,1: I2C Interface is available on the core"
newline
bitfld.long 0x10 7. "OtgEn,OTG Function Enabled (OtgEn)" "0: Not OTG capable,1: OTG Capable"
newline
bitfld.long 0x10 4.--6. "PktSizeWidth,Width of Packet Size Counters (PktSizeWidth)" "0: 4 bits,1: 5 bits,2: 6 bits,3: 7 bits,4: 8 bits,5: 9 bits,6: 10 bits,?"
newline
hexmask.long.byte 0x10 0.--3. 1. "XferSizeWidth,Width of Transfer Size Counters (XferSizeWidth)"
line.long 0x14 "GHWCFG4,User HW Config4 Register"
bitfld.long 0x14 31. "DescDMA,Scatter/Gather DMA configuration" "0: Non Dynamic configuration,1: Dynamic configuration"
newline
bitfld.long 0x14 30. "DescDMAEnabled,Scatter/Gather DMA configuration" "0: Non-Scatter/Gather DMA configuration,1: Scatter/Gather DMA configuration"
newline
hexmask.long.byte 0x14 26.--29. 1. "INEps,Number of Device Mode IN Endpoints Including Control"
newline
bitfld.long 0x14 25. "DedFifoMode,Enable Dedicated Transmit FIFO For device IN Endpoints" "0: Dedicated Transmit FIFO Operation not enabled,1: Dedicated Transmit FIFO Operation enabled"
newline
bitfld.long 0x14 24. "SessEndFltr,session_end Filter Enabled (SessEndFltr)" "0: No filter,1: Filter"
newline
bitfld.long 0x14 23. "BValidFltr,b_valid Filter Enabled (BValidFltr)" "0: No filter,1: Filter"
newline
bitfld.long 0x14 22. "AValidFltr,a_valid Filter Enabled (AValidFltr)" "0: No filter,1: Filter"
newline
bitfld.long 0x14 21. "VBusValidFltr,VBUS Valid Filter Enabled (VBusValidFltr)" "0: No filter,1: Filter"
newline
bitfld.long 0x14 20. "IddgFltr,IDDIG Filter Enable (IddgFltr)" "0: No filter,1: Filter"
newline
hexmask.long.byte 0x14 16.--19. 1. "NumCtlEps,Number of Device Mode Control Endpoints in Addition to"
newline
bitfld.long 0x14 14.--15. "PhyDataWidth,UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width" "0: 8 bits,1: 16 bits,2: 8/16 bits,?"
newline
hexmask.long.byte 0x14 8.--13. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x14 7. "ExtendedHibernation,Enable Hibernation" "0: Extended Hibernation feature not enabled,1: Extended Hibernation feature enabled"
newline
bitfld.long 0x14 6. "Hibernation,Enable Hibernation (Hibernation)" "0: Hibernation feature not enabled,1: Hibernation feature enabled"
newline
bitfld.long 0x14 5. "AhbFreq,Minimum AHB Frequency Less Than 60 MHz (AhbFreq)" "0: No,1: Yes"
newline
bitfld.long 0x14 4. "PartialPwrDn,Enable Partial Power Down (PartialPwrDn)" "0: Partial Power Down Not Enabled,1: Partial Power Down Enabled"
newline
hexmask.long.byte 0x14 0.--3. 1. "NumDevPerioEps,Number of Device Mode Periodic IN Endpoints"
group.long 0x5C++0x3
line.long 0x0 "GDFIFOCFG,Global DFIFO Configuration Register"
hexmask.long.word 0x0 16.--31. 1. "EPInfoBaseAddr,EPInfoBaseAddr"
newline
hexmask.long.word 0x0 0.--15. 1. "GDFIFOCfg,GDFIFOCfg"
group.long 0x100++0x3F
line.long 0x0 "HPTXFSIZ,Host Periodic Transmit FIFO Size Register"
hexmask.long.word 0x0 16.--29. 1. "PTxFSize,Host Periodic TxFIFO Depth (PTxFSize)"
newline
hexmask.long.word 0x0 0.--14. 1. "PTxFStAddr,Host Periodic TxFIFO Start Address (PTxFStAddr)"
line.long 0x4 "DIEPTXF1,Device IN Endpoint Transmit FIFO Size Register 1"
hexmask.long.word 0x4 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x4 0.--14. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x8 "DIEPTXF2,Device IN Endpoint Transmit FIFO Size Register 2"
hexmask.long.word 0x8 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x8 0.--14. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0xC "DIEPTXF3,Device IN Endpoint Transmit FIFO Size Register 3"
hexmask.long.word 0xC 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0xC 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x10 "DIEPTXF4,Device IN Endpoint Transmit FIFO Size Register 4"
hexmask.long.word 0x10 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x10 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x14 "DIEPTXF5,Device IN Endpoint Transmit FIFO Size Register 5"
hexmask.long.word 0x14 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x14 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x18 "DIEPTXF6,Device IN Endpoint Transmit FIFO Size Register 6"
hexmask.long.word 0x18 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x18 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x1C "DIEPTXF7,Device IN Endpoint Transmit FIFO Size Register 7"
hexmask.long.word 0x1C 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x1C 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x20 "DIEPTXF8,Device IN Endpoint Transmit FIFO Size Register 8"
hexmask.long.word 0x20 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x20 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x24 "DIEPTXF9,Device IN Endpoint Transmit FIFO Size Register 9"
hexmask.long.word 0x24 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x24 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x28 "DIEPTXF10,Device IN Endpoint Transmit FIFO Size Register 10"
hexmask.long.word 0x28 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x28 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x2C "DIEPTXF11,Device IN Endpoint Transmit FIFO Size Register 11"
hexmask.long.word 0x2C 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x2C 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x30 "DIEPTXF12,Device IN Endpoint Transmit FIFO Size Register 12"
hexmask.long.word 0x30 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x30 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x34 "DIEPTXF13,Device IN Endpoint Transmit FIFO Size Register 13"
hexmask.long.word 0x34 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x34 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x38 "DIEPTXF14,Device IN Endpoint Transmit FIFO Size Register 14"
hexmask.long.word 0x38 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x38 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x3C "DIEPTXF15,Device IN Endpoint Transmit FIFO Size Register 15"
hexmask.long.word 0x3C 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x3C 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
group.long 0x400++0x7
line.long 0x0 "HCFG,Host Configuration Register"
bitfld.long 0x0 31. "ModeChTimEn,Mode Change Ready Timer Enable (ModeChTimEn)" "0: The Host core waits for either 200 PHY clock..,1: The Host core waits only for a linstate of SE0.."
newline
hexmask.long.byte 0x0 27.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x0 26. "PerSchedEna,Enable Periodic Scheduling (PerSchedEna):" "0,1"
newline
bitfld.long 0x0 24.--25. "FrListEn,Frame List Entries(FrListEn). The value in the register specifies the number" "0: 8 Entries,1: 16 Entries,2: 32 Entries,3: 63 Entries"
newline
bitfld.long 0x0 23. "DescDMA,Enable Scatter/gather DMA in Host mode (DescDMA)." "0: Buffered DMA mode,1: Scatter/Gather DMA mode"
newline
hexmask.long.byte 0x0 16.--22. 1. "RESERVED1,RESERVED"
newline
hexmask.long.byte 0x0 8.--15. 1. "ResValid,Resume Validation Period (ResValid)"
newline
bitfld.long 0x0 7. "Ena32KHzS,Enable 32 KHz Suspend mode (Ena32KHzS)" "0,1"
newline
hexmask.long.byte 0x0 3.--6. 1. "RESERVED2,RESERVED"
newline
bitfld.long 0x0 2. "FSLSSupp,FS- and LS-Only Support (FSLSSupp)" "0: HS/FS/LS,1: FS/LS-only"
newline
bitfld.long 0x0 0.--1. "FSLSPclkSel,FS/LS PHY Clock Select (FSLSPclkSel)" "0: Internal and external clocks have the same..,1: PHY clock is running at 48 MHz,2: Internal clock is the divided by eight version..,3: Reserved"
line.long 0x4 "HFIR,Host Frame Interval Register"
hexmask.long.word 0x4 17.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x4 16. "HFIRRldCtrl,Reload Control (HFIRRldCtrl)" "0: The HFIR cannot be reloaded dynamically,1: the HFIR can be dynamically reloaded during.."
newline
hexmask.long.word 0x4 0.--15. 1. "FrInt,Frame Interval (FrInt)"
rgroup.long 0x408++0x3
line.long 0x0 "HFNUM,Host Frame Number/Frame Time Remaining Register"
hexmask.long.word 0x0 16.--31. 1. "FrRem,Frame Time Remaining (FrRem)"
newline
hexmask.long.word 0x0 0.--15. 1. "FrNum,Frame Number (FrNum)"
rgroup.long 0x410++0x7
line.long 0x0 "HPTXSTS,Host Periodic Transmit FIFO/Queue Status Register"
hexmask.long.byte 0x0 24.--31. 1. "PTxQTop,Top of the Periodic Transmit Request Queue (PTxQTop)"
newline
hexmask.long.byte 0x0 16.--23. 1. "PTxQSpcAvail,Periodic Transmit Request Queue Space Available"
newline
hexmask.long.word 0x0 0.--15. 1. "PTxFSpcAvail,Periodic Transmit Data FIFO Space Available"
line.long 0x4 "HAINT,Host All Channels Interrupt Register"
hexmask.long.word 0x4 0.--15. 1. "HAINT,Channel Interrupt for channel no."
group.long 0x418++0x7
line.long 0x0 "HAINTMSK,Host All Channels Interrupt Mask Register"
hexmask.long.word 0x0 0.--15. 1. "HAINTMsk,Channel Interrupt Msk for channel"
line.long 0x4 "HFLBAddr,Host Frame List Base Address Register"
hexmask.long 0x4 0.--31. 1. "HFLBAddr,The starting address of the Frame list."
group.long 0x440++0x3
line.long 0x0 "HPRT,Host Port Control and Status Register"
rbitfld.long 0x0 17.--18. "PrtSpd,Port Speed (PrtSpd)" "0: High speed,1: Full speed,2: Low speed,3: Reserved"
newline
hexmask.long.byte 0x0 13.--16. 1. "PrtTstCtl,Port Test Control (PrtTstCtl)"
newline
bitfld.long 0x0 12. "PrtPwr,Port Power (PrtPwr)" "0: Power off,1: Power on"
newline
rbitfld.long 0x0 10.--11. "PrtLnSts,Port Line Status (PrtLnSts)" "0,1,2,3"
newline
rbitfld.long 0x0 9. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 8. "PrtRst,Port Reset (PrtRst)" "0: Port not in reset,1: Port in reset"
newline
bitfld.long 0x0 7. "PrtSusp,Port Suspend (PrtSusp)" "0: Port not in Suspend mode,1: Port in Suspend mode"
newline
bitfld.long 0x0 6. "PrtRes,Port Resume (PrtRes)" "0: No resume driven,1: Resume driven"
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eventfld.long 0x0 5. "PrtOvrCurrChng,Port Overcurrent Change (PrtOvrCurrChng)" "0,1"
newline
rbitfld.long 0x0 4. "PrtOvrCurrAct,Port Overcurrent Active (PrtOvrCurrAct)" "0: No overcurrent condition,1: Overcurrent condition"
newline
eventfld.long 0x0 3. "PrtEnChng,Port Enable/Disable Change (PrtEnChng)" "0,1"
newline
eventfld.long 0x0 2. "PrtEna,Port Enable (PrtEna)" "0: Port disabled,1: Port enabled"
newline
eventfld.long 0x0 1. "PrtConnDet,Port Connect Detected (PrtConnDet)" "0,1"
newline
rbitfld.long 0x0 0. "PrtConnSts,Port Connect Status (PrtConnSts)" "0: No device is attached to the port,1: A device is attached to the port"
group.long 0x500++0x17
line.long 0x0 "HCCHAR0,Host Channel 0 Characteristics Register"
bitfld.long 0x0 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x0 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x0 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x0 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x0 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x0 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x0 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x0 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x4 "HCSPLT0,Host Channel 0 Split Control Register"
bitfld.long 0x4 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x4 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x4 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x4 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x4 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x4 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0x8 "HCINT0,Host Channel 0 Interrupt Register"
hexmask.long.tbyte 0x8 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x8 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0x8 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0x8 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x8 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0x8 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0x8 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0x8 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0x8 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0x8 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0x8 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0x8 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0x8 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x8 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0x8 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0xC "HCINTMSK0,Host Channel 0 Interrupt Mask Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0xC 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0xC 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0xC 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0xC 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0xC 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0xC 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0xC 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0xC 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0xC 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0xC 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0xC 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0xC 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0xC 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0xC 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x10 "HCTSIZ0,Host Channel 0 Transfer Size Register"
bitfld.long 0x10 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x10 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x10 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x10 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x14 "HCDMA0,Host Channel 0 DMA Address Register"
hexmask.long 0x14 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x51C++0x1B
line.long 0x0 "HCDMAB0,Host Channel 0 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR1,Host Channel 1 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT1,Host Channel 1 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT1,Host Channel 1 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK1,Host Channel 1 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ1,Host Channel 1 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA1,Host Channel 1 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x53C++0x1B
line.long 0x0 "HCDMAB1,Host Channel 1 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR2,Host Channel 2 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT2,Host Channel 2 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT2,Host Channel 2 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK2,Host Channel 2 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ2,Host Channel 2 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA2,Host Channel 2 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x55C++0x1B
line.long 0x0 "HCDMAB2,Host Channel 2 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR3,Host Channel 3 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT3,Host Channel 3 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT3,Host Channel 3 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK3,Host Channel 3 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
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bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
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bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ3,Host Channel 3 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA3,Host Channel 3 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x57C++0x1B
line.long 0x0 "HCDMAB3,Host Channel 3 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR4,Host Channel 4 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT4,Host Channel 4 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT4,Host Channel 4 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK4,Host Channel 4 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ4,Host Channel 4 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA4,Host Channel 4 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x59C++0x1B
line.long 0x0 "HCDMAB4,Host Channel 4 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR5,Host Channel 5 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT5,Host Channel 5 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT5,Host Channel 5 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK5,Host Channel 5 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ5,Host Channel 5 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA5,Host Channel 5 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x5BC++0x1B
line.long 0x0 "HCDMAB5,Host Channel 5 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR6,Host Channel 6 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT6,Host Channel 6 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT6,Host Channel 6 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK6,Host Channel 6 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ6,Host Channel 6 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA6,Host Channel 6 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x5DC++0x1B
line.long 0x0 "HCDMAB6,Host Channel 6 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR7,Host Channel 7 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
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bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
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rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
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bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
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hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
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hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT7,Host Channel 7 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
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hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
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bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
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bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
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hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT7,Host Channel 7 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
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eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
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eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
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eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
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eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
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eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
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eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
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eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
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eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
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eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
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eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
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eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK7,Host Channel 7 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
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bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
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rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
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bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
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bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
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bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ7,Host Channel 7 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
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hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA7,Host Channel 7 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x5FC++0x1B
line.long 0x0 "HCDMAB7,Host Channel 7 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR8,Host Channel 8 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
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bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
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bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
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hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
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bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
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bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
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hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
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hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT8,Host Channel 8 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
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hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
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bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
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bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
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hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT8,Host Channel 8 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
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eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
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eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
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eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
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eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
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eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK8,Host Channel 8 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
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bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ8,Host Channel 8 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA8,Host Channel 8 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x61C++0x1B
line.long 0x0 "HCDMAB8,Host Channel 8 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR9,Host Channel 9 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT9,Host Channel 9 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT9,Host Channel 9 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK9,Host Channel 9 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ9,Host Channel 9 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA9,Host Channel 9 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x63C++0x1B
line.long 0x0 "HCDMAB9,Host Channel 9 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR10,Host Channel 10 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT10,Host Channel 10 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT10,Host Channel 10 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK10,Host Channel 10 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ10,Host Channel 10 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
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bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA10,Host Channel 10 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x65C++0x1B
line.long 0x0 "HCDMAB10,Host Channel 10 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR11,Host Channel 11 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
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hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT11,Host Channel 11 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
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hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
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bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT11,Host Channel 11 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK11,Host Channel 11 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
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bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ11,Host Channel 11 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA11,Host Channel 11 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x67C++0x1B
line.long 0x0 "HCDMAB11,Host Channel 11 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR12,Host Channel 12 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT12,Host Channel 12 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT12,Host Channel 12 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK12,Host Channel 12 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ12,Host Channel 12 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA12,Host Channel 12 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x69C++0x1B
line.long 0x0 "HCDMAB12,Host Channel 12 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR13,Host Channel 13 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT13,Host Channel 13 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT13,Host Channel 13 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK13,Host Channel 13 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ13,Host Channel 13 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA13,Host Channel 13 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x6BC++0x1B
line.long 0x0 "HCDMAB13,Host Channel 13 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR14,Host Channel 14 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT14,Host Channel 14 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT14,Host Channel 14 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK14,Host Channel 14 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
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bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
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rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
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bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
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bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
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bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
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bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
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bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
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bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
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bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
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bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
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bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
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bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
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bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
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bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ14,Host Channel 14 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
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bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
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hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
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hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA14,Host Channel 14 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x6DC++0x1B
line.long 0x0 "HCDMAB14,Host Channel 14 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR15,Host Channel 15 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
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bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
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bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
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hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
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bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
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bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
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bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
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rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
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bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
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hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
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hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT15,Host Channel 15 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
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hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
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bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
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bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
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hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
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hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT15,Host Channel 15 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
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eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
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eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
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eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
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eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
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eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
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eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
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eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
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eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
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eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
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eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
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eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
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eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
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eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
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eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK15,Host Channel 15 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
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bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
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rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
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bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
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bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
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bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
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bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
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bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
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bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
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bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
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bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
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bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
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bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
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bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
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bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ15,Host Channel 15 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
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bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
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hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
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hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA15,Host Channel 15 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x6FC++0x3
line.long 0x0 "HCDMAB15,Host Channel 15 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
group.long 0x800++0x7
line.long 0x0 "DCFG,Device Configuration Register"
hexmask.long.byte 0x0 26.--31. 1. "ResValid,Resume Validation Period (ResValid)"
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bitfld.long 0x0 24.--25. "PerSchIntvl,Periodic Scheduling Interval (PerSchIntvl)" "0: 25% of,1: 50% of,2: 75% of,3: Reserved"
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bitfld.long 0x0 23. "DescDMA,Enable Scatter/gather DMA in device mode (DescDMA)." "0: Buffered DMA,1: Scatter/Gather DMA mode"
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rbitfld.long 0x0 16.--17. "RESERVED,RESERVED" "0,1,2,3"
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bitfld.long 0x0 15. "ErraticIntMsk,Erratic Error Interrupt Mask" "0: Early suspend interrupt is generated on erratic..,1: Mask early suspend interrupt on erratic error"
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bitfld.long 0x0 14. "XCVRDLY,1'b1: Enable delay between xcvr_sel and txvalid during Device chirp" "0: No delay between xcvr_sel and txvalid during..,1: Enable delay between xcvr_sel and txvalid during.."
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bitfld.long 0x0 13. "EnDevOutNak,Enable Device OUT NAK (EnDevOutNak)" "0: The core does not set NAK after Bulk OUT..,1: The core sets NAK after Bulk OUT transfer complete"
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bitfld.long 0x0 11.--12. "PerFrInt,Periodic Frame Interval (PerFrInt)" "0: 80% of the,1: 85%,2: 90%,3: 95%"
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hexmask.long.byte 0x0 4.--10. 1. "DevAddr,Device Address (DevAddr)"
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bitfld.long 0x0 3. "Ena32KHzSusp,Enable 32 KHz Suspend mode (Ena32KHzSusp)" "0,1"
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bitfld.long 0x0 2. "NZStsOUTHShk,Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)" "0: Send the received OUT packet to the application,1: Send a STALL handshake on a nonzero-length status"
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bitfld.long 0x0 0.--1. "DevSpd,Device Speed (DevSpd)" "0: High speed,1: Full speed,2: Low speed,3: Full speed"
line.long 0x4 "DCTL,Device Control Register"
hexmask.long.word 0x4 19.--31. 1. "RESERVED,RESERVED"
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bitfld.long 0x4 17. "EnContOnBNA,Enable Continue on BNA (EnContOnBNA)" "0: After receiving BNA interrupt,1: After receiving BNA interrupt"
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bitfld.long 0x4 16. "NakOnBble,NAK on Babble Error (NakOnBble)" "0,1"
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bitfld.long 0x4 15. "IgnrFrmNum,Ignore Frame number For Isochronous End points (IgnrFrmNum)" "0: periodic transfer interrupt feature is disabled,1: periodic transfer interrupt feature is enabled"
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bitfld.long 0x4 13.--14. "GMC,Global Multi Count (GMC)" "0: Invalid,1: 1 packet,2: 2 packets,3: 3 packets"
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bitfld.long 0x4 11. "PWROnPrgDone,Power-On Programming Done (PWROnPrgDone)" "0,1"
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bitfld.long 0x4 10. "CGOUTNak,Clear Global OUT NAK (CGOUTNak)" "0,1"
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bitfld.long 0x4 9. "SGOUTNak,Set Global OUT NAK (SGOUTNak)" "0,1"
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bitfld.long 0x4 8. "CGNPInNak,Clear Global Non-periodic IN NAK (CGNPInNak)" "0,1"
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bitfld.long 0x4 7. "SGNPInNak,Set Global Non-periodic IN NAK (SGNPInNak)" "0,1"
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bitfld.long 0x4 4.--6. "TstCtl,Test Control (TstCtl)" "0: Test mode disabled,1: Test_J mode,2: Test_K mode,3: Test_SE0_NAK mode,4: Test_Packet mode,5: Test_Force_Enable,?,?"
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rbitfld.long 0x4 3. "GOUTNakSts,Global OUT NAK Status (GOUTNakSts)" "0: A handshake is sent based on the FIFO Status and..,1: No data is written to the RxFIFO"
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rbitfld.long 0x4 2. "GNPINNakSts,Global Non-periodic IN NAK Status (GNPINNakSts)" "0: A handshake is sent out based on the data..,1: A NAK handshake is sent out on all non-periodic IN"
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bitfld.long 0x4 1. "SftDiscon,Soft Disconnect (SftDiscon)" "0: Normal operation,1: The core drives the phy_opmode_o signal on the"
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bitfld.long 0x4 0. "RmtWkUpSig,Remote Wakeup Signaling (RmtWkUpSig)" "0,1"
rgroup.long 0x808++0x3
line.long 0x0 "DSTS,Device Status Register"
hexmask.long.byte 0x0 24.--31. 1. "RESERVED,RESERVED"
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bitfld.long 0x0 22.--23. "DevLnSts,Device Line Status (DevLnSts)" "0,1,2,3"
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hexmask.long.word 0x0 8.--21. 1. "SOFFN,Frame or Microframe Number of the Received SOF (SOFFN)"
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hexmask.long.byte 0x0 4.--7. 1. "RESERVED1,RESERVED"
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bitfld.long 0x0 3. "ErrticErr,Erratic Error (ErrticErr)" "0,1"
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bitfld.long 0x0 1.--2. "EnumSpd,Enumerated Speed (EnumSpd)" "0: High speed,1: Full speed,2: Low speed,3: Full speed"
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bitfld.long 0x0 0. "SuspSts,Suspend Status (SuspSts)" "0,1"
group.long 0x810++0x7
line.long 0x0 "DIEPMSK,Device IN Endpoint Common Interrupt Mask Register"
hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED,RESERVED"
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bitfld.long 0x0 13. "NAKMsk,NAK interrupt Mask (NAKMsk)" "0,1"
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bitfld.long 0x0 9. "BNAInIntrMsk,BNA interrupt Mask (BNAInIntrMsk)" "0,1"
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bitfld.long 0x0 8. "TxfifoUndrnMsk,Fifo Underrun Mask (TxfifoUndrnMsk)" "0,1"
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rbitfld.long 0x0 7. "RESERVED1,RESERVED" "0,1"
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bitfld.long 0x0 6. "INEPNakEffMsk,IN Endpoint NAK Effective Mask (INEPNakEffMsk)" "0,1"
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bitfld.long 0x0 5. "INTknEPMisMsk,IN Token received with EP Mismatch Mask (INTknEPMisMsk)" "0,1"
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bitfld.long 0x0 4. "INTknTXFEmpMsk,IN Token Received When TxFIFO Empty Mask" "0,1"
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bitfld.long 0x0 3. "TimeOUTMsk,Timeout Condition Mask (TimeOUTMsk)" "0,1"
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bitfld.long 0x0 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
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bitfld.long 0x0 1. "EPDisbldMsk,Endpoint Disabled Interrupt Mask (EPDisbldMsk)" "0,1"
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bitfld.long 0x0 0. "XferComplMsk,Transfer Completed Interrupt Mask (XferComplMsk)" "0,1"
line.long 0x4 "DOEPMSK,Device OUT Endpoint Common Interrupt Mask Register"
hexmask.long.tbyte 0x4 15.--31. 1. "RESERVED,RESERVED"
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bitfld.long 0x4 14. "NYETMsk,NYET interrupt Mask (NYETMsk)" "0,1"
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bitfld.long 0x4 13. "NAKMsk,NAK interrupt Mask (NAKMsk)" "0,1"
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bitfld.long 0x4 12. "BbleErrMsk,Babble Error interrupt Mask (BbleErrMsk)" "0,1"
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bitfld.long 0x4 9. "BnaOutIntrMsk,BNA interrupt Mask (BnaOutIntrMsk)" "0,1"
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bitfld.long 0x4 8. "OutPktErrMsk,OUT Packet Error Mask (OutPktErrMsk)" "0,1"
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rbitfld.long 0x4 7. "RESERVED1,RESERVED" "0,1"
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bitfld.long 0x4 6. "Back2BackSETup,Back-to-Back SETUP Packets Received Mask" "0,1"
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bitfld.long 0x4 5. "StsPhseRcvdMsk,Status Phase Received Mask" "0,1"
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bitfld.long 0x4 4. "OUTTknEPdisMsk,OUT Token Received when Endpoint Disabled Mask" "0,1"
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bitfld.long 0x4 3. "SetUPMsk,SETUP Phase Done Mask (SetUPMsk)" "0,1"
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bitfld.long 0x4 2. "AHBErrMsk,AHB Error (AHBErrMsk)" "0,1"
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bitfld.long 0x4 1. "EPDisbldMsk,Endpoint Disabled Interrupt Mask (EPDisbldMsk)" "0,1"
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bitfld.long 0x4 0. "XferComplMsk,Transfer Completed Interrupt Mask (XferComplMsk)" "0,1"
rgroup.long 0x818++0x3
line.long 0x0 "DAINT,Device All Endpoints Interrupt Register"
bitfld.long 0x0 31. "OutEPInt15,OUT Endpoint 15 Interrupt Bit" "0,1"
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bitfld.long 0x0 30. "OutEPInt14,OUT Endpoint 14 Interrupt Bit" "0,1"
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bitfld.long 0x0 29. "OutEPInt13,OUT Endpoint 13 Interrupt Bit" "0,1"
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bitfld.long 0x0 28. "OutEPInt12,OUT Endpoint 12 Interrupt Bit" "0,1"
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bitfld.long 0x0 27. "OutEPInt11,OUT Endpoint 11 Interrupt Bit" "0,1"
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bitfld.long 0x0 26. "OutEPInt10,OUT Endpoint 10 Interrupt Bit" "0,1"
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bitfld.long 0x0 25. "OutEPInt9,OUT Endpoint 9 Interrupt Bit" "0,1"
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bitfld.long 0x0 24. "OutEPInt8,OUT Endpoint 8 Interrupt Bit" "0,1"
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bitfld.long 0x0 23. "OutEPInt7,OUT Endpoint 7 Interrupt Bit" "0,1"
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bitfld.long 0x0 22. "OutEPInt6,OUT Endpoint 6 Interrupt Bit" "0,1"
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bitfld.long 0x0 21. "OutEPInt5,OUT Endpoint 5 Interrupt Bit" "0,1"
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bitfld.long 0x0 20. "OutEPInt4,OUT Endpoint 4 Interrupt Bit" "0,1"
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bitfld.long 0x0 19. "OutEPInt3,OUT Endpoint 3 Interrupt Bit" "0,1"
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bitfld.long 0x0 18. "OutEPInt2,OUT Endpoint 2 Interrupt Bit" "0,1"
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bitfld.long 0x0 17. "OutEPInt1,OUT Endpoint 1 Interrupt Bit" "0,1"
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bitfld.long 0x0 16. "OutEPInt0,OUT Endpoint 0 Interrupt Bit" "0,1"
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bitfld.long 0x0 15. "InEpInt15,IN Endpoint 15 Interrupt Bit" "0,1"
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bitfld.long 0x0 14. "InEpInt14,IN Endpoint 14 Interrupt Bit" "0,1"
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bitfld.long 0x0 13. "InEpInt13,IN Endpoint 13 Interrupt Bit" "0,1"
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bitfld.long 0x0 12. "InEpInt12,IN Endpoint 12 Interrupt Bit" "0,1"
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bitfld.long 0x0 11. "InEpInt11,IN Endpoint 11 Interrupt Bit" "0,1"
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bitfld.long 0x0 10. "InEpInt10,IN Endpoint 10 Interrupt Bit" "0,1"
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bitfld.long 0x0 9. "InEpInt9,IN Endpoint 9 Interrupt Bit" "0,1"
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bitfld.long 0x0 8. "InEpInt8,IN Endpoint 8 Interrupt Bit" "0,1"
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bitfld.long 0x0 7. "InEpInt7,IN Endpoint 7 Interrupt Bit" "0,1"
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bitfld.long 0x0 6. "InEpInt6,IN Endpoint 6 Interrupt Bit" "0,1"
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bitfld.long 0x0 5. "InEpInt5,IN Endpoint 5 Interrupt Bit" "0,1"
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bitfld.long 0x0 4. "InEpInt4,IN Endpoint 4 Interrupt Bit" "0,1"
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bitfld.long 0x0 3. "InEpInt3,IN Endpoint 3 Interrupt Bit" "0,1"
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bitfld.long 0x0 2. "InEpInt2,IN Endpoint 2 Interrupt Bit" "0,1"
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bitfld.long 0x0 1. "InEpInt1,IN Endpoint 1 Interrupt Bit" "0,1"
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bitfld.long 0x0 0. "InEpInt0,IN Endpoint 0 Interrupt Bit" "0,1"
group.long 0x81C++0x3
line.long 0x0 "DAINTMSK,Device All Endpoints Interrupt Mask Register"
bitfld.long 0x0 31. "OutEPMsk15,OUT Endpoint 15 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 30. "OutEPMsk14,OUT Endpoint 14 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 29. "OutEPMsk13,OUT Endpoint 13 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 28. "OutEPMsk12,OUT Endpoint 12 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 27. "OutEPMsk11,OUT Endpoint 11 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 26. "OutEPMsk10,OUT Endpoint 10 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 25. "OutEPMsk9,OUT Endpoint 9 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 24. "OutEPMsk8,OUT Endpoint 8 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 23. "OutEPMsk7,OUT Endpoint 7 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 22. "OutEPMsk6,OUT Endpoint 6 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 21. "OutEPMsk5,OUT Endpoint 5 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 20. "OutEPMsk4,OUT Endpoint 4 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 19. "OutEPMsk3,OUT Endpoint 3 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 18. "OutEPMsk2,OUT Endpoint 2 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 17. "OutEPMsk1,OUT Endpoint 1 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 16. "OutEPMsk0,OUT Endpoint 0 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 15. "InEpMsk15,IN Endpoint 15 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 14. "InEpMsk14,IN Endpoint 14 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 13. "InEpMsk13,IN Endpoint 13 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 12. "InEpMsk12,IN Endpoint 12 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 11. "InEpMsk11,IN Endpoint 11 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 10. "InEpMsk10,IN Endpoint 10 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 9. "InEpMsk9,IN Endpoint 9 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 8. "InEpMsk8,IN Endpoint 8 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 7. "InEpMsk7,IN Endpoint 7 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 6. "InEpMsk6,IN Endpoint 6 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 5. "InEpMsk5,IN Endpoint 5 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 4. "InEpMsk4,IN Endpoint 4 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 3. "InEpMsk3,IN Endpoint 3 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 2. "InEpMsk2,IN Endpoint 2 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 1. "InEpMsk1,IN Endpoint 1 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 0. "InEpMsk0,IN Endpoint 0 Interrupt mask Bit" "0,1"
group.long 0x828++0xF
line.long 0x0 "DVBUSDIS,Device VBUS Discharge Time Register"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "DVBUSDis,Device VBUS Discharge Time (DVBUSDis)"
line.long 0x4 "DVBUSPULSE,Device VBUS Pulsing Time Register"
hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x4 0.--11. 1. "DVBUSPulse,Device VBUS Pulsing Time (DVBUSPulse)"
line.long 0x8 "DTHRCTL,Device Threshold Control Register"
hexmask.long.byte 0x8 28.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 27. "ArbPrkEn,Arbiter Parking Enable (ArbPrkEn)" "0,1"
newline
rbitfld.long 0x8 26. "RESERVED1,RESERVED" "0,1"
newline
hexmask.long.word 0x8 17.--25. 1. "RxThrLen,Receive Threshold Length (RxThrLen)"
newline
bitfld.long 0x8 16. "RxThrEn,Receive Threshold Enable (RxThrEn)" "0,1"
newline
rbitfld.long 0x8 13.--15. "RESERVED2,RESERVED" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 11.--12. "AHBThrRatio,AHB Threshold Ratio (AHBThrRatio)" "0: AHB threshold = MAC threshold,1: AHB threshold = MAC threshold / 2,2: AHB threshold = MAC threshold / 4,3: AHB threshold = MAC threshold / 8"
newline
hexmask.long.word 0x8 2.--10. 1. "TxThrLen,Transmit Threshold Length (TxThrLen)"
newline
bitfld.long 0x8 1. "ISOThrEn,ISO IN Endpoints Threshold Enable. (ISOThrEn)" "0,1"
newline
bitfld.long 0x8 0. "NonISOThrEn,Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn)" "0,1"
line.long 0xC "DIEPEMPMSK,Device IN Endpoint FIFO Empty Interrupt Mask Register"
hexmask.long.word 0xC 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0xC 0.--15. 1. "InEpTxfEmpMsk,IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk)"
group.long 0x900++0x3
line.long 0x0 "DIEPCTL0,Device Control IN Endpoint 0 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
rbitfld.long 0x0 28.--29. "RESERVED,RESERVED" "0,1,2,3"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "RESERVED1,RESERVED" "0,1"
newline
rbitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0,1,2,3"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "RESERVED2,RESERVED" "0,1"
newline
rbitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 2.--10. 1. "RESERVED3,RESERVED"
newline
bitfld.long 0x0 0.--1. "MPS,Maximum Packet Size (MPS)" "0: 64 bytes,1: 32 bytes,2: 16 bytes,3: 8 bytes"
group.long 0x908++0x3
line.long 0x0 "DIEPINT0,Device IN Endpoint 0 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x910++0x7
line.long 0x0 "DIEPTSIZ0,Device IN Endpoint 0 Transfer Size Register"
hexmask.long.word 0x0 21.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x0 19.--20. "PktCnt,Packet Count (PktCnt)" "0,1,2,3"
newline
hexmask.long.word 0x0 7.--18. 1. "RESERVED1,RESERVED"
newline
hexmask.long.byte 0x0 0.--6. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA0,Device IN Endpoint 0 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x918++0x7
line.long 0x0 "DTXFSTS0,Device IN Endpoint Transmit FIFO Status Register 0"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB0,Device IN Endpoint 16 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x920++0x3
line.long 0x0 "DIEPCTL1,Device Control IN Endpoint 1 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x928++0x3
line.long 0x0 "DIEPINT1,Device IN Endpoint 1 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x930++0x7
line.long 0x0 "DIEPTSIZ1,Device IN Endpoint 1 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA1,Device IN Endpoint 1 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x938++0x7
line.long 0x0 "DTXFSTS1,Device IN Endpoint Transmit FIFO Status Register 1"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB1,Device IN Endpoint 1 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x940++0x3
line.long 0x0 "DIEPCTL2,Device Control IN Endpoint 2 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x948++0x3
line.long 0x0 "DIEPINT2,Device IN Endpoint 2 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x950++0x7
line.long 0x0 "DIEPTSIZ2,Device IN Endpoint 2 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA2,Device IN Endpoint 2 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x958++0x7
line.long 0x0 "DTXFSTS2,Device IN Endpoint Transmit FIFO Status Register 2"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB2,Device IN Endpoint 2 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x960++0x3
line.long 0x0 "DIEPCTL3,Device Control IN Endpoint 3 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x968++0x3
line.long 0x0 "DIEPINT3,Device IN Endpoint 3 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x970++0x7
line.long 0x0 "DIEPTSIZ3,Device IN Endpoint 3 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA3,Device IN Endpoint 3 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x978++0x7
line.long 0x0 "DTXFSTS3,Device IN Endpoint Transmit FIFO Status Register 3"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB3,Device IN Endpoint 3 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x980++0x3
line.long 0x0 "DIEPCTL4,Device Control IN Endpoint 4 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x988++0x3
line.long 0x0 "DIEPINT4,Device IN Endpoint 4 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x990++0x7
line.long 0x0 "DIEPTSIZ4,Device IN Endpoint 4 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA4,Device IN Endpoint 4 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x998++0x7
line.long 0x0 "DTXFSTS4,Device IN Endpoint Transmit FIFO Status Register 4"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB4,Device IN Endpoint 4 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x9A0++0x3
line.long 0x0 "DIEPCTL5,Device Control IN Endpoint 5 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x9A8++0x3
line.long 0x0 "DIEPINT5,Device IN Endpoint 5 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x9B0++0x7
line.long 0x0 "DIEPTSIZ5,Device IN Endpoint 5 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA5,Device IN Endpoint 5 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x9B8++0x7
line.long 0x0 "DTXFSTS5,Device IN Endpoint Transmit FIFO Status Register 5"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB5,Device IN Endpoint 5 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x9C0++0x3
line.long 0x0 "DIEPCTL6,Device Control IN Endpoint 6 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x9C8++0x3
line.long 0x0 "DIEPINT6,Device IN Endpoint 6 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x9D0++0x7
line.long 0x0 "DIEPTSIZ6,Device IN Endpoint 6 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA6,Device IN Endpoint 6 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x9D8++0x7
line.long 0x0 "DTXFSTS6,Device IN Endpoint Transmit FIFO Status Register 6"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB6,Device IN Endpoint 6 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x9E0++0x3
line.long 0x0 "DIEPCTL7,Device Control IN Endpoint 7 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x9E8++0x3
line.long 0x0 "DIEPINT7,Device IN Endpoint 7 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x9F0++0x7
line.long 0x0 "DIEPTSIZ7,Device IN Endpoint 7 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA7,Device IN Endpoint 7 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x9F8++0x7
line.long 0x0 "DTXFSTS7,Device IN Endpoint Transmit FIFO Status Register 7"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB7,Device IN Endpoint 7 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xA00++0x3
line.long 0x0 "DIEPCTL8,Device Control IN Endpoint 8 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xA08++0x3
line.long 0x0 "DIEPINT8,Device IN Endpoint 8 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xA10++0x7
line.long 0x0 "DIEPTSIZ8,Device IN Endpoint 8 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA8,Device IN Endpoint 8 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xA18++0x7
line.long 0x0 "DTXFSTS8,Device IN Endpoint Transmit FIFO Status Register 8"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB8,Device IN Endpoint 8 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xA20++0x3
line.long 0x0 "DIEPCTL9,Device Control IN Endpoint 9 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xA28++0x3
line.long 0x0 "DIEPINT9,Device IN Endpoint 9 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xA30++0x7
line.long 0x0 "DIEPTSIZ9,Device IN Endpoint 9 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA9,Device IN Endpoint 9 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xA38++0x7
line.long 0x0 "DTXFSTS9,Device IN Endpoint Transmit FIFO Status Register 9"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB9,Device IN Endpoint 9 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xA40++0x3
line.long 0x0 "DIEPCTL10,Device Control IN Endpoint 10 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xA48++0x3
line.long 0x0 "DIEPINT10,Device IN Endpoint 10 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xA50++0x7
line.long 0x0 "DIEPTSIZ10,Device IN Endpoint 10 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA10,Device IN Endpoint 10 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xA58++0x7
line.long 0x0 "DTXFSTS10,Device IN Endpoint Transmit FIFO Status Register 10"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB10,Device IN Endpoint 10 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xA60++0x3
line.long 0x0 "DIEPCTL11,Device Control IN Endpoint 11 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xA68++0x3
line.long 0x0 "DIEPINT11,Device IN Endpoint 11 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xA70++0x7
line.long 0x0 "DIEPTSIZ11,Device IN Endpoint 11 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA11,Device IN Endpoint 11 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xA78++0x7
line.long 0x0 "DTXFSTS11,Device IN Endpoint Transmit FIFO Status Register 11"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB11,Device IN Endpoint 11 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xA80++0x3
line.long 0x0 "DIEPCTL12,Device Control IN Endpoint 12 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xA88++0x3
line.long 0x0 "DIEPINT12,Device IN Endpoint 12 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xA90++0x7
line.long 0x0 "DIEPTSIZ12,Device IN Endpoint 12 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA12,Device IN Endpoint 12 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xA98++0x7
line.long 0x0 "DTXFSTS12,Device IN Endpoint Transmit FIFO Status Register 12"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB12,Device IN Endpoint 12 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xAA0++0x3
line.long 0x0 "DIEPCTL13,Device Control IN Endpoint 13 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xAA8++0x3
line.long 0x0 "DIEPINT13,Device IN Endpoint 13 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xAB0++0x7
line.long 0x0 "DIEPTSIZ13,Device IN Endpoint 13 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA13,Device IN Endpoint 13 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xAB8++0x7
line.long 0x0 "DTXFSTS13,Device IN Endpoint Transmit FIFO Status Register 13"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB13,Device IN Endpoint 13 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xAC0++0x3
line.long 0x0 "DIEPCTL14,Device Control IN Endpoint 14 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xAC8++0x3
line.long 0x0 "DIEPINT14,Device IN Endpoint 14 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xAD0++0x7
line.long 0x0 "DIEPTSIZ14,Device IN Endpoint 14 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA14,Device IN Endpoint 14 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xAD8++0x7
line.long 0x0 "DTXFSTS14,Device IN Endpoint Transmit FIFO Status Register 14"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB14,Device IN Endpoint 14 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xAE0++0x3
line.long 0x0 "DIEPCTL15,Device Control IN Endpoint 15 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xAE8++0x3
line.long 0x0 "DIEPINT15,Device IN Endpoint 15 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xAF0++0x7
line.long 0x0 "DIEPTSIZ15,Device IN Endpoint 15 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA15,Device IN Endpoint 15 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xAF8++0x7
line.long 0x0 "DTXFSTS15,Device IN Endpoint Transmit FIFO Status Register 15"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB15,Device IN Endpoint 15 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xB00++0x3
line.long 0x0 "DOEPCTL0,Device Control OUT Endpoint 0 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
rbitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
rbitfld.long 0x0 28.--29. "RESERVED,RESERVED" "0,1,2,3"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "RESERVED1,RESERVED"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
rbitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0,1,2,3"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes based,1: The core is transmitting NAK handshakes on this"
newline
rbitfld.long 0x0 16. "RESERVED2,RESERVED" "0,1"
newline
rbitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 2.--14. 1. "RESERVED3,RESERVED"
newline
rbitfld.long 0x0 0.--1. "MPS,Maximum Packet Size (MPS)" "0: 64 bytes,1: 32 bytes,2: 16 bytes,3: 8 bytes"
group.long 0xB08++0x3
line.long 0x0 "DOEPINT0,Device OUT Endpoint 0 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB10++0x7
line.long 0x0 "DOEPTSIZ0,Device OUT Endpoint 0 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "SUPCnt,SETUP Packet Count (SUPCnt)" "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 20.--28. 1. "RESERVED1,RESERVED"
newline
bitfld.long 0x0 19. "PktCnt,Packet Count (PktCnt)" "0,1"
newline
hexmask.long.word 0x0 7.--18. 1. "RESERVED2,RESERVED"
newline
hexmask.long.byte 0x0 0.--6. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA0,Device OUT Endpoint 0 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xB1C++0x3
line.long 0x0 "DOEPDMAB0,Device OUT Endpoint 16 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xB20++0x3
line.long 0x0 "DOEPCTL1,Device Control OUT Endpoint 1 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xB28++0x3
line.long 0x0 "DOEPINT1,Device OUT Endpoint 1 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB30++0x7
line.long 0x0 "DOEPTSIZ1,Device OUT Endpoint 1 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA1,Device OUT Endpoint 1 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xB3C++0x3
line.long 0x0 "DOEPDMAB1,Device OUT Endpoint 1 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xB40++0x3
line.long 0x0 "DOEPCTL2,Device Control OUT Endpoint 2 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xB48++0x3
line.long 0x0 "DOEPINT2,Device OUT Endpoint 2 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB50++0x7
line.long 0x0 "DOEPTSIZ2,Device OUT Endpoint 2 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA2,Device OUT Endpoint 2 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xB5C++0x3
line.long 0x0 "DOEPDMAB2,Device OUT Endpoint 2 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xB60++0x3
line.long 0x0 "DOEPCTL3,Device Control OUT Endpoint 3 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xB68++0x3
line.long 0x0 "DOEPINT3,Device OUT Endpoint 3 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB70++0x7
line.long 0x0 "DOEPTSIZ3,Device OUT Endpoint 3 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA3,Device OUT Endpoint 3 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xB7C++0x3
line.long 0x0 "DOEPDMAB3,Device OUT Endpoint 3 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xB80++0x3
line.long 0x0 "DOEPCTL4,Device Control OUT Endpoint 4 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xB88++0x3
line.long 0x0 "DOEPINT4,Device OUT Endpoint 4 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB90++0x7
line.long 0x0 "DOEPTSIZ4,Device OUT Endpoint 4 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA4,Device OUT Endpoint 4 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xB9C++0x3
line.long 0x0 "DOEPDMAB4,Device OUT Endpoint 4 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xBA0++0x3
line.long 0x0 "DOEPCTL5,Device Control OUT Endpoint 5 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xBA8++0x3
line.long 0x0 "DOEPINT5,Device OUT Endpoint 5 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xBB0++0x7
line.long 0x0 "DOEPTSIZ5,Device OUT Endpoint 5 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA5,Device OUT Endpoint 5 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xBBC++0x3
line.long 0x0 "DOEPDMAB5,Device OUT Endpoint 5 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xBC0++0x3
line.long 0x0 "DOEPCTL6,Device Control OUT Endpoint 6 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xBC8++0x3
line.long 0x0 "DOEPINT6,Device OUT Endpoint 6 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xBD0++0x7
line.long 0x0 "DOEPTSIZ6,Device OUT Endpoint 6 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA6,Device OUT Endpoint 6 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xBDC++0x3
line.long 0x0 "DOEPDMAB6,Device OUT Endpoint 6 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xBE0++0x3
line.long 0x0 "DOEPCTL7,Device Control OUT Endpoint 7 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xBE8++0x3
line.long 0x0 "DOEPINT7,Device OUT Endpoint 7 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xBF0++0x7
line.long 0x0 "DOEPTSIZ7,Device OUT Endpoint 7 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA7,Device OUT Endpoint 7 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xBFC++0x3
line.long 0x0 "DOEPDMAB7,Device OUT Endpoint 7 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xC00++0x3
line.long 0x0 "DOEPCTL8,Device Control OUT Endpoint 8 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xC08++0x3
line.long 0x0 "DOEPINT8,Device OUT Endpoint 8 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xC10++0x7
line.long 0x0 "DOEPTSIZ8,Device OUT Endpoint 8 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA8,Device OUT Endpoint 8 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xC1C++0x3
line.long 0x0 "DOEPDMAB8,Device OUT Endpoint 8 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xC20++0x3
line.long 0x0 "DOEPCTL9,Device Control OUT Endpoint 9 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xC28++0x3
line.long 0x0 "DOEPINT9,Device OUT Endpoint 9 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xC30++0x7
line.long 0x0 "DOEPTSIZ9,Device OUT Endpoint 9 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA9,Device OUT Endpoint 9 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xC3C++0x3
line.long 0x0 "DOEPDMAB9,Device OUT Endpoint 9 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xC40++0x3
line.long 0x0 "DOEPCTL10,Device Control OUT Endpoint 10 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xC48++0x3
line.long 0x0 "DOEPINT10,Device OUT Endpoint 10 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xC50++0x7
line.long 0x0 "DOEPTSIZ10,Device OUT Endpoint 10 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA10,Device OUT Endpoint 10 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xC5C++0x3
line.long 0x0 "DOEPDMAB10,Device OUT Endpoint 10 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xC60++0x3
line.long 0x0 "DOEPCTL11,Device Control OUT Endpoint 11 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xC68++0x3
line.long 0x0 "DOEPINT11,Device OUT Endpoint 11 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xC70++0x7
line.long 0x0 "DOEPTSIZ11,Device OUT Endpoint 11 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA11,Device OUT Endpoint 11 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xC7C++0x3
line.long 0x0 "DOEPDMAB11,Device OUT Endpoint 11 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xC80++0x3
line.long 0x0 "DOEPCTL12,Device Control OUT Endpoint 12 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xC88++0x3
line.long 0x0 "DOEPINT12,Device OUT Endpoint 12 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xC90++0x7
line.long 0x0 "DOEPTSIZ12,Device OUT Endpoint 12 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA12,Device OUT Endpoint 12 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xC9C++0x3
line.long 0x0 "DOEPDMAB12,Device OUT Endpoint 12 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xCA0++0x3
line.long 0x0 "DOEPCTL13,Device Control OUT Endpoint 13 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xCA8++0x3
line.long 0x0 "DOEPINT13,Device OUT Endpoint 13 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xCB0++0x7
line.long 0x0 "DOEPTSIZ13,Device OUT Endpoint 13 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA13,Device OUT Endpoint 13 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xCBC++0x3
line.long 0x0 "DOEPDMAB13,Device OUT Endpoint 13 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xCC0++0x3
line.long 0x0 "DOEPCTL14,Device Control OUT Endpoint 14 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xCC8++0x3
line.long 0x0 "DOEPINT14,Device OUT Endpoint 14 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xCD0++0x7
line.long 0x0 "DOEPTSIZ14,Device OUT Endpoint 14 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA14,Device OUT Endpoint 14 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xCDC++0x3
line.long 0x0 "DOEPDMAB14,Device OUT Endpoint 14 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xCE0++0x3
line.long 0x0 "DOEPCTL15,Device Control OUT Endpoint 15 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xCE8++0x3
line.long 0x0 "DOEPINT15,Device OUT Endpoint 15 Interrupt Register"
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xCF0++0x7
line.long 0x0 "DOEPTSIZ15,Device OUT Endpoint 15 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA15,Device OUT Endpoint 15 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xCFC++0x3
line.long 0x0 "DOEPDMAB15,Device OUT Endpoint 15 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xE00++0x3
line.long 0x0 "PCGCCTL,Power and Clock Gating Control Register"
rbitfld.long 0x0 7. "L1Suspended,L1 Deep Sleep" "0,1"
newline
rbitfld.long 0x0 6. "PhySleep,PHY In Sleep" "0,1"
newline
bitfld.long 0x0 3. "RstPdwnModule,Reset Power-Down Modules (RstPdwnModule)" "0,1"
newline
bitfld.long 0x0 0. "StopPclk,Stop Pclk (StopPclk)" "0,1"
tree.end
tree.end
AUTOINDENT.OFF